Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/iommu/tegra-smmu.c

  1 /*
  2  * IOMMU API for SMMU in Tegra30
  3  *
  4  * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify it
  7  * under the terms and conditions of the GNU General Public License,
  8  * version 2, as published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  * more details.
 14  *
 15  * You should have received a copy of the GNU General Public License along with
 16  * this program; if not, write to the Free Software Foundation, Inc.,
 17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 18  */
 19 
 20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
 21 
 22 #include <linux/err.h>
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/spinlock.h>
 26 #include <linux/slab.h>
 27 #include <linux/vmalloc.h>
 28 #include <linux/mm.h>
 29 #include <linux/pagemap.h>
 30 #include <linux/device.h>
 31 #include <linux/sched.h>
 32 #include <linux/iommu.h>
 33 #include <linux/io.h>
 34 #include <linux/of.h>
 35 #include <linux/of_iommu.h>
 36 #include <linux/debugfs.h>
 37 #include <linux/seq_file.h>
 38 #include <linux/tegra-ahb.h>
 39 
 40 #include <asm/page.h>
 41 #include <asm/cacheflush.h>
 42 
 43 enum smmu_hwgrp {
 44         HWGRP_AFI,
 45         HWGRP_AVPC,
 46         HWGRP_DC,
 47         HWGRP_DCB,
 48         HWGRP_EPP,
 49         HWGRP_G2,
 50         HWGRP_HC,
 51         HWGRP_HDA,
 52         HWGRP_ISP,
 53         HWGRP_MPE,
 54         HWGRP_NV,
 55         HWGRP_NV2,
 56         HWGRP_PPCS,
 57         HWGRP_SATA,
 58         HWGRP_VDE,
 59         HWGRP_VI,
 60 
 61         HWGRP_COUNT,
 62 
 63         HWGRP_END = ~0,
 64 };
 65 
 66 #define HWG_AFI         (1 << HWGRP_AFI)
 67 #define HWG_AVPC        (1 << HWGRP_AVPC)
 68 #define HWG_DC          (1 << HWGRP_DC)
 69 #define HWG_DCB         (1 << HWGRP_DCB)
 70 #define HWG_EPP         (1 << HWGRP_EPP)
 71 #define HWG_G2          (1 << HWGRP_G2)
 72 #define HWG_HC          (1 << HWGRP_HC)
 73 #define HWG_HDA         (1 << HWGRP_HDA)
 74 #define HWG_ISP         (1 << HWGRP_ISP)
 75 #define HWG_MPE         (1 << HWGRP_MPE)
 76 #define HWG_NV          (1 << HWGRP_NV)
 77 #define HWG_NV2         (1 << HWGRP_NV2)
 78 #define HWG_PPCS        (1 << HWGRP_PPCS)
 79 #define HWG_SATA        (1 << HWGRP_SATA)
 80 #define HWG_VDE         (1 << HWGRP_VDE)
 81 #define HWG_VI          (1 << HWGRP_VI)
 82 
 83 /* bitmap of the page sizes currently supported */
 84 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
 85 
 86 #define SMMU_CONFIG                             0x10
 87 #define SMMU_CONFIG_DISABLE                     0
 88 #define SMMU_CONFIG_ENABLE                      1
 89 
 90 /* REVISIT: To support multiple MCs */
 91 enum {
 92         _MC = 0,
 93 };
 94 
 95 enum {
 96         _TLB = 0,
 97         _PTC,
 98 };
 99 
100 #define SMMU_CACHE_CONFIG_BASE                  0x14
101 #define __SMMU_CACHE_CONFIG(mc, cache)          (SMMU_CACHE_CONFIG_BASE + 4 * cache)
102 #define SMMU_CACHE_CONFIG(cache)                __SMMU_CACHE_CONFIG(_MC, cache)
103 
104 #define SMMU_CACHE_CONFIG_STATS_SHIFT           31
105 #define SMMU_CACHE_CONFIG_STATS_ENABLE          (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
106 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT      30
107 #define SMMU_CACHE_CONFIG_STATS_TEST            (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
108 
109 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
110 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
111 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
112 
113 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
114 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
115 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
116 
117 #define SMMU_PTB_ASID                           0x1c
118 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
119 
120 #define SMMU_PTB_DATA                           0x20
121 #define SMMU_PTB_DATA_RESET_VAL                 0
122 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
123 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
124 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
125 
126 #define SMMU_TLB_FLUSH                          0x30
127 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
128 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
129 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
130 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
131 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
132 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
133 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
134 
135 #define SMMU_PTC_FLUSH                          0x34
136 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
137 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
138 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
139 
140 #define SMMU_ASID_SECURITY                      0x38
141 
142 #define SMMU_STATS_CACHE_COUNT_BASE             0x1f0
143 
144 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss)              \
145         (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
146 
147 #define SMMU_TRANSLATION_ENABLE_0               0x228
148 #define SMMU_TRANSLATION_ENABLE_1               0x22c
149 #define SMMU_TRANSLATION_ENABLE_2               0x230
150 
151 #define SMMU_AFI_ASID   0x238   /* PCIE */
152 #define SMMU_AVPC_ASID  0x23c   /* AVP */
153 #define SMMU_DC_ASID    0x240   /* Display controller */
154 #define SMMU_DCB_ASID   0x244   /* Display controller B */
155 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
156 #define SMMU_G2_ASID    0x24c   /* 2D engine */
157 #define SMMU_HC_ASID    0x250   /* Host1x */
158 #define SMMU_HDA_ASID   0x254   /* High-def audio */
159 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
160 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
161 #define SMMU_NV_ASID    0x268   /* (3D) */
162 #define SMMU_NV2_ASID   0x26c   /* (3D) */
163 #define SMMU_PPCS_ASID  0x270   /* AHB */
164 #define SMMU_SATA_ASID  0x278   /* SATA */
165 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
166 #define SMMU_VI_ASID    0x280   /* Video input */
167 
168 #define SMMU_PDE_NEXT_SHIFT             28
169 
170 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
171 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
172 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
173 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
174 #define SMMU_TLB_FLUSH_VA(iova, which)  \
175         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
176                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
177         SMMU_TLB_FLUSH_VA_MATCH_##which)
178 #define SMMU_PTB_ASID_CUR(n)    \
179                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
180 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
181                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
182                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
183 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
184                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
185                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
186 
187 #define SMMU_PAGE_SHIFT 12
188 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
189 #define SMMU_PAGE_MASK  ((1 << SMMU_PAGE_SHIFT) - 1)
190 
191 #define SMMU_PDIR_COUNT 1024
192 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
193 #define SMMU_PTBL_COUNT 1024
194 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
195 #define SMMU_PDIR_SHIFT 12
196 #define SMMU_PDE_SHIFT  12
197 #define SMMU_PTE_SHIFT  12
198 #define SMMU_PFN_MASK   0x000fffff
199 
200 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
201 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
202 #define SMMU_PDN_TO_ADDR(pdn)   ((pdn) << 22)
203 
204 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
205 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
206 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
207 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
208 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
209 
210 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
211 
212 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
213 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
214 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
215 
216 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
217 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
218 
219 #define SMMU_MK_PDIR(page, attr)        \
220                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
221 #define SMMU_MK_PDE(page, attr)         \
222                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
223 #define SMMU_EX_PTBL_PAGE(pde)          \
224                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
225 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
226 
227 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
228 #define SMMU_ASID_DISABLE       0
229 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
230 
231 #define NUM_SMMU_REG_BANKS      3
232 
233 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
234 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
235 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
236 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
237 
238 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
239 
240 static const u32 smmu_hwgrp_asid_reg[] = {
241         HWGRP_INIT(AFI),
242         HWGRP_INIT(AVPC),
243         HWGRP_INIT(DC),
244         HWGRP_INIT(DCB),
245         HWGRP_INIT(EPP),
246         HWGRP_INIT(G2),
247         HWGRP_INIT(HC),
248         HWGRP_INIT(HDA),
249         HWGRP_INIT(ISP),
250         HWGRP_INIT(MPE),
251         HWGRP_INIT(NV),
252         HWGRP_INIT(NV2),
253         HWGRP_INIT(PPCS),
254         HWGRP_INIT(SATA),
255         HWGRP_INIT(VDE),
256         HWGRP_INIT(VI),
257 };
258 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
259 
260 /*
261  * Per client for address space
262  */
263 struct smmu_client {
264         struct device           *dev;
265         struct list_head        list;
266         struct smmu_as          *as;
267         u32                     hwgrp;
268 };
269 
270 /*
271  * Per address space
272  */
273 struct smmu_as {
274         struct smmu_device      *smmu;  /* back pointer to container */
275         unsigned int            asid;
276         spinlock_t              lock;   /* for pagetable */
277         struct page             *pdir_page;
278         unsigned long           pdir_attr;
279         unsigned long           pde_attr;
280         unsigned long           pte_attr;
281         unsigned int            *pte_count;
282 
283         struct list_head        client;
284         spinlock_t              client_lock; /* for client list */
285 };
286 
287 struct smmu_debugfs_info {
288         struct smmu_device *smmu;
289         int mc;
290         int cache;
291 };
292 
293 /*
294  * Per SMMU device - IOMMU device
295  */
296 struct smmu_device {
297         void __iomem    *regbase;       /* register offset base */
298         void __iomem    **regs;         /* register block start address array */
299         void __iomem    **rege;         /* register block end address array */
300         int             nregs;          /* number of register blocks */
301 
302         unsigned long   iovmm_base;     /* remappable base address */
303         unsigned long   page_count;     /* total remappable size */
304         spinlock_t      lock;
305         char            *name;
306         struct device   *dev;
307         struct page *avp_vector_page;   /* dummy page shared by all AS's */
308 
309         /*
310          * Register image savers for suspend/resume
311          */
312         unsigned long translation_enable_0;
313         unsigned long translation_enable_1;
314         unsigned long translation_enable_2;
315         unsigned long asid_security;
316 
317         struct dentry *debugfs_root;
318         struct smmu_debugfs_info *debugfs_info;
319 
320         struct device_node *ahb;
321 
322         int             num_as;
323         struct smmu_as  as[0];          /* Run-time allocated array */
324 };
325 
326 static struct smmu_device *smmu_handle; /* unique for a system */
327 
328 /*
329  *      SMMU register accessors
330  */
331 static bool inline smmu_valid_reg(struct smmu_device *smmu,
332                                   void __iomem *addr)
333 {
334         int i;
335 
336         for (i = 0; i < smmu->nregs; i++) {
337                 if (addr < smmu->regs[i])
338                         break;
339                 if (addr <= smmu->rege[i])
340                         return true;
341         }
342 
343         return false;
344 }
345 
346 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
347 {
348         void __iomem *addr = smmu->regbase + offs;
349 
350         BUG_ON(!smmu_valid_reg(smmu, addr));
351 
352         return readl(addr);
353 }
354 
355 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
356 {
357         void __iomem *addr = smmu->regbase + offs;
358 
359         BUG_ON(!smmu_valid_reg(smmu, addr));
360 
361         writel(val, addr);
362 }
363 
364 #define VA_PAGE_TO_PA(va, page) \
365         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
366 
367 #define FLUSH_CPU_DCACHE(va, page, size)        \
368         do {    \
369                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
370                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
371                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
372         } while (0)
373 
374 /*
375  * Any interaction between any block on PPSB and a block on APB or AHB
376  * must have these read-back barriers to ensure the APB/AHB bus
377  * transaction is complete before initiating activity on the PPSB
378  * block.
379  */
380 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
381 
382 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
383 
384 static int __smmu_client_set_hwgrp(struct smmu_client *c,
385                                    unsigned long map, int on)
386 {
387         int i;
388         struct smmu_as *as = c->as;
389         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
390         struct smmu_device *smmu = as->smmu;
391 
392         WARN_ON(!on && map);
393         if (on && !map)
394                 return -EINVAL;
395         if (!on)
396                 map = smmu_client_hwgrp(c);
397 
398         for_each_set_bit(i, &map, HWGRP_COUNT) {
399                 offs = HWGRP_ASID_REG(i);
400                 val = smmu_read(smmu, offs);
401                 if (on) {
402                         if (WARN_ON(val & mask))
403                                 goto err_hw_busy;
404                         val |= mask;
405                 } else {
406                         WARN_ON((val & mask) == mask);
407                         val &= ~mask;
408                 }
409                 smmu_write(smmu, val, offs);
410         }
411         FLUSH_SMMU_REGS(smmu);
412         c->hwgrp = map;
413         return 0;
414 
415 err_hw_busy:
416         for_each_set_bit(i, &map, HWGRP_COUNT) {
417                 offs = HWGRP_ASID_REG(i);
418                 val = smmu_read(smmu, offs);
419                 val &= ~mask;
420                 smmu_write(smmu, val, offs);
421         }
422         return -EBUSY;
423 }
424 
425 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
426 {
427         u32 val;
428         unsigned long flags;
429         struct smmu_as *as = c->as;
430         struct smmu_device *smmu = as->smmu;
431 
432         spin_lock_irqsave(&smmu->lock, flags);
433         val = __smmu_client_set_hwgrp(c, map, on);
434         spin_unlock_irqrestore(&smmu->lock, flags);
435         return val;
436 }
437 
438 /*
439  * Flush all TLB entries and all PTC entries
440  * Caller must lock smmu
441  */
442 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
443 {
444         u32 val;
445 
446         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
447         FLUSH_SMMU_REGS(smmu);
448         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
449                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
450         smmu_write(smmu, val, SMMU_TLB_FLUSH);
451 
452         if (enable)
453                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
454         FLUSH_SMMU_REGS(smmu);
455 }
456 
457 static int smmu_setup_regs(struct smmu_device *smmu)
458 {
459         int i;
460         u32 val;
461 
462         for (i = 0; i < smmu->num_as; i++) {
463                 struct smmu_as *as = &smmu->as[i];
464                 struct smmu_client *c;
465 
466                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
467                 val = as->pdir_page ?
468                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
469                         SMMU_PTB_DATA_RESET_VAL;
470                 smmu_write(smmu, val, SMMU_PTB_DATA);
471 
472                 list_for_each_entry(c, &as->client, list)
473                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
474         }
475 
476         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
477         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
478         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
479         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
480         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
481         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
482 
483         smmu_flush_regs(smmu, 1);
484 
485         return tegra_ahb_enable_smmu(smmu->ahb);
486 }
487 
488 static void flush_ptc_and_tlb(struct smmu_device *smmu,
489                       struct smmu_as *as, dma_addr_t iova,
490                       unsigned long *pte, struct page *page, int is_pde)
491 {
492         u32 val;
493         unsigned long tlb_flush_va = is_pde
494                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
495                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
496 
497         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
498         smmu_write(smmu, val, SMMU_PTC_FLUSH);
499         FLUSH_SMMU_REGS(smmu);
500         val = tlb_flush_va |
501                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
502                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
503         smmu_write(smmu, val, SMMU_TLB_FLUSH);
504         FLUSH_SMMU_REGS(smmu);
505 }
506 
507 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
508 {
509         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
510         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
511 
512         if (pdir[pdn] != _PDE_VACANT(pdn)) {
513                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
514 
515                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
516                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
517                 pdir[pdn] = _PDE_VACANT(pdn);
518                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
519                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
520                                   as->pdir_page, 1);
521         }
522 }
523 
524 static void free_pdir(struct smmu_as *as)
525 {
526         unsigned addr;
527         int count;
528         struct device *dev = as->smmu->dev;
529 
530         if (!as->pdir_page)
531                 return;
532 
533         addr = as->smmu->iovmm_base;
534         count = as->smmu->page_count;
535         while (count-- > 0) {
536                 free_ptbl(as, addr);
537                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
538         }
539         ClearPageReserved(as->pdir_page);
540         __free_page(as->pdir_page);
541         as->pdir_page = NULL;
542         devm_kfree(dev, as->pte_count);
543         as->pte_count = NULL;
544 }
545 
546 /*
547  * Maps PTBL for given iova and returns the PTE address
548  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
549  */
550 static unsigned long *locate_pte(struct smmu_as *as,
551                                  dma_addr_t iova, bool allocate,
552                                  struct page **ptbl_page_p,
553                                  unsigned int **count)
554 {
555         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
556         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
557         unsigned long *pdir = page_address(as->pdir_page);
558         unsigned long *ptbl;
559 
560         if (pdir[pdn] != _PDE_VACANT(pdn)) {
561                 /* Mapped entry table already exists */
562                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
563                 ptbl = page_address(*ptbl_page_p);
564         } else if (!allocate) {
565                 return NULL;
566         } else {
567                 int pn;
568                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
569 
570                 /* Vacant - allocate a new page table */
571                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
572 
573                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
574                 if (!*ptbl_page_p) {
575                         dev_err(as->smmu->dev,
576                                 "failed to allocate smmu_device page table\n");
577                         return NULL;
578                 }
579                 SetPageReserved(*ptbl_page_p);
580                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
581                 for (pn = 0; pn < SMMU_PTBL_COUNT;
582                      pn++, addr += SMMU_PAGE_SIZE) {
583                         ptbl[pn] = _PTE_VACANT(addr);
584                 }
585                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
586                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
587                                         as->pde_attr | _PDE_NEXT);
588                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
589                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
590                                   as->pdir_page, 1);
591         }
592         *count = &as->pte_count[pdn];
593 
594         return &ptbl[ptn % SMMU_PTBL_COUNT];
595 }
596 
597 #ifdef CONFIG_SMMU_SIG_DEBUG
598 static void put_signature(struct smmu_as *as,
599                           dma_addr_t iova, unsigned long pfn)
600 {
601         struct page *page;
602         unsigned long *vaddr;
603 
604         page = pfn_to_page(pfn);
605         vaddr = page_address(page);
606         if (!vaddr)
607                 return;
608 
609         vaddr[0] = iova;
610         vaddr[1] = pfn << PAGE_SHIFT;
611         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
612 }
613 #else
614 static inline void put_signature(struct smmu_as *as,
615                                  unsigned long addr, unsigned long pfn)
616 {
617 }
618 #endif
619 
620 /*
621  * Caller must not hold as->lock
622  */
623 static int alloc_pdir(struct smmu_as *as)
624 {
625         unsigned long *pdir, flags;
626         int pdn, err = 0;
627         u32 val;
628         struct smmu_device *smmu = as->smmu;
629         struct page *page;
630         unsigned int *cnt;
631 
632         /*
633          * do the allocation, then grab as->lock
634          */
635         cnt = devm_kzalloc(smmu->dev,
636                            sizeof(cnt[0]) * SMMU_PDIR_COUNT,
637                            GFP_KERNEL);
638         page = alloc_page(GFP_KERNEL | __GFP_DMA);
639 
640         spin_lock_irqsave(&as->lock, flags);
641 
642         if (as->pdir_page) {
643                 /* We raced, free the redundant */
644                 err = -EAGAIN;
645                 goto err_out;
646         }
647 
648         if (!page || !cnt) {
649                 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
650                 err = -ENOMEM;
651                 goto err_out;
652         }
653 
654         as->pdir_page = page;
655         as->pte_count = cnt;
656 
657         SetPageReserved(as->pdir_page);
658         pdir = page_address(as->pdir_page);
659 
660         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
661                 pdir[pdn] = _PDE_VACANT(pdn);
662         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
663         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
664         smmu_write(smmu, val, SMMU_PTC_FLUSH);
665         FLUSH_SMMU_REGS(as->smmu);
666         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
667                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
668                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
669         smmu_write(smmu, val, SMMU_TLB_FLUSH);
670         FLUSH_SMMU_REGS(as->smmu);
671 
672         spin_unlock_irqrestore(&as->lock, flags);
673 
674         return 0;
675 
676 err_out:
677         spin_unlock_irqrestore(&as->lock, flags);
678 
679         devm_kfree(smmu->dev, cnt);
680         if (page)
681                 __free_page(page);
682         return err;
683 }
684 
685 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
686 {
687         unsigned long *pte;
688         struct page *page;
689         unsigned int *count;
690 
691         pte = locate_pte(as, iova, false, &page, &count);
692         if (WARN_ON(!pte))
693                 return;
694 
695         if (WARN_ON(*pte == _PTE_VACANT(iova)))
696                 return;
697 
698         *pte = _PTE_VACANT(iova);
699         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
700         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
701         if (!--(*count))
702                 free_ptbl(as, iova);
703 }
704 
705 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
706                                  unsigned long pfn)
707 {
708         struct smmu_device *smmu = as->smmu;
709         unsigned long *pte;
710         unsigned int *count;
711         struct page *page;
712 
713         pte = locate_pte(as, iova, true, &page, &count);
714         if (WARN_ON(!pte))
715                 return;
716 
717         if (*pte == _PTE_VACANT(iova))
718                 (*count)++;
719         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
720         if (unlikely((*pte == _PTE_VACANT(iova))))
721                 (*count)--;
722         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
723         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
724         put_signature(as, iova, pfn);
725 }
726 
727 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
728                           phys_addr_t pa, size_t bytes, int prot)
729 {
730         struct smmu_as *as = domain->priv;
731         unsigned long pfn = __phys_to_pfn(pa);
732         unsigned long flags;
733 
734         dev_dbg(as->smmu->dev, "[%d] %08lx:%pa\n", as->asid, iova, &pa);
735 
736         if (!pfn_valid(pfn))
737                 return -ENOMEM;
738 
739         spin_lock_irqsave(&as->lock, flags);
740         __smmu_iommu_map_pfn(as, iova, pfn);
741         spin_unlock_irqrestore(&as->lock, flags);
742         return 0;
743 }
744 
745 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
746                                size_t bytes)
747 {
748         struct smmu_as *as = domain->priv;
749         unsigned long flags;
750 
751         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
752 
753         spin_lock_irqsave(&as->lock, flags);
754         __smmu_iommu_unmap(as, iova);
755         spin_unlock_irqrestore(&as->lock, flags);
756         return SMMU_PAGE_SIZE;
757 }
758 
759 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
760                                            dma_addr_t iova)
761 {
762         struct smmu_as *as = domain->priv;
763         unsigned long *pte;
764         unsigned int *count;
765         struct page *page;
766         unsigned long pfn;
767         unsigned long flags;
768 
769         spin_lock_irqsave(&as->lock, flags);
770 
771         pte = locate_pte(as, iova, true, &page, &count);
772         pfn = *pte & SMMU_PFN_MASK;
773         WARN_ON(!pfn_valid(pfn));
774         dev_dbg(as->smmu->dev,
775                 "iova:%08llx pfn:%08lx asid:%d\n", (unsigned long long)iova,
776                  pfn, as->asid);
777 
778         spin_unlock_irqrestore(&as->lock, flags);
779         return PFN_PHYS(pfn);
780 }
781 
782 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
783                                      unsigned long cap)
784 {
785         return 0;
786 }
787 
788 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
789                                  struct device *dev)
790 {
791         struct smmu_as *as = domain->priv;
792         struct smmu_device *smmu = as->smmu;
793         struct smmu_client *client, *c;
794         u32 map;
795         int err;
796 
797         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
798         if (!client)
799                 return -ENOMEM;
800         client->dev = dev;
801         client->as = as;
802         map = (unsigned long)dev->platform_data;
803         if (!map)
804                 return -EINVAL;
805 
806         err = smmu_client_enable_hwgrp(client, map);
807         if (err)
808                 goto err_hwgrp;
809 
810         spin_lock(&as->client_lock);
811         list_for_each_entry(c, &as->client, list) {
812                 if (c->dev == dev) {
813                         dev_err(smmu->dev,
814                                 "%s is already attached\n", dev_name(c->dev));
815                         err = -EINVAL;
816                         goto err_client;
817                 }
818         }
819         list_add(&client->list, &as->client);
820         spin_unlock(&as->client_lock);
821 
822         /*
823          * Reserve "page zero" for AVP vectors using a common dummy
824          * page.
825          */
826         if (map & HWG_AVPC) {
827                 struct page *page;
828 
829                 page = as->smmu->avp_vector_page;
830                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
831 
832                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
833         }
834 
835         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
836         return 0;
837 
838 err_client:
839         smmu_client_disable_hwgrp(client);
840         spin_unlock(&as->client_lock);
841 err_hwgrp:
842         devm_kfree(smmu->dev, client);
843         return err;
844 }
845 
846 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
847                                   struct device *dev)
848 {
849         struct smmu_as *as = domain->priv;
850         struct smmu_device *smmu = as->smmu;
851         struct smmu_client *c;
852 
853         spin_lock(&as->client_lock);
854 
855         list_for_each_entry(c, &as->client, list) {
856                 if (c->dev == dev) {
857                         smmu_client_disable_hwgrp(c);
858                         list_del(&c->list);
859                         devm_kfree(smmu->dev, c);
860                         c->as = NULL;
861                         dev_dbg(smmu->dev,
862                                 "%s is detached\n", dev_name(c->dev));
863                         goto out;
864                 }
865         }
866         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev));
867 out:
868         spin_unlock(&as->client_lock);
869 }
870 
871 static int smmu_iommu_domain_init(struct iommu_domain *domain)
872 {
873         int i, err = -EAGAIN;
874         unsigned long flags;
875         struct smmu_as *as;
876         struct smmu_device *smmu = smmu_handle;
877 
878         /* Look for a free AS with lock held */
879         for  (i = 0; i < smmu->num_as; i++) {
880                 as = &smmu->as[i];
881 
882                 if (as->pdir_page)
883                         continue;
884 
885                 err = alloc_pdir(as);
886                 if (!err)
887                         goto found;
888 
889                 if (err != -EAGAIN)
890                         break;
891         }
892         if (i == smmu->num_as)
893                 dev_err(smmu->dev,  "no free AS\n");
894         return err;
895 
896 found:
897         spin_lock_irqsave(&smmu->lock, flags);
898 
899         /* Update PDIR register */
900         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
901         smmu_write(smmu,
902                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
903         FLUSH_SMMU_REGS(smmu);
904 
905         spin_unlock_irqrestore(&smmu->lock, flags);
906 
907         domain->priv = as;
908 
909         domain->geometry.aperture_start = smmu->iovmm_base;
910         domain->geometry.aperture_end   = smmu->iovmm_base +
911                 smmu->page_count * SMMU_PAGE_SIZE - 1;
912         domain->geometry.force_aperture = true;
913 
914         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
915 
916         return 0;
917 }
918 
919 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
920 {
921         struct smmu_as *as = domain->priv;
922         struct smmu_device *smmu = as->smmu;
923         unsigned long flags;
924 
925         spin_lock_irqsave(&as->lock, flags);
926 
927         if (as->pdir_page) {
928                 spin_lock(&smmu->lock);
929                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
930                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
931                 FLUSH_SMMU_REGS(smmu);
932                 spin_unlock(&smmu->lock);
933 
934                 free_pdir(as);
935         }
936 
937         if (!list_empty(&as->client)) {
938                 struct smmu_client *c;
939 
940                 list_for_each_entry(c, &as->client, list)
941                         smmu_iommu_detach_dev(domain, c->dev);
942         }
943 
944         spin_unlock_irqrestore(&as->lock, flags);
945 
946         domain->priv = NULL;
947         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
948 }
949 
950 static struct iommu_ops smmu_iommu_ops = {
951         .domain_init    = smmu_iommu_domain_init,
952         .domain_destroy = smmu_iommu_domain_destroy,
953         .attach_dev     = smmu_iommu_attach_dev,
954         .detach_dev     = smmu_iommu_detach_dev,
955         .map            = smmu_iommu_map,
956         .unmap          = smmu_iommu_unmap,
957         .iova_to_phys   = smmu_iommu_iova_to_phys,
958         .domain_has_cap = smmu_iommu_domain_has_cap,
959         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
960 };
961 
962 /* Should be in the order of enum */
963 static const char * const smmu_debugfs_mc[] = { "mc", };
964 static const char * const smmu_debugfs_cache[] = {  "tlb", "ptc", };
965 
966 static ssize_t smmu_debugfs_stats_write(struct file *file,
967                                         const char __user *buffer,
968                                         size_t count, loff_t *pos)
969 {
970         struct smmu_debugfs_info *info;
971         struct smmu_device *smmu;
972         int i;
973         enum {
974                 _OFF = 0,
975                 _ON,
976                 _RESET,
977         };
978         const char * const command[] = {
979                 [_OFF]          = "off",
980                 [_ON]           = "on",
981                 [_RESET]        = "reset",
982         };
983         char str[] = "reset";
984         u32 val;
985         size_t offs;
986 
987         count = min_t(size_t, count, sizeof(str));
988         if (copy_from_user(str, buffer, count))
989                 return -EINVAL;
990 
991         for (i = 0; i < ARRAY_SIZE(command); i++)
992                 if (strncmp(str, command[i],
993                             strlen(command[i])) == 0)
994                         break;
995 
996         if (i == ARRAY_SIZE(command))
997                 return -EINVAL;
998 
999         info = file_inode(file)->i_private;
1000         smmu = info->smmu;
1001 
1002         offs = SMMU_CACHE_CONFIG(info->cache);
1003         val = smmu_read(smmu, offs);
1004         switch (i) {
1005         case _OFF:
1006                 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
1007                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1008                 smmu_write(smmu, val, offs);
1009                 break;
1010         case _ON:
1011                 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
1012                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1013                 smmu_write(smmu, val, offs);
1014                 break;
1015         case _RESET:
1016                 val |= SMMU_CACHE_CONFIG_STATS_TEST;
1017                 smmu_write(smmu, val, offs);
1018                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1019                 smmu_write(smmu, val, offs);
1020                 break;
1021         default:
1022                 BUG();
1023                 break;
1024         }
1025 
1026         dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
1027                 val, smmu_read(smmu, offs), offs);
1028 
1029         return count;
1030 }
1031 
1032 static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
1033 {
1034         struct smmu_debugfs_info *info = s->private;
1035         struct smmu_device *smmu = info->smmu;
1036         int i;
1037         const char * const stats[] = { "hit", "miss", };
1038 
1039 
1040         for (i = 0; i < ARRAY_SIZE(stats); i++) {
1041                 u32 val;
1042                 size_t offs;
1043 
1044                 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i);
1045                 val = smmu_read(smmu, offs);
1046                 seq_printf(s, "%s:%08x ", stats[i], val);
1047 
1048                 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1049                         stats[i], val, offs);
1050         }
1051         seq_printf(s, "\n");
1052         return 0;
1053 }
1054 
1055 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1056 {
1057         return single_open(file, smmu_debugfs_stats_show, inode->i_private);
1058 }
1059 
1060 static const struct file_operations smmu_debugfs_stats_fops = {
1061         .open           = smmu_debugfs_stats_open,
1062         .read           = seq_read,
1063         .llseek         = seq_lseek,
1064         .release        = single_release,
1065         .write          = smmu_debugfs_stats_write,
1066 };
1067 
1068 static void smmu_debugfs_delete(struct smmu_device *smmu)
1069 {
1070         debugfs_remove_recursive(smmu->debugfs_root);
1071         kfree(smmu->debugfs_info);
1072 }
1073 
1074 static void smmu_debugfs_create(struct smmu_device *smmu)
1075 {
1076         int i;
1077         size_t bytes;
1078         struct dentry *root;
1079 
1080         bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) *
1081                 sizeof(*smmu->debugfs_info);
1082         smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL);
1083         if (!smmu->debugfs_info)
1084                 return;
1085 
1086         root = debugfs_create_dir(dev_name(smmu->dev), NULL);
1087         if (!root)
1088                 goto err_out;
1089         smmu->debugfs_root = root;
1090 
1091         for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1092                 int j;
1093                 struct dentry *mc;
1094 
1095                 mc = debugfs_create_dir(smmu_debugfs_mc[i], root);
1096                 if (!mc)
1097                         goto err_out;
1098 
1099                 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1100                         struct dentry *cache;
1101                         struct smmu_debugfs_info *info;
1102 
1103                         info = smmu->debugfs_info;
1104                         info += i * ARRAY_SIZE(smmu_debugfs_mc) + j;
1105                         info->smmu = smmu;
1106                         info->mc = i;
1107                         info->cache = j;
1108 
1109                         cache = debugfs_create_file(smmu_debugfs_cache[j],
1110                                                     S_IWUGO | S_IRUGO, mc,
1111                                                     (void *)info,
1112                                                     &smmu_debugfs_stats_fops);
1113                         if (!cache)
1114                                 goto err_out;
1115                 }
1116         }
1117 
1118         return;
1119 
1120 err_out:
1121         smmu_debugfs_delete(smmu);
1122 }
1123 
1124 static int tegra_smmu_suspend(struct device *dev)
1125 {
1126         struct smmu_device *smmu = dev_get_drvdata(dev);
1127 
1128         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1129         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1130         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1131         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1132         return 0;
1133 }
1134 
1135 static int tegra_smmu_resume(struct device *dev)
1136 {
1137         struct smmu_device *smmu = dev_get_drvdata(dev);
1138         unsigned long flags;
1139         int err;
1140 
1141         spin_lock_irqsave(&smmu->lock, flags);
1142         err = smmu_setup_regs(smmu);
1143         spin_unlock_irqrestore(&smmu->lock, flags);
1144         return err;
1145 }
1146 
1147 static int tegra_smmu_probe(struct platform_device *pdev)
1148 {
1149         struct smmu_device *smmu;
1150         struct device *dev = &pdev->dev;
1151         int i, asids, err = 0;
1152         dma_addr_t uninitialized_var(base);
1153         size_t bytes, uninitialized_var(size);
1154 
1155         if (smmu_handle)
1156                 return -EIO;
1157 
1158         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1159 
1160         if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
1161                 return -ENODEV;
1162 
1163         bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
1164         smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
1165         if (!smmu) {
1166                 dev_err(dev, "failed to allocate smmu_device\n");
1167                 return -ENOMEM;
1168         }
1169 
1170         smmu->nregs = pdev->num_resources;
1171         smmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),
1172                                   GFP_KERNEL);
1173         smmu->rege = smmu->regs + smmu->nregs;
1174         if (!smmu->regs)
1175                 return -ENOMEM;
1176         for (i = 0; i < smmu->nregs; i++) {
1177                 struct resource *res;
1178 
1179                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1180                 smmu->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1181                 if (IS_ERR(smmu->regs[i]))
1182                         return PTR_ERR(smmu->regs[i]);
1183                 smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1;
1184         }
1185         /* Same as "mc" 1st regiter block start address */
1186         smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & PAGE_MASK);
1187 
1188         err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
1189         if (err)
1190                 return -ENODEV;
1191 
1192         if (size & SMMU_PAGE_MASK)
1193                 return -EINVAL;
1194 
1195         size >>= SMMU_PAGE_SHIFT;
1196         if (!size)
1197                 return -EINVAL;
1198 
1199         smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
1200         if (!smmu->ahb)
1201                 return -ENODEV;
1202 
1203         smmu->dev = dev;
1204         smmu->num_as = asids;
1205         smmu->iovmm_base = base;
1206         smmu->page_count = size;
1207 
1208         smmu->translation_enable_0 = ~0;
1209         smmu->translation_enable_1 = ~0;
1210         smmu->translation_enable_2 = ~0;
1211         smmu->asid_security = 0;
1212 
1213         for (i = 0; i < smmu->num_as; i++) {
1214                 struct smmu_as *as = &smmu->as[i];
1215 
1216                 as->smmu = smmu;
1217                 as->asid = i;
1218                 as->pdir_attr = _PDIR_ATTR;
1219                 as->pde_attr = _PDE_ATTR;
1220                 as->pte_attr = _PTE_ATTR;
1221 
1222                 spin_lock_init(&as->lock);
1223                 spin_lock_init(&as->client_lock);
1224                 INIT_LIST_HEAD(&as->client);
1225         }
1226         spin_lock_init(&smmu->lock);
1227         err = smmu_setup_regs(smmu);
1228         if (err)
1229                 return err;
1230         platform_set_drvdata(pdev, smmu);
1231 
1232         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1233         if (!smmu->avp_vector_page)
1234                 return -ENOMEM;
1235 
1236         smmu_debugfs_create(smmu);
1237         smmu_handle = smmu;
1238         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1239         return 0;
1240 }
1241 
1242 static int tegra_smmu_remove(struct platform_device *pdev)
1243 {
1244         struct smmu_device *smmu = platform_get_drvdata(pdev);
1245         int i;
1246 
1247         smmu_debugfs_delete(smmu);
1248 
1249         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
1250         for (i = 0; i < smmu->num_as; i++)
1251                 free_pdir(&smmu->as[i]);
1252         __free_page(smmu->avp_vector_page);
1253         smmu_handle = NULL;
1254         return 0;
1255 }
1256 
1257 static const struct dev_pm_ops tegra_smmu_pm_ops = {
1258         .suspend        = tegra_smmu_suspend,
1259         .resume         = tegra_smmu_resume,
1260 };
1261 
1262 static struct of_device_id tegra_smmu_of_match[] = {
1263         { .compatible = "nvidia,tegra30-smmu", },
1264         { },
1265 };
1266 MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
1267 
1268 static struct platform_driver tegra_smmu_driver = {
1269         .probe          = tegra_smmu_probe,
1270         .remove         = tegra_smmu_remove,
1271         .driver = {
1272                 .owner  = THIS_MODULE,
1273                 .name   = "tegra-smmu",
1274                 .pm     = &tegra_smmu_pm_ops,
1275                 .of_match_table = tegra_smmu_of_match,
1276         },
1277 };
1278 
1279 static int tegra_smmu_init(void)
1280 {
1281         return platform_driver_register(&tegra_smmu_driver);
1282 }
1283 
1284 static void __exit tegra_smmu_exit(void)
1285 {
1286         platform_driver_unregister(&tegra_smmu_driver);
1287 }
1288 
1289 subsys_initcall(tegra_smmu_init);
1290 module_exit(tegra_smmu_exit);
1291 
1292 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1293 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1294 MODULE_ALIAS("platform:tegra-smmu");
1295 MODULE_LICENSE("GPL v2");
1296 

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