Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/iommu/omap-iommu.c

  1 /*
  2  * omap iommu: tlb and pagetable primitives
  3  *
  4  * Copyright (C) 2008-2010 Nokia Corporation
  5  *
  6  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
  7  *              Paul Mundt and Toshihiro Kobayashi
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 
 14 #include <linux/err.h>
 15 #include <linux/module.h>
 16 #include <linux/slab.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/ioport.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/iommu.h>
 21 #include <linux/omap-iommu.h>
 22 #include <linux/mutex.h>
 23 #include <linux/spinlock.h>
 24 #include <linux/io.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/of.h>
 27 #include <linux/of_iommu.h>
 28 #include <linux/of_irq.h>
 29 
 30 #include <asm/cacheflush.h>
 31 
 32 #include <linux/platform_data/iommu-omap.h>
 33 
 34 #include "omap-iopgtable.h"
 35 #include "omap-iommu.h"
 36 
 37 #define for_each_iotlb_cr(obj, n, __i, cr)                              \
 38         for (__i = 0;                                                   \
 39              (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);   \
 40              __i++)
 41 
 42 /* bitmap of the page sizes currently supported */
 43 #define OMAP_IOMMU_PGSIZES      (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
 44 
 45 /**
 46  * struct omap_iommu_domain - omap iommu domain
 47  * @pgtable:    the page table
 48  * @iommu_dev:  an omap iommu device attached to this domain. only a single
 49  *              iommu device can be attached for now.
 50  * @dev:        Device using this domain.
 51  * @lock:       domain lock, should be taken when attaching/detaching
 52  */
 53 struct omap_iommu_domain {
 54         u32 *pgtable;
 55         struct omap_iommu *iommu_dev;
 56         struct device *dev;
 57         spinlock_t lock;
 58 };
 59 
 60 #define MMU_LOCK_BASE_SHIFT     10
 61 #define MMU_LOCK_BASE_MASK      (0x1f << MMU_LOCK_BASE_SHIFT)
 62 #define MMU_LOCK_BASE(x)        \
 63         ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
 64 
 65 #define MMU_LOCK_VICT_SHIFT     4
 66 #define MMU_LOCK_VICT_MASK      (0x1f << MMU_LOCK_VICT_SHIFT)
 67 #define MMU_LOCK_VICT(x)        \
 68         ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
 69 
 70 struct iotlb_lock {
 71         short base;
 72         short vict;
 73 };
 74 
 75 /* accommodate the difference between omap1 and omap2/3 */
 76 static const struct iommu_functions *arch_iommu;
 77 
 78 static struct platform_driver omap_iommu_driver;
 79 static struct kmem_cache *iopte_cachep;
 80 
 81 /**
 82  * omap_install_iommu_arch - Install archtecure specific iommu functions
 83  * @ops:        a pointer to architecture specific iommu functions
 84  *
 85  * There are several kind of iommu algorithm(tlb, pagetable) among
 86  * omap series. This interface installs such an iommu algorighm.
 87  **/
 88 int omap_install_iommu_arch(const struct iommu_functions *ops)
 89 {
 90         if (arch_iommu)
 91                 return -EBUSY;
 92 
 93         arch_iommu = ops;
 94         return 0;
 95 }
 96 EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
 97 
 98 /**
 99  * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
100  * @ops:        a pointer to architecture specific iommu functions
101  *
102  * This interface uninstalls the iommu algorighm installed previously.
103  **/
104 void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
105 {
106         if (arch_iommu != ops)
107                 pr_err("%s: not your arch\n", __func__);
108 
109         arch_iommu = NULL;
110 }
111 EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
112 
113 /**
114  * omap_iommu_save_ctx - Save registers for pm off-mode support
115  * @dev:        client device
116  **/
117 void omap_iommu_save_ctx(struct device *dev)
118 {
119         struct omap_iommu *obj = dev_to_omap_iommu(dev);
120 
121         arch_iommu->save_ctx(obj);
122 }
123 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
124 
125 /**
126  * omap_iommu_restore_ctx - Restore registers for pm off-mode support
127  * @dev:        client device
128  **/
129 void omap_iommu_restore_ctx(struct device *dev)
130 {
131         struct omap_iommu *obj = dev_to_omap_iommu(dev);
132 
133         arch_iommu->restore_ctx(obj);
134 }
135 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
136 
137 /**
138  * omap_iommu_arch_version - Return running iommu arch version
139  **/
140 u32 omap_iommu_arch_version(void)
141 {
142         return arch_iommu->version;
143 }
144 EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
145 
146 static int iommu_enable(struct omap_iommu *obj)
147 {
148         int err;
149         struct platform_device *pdev = to_platform_device(obj->dev);
150         struct iommu_platform_data *pdata = pdev->dev.platform_data;
151 
152         if (!arch_iommu)
153                 return -ENODEV;
154 
155         if (pdata && pdata->deassert_reset) {
156                 err = pdata->deassert_reset(pdev, pdata->reset_name);
157                 if (err) {
158                         dev_err(obj->dev, "deassert_reset failed: %d\n", err);
159                         return err;
160                 }
161         }
162 
163         pm_runtime_get_sync(obj->dev);
164 
165         err = arch_iommu->enable(obj);
166 
167         return err;
168 }
169 
170 static void iommu_disable(struct omap_iommu *obj)
171 {
172         struct platform_device *pdev = to_platform_device(obj->dev);
173         struct iommu_platform_data *pdata = pdev->dev.platform_data;
174 
175         arch_iommu->disable(obj);
176 
177         pm_runtime_put_sync(obj->dev);
178 
179         if (pdata && pdata->assert_reset)
180                 pdata->assert_reset(pdev, pdata->reset_name);
181 }
182 
183 /*
184  *      TLB operations
185  */
186 void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
187 {
188         BUG_ON(!cr || !e);
189 
190         arch_iommu->cr_to_e(cr, e);
191 }
192 EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
193 
194 static inline int iotlb_cr_valid(struct cr_regs *cr)
195 {
196         if (!cr)
197                 return -EINVAL;
198 
199         return arch_iommu->cr_valid(cr);
200 }
201 
202 static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
203                                              struct iotlb_entry *e)
204 {
205         if (!e)
206                 return NULL;
207 
208         return arch_iommu->alloc_cr(obj, e);
209 }
210 
211 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
212 {
213         return arch_iommu->cr_to_virt(cr);
214 }
215 
216 static u32 get_iopte_attr(struct iotlb_entry *e)
217 {
218         return arch_iommu->get_pte_attr(e);
219 }
220 
221 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
222 {
223         return arch_iommu->fault_isr(obj, da);
224 }
225 
226 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
227 {
228         u32 val;
229 
230         val = iommu_read_reg(obj, MMU_LOCK);
231 
232         l->base = MMU_LOCK_BASE(val);
233         l->vict = MMU_LOCK_VICT(val);
234 
235 }
236 
237 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
238 {
239         u32 val;
240 
241         val = (l->base << MMU_LOCK_BASE_SHIFT);
242         val |= (l->vict << MMU_LOCK_VICT_SHIFT);
243 
244         iommu_write_reg(obj, val, MMU_LOCK);
245 }
246 
247 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
248 {
249         arch_iommu->tlb_read_cr(obj, cr);
250 }
251 
252 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
253 {
254         arch_iommu->tlb_load_cr(obj, cr);
255 
256         iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
257         iommu_write_reg(obj, 1, MMU_LD_TLB);
258 }
259 
260 /**
261  * iotlb_dump_cr - Dump an iommu tlb entry into buf
262  * @obj:        target iommu
263  * @cr:         contents of cam and ram register
264  * @buf:        output buffer
265  **/
266 static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
267                                     char *buf)
268 {
269         BUG_ON(!cr || !buf);
270 
271         return arch_iommu->dump_cr(obj, cr, buf);
272 }
273 
274 /* only used in iotlb iteration for-loop */
275 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
276 {
277         struct cr_regs cr;
278         struct iotlb_lock l;
279 
280         iotlb_lock_get(obj, &l);
281         l.vict = n;
282         iotlb_lock_set(obj, &l);
283         iotlb_read_cr(obj, &cr);
284 
285         return cr;
286 }
287 
288 /**
289  * load_iotlb_entry - Set an iommu tlb entry
290  * @obj:        target iommu
291  * @e:          an iommu tlb entry info
292  **/
293 #ifdef PREFETCH_IOTLB
294 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
295 {
296         int err = 0;
297         struct iotlb_lock l;
298         struct cr_regs *cr;
299 
300         if (!obj || !obj->nr_tlb_entries || !e)
301                 return -EINVAL;
302 
303         pm_runtime_get_sync(obj->dev);
304 
305         iotlb_lock_get(obj, &l);
306         if (l.base == obj->nr_tlb_entries) {
307                 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
308                 err = -EBUSY;
309                 goto out;
310         }
311         if (!e->prsvd) {
312                 int i;
313                 struct cr_regs tmp;
314 
315                 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
316                         if (!iotlb_cr_valid(&tmp))
317                                 break;
318 
319                 if (i == obj->nr_tlb_entries) {
320                         dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
321                         err = -EBUSY;
322                         goto out;
323                 }
324 
325                 iotlb_lock_get(obj, &l);
326         } else {
327                 l.vict = l.base;
328                 iotlb_lock_set(obj, &l);
329         }
330 
331         cr = iotlb_alloc_cr(obj, e);
332         if (IS_ERR(cr)) {
333                 pm_runtime_put_sync(obj->dev);
334                 return PTR_ERR(cr);
335         }
336 
337         iotlb_load_cr(obj, cr);
338         kfree(cr);
339 
340         if (e->prsvd)
341                 l.base++;
342         /* increment victim for next tlb load */
343         if (++l.vict == obj->nr_tlb_entries)
344                 l.vict = l.base;
345         iotlb_lock_set(obj, &l);
346 out:
347         pm_runtime_put_sync(obj->dev);
348         return err;
349 }
350 
351 #else /* !PREFETCH_IOTLB */
352 
353 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
354 {
355         return 0;
356 }
357 
358 #endif /* !PREFETCH_IOTLB */
359 
360 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
361 {
362         return load_iotlb_entry(obj, e);
363 }
364 
365 /**
366  * flush_iotlb_page - Clear an iommu tlb entry
367  * @obj:        target iommu
368  * @da:         iommu device virtual address
369  *
370  * Clear an iommu tlb entry which includes 'da' address.
371  **/
372 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
373 {
374         int i;
375         struct cr_regs cr;
376 
377         pm_runtime_get_sync(obj->dev);
378 
379         for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
380                 u32 start;
381                 size_t bytes;
382 
383                 if (!iotlb_cr_valid(&cr))
384                         continue;
385 
386                 start = iotlb_cr_to_virt(&cr);
387                 bytes = iopgsz_to_bytes(cr.cam & 3);
388 
389                 if ((start <= da) && (da < start + bytes)) {
390                         dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
391                                 __func__, start, da, bytes);
392                         iotlb_load_cr(obj, &cr);
393                         iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
394                 }
395         }
396         pm_runtime_put_sync(obj->dev);
397 
398         if (i == obj->nr_tlb_entries)
399                 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
400 }
401 
402 /**
403  * flush_iotlb_all - Clear all iommu tlb entries
404  * @obj:        target iommu
405  **/
406 static void flush_iotlb_all(struct omap_iommu *obj)
407 {
408         struct iotlb_lock l;
409 
410         pm_runtime_get_sync(obj->dev);
411 
412         l.base = 0;
413         l.vict = 0;
414         iotlb_lock_set(obj, &l);
415 
416         iommu_write_reg(obj, 1, MMU_GFLUSH);
417 
418         pm_runtime_put_sync(obj->dev);
419 }
420 
421 #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
422 
423 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
424 {
425         if (!obj || !buf)
426                 return -EINVAL;
427 
428         pm_runtime_get_sync(obj->dev);
429 
430         bytes = arch_iommu->dump_ctx(obj, buf, bytes);
431 
432         pm_runtime_put_sync(obj->dev);
433 
434         return bytes;
435 }
436 EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
437 
438 static int
439 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
440 {
441         int i;
442         struct iotlb_lock saved;
443         struct cr_regs tmp;
444         struct cr_regs *p = crs;
445 
446         pm_runtime_get_sync(obj->dev);
447         iotlb_lock_get(obj, &saved);
448 
449         for_each_iotlb_cr(obj, num, i, tmp) {
450                 if (!iotlb_cr_valid(&tmp))
451                         continue;
452                 *p++ = tmp;
453         }
454 
455         iotlb_lock_set(obj, &saved);
456         pm_runtime_put_sync(obj->dev);
457 
458         return  p - crs;
459 }
460 
461 /**
462  * omap_dump_tlb_entries - dump cr arrays to given buffer
463  * @obj:        target iommu
464  * @buf:        output buffer
465  **/
466 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
467 {
468         int i, num;
469         struct cr_regs *cr;
470         char *p = buf;
471 
472         num = bytes / sizeof(*cr);
473         num = min(obj->nr_tlb_entries, num);
474 
475         cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
476         if (!cr)
477                 return 0;
478 
479         num = __dump_tlb_entries(obj, cr, num);
480         for (i = 0; i < num; i++)
481                 p += iotlb_dump_cr(obj, cr + i, p);
482         kfree(cr);
483 
484         return p - buf;
485 }
486 EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
487 
488 int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
489 {
490         return driver_for_each_device(&omap_iommu_driver.driver,
491                                       NULL, data, fn);
492 }
493 EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
494 
495 #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
496 
497 /*
498  *      H/W pagetable operations
499  */
500 static void flush_iopgd_range(u32 *first, u32 *last)
501 {
502         /* FIXME: L2 cache should be taken care of if it exists */
503         do {
504                 asm("mcr        p15, 0, %0, c7, c10, 1 @ flush_pgd"
505                     : : "r" (first));
506                 first += L1_CACHE_BYTES / sizeof(*first);
507         } while (first <= last);
508 }
509 
510 static void flush_iopte_range(u32 *first, u32 *last)
511 {
512         /* FIXME: L2 cache should be taken care of if it exists */
513         do {
514                 asm("mcr        p15, 0, %0, c7, c10, 1 @ flush_pte"
515                     : : "r" (first));
516                 first += L1_CACHE_BYTES / sizeof(*first);
517         } while (first <= last);
518 }
519 
520 static void iopte_free(u32 *iopte)
521 {
522         /* Note: freed iopte's must be clean ready for re-use */
523         if (iopte)
524                 kmem_cache_free(iopte_cachep, iopte);
525 }
526 
527 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
528 {
529         u32 *iopte;
530 
531         /* a table has already existed */
532         if (*iopgd)
533                 goto pte_ready;
534 
535         /*
536          * do the allocation outside the page table lock
537          */
538         spin_unlock(&obj->page_table_lock);
539         iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
540         spin_lock(&obj->page_table_lock);
541 
542         if (!*iopgd) {
543                 if (!iopte)
544                         return ERR_PTR(-ENOMEM);
545 
546                 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
547                 flush_iopgd_range(iopgd, iopgd);
548 
549                 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
550         } else {
551                 /* We raced, free the reduniovant table */
552                 iopte_free(iopte);
553         }
554 
555 pte_ready:
556         iopte = iopte_offset(iopgd, da);
557 
558         dev_vdbg(obj->dev,
559                  "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
560                  __func__, da, iopgd, *iopgd, iopte, *iopte);
561 
562         return iopte;
563 }
564 
565 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
566 {
567         u32 *iopgd = iopgd_offset(obj, da);
568 
569         if ((da | pa) & ~IOSECTION_MASK) {
570                 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
571                         __func__, da, pa, IOSECTION_SIZE);
572                 return -EINVAL;
573         }
574 
575         *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
576         flush_iopgd_range(iopgd, iopgd);
577         return 0;
578 }
579 
580 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
581 {
582         u32 *iopgd = iopgd_offset(obj, da);
583         int i;
584 
585         if ((da | pa) & ~IOSUPER_MASK) {
586                 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
587                         __func__, da, pa, IOSUPER_SIZE);
588                 return -EINVAL;
589         }
590 
591         for (i = 0; i < 16; i++)
592                 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
593         flush_iopgd_range(iopgd, iopgd + 15);
594         return 0;
595 }
596 
597 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
598 {
599         u32 *iopgd = iopgd_offset(obj, da);
600         u32 *iopte = iopte_alloc(obj, iopgd, da);
601 
602         if (IS_ERR(iopte))
603                 return PTR_ERR(iopte);
604 
605         *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
606         flush_iopte_range(iopte, iopte);
607 
608         dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
609                  __func__, da, pa, iopte, *iopte);
610 
611         return 0;
612 }
613 
614 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
615 {
616         u32 *iopgd = iopgd_offset(obj, da);
617         u32 *iopte = iopte_alloc(obj, iopgd, da);
618         int i;
619 
620         if ((da | pa) & ~IOLARGE_MASK) {
621                 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
622                         __func__, da, pa, IOLARGE_SIZE);
623                 return -EINVAL;
624         }
625 
626         if (IS_ERR(iopte))
627                 return PTR_ERR(iopte);
628 
629         for (i = 0; i < 16; i++)
630                 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
631         flush_iopte_range(iopte, iopte + 15);
632         return 0;
633 }
634 
635 static int
636 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
637 {
638         int (*fn)(struct omap_iommu *, u32, u32, u32);
639         u32 prot;
640         int err;
641 
642         if (!obj || !e)
643                 return -EINVAL;
644 
645         switch (e->pgsz) {
646         case MMU_CAM_PGSZ_16M:
647                 fn = iopgd_alloc_super;
648                 break;
649         case MMU_CAM_PGSZ_1M:
650                 fn = iopgd_alloc_section;
651                 break;
652         case MMU_CAM_PGSZ_64K:
653                 fn = iopte_alloc_large;
654                 break;
655         case MMU_CAM_PGSZ_4K:
656                 fn = iopte_alloc_page;
657                 break;
658         default:
659                 fn = NULL;
660                 BUG();
661                 break;
662         }
663 
664         prot = get_iopte_attr(e);
665 
666         spin_lock(&obj->page_table_lock);
667         err = fn(obj, e->da, e->pa, prot);
668         spin_unlock(&obj->page_table_lock);
669 
670         return err;
671 }
672 
673 /**
674  * omap_iopgtable_store_entry - Make an iommu pte entry
675  * @obj:        target iommu
676  * @e:          an iommu tlb entry info
677  **/
678 int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
679 {
680         int err;
681 
682         flush_iotlb_page(obj, e->da);
683         err = iopgtable_store_entry_core(obj, e);
684         if (!err)
685                 prefetch_iotlb_entry(obj, e);
686         return err;
687 }
688 EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
689 
690 /**
691  * iopgtable_lookup_entry - Lookup an iommu pte entry
692  * @obj:        target iommu
693  * @da:         iommu device virtual address
694  * @ppgd:       iommu pgd entry pointer to be returned
695  * @ppte:       iommu pte entry pointer to be returned
696  **/
697 static void
698 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
699 {
700         u32 *iopgd, *iopte = NULL;
701 
702         iopgd = iopgd_offset(obj, da);
703         if (!*iopgd)
704                 goto out;
705 
706         if (iopgd_is_table(*iopgd))
707                 iopte = iopte_offset(iopgd, da);
708 out:
709         *ppgd = iopgd;
710         *ppte = iopte;
711 }
712 
713 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
714 {
715         size_t bytes;
716         u32 *iopgd = iopgd_offset(obj, da);
717         int nent = 1;
718 
719         if (!*iopgd)
720                 return 0;
721 
722         if (iopgd_is_table(*iopgd)) {
723                 int i;
724                 u32 *iopte = iopte_offset(iopgd, da);
725 
726                 bytes = IOPTE_SIZE;
727                 if (*iopte & IOPTE_LARGE) {
728                         nent *= 16;
729                         /* rewind to the 1st entry */
730                         iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
731                 }
732                 bytes *= nent;
733                 memset(iopte, 0, nent * sizeof(*iopte));
734                 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
735 
736                 /*
737                  * do table walk to check if this table is necessary or not
738                  */
739                 iopte = iopte_offset(iopgd, 0);
740                 for (i = 0; i < PTRS_PER_IOPTE; i++)
741                         if (iopte[i])
742                                 goto out;
743 
744                 iopte_free(iopte);
745                 nent = 1; /* for the next L1 entry */
746         } else {
747                 bytes = IOPGD_SIZE;
748                 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
749                         nent *= 16;
750                         /* rewind to the 1st entry */
751                         iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
752                 }
753                 bytes *= nent;
754         }
755         memset(iopgd, 0, nent * sizeof(*iopgd));
756         flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
757 out:
758         return bytes;
759 }
760 
761 /**
762  * iopgtable_clear_entry - Remove an iommu pte entry
763  * @obj:        target iommu
764  * @da:         iommu device virtual address
765  **/
766 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
767 {
768         size_t bytes;
769 
770         spin_lock(&obj->page_table_lock);
771 
772         bytes = iopgtable_clear_entry_core(obj, da);
773         flush_iotlb_page(obj, da);
774 
775         spin_unlock(&obj->page_table_lock);
776 
777         return bytes;
778 }
779 
780 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
781 {
782         int i;
783 
784         spin_lock(&obj->page_table_lock);
785 
786         for (i = 0; i < PTRS_PER_IOPGD; i++) {
787                 u32 da;
788                 u32 *iopgd;
789 
790                 da = i << IOPGD_SHIFT;
791                 iopgd = iopgd_offset(obj, da);
792 
793                 if (!*iopgd)
794                         continue;
795 
796                 if (iopgd_is_table(*iopgd))
797                         iopte_free(iopte_offset(iopgd, 0));
798 
799                 *iopgd = 0;
800                 flush_iopgd_range(iopgd, iopgd);
801         }
802 
803         flush_iotlb_all(obj);
804 
805         spin_unlock(&obj->page_table_lock);
806 }
807 
808 /*
809  *      Device IOMMU generic operations
810  */
811 static irqreturn_t iommu_fault_handler(int irq, void *data)
812 {
813         u32 da, errs;
814         u32 *iopgd, *iopte;
815         struct omap_iommu *obj = data;
816         struct iommu_domain *domain = obj->domain;
817 
818         if (!obj->refcount)
819                 return IRQ_NONE;
820 
821         errs = iommu_report_fault(obj, &da);
822         if (errs == 0)
823                 return IRQ_HANDLED;
824 
825         /* Fault callback or TLB/PTE Dynamic loading */
826         if (!report_iommu_fault(domain, obj->dev, da, 0))
827                 return IRQ_HANDLED;
828 
829         iommu_disable(obj);
830 
831         iopgd = iopgd_offset(obj, da);
832 
833         if (!iopgd_is_table(*iopgd)) {
834                 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
835                                 obj->name, errs, da, iopgd, *iopgd);
836                 return IRQ_NONE;
837         }
838 
839         iopte = iopte_offset(iopgd, da);
840 
841         dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
842                         obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
843 
844         return IRQ_NONE;
845 }
846 
847 static int device_match_by_alias(struct device *dev, void *data)
848 {
849         struct omap_iommu *obj = to_iommu(dev);
850         const char *name = data;
851 
852         pr_debug("%s: %s %s\n", __func__, obj->name, name);
853 
854         return strcmp(obj->name, name) == 0;
855 }
856 
857 /**
858  * omap_iommu_attach() - attach iommu device to an iommu domain
859  * @name:       name of target omap iommu device
860  * @iopgd:      page table
861  **/
862 static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
863 {
864         int err;
865         struct device *dev;
866         struct omap_iommu *obj;
867 
868         dev = driver_find_device(&omap_iommu_driver.driver, NULL,
869                                 (void *)name,
870                                 device_match_by_alias);
871         if (!dev)
872                 return ERR_PTR(-ENODEV);
873 
874         obj = to_iommu(dev);
875 
876         spin_lock(&obj->iommu_lock);
877 
878         /* an iommu device can only be attached once */
879         if (++obj->refcount > 1) {
880                 dev_err(dev, "%s: already attached!\n", obj->name);
881                 err = -EBUSY;
882                 goto err_enable;
883         }
884 
885         obj->iopgd = iopgd;
886         err = iommu_enable(obj);
887         if (err)
888                 goto err_enable;
889         flush_iotlb_all(obj);
890 
891         if (!try_module_get(obj->owner)) {
892                 err = -ENODEV;
893                 goto err_module;
894         }
895 
896         spin_unlock(&obj->iommu_lock);
897 
898         dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
899         return obj;
900 
901 err_module:
902         if (obj->refcount == 1)
903                 iommu_disable(obj);
904 err_enable:
905         obj->refcount--;
906         spin_unlock(&obj->iommu_lock);
907         return ERR_PTR(err);
908 }
909 
910 /**
911  * omap_iommu_detach - release iommu device
912  * @obj:        target iommu
913  **/
914 static void omap_iommu_detach(struct omap_iommu *obj)
915 {
916         if (!obj || IS_ERR(obj))
917                 return;
918 
919         spin_lock(&obj->iommu_lock);
920 
921         if (--obj->refcount == 0)
922                 iommu_disable(obj);
923 
924         module_put(obj->owner);
925 
926         obj->iopgd = NULL;
927 
928         spin_unlock(&obj->iommu_lock);
929 
930         dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
931 }
932 
933 /*
934  *      OMAP Device MMU(IOMMU) detection
935  */
936 static int omap_iommu_probe(struct platform_device *pdev)
937 {
938         int err = -ENODEV;
939         int irq;
940         struct omap_iommu *obj;
941         struct resource *res;
942         struct iommu_platform_data *pdata = pdev->dev.platform_data;
943         struct device_node *of = pdev->dev.of_node;
944 
945         obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
946         if (!obj)
947                 return -ENOMEM;
948 
949         if (of) {
950                 obj->name = dev_name(&pdev->dev);
951                 obj->nr_tlb_entries = 32;
952                 err = of_property_read_u32(of, "ti,#tlb-entries",
953                                            &obj->nr_tlb_entries);
954                 if (err && err != -EINVAL)
955                         return err;
956                 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
957                         return -EINVAL;
958                 /*
959                  * da_start and da_end are needed for omap-iovmm, so hardcode
960                  * these values as used by OMAP3 ISP - the only user for
961                  * omap-iovmm
962                  */
963                 obj->da_start = 0;
964                 obj->da_end = 0xfffff000;
965                 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
966                         obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
967         } else {
968                 obj->nr_tlb_entries = pdata->nr_tlb_entries;
969                 obj->name = pdata->name;
970                 obj->da_start = pdata->da_start;
971                 obj->da_end = pdata->da_end;
972         }
973         if (obj->da_end <= obj->da_start)
974                 return -EINVAL;
975 
976         obj->dev = &pdev->dev;
977         obj->ctx = (void *)obj + sizeof(*obj);
978 
979         spin_lock_init(&obj->iommu_lock);
980         mutex_init(&obj->mmap_lock);
981         spin_lock_init(&obj->page_table_lock);
982         INIT_LIST_HEAD(&obj->mmap);
983 
984         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
985         obj->regbase = devm_ioremap_resource(obj->dev, res);
986         if (IS_ERR(obj->regbase))
987                 return PTR_ERR(obj->regbase);
988 
989         irq = platform_get_irq(pdev, 0);
990         if (irq < 0)
991                 return -ENODEV;
992 
993         err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
994                                dev_name(obj->dev), obj);
995         if (err < 0)
996                 return err;
997         platform_set_drvdata(pdev, obj);
998 
999         pm_runtime_irq_safe(obj->dev);
1000         pm_runtime_enable(obj->dev);
1001 
1002         dev_info(&pdev->dev, "%s registered\n", obj->name);
1003         return 0;
1004 }
1005 
1006 static int omap_iommu_remove(struct platform_device *pdev)
1007 {
1008         struct omap_iommu *obj = platform_get_drvdata(pdev);
1009 
1010         iopgtable_clear_entry_all(obj);
1011 
1012         pm_runtime_disable(obj->dev);
1013 
1014         dev_info(&pdev->dev, "%s removed\n", obj->name);
1015         return 0;
1016 }
1017 
1018 static struct of_device_id omap_iommu_of_match[] = {
1019         { .compatible = "ti,omap2-iommu" },
1020         { .compatible = "ti,omap4-iommu" },
1021         { .compatible = "ti,dra7-iommu" },
1022         {},
1023 };
1024 MODULE_DEVICE_TABLE(of, omap_iommu_of_match);
1025 
1026 static struct platform_driver omap_iommu_driver = {
1027         .probe  = omap_iommu_probe,
1028         .remove = omap_iommu_remove,
1029         .driver = {
1030                 .name   = "omap-iommu",
1031                 .of_match_table = of_match_ptr(omap_iommu_of_match),
1032         },
1033 };
1034 
1035 static void iopte_cachep_ctor(void *iopte)
1036 {
1037         clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1038 }
1039 
1040 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
1041                                    u32 flags)
1042 {
1043         memset(e, 0, sizeof(*e));
1044 
1045         e->da           = da;
1046         e->pa           = pa;
1047         e->valid        = 1;
1048         /* FIXME: add OMAP1 support */
1049         e->pgsz         = flags & MMU_CAM_PGSZ_MASK;
1050         e->endian       = flags & MMU_RAM_ENDIAN_MASK;
1051         e->elsz         = flags & MMU_RAM_ELSZ_MASK;
1052         e->mixed        = flags & MMU_RAM_MIXED_MASK;
1053 
1054         return iopgsz_to_bytes(e->pgsz);
1055 }
1056 
1057 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1058                          phys_addr_t pa, size_t bytes, int prot)
1059 {
1060         struct omap_iommu_domain *omap_domain = domain->priv;
1061         struct omap_iommu *oiommu = omap_domain->iommu_dev;
1062         struct device *dev = oiommu->dev;
1063         struct iotlb_entry e;
1064         int omap_pgsz;
1065         u32 ret, flags;
1066 
1067         /* we only support mapping a single iommu page for now */
1068         omap_pgsz = bytes_to_iopgsz(bytes);
1069         if (omap_pgsz < 0) {
1070                 dev_err(dev, "invalid size to map: %d\n", bytes);
1071                 return -EINVAL;
1072         }
1073 
1074         dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1075 
1076         flags = omap_pgsz | prot;
1077 
1078         iotlb_init_entry(&e, da, pa, flags);
1079 
1080         ret = omap_iopgtable_store_entry(oiommu, &e);
1081         if (ret)
1082                 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1083 
1084         return ret;
1085 }
1086 
1087 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1088                             size_t size)
1089 {
1090         struct omap_iommu_domain *omap_domain = domain->priv;
1091         struct omap_iommu *oiommu = omap_domain->iommu_dev;
1092         struct device *dev = oiommu->dev;
1093 
1094         dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1095 
1096         return iopgtable_clear_entry(oiommu, da);
1097 }
1098 
1099 static int
1100 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1101 {
1102         struct omap_iommu_domain *omap_domain = domain->priv;
1103         struct omap_iommu *oiommu;
1104         struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1105         int ret = 0;
1106 
1107         spin_lock(&omap_domain->lock);
1108 
1109         /* only a single device is supported per domain for now */
1110         if (omap_domain->iommu_dev) {
1111                 dev_err(dev, "iommu domain is already attached\n");
1112                 ret = -EBUSY;
1113                 goto out;
1114         }
1115 
1116         /* get a handle to and enable the omap iommu */
1117         oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
1118         if (IS_ERR(oiommu)) {
1119                 ret = PTR_ERR(oiommu);
1120                 dev_err(dev, "can't get omap iommu: %d\n", ret);
1121                 goto out;
1122         }
1123 
1124         omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
1125         omap_domain->dev = dev;
1126         oiommu->domain = domain;
1127 
1128 out:
1129         spin_unlock(&omap_domain->lock);
1130         return ret;
1131 }
1132 
1133 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1134                         struct device *dev)
1135 {
1136         struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
1137         struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1138 
1139         /* only a single device is supported per domain for now */
1140         if (omap_domain->iommu_dev != oiommu) {
1141                 dev_err(dev, "invalid iommu device\n");
1142                 return;
1143         }
1144 
1145         iopgtable_clear_entry_all(oiommu);
1146 
1147         omap_iommu_detach(oiommu);
1148 
1149         omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
1150         omap_domain->dev = NULL;
1151 }
1152 
1153 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1154                                  struct device *dev)
1155 {
1156         struct omap_iommu_domain *omap_domain = domain->priv;
1157 
1158         spin_lock(&omap_domain->lock);
1159         _omap_iommu_detach_dev(omap_domain, dev);
1160         spin_unlock(&omap_domain->lock);
1161 }
1162 
1163 static int omap_iommu_domain_init(struct iommu_domain *domain)
1164 {
1165         struct omap_iommu_domain *omap_domain;
1166 
1167         omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1168         if (!omap_domain) {
1169                 pr_err("kzalloc failed\n");
1170                 goto out;
1171         }
1172 
1173         omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1174         if (!omap_domain->pgtable) {
1175                 pr_err("kzalloc failed\n");
1176                 goto fail_nomem;
1177         }
1178 
1179         /*
1180          * should never fail, but please keep this around to ensure
1181          * we keep the hardware happy
1182          */
1183         BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1184 
1185         clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1186         spin_lock_init(&omap_domain->lock);
1187 
1188         domain->priv = omap_domain;
1189 
1190         domain->geometry.aperture_start = 0;
1191         domain->geometry.aperture_end   = (1ULL << 32) - 1;
1192         domain->geometry.force_aperture = true;
1193 
1194         return 0;
1195 
1196 fail_nomem:
1197         kfree(omap_domain);
1198 out:
1199         return -ENOMEM;
1200 }
1201 
1202 static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1203 {
1204         struct omap_iommu_domain *omap_domain = domain->priv;
1205 
1206         domain->priv = NULL;
1207 
1208         /*
1209          * An iommu device is still attached
1210          * (currently, only one device can be attached) ?
1211          */
1212         if (omap_domain->iommu_dev)
1213                 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1214 
1215         kfree(omap_domain->pgtable);
1216         kfree(omap_domain);
1217 }
1218 
1219 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1220                                           dma_addr_t da)
1221 {
1222         struct omap_iommu_domain *omap_domain = domain->priv;
1223         struct omap_iommu *oiommu = omap_domain->iommu_dev;
1224         struct device *dev = oiommu->dev;
1225         u32 *pgd, *pte;
1226         phys_addr_t ret = 0;
1227 
1228         iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1229 
1230         if (pte) {
1231                 if (iopte_is_small(*pte))
1232                         ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1233                 else if (iopte_is_large(*pte))
1234                         ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1235                 else
1236                         dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1237                                                         (unsigned long long)da);
1238         } else {
1239                 if (iopgd_is_section(*pgd))
1240                         ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1241                 else if (iopgd_is_super(*pgd))
1242                         ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1243                 else
1244                         dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1245                                                         (unsigned long long)da);
1246         }
1247 
1248         return ret;
1249 }
1250 
1251 static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1252                                     unsigned long cap)
1253 {
1254         return 0;
1255 }
1256 
1257 static int omap_iommu_add_device(struct device *dev)
1258 {
1259         struct omap_iommu_arch_data *arch_data;
1260         struct device_node *np;
1261 
1262         /*
1263          * Allocate the archdata iommu structure for DT-based devices.
1264          *
1265          * TODO: Simplify this when removing non-DT support completely from the
1266          * IOMMU users.
1267          */
1268         if (!dev->of_node)
1269                 return 0;
1270 
1271         np = of_parse_phandle(dev->of_node, "iommus", 0);
1272         if (!np)
1273                 return 0;
1274 
1275         arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL);
1276         if (!arch_data) {
1277                 of_node_put(np);
1278                 return -ENOMEM;
1279         }
1280 
1281         arch_data->name = kstrdup(dev_name(dev), GFP_KERNEL);
1282         dev->archdata.iommu = arch_data;
1283 
1284         of_node_put(np);
1285 
1286         return 0;
1287 }
1288 
1289 static void omap_iommu_remove_device(struct device *dev)
1290 {
1291         struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1292 
1293         if (!dev->of_node || !arch_data)
1294                 return;
1295 
1296         kfree(arch_data->name);
1297         kfree(arch_data);
1298 }
1299 
1300 static struct iommu_ops omap_iommu_ops = {
1301         .domain_init    = omap_iommu_domain_init,
1302         .domain_destroy = omap_iommu_domain_destroy,
1303         .attach_dev     = omap_iommu_attach_dev,
1304         .detach_dev     = omap_iommu_detach_dev,
1305         .map            = omap_iommu_map,
1306         .unmap          = omap_iommu_unmap,
1307         .iova_to_phys   = omap_iommu_iova_to_phys,
1308         .domain_has_cap = omap_iommu_domain_has_cap,
1309         .add_device     = omap_iommu_add_device,
1310         .remove_device  = omap_iommu_remove_device,
1311         .pgsize_bitmap  = OMAP_IOMMU_PGSIZES,
1312 };
1313 
1314 static int __init omap_iommu_init(void)
1315 {
1316         struct kmem_cache *p;
1317         const unsigned long flags = SLAB_HWCACHE_ALIGN;
1318         size_t align = 1 << 10; /* L2 pagetable alignement */
1319 
1320         p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1321                               iopte_cachep_ctor);
1322         if (!p)
1323                 return -ENOMEM;
1324         iopte_cachep = p;
1325 
1326         bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1327 
1328         return platform_driver_register(&omap_iommu_driver);
1329 }
1330 /* must be ready before omap3isp is probed */
1331 subsys_initcall(omap_iommu_init);
1332 
1333 static void __exit omap_iommu_exit(void)
1334 {
1335         kmem_cache_destroy(iopte_cachep);
1336 
1337         platform_driver_unregister(&omap_iommu_driver);
1338 }
1339 module_exit(omap_iommu_exit);
1340 
1341 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1342 MODULE_ALIAS("platform:omap-iommu");
1343 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1344 MODULE_LICENSE("GPL v2");
1345 

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