Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/iommu/fsl_pamu.c

  1 /*
  2  * This program is free software; you can redistribute it and/or modify
  3  * it under the terms of the GNU General Public License, version 2, as
  4  * published by the Free Software Foundation.
  5  *
  6  * This program is distributed in the hope that it will be useful,
  7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  9  * GNU General Public License for more details.
 10  *
 11  * You should have received a copy of the GNU General Public License
 12  * along with this program; if not, write to the Free Software
 13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 14  *
 15  * Copyright (C) 2013 Freescale Semiconductor, Inc.
 16  *
 17  */
 18 
 19 #define pr_fmt(fmt)    "fsl-pamu: %s: " fmt, __func__
 20 
 21 #include "fsl_pamu.h"
 22 
 23 #include <linux/fsl/guts.h>
 24 #include <linux/interrupt.h>
 25 #include <linux/genalloc.h>
 26 
 27 #include <asm/mpc85xx.h>
 28 
 29 /* define indexes for each operation mapping scenario */
 30 #define OMI_QMAN        0x00
 31 #define OMI_FMAN        0x01
 32 #define OMI_QMAN_PRIV   0x02
 33 #define OMI_CAAM        0x03
 34 
 35 #define make64(high, low) (((u64)(high) << 32) | (low))
 36 
 37 struct pamu_isr_data {
 38         void __iomem *pamu_reg_base;    /* Base address of PAMU regs */
 39         unsigned int count;             /* The number of PAMUs */
 40 };
 41 
 42 static struct paace *ppaact;
 43 static struct paace *spaact;
 44 
 45 /*
 46  * Table for matching compatible strings, for device tree
 47  * guts node, for QorIQ SOCs.
 48  * "fsl,qoriq-device-config-2.0" corresponds to T4 & B4
 49  * SOCs. For the older SOCs "fsl,qoriq-device-config-1.0"
 50  * string would be used.
 51  */
 52 static const struct of_device_id guts_device_ids[] = {
 53         { .compatible = "fsl,qoriq-device-config-1.0", },
 54         { .compatible = "fsl,qoriq-device-config-2.0", },
 55         {}
 56 };
 57 
 58 /*
 59  * Table for matching compatible strings, for device tree
 60  * L3 cache controller node.
 61  * "fsl,t4240-l3-cache-controller" corresponds to T4,
 62  * "fsl,b4860-l3-cache-controller" corresponds to B4 &
 63  * "fsl,p4080-l3-cache-controller" corresponds to other,
 64  * SOCs.
 65  */
 66 static const struct of_device_id l3_device_ids[] = {
 67         { .compatible = "fsl,t4240-l3-cache-controller", },
 68         { .compatible = "fsl,b4860-l3-cache-controller", },
 69         { .compatible = "fsl,p4080-l3-cache-controller", },
 70         {}
 71 };
 72 
 73 /* maximum subwindows permitted per liodn */
 74 static u32 max_subwindow_count;
 75 
 76 /* Pool for fspi allocation */
 77 static struct gen_pool *spaace_pool;
 78 
 79 /**
 80  * pamu_get_max_subwin_cnt() - Return the maximum supported
 81  * subwindow count per liodn.
 82  *
 83  */
 84 u32 pamu_get_max_subwin_cnt(void)
 85 {
 86         return max_subwindow_count;
 87 }
 88 
 89 /**
 90  * pamu_get_ppaace() - Return the primary PACCE
 91  * @liodn: liodn PAACT index for desired PAACE
 92  *
 93  * Returns the ppace pointer upon success else return
 94  * null.
 95  */
 96 static struct paace *pamu_get_ppaace(int liodn)
 97 {
 98         if (!ppaact || liodn >= PAACE_NUMBER_ENTRIES) {
 99                 pr_debug("PPAACT doesn't exist\n");
100                 return NULL;
101         }
102 
103         return &ppaact[liodn];
104 }
105 
106 /**
107  * pamu_enable_liodn() - Set valid bit of PACCE
108  * @liodn: liodn PAACT index for desired PAACE
109  *
110  * Returns 0 upon success else error code < 0 returned
111  */
112 int pamu_enable_liodn(int liodn)
113 {
114         struct paace *ppaace;
115 
116         ppaace = pamu_get_ppaace(liodn);
117         if (!ppaace) {
118                 pr_debug("Invalid primary paace entry\n");
119                 return -ENOENT;
120         }
121 
122         if (!get_bf(ppaace->addr_bitfields, PPAACE_AF_WSE)) {
123                 pr_debug("liodn %d not configured\n", liodn);
124                 return -EINVAL;
125         }
126 
127         /* Ensure that all other stores to the ppaace complete first */
128         mb();
129 
130         set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID);
131         mb();
132 
133         return 0;
134 }
135 
136 /**
137  * pamu_disable_liodn() - Clears valid bit of PACCE
138  * @liodn: liodn PAACT index for desired PAACE
139  *
140  * Returns 0 upon success else error code < 0 returned
141  */
142 int pamu_disable_liodn(int liodn)
143 {
144         struct paace *ppaace;
145 
146         ppaace = pamu_get_ppaace(liodn);
147         if (!ppaace) {
148                 pr_debug("Invalid primary paace entry\n");
149                 return -ENOENT;
150         }
151 
152         set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
153         mb();
154 
155         return 0;
156 }
157 
158 /* Derive the window size encoding for a particular PAACE entry */
159 static unsigned int map_addrspace_size_to_wse(phys_addr_t addrspace_size)
160 {
161         /* Bug if not a power of 2 */
162         BUG_ON(addrspace_size & (addrspace_size - 1));
163 
164         /* window size is 2^(WSE+1) bytes */
165         return fls64(addrspace_size) - 2;
166 }
167 
168 /* Derive the PAACE window count encoding for the subwindow count */
169 static unsigned int map_subwindow_cnt_to_wce(u32 subwindow_cnt)
170 {
171         /* window count is 2^(WCE+1) bytes */
172         return __ffs(subwindow_cnt) - 1;
173 }
174 
175 /*
176  * Set the PAACE type as primary and set the coherency required domain
177  * attribute
178  */
179 static void pamu_init_ppaace(struct paace *ppaace)
180 {
181         set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
182 
183         set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
184                PAACE_M_COHERENCE_REQ);
185 }
186 
187 /*
188  * Set the PAACE type as secondary and set the coherency required domain
189  * attribute.
190  */
191 static void pamu_init_spaace(struct paace *spaace)
192 {
193         set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
194         set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
195                PAACE_M_COHERENCE_REQ);
196 }
197 
198 /*
199  * Return the spaace (corresponding to the secondary window index)
200  * for a particular ppaace.
201  */
202 static struct paace *pamu_get_spaace(struct paace *paace, u32 wnum)
203 {
204         u32 subwin_cnt;
205         struct paace *spaace = NULL;
206 
207         subwin_cnt = 1UL << (get_bf(paace->impl_attr, PAACE_IA_WCE) + 1);
208 
209         if (wnum < subwin_cnt)
210                 spaace = &spaact[paace->fspi + wnum];
211         else
212                 pr_debug("secondary paace out of bounds\n");
213 
214         return spaace;
215 }
216 
217 /**
218  * pamu_get_fspi_and_allocate() - Allocates fspi index and reserves subwindows
219  *                                required for primary PAACE in the secondary
220  *                                PAACE table.
221  * @subwin_cnt: Number of subwindows to be reserved.
222  *
223  * A PPAACE entry may have a number of associated subwindows. A subwindow
224  * corresponds to a SPAACE entry in the SPAACT table. Each PAACE entry stores
225  * the index (fspi) of the first SPAACE entry in the SPAACT table. This
226  * function returns the index of the first SPAACE entry. The remaining
227  * SPAACE entries are reserved contiguously from that index.
228  *
229  * Returns a valid fspi index in the range of 0 - SPAACE_NUMBER_ENTRIES on success.
230  * If no SPAACE entry is available or the allocator can not reserve the required
231  * number of contiguous entries function returns ULONG_MAX indicating a failure.
232  *
233  */
234 static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
235 {
236         unsigned long spaace_addr;
237 
238         spaace_addr = gen_pool_alloc(spaace_pool, subwin_cnt * sizeof(struct paace));
239         if (!spaace_addr)
240                 return ULONG_MAX;
241 
242         return (spaace_addr - (unsigned long)spaact) / (sizeof(struct paace));
243 }
244 
245 /* Release the subwindows reserved for a particular LIODN */
246 void pamu_free_subwins(int liodn)
247 {
248         struct paace *ppaace;
249         u32 subwin_cnt, size;
250 
251         ppaace = pamu_get_ppaace(liodn);
252         if (!ppaace) {
253                 pr_debug("Invalid liodn entry\n");
254                 return;
255         }
256 
257         if (get_bf(ppaace->addr_bitfields, PPAACE_AF_MW)) {
258                 subwin_cnt = 1UL << (get_bf(ppaace->impl_attr, PAACE_IA_WCE) + 1);
259                 size = (subwin_cnt - 1) * sizeof(struct paace);
260                 gen_pool_free(spaace_pool, (unsigned long)&spaact[ppaace->fspi], size);
261                 set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
262         }
263 }
264 
265 /*
266  * Function used for updating stash destination for the coressponding
267  * LIODN.
268  */
269 int  pamu_update_paace_stash(int liodn, u32 subwin, u32 value)
270 {
271         struct paace *paace;
272 
273         paace = pamu_get_ppaace(liodn);
274         if (!paace) {
275                 pr_debug("Invalid liodn entry\n");
276                 return -ENOENT;
277         }
278         if (subwin) {
279                 paace = pamu_get_spaace(paace, subwin - 1);
280                 if (!paace)
281                         return -ENOENT;
282         }
283         set_bf(paace->impl_attr, PAACE_IA_CID, value);
284 
285         mb();
286 
287         return 0;
288 }
289 
290 /* Disable a subwindow corresponding to the LIODN */
291 int pamu_disable_spaace(int liodn, u32 subwin)
292 {
293         struct paace *paace;
294 
295         paace = pamu_get_ppaace(liodn);
296         if (!paace) {
297                 pr_debug("Invalid liodn entry\n");
298                 return -ENOENT;
299         }
300         if (subwin) {
301                 paace = pamu_get_spaace(paace, subwin - 1);
302                 if (!paace)
303                         return -ENOENT;
304                 set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
305         } else {
306                 set_bf(paace->addr_bitfields, PAACE_AF_AP,
307                        PAACE_AP_PERMS_DENIED);
308         }
309 
310         mb();
311 
312         return 0;
313 }
314 
315 /**
316  * pamu_config_paace() - Sets up PPAACE entry for specified liodn
317  *
318  * @liodn: Logical IO device number
319  * @win_addr: starting address of DSA window
320  * @win-size: size of DSA window
321  * @omi: Operation mapping index -- if ~omi == 0 then omi not defined
322  * @rpn: real (true physical) page number
323  * @stashid: cache stash id for associated cpu -- if ~stashid == 0 then
324  *           stashid not defined
325  * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
326  *           snoopid not defined
327  * @subwin_cnt: number of sub-windows
328  * @prot: window permissions
329  *
330  * Returns 0 upon success else error code < 0 returned
331  */
332 int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
333                        u32 omi, unsigned long rpn, u32 snoopid, u32 stashid,
334                        u32 subwin_cnt, int prot)
335 {
336         struct paace *ppaace;
337         unsigned long fspi;
338 
339         if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) {
340                 pr_debug("window size too small or not a power of two %pa\n",
341                          &win_size);
342                 return -EINVAL;
343         }
344 
345         if (win_addr & (win_size - 1)) {
346                 pr_debug("window address is not aligned with window size\n");
347                 return -EINVAL;
348         }
349 
350         ppaace = pamu_get_ppaace(liodn);
351         if (!ppaace)
352                 return -ENOENT;
353 
354         /* window size is 2^(WSE+1) bytes */
355         set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
356                map_addrspace_size_to_wse(win_size));
357 
358         pamu_init_ppaace(ppaace);
359 
360         ppaace->wbah = win_addr >> (PAMU_PAGE_SHIFT + 20);
361         set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
362                (win_addr >> PAMU_PAGE_SHIFT));
363 
364         /* set up operation mapping if it's configured */
365         if (omi < OME_NUMBER_ENTRIES) {
366                 set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
367                 ppaace->op_encode.index_ot.omi = omi;
368         } else if (~omi != 0) {
369                 pr_debug("bad operation mapping index: %d\n", omi);
370                 return -EINVAL;
371         }
372 
373         /* configure stash id */
374         if (~stashid != 0)
375                 set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
376 
377         /* configure snoop id */
378         if (~snoopid != 0)
379                 ppaace->domain_attr.to_host.snpid = snoopid;
380 
381         if (subwin_cnt) {
382                 /* The first entry is in the primary PAACE instead */
383                 fspi = pamu_get_fspi_and_allocate(subwin_cnt - 1);
384                 if (fspi == ULONG_MAX) {
385                         pr_debug("spaace indexes exhausted\n");
386                         return -EINVAL;
387                 }
388 
389                 /* window count is 2^(WCE+1) bytes */
390                 set_bf(ppaace->impl_attr, PAACE_IA_WCE,
391                        map_subwindow_cnt_to_wce(subwin_cnt));
392                 set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
393                 ppaace->fspi = fspi;
394         } else {
395                 set_bf(ppaace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
396                 ppaace->twbah = rpn >> 20;
397                 set_bf(ppaace->win_bitfields, PAACE_WIN_TWBAL, rpn);
398                 set_bf(ppaace->addr_bitfields, PAACE_AF_AP, prot);
399                 set_bf(ppaace->impl_attr, PAACE_IA_WCE, 0);
400                 set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
401         }
402         mb();
403 
404         return 0;
405 }
406 
407 /**
408  * pamu_config_spaace() - Sets up SPAACE entry for specified subwindow
409  *
410  * @liodn:  Logical IO device number
411  * @subwin_cnt:  number of sub-windows associated with dma-window
412  * @subwin: subwindow index
413  * @subwin_size: size of subwindow
414  * @omi: Operation mapping index
415  * @rpn: real (true physical) page number
416  * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
417  *                        snoopid not defined
418  * @stashid: cache stash id for associated cpu
419  * @enable: enable/disable subwindow after reconfiguration
420  * @prot: sub window permissions
421  *
422  * Returns 0 upon success else error code < 0 returned
423  */
424 int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin,
425                        phys_addr_t subwin_size, u32 omi, unsigned long rpn,
426                        u32 snoopid, u32 stashid, int enable, int prot)
427 {
428         struct paace *paace;
429 
430         /* setup sub-windows */
431         if (!subwin_cnt) {
432                 pr_debug("Invalid subwindow count\n");
433                 return -EINVAL;
434         }
435 
436         paace = pamu_get_ppaace(liodn);
437         if (subwin > 0 && subwin < subwin_cnt && paace) {
438                 paace = pamu_get_spaace(paace, subwin - 1);
439 
440                 if (paace && !(paace->addr_bitfields & PAACE_V_VALID)) {
441                         pamu_init_spaace(paace);
442                         set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
443                 }
444         }
445 
446         if (!paace) {
447                 pr_debug("Invalid liodn entry\n");
448                 return -ENOENT;
449         }
450 
451         if ((subwin_size & (subwin_size - 1)) || subwin_size < PAMU_PAGE_SIZE) {
452                 pr_debug("subwindow size out of range, or not a power of 2\n");
453                 return -EINVAL;
454         }
455 
456         if (rpn == ULONG_MAX) {
457                 pr_debug("real page number out of range\n");
458                 return -EINVAL;
459         }
460 
461         /* window size is 2^(WSE+1) bytes */
462         set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
463                map_addrspace_size_to_wse(subwin_size));
464 
465         set_bf(paace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
466         paace->twbah = rpn >> 20;
467         set_bf(paace->win_bitfields, PAACE_WIN_TWBAL, rpn);
468         set_bf(paace->addr_bitfields, PAACE_AF_AP, prot);
469 
470         /* configure snoop id */
471         if (~snoopid != 0)
472                 paace->domain_attr.to_host.snpid = snoopid;
473 
474         /* set up operation mapping if it's configured */
475         if (omi < OME_NUMBER_ENTRIES) {
476                 set_bf(paace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
477                 paace->op_encode.index_ot.omi = omi;
478         } else if (~omi != 0) {
479                 pr_debug("bad operation mapping index: %d\n", omi);
480                 return -EINVAL;
481         }
482 
483         if (~stashid != 0)
484                 set_bf(paace->impl_attr, PAACE_IA_CID, stashid);
485 
486         smp_wmb();
487 
488         if (enable)
489                 set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID);
490 
491         mb();
492 
493         return 0;
494 }
495 
496 /**
497  * get_ome_index() - Returns the index in the operation mapping table
498  *                   for device.
499  * @*omi_index: pointer for storing the index value
500  *
501  */
502 void get_ome_index(u32 *omi_index, struct device *dev)
503 {
504         if (of_device_is_compatible(dev->of_node, "fsl,qman-portal"))
505                 *omi_index = OMI_QMAN;
506         if (of_device_is_compatible(dev->of_node, "fsl,qman"))
507                 *omi_index = OMI_QMAN_PRIV;
508 }
509 
510 /**
511  * get_stash_id - Returns stash destination id corresponding to a
512  *                cache type and vcpu.
513  * @stash_dest_hint: L1, L2 or L3
514  * @vcpu: vpcu target for a particular cache type.
515  *
516  * Returs stash on success or ~(u32)0 on failure.
517  *
518  */
519 u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
520 {
521         const u32 *prop;
522         struct device_node *node;
523         u32 cache_level;
524         int len, found = 0;
525         int i;
526 
527         /* Fastpath, exit early if L3/CPC cache is target for stashing */
528         if (stash_dest_hint == PAMU_ATTR_CACHE_L3) {
529                 node = of_find_matching_node(NULL, l3_device_ids);
530                 if (node) {
531                         prop = of_get_property(node, "cache-stash-id", NULL);
532                         if (!prop) {
533                                 pr_debug("missing cache-stash-id at %s\n",
534                                          node->full_name);
535                                 of_node_put(node);
536                                 return ~(u32)0;
537                         }
538                         of_node_put(node);
539                         return be32_to_cpup(prop);
540                 }
541                 return ~(u32)0;
542         }
543 
544         for_each_node_by_type(node, "cpu") {
545                 prop = of_get_property(node, "reg", &len);
546                 for (i = 0; i < len / sizeof(u32); i++) {
547                         if (be32_to_cpup(&prop[i]) == vcpu) {
548                                 found = 1;
549                                 goto found_cpu_node;
550                         }
551                 }
552         }
553 found_cpu_node:
554 
555         /* find the hwnode that represents the cache */
556         for (cache_level = PAMU_ATTR_CACHE_L1; (cache_level < PAMU_ATTR_CACHE_L3) && found; cache_level++) {
557                 if (stash_dest_hint == cache_level) {
558                         prop = of_get_property(node, "cache-stash-id", NULL);
559                         if (!prop) {
560                                 pr_debug("missing cache-stash-id at %s\n",
561                                          node->full_name);
562                                 of_node_put(node);
563                                 return ~(u32)0;
564                         }
565                         of_node_put(node);
566                         return be32_to_cpup(prop);
567                 }
568 
569                 prop = of_get_property(node, "next-level-cache", NULL);
570                 if (!prop) {
571                         pr_debug("can't find next-level-cache at %s\n",
572                                  node->full_name);
573                         of_node_put(node);
574                         return ~(u32)0;  /* can't traverse any further */
575                 }
576                 of_node_put(node);
577 
578                 /* advance to next node in cache hierarchy */
579                 node = of_find_node_by_phandle(*prop);
580                 if (!node) {
581                         pr_debug("Invalid node for cache hierarchy\n");
582                         return ~(u32)0;
583                 }
584         }
585 
586         pr_debug("stash dest not found for %d on vcpu %d\n",
587                  stash_dest_hint, vcpu);
588         return ~(u32)0;
589 }
590 
591 /* Identify if the PAACT table entry belongs to QMAN, BMAN or QMAN Portal */
592 #define QMAN_PAACE 1
593 #define QMAN_PORTAL_PAACE 2
594 #define BMAN_PAACE 3
595 
596 /**
597  * Setup operation mapping and stash destinations for QMAN and QMAN portal.
598  * Memory accesses to QMAN and BMAN private memory need not be coherent, so
599  * clear the PAACE entry coherency attribute for them.
600  */
601 static void setup_qbman_paace(struct paace *ppaace, int  paace_type)
602 {
603         switch (paace_type) {
604         case QMAN_PAACE:
605                 set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
606                 ppaace->op_encode.index_ot.omi = OMI_QMAN_PRIV;
607                 /* setup QMAN Private data stashing for the L3 cache */
608                 set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));
609                 set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
610                        0);
611                 break;
612         case QMAN_PORTAL_PAACE:
613                 set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
614                 ppaace->op_encode.index_ot.omi = OMI_QMAN;
615                 /* Set DQRR and Frame stashing for the L3 cache */
616                 set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));
617                 break;
618         case BMAN_PAACE:
619                 set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
620                        0);
621                 break;
622         }
623 }
624 
625 /**
626  * Setup the operation mapping table for various devices. This is a static
627  * table where each table index corresponds to a particular device. PAMU uses
628  * this table to translate device transaction to appropriate corenet
629  * transaction.
630  */
631 static void setup_omt(struct ome *omt)
632 {
633         struct ome *ome;
634 
635         /* Configure OMI_QMAN */
636         ome = &omt[OMI_QMAN];
637 
638         ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READ;
639         ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
640         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
641         ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO;
642 
643         ome->moe[IOE_DIRECT0_IDX] = EOE_VALID | EOE_LDEC;
644         ome->moe[IOE_DIRECT1_IDX] = EOE_VALID | EOE_LDECPE;
645 
646         /* Configure OMI_FMAN */
647         ome = &omt[OMI_FMAN];
648         ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READI;
649         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
650 
651         /* Configure OMI_QMAN private */
652         ome = &omt[OMI_QMAN_PRIV];
653         ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READ;
654         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
655         ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
656         ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
657 
658         /* Configure OMI_CAAM */
659         ome = &omt[OMI_CAAM];
660         ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READI;
661         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
662 }
663 
664 /*
665  * Get the maximum number of PAACT table entries
666  * and subwindows supported by PAMU
667  */
668 static void get_pamu_cap_values(unsigned long pamu_reg_base)
669 {
670         u32 pc_val;
671 
672         pc_val = in_be32((u32 *)(pamu_reg_base + PAMU_PC3));
673         /* Maximum number of subwindows per liodn */
674         max_subwindow_count = 1 << (1 + PAMU_PC3_MWCE(pc_val));
675 }
676 
677 /* Setup PAMU registers pointing to PAACT, SPAACT and OMT */
678 static int setup_one_pamu(unsigned long pamu_reg_base, unsigned long pamu_reg_size,
679                           phys_addr_t ppaact_phys, phys_addr_t spaact_phys,
680                           phys_addr_t omt_phys)
681 {
682         u32 *pc;
683         struct pamu_mmap_regs *pamu_regs;
684 
685         pc = (u32 *) (pamu_reg_base + PAMU_PC);
686</