Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/iommu/fsl_pamu.c

  1 /*
  2  * This program is free software; you can redistribute it and/or modify
  3  * it under the terms of the GNU General Public License, version 2, as
  4  * published by the Free Software Foundation.
  5  *
  6  * This program is distributed in the hope that it will be useful,
  7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  9  * GNU General Public License for more details.
 10  *
 11  * You should have received a copy of the GNU General Public License
 12  * along with this program; if not, write to the Free Software
 13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 14  *
 15  * Copyright (C) 2013 Freescale Semiconductor, Inc.
 16  *
 17  */
 18 
 19 #define pr_fmt(fmt)    "fsl-pamu: %s: " fmt, __func__
 20 
 21 #include "fsl_pamu.h"
 22 
 23 #include <linux/interrupt.h>
 24 #include <linux/genalloc.h>
 25 
 26 #include <asm/mpc85xx.h>
 27 #include <asm/fsl_guts.h>
 28 
 29 /* define indexes for each operation mapping scenario */
 30 #define OMI_QMAN        0x00
 31 #define OMI_FMAN        0x01
 32 #define OMI_QMAN_PRIV   0x02
 33 #define OMI_CAAM        0x03
 34 
 35 #define make64(high, low) (((u64)(high) << 32) | (low))
 36 
 37 struct pamu_isr_data {
 38         void __iomem *pamu_reg_base;    /* Base address of PAMU regs */
 39         unsigned int count;             /* The number of PAMUs */
 40 };
 41 
 42 static struct paace *ppaact;
 43 static struct paace *spaact;
 44 static struct ome *omt __initdata;
 45 
 46 /*
 47  * Table for matching compatible strings, for device tree
 48  * guts node, for QorIQ SOCs.
 49  * "fsl,qoriq-device-config-2.0" corresponds to T4 & B4
 50  * SOCs. For the older SOCs "fsl,qoriq-device-config-1.0"
 51  * string would be used.
 52  */
 53 static const struct of_device_id guts_device_ids[] __initconst = {
 54         { .compatible = "fsl,qoriq-device-config-1.0", },
 55         { .compatible = "fsl,qoriq-device-config-2.0", },
 56         {}
 57 };
 58 
 59 /*
 60  * Table for matching compatible strings, for device tree
 61  * L3 cache controller node.
 62  * "fsl,t4240-l3-cache-controller" corresponds to T4,
 63  * "fsl,b4860-l3-cache-controller" corresponds to B4 &
 64  * "fsl,p4080-l3-cache-controller" corresponds to other,
 65  * SOCs.
 66  */
 67 static const struct of_device_id l3_device_ids[] = {
 68         { .compatible = "fsl,t4240-l3-cache-controller", },
 69         { .compatible = "fsl,b4860-l3-cache-controller", },
 70         { .compatible = "fsl,p4080-l3-cache-controller", },
 71         {}
 72 };
 73 
 74 /* maximum subwindows permitted per liodn */
 75 static u32 max_subwindow_count;
 76 
 77 /* Pool for fspi allocation */
 78 static struct gen_pool *spaace_pool;
 79 
 80 /**
 81  * pamu_get_max_subwin_cnt() - Return the maximum supported
 82  * subwindow count per liodn.
 83  *
 84  */
 85 u32 pamu_get_max_subwin_cnt(void)
 86 {
 87         return max_subwindow_count;
 88 }
 89 
 90 /**
 91  * pamu_get_ppaace() - Return the primary PACCE
 92  * @liodn: liodn PAACT index for desired PAACE
 93  *
 94  * Returns the ppace pointer upon success else return
 95  * null.
 96  */
 97 static struct paace *pamu_get_ppaace(int liodn)
 98 {
 99         if (!ppaact || liodn >= PAACE_NUMBER_ENTRIES) {
100                 pr_debug("PPAACT doesn't exist\n");
101                 return NULL;
102         }
103 
104         return &ppaact[liodn];
105 }
106 
107 /**
108  * pamu_enable_liodn() - Set valid bit of PACCE
109  * @liodn: liodn PAACT index for desired PAACE
110  *
111  * Returns 0 upon success else error code < 0 returned
112  */
113 int pamu_enable_liodn(int liodn)
114 {
115         struct paace *ppaace;
116 
117         ppaace = pamu_get_ppaace(liodn);
118         if (!ppaace) {
119                 pr_debug("Invalid primary paace entry\n");
120                 return -ENOENT;
121         }
122 
123         if (!get_bf(ppaace->addr_bitfields, PPAACE_AF_WSE)) {
124                 pr_debug("liodn %d not configured\n", liodn);
125                 return -EINVAL;
126         }
127 
128         /* Ensure that all other stores to the ppaace complete first */
129         mb();
130 
131         set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID);
132         mb();
133 
134         return 0;
135 }
136 
137 /**
138  * pamu_disable_liodn() - Clears valid bit of PACCE
139  * @liodn: liodn PAACT index for desired PAACE
140  *
141  * Returns 0 upon success else error code < 0 returned
142  */
143 int pamu_disable_liodn(int liodn)
144 {
145         struct paace *ppaace;
146 
147         ppaace = pamu_get_ppaace(liodn);
148         if (!ppaace) {
149                 pr_debug("Invalid primary paace entry\n");
150                 return -ENOENT;
151         }
152 
153         set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
154         mb();
155 
156         return 0;
157 }
158 
159 /* Derive the window size encoding for a particular PAACE entry */
160 static unsigned int map_addrspace_size_to_wse(phys_addr_t addrspace_size)
161 {
162         /* Bug if not a power of 2 */
163         BUG_ON(addrspace_size & (addrspace_size - 1));
164 
165         /* window size is 2^(WSE+1) bytes */
166         return fls64(addrspace_size) - 2;
167 }
168 
169 /* Derive the PAACE window count encoding for the subwindow count */
170 static unsigned int map_subwindow_cnt_to_wce(u32 subwindow_cnt)
171 {
172         /* window count is 2^(WCE+1) bytes */
173         return __ffs(subwindow_cnt) - 1;
174 }
175 
176 /*
177  * Set the PAACE type as primary and set the coherency required domain
178  * attribute
179  */
180 static void pamu_init_ppaace(struct paace *ppaace)
181 {
182         set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
183 
184         set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
185                PAACE_M_COHERENCE_REQ);
186 }
187 
188 /*
189  * Set the PAACE type as secondary and set the coherency required domain
190  * attribute.
191  */
192 static void pamu_init_spaace(struct paace *spaace)
193 {
194         set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
195         set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
196                PAACE_M_COHERENCE_REQ);
197 }
198 
199 /*
200  * Return the spaace (corresponding to the secondary window index)
201  * for a particular ppaace.
202  */
203 static struct paace *pamu_get_spaace(struct paace *paace, u32 wnum)
204 {
205         u32 subwin_cnt;
206         struct paace *spaace = NULL;
207 
208         subwin_cnt = 1UL << (get_bf(paace->impl_attr, PAACE_IA_WCE) + 1);
209 
210         if (wnum < subwin_cnt)
211                 spaace = &spaact[paace->fspi + wnum];
212         else
213                 pr_debug("secondary paace out of bounds\n");
214 
215         return spaace;
216 }
217 
218 /**
219  * pamu_get_fspi_and_allocate() - Allocates fspi index and reserves subwindows
220  *                                required for primary PAACE in the secondary
221  *                                PAACE table.
222  * @subwin_cnt: Number of subwindows to be reserved.
223  *
224  * A PPAACE entry may have a number of associated subwindows. A subwindow
225  * corresponds to a SPAACE entry in the SPAACT table. Each PAACE entry stores
226  * the index (fspi) of the first SPAACE entry in the SPAACT table. This
227  * function returns the index of the first SPAACE entry. The remaining
228  * SPAACE entries are reserved contiguously from that index.
229  *
230  * Returns a valid fspi index in the range of 0 - SPAACE_NUMBER_ENTRIES on success.
231  * If no SPAACE entry is available or the allocator can not reserve the required
232  * number of contiguous entries function returns ULONG_MAX indicating a failure.
233  *
234  */
235 static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
236 {
237         unsigned long spaace_addr;
238 
239         spaace_addr = gen_pool_alloc(spaace_pool, subwin_cnt * sizeof(struct paace));
240         if (!spaace_addr)
241                 return ULONG_MAX;
242 
243         return (spaace_addr - (unsigned long)spaact) / (sizeof(struct paace));
244 }
245 
246 /* Release the subwindows reserved for a particular LIODN */
247 void pamu_free_subwins(int liodn)
248 {
249         struct paace *ppaace;
250         u32 subwin_cnt, size;
251 
252         ppaace = pamu_get_ppaace(liodn);
253         if (!ppaace) {
254                 pr_debug("Invalid liodn entry\n");
255                 return;
256         }
257 
258         if (get_bf(ppaace->addr_bitfields, PPAACE_AF_MW)) {
259                 subwin_cnt = 1UL << (get_bf(ppaace->impl_attr, PAACE_IA_WCE) + 1);
260                 size = (subwin_cnt - 1) * sizeof(struct paace);
261                 gen_pool_free(spaace_pool, (unsigned long)&spaact[ppaace->fspi], size);
262                 set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
263         }
264 }
265 
266 /*
267  * Function used for updating stash destination for the coressponding
268  * LIODN.
269  */
270 int  pamu_update_paace_stash(int liodn, u32 subwin, u32 value)
271 {
272         struct paace *paace;
273 
274         paace = pamu_get_ppaace(liodn);
275         if (!paace) {
276                 pr_debug("Invalid liodn entry\n");
277                 return -ENOENT;
278         }
279         if (subwin) {
280                 paace = pamu_get_spaace(paace, subwin - 1);
281                 if (!paace)
282                         return -ENOENT;
283         }
284         set_bf(paace->impl_attr, PAACE_IA_CID, value);
285 
286         mb();
287 
288         return 0;
289 }
290 
291 /* Disable a subwindow corresponding to the LIODN */
292 int pamu_disable_spaace(int liodn, u32 subwin)
293 {
294         struct paace *paace;
295 
296         paace = pamu_get_ppaace(liodn);
297         if (!paace) {
298                 pr_debug("Invalid liodn entry\n");
299                 return -ENOENT;
300         }
301         if (subwin) {
302                 paace = pamu_get_spaace(paace, subwin - 1);
303                 if (!paace)
304                         return -ENOENT;
305                 set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
306         } else {
307                 set_bf(paace->addr_bitfields, PAACE_AF_AP,
308                        PAACE_AP_PERMS_DENIED);
309         }
310 
311         mb();
312 
313         return 0;
314 }
315 
316 /**
317  * pamu_config_paace() - Sets up PPAACE entry for specified liodn
318  *
319  * @liodn: Logical IO device number
320  * @win_addr: starting address of DSA window
321  * @win-size: size of DSA window
322  * @omi: Operation mapping index -- if ~omi == 0 then omi not defined
323  * @rpn: real (true physical) page number
324  * @stashid: cache stash id for associated cpu -- if ~stashid == 0 then
325  *           stashid not defined
326  * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
327  *           snoopid not defined
328  * @subwin_cnt: number of sub-windows
329  * @prot: window permissions
330  *
331  * Returns 0 upon success else error code < 0 returned
332  */
333 int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
334                        u32 omi, unsigned long rpn, u32 snoopid, u32 stashid,
335                        u32 subwin_cnt, int prot)
336 {
337         struct paace *ppaace;
338         unsigned long fspi;
339 
340         if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) {
341                 pr_debug("window size too small or not a power of two %pa\n",
342                          &win_size);
343                 return -EINVAL;
344         }
345 
346         if (win_addr & (win_size - 1)) {
347                 pr_debug("window address is not aligned with window size\n");
348                 return -EINVAL;
349         }
350 
351         ppaace = pamu_get_ppaace(liodn);
352         if (!ppaace)
353                 return -ENOENT;
354 
355         /* window size is 2^(WSE+1) bytes */
356         set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
357                map_addrspace_size_to_wse(win_size));
358 
359         pamu_init_ppaace(ppaace);
360 
361         ppaace->wbah = win_addr >> (PAMU_PAGE_SHIFT + 20);
362         set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
363                (win_addr >> PAMU_PAGE_SHIFT));
364 
365         /* set up operation mapping if it's configured */
366         if (omi < OME_NUMBER_ENTRIES) {
367                 set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
368                 ppaace->op_encode.index_ot.omi = omi;
369         } else if (~omi != 0) {
370                 pr_debug("bad operation mapping index: %d\n", omi);
371                 return -EINVAL;
372         }
373 
374         /* configure stash id */
375         if (~stashid != 0)
376                 set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
377 
378         /* configure snoop id */
379         if (~snoopid != 0)
380                 ppaace->domain_attr.to_host.snpid = snoopid;
381 
382         if (subwin_cnt) {
383                 /* The first entry is in the primary PAACE instead */
384                 fspi = pamu_get_fspi_and_allocate(subwin_cnt - 1);
385                 if (fspi == ULONG_MAX) {
386                         pr_debug("spaace indexes exhausted\n");
387                         return -EINVAL;
388                 }
389 
390                 /* window count is 2^(WCE+1) bytes */
391                 set_bf(ppaace->impl_attr, PAACE_IA_WCE,
392                        map_subwindow_cnt_to_wce(subwin_cnt));
393                 set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
394                 ppaace->fspi = fspi;
395         } else {
396                 set_bf(ppaace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
397                 ppaace->twbah = rpn >> 20;
398                 set_bf(ppaace->win_bitfields, PAACE_WIN_TWBAL, rpn);
399                 set_bf(ppaace->addr_bitfields, PAACE_AF_AP, prot);
400                 set_bf(ppaace->impl_attr, PAACE_IA_WCE, 0);
401                 set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
402         }
403         mb();
404 
405         return 0;
406 }
407 
408 /**
409  * pamu_config_spaace() - Sets up SPAACE entry for specified subwindow
410  *
411  * @liodn:  Logical IO device number
412  * @subwin_cnt:  number of sub-windows associated with dma-window
413  * @subwin: subwindow index
414  * @subwin_size: size of subwindow
415  * @omi: Operation mapping index
416  * @rpn: real (true physical) page number
417  * @snoopid: snoop id for hardware coherency -- if ~snoopid == 0 then
418  *                        snoopid not defined
419  * @stashid: cache stash id for associated cpu
420  * @enable: enable/disable subwindow after reconfiguration
421  * @prot: sub window permissions
422  *
423  * Returns 0 upon success else error code < 0 returned
424  */
425 int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin,
426                        phys_addr_t subwin_size, u32 omi, unsigned long rpn,
427                        u32 snoopid, u32 stashid, int enable, int prot)
428 {
429         struct paace *paace;
430 
431         /* setup sub-windows */
432         if (!subwin_cnt) {
433                 pr_debug("Invalid subwindow count\n");
434                 return -EINVAL;
435         }
436 
437         paace = pamu_get_ppaace(liodn);
438         if (subwin > 0 && subwin < subwin_cnt && paace) {
439                 paace = pamu_get_spaace(paace, subwin - 1);
440 
441                 if (paace && !(paace->addr_bitfields & PAACE_V_VALID)) {
442                         pamu_init_spaace(paace);
443                         set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
444                 }
445         }
446 
447         if (!paace) {
448                 pr_debug("Invalid liodn entry\n");
449                 return -ENOENT;
450         }
451 
452         if ((subwin_size & (subwin_size - 1)) || subwin_size < PAMU_PAGE_SIZE) {
453                 pr_debug("subwindow size out of range, or not a power of 2\n");
454                 return -EINVAL;
455         }
456 
457         if (rpn == ULONG_MAX) {
458                 pr_debug("real page number out of range\n");
459                 return -EINVAL;
460         }
461 
462         /* window size is 2^(WSE+1) bytes */
463         set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
464                map_addrspace_size_to_wse(subwin_size));
465 
466         set_bf(paace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
467         paace->twbah = rpn >> 20;
468         set_bf(paace->win_bitfields, PAACE_WIN_TWBAL, rpn);
469         set_bf(paace->addr_bitfields, PAACE_AF_AP, prot);
470 
471         /* configure snoop id */
472         if (~snoopid != 0)
473                 paace->domain_attr.to_host.snpid = snoopid;
474 
475         /* set up operation mapping if it's configured */
476         if (omi < OME_NUMBER_ENTRIES) {
477                 set_bf(paace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
478                 paace->op_encode.index_ot.omi = omi;
479         } else if (~omi != 0) {
480                 pr_debug("bad operation mapping index: %d\n", omi);
481                 return -EINVAL;
482         }
483 
484         if (~stashid != 0)
485                 set_bf(paace->impl_attr, PAACE_IA_CID, stashid);
486 
487         smp_wmb();
488 
489         if (enable)
490                 set_bf(paace->addr_bitfields, PAACE_AF_V, PAACE_V_VALID);
491 
492         mb();
493 
494         return 0;
495 }
496 
497 /**
498  * get_ome_index() - Returns the index in the operation mapping table
499  *                   for device.
500  * @*omi_index: pointer for storing the index value
501  *
502  */
503 void get_ome_index(u32 *omi_index, struct device *dev)
504 {
505         if (of_device_is_compatible(dev->of_node, "fsl,qman-portal"))
506                 *omi_index = OMI_QMAN;
507         if (of_device_is_compatible(dev->of_node, "fsl,qman"))
508                 *omi_index = OMI_QMAN_PRIV;
509 }
510 
511 /**
512  * get_stash_id - Returns stash destination id corresponding to a
513  *                cache type and vcpu.
514  * @stash_dest_hint: L1, L2 or L3
515  * @vcpu: vpcu target for a particular cache type.
516  *
517  * Returs stash on success or ~(u32)0 on failure.
518  *
519  */
520 u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
521 {
522         const u32 *prop;
523         struct device_node *node;
524         u32 cache_level;
525         int len, found = 0;
526         int i;
527 
528         /* Fastpath, exit early if L3/CPC cache is target for stashing */
529         if (stash_dest_hint == PAMU_ATTR_CACHE_L3) {
530                 node = of_find_matching_node(NULL, l3_device_ids);
531                 if (node) {
532                         prop = of_get_property(node, "cache-stash-id", NULL);
533                         if (!prop) {
534                                 pr_debug("missing cache-stash-id at %s\n",
535                                          node->full_name);
536                                 of_node_put(node);
537                                 return ~(u32)0;
538                         }
539                         of_node_put(node);
540                         return be32_to_cpup(prop);
541                 }
542                 return ~(u32)0;
543         }
544 
545         for_each_node_by_type(node, "cpu") {
546                 prop = of_get_property(node, "reg", &len);
547                 for (i = 0; i < len / sizeof(u32); i++) {
548                         if (be32_to_cpup(&prop[i]) == vcpu) {
549                                 found = 1;
550                                 goto found_cpu_node;
551                         }
552                 }
553         }
554 found_cpu_node:
555 
556         /* find the hwnode that represents the cache */
557         for (cache_level = PAMU_ATTR_CACHE_L1; (cache_level < PAMU_ATTR_CACHE_L3) && found; cache_level++) {
558                 if (stash_dest_hint == cache_level) {
559                         prop = of_get_property(node, "cache-stash-id", NULL);
560                         if (!prop) {
561                                 pr_debug("missing cache-stash-id at %s\n",
562                                          node->full_name);
563                                 of_node_put(node);
564                                 return ~(u32)0;
565                         }
566                         of_node_put(node);
567                         return be32_to_cpup(prop);
568                 }
569 
570                 prop = of_get_property(node, "next-level-cache", NULL);
571                 if (!prop) {
572                         pr_debug("can't find next-level-cache at %s\n",
573                                  node->full_name);
574                         of_node_put(node);
575                         return ~(u32)0;  /* can't traverse any further */
576                 }
577                 of_node_put(node);
578 
579                 /* advance to next node in cache hierarchy */
580                 node = of_find_node_by_phandle(*prop);
581                 if (!node) {
582                         pr_debug("Invalid node for cache hierarchy\n");
583                         return ~(u32)0;
584                 }
585         }
586 
587         pr_debug("stash dest not found for %d on vcpu %d\n",
588                  stash_dest_hint, vcpu);
589         return ~(u32)0;
590 }
591 
592 /* Identify if the PAACT table entry belongs to QMAN, BMAN or QMAN Portal */
593 #define QMAN_PAACE 1
594 #define QMAN_PORTAL_PAACE 2
595 #define BMAN_PAACE 3
596 
597 /**
598  * Setup operation mapping and stash destinations for QMAN and QMAN portal.
599  * Memory accesses to QMAN and BMAN private memory need not be coherent, so
600  * clear the PAACE entry coherency attribute for them.
601  */
602 static void __init setup_qbman_paace(struct paace *ppaace, int  paace_type)
603 {
604         switch (paace_type) {
605         case QMAN_PAACE:
606                 set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
607                 ppaace->op_encode.index_ot.omi = OMI_QMAN_PRIV;
608                 /* setup QMAN Private data stashing for the L3 cache */
609                 set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));
610                 set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
611                        0);
612                 break;
613         case QMAN_PORTAL_PAACE:
614                 set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
615                 ppaace->op_encode.index_ot.omi = OMI_QMAN;
616                 /* Set DQRR and Frame stashing for the L3 cache */
617                 set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(PAMU_ATTR_CACHE_L3, 0));
618                 break;
619         case BMAN_PAACE:
620                 set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
621                        0);
622                 break;
623         }
624 }
625 
626 /**
627  * Setup the operation mapping table for various devices. This is a static
628  * table where each table index corresponds to a particular device. PAMU uses
629  * this table to translate device transaction to appropriate corenet
630  * transaction.
631  */
632 static void __init setup_omt(struct ome *omt)
633 {
634         struct ome *ome;
635 
636         /* Configure OMI_QMAN */
637         ome = &omt[OMI_QMAN];
638 
639         ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READ;
640         ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
641         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
642         ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO;
643 
644         ome->moe[IOE_DIRECT0_IDX] = EOE_VALID | EOE_LDEC;
645         ome->moe[IOE_DIRECT1_IDX] = EOE_VALID | EOE_LDECPE;
646 
647         /* Configure OMI_FMAN */
648         ome = &omt[OMI_FMAN];
649         ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READI;
650         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
651 
652         /* Configure OMI_QMAN private */
653         ome = &omt[OMI_QMAN_PRIV];
654         ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READ;
655         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
656         ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
657         ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
658 
659         /* Configure OMI_CAAM */
660         ome = &omt[OMI_CAAM];
661         ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READI;
662         ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
663 }
664 
665 /*
666  * Get the maximum number of PAACT table entries
667  * and subwindows supported by PAMU
668  */
669 static void __init get_pamu_cap_values(unsigned long pamu_reg_base)
670 {
671         u32 pc_val;
672 
673         pc_val = in_be32((u32 *)(pamu_reg_base + PAMU_PC3));
674         /* Maximum number of subwindows per liodn */
675         max_subwindow_count = 1 << (1 + PAMU_PC3_MWCE(pc_val));
676 }
677 
678 /* Setup PAMU registers pointing to PAACT, SPAACT and OMT */
679 static int __init setup_one_pamu(unsigned long pamu_reg_base, unsigned long pamu_reg_size,
680                                  phys_addr_t ppaact_phys, phys_addr_t spaact_phys,
681                                  phys_addr_t omt_phys)
682 {
683         u32 *pc;
684         struct pamu_mmap_regs *pamu_regs;
685 
686         pc = (u32 *) (pamu_reg_base + PAMU_PC);
687         pamu_regs = (struct pamu_mmap_regs *)
688                 (pamu_reg_base + PAMU_MMAP_REGS_BASE);
689 
690         /* set up pointers to corenet control blocks */
691 
692         out_be32(&pamu_regs->ppbah, upper_32_bits(ppaact_phys));
693         out_be32(&pamu_regs->ppbal, lower_32_bits(ppaact_phys));
694         ppaact_phys = ppaact_phys + PAACT_SIZE;
695         out_be32(&pamu_regs->pplah, upper_32_bits(ppaact_phys));
696         out_be32(&pamu_regs->pplal, lower_32_bits(ppaact_phys));
697 
698         out_be32(&pamu_regs->spbah, upper_32_bits(spaact_phys));
699         out_be32(&pamu_regs->spbal, lower_32_bits(spaact_phys));
700         spaact_phys = spaact_phys + SPAACT_SIZE;
701         out_be32(&pamu_regs->splah, upper_32_bits(spaact_phys));
702         out_be32(&pamu_regs->splal, lower_32_bits(spaact_phys));
703 
704         out_be32(&pamu_regs->obah, upper_32_bits(omt_phys));
705         out_be32(&pamu_regs->obal, lower_32_bits(omt_phys));
706         omt_phys = omt_phys + OMT_SIZE;
707         out_be32(&pamu_regs->olah, upper_32_bits(omt_phys));
708         out_be32(&pamu_regs->olal, lower_32_bits(omt_phys));
709 
710         /*
711          * set PAMU enable bit,
712          * allow ppaact & omt to be cached
713          * & enable PAMU access violation interrupts.
714          */
715 
716         out_be32((u32 *)(pamu_reg_base + PAMU_PICS),
717                  PAMU_ACCESS_VIOLATION_ENABLE);
718         out_be32(pc, PAMU_PC_PE | PAMU_PC_OCE | PAMU_PC_SPCC | PAMU_PC_PPCC);
719         return 0;
720 }
721 
722 /* Enable all device LIODNS */
723 static void __init setup_liodns(void)
724 {
725         int i, len;
726         struct paace *ppaace;
727         struct device_node *node = NULL;
728         const u32 *prop;
729 
730         for_each_node_with_property(node, "fsl,liodn") {
731                 prop = of_get_property(node, "fsl,liodn", &len);
732                 for (i = 0; i < len / sizeof(u32); i++) {
733                         int liodn;
734 
735                         liodn = be32_to_cpup(&prop[i]);
736                         if (liodn >= PAACE_NUMBER_ENTRIES) {
737                                 pr_debug("Invalid LIODN value %d\n", liodn);
738                                 continue;
739                         }
740                         ppaace = pamu_get_ppaace(liodn);
741                         pamu_init_ppaace(ppaace);
742                         /* window size is 2^(WSE+1) bytes */
743                         set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, 35);
744                         ppaace->wbah = 0;
745                         set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);
746                         set_bf(ppaace->impl_attr, PAACE_IA_ATM,
747                                PAACE_ATM_NO_XLATE);
748                         set_bf(ppaace->addr_bitfields, PAACE_AF_AP,
749                                PAACE_AP_PERMS_ALL);
750                         if (of_device_is_compatible(node, "fsl,qman-portal"))
751                                 setup_qbman_paace(ppaace, QMAN_PORTAL_PAACE);
752                         if (of_device_is_compatible(node, "fsl,qman"))
753                                 setup_qbman_paace(ppaace, QMAN_PAACE);
754                         if (of_device_is_compatible(node, "fsl,bman"))
755                                 setup_qbman_paace(ppaace, BMAN_PAACE);
756                         mb();
757                         pamu_enable_liodn(liodn);
758                 }
759         }
760 }
761 
762 static irqreturn_t pamu_av_isr(int irq, void *arg)
763 {
764         struct pamu_isr_data *data = arg;
765         phys_addr_t phys;
766         unsigned int i, j, ret;
767 
768         pr_emerg("access violation interrupt\n");
769 
770         for (i = 0; i < data->count; i++) {
771                 void __iomem *p = data->pamu_reg_base + i * PAMU_OFFSET;
772                 u32 pics = in_be32(p + PAMU_PICS);
773 
774                 if (pics & PAMU_ACCESS_VIOLATION_STAT) {
775                         u32 avs1 = in_be32(p + PAMU_AVS1);
776                         struct paace *paace;
777 
778                         pr_emerg("POES1=%08x\n", in_be32(p + PAMU_POES1));
779                         pr_emerg("POES2=%08x\n", in_be32(p + PAMU_POES2));
780                         pr_emerg("AVS1=%08x\n", avs1);
781                         pr_emerg("AVS2=%08x\n", in_be32(p + PAMU_AVS2));
782                         pr_emerg("AVA=%016llx\n",
783                                  make64(in_be32(p + PAMU_AVAH),
784                                         in_be32(p + PAMU_AVAL)));
785                         pr_emerg("UDAD=%08x\n", in_be32(p + PAMU_UDAD));
786                         pr_emerg("POEA=%016llx\n",
787                                  make64(in_be32(p + PAMU_POEAH),
788                                         in_be32(p + PAMU_POEAL)));
789 
790                         phys = make64(in_be32(p + PAMU_POEAH),
791                                       in_be32(p + PAMU_POEAL));
792 
793                         /* Assume that POEA points to a PAACE */
794                         if (phys) {
795                                 u32 *paace = phys_to_virt(phys);
796 
797                                 /* Only the first four words are relevant */
798                                 for (j = 0; j < 4; j++)
799                                         pr_emerg("PAACE[%u]=%08x\n",
800                                                  j, in_be32(paace + j));
801                         }
802 
803                         /* clear access violation condition */
804                         out_be32(p + PAMU_AVS1, avs1 & PAMU_AV_MASK);
805                         paace = pamu_get_ppaace(avs1 >> PAMU_AVS1_LIODN_SHIFT);
806                         BUG_ON(!paace);
807                         /* check if we got a violation for a disabled LIODN */
808                         if (!get_bf(paace->addr_bitfields, PAACE_AF_V)) {
809                                 /*
810                                  * As per hardware erratum A-003638, access
811                                  * violation can be reported for a disabled
812                                  * LIODN. If we hit that condition, disable
813                                  * access violation reporting.
814                                  */
815                                 pics &= ~PAMU_ACCESS_VIOLATION_ENABLE;
816                         } else {
817                                 /* Disable the LIODN */
818                                 ret = pamu_disable_liodn(avs1 >> PAMU_AVS1_LIODN_SHIFT);
819                                 BUG_ON(ret);
820                                 pr_emerg("Disabling liodn %x\n",
821                                          avs1 >> PAMU_AVS1_LIODN_SHIFT);
822                         }
823                         out_be32((p + PAMU_PICS), pics);
824                 }
825         }
826 
827         return IRQ_HANDLED;
828 }
829 
830 #define LAWAR_EN                0x80000000
831 #define LAWAR_TARGET_MASK       0x0FF00000
832 #define LAWAR_TARGET_SHIFT      20
833 #define LAWAR_SIZE_MASK         0x0000003F
834 #define LAWAR_CSDID_MASK        0x000FF000
835 #define LAWAR_CSDID_SHIFT       12
836 
837 #define LAW_SIZE_4K             0xb
838 
839 struct ccsr_law {
840         u32     lawbarh;        /* LAWn base address high */
841         u32     lawbarl;        /* LAWn base address low */
842         u32     lawar;          /* LAWn attributes */
843         u32     reserved;
844 };
845 
846 /*
847  * Create a coherence subdomain for a given memory block.
848  */
849 static int __init create_csd(phys_addr_t phys, size_t size, u32 csd_port_id)
850 {
851         struct device_node *np;
852         const __be32 *iprop;
853         void __iomem *lac = NULL;       /* Local Access Control registers */
854         struct ccsr_law __iomem *law;
855         void __iomem *ccm = NULL;
856         u32 __iomem *csdids;
857         unsigned int i, num_laws, num_csds;
858         u32 law_target = 0;
859         u32 csd_id = 0;
860         int ret = 0;
861 
862         np = of_find_compatible_node(NULL, NULL, "fsl,corenet-law");
863         if (!np)
864                 return -ENODEV;
865 
866         iprop = of_get_property(np, "fsl,num-laws", NULL);
867         if (!iprop) {
868                 ret = -ENODEV;
869                 goto error;
870         }
871 
872         num_laws = be32_to_cpup(iprop);
873         if (!num_laws) {
874                 ret = -ENODEV;
875                 goto error;
876         }
877 
878         lac = of_iomap(np, 0);
879         if (!lac) {
880                 ret = -ENODEV;
881                 goto error;
882         }
883 
884         /* LAW registers are at offset 0xC00 */
885         law = lac + 0xC00;
886 
887         of_node_put(np);
888 
889         np = of_find_compatible_node(NULL, NULL, "fsl,corenet-cf");
890         if (!np) {
891                 ret = -ENODEV;
892                 goto error;
893         }
894 
895         iprop = of_get_property(np, "fsl,ccf-num-csdids", NULL);
896         if (!iprop) {
897                 ret = -ENODEV;
898                 goto error;
899         }
900 
901         num_csds = be32_to_cpup(iprop);
902         if (!num_csds) {
903                 ret = -ENODEV;
904                 goto error;
905         }
906 
907         ccm = of_iomap(np, 0);
908         if (!ccm) {
909                 ret = -ENOMEM;
910                 goto error;
911         }
912 
913         /* The undocumented CSDID registers are at offset 0x600 */
914         csdids = ccm + 0x600;
915 
916         of_node_put(np);
917         np = NULL;
918 
919         /* Find an unused coherence subdomain ID */
920         for (csd_id = 0; csd_id < num_csds; csd_id++) {
921                 if (!csdids[csd_id])
922                         break;
923         }
924 
925         /* Store the Port ID in the (undocumented) proper CIDMRxx register */
926         csdids[csd_id] = csd_port_id;
927 
928         /* Find the DDR LAW that maps to our buffer. */
929         for (i = 0; i < num_laws; i++) {
930                 if (law[i].lawar & LAWAR_EN) {
931                         phys_addr_t law_start, law_end;
932 
933                         law_start = make64(law[i].lawbarh, law[i].lawbarl);
934                         law_end = law_start +
935                                 (2ULL << (law[i].lawar & LAWAR_SIZE_MASK));
936 
937                         if (law_start <= phys && phys < law_end) {
938                                 law_target = law[i].lawar & LAWAR_TARGET_MASK;
939                                 break;
940                         }
941                 }
942         }
943 
944         if (i == 0 || i == num_laws) {
945                 /* This should never happen */
946                 ret = -ENOENT;
947                 goto error;
948         }
949 
950         /* Find a free LAW entry */
951         while (law[--i].lawar & LAWAR_EN) {
952                 if (i == 0) {
953                         /* No higher priority LAW slots available */
954                         ret = -ENOENT;
955                         goto error;
956                 }
957         }
958 
959         law[i].lawbarh = upper_32_bits(phys);
960         law[i].lawbarl = lower_32_bits(phys);
961         wmb();
962         law[i].lawar = LAWAR_EN | law_target | (csd_id << LAWAR_CSDID_SHIFT) |
963                 (LAW_SIZE_4K + get_order(size));
964         wmb();
965 
966 error:
967         if (ccm)
968                 iounmap(ccm);
969 
970         if (lac)
971                 iounmap(lac);
972 
973         if (np)
974                 of_node_put(np);
975 
976         return ret;
977 }
978 
979 /*
980  * Table of SVRs and the corresponding PORT_ID values. Port ID corresponds to a
981  * bit map of snoopers for a given range of memory mapped by a LAW.
982  *
983  * All future CoreNet-enabled SOCs will have this erratum(A-004510) fixed, so this
984  * table should never need to be updated.  SVRs are guaranteed to be unique, so
985  * there is no worry that a future SOC will inadvertently have one of these
986  * values.
987  */
988 static const struct {
989         u32 svr;
990         u32 port_id;
991 } port_id_map[] __initconst = {
992         {(SVR_P2040 << 8) | 0x10, 0xFF000000},  /* P2040 1.0 */
993         {(SVR_P2040 << 8) | 0x11, 0xFF000000},  /* P2040 1.1 */
994         {(SVR_P2041 << 8) | 0x10, 0xFF000000},  /* P2041 1.0 */
995         {(SVR_P2041 << 8) | 0x11, 0xFF000000},  /* P2041 1.1 */
996         {(SVR_P3041 << 8) | 0x10, 0xFF000000},  /* P3041 1.0 */
997         {(SVR_P3041 << 8) | 0x11, 0xFF000000},  /* P3041 1.1 */
998         {(SVR_P4040 << 8) | 0x20, 0xFFF80000},  /* P4040 2.0 */
999         {(SVR_P4080 << 8) | 0x20, 0xFFF80000},  /* P4080 2.0 */
1000         {(SVR_P5010 << 8) | 0x10, 0xFC000000},  /* P5010 1.0 */
1001         {(SVR_P5010 << 8) | 0x20, 0xFC000000},  /* P5010 2.0 */
1002         {(SVR_P5020 << 8) | 0x10, 0xFC000000},  /* P5020 1.0 */
1003         {(SVR_P5021 << 8) | 0x10, 0xFF800000},  /* P5021 1.0 */
1004         {(SVR_P5040 << 8) | 0x10, 0xFF800000},  /* P5040 1.0 */
1005 };
1006 
1007 #define SVR_SECURITY    0x80000 /* The Security (E) bit */
1008 
1009 static int __init fsl_pamu_probe(struct platform_device *pdev)
1010 {
1011         struct device *dev = &pdev->dev;
1012         void __iomem *pamu_regs = NULL;
1013         struct ccsr_guts __iomem *guts_regs = NULL;
1014         u32 pamubypenr, pamu_counter;
1015         unsigned long pamu_reg_off;
1016         unsigned long pamu_reg_base;
1017         struct pamu_isr_data *data = NULL;
1018         struct device_node *guts_node;
1019         u64 size;
1020         struct page *p;
1021         int ret = 0;
1022         int irq;
1023         phys_addr_t ppaact_phys;
1024         phys_addr_t spaact_phys;
1025         phys_addr_t omt_phys;
1026         size_t mem_size = 0;
1027         unsigned int order = 0;
1028         u32 csd_port_id = 0;
1029         unsigned i;
1030         /*
1031          * enumerate all PAMUs and allocate and setup PAMU tables
1032          * for each of them,
1033          * NOTE : All PAMUs share the same LIODN tables.
1034          */
1035 
1036         pamu_regs = of_iomap(dev->of_node, 0);
1037         if (!pamu_regs) {
1038                 dev_err(dev, "ioremap of PAMU node failed\n");
1039                 return -ENOMEM;
1040         }
1041         of_get_address(dev->of_node, 0, &size, NULL);
1042 
1043         irq = irq_of_parse_and_map(dev->of_node, 0);
1044         if (irq == NO_IRQ) {
1045                 dev_warn(dev, "no interrupts listed in PAMU node\n");
1046                 goto error;
1047         }
1048 
1049         data = kzalloc(sizeof(*data), GFP_KERNEL);
1050         if (!data) {
1051                 ret = -ENOMEM;
1052                 goto error;
1053         }
1054         data->pamu_reg_base = pamu_regs;
1055         data->count = size / PAMU_OFFSET;
1056 
1057         /* The ISR needs access to the regs, so we won't iounmap them */
1058         ret = request_irq(irq, pamu_av_isr, 0, "pamu", data);
1059         if (ret < 0) {
1060                 dev_err(dev, "error %i installing ISR for irq %i\n", ret, irq);
1061                 goto error;
1062         }
1063 
1064         guts_node = of_find_matching_node(NULL, guts_device_ids);
1065         if (!guts_node) {
1066                 dev_err(dev, "could not find GUTS node %s\n",
1067                         dev->of_node->full_name);
1068                 ret = -ENODEV;
1069                 goto error;
1070         }
1071 
1072         guts_regs = of_iomap(guts_node, 0);
1073         of_node_put(guts_node);
1074         if (!guts_regs) {
1075                 dev_err(dev, "ioremap of GUTS node failed\n");
1076                 ret = -ENODEV;
1077                 goto error;
1078         }
1079 
1080         /* read in the PAMU capability registers */
1081         get_pamu_cap_values((unsigned long)pamu_regs);
1082         /*
1083          * To simplify the allocation of a coherency domain, we allocate the
1084          * PAACT and the OMT in the same memory buffer.  Unfortunately, this
1085          * wastes more memory compared to allocating the buffers separately.
1086          */
1087         /* Determine how much memory we need */
1088         mem_size = (PAGE_SIZE << get_order(PAACT_SIZE)) +
1089                 (PAGE_SIZE << get_order(SPAACT_SIZE)) +
1090                 (PAGE_SIZE << get_order(OMT_SIZE));
1091         order = get_order(mem_size);
1092 
1093         p = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
1094         if (!p) {
1095                 dev_err(dev, "unable to allocate PAACT/SPAACT/OMT block\n");
1096                 ret = -ENOMEM;
1097                 goto error;
1098         }
1099 
1100         ppaact = page_address(p);
1101         ppaact_phys = page_to_phys(p);
1102 
1103         /* Make sure the memory is naturally aligned */
1104         if (ppaact_phys & ((PAGE_SIZE << order) - 1)) {
1105                 dev_err(dev, "PAACT/OMT block is unaligned\n");
1106                 ret = -ENOMEM;
1107                 goto error;
1108         }
1109 
1110         spaact = (void *)ppaact + (PAGE_SIZE << get_order(PAACT_SIZE));
1111         omt = (void *)spaact + (PAGE_SIZE << get_order(SPAACT_SIZE));
1112 
1113         dev_dbg(dev, "ppaact virt=%p phys=%pa\n", ppaact, &ppaact_phys);
1114 
1115         /* Check to see if we need to implement the work-around on this SOC */
1116 
1117         /* Determine the Port ID for our coherence subdomain */
1118         for (i = 0; i < ARRAY_SIZE(port_id_map); i++) {
1119                 if (port_id_map[i].svr == (mfspr(SPRN_SVR) & ~SVR_SECURITY)) {
1120                         csd_port_id = port_id_map[i].port_id;
1121                         dev_dbg(dev, "found matching SVR %08x\n",
1122                                 port_id_map[i].svr);
1123                         break;
1124                 }
1125         }
1126 
1127         if (csd_port_id) {
1128                 dev_dbg(dev, "creating coherency subdomain at address %pa, size %zu, port id 0x%08x",
1129                         &ppaact_phys, mem_size, csd_port_id);
1130 
1131                 ret = create_csd(ppaact_phys, mem_size, csd_port_id);
1132                 if (ret) {
1133                         dev_err(dev, "could not create coherence subdomain\n");
1134                         return ret;
1135                 }
1136         }
1137 
1138         spaact_phys = virt_to_phys(spaact);
1139         omt_phys = virt_to_phys(omt);
1140 
1141         spaace_pool = gen_pool_create(ilog2(sizeof(struct paace)), -1);
1142         if (!spaace_pool) {
1143                 ret = -ENOMEM;
1144                 dev_err(dev, "Failed to allocate spaace gen pool\n");
1145                 goto error;
1146         }
1147 
1148         ret = gen_pool_add(spaace_pool, (unsigned long)spaact, SPAACT_SIZE, -1);
1149         if (ret)
1150                 goto error_genpool;
1151 
1152         pamubypenr = in_be32(&guts_regs->pamubypenr);
1153 
1154         for (pamu_reg_off = 0, pamu_counter = 0x80000000; pamu_reg_off < size;
1155              pamu_reg_off += PAMU_OFFSET, pamu_counter >>= 1) {
1156 
1157                 pamu_reg_base = (unsigned long)pamu_regs + pamu_reg_off;
1158                 setup_one_pamu(pamu_reg_base, pamu_reg_off, ppaact_phys,
1159                                spaact_phys, omt_phys);
1160                 /* Disable PAMU bypass for this PAMU */
1161                 pamubypenr &= ~pamu_counter;
1162         }
1163 
1164         setup_omt(omt);
1165 
1166         /* Enable all relevant PAMU(s) */
1167         out_be32(&guts_regs->pamubypenr, pamubypenr);
1168 
1169         iounmap(guts_regs);
1170 
1171         /* Enable DMA for the LIODNs in the device tree */
1172 
1173         setup_liodns();
1174 
1175         return 0;
1176 
1177 error_genpool:
1178         gen_pool_destroy(spaace_pool);
1179 
1180 error:
1181         if (irq != NO_IRQ)
1182                 free_irq(irq, data);
1183 
1184         if (data) {
1185                 memset(data, 0, sizeof(struct pamu_isr_data));
1186                 kfree(data);
1187         }
1188 
1189         if (pamu_regs)
1190                 iounmap(pamu_regs);
1191 
1192         if (guts_regs)
1193                 iounmap(guts_regs);
1194 
1195         if (ppaact)
1196                 free_pages((unsigned long)ppaact, order);
1197 
1198         ppaact = NULL;
1199 
1200         return ret;
1201 }
1202 
1203 static struct platform_driver fsl_of_pamu_driver __initdata = {
1204         .driver = {
1205                 .name = "fsl-of-pamu",
1206         },
1207         .probe = fsl_pamu_probe,
1208 };
1209 
1210 static __init int fsl_pamu_init(void)
1211 {
1212         struct platform_device *pdev = NULL;
1213         struct device_node *np;
1214         int ret;
1215 
1216         /*
1217          * The normal OF process calls the probe function at some
1218          * indeterminate later time, after most drivers have loaded.  This is
1219          * too late for us, because PAMU clients (like the Qman driver)
1220          * depend on PAMU being initialized early.
1221          *
1222          * So instead, we "manually" call our probe function by creating the
1223          * platform devices ourselves.
1224          */
1225 
1226         /*
1227          * We assume that there is only one PAMU node in the device tree.  A
1228          * single PAMU node represents all of the PAMU devices in the SOC
1229          * already.   Everything else already makes that assumption, and the
1230          * binding for the PAMU nodes doesn't allow for any parent-child
1231          * relationships anyway.  In other words, support for more than one
1232          * PAMU node would require significant changes to a lot of code.
1233          */
1234 
1235         np = of_find_compatible_node(NULL, NULL, "fsl,pamu");
1236         if (!np) {
1237                 pr_err("could not find a PAMU node\n");
1238                 return -ENODEV;
1239         }
1240 
1241         ret = platform_driver_register(&fsl_of_pamu_driver);
1242         if (ret) {
1243                 pr_err("could not register driver (err=%i)\n", ret);
1244                 goto error_driver_register;
1245         }
1246 
1247         pdev = platform_device_alloc("fsl-of-pamu", 0);
1248         if (!pdev) {
1249                 pr_err("could not allocate device %s\n",
1250                        np->full_name);
1251                 ret = -ENOMEM;
1252                 goto error_device_alloc;
1253         }
1254         pdev->dev.of_node = of_node_get(np);
1255 
1256         ret = pamu_domain_init();
1257         if (ret)
1258                 goto error_device_add;
1259 
1260         ret = platform_device_add(pdev);
1261         if (ret) {
1262                 pr_err("could not add device %s (err=%i)\n",
1263                        np->full_name, ret);
1264                 goto error_device_add;
1265         }
1266 
1267         return 0;
1268 
1269 error_device_add:
1270         of_node_put(pdev->dev.of_node);
1271         pdev->dev.of_node = NULL;
1272 
1273         platform_device_put(pdev);
1274 
1275 error_device_alloc:
1276         platform_driver_unregister(&fsl_of_pamu_driver);
1277 
1278 error_driver_register:
1279         of_node_put(np);
1280 
1281         return ret;
1282 }
1283 arch_initcall(fsl_pamu_init);
1284 

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