Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/iommu/exynos-iommu.c

  1 /*
  2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
  3  *              http://www.samsung.com
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License version 2 as
  7  * published by the Free Software Foundation.
  8  */
  9 
 10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
 11 #define DEBUG
 12 #endif
 13 
 14 #include <linux/clk.h>
 15 #include <linux/dma-mapping.h>
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/iommu.h>
 19 #include <linux/interrupt.h>
 20 #include <linux/list.h>
 21 #include <linux/of.h>
 22 #include <linux/of_iommu.h>
 23 #include <linux/of_platform.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/pm_runtime.h>
 26 #include <linux/slab.h>
 27 #include <linux/dma-iommu.h>
 28 
 29 typedef u32 sysmmu_iova_t;
 30 typedef u32 sysmmu_pte_t;
 31 
 32 /* We do not consider super section mapping (16MB) */
 33 #define SECT_ORDER 20
 34 #define LPAGE_ORDER 16
 35 #define SPAGE_ORDER 12
 36 
 37 #define SECT_SIZE (1 << SECT_ORDER)
 38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
 39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
 40 
 41 #define SECT_MASK (~(SECT_SIZE - 1))
 42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
 43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
 44 
 45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
 46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
 47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
 48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
 49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
 50                           ((*(sent) & 3) == 1))
 51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
 52 
 53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
 54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
 55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
 56 
 57 #ifdef CONFIG_BIG_ENDIAN
 58 #warning "revisit driver if we can enable big-endian ptes"
 59 #endif
 60 
 61 /*
 62  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
 63  * v5.0 introduced support for 36bit physical address space by shifting
 64  * all page entry values by 4 bits.
 65  * All SYSMMU controllers in the system support the address spaces of the same
 66  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
 67  * value (0 or 4).
 68  */
 69 static short PG_ENT_SHIFT = -1;
 70 #define SYSMMU_PG_ENT_SHIFT 0
 71 #define SYSMMU_V5_PG_ENT_SHIFT 4
 72 
 73 static const sysmmu_pte_t *LV1_PROT;
 74 static const sysmmu_pte_t SYSMMU_LV1_PROT[] = {
 75         ((0 << 15) | (0 << 10)), /* no access */
 76         ((1 << 15) | (1 << 10)), /* IOMMU_READ only */
 77         ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
 78         ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
 79 };
 80 static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = {
 81         (0 << 4), /* no access */
 82         (1 << 4), /* IOMMU_READ only */
 83         (2 << 4), /* IOMMU_WRITE only */
 84         (3 << 4), /* IOMMU_READ | IOMMU_WRITE */
 85 };
 86 
 87 static const sysmmu_pte_t *LV2_PROT;
 88 static const sysmmu_pte_t SYSMMU_LV2_PROT[] = {
 89         ((0 << 9) | (0 << 4)), /* no access */
 90         ((1 << 9) | (1 << 4)), /* IOMMU_READ only */
 91         ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
 92         ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
 93 };
 94 static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = {
 95         (0 << 2), /* no access */
 96         (1 << 2), /* IOMMU_READ only */
 97         (2 << 2), /* IOMMU_WRITE only */
 98         (3 << 2), /* IOMMU_READ | IOMMU_WRITE */
 99 };
100 
101 #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE)
102 
103 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
104 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
105 #define section_offs(iova) (iova & (SECT_SIZE - 1))
106 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
107 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
108 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
109 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
110 
111 #define NUM_LV1ENTRIES 4096
112 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
113 
114 static u32 lv1ent_offset(sysmmu_iova_t iova)
115 {
116         return iova >> SECT_ORDER;
117 }
118 
119 static u32 lv2ent_offset(sysmmu_iova_t iova)
120 {
121         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
122 }
123 
124 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
125 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
126 
127 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
128 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
129 
130 #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2)
131 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
132 #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1)
133 #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2)
134 
135 #define CTRL_ENABLE     0x5
136 #define CTRL_BLOCK      0x7
137 #define CTRL_DISABLE    0x0
138 
139 #define CFG_LRU         0x1
140 #define CFG_EAP         (1 << 2)
141 #define CFG_QOS(n)      ((n & 0xF) << 7)
142 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
143 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
144 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
145 
146 /* common registers */
147 #define REG_MMU_CTRL            0x000
148 #define REG_MMU_CFG             0x004
149 #define REG_MMU_STATUS          0x008
150 #define REG_MMU_VERSION         0x034
151 
152 #define MMU_MAJ_VER(val)        ((val) >> 7)
153 #define MMU_MIN_VER(val)        ((val) & 0x7F)
154 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
155 
156 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
157 
158 /* v1.x - v3.x registers */
159 #define REG_MMU_FLUSH           0x00C
160 #define REG_MMU_FLUSH_ENTRY     0x010
161 #define REG_PT_BASE_ADDR        0x014
162 #define REG_INT_STATUS          0x018
163 #define REG_INT_CLEAR           0x01C
164 
165 #define REG_PAGE_FAULT_ADDR     0x024
166 #define REG_AW_FAULT_ADDR       0x028
167 #define REG_AR_FAULT_ADDR       0x02C
168 #define REG_DEFAULT_SLAVE_ADDR  0x030
169 
170 /* v5.x registers */
171 #define REG_V5_PT_BASE_PFN      0x00C
172 #define REG_V5_MMU_FLUSH_ALL    0x010
173 #define REG_V5_MMU_FLUSH_ENTRY  0x014
174 #define REG_V5_INT_STATUS       0x060
175 #define REG_V5_INT_CLEAR        0x064
176 #define REG_V5_FAULT_AR_VA      0x070
177 #define REG_V5_FAULT_AW_VA      0x080
178 
179 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
180 
181 static struct device *dma_dev;
182 static struct kmem_cache *lv2table_kmem_cache;
183 static sysmmu_pte_t *zero_lv2_table;
184 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
185 
186 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
187 {
188         return pgtable + lv1ent_offset(iova);
189 }
190 
191 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
192 {
193         return (sysmmu_pte_t *)phys_to_virt(
194                                 lv2table_base(sent)) + lv2ent_offset(iova);
195 }
196 
197 /*
198  * IOMMU fault information register
199  */
200 struct sysmmu_fault_info {
201         unsigned int bit;       /* bit number in STATUS register */
202         unsigned short addr_reg; /* register to read VA fault address */
203         const char *name;       /* human readable fault name */
204         unsigned int type;      /* fault type for report_iommu_fault */
205 };
206 
207 static const struct sysmmu_fault_info sysmmu_faults[] = {
208         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
209         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
210         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
211         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
212         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
213         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
214         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
215         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
216 };
217 
218 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
219         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
220         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
221         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
222         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
223         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
224         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
225         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
226         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
227         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
228         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
229 };
230 
231 /*
232  * This structure is attached to dev.archdata.iommu of the master device
233  * on device add, contains a list of SYSMMU controllers defined by device tree,
234  * which are bound to given master device. It is usually referenced by 'owner'
235  * pointer.
236 */
237 struct exynos_iommu_owner {
238         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
239         struct iommu_domain *domain;    /* domain this device is attached */
240         struct mutex rpm_lock;          /* for runtime pm of all sysmmus */
241 };
242 
243 /*
244  * This structure exynos specific generalization of struct iommu_domain.
245  * It contains list of SYSMMU controllers from all master devices, which has
246  * been attached to this domain and page tables of IO address space defined by
247  * it. It is usually referenced by 'domain' pointer.
248  */
249 struct exynos_iommu_domain {
250         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
251         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
252         short *lv2entcnt;       /* free lv2 entry counter for each section */
253         spinlock_t lock;        /* lock for modyfying list of clients */
254         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
255         struct iommu_domain domain; /* generic domain data structure */
256 };
257 
258 /*
259  * This structure hold all data of a single SYSMMU controller, this includes
260  * hw resources like registers and clocks, pointers and list nodes to connect
261  * it to all other structures, internal state and parameters read from device
262  * tree. It is usually referenced by 'data' pointer.
263  */
264 struct sysmmu_drvdata {
265         struct device *sysmmu;          /* SYSMMU controller device */
266         struct device *master;          /* master device (owner) */
267         void __iomem *sfrbase;          /* our registers */
268         struct clk *clk;                /* SYSMMU's clock */
269         struct clk *aclk;               /* SYSMMU's aclk clock */
270         struct clk *pclk;               /* SYSMMU's pclk clock */
271         struct clk *clk_master;         /* master's device clock */
272         spinlock_t lock;                /* lock for modyfying state */
273         bool active;                    /* current status */
274         struct exynos_iommu_domain *domain; /* domain we belong to */
275         struct list_head domain_node;   /* node for domain clients list */
276         struct list_head owner_node;    /* node for owner controllers list */
277         phys_addr_t pgtable;            /* assigned page table structure */
278         unsigned int version;           /* our version */
279 };
280 
281 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
282 {
283         return container_of(dom, struct exynos_iommu_domain, domain);
284 }
285 
286 static void sysmmu_unblock(struct sysmmu_drvdata *data)
287 {
288         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
289 }
290 
291 static bool sysmmu_block(struct sysmmu_drvdata *data)
292 {
293         int i = 120;
294 
295         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
296         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
297                 --i;
298 
299         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
300                 sysmmu_unblock(data);
301                 return false;
302         }
303 
304         return true;
305 }
306 
307 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
308 {
309         if (MMU_MAJ_VER(data->version) < 5)
310                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
311         else
312                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
313 }
314 
315 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
316                                 sysmmu_iova_t iova, unsigned int num_inv)
317 {
318         unsigned int i;
319 
320         for (i = 0; i < num_inv; i++) {
321                 if (MMU_MAJ_VER(data->version) < 5)
322                         writel((iova & SPAGE_MASK) | 1,
323                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
324                 else
325                         writel((iova & SPAGE_MASK) | 1,
326                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
327                 iova += SPAGE_SIZE;
328         }
329 }
330 
331 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
332 {
333         if (MMU_MAJ_VER(data->version) < 5)
334                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
335         else
336                 writel(pgd >> PAGE_SHIFT,
337                              data->sfrbase + REG_V5_PT_BASE_PFN);
338 
339         __sysmmu_tlb_invalidate(data);
340 }
341 
342 static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data)
343 {
344         BUG_ON(clk_prepare_enable(data->clk_master));
345         BUG_ON(clk_prepare_enable(data->clk));
346         BUG_ON(clk_prepare_enable(data->pclk));
347         BUG_ON(clk_prepare_enable(data->aclk));
348 }
349 
350 static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data)
351 {
352         clk_disable_unprepare(data->aclk);
353         clk_disable_unprepare(data->pclk);
354         clk_disable_unprepare(data->clk);
355         clk_disable_unprepare(data->clk_master);
356 }
357 
358 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
359 {
360         u32 ver;
361 
362         __sysmmu_enable_clocks(data);
363 
364         ver = readl(data->sfrbase + REG_MMU_VERSION);
365 
366         /* controllers on some SoCs don't report proper version */
367         if (ver == 0x80000001u)
368                 data->version = MAKE_MMU_VER(1, 0);
369         else
370                 data->version = MMU_RAW_VER(ver);
371 
372         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
373                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
374 
375         __sysmmu_disable_clocks(data);
376 }
377 
378 static void show_fault_information(struct sysmmu_drvdata *data,
379                                    const struct sysmmu_fault_info *finfo,
380                                    sysmmu_iova_t fault_addr)
381 {
382         sysmmu_pte_t *ent;
383 
384         dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
385                 finfo->name, fault_addr, &data->pgtable);
386         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
387         dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
388         if (lv1ent_page(ent)) {
389                 ent = page_entry(ent, fault_addr);
390                 dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
391         }
392 }
393 
394 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
395 {
396         /* SYSMMU is in blocked state when interrupt occurred. */
397         struct sysmmu_drvdata *data = dev_id;
398         const struct sysmmu_fault_info *finfo;
399         unsigned int i, n, itype;
400         sysmmu_iova_t fault_addr = -1;
401         unsigned short reg_status, reg_clear;
402         int ret = -ENOSYS;
403 
404         WARN_ON(!data->active);
405 
406         if (MMU_MAJ_VER(data->version) < 5) {
407                 reg_status = REG_INT_STATUS;
408                 reg_clear = REG_INT_CLEAR;
409                 finfo = sysmmu_faults;
410                 n = ARRAY_SIZE(sysmmu_faults);
411         } else {
412                 reg_status = REG_V5_INT_STATUS;
413                 reg_clear = REG_V5_INT_CLEAR;
414                 finfo = sysmmu_v5_faults;
415                 n = ARRAY_SIZE(sysmmu_v5_faults);
416         }
417 
418         spin_lock(&data->lock);
419 
420         clk_enable(data->clk_master);
421 
422         itype = __ffs(readl(data->sfrbase + reg_status));
423         for (i = 0; i < n; i++, finfo++)
424                 if (finfo->bit == itype)
425                         break;
426         /* unknown/unsupported fault */
427         BUG_ON(i == n);
428 
429         /* print debug message */
430         fault_addr = readl(data->sfrbase + finfo->addr_reg);
431         show_fault_information(data, finfo, fault_addr);
432 
433         if (data->domain)
434                 ret = report_iommu_fault(&data->domain->domain,
435                                         data->master, fault_addr, finfo->type);
436         /* fault is not recovered by fault handler */
437         BUG_ON(ret != 0);
438 
439         writel(1 << itype, data->sfrbase + reg_clear);
440 
441         sysmmu_unblock(data);
442 
443         clk_disable(data->clk_master);
444 
445         spin_unlock(&data->lock);
446 
447         return IRQ_HANDLED;
448 }
449 
450 static void __sysmmu_disable(struct sysmmu_drvdata *data)
451 {
452         unsigned long flags;
453 
454         clk_enable(data->clk_master);
455 
456         spin_lock_irqsave(&data->lock, flags);
457         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
458         writel(0, data->sfrbase + REG_MMU_CFG);
459         data->active = false;
460         spin_unlock_irqrestore(&data->lock, flags);
461 
462         __sysmmu_disable_clocks(data);
463 }
464 
465 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
466 {
467         unsigned int cfg;
468 
469         if (data->version <= MAKE_MMU_VER(3, 1))
470                 cfg = CFG_LRU | CFG_QOS(15);
471         else if (data->version <= MAKE_MMU_VER(3, 2))
472                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
473         else
474                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
475 
476         cfg |= CFG_EAP; /* enable access protection bits check */
477 
478         writel(cfg, data->sfrbase + REG_MMU_CFG);
479 }
480 
481 static void __sysmmu_enable(struct sysmmu_drvdata *data)
482 {
483         unsigned long flags;
484 
485         __sysmmu_enable_clocks(data);
486 
487         spin_lock_irqsave(&data->lock, flags);
488         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
489         __sysmmu_init_config(data);
490         __sysmmu_set_ptbase(data, data->pgtable);
491         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
492         data->active = true;
493         spin_unlock_irqrestore(&data->lock, flags);
494 
495         /*
496          * SYSMMU driver keeps master's clock enabled only for the short
497          * time, while accessing the registers. For performing address
498          * translation during DMA transaction it relies on the client
499          * driver to enable it.
500          */
501         clk_disable(data->clk_master);
502 }
503 
504 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
505                                             sysmmu_iova_t iova)
506 {
507         unsigned long flags;
508 
509         spin_lock_irqsave(&data->lock, flags);
510         if (data->active && data->version >= MAKE_MMU_VER(3, 3)) {
511                 clk_enable(data->clk_master);
512                 __sysmmu_tlb_invalidate_entry(data, iova, 1);
513                 clk_disable(data->clk_master);
514         }
515         spin_unlock_irqrestore(&data->lock, flags);
516 }
517 
518 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
519                                         sysmmu_iova_t iova, size_t size)
520 {
521         unsigned long flags;
522 
523         spin_lock_irqsave(&data->lock, flags);
524         if (data->active) {
525                 unsigned int num_inv = 1;
526 
527                 clk_enable(data->clk_master);
528 
529                 /*
530                  * L2TLB invalidation required
531                  * 4KB page: 1 invalidation
532                  * 64KB page: 16 invalidations
533                  * 1MB page: 64 invalidations
534                  * because it is set-associative TLB
535                  * with 8-way and 64 sets.
536                  * 1MB page can be cached in one of all sets.
537                  * 64KB page can be one of 16 consecutive sets.
538                  */
539                 if (MMU_MAJ_VER(data->version) == 2)
540                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
541 
542                 if (sysmmu_block(data)) {
543                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
544                         sysmmu_unblock(data);
545                 }
546                 clk_disable(data->clk_master);
547         }
548         spin_unlock_irqrestore(&data->lock, flags);
549 }
550 
551 static struct iommu_ops exynos_iommu_ops;
552 
553 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
554 {
555         int irq, ret;
556         struct device *dev = &pdev->dev;
557         struct sysmmu_drvdata *data;
558         struct resource *res;
559 
560         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
561         if (!data)
562                 return -ENOMEM;
563 
564         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
565         data->sfrbase = devm_ioremap_resource(dev, res);
566         if (IS_ERR(data->sfrbase))
567                 return PTR_ERR(data->sfrbase);
568 
569         irq = platform_get_irq(pdev, 0);
570         if (irq <= 0) {
571                 dev_err(dev, "Unable to find IRQ resource\n");
572                 return irq;
573         }
574 
575         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
576                                 dev_name(dev), data);
577         if (ret) {
578                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
579                 return ret;
580         }
581 
582         data->clk = devm_clk_get(dev, "sysmmu");
583         if (PTR_ERR(data->clk) == -ENOENT)
584                 data->clk = NULL;
585         else if (IS_ERR(data->clk))
586                 return PTR_ERR(data->clk);
587 
588         data->aclk = devm_clk_get(dev, "aclk");
589         if (PTR_ERR(data->aclk) == -ENOENT)
590                 data->aclk = NULL;
591         else if (IS_ERR(data->aclk))
592                 return PTR_ERR(data->aclk);
593 
594         data->pclk = devm_clk_get(dev, "pclk");
595         if (PTR_ERR(data->pclk) == -ENOENT)
596                 data->pclk = NULL;
597         else if (IS_ERR(data->pclk))
598                 return PTR_ERR(data->pclk);
599 
600         if (!data->clk && (!data->aclk || !data->pclk)) {
601                 dev_err(dev, "Failed to get device clock(s)!\n");
602                 return -ENOSYS;
603         }
604 
605         data->clk_master = devm_clk_get(dev, "master");
606         if (PTR_ERR(data->clk_master) == -ENOENT)
607                 data->clk_master = NULL;
608         else if (IS_ERR(data->clk_master))
609                 return PTR_ERR(data->clk_master);
610 
611         data->sysmmu = dev;
612         spin_lock_init(&data->lock);
613 
614         platform_set_drvdata(pdev, data);
615 
616         __sysmmu_get_version(data);
617         if (PG_ENT_SHIFT < 0) {
618                 if (MMU_MAJ_VER(data->version) < 5) {
619                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
620                         LV1_PROT = SYSMMU_LV1_PROT;
621                         LV2_PROT = SYSMMU_LV2_PROT;
622                 } else {
623                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
624                         LV1_PROT = SYSMMU_V5_LV1_PROT;
625                         LV2_PROT = SYSMMU_V5_LV2_PROT;
626                 }
627         }
628 
629         pm_runtime_enable(dev);
630 
631         of_iommu_set_ops(dev->of_node, &exynos_iommu_ops);
632 
633         return 0;
634 }
635 
636 static int __maybe_unused exynos_sysmmu_suspend(struct device *dev)
637 {
638         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
639         struct device *master = data->master;
640 
641         if (master) {
642                 struct exynos_iommu_owner *owner = master->archdata.iommu;
643 
644                 mutex_lock(&owner->rpm_lock);
645                 if (data->domain) {
646                         dev_dbg(data->sysmmu, "saving state\n");
647                         __sysmmu_disable(data);
648                 }
649                 mutex_unlock(&owner->rpm_lock);
650         }
651         return 0;
652 }
653 
654 static int __maybe_unused exynos_sysmmu_resume(struct device *dev)
655 {
656         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
657         struct device *master = data->master;
658 
659         if (master) {
660                 struct exynos_iommu_owner *owner = master->archdata.iommu;
661 
662                 mutex_lock(&owner->rpm_lock);
663                 if (data->domain) {
664                         dev_dbg(data->sysmmu, "restoring state\n");
665                         __sysmmu_enable(data);
666                 }
667                 mutex_unlock(&owner->rpm_lock);
668         }
669         return 0;
670 }
671 
672 static const struct dev_pm_ops sysmmu_pm_ops = {
673         SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL)
674         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
675                                 pm_runtime_force_resume)
676 };
677 
678 static const struct of_device_id sysmmu_of_match[] __initconst = {
679         { .compatible   = "samsung,exynos-sysmmu", },
680         { },
681 };
682 
683 static struct platform_driver exynos_sysmmu_driver __refdata = {
684         .probe  = exynos_sysmmu_probe,
685         .driver = {
686                 .name           = "exynos-sysmmu",
687                 .of_match_table = sysmmu_of_match,
688                 .pm             = &sysmmu_pm_ops,
689                 .suppress_bind_attrs = true,
690         }
691 };
692 
693 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
694 {
695         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
696                                 DMA_TO_DEVICE);
697         *ent = cpu_to_le32(val);
698         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
699                                    DMA_TO_DEVICE);
700 }
701 
702 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
703 {
704         struct exynos_iommu_domain *domain;
705         dma_addr_t handle;
706         int i;
707 
708         /* Check if correct PTE offsets are initialized */
709         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
710 
711         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
712         if (!domain)
713                 return NULL;
714 
715         if (type == IOMMU_DOMAIN_DMA) {
716                 if (iommu_get_dma_cookie(&domain->domain) != 0)
717                         goto err_pgtable;
718         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
719                 goto err_pgtable;
720         }
721 
722         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
723         if (!domain->pgtable)
724                 goto err_dma_cookie;
725 
726         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
727         if (!domain->lv2entcnt)
728                 goto err_counter;
729 
730         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
731         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
732                 domain->pgtable[i + 0] = ZERO_LV2LINK;
733                 domain->pgtable[i + 1] = ZERO_LV2LINK;
734                 domain->pgtable[i + 2] = ZERO_LV2LINK;
735                 domain->pgtable[i + 3] = ZERO_LV2LINK;
736                 domain->pgtable[i + 4] = ZERO_LV2LINK;
737                 domain->pgtable[i + 5] = ZERO_LV2LINK;
738                 domain->pgtable[i + 6] = ZERO_LV2LINK;
739                 domain->pgtable[i + 7] = ZERO_LV2LINK;
740         }
741 
742         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
743                                 DMA_TO_DEVICE);
744         /* For mapping page table entries we rely on dma == phys */
745         BUG_ON(handle != virt_to_phys(domain->pgtable));
746 
747         spin_lock_init(&domain->lock);
748         spin_lock_init(&domain->pgtablelock);
749         INIT_LIST_HEAD(&domain->clients);
750 
751         domain->domain.geometry.aperture_start = 0;
752         domain->domain.geometry.aperture_end   = ~0UL;
753         domain->domain.geometry.force_aperture = true;
754 
755         return &domain->domain;
756 
757 err_counter:
758         free_pages((unsigned long)domain->pgtable, 2);
759 err_dma_cookie:
760         if (type == IOMMU_DOMAIN_DMA)
761                 iommu_put_dma_cookie(&domain->domain);
762 err_pgtable:
763         kfree(domain);
764         return NULL;
765 }
766 
767 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
768 {
769         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
770         struct sysmmu_drvdata *data, *next;
771         unsigned long flags;
772         int i;
773 
774         WARN_ON(!list_empty(&domain->clients));
775 
776         spin_lock_irqsave(&domain->lock, flags);
777 
778         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
779                 spin_lock(&data->lock);
780                 __sysmmu_disable(data);
781                 data->pgtable = 0;
782                 data->domain = NULL;
783                 list_del_init(&data->domain_node);
784                 spin_unlock(&data->lock);
785         }
786 
787         spin_unlock_irqrestore(&domain->lock, flags);
788 
789         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
790                 iommu_put_dma_cookie(iommu_domain);
791 
792         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
793                          DMA_TO_DEVICE);
794 
795         for (i = 0; i < NUM_LV1ENTRIES; i++)
796                 if (lv1ent_page(domain->pgtable + i)) {
797                         phys_addr_t base = lv2table_base(domain->pgtable + i);
798 
799                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
800                                          DMA_TO_DEVICE);
801                         kmem_cache_free(lv2table_kmem_cache,
802                                         phys_to_virt(base));
803                 }
804 
805         free_pages((unsigned long)domain->pgtable, 2);
806         free_pages((unsigned long)domain->lv2entcnt, 1);
807         kfree(domain);
808 }
809 
810 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
811                                     struct device *dev)
812 {
813         struct exynos_iommu_owner *owner = dev->archdata.iommu;
814         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
815         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
816         struct sysmmu_drvdata *data, *next;
817         unsigned long flags;
818 
819         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
820                 return;
821 
822         mutex_lock(&owner->rpm_lock);
823 
824         list_for_each_entry(data, &owner->controllers, owner_node) {
825                 pm_runtime_get_noresume(data->sysmmu);
826                 if (pm_runtime_active(data->sysmmu))
827                         __sysmmu_disable(data);
828                 pm_runtime_put(data->sysmmu);
829         }
830 
831         spin_lock_irqsave(&domain->lock, flags);
832         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
833                 spin_lock(&data->lock);
834                 data->pgtable = 0;
835                 data->domain = NULL;
836                 list_del_init(&data->domain_node);
837                 spin_unlock(&data->lock);
838         }
839         owner->domain = NULL;
840         spin_unlock_irqrestore(&domain->lock, flags);
841 
842         mutex_unlock(&owner->rpm_lock);
843 
844         dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__,
845                 &pagetable);
846 }
847 
848 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
849                                    struct device *dev)
850 {
851         struct exynos_iommu_owner *owner = dev->archdata.iommu;
852         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
853         struct sysmmu_drvdata *data;
854         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
855         unsigned long flags;
856 
857         if (!has_sysmmu(dev))
858                 return -ENODEV;
859 
860         if (owner->domain)
861                 exynos_iommu_detach_device(owner->domain, dev);
862 
863         mutex_lock(&owner->rpm_lock);
864 
865         spin_lock_irqsave(&domain->lock, flags);
866         list_for_each_entry(data, &owner->controllers, owner_node) {
867                 spin_lock(&data->lock);
868                 data->pgtable = pagetable;
869                 data->domain = domain;
870                 list_add_tail(&data->domain_node, &domain->clients);
871                 spin_unlock(&data->lock);
872         }
873         owner->domain = iommu_domain;
874         spin_unlock_irqrestore(&domain->lock, flags);
875 
876         list_for_each_entry(data, &owner->controllers, owner_node) {
877                 pm_runtime_get_noresume(data->sysmmu);
878                 if (pm_runtime_active(data->sysmmu))
879                         __sysmmu_enable(data);
880                 pm_runtime_put(data->sysmmu);
881         }
882 
883         mutex_unlock(&owner->rpm_lock);
884 
885         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__,
886                 &pagetable);
887 
888         return 0;
889 }
890 
891 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
892                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
893 {
894         if (lv1ent_section(sent)) {
895                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
896                 return ERR_PTR(-EADDRINUSE);
897         }
898 
899         if (lv1ent_fault(sent)) {
900                 sysmmu_pte_t *pent;
901                 bool need_flush_flpd_cache = lv1ent_zero(sent);
902 
903                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
904                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
905                 if (!pent)
906                         return ERR_PTR(-ENOMEM);
907 
908                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
909                 kmemleak_ignore(pent);
910                 *pgcounter = NUM_LV2ENTRIES;
911                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
912 
913                 /*
914                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
915                  * FLPD cache may cache the address of zero_l2_table. This
916                  * function replaces the zero_l2_table with new L2 page table
917                  * to write valid mappings.
918                  * Accessing the valid area may cause page fault since FLPD
919                  * cache may still cache zero_l2_table for the valid area
920                  * instead of new L2 page table that has the mapping
921                  * information of the valid area.
922                  * Thus any replacement of zero_l2_table with other valid L2
923                  * page table must involve FLPD cache invalidation for System
924                  * MMU v3.3.
925                  * FLPD cache invalidation is performed with TLB invalidation
926                  * by VPN without blocking. It is safe to invalidate TLB without
927                  * blocking because the target address of TLB invalidation is
928                  * not currently mapped.
929                  */
930                 if (need_flush_flpd_cache) {
931                         struct sysmmu_drvdata *data;
932 
933                         spin_lock(&domain->lock);
934                         list_for_each_entry(data, &domain->clients, domain_node)
935                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
936                         spin_unlock(&domain->lock);
937                 }
938         }
939 
940         return page_entry(sent, iova);
941 }
942 
943 static int lv1set_section(struct exynos_iommu_domain *domain,
944                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
945                           phys_addr_t paddr, int prot, short *pgcnt)
946 {
947         if (lv1ent_section(sent)) {
948                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
949                         iova);
950                 return -EADDRINUSE;
951         }
952 
953         if (lv1ent_page(sent)) {
954                 if (*pgcnt != NUM_LV2ENTRIES) {
955                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
956                                 iova);
957                         return -EADDRINUSE;
958                 }
959 
960                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
961                 *pgcnt = 0;
962         }
963 
964         update_pte(sent, mk_lv1ent_sect(paddr, prot));
965 
966         spin_lock(&domain->lock);
967         if (lv1ent_page_zero(sent)) {
968                 struct sysmmu_drvdata *data;
969                 /*
970                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
971                  * entry by speculative prefetch of SLPD which has no mapping.
972                  */
973                 list_for_each_entry(data, &domain->clients, domain_node)
974                         sysmmu_tlb_invalidate_flpdcache(data, iova);
975         }
976         spin_unlock(&domain->lock);
977 
978         return 0;
979 }
980 
981 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
982                        int prot, short *pgcnt)
983 {
984         if (size == SPAGE_SIZE) {
985                 if (WARN_ON(!lv2ent_fault(pent)))
986                         return -EADDRINUSE;
987 
988                 update_pte(pent, mk_lv2ent_spage(paddr, prot));
989                 *pgcnt -= 1;
990         } else { /* size == LPAGE_SIZE */
991                 int i;
992                 dma_addr_t pent_base = virt_to_phys(pent);
993 
994                 dma_sync_single_for_cpu(dma_dev, pent_base,
995                                         sizeof(*pent) * SPAGES_PER_LPAGE,
996                                         DMA_TO_DEVICE);
997                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
998                         if (WARN_ON(!lv2ent_fault(pent))) {
999                                 if (i > 0)
1000                                         memset(pent - i, 0, sizeof(*pent) * i);
1001                                 return -EADDRINUSE;
1002                         }
1003 
1004                         *pent = mk_lv2ent_lpage(paddr, prot);
1005                 }
1006                 dma_sync_single_for_device(dma_dev, pent_base,
1007                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1008                                            DMA_TO_DEVICE);
1009                 *pgcnt -= SPAGES_PER_LPAGE;
1010         }
1011 
1012         return 0;
1013 }
1014 
1015 /*
1016  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1017  *
1018  * System MMU v3.x has advanced logic to improve address translation
1019  * performance with caching more page table entries by a page table walk.
1020  * However, the logic has a bug that while caching faulty page table entries,
1021  * System MMU reports page fault if the cached fault entry is hit even though
1022  * the fault entry is updated to a valid entry after the entry is cached.
1023  * To prevent caching faulty page table entries which may be updated to valid
1024  * entries later, the virtual memory manager should care about the workaround
1025  * for the problem. The following describes the workaround.
1026  *
1027  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1028  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1029  *
1030  * Precisely, any start address of I/O virtual region must be aligned with
1031  * the following sizes for System MMU v3.1 and v3.2.
1032  * System MMU v3.1: 128KiB
1033  * System MMU v3.2: 256KiB
1034  *
1035  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1036  * more workarounds.
1037  * - Any two consecutive I/O virtual regions must have a hole of size larger
1038  *   than or equal to 128KiB.
1039  * - Start address of an I/O virtual region must be aligned by 128KiB.
1040  */
1041 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1042                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1043                             int prot)
1044 {
1045         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1046         sysmmu_pte_t *entry;
1047         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1048         unsigned long flags;
1049         int ret = -ENOMEM;
1050 
1051         BUG_ON(domain->pgtable == NULL);
1052         prot &= SYSMMU_SUPPORTED_PROT_BITS;
1053 
1054         spin_lock_irqsave(&domain->pgtablelock, flags);
1055 
1056         entry = section_entry(domain->pgtable, iova);
1057 
1058         if (size == SECT_SIZE) {
1059                 ret = lv1set_section(domain, entry, iova, paddr, prot,
1060                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1061         } else {
1062                 sysmmu_pte_t *pent;
1063 
1064                 pent = alloc_lv2entry(domain, entry, iova,
1065                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1066 
1067                 if (IS_ERR(pent))
1068                         ret = PTR_ERR(pent);
1069                 else
1070                         ret = lv2set_page(pent, paddr, size, prot,
1071                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1072         }
1073 
1074         if (ret)
1075                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1076                         __func__, ret, size, iova);
1077 
1078         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1079 
1080         return ret;
1081 }
1082 
1083 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1084                                               sysmmu_iova_t iova, size_t size)
1085 {
1086         struct sysmmu_drvdata *data;
1087         unsigned long flags;
1088 
1089         spin_lock_irqsave(&domain->lock, flags);
1090 
1091         list_for_each_entry(data, &domain->clients, domain_node)
1092                 sysmmu_tlb_invalidate_entry(data, iova, size);
1093 
1094         spin_unlock_irqrestore(&domain->lock, flags);
1095 }
1096 
1097 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1098                                  unsigned long l_iova, size_t size)
1099 {
1100         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1101         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1102         sysmmu_pte_t *ent;
1103         size_t err_pgsize;
1104         unsigned long flags;
1105 
1106         BUG_ON(domain->pgtable == NULL);
1107 
1108         spin_lock_irqsave(&domain->pgtablelock, flags);
1109 
1110         ent = section_entry(domain->pgtable, iova);
1111 
1112         if (lv1ent_section(ent)) {
1113                 if (WARN_ON(size < SECT_SIZE)) {
1114                         err_pgsize = SECT_SIZE;
1115                         goto err;
1116                 }
1117 
1118                 /* workaround for h/w bug in System MMU v3.3 */
1119                 update_pte(ent, ZERO_LV2LINK);
1120                 size = SECT_SIZE;
1121                 goto done;
1122         }
1123 
1124         if (unlikely(lv1ent_fault(ent))) {
1125                 if (size > SECT_SIZE)
1126                         size = SECT_SIZE;
1127                 goto done;
1128         }
1129 
1130         /* lv1ent_page(sent) == true here */
1131 
1132         ent = page_entry(ent, iova);
1133 
1134         if (unlikely(lv2ent_fault(ent))) {
1135                 size = SPAGE_SIZE;
1136                 goto done;
1137         }
1138 
1139         if (lv2ent_small(ent)) {
1140                 update_pte(ent, 0);
1141                 size = SPAGE_SIZE;
1142                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1143                 goto done;
1144         }
1145 
1146         /* lv1ent_large(ent) == true here */
1147         if (WARN_ON(size < LPAGE_SIZE)) {
1148                 err_pgsize = LPAGE_SIZE;
1149                 goto err;
1150         }
1151 
1152         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1153                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1154                                 DMA_TO_DEVICE);
1155         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1156         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1157                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1158                                    DMA_TO_DEVICE);
1159         size = LPAGE_SIZE;
1160         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1161 done:
1162         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1163 
1164         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1165 
1166         return size;
1167 err:
1168         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1169 
1170         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1171                 __func__, size, iova, err_pgsize);
1172 
1173         return 0;
1174 }
1175 
1176 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1177                                           dma_addr_t iova)
1178 {
1179         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1180         sysmmu_pte_t *entry;
1181         unsigned long flags;
1182         phys_addr_t phys = 0;
1183 
1184         spin_lock_irqsave(&domain->pgtablelock, flags);
1185 
1186         entry = section_entry(domain->pgtable, iova);
1187 
1188         if (lv1ent_section(entry)) {
1189                 phys = section_phys(entry) + section_offs(iova);
1190         } else if (lv1ent_page(entry)) {
1191                 entry = page_entry(entry, iova);
1192 
1193                 if (lv2ent_large(entry))
1194                         phys = lpage_phys(entry) + lpage_offs(iova);
1195                 else if (lv2ent_small(entry))
1196                         phys = spage_phys(entry) + spage_offs(iova);
1197         }
1198 
1199         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1200 
1201         return phys;
1202 }
1203 
1204 static struct iommu_group *get_device_iommu_group(struct device *dev)
1205 {
1206         struct iommu_group *group;
1207 
1208         group = iommu_group_get(dev);
1209         if (!group)
1210                 group = iommu_group_alloc();
1211 
1212         return group;
1213 }
1214 
1215 static int exynos_iommu_add_device(struct device *dev)
1216 {
1217         struct iommu_group *group;
1218 
1219         if (!has_sysmmu(dev))
1220                 return -ENODEV;
1221 
1222         group = iommu_group_get_for_dev(dev);
1223 
1224         if (IS_ERR(group))
1225                 return PTR_ERR(group);
1226 
1227         iommu_group_put(group);
1228 
1229         return 0;
1230 }
1231 
1232 static void exynos_iommu_remove_device(struct device *dev)
1233 {
1234         if (!has_sysmmu(dev))
1235                 return;
1236 
1237         iommu_group_remove_device(dev);
1238 }
1239 
1240 static int exynos_iommu_of_xlate(struct device *dev,
1241                                  struct of_phandle_args *spec)
1242 {
1243         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1244         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1245         struct sysmmu_drvdata *data;
1246 
1247         if (!sysmmu)
1248                 return -ENODEV;
1249 
1250         data = platform_get_drvdata(sysmmu);
1251         if (!data)
1252                 return -ENODEV;
1253 
1254         if (!owner) {
1255                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1256                 if (!owner)
1257                         return -ENOMEM;
1258 
1259                 INIT_LIST_HEAD(&owner->controllers);
1260                 mutex_init(&owner->rpm_lock);
1261                 dev->archdata.iommu = owner;
1262         }
1263 
1264         list_add_tail(&data->owner_node, &owner->controllers);
1265         data->master = dev;
1266 
1267         /*
1268          * SYSMMU will be runtime activated via device link (dependency) to its
1269          * master device, so there are no direct calls to pm_runtime_get/put
1270          * in this driver.
1271          */
1272         device_link_add(dev, data->sysmmu, DL_FLAG_PM_RUNTIME);
1273 
1274         return 0;
1275 }
1276 
1277 static struct iommu_ops exynos_iommu_ops = {
1278         .domain_alloc = exynos_iommu_domain_alloc,
1279         .domain_free = exynos_iommu_domain_free,
1280         .attach_dev = exynos_iommu_attach_device,
1281         .detach_dev = exynos_iommu_detach_device,
1282         .map = exynos_iommu_map,
1283         .unmap = exynos_iommu_unmap,
1284         .map_sg = default_iommu_map_sg,
1285         .iova_to_phys = exynos_iommu_iova_to_phys,
1286         .device_group = get_device_iommu_group,
1287         .add_device = exynos_iommu_add_device,
1288         .remove_device = exynos_iommu_remove_device,
1289         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1290         .of_xlate = exynos_iommu_of_xlate,
1291 };
1292 
1293 static bool init_done;
1294 
1295 static int __init exynos_iommu_init(void)
1296 {
1297         int ret;
1298 
1299         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1300                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1301         if (!lv2table_kmem_cache) {
1302                 pr_err("%s: Failed to create kmem cache\n", __func__);
1303                 return -ENOMEM;
1304         }
1305 
1306         ret = platform_driver_register(&exynos_sysmmu_driver);
1307         if (ret) {
1308                 pr_err("%s: Failed to register driver\n", __func__);
1309                 goto err_reg_driver;
1310         }
1311 
1312         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1313         if (zero_lv2_table == NULL) {
1314                 pr_err("%s: Failed to allocate zero level2 page table\n",
1315                         __func__);
1316                 ret = -ENOMEM;
1317                 goto err_zero_lv2;
1318         }
1319 
1320         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1321         if (ret) {
1322                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1323                                                                 __func__);
1324                 goto err_set_iommu;
1325         }
1326 
1327         init_done = true;
1328 
1329         return 0;
1330 err_set_iommu:
1331         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1332 err_zero_lv2:
1333         platform_driver_unregister(&exynos_sysmmu_driver);
1334 err_reg_driver:
1335         kmem_cache_destroy(lv2table_kmem_cache);
1336         return ret;
1337 }
1338 
1339 static int __init exynos_iommu_of_setup(struct device_node *np)
1340 {
1341         struct platform_device *pdev;
1342 
1343         if (!init_done)
1344                 exynos_iommu_init();
1345 
1346         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1347         if (!pdev)
1348                 return -ENODEV;
1349 
1350         /*
1351          * use the first registered sysmmu device for performing
1352          * dma mapping operations on iommu page tables (cpu cache flush)
1353          */
1354         if (!dma_dev)
1355                 dma_dev = &pdev->dev;
1356 
1357         return 0;
1358 }
1359 
1360 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1361                  exynos_iommu_of_setup);
1362 

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