Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/iommu/arm-smmu.c

  1 /*
  2  * IOMMU API for ARM architected SMMU implementations.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope that it will be useful,
  9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11  * GNU General Public License for more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program; if not, write to the Free Software
 15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 16  *
 17  * Copyright (C) 2013 ARM Limited
 18  *
 19  * Author: Will Deacon <will.deacon@arm.com>
 20  *
 21  * This driver currently supports:
 22  *      - SMMUv1 and v2 implementations
 23  *      - Stream-matching and stream-indexing
 24  *      - v7/v8 long-descriptor format
 25  *      - Non-secure access to the SMMU
 26  *      - Context fault reporting
 27  */
 28 
 29 #define pr_fmt(fmt) "arm-smmu: " fmt
 30 
 31 #include <linux/delay.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/err.h>
 34 #include <linux/interrupt.h>
 35 #include <linux/io.h>
 36 #include <linux/iommu.h>
 37 #include <linux/iopoll.h>
 38 #include <linux/module.h>
 39 #include <linux/of.h>
 40 #include <linux/pci.h>
 41 #include <linux/platform_device.h>
 42 #include <linux/slab.h>
 43 #include <linux/spinlock.h>
 44 
 45 #include <linux/amba/bus.h>
 46 
 47 #include "io-pgtable.h"
 48 
 49 /* Maximum number of stream IDs assigned to a single device */
 50 #define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
 51 
 52 /* Maximum number of context banks per SMMU */
 53 #define ARM_SMMU_MAX_CBS                128
 54 
 55 /* Maximum number of mapping groups per SMMU */
 56 #define ARM_SMMU_MAX_SMRS               128
 57 
 58 /* SMMU global address space */
 59 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
 60 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (1 << (smmu)->pgshift))
 61 
 62 /*
 63  * SMMU global address space with conditional offset to access secure
 64  * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
 65  * nsGFSYNR0: 0x450)
 66  */
 67 #define ARM_SMMU_GR0_NS(smmu)                                           \
 68         ((smmu)->base +                                                 \
 69                 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
 70                         ? 0x400 : 0))
 71 
 72 /* Configuration registers */
 73 #define ARM_SMMU_GR0_sCR0               0x0
 74 #define sCR0_CLIENTPD                   (1 << 0)
 75 #define sCR0_GFRE                       (1 << 1)
 76 #define sCR0_GFIE                       (1 << 2)
 77 #define sCR0_GCFGFRE                    (1 << 4)
 78 #define sCR0_GCFGFIE                    (1 << 5)
 79 #define sCR0_USFCFG                     (1 << 10)
 80 #define sCR0_VMIDPNE                    (1 << 11)
 81 #define sCR0_PTM                        (1 << 12)
 82 #define sCR0_FB                         (1 << 13)
 83 #define sCR0_BSU_SHIFT                  14
 84 #define sCR0_BSU_MASK                   0x3
 85 
 86 /* Identification registers */
 87 #define ARM_SMMU_GR0_ID0                0x20
 88 #define ARM_SMMU_GR0_ID1                0x24
 89 #define ARM_SMMU_GR0_ID2                0x28
 90 #define ARM_SMMU_GR0_ID3                0x2c
 91 #define ARM_SMMU_GR0_ID4                0x30
 92 #define ARM_SMMU_GR0_ID5                0x34
 93 #define ARM_SMMU_GR0_ID6                0x38
 94 #define ARM_SMMU_GR0_ID7                0x3c
 95 #define ARM_SMMU_GR0_sGFSR              0x48
 96 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 97 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 98 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 99 
100 #define ID0_S1TS                        (1 << 30)
101 #define ID0_S2TS                        (1 << 29)
102 #define ID0_NTS                         (1 << 28)
103 #define ID0_SMS                         (1 << 27)
104 #define ID0_ATOSNS                      (1 << 26)
105 #define ID0_CTTW                        (1 << 14)
106 #define ID0_NUMIRPT_SHIFT               16
107 #define ID0_NUMIRPT_MASK                0xff
108 #define ID0_NUMSIDB_SHIFT               9
109 #define ID0_NUMSIDB_MASK                0xf
110 #define ID0_NUMSMRG_SHIFT               0
111 #define ID0_NUMSMRG_MASK                0xff
112 
113 #define ID1_PAGESIZE                    (1 << 31)
114 #define ID1_NUMPAGENDXB_SHIFT           28
115 #define ID1_NUMPAGENDXB_MASK            7
116 #define ID1_NUMS2CB_SHIFT               16
117 #define ID1_NUMS2CB_MASK                0xff
118 #define ID1_NUMCB_SHIFT                 0
119 #define ID1_NUMCB_MASK                  0xff
120 
121 #define ID2_OAS_SHIFT                   4
122 #define ID2_OAS_MASK                    0xf
123 #define ID2_IAS_SHIFT                   0
124 #define ID2_IAS_MASK                    0xf
125 #define ID2_UBS_SHIFT                   8
126 #define ID2_UBS_MASK                    0xf
127 #define ID2_PTFS_4K                     (1 << 12)
128 #define ID2_PTFS_16K                    (1 << 13)
129 #define ID2_PTFS_64K                    (1 << 14)
130 
131 /* Global TLB invalidation */
132 #define ARM_SMMU_GR0_TLBIVMID           0x64
133 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
134 #define ARM_SMMU_GR0_TLBIALLH           0x6c
135 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
136 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
137 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
138 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
139 
140 /* Stream mapping registers */
141 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
142 #define SMR_VALID                       (1 << 31)
143 #define SMR_MASK_SHIFT                  16
144 #define SMR_MASK_MASK                   0x7fff
145 #define SMR_ID_SHIFT                    0
146 #define SMR_ID_MASK                     0x7fff
147 
148 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
149 #define S2CR_CBNDX_SHIFT                0
150 #define S2CR_CBNDX_MASK                 0xff
151 #define S2CR_TYPE_SHIFT                 16
152 #define S2CR_TYPE_MASK                  0x3
153 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
154 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
155 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
156 
157 /* Context bank attribute registers */
158 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
159 #define CBAR_VMID_SHIFT                 0
160 #define CBAR_VMID_MASK                  0xff
161 #define CBAR_S1_BPSHCFG_SHIFT           8
162 #define CBAR_S1_BPSHCFG_MASK            3
163 #define CBAR_S1_BPSHCFG_NSH             3
164 #define CBAR_S1_MEMATTR_SHIFT           12
165 #define CBAR_S1_MEMATTR_MASK            0xf
166 #define CBAR_S1_MEMATTR_WB              0xf
167 #define CBAR_TYPE_SHIFT                 16
168 #define CBAR_TYPE_MASK                  0x3
169 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
170 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
171 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
172 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
173 #define CBAR_IRPTNDX_SHIFT              24
174 #define CBAR_IRPTNDX_MASK               0xff
175 
176 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
177 #define CBA2R_RW64_32BIT                (0 << 0)
178 #define CBA2R_RW64_64BIT                (1 << 0)
179 
180 /* Translation context bank */
181 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
182 #define ARM_SMMU_CB(smmu, n)            ((n) * (1 << (smmu)->pgshift))
183 
184 #define ARM_SMMU_CB_SCTLR               0x0
185 #define ARM_SMMU_CB_RESUME              0x8
186 #define ARM_SMMU_CB_TTBCR2              0x10
187 #define ARM_SMMU_CB_TTBR0_LO            0x20
188 #define ARM_SMMU_CB_TTBR0_HI            0x24
189 #define ARM_SMMU_CB_TTBR1_LO            0x28
190 #define ARM_SMMU_CB_TTBR1_HI            0x2c
191 #define ARM_SMMU_CB_TTBCR               0x30
192 #define ARM_SMMU_CB_S1_MAIR0            0x38
193 #define ARM_SMMU_CB_S1_MAIR1            0x3c
194 #define ARM_SMMU_CB_PAR_LO              0x50
195 #define ARM_SMMU_CB_PAR_HI              0x54
196 #define ARM_SMMU_CB_FSR                 0x58
197 #define ARM_SMMU_CB_FAR_LO              0x60
198 #define ARM_SMMU_CB_FAR_HI              0x64
199 #define ARM_SMMU_CB_FSYNR0              0x68
200 #define ARM_SMMU_CB_S1_TLBIVA           0x600
201 #define ARM_SMMU_CB_S1_TLBIASID         0x610
202 #define ARM_SMMU_CB_S1_TLBIVAL          0x620
203 #define ARM_SMMU_CB_S2_TLBIIPAS2        0x630
204 #define ARM_SMMU_CB_S2_TLBIIPAS2L       0x638
205 #define ARM_SMMU_CB_ATS1PR_LO           0x800
206 #define ARM_SMMU_CB_ATS1PR_HI           0x804
207 #define ARM_SMMU_CB_ATSR                0x8f0
208 
209 #define SCTLR_S1_ASIDPNE                (1 << 12)
210 #define SCTLR_CFCFG                     (1 << 7)
211 #define SCTLR_CFIE                      (1 << 6)
212 #define SCTLR_CFRE                      (1 << 5)
213 #define SCTLR_E                         (1 << 4)
214 #define SCTLR_AFE                       (1 << 2)
215 #define SCTLR_TRE                       (1 << 1)
216 #define SCTLR_M                         (1 << 0)
217 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
218 
219 #define CB_PAR_F                        (1 << 0)
220 
221 #define ATSR_ACTIVE                     (1 << 0)
222 
223 #define RESUME_RETRY                    (0 << 0)
224 #define RESUME_TERMINATE                (1 << 0)
225 
226 #define TTBCR2_SEP_SHIFT                15
227 #define TTBCR2_SEP_MASK                 0x7
228 
229 #define TTBCR2_ADDR_32                  0
230 #define TTBCR2_ADDR_36                  1
231 #define TTBCR2_ADDR_40                  2
232 #define TTBCR2_ADDR_42                  3
233 #define TTBCR2_ADDR_44                  4
234 #define TTBCR2_ADDR_48                  5
235 
236 #define TTBRn_HI_ASID_SHIFT            16
237 
238 #define FSR_MULTI                       (1 << 31)
239 #define FSR_SS                          (1 << 30)
240 #define FSR_UUT                         (1 << 8)
241 #define FSR_ASF                         (1 << 7)
242 #define FSR_TLBLKF                      (1 << 6)
243 #define FSR_TLBMCF                      (1 << 5)
244 #define FSR_EF                          (1 << 4)
245 #define FSR_PF                          (1 << 3)
246 #define FSR_AFF                         (1 << 2)
247 #define FSR_TF                          (1 << 1)
248 
249 #define FSR_IGN                         (FSR_AFF | FSR_ASF | \
250                                          FSR_TLBMCF | FSR_TLBLKF)
251 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT | \
252                                          FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
253 
254 #define FSYNR0_WNR                      (1 << 4)
255 
256 static int force_stage;
257 module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR);
258 MODULE_PARM_DESC(force_stage,
259         "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
260 
261 enum arm_smmu_arch_version {
262         ARM_SMMU_V1 = 1,
263         ARM_SMMU_V2,
264 };
265 
266 struct arm_smmu_smr {
267         u8                              idx;
268         u16                             mask;
269         u16                             id;
270 };
271 
272 struct arm_smmu_master_cfg {
273         int                             num_streamids;
274         u16                             streamids[MAX_MASTER_STREAMIDS];
275         struct arm_smmu_smr             *smrs;
276 };
277 
278 struct arm_smmu_master {
279         struct device_node              *of_node;
280         struct rb_node                  node;
281         struct arm_smmu_master_cfg      cfg;
282 };
283 
284 struct arm_smmu_device {
285         struct device                   *dev;
286 
287         void __iomem                    *base;
288         unsigned long                   size;
289         unsigned long                   pgshift;
290 
291 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
292 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
293 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
294 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
295 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
296 #define ARM_SMMU_FEAT_TRANS_OPS         (1 << 5)
297         u32                             features;
298 
299 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
300         u32                             options;
301         enum arm_smmu_arch_version      version;
302 
303         u32                             num_context_banks;
304         u32                             num_s2_context_banks;
305         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
306         atomic_t                        irptndx;
307 
308         u32                             num_mapping_groups;
309         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
310 
311         unsigned long                   va_size;
312         unsigned long                   ipa_size;
313         unsigned long                   pa_size;
314 
315         u32                             num_global_irqs;
316         u32                             num_context_irqs;
317         unsigned int                    *irqs;
318 
319         struct list_head                list;
320         struct rb_root                  masters;
321 };
322 
323 struct arm_smmu_cfg {
324         u8                              cbndx;
325         u8                              irptndx;
326         u32                             cbar;
327 };
328 #define INVALID_IRPTNDX                 0xff
329 
330 #define ARM_SMMU_CB_ASID(cfg)           ((cfg)->cbndx)
331 #define ARM_SMMU_CB_VMID(cfg)           ((cfg)->cbndx + 1)
332 
333 enum arm_smmu_domain_stage {
334         ARM_SMMU_DOMAIN_S1 = 0,
335         ARM_SMMU_DOMAIN_S2,
336         ARM_SMMU_DOMAIN_NESTED,
337 };
338 
339 struct arm_smmu_domain {
340         struct arm_smmu_device          *smmu;
341         struct io_pgtable_ops           *pgtbl_ops;
342         spinlock_t                      pgtbl_lock;
343         struct arm_smmu_cfg             cfg;
344         enum arm_smmu_domain_stage      stage;
345         struct mutex                    init_mutex; /* Protects smmu pointer */
346 };
347 
348 static struct iommu_ops arm_smmu_ops;
349 
350 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
351 static LIST_HEAD(arm_smmu_devices);
352 
353 struct arm_smmu_option_prop {
354         u32 opt;
355         const char *prop;
356 };
357 
358 static struct arm_smmu_option_prop arm_smmu_options[] = {
359         { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
360         { 0, NULL},
361 };
362 
363 static void parse_driver_options(struct arm_smmu_device *smmu)
364 {
365         int i = 0;
366 
367         do {
368                 if (of_property_read_bool(smmu->dev->of_node,
369                                                 arm_smmu_options[i].prop)) {
370                         smmu->options |= arm_smmu_options[i].opt;
371                         dev_notice(smmu->dev, "option %s\n",
372                                 arm_smmu_options[i].prop);
373                 }
374         } while (arm_smmu_options[++i].opt);
375 }
376 
377 static struct device_node *dev_get_dev_node(struct device *dev)
378 {
379         if (dev_is_pci(dev)) {
380                 struct pci_bus *bus = to_pci_dev(dev)->bus;
381 
382                 while (!pci_is_root_bus(bus))
383                         bus = bus->parent;
384                 return bus->bridge->parent->of_node;
385         }
386 
387         return dev->of_node;
388 }
389 
390 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
391                                                 struct device_node *dev_node)
392 {
393         struct rb_node *node = smmu->masters.rb_node;
394 
395         while (node) {
396                 struct arm_smmu_master *master;
397 
398                 master = container_of(node, struct arm_smmu_master, node);
399 
400                 if (dev_node < master->of_node)
401                         node = node->rb_left;
402                 else if (dev_node > master->of_node)
403                         node = node->rb_right;
404                 else
405                         return master;
406         }
407 
408         return NULL;
409 }
410 
411 static struct arm_smmu_master_cfg *
412 find_smmu_master_cfg(struct device *dev)
413 {
414         struct arm_smmu_master_cfg *cfg = NULL;
415         struct iommu_group *group = iommu_group_get(dev);
416 
417         if (group) {
418                 cfg = iommu_group_get_iommudata(group);
419                 iommu_group_put(group);
420         }
421 
422         return cfg;
423 }
424 
425 static int insert_smmu_master(struct arm_smmu_device *smmu,
426                               struct arm_smmu_master *master)
427 {
428         struct rb_node **new, *parent;
429 
430         new = &smmu->masters.rb_node;
431         parent = NULL;
432         while (*new) {
433                 struct arm_smmu_master *this
434                         = container_of(*new, struct arm_smmu_master, node);
435 
436                 parent = *new;
437                 if (master->of_node < this->of_node)
438                         new = &((*new)->rb_left);
439                 else if (master->of_node > this->of_node)
440                         new = &((*new)->rb_right);
441                 else
442                         return -EEXIST;
443         }
444 
445         rb_link_node(&master->node, parent, new);
446         rb_insert_color(&master->node, &smmu->masters);
447         return 0;
448 }
449 
450 static int register_smmu_master(struct arm_smmu_device *smmu,
451                                 struct device *dev,
452                                 struct of_phandle_args *masterspec)
453 {
454         int i;
455         struct arm_smmu_master *master;
456 
457         master = find_smmu_master(smmu, masterspec->np);
458         if (master) {
459                 dev_err(dev,
460                         "rejecting multiple registrations for master device %s\n",
461                         masterspec->np->name);
462                 return -EBUSY;
463         }
464 
465         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
466                 dev_err(dev,
467                         "reached maximum number (%d) of stream IDs for master device %s\n",
468                         MAX_MASTER_STREAMIDS, masterspec->np->name);
469                 return -ENOSPC;
470         }
471 
472         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
473         if (!master)
474                 return -ENOMEM;
475 
476         master->of_node                 = masterspec->np;
477         master->cfg.num_streamids       = masterspec->args_count;
478 
479         for (i = 0; i < master->cfg.num_streamids; ++i) {
480                 u16 streamid = masterspec->args[i];
481 
482                 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
483                      (streamid >= smmu->num_mapping_groups)) {
484                         dev_err(dev,
485                                 "stream ID for master device %s greater than maximum allowed (%d)\n",
486                                 masterspec->np->name, smmu->num_mapping_groups);
487                         return -ERANGE;
488                 }
489                 master->cfg.streamids[i] = streamid;
490         }
491         return insert_smmu_master(smmu, master);
492 }
493 
494 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
495 {
496         struct arm_smmu_device *smmu;
497         struct arm_smmu_master *master = NULL;
498         struct device_node *dev_node = dev_get_dev_node(dev);
499 
500         spin_lock(&arm_smmu_devices_lock);
501         list_for_each_entry(smmu, &arm_smmu_devices, list) {
502                 master = find_smmu_master(smmu, dev_node);
503                 if (master)
504                         break;
505         }
506         spin_unlock(&arm_smmu_devices_lock);
507 
508         return master ? smmu : NULL;
509 }
510 
511 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
512 {
513         int idx;
514 
515         do {
516                 idx = find_next_zero_bit(map, end, start);
517                 if (idx == end)
518                         return -ENOSPC;
519         } while (test_and_set_bit(idx, map));
520 
521         return idx;
522 }
523 
524 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
525 {
526         clear_bit(idx, map);
527 }
528 
529 /* Wait for any pending TLB invalidations to complete */
530 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
531 {
532         int count = 0;
533         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
534 
535         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
536         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
537                & sTLBGSTATUS_GSACTIVE) {
538                 cpu_relax();
539                 if (++count == TLB_LOOP_TIMEOUT) {
540                         dev_err_ratelimited(smmu->dev,
541                         "TLB sync timed out -- SMMU may be deadlocked\n");
542                         return;
543                 }
544                 udelay(1);
545         }
546 }
547 
548 static void arm_smmu_tlb_sync(void *cookie)
549 {
550         struct arm_smmu_domain *smmu_domain = cookie;
551         __arm_smmu_tlb_sync(smmu_domain->smmu);
552 }
553 
554 static void arm_smmu_tlb_inv_context(void *cookie)
555 {
556         struct arm_smmu_domain *smmu_domain = cookie;
557         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
558         struct arm_smmu_device *smmu = smmu_domain->smmu;
559         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
560         void __iomem *base;
561 
562         if (stage1) {
563                 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
564                 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
565                                base + ARM_SMMU_CB_S1_TLBIASID);
566         } else {
567                 base = ARM_SMMU_GR0(smmu);
568                 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
569                                base + ARM_SMMU_GR0_TLBIVMID);
570         }
571 
572         __arm_smmu_tlb_sync(smmu);
573 }
574 
575 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
576                                           bool leaf, void *cookie)
577 {
578         struct arm_smmu_domain *smmu_domain = cookie;
579         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
580         struct arm_smmu_device *smmu = smmu_domain->smmu;
581         bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
582         void __iomem *reg;
583 
584         if (stage1) {
585                 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
586                 reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
587 
588                 if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
589                         iova &= ~12UL;
590                         iova |= ARM_SMMU_CB_ASID(cfg);
591                         writel_relaxed(iova, reg);
592 #ifdef CONFIG_64BIT
593                 } else {
594                         iova >>= 12;
595                         iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
596                         writeq_relaxed(iova, reg);
597 #endif
598                 }
599 #ifdef CONFIG_64BIT
600         } else if (smmu->version == ARM_SMMU_V2) {
601                 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
602                 reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
603                               ARM_SMMU_CB_S2_TLBIIPAS2;
604                 writeq_relaxed(iova >> 12, reg);
605 #endif
606         } else {
607                 reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
608                 writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
609         }
610 }
611 
612 static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
613 {
614         struct arm_smmu_domain *smmu_domain = cookie;
615         struct arm_smmu_device *smmu = smmu_domain->smmu;
616         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
617 
618 
619         /* Ensure new page tables are visible to the hardware walker */
620         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
621                 dsb(ishst);
622         } else {
623                 /*
624                  * If the SMMU can't walk tables in the CPU caches, treat them
625                  * like non-coherent DMA since we need to flush the new entries
626                  * all the way out to memory. There's no possibility of
627                  * recursion here as the SMMU table walker will not be wired
628                  * through another SMMU.
629                  */
630                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
631                              DMA_TO_DEVICE);
632         }
633 }
634 
635 static struct iommu_gather_ops arm_smmu_gather_ops = {
636         .tlb_flush_all  = arm_smmu_tlb_inv_context,
637         .tlb_add_flush  = arm_smmu_tlb_inv_range_nosync,
638         .tlb_sync       = arm_smmu_tlb_sync,
639         .flush_pgtable  = arm_smmu_flush_pgtable,
640 };
641 
642 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
643 {
644         int flags, ret;
645         u32 fsr, far, fsynr, resume;
646         unsigned long iova;
647         struct iommu_domain *domain = dev;
648         struct arm_smmu_domain *smmu_domain = domain->priv;
649         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
650         struct arm_smmu_device *smmu = smmu_domain->smmu;
651         void __iomem *cb_base;
652 
653         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
654         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
655 
656         if (!(fsr & FSR_FAULT))
657                 return IRQ_NONE;
658 
659         if (fsr & FSR_IGN)
660                 dev_err_ratelimited(smmu->dev,
661                                     "Unexpected context fault (fsr 0x%x)\n",
662                                     fsr);
663 
664         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
665         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
666 
667         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
668         iova = far;
669 #ifdef CONFIG_64BIT
670         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
671         iova |= ((unsigned long)far << 32);
672 #endif
673 
674         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
675                 ret = IRQ_HANDLED;
676                 resume = RESUME_RETRY;
677         } else {
678                 dev_err_ratelimited(smmu->dev,
679                     "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
680                     iova, fsynr, cfg->cbndx);
681                 ret = IRQ_NONE;
682                 resume = RESUME_TERMINATE;
683         }
684 
685         /* Clear the faulting FSR */
686         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
687 
688         /* Retry or terminate any stalled transactions */
689         if (fsr & FSR_SS)
690                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
691 
692         return ret;
693 }
694 
695 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
696 {
697         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
698         struct arm_smmu_device *smmu = dev;
699         void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
700 
701         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
702         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
703         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
704         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
705 
706         if (!gfsr)
707                 return IRQ_NONE;
708 
709         dev_err_ratelimited(smmu->dev,
710                 "Unexpected global fault, this could be serious\n");
711         dev_err_ratelimited(smmu->dev,
712                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
713                 gfsr, gfsynr0, gfsynr1, gfsynr2);
714 
715         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
716         return IRQ_HANDLED;
717 }
718 
719 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
720                                        struct io_pgtable_cfg *pgtbl_cfg)
721 {
722         u32 reg;
723         bool stage1;
724         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
725         struct arm_smmu_device *smmu = smmu_domain->smmu;
726         void __iomem *cb_base, *gr0_base, *gr1_base;
727 
728         gr0_base = ARM_SMMU_GR0(smmu);
729         gr1_base = ARM_SMMU_GR1(smmu);
730         stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
731         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
732 
733         /* CBAR */
734         reg = cfg->cbar;
735         if (smmu->version == ARM_SMMU_V1)
736                 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
737 
738         /*
739          * Use the weakest shareability/memory types, so they are
740          * overridden by the ttbcr/pte.
741          */
742         if (stage1) {
743                 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
744                         (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
745         } else {
746                 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
747         }
748         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
749 
750         if (smmu->version > ARM_SMMU_V1) {
751                 /* CBA2R */
752 #ifdef CONFIG_64BIT
753                 reg = CBA2R_RW64_64BIT;
754 #else
755                 reg = CBA2R_RW64_32BIT;
756 #endif
757                 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
758         }
759 
760         /* TTBRs */
761         if (stage1) {
762                 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
763                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
764                 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32;
765                 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
766                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
767 
768                 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
769                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);
770                 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32;
771                 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
772                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);
773         } else {
774                 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
775                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
776                 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32;
777                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
778         }
779 
780         /* TTBCR */
781         if (stage1) {
782                 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
783                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
784                 if (smmu->version > ARM_SMMU_V1) {
785                         reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
786                         switch (smmu->va_size) {
787                         case 32:
788                                 reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
789                                 break;
790                         case 36:
791                                 reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
792                                 break;
793                         case 40:
794                                 reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
795                                 break;
796                         case 42:
797                                 reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
798                                 break;
799                         case 44:
800                                 reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
801                                 break;
802                         case 48:
803                                 reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
804                                 break;
805                         }
806                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
807                 }
808         } else {
809                 reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
810                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
811         }
812 
813         /* MAIRs (stage-1 only) */
814         if (stage1) {
815                 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
816                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
817                 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
818                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
819         }
820 
821         /* SCTLR */
822         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
823         if (stage1)
824                 reg |= SCTLR_S1_ASIDPNE;
825 #ifdef __BIG_ENDIAN
826         reg |= SCTLR_E;
827 #endif
828         writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
829 }
830 
831 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
832                                         struct arm_smmu_device *smmu)
833 {
834         int irq, start, ret = 0;
835         unsigned long ias, oas;
836         struct io_pgtable_ops *pgtbl_ops;
837         struct io_pgtable_cfg pgtbl_cfg;
838         enum io_pgtable_fmt fmt;
839         struct arm_smmu_domain *smmu_domain = domain->priv;
840         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
841 
842         mutex_lock(&smmu_domain->init_mutex);
843         if (smmu_domain->smmu)
844                 goto out_unlock;
845 
846         /*
847          * Mapping the requested stage onto what we support is surprisingly
848          * complicated, mainly because the spec allows S1+S2 SMMUs without
849          * support for nested translation. That means we end up with the
850          * following table:
851          *
852          * Requested        Supported        Actual
853          *     S1               N              S1
854          *     S1             S1+S2            S1
855          *     S1               S2             S2
856          *     S1               S1             S1
857          *     N                N              N
858          *     N              S1+S2            S2
859          *     N                S2             S2
860          *     N                S1             S1
861          *
862          * Note that you can't actually request stage-2 mappings.
863          */
864         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
865                 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
866         if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
867                 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
868 
869         switch (smmu_domain->stage) {
870         case ARM_SMMU_DOMAIN_S1:
871                 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
872                 start = smmu->num_s2_context_banks;
873                 ias = smmu->va_size;
874                 oas = smmu->ipa_size;
875                 if (IS_ENABLED(CONFIG_64BIT))
876                         fmt = ARM_64_LPAE_S1;
877                 else
878                         fmt = ARM_32_LPAE_S1;
879                 break;
880         case ARM_SMMU_DOMAIN_NESTED:
881                 /*
882                  * We will likely want to change this if/when KVM gets
883                  * involved.
884                  */
885         case ARM_SMMU_DOMAIN_S2:
886                 cfg->cbar = CBAR_TYPE_S2_TRANS;
887                 start = 0;
888                 ias = smmu->ipa_size;
889                 oas = smmu->pa_size;
890                 if (IS_ENABLED(CONFIG_64BIT))
891                         fmt = ARM_64_LPAE_S2;
892                 else
893                         fmt = ARM_32_LPAE_S2;
894                 break;
895         default:
896                 ret = -EINVAL;
897                 goto out_unlock;
898         }
899 
900         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
901                                       smmu->num_context_banks);
902         if (IS_ERR_VALUE(ret))
903                 goto out_unlock;
904 
905         cfg->cbndx = ret;
906         if (smmu->version == ARM_SMMU_V1) {
907                 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
908                 cfg->irptndx %= smmu->num_context_irqs;
909         } else {
910                 cfg->irptndx = cfg->cbndx;
911         }
912 
913         pgtbl_cfg = (struct io_pgtable_cfg) {
914                 .pgsize_bitmap  = arm_smmu_ops.pgsize_bitmap,
915                 .ias            = ias,
916                 .oas            = oas,
917                 .tlb            = &arm_smmu_gather_ops,
918         };
919 
920         smmu_domain->smmu = smmu;
921         pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
922         if (!pgtbl_ops) {
923                 ret = -ENOMEM;
924                 goto out_clear_smmu;
925         }
926 
927         /* Update our support page sizes to reflect the page table format */
928         arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
929 
930         /* Initialise the context bank with our page table cfg */
931         arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
932 
933         /*
934          * Request context fault interrupt. Do this last to avoid the
935          * handler seeing a half-initialised domain state.
936          */
937         irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
938         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
939                           "arm-smmu-context-fault", domain);
940         if (IS_ERR_VALUE(ret)) {
941                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
942                         cfg->irptndx, irq);
943                 cfg->irptndx = INVALID_IRPTNDX;
944         }
945 
946         mutex_unlock(&smmu_domain->init_mutex);
947 
948         /* Publish page table ops for map/unmap */
949         smmu_domain->pgtbl_ops = pgtbl_ops;
950         return 0;
951 
952 out_clear_smmu:
953         smmu_domain->smmu = NULL;
954 out_unlock:
955         mutex_unlock(&smmu_domain->init_mutex);
956         return ret;
957 }
958 
959 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
960 {
961         struct arm_smmu_domain *smmu_domain = domain->priv;
962         struct arm_smmu_device *smmu = smmu_domain->smmu;
963         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
964         void __iomem *cb_base;
965         int irq;
966 
967         if (!smmu)
968                 return;
969 
970         /*
971          * Disable the context bank and free the page tables before freeing
972          * it.
973          */
974         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
975         writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
976 
977         if (cfg->irptndx != INVALID_IRPTNDX) {
978                 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
979                 free_irq(irq, domain);
980         }
981 
982         if (smmu_domain->pgtbl_ops)
983                 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
984 
985         __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
986 }
987 
988 static int arm_smmu_domain_init(struct iommu_domain *domain)
989 {
990         struct arm_smmu_domain *smmu_domain;
991 
992         /*
993          * Allocate the domain and initialise some of its data structures.
994          * We can't really do anything meaningful until we've added a
995          * master.
996          */
997         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
998         if (!smmu_domain)
999                 return -ENOMEM;
1000 
1001         mutex_init(&smmu_domain->init_mutex);
1002         spin_lock_init(&smmu_domain->pgtbl_lock);
1003         domain->priv = smmu_domain;
1004         return 0;
1005 }
1006 
1007 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1008 {
1009         struct arm_smmu_domain *smmu_domain = domain->priv;
1010 
1011         /*
1012          * Free the domain resources. We assume that all devices have
1013          * already been detached.
1014          */
1015         arm_smmu_destroy_domain_context(domain);
1016         kfree(smmu_domain);
1017 }
1018 
1019 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1020                                           struct arm_smmu_master_cfg *cfg)
1021 {
1022         int i;
1023         struct arm_smmu_smr *smrs;
1024         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1025 
1026         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1027                 return 0;
1028 
1029         if (cfg->smrs)
1030                 return -EEXIST;
1031 
1032         smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1033         if (!smrs) {
1034                 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1035                         cfg->num_streamids);
1036                 return -ENOMEM;
1037         }
1038 
1039         /* Allocate the SMRs on the SMMU */
1040         for (i = 0; i < cfg->num_streamids; ++i) {
1041                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1042                                                   smmu->num_mapping_groups);
1043                 if (IS_ERR_VALUE(idx)) {
1044                         dev_err(smmu->dev, "failed to allocate free SMR\n");
1045                         goto err_free_smrs;
1046                 }
1047 
1048                 smrs[i] = (struct arm_smmu_smr) {
1049                         .idx    = idx,
1050                         .mask   = 0, /* We don't currently share SMRs */
1051                         .id     = cfg->streamids[i],
1052                 };
1053         }
1054 
1055         /* It worked! Now, poke the actual hardware */
1056         for (i = 0; i < cfg->num_streamids; ++i) {
1057                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1058                           smrs[i].mask << SMR_MASK_SHIFT;
1059                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1060         }
1061 
1062         cfg->smrs = smrs;
1063         return 0;
1064 
1065 err_free_smrs:
1066         while (--i >= 0)
1067                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1068         kfree(smrs);
1069         return -ENOSPC;
1070 }
1071 
1072 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1073                                       struct arm_smmu_master_cfg *cfg)
1074 {
1075         int i;
1076         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1077         struct arm_smmu_smr *smrs = cfg->smrs;
1078 
1079         if (!smrs)
1080                 return;
1081 
1082         /* Invalidate the SMRs before freeing back to the allocator */
1083         for (i = 0; i < cfg->num_streamids; ++i) {
1084                 u8 idx = smrs[i].idx;
1085 
1086                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1087                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1088         }
1089 
1090         cfg->smrs = NULL;
1091         kfree(smrs);
1092 }
1093 
1094 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1095                                       struct arm_smmu_master_cfg *cfg)
1096 {
1097         int i, ret;
1098         struct arm_smmu_device *smmu = smmu_domain->smmu;
1099         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1100 
1101         /* Devices in an IOMMU group may already be configured */
1102         ret = arm_smmu_master_configure_smrs(smmu, cfg);
1103         if (ret)
1104                 return ret == -EEXIST ? 0 : ret;
1105 
1106         for (i = 0; i < cfg->num_streamids; ++i) {
1107                 u32 idx, s2cr;
1108 
1109                 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1110                 s2cr = S2CR_TYPE_TRANS |
1111                        (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1112                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1113         }
1114 
1115         return 0;
1116 }
1117 
1118 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1119                                           struct arm_smmu_master_cfg *cfg)
1120 {
1121         int i;
1122         struct arm_smmu_device *smmu = smmu_domain->smmu;
1123         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1124 
1125         /* An IOMMU group is torn down by the first device to be removed */
1126         if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1127                 return;
1128 
1129         /*
1130          * We *must* clear the S2CR first, because freeing the SMR means
1131          * that it can be re-allocated immediately.
1132          */
1133         for (i = 0; i < cfg->num_streamids; ++i) {
1134                 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1135 
1136                 writel_relaxed(S2CR_TYPE_BYPASS,
1137                                gr0_base + ARM_SMMU_GR0_S2CR(idx));
1138         }
1139 
1140         arm_smmu_master_free_smrs(smmu, cfg);
1141 }
1142 
1143 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1144 {
1145         int ret;
1146         struct arm_smmu_domain *smmu_domain = domain->priv;
1147         struct arm_smmu_device *smmu;
1148         struct arm_smmu_master_cfg *cfg;
1149 
1150         smmu = find_smmu_for_device(dev);
1151         if (!smmu) {
1152                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1153                 return -ENXIO;
1154         }
1155 
1156         if (dev->archdata.iommu) {
1157                 dev_err(dev, "already attached to IOMMU domain\n");
1158                 return -EEXIST;
1159         }
1160 
1161         /* Ensure that the domain is finalised */
1162         ret = arm_smmu_init_domain_context(domain, smmu);
1163         if (IS_ERR_VALUE(ret))
1164                 return ret;
1165 
1166         /*
1167          * Sanity check the domain. We don't support domains across
1168          * different SMMUs.
1169          */
1170         if (smmu_domain->smmu != smmu) {
1171                 dev_err(dev,
1172                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1173                         dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1174                 return -EINVAL;
1175         }
1176 
1177         /* Looks ok, so add the device to the domain */
1178         cfg = find_smmu_master_cfg(dev);
1179         if (!cfg)
1180                 return -ENODEV;
1181 
1182         ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1183         if (!ret)
1184                 dev->archdata.iommu = domain;
1185         return ret;
1186 }
1187 
1188 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1189 {
1190         struct arm_smmu_domain *smmu_domain = domain->priv;
1191         struct arm_smmu_master_cfg *cfg;
1192 
1193         cfg = find_smmu_master_cfg(dev);
1194         if (!cfg)
1195                 return;
1196 
1197         dev->archdata.iommu = NULL;
1198         arm_smmu_domain_remove_master(smmu_domain, cfg);
1199 }
1200 
1201 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1202                         phys_addr_t paddr, size_t size, int prot)
1203 {
1204         int ret;
1205         unsigned long flags;
1206         struct arm_smmu_domain *smmu_domain = domain->priv;
1207         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1208 
1209         if (!ops)
1210                 return -ENODEV;
1211 
1212         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1213         ret = ops->map(ops, iova, paddr, size, prot);
1214         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1215         return ret;
1216 }
1217 
1218 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1219                              size_t size)
1220 {
1221         size_t ret;
1222         unsigned long flags;
1223         struct arm_smmu_domain *smmu_domain = domain->priv;
1224         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1225 
1226         if (!ops)
1227                 return 0;
1228 
1229         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1230         ret = ops->unmap(ops, iova, size);
1231         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1232         return ret;
1233 }
1234 
1235 static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1236                                               dma_addr_t iova)
1237 {
1238         struct arm_smmu_domain *smmu_domain = domain->priv;
1239         struct arm_smmu_device *smmu = smmu_domain->smmu;
1240         struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1241         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1242         struct device *dev = smmu->dev;
1243         void __iomem *cb_base;
1244         u32 tmp;
1245         u64 phys;
1246 
1247         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1248 
1249         if (smmu->version == 1) {
1250                 u32 reg = iova & ~0xfff;
1251                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
1252         } else {
1253                 u32 reg = iova & ~0xfff;
1254                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
1255                 reg = ((u64)iova & ~0xfff) >> 32;
1256                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
1257         }
1258 
1259         if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
1260                                       !(tmp & ATSR_ACTIVE), 5, 50)) {
1261                 dev_err(dev,
1262                         "iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
1263                         &iova);
1264                 return ops->iova_to_phys(ops, iova);
1265         }
1266 
1267         phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
1268         phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
1269 
1270         if (phys & CB_PAR_F) {
1271                 dev_err(dev, "translation fault!\n");
1272                 dev_err(dev, "PAR = 0x%llx\n", phys);
1273                 return 0;
1274         }
1275 
1276         return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
1277 }
1278 
1279 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1280                                         dma_addr_t iova)
1281 {
1282         phys_addr_t ret;
1283         unsigned long flags;
1284         struct arm_smmu_domain *smmu_domain = domain->priv;
1285         struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1286 
1287         if (!ops)
1288                 return 0;
1289 
1290         spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1291         if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
1292                         smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1293                 ret = arm_smmu_iova_to_phys_hard(domain, iova);
1294         } else {
1295                 ret = ops->iova_to_phys(ops, iova);
1296         }
1297 
1298         spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1299 
1300         return ret;
1301 }
1302 
1303 static bool arm_smmu_capable(enum iommu_cap cap)
1304 {
1305         switch (cap) {
1306         case IOMMU_CAP_CACHE_COHERENCY:
1307                 /*
1308                  * Return true here as the SMMU can always send out coherent
1309                  * requests.
1310                  */
1311                 return true;
1312         case IOMMU_CAP_INTR_REMAP:
1313                 return true; /* MSIs are just memory writes */
1314         case IOMMU_CAP_NOEXEC:
1315                 return true;
1316         default:
1317                 return false;
1318         }
1319 }
1320 
1321 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1322 {
1323         *((u16 *)data) = alias;
1324         return 0; /* Continue walking */
1325 }
1326 
1327 static void __arm_smmu_release_pci_iommudata(void *data)
1328 {
1329         kfree(data);
1330 }
1331 
1332 static int arm_smmu_add_device(struct device *dev)
1333 {
1334         struct arm_smmu_device *smmu;
1335         struct arm_smmu_master_cfg *cfg;
1336         struct iommu_group *group;
1337         void (*releasefn)(void *) = NULL;
1338         int ret;
1339 
1340         smmu = find_smmu_for_device(dev);
1341         if (!smmu)
1342                 return -ENODEV;
1343 
1344         group = iommu_group_alloc();
1345         if (IS_ERR(group)) {
1346                 dev_err(dev, "Failed to allocate IOMMU group\n");
1347                 return PTR_ERR(group);
1348         }
1349 
1350         if (dev_is_pci(dev)) {
1351                 struct pci_dev *pdev = to_pci_dev(dev);
1352 
1353                 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1354                 if (!cfg) {
1355                         ret = -ENOMEM;
1356                         goto out_put_group;
1357                 }
1358 
1359                 cfg->num_streamids = 1;
1360                 /*
1361                  * Assume Stream ID == Requester ID for now.
1362                  * We need a way to describe the ID mappings in FDT.
1363                  */
1364                 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1365                                        &cfg->streamids[0]);
1366                 releasefn = __arm_smmu_release_pci_iommudata;
1367         } else {
1368                 struct arm_smmu_master *master;
1369 
1370                 master = find_smmu_master(smmu, dev->of_node);
1371                 if (!master) {
1372                         ret = -ENODEV;
1373                         goto out_put_group;
1374                 }
1375 
1376                 cfg = &master->cfg;
1377         }
1378 
1379         iommu_group_set_iommudata(group, cfg, releasefn);
1380         ret = iommu_group_add_device(group, dev);
1381 
1382 out_put_group:
1383         iommu_group_put(group);
1384         return ret;
1385 }
1386 
1387 static void arm_smmu_remove_device(struct device *dev)
1388 {
1389         iommu_group_remove_device(dev);
1390 }
1391 
1392 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1393                                     enum iommu_attr attr, void *data)
1394 {
1395         struct arm_smmu_domain *smmu_domain = domain->priv;
1396 
1397         switch (attr) {
1398         case DOMAIN_ATTR_NESTING:
1399                 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1400                 return 0;
1401         default:
1402                 return -ENODEV;
1403         }
1404 }
1405 
1406 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1407                                     enum iommu_attr attr, void *data)
1408 {
1409         int ret = 0;
1410         struct arm_smmu_domain *smmu_domain = domain->priv;
1411 
1412         mutex_lock(&smmu_domain->init_mutex);
1413 
1414         switch (attr) {
1415         case DOMAIN_ATTR_NESTING:
1416                 if (smmu_domain->smmu) {
1417                         ret = -EPERM;
1418                         goto out_unlock;
1419                 }
1420 
1421                 if (*(int *)data)
1422                         smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1423                 else
1424                         smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1425 
1426                 break;
1427         default:
1428                 ret = -ENODEV;
1429         }
1430 
1431 out_unlock:
1432         mutex_unlock(&smmu_domain->init_mutex);
1433         return ret;
1434 }
1435 
1436 static struct iommu_ops arm_smmu_ops = {
1437         .capable                = arm_smmu_capable,
1438         .domain_init            = arm_smmu_domain_init,
1439         .domain_destroy         = arm_smmu_domain_destroy,
1440         .attach_dev             = arm_smmu_attach_dev,
1441         .detach_dev             = arm_smmu_detach_dev,
1442         .map                    = arm_smmu_map,
1443         .unmap                  = arm_smmu_unmap,
1444         .map_sg                 = default_iommu_map_sg,
1445         .iova_to_phys           = arm_smmu_iova_to_phys,
1446         .add_device             = arm_smmu_add_device,
1447         .remove_device          = arm_smmu_remove_device,
1448         .domain_get_attr        = arm_smmu_domain_get_attr,
1449         .domain_set_attr        = arm_smmu_domain_set_attr,
1450         .pgsize_bitmap          = -1UL, /* Restricted during device attach */
1451 };
1452 
1453 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1454 {
1455         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1456         void __iomem *cb_base;
1457         int i = 0;
1458         u32 reg;
1459 
1460         /* clear global FSR */
1461         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1462         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1463 
1464         /* Mark all SMRn as invalid and all S2CRn as bypass */
1465         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1466                 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1467                 writel_relaxed(S2CR_TYPE_BYPASS,
1468                         gr0_base + ARM_SMMU_GR0_S2CR(i));
1469         }
1470 
1471         /* Make sure all context banks are disabled and clear CB_FSR  */
1472         for (i = 0; i < smmu->num_context_banks; ++i) {
1473                 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1474                 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1475                 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1476         }
1477 
1478         /* Invalidate the TLB, just in case */
1479         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1480         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1481 
1482         reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1483 
1484         /* Enable fault reporting */
1485         reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1486 
1487         /* Disable TLB broadcasting. */
1488         reg |= (sCR0_VMIDPNE | sCR0_PTM);
1489 
1490         /* Enable client access, but bypass when no mapping is found */
1491         reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1492 
1493         /* Disable forced broadcasting */
1494         reg &= ~sCR0_FB;
1495 
1496         /* Don't upgrade barriers */
1497         reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1498 
1499         /* Push the button */
1500         __arm_smmu_tlb_sync(smmu);
1501         writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1502 }
1503 
1504 static int arm_smmu_id_size_to_bits(int size)
1505 {
1506         switch (size) {
1507         case 0:
1508                 return 32;
1509         case 1:
1510                 return 36;
1511         case 2:
1512                 return 40;
1513         case 3:
1514                 return 42;
1515         case 4:
1516                 return 44;
1517         case 5:
1518         default:
1519                 return 48;
1520         }
1521 }
1522 
1523 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1524 {
1525         unsigned long size;
1526         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1527         u32 id;
1528 
1529         dev_notice(smmu->dev, "probing hardware configuration...\n");
1530         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1531 
1532         /* ID0 */
1533         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1534 
1535         /* Restrict available stages based on module parameter */
1536         if (force_stage == 1)
1537                 id &= ~(ID0_S2TS | ID0_NTS);
1538         else if (force_stage == 2)
1539                 id &= ~(ID0_S1TS | ID0_NTS);
1540 
1541         if (id & ID0_S1TS) {
1542                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1543                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1544         }
1545 
1546         if (id & ID0_S2TS) {
1547                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1548                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1549         }
1550 
1551         if (id & ID0_NTS) {
1552                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1553                 dev_notice(smmu->dev, "\tnested translation\n");
1554         }
1555 
1556         if (!(smmu->features &
1557                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1558                 dev_err(smmu->dev, "\tno translation support!\n");
1559                 return -ENODEV;
1560         }
1561 
1562         if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
1563                 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
1564                 dev_notice(smmu->dev, "\taddress translation ops\n");
1565         }
1566 
1567         if (id & ID0_CTTW) {
1568                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1569                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1570         }
1571 
1572         if (id & ID0_SMS) {
1573                 u32 smr, sid, mask;
1574 
1575                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1576                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1577                                            ID0_NUMSMRG_MASK;
1578                 if (smmu->num_mapping_groups == 0) {
1579                         dev_err(smmu->dev,
1580                                 "stream-matching supported, but no SMRs present!\n");
1581                         return -ENODEV;
1582                 }
1583 
1584                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1585                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1586                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1587                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1588 
1589                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1590                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1591                 if ((mask & sid) != sid) {
1592                         dev_err(smmu->dev,
1593                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1594                                 mask, sid);
1595                         return -ENODEV;
1596                 }
1597 
1598                 dev_notice(smmu->dev,
1599                            "\tstream matching with %u register groups, mask 0x%x",
1600                            smmu->num_mapping_groups, mask);
1601         } else {
1602                 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1603                                            ID0_NUMSIDB_MASK;
1604         }
1605 
1606         /* ID1 */
1607         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1608         smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1609 
1610         /* Check for size mismatch of SMMU address space from mapped region */
1611         size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1612         size *= 2 << smmu->pgshift;
1613         if (smmu->size != size)
1614                 dev_warn(smmu->dev,
1615                         "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1616                         size, smmu->size);
1617 
1618         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1619         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1620         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1621                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1622                 return -ENODEV;
1623         }
1624         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1625                    smmu->num_context_banks, smmu->num_s2_context_banks);
1626 
1627         /* ID2 */
1628         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1629         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1630         smmu->ipa_size = size;
1631 
1632         /* The output mask is also applied for bypass */
1633         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1634         smmu->pa_size = size;
1635 
1636         if (smmu->version == ARM_SMMU_V1) {
1637                 smmu->va_size = smmu->ipa_size;
1638                 size = SZ_4K | SZ_2M | SZ_1G;
1639         } else {
1640                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1641                 smmu->va_size = arm_smmu_id_size_to_bits(size);
1642 #ifndef CONFIG_64BIT
1643                 smmu->va_size = min(32UL, smmu->va_size);
1644 #endif
1645                 size = 0;
1646                 if (id & ID2_PTFS_4K)
1647                         size |= SZ_4K | SZ_2M | SZ_1G;
1648                 if (id & ID2_PTFS_16K)
1649                         size |= SZ_16K | SZ_32M;
1650                 if (id & ID2_PTFS_64K)
1651                         size |= SZ_64K | SZ_512M;
1652         }
1653 
1654         arm_smmu_ops.pgsize_bitmap &= size;
1655         dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size);
1656 
1657         if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1658                 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1659                            smmu->va_size, smmu->ipa_size);
1660 
1661         if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1662                 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1663                            smmu->ipa_size, smmu->pa_size);
1664 
1665         return 0;
1666 }
1667 
1668 static const struct of_device_id arm_smmu_of_match[] = {
1669         { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
1670         { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
1671         { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
1672         { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
1673         { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
1674         { },
1675 };
1676 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1677 
1678 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1679 {
1680         const struct of_device_id *of_id;
1681         struct resource *res;
1682         struct arm_smmu_device *smmu;
1683         struct device *dev = &pdev->dev;
1684         struct rb_node *node;
1685         struct of_phandle_args masterspec;
1686         int num_irqs, i, err;
1687 
1688         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1689         if (!smmu) {
1690                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1691                 return -ENOMEM;
1692         }
1693         smmu->dev = dev;
1694 
1695         of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1696         smmu->version = (enum arm_smmu_arch_version)of_id->data;
1697 
1698         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1699         smmu->base = devm_ioremap_resource(dev, res);
1700         if (IS_ERR(smmu->base))
1701                 return PTR_ERR(smmu->base);
1702         smmu->size = resource_size(res);
1703 
1704         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1705                                  &smmu->num_global_irqs)) {
1706                 dev_err(dev, "missing #global-interrupts property\n");
1707                 return -ENODEV;
1708         }
1709 
1710         num_irqs = 0;
1711         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1712                 num_irqs++;
1713                 if (num_irqs > smmu->num_global_irqs)
1714                         smmu->num_context_irqs++;
1715         }
1716 
1717         if (!smmu->num_context_irqs) {
1718                 dev_err(dev, "found %d interrupts but expected at least %d\n",
1719                         num_irqs, smmu->num_global_irqs + 1);
1720                 return -ENODEV;
1721         }
1722 
1723         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1724                                   GFP_KERNEL);
1725         if (!smmu->irqs) {
1726                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1727                 return -ENOMEM;
1728         }
1729 
1730         for (i = 0; i < num_irqs; ++i) {
1731                 int irq = platform_get_irq(pdev, i);
1732 
1733                 if (irq < 0) {
1734                         dev_err(dev, "failed to get irq index %d\n", i);
1735                         return -ENODEV;
1736                 }
1737                 smmu->irqs[i] = irq;
1738         }
1739 
1740         err = arm_smmu_device_cfg_probe(smmu);
1741         if (err)
1742                 return err;
1743 
1744         i = 0;
1745         smmu->masters = RB_ROOT;
1746         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1747                                            "#stream-id-cells", i,
1748                                            &masterspec)) {
1749                 err = register_smmu_master(smmu, dev, &masterspec);
1750                 if (err) {
1751                         dev_err(dev, "failed to add master %s\n",
1752                                 masterspec.np->name);
1753                         goto out_put_masters;
1754                 }
1755 
1756                 i++;
1757         }
1758         dev_notice(dev, "registered %d master devices\n", i);
1759 
1760         parse_driver_options(smmu);
1761 
1762         if (smmu->version > ARM_SMMU_V1 &&
1763             smmu->num_context_banks != smmu->num_context_irqs) {
1764                 dev_err(dev,
1765                         "found only %d context interrupt(s) but %d required\n",
1766                         smmu->num_context_irqs, smmu->num_context_banks);
1767                 err = -ENODEV;
1768                 goto out_put_masters;
1769         }
1770 
1771         for (i = 0; i < smmu->num_global_irqs; ++i) {
1772                 err = request_irq(smmu->irqs[i],
1773                                   arm_smmu_global_fault,
1774                                   IRQF_SHARED,
1775                                   "arm-smmu global fault",
1776                                   smmu);
1777                 if (err) {
1778                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1779                                 i, smmu->irqs[i]);
1780                         goto out_free_irqs;
1781                 }
1782         }
1783 
1784         INIT_LIST_HEAD(&smmu->list);
1785         spin_lock(&arm_smmu_devices_lock);
1786         list_add(&smmu->list, &arm_smmu_devices);
1787         spin_unlock(&arm_smmu_devices_lock);
1788 
1789         arm_smmu_device_reset(smmu);
1790         return 0;
1791 
1792 out_free_irqs:
1793         while (i--)
1794                 free_irq(smmu->irqs[i], smmu);
1795 
1796 out_put_masters:
1797         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1798                 struct arm_smmu_master *master
1799                         = container_of(node, struct arm_smmu_master, node);
1800                 of_node_put(master->of_node);
1801         }
1802 
1803         return err;
1804 }
1805 
1806 static int arm_smmu_device_remove(struct platform_device *pdev)
1807 {
1808         int i;
1809         struct device *dev = &pdev->dev;
1810         struct arm_smmu_device *curr, *smmu = NULL;
1811         struct rb_node *node;
1812 
1813         spin_lock(&arm_smmu_devices_lock);
1814         list_for_each_entry(curr, &arm_smmu_devices, list) {
1815                 if (curr->dev == dev) {
1816                         smmu = curr;
1817                         list_del(&smmu->list);
1818                         break;
1819                 }
1820         }
1821         spin_unlock(&arm_smmu_devices_lock);
1822 
1823         if (!smmu)
1824                 return -ENODEV;
1825 
1826         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1827                 struct arm_smmu_master *master
1828                         = container_of(node, struct arm_smmu_master, node);
1829                 of_node_put(master->of_node);
1830         }
1831 
1832         if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1833                 dev_err(dev, "removing device with active domains!\n");
1834 
1835         for (i = 0; i < smmu->num_global_irqs; ++i)
1836                 free_irq(smmu->irqs[i], smmu);
1837 
1838         /* Turn the thing off */
1839         writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1840         return 0;
1841 }
1842 
1843 static struct platform_driver arm_smmu_driver = {
1844         .driver = {
1845                 .name           = "arm-smmu",
1846                 .of_match_table = of_match_ptr(arm_smmu_of_match),
1847         },
1848         .probe  = arm_smmu_device_dt_probe,
1849         .remove = arm_smmu_device_remove,
1850 };
1851 
1852 static int __init arm_smmu_init(void)
1853 {
1854         struct device_node *np;
1855         int ret;
1856 
1857         /*
1858          * Play nice with systems that don't have an ARM SMMU by checking that
1859          * an ARM SMMU exists in the system before proceeding with the driver
1860          * and IOMMU bus operation registration.
1861          */
1862         np = of_find_matching_node(NULL, arm_smmu_of_match);
1863         if (!np)
1864                 return 0;
1865 
1866         of_node_put(np);
1867 
1868         ret = platform_driver_register(&arm_smmu_driver);
1869         if (ret)
1870                 return ret;
1871 
1872         /* Oh, for a proper bus abstraction */
1873         if (!iommu_present(&platform_bus_type))
1874                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1875 
1876 #ifdef CONFIG_ARM_AMBA
1877         if (!iommu_present(&amba_bustype))
1878                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1879 #endif
1880 
1881 #ifdef CONFIG_PCI
1882         if (!iommu_present(&pci_bus_type))
1883                 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
1884 #endif
1885 
1886         return 0;
1887 }
1888 
1889 static void __exit arm_smmu_exit(void)
1890 {
1891         return platform_driver_unregister(&arm_smmu_driver);
1892 }
1893 
1894 subsys_initcall(arm_smmu_init);
1895 module_exit(arm_smmu_exit);
1896 
1897 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1898 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1899 MODULE_LICENSE("GPL v2");
1900 

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