Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/iio/adc/exynos_adc.c

  1 /*
  2  *  exynos_adc.c - Support for ADC in EXYNOS SoCs
  3  *
  4  *  8 ~ 10 channel, 10/12-bit ADC
  5  *
  6  *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
  7  *
  8  *  This program is free software; you can redistribute it and/or modify
  9  *  it under the terms of the GNU General Public License as published by
 10  *  the Free Software Foundation; either version 2 of the License, or
 11  *  (at your option) any later version.
 12  *
 13  *  This program is distributed in the hope that it will be useful,
 14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  *  GNU General Public License for more details.
 17  *
 18  *  You should have received a copy of the GNU General Public License
 19  *  along with this program; if not, write to the Free Software
 20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  */
 22 
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/delay.h>
 27 #include <linux/errno.h>
 28 #include <linux/kernel.h>
 29 #include <linux/slab.h>
 30 #include <linux/io.h>
 31 #include <linux/clk.h>
 32 #include <linux/completion.h>
 33 #include <linux/of.h>
 34 #include <linux/of_irq.h>
 35 #include <linux/regulator/consumer.h>
 36 #include <linux/of_platform.h>
 37 #include <linux/err.h>
 38 
 39 #include <linux/iio/iio.h>
 40 #include <linux/iio/machine.h>
 41 #include <linux/iio/driver.h>
 42 
 43 /* EXYNOS4412/5250 ADC_V1 registers definitions */
 44 #define ADC_V1_CON(x)           ((x) + 0x00)
 45 #define ADC_V1_DLY(x)           ((x) + 0x08)
 46 #define ADC_V1_DATX(x)          ((x) + 0x0C)
 47 #define ADC_V1_INTCLR(x)        ((x) + 0x18)
 48 #define ADC_V1_MUX(x)           ((x) + 0x1c)
 49 
 50 /* Future ADC_V2 registers definitions */
 51 #define ADC_V2_CON1(x)          ((x) + 0x00)
 52 #define ADC_V2_CON2(x)          ((x) + 0x04)
 53 #define ADC_V2_STAT(x)          ((x) + 0x08)
 54 #define ADC_V2_INT_EN(x)        ((x) + 0x10)
 55 #define ADC_V2_INT_ST(x)        ((x) + 0x14)
 56 #define ADC_V2_VER(x)           ((x) + 0x20)
 57 
 58 /* Bit definitions for ADC_V1 */
 59 #define ADC_V1_CON_RES          (1u << 16)
 60 #define ADC_V1_CON_PRSCEN       (1u << 14)
 61 #define ADC_V1_CON_PRSCLV(x)    (((x) & 0xFF) << 6)
 62 #define ADC_V1_CON_STANDBY      (1u << 2)
 63 
 64 /* Bit definitions for ADC_V2 */
 65 #define ADC_V2_CON1_SOFT_RESET  (1u << 2)
 66 
 67 #define ADC_V2_CON2_OSEL        (1u << 10)
 68 #define ADC_V2_CON2_ESEL        (1u << 9)
 69 #define ADC_V2_CON2_HIGHF       (1u << 8)
 70 #define ADC_V2_CON2_C_TIME(x)   (((x) & 7) << 4)
 71 #define ADC_V2_CON2_ACH_SEL(x)  (((x) & 0xF) << 0)
 72 #define ADC_V2_CON2_ACH_MASK    0xF
 73 
 74 #define MAX_ADC_V2_CHANNELS             10
 75 #define MAX_ADC_V1_CHANNELS             8
 76 #define MAX_EXYNOS3250_ADC_CHANNELS     2
 77 
 78 /* Bit definitions common for ADC_V1 and ADC_V2 */
 79 #define ADC_CON_EN_START        (1u << 0)
 80 #define ADC_DATX_MASK           0xFFF
 81 
 82 #define EXYNOS_ADC_TIMEOUT      (msecs_to_jiffies(100))
 83 
 84 struct exynos_adc {
 85         struct exynos_adc_data  *data;
 86         struct device           *dev;
 87         void __iomem            *regs;
 88         void __iomem            *enable_reg;
 89         struct clk              *clk;
 90         struct clk              *sclk;
 91         unsigned int            irq;
 92         struct regulator        *vdd;
 93 
 94         struct completion       completion;
 95 
 96         u32                     value;
 97         unsigned int            version;
 98 };
 99 
100 struct exynos_adc_data {
101         int num_channels;
102         bool needs_sclk;
103 
104         void (*init_hw)(struct exynos_adc *info);
105         void (*exit_hw)(struct exynos_adc *info);
106         void (*clear_irq)(struct exynos_adc *info);
107         void (*start_conv)(struct exynos_adc *info, unsigned long addr);
108 };
109 
110 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
111 {
112         if (info->data->needs_sclk)
113                 clk_unprepare(info->sclk);
114         clk_unprepare(info->clk);
115 }
116 
117 static int exynos_adc_prepare_clk(struct exynos_adc *info)
118 {
119         int ret;
120 
121         ret = clk_prepare(info->clk);
122         if (ret) {
123                 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
124                 return ret;
125         }
126 
127         if (info->data->needs_sclk) {
128                 ret = clk_prepare(info->sclk);
129                 if (ret) {
130                         clk_unprepare(info->clk);
131                         dev_err(info->dev,
132                                 "failed preparing sclk_adc clock: %d\n", ret);
133                         return ret;
134                 }
135         }
136 
137         return 0;
138 }
139 
140 static void exynos_adc_disable_clk(struct exynos_adc *info)
141 {
142         if (info->data->needs_sclk)
143                 clk_disable(info->sclk);
144         clk_disable(info->clk);
145 }
146 
147 static int exynos_adc_enable_clk(struct exynos_adc *info)
148 {
149         int ret;
150 
151         ret = clk_enable(info->clk);
152         if (ret) {
153                 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
154                 return ret;
155         }
156 
157         if (info->data->needs_sclk) {
158                 ret = clk_enable(info->sclk);
159                 if (ret) {
160                         clk_disable(info->clk);
161                         dev_err(info->dev,
162                                 "failed enabling sclk_adc clock: %d\n", ret);
163                         return ret;
164                 }
165         }
166 
167         return 0;
168 }
169 
170 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
171 {
172         u32 con1;
173 
174         writel(1, info->enable_reg);
175 
176         /* set default prescaler values and Enable prescaler */
177         con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
178 
179         /* Enable 12-bit ADC resolution */
180         con1 |= ADC_V1_CON_RES;
181         writel(con1, ADC_V1_CON(info->regs));
182 }
183 
184 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
185 {
186         u32 con;
187 
188         writel(0, info->enable_reg);
189 
190         con = readl(ADC_V1_CON(info->regs));
191         con |= ADC_V1_CON_STANDBY;
192         writel(con, ADC_V1_CON(info->regs));
193 }
194 
195 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
196 {
197         writel(1, ADC_V1_INTCLR(info->regs));
198 }
199 
200 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
201                                      unsigned long addr)
202 {
203         u32 con1;
204 
205         writel(addr, ADC_V1_MUX(info->regs));
206 
207         con1 = readl(ADC_V1_CON(info->regs));
208         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
209 }
210 
211 static const struct exynos_adc_data exynos_adc_v1_data = {
212         .num_channels   = MAX_ADC_V1_CHANNELS,
213 
214         .init_hw        = exynos_adc_v1_init_hw,
215         .exit_hw        = exynos_adc_v1_exit_hw,
216         .clear_irq      = exynos_adc_v1_clear_irq,
217         .start_conv     = exynos_adc_v1_start_conv,
218 };
219 
220 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
221 {
222         u32 con1, con2;
223 
224         writel(1, info->enable_reg);
225 
226         con1 = ADC_V2_CON1_SOFT_RESET;
227         writel(con1, ADC_V2_CON1(info->regs));
228 
229         con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
230                 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
231         writel(con2, ADC_V2_CON2(info->regs));
232 
233         /* Enable interrupts */
234         writel(1, ADC_V2_INT_EN(info->regs));
235 }
236 
237 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
238 {
239         u32 con;
240 
241         writel(0, info->enable_reg);
242 
243         con = readl(ADC_V2_CON1(info->regs));
244         con &= ~ADC_CON_EN_START;
245         writel(con, ADC_V2_CON1(info->regs));
246 }
247 
248 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
249 {
250         writel(1, ADC_V2_INT_ST(info->regs));
251 }
252 
253 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
254                                      unsigned long addr)
255 {
256         u32 con1, con2;
257 
258         con2 = readl(ADC_V2_CON2(info->regs));
259         con2 &= ~ADC_V2_CON2_ACH_MASK;
260         con2 |= ADC_V2_CON2_ACH_SEL(addr);
261         writel(con2, ADC_V2_CON2(info->regs));
262 
263         con1 = readl(ADC_V2_CON1(info->regs));
264         writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
265 }
266 
267 static const struct exynos_adc_data exynos_adc_v2_data = {
268         .num_channels   = MAX_ADC_V2_CHANNELS,
269 
270         .init_hw        = exynos_adc_v2_init_hw,
271         .exit_hw        = exynos_adc_v2_exit_hw,
272         .clear_irq      = exynos_adc_v2_clear_irq,
273         .start_conv     = exynos_adc_v2_start_conv,
274 };
275 
276 static const struct exynos_adc_data exynos3250_adc_data = {
277         .num_channels   = MAX_EXYNOS3250_ADC_CHANNELS,
278         .needs_sclk     = true,
279 
280         .init_hw        = exynos_adc_v2_init_hw,
281         .exit_hw        = exynos_adc_v2_exit_hw,
282         .clear_irq      = exynos_adc_v2_clear_irq,
283         .start_conv     = exynos_adc_v2_start_conv,
284 };
285 
286 static const struct of_device_id exynos_adc_match[] = {
287         {
288                 .compatible = "samsung,exynos-adc-v1",
289                 .data = &exynos_adc_v1_data,
290         }, {
291                 .compatible = "samsung,exynos-adc-v2",
292                 .data = &exynos_adc_v2_data,
293         }, {
294                 .compatible = "samsung,exynos3250-adc",
295                 .data = &exynos3250_adc_data,
296         },
297         {},
298 };
299 MODULE_DEVICE_TABLE(of, exynos_adc_match);
300 
301 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
302 {
303         const struct of_device_id *match;
304 
305         match = of_match_node(exynos_adc_match, pdev->dev.of_node);
306         return (struct exynos_adc_data *)match->data;
307 }
308 
309 static int exynos_read_raw(struct iio_dev *indio_dev,
310                                 struct iio_chan_spec const *chan,
311                                 int *val,
312                                 int *val2,
313                                 long mask)
314 {
315         struct exynos_adc *info = iio_priv(indio_dev);
316         unsigned long timeout;
317         int ret;
318 
319         if (mask != IIO_CHAN_INFO_RAW)
320                 return -EINVAL;
321 
322         mutex_lock(&indio_dev->mlock);
323         reinit_completion(&info->completion);
324 
325         /* Select the channel to be used and Trigger conversion */
326         if (info->data->start_conv)
327                 info->data->start_conv(info, chan->address);
328 
329         timeout = wait_for_completion_timeout
330                         (&info->completion, EXYNOS_ADC_TIMEOUT);
331         if (timeout == 0) {
332                 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
333                 if (info->data->init_hw)
334                         info->data->init_hw(info);
335                 ret = -ETIMEDOUT;
336         } else {
337                 *val = info->value;
338                 *val2 = 0;
339                 ret = IIO_VAL_INT;
340         }
341 
342         mutex_unlock(&indio_dev->mlock);
343 
344         return ret;
345 }
346 
347 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
348 {
349         struct exynos_adc *info = (struct exynos_adc *)dev_id;
350 
351         /* Read value */
352         info->value = readl(ADC_V1_DATX(info->regs)) & ADC_DATX_MASK;
353 
354         /* clear irq */
355         if (info->data->clear_irq)
356                 info->data->clear_irq(info);
357 
358         complete(&info->completion);
359 
360         return IRQ_HANDLED;
361 }
362 
363 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
364                               unsigned reg, unsigned writeval,
365                               unsigned *readval)
366 {
367         struct exynos_adc *info = iio_priv(indio_dev);
368 
369         if (readval == NULL)
370                 return -EINVAL;
371 
372         *readval = readl(info->regs + reg);
373 
374         return 0;
375 }
376 
377 static const struct iio_info exynos_adc_iio_info = {
378         .read_raw = &exynos_read_raw,
379         .debugfs_reg_access = &exynos_adc_reg_access,
380         .driver_module = THIS_MODULE,
381 };
382 
383 #define ADC_CHANNEL(_index, _id) {                      \
384         .type = IIO_VOLTAGE,                            \
385         .indexed = 1,                                   \
386         .channel = _index,                              \
387         .address = _index,                              \
388         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
389         .datasheet_name = _id,                          \
390 }
391 
392 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
393         ADC_CHANNEL(0, "adc0"),
394         ADC_CHANNEL(1, "adc1"),
395         ADC_CHANNEL(2, "adc2"),
396         ADC_CHANNEL(3, "adc3"),
397         ADC_CHANNEL(4, "adc4"),
398         ADC_CHANNEL(5, "adc5"),
399         ADC_CHANNEL(6, "adc6"),
400         ADC_CHANNEL(7, "adc7"),
401         ADC_CHANNEL(8, "adc8"),
402         ADC_CHANNEL(9, "adc9"),
403 };
404 
405 static int exynos_adc_remove_devices(struct device *dev, void *c)
406 {
407         struct platform_device *pdev = to_platform_device(dev);
408 
409         platform_device_unregister(pdev);
410 
411         return 0;
412 }
413 
414 static int exynos_adc_probe(struct platform_device *pdev)
415 {
416         struct exynos_adc *info = NULL;
417         struct device_node *np = pdev->dev.of_node;
418         struct iio_dev *indio_dev = NULL;
419         struct resource *mem;
420         int ret = -ENODEV;
421         int irq;
422 
423         if (!np)
424                 return ret;
425 
426         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
427         if (!indio_dev) {
428                 dev_err(&pdev->dev, "failed allocating iio device\n");
429                 return -ENOMEM;
430         }
431 
432         info = iio_priv(indio_dev);
433 
434         info->data = exynos_adc_get_data(pdev);
435         if (!info->data) {
436                 dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
437                 return -EINVAL;
438         }
439 
440         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441         info->regs = devm_ioremap_resource(&pdev->dev, mem);
442         if (IS_ERR(info->regs))
443                 return PTR_ERR(info->regs);
444 
445         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
446         info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
447         if (IS_ERR(info->enable_reg))
448                 return PTR_ERR(info->enable_reg);
449 
450         irq = platform_get_irq(pdev, 0);
451         if (irq < 0) {
452                 dev_err(&pdev->dev, "no irq resource?\n");
453                 return irq;
454         }
455 
456         info->irq = irq;
457         info->dev = &pdev->dev;
458 
459         init_completion(&info->completion);
460 
461         info->clk = devm_clk_get(&pdev->dev, "adc");
462         if (IS_ERR(info->clk)) {
463                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
464                                                         PTR_ERR(info->clk));
465                 return PTR_ERR(info->clk);
466         }
467 
468         if (info->data->needs_sclk) {
469                 info->sclk = devm_clk_get(&pdev->dev, "sclk");
470                 if (IS_ERR(info->sclk)) {
471                         dev_err(&pdev->dev,
472                                 "failed getting sclk clock, err = %ld\n",
473                                 PTR_ERR(info->sclk));
474                         return PTR_ERR(info->sclk);
475                 }
476         }
477 
478         info->vdd = devm_regulator_get(&pdev->dev, "vdd");
479         if (IS_ERR(info->vdd)) {
480                 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
481                                                         PTR_ERR(info->vdd));
482                 return PTR_ERR(info->vdd);
483         }
484 
485         ret = regulator_enable(info->vdd);
486         if (ret)
487                 return ret;
488 
489         ret = exynos_adc_prepare_clk(info);
490         if (ret)
491                 goto err_disable_reg;
492 
493         ret = exynos_adc_enable_clk(info);
494         if (ret)
495                 goto err_unprepare_clk;
496 
497         platform_set_drvdata(pdev, indio_dev);
498 
499         indio_dev->name = dev_name(&pdev->dev);
500         indio_dev->dev.parent = &pdev->dev;
501         indio_dev->dev.of_node = pdev->dev.of_node;
502         indio_dev->info = &exynos_adc_iio_info;
503         indio_dev->modes = INDIO_DIRECT_MODE;
504         indio_dev->channels = exynos_adc_iio_channels;
505         indio_dev->num_channels = info->data->num_channels;
506 
507         ret = request_irq(info->irq, exynos_adc_isr,
508                                         0, dev_name(&pdev->dev), info);
509         if (ret < 0) {
510                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
511                                                         info->irq);
512                 goto err_disable_clk;
513         }
514 
515         ret = iio_device_register(indio_dev);
516         if (ret)
517                 goto err_irq;
518 
519         if (info->data->init_hw)
520                 info->data->init_hw(info);
521 
522         ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
523         if (ret < 0) {
524                 dev_err(&pdev->dev, "failed adding child nodes\n");
525                 goto err_of_populate;
526         }
527 
528         return 0;
529 
530 err_of_populate:
531         device_for_each_child(&indio_dev->dev, NULL,
532                                 exynos_adc_remove_devices);
533         iio_device_unregister(indio_dev);
534 err_irq:
535         free_irq(info->irq, info);
536 err_disable_clk:
537         if (info->data->exit_hw)
538                 info->data->exit_hw(info);
539         exynos_adc_disable_clk(info);
540 err_unprepare_clk:
541         exynos_adc_unprepare_clk(info);
542 err_disable_reg:
543         regulator_disable(info->vdd);
544         return ret;
545 }
546 
547 static int exynos_adc_remove(struct platform_device *pdev)
548 {
549         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
550         struct exynos_adc *info = iio_priv(indio_dev);
551 
552         device_for_each_child(&indio_dev->dev, NULL,
553                                 exynos_adc_remove_devices);
554         iio_device_unregister(indio_dev);
555         free_irq(info->irq, info);
556         if (info->data->exit_hw)
557                 info->data->exit_hw(info);
558         exynos_adc_disable_clk(info);
559         exynos_adc_unprepare_clk(info);
560         regulator_disable(info->vdd);
561 
562         return 0;
563 }
564 
565 #ifdef CONFIG_PM_SLEEP
566 static int exynos_adc_suspend(struct device *dev)
567 {
568         struct iio_dev *indio_dev = dev_get_drvdata(dev);
569         struct exynos_adc *info = iio_priv(indio_dev);
570 
571         if (info->data->exit_hw)
572                 info->data->exit_hw(info);
573         exynos_adc_disable_clk(info);
574         regulator_disable(info->vdd);
575 
576         return 0;
577 }
578 
579 static int exynos_adc_resume(struct device *dev)
580 {
581         struct iio_dev *indio_dev = dev_get_drvdata(dev);
582         struct exynos_adc *info = iio_priv(indio_dev);
583         int ret;
584 
585         ret = regulator_enable(info->vdd);
586         if (ret)
587                 return ret;
588 
589         ret = exynos_adc_enable_clk(info);
590         if (ret)
591                 return ret;
592 
593         if (info->data->init_hw)
594                 info->data->init_hw(info);
595 
596         return 0;
597 }
598 #endif
599 
600 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
601                         exynos_adc_suspend,
602                         exynos_adc_resume);
603 
604 static struct platform_driver exynos_adc_driver = {
605         .probe          = exynos_adc_probe,
606         .remove         = exynos_adc_remove,
607         .driver         = {
608                 .name   = "exynos-adc",
609                 .owner  = THIS_MODULE,
610                 .of_match_table = exynos_adc_match,
611                 .pm     = &exynos_adc_pm_ops,
612         },
613 };
614 
615 module_platform_driver(exynos_adc_driver);
616 
617 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
618 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
619 MODULE_LICENSE("GPL v2");
620 

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