Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/iio/adc/at91_adc.c

  1 /*
  2  * Driver for the ADC present in the Atmel AT91 evaluation boards.
  3  *
  4  * Copyright 2011 Free Electrons
  5  *
  6  * Licensed under the GPLv2 or later.
  7  */
  8 
  9 #include <linux/bitmap.h>
 10 #include <linux/bitops.h>
 11 #include <linux/clk.h>
 12 #include <linux/err.h>
 13 #include <linux/io.h>
 14 #include <linux/input.h>
 15 #include <linux/interrupt.h>
 16 #include <linux/jiffies.h>
 17 #include <linux/kernel.h>
 18 #include <linux/module.h>
 19 #include <linux/of.h>
 20 #include <linux/of_device.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/sched.h>
 23 #include <linux/slab.h>
 24 #include <linux/wait.h>
 25 
 26 #include <linux/platform_data/at91_adc.h>
 27 
 28 #include <linux/iio/iio.h>
 29 #include <linux/iio/buffer.h>
 30 #include <linux/iio/trigger.h>
 31 #include <linux/iio/trigger_consumer.h>
 32 #include <linux/iio/triggered_buffer.h>
 33 
 34 /* Registers */
 35 #define AT91_ADC_CR             0x00            /* Control Register */
 36 #define         AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
 37 #define         AT91_ADC_START          (1 << 1)        /* Start Conversion */
 38 
 39 #define AT91_ADC_MR             0x04            /* Mode Register */
 40 #define         AT91_ADC_TSAMOD         (3 << 0)        /* ADC mode */
 41 #define         AT91_ADC_TSAMOD_ADC_ONLY_MODE           (0 << 0)        /* ADC Mode */
 42 #define         AT91_ADC_TSAMOD_TS_ONLY_MODE            (1 << 0)        /* Touch Screen Only Mode */
 43 #define         AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
 44 #define         AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
 45 #define                 AT91_ADC_TRGSEL_TC0             (0 << 1)
 46 #define                 AT91_ADC_TRGSEL_TC1             (1 << 1)
 47 #define                 AT91_ADC_TRGSEL_TC2             (2 << 1)
 48 #define                 AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
 49 #define         AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
 50 #define         AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
 51 #define         AT91_ADC_PENDET         (1 << 6)        /* Pen contact detection enable */
 52 #define         AT91_ADC_PRESCAL_9260   (0x3f << 8)     /* Prescalar Rate Selection */
 53 #define         AT91_ADC_PRESCAL_9G45   (0xff << 8)
 54 #define                 AT91_ADC_PRESCAL_(x)    ((x) << 8)
 55 #define         AT91_ADC_STARTUP_9260   (0x1f << 16)    /* Startup Up Time */
 56 #define         AT91_ADC_STARTUP_9G45   (0x7f << 16)
 57 #define         AT91_ADC_STARTUP_9X5    (0xf << 16)
 58 #define                 AT91_ADC_STARTUP_(x)    ((x) << 16)
 59 #define         AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
 60 #define                 AT91_ADC_SHTIM_(x)      ((x) << 24)
 61 #define         AT91_ADC_PENDBC         (0x0f << 28)    /* Pen Debounce time */
 62 #define                 AT91_ADC_PENDBC_(x)     ((x) << 28)
 63 
 64 #define AT91_ADC_TSR            0x0C
 65 #define         AT91_ADC_TSR_SHTIM      (0xf  << 24)    /* Sample & Hold Time */
 66 #define                 AT91_ADC_TSR_SHTIM_(x)  ((x) << 24)
 67 
 68 #define AT91_ADC_CHER           0x10            /* Channel Enable Register */
 69 #define AT91_ADC_CHDR           0x14            /* Channel Disable Register */
 70 #define AT91_ADC_CHSR           0x18            /* Channel Status Register */
 71 #define         AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
 72 
 73 #define AT91_ADC_SR             0x1C            /* Status Register */
 74 #define         AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
 75 #define         AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
 76 #define         AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
 77 #define         AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
 78 #define         AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
 79 #define         AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
 80 
 81 #define AT91_ADC_SR_9X5         0x30            /* Status Register for 9x5 */
 82 #define         AT91_ADC_SR_DRDY_9X5    (1 << 24)       /* Data Ready */
 83 
 84 #define AT91_ADC_LCDR           0x20            /* Last Converted Data Register */
 85 #define         AT91_ADC_LDATA          (0x3ff)
 86 
 87 #define AT91_ADC_IER            0x24            /* Interrupt Enable Register */
 88 #define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
 89 #define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
 90 #define         AT91RL_ADC_IER_PEN      (1 << 20)
 91 #define         AT91RL_ADC_IER_NOPEN    (1 << 21)
 92 #define         AT91_ADC_IER_PEN        (1 << 29)
 93 #define         AT91_ADC_IER_NOPEN      (1 << 30)
 94 #define         AT91_ADC_IER_XRDY       (1 << 20)
 95 #define         AT91_ADC_IER_YRDY       (1 << 21)
 96 #define         AT91_ADC_IER_PRDY       (1 << 22)
 97 #define         AT91_ADC_ISR_PENS       (1 << 31)
 98 
 99 #define AT91_ADC_CHR(n)         (0x30 + ((n) * 4))      /* Channel Data Register N */
100 #define         AT91_ADC_DATA           (0x3ff)
101 
102 #define AT91_ADC_CDR0_9X5       (0x50)                  /* Channel Data Register 0 for 9X5 */
103 
104 #define AT91_ADC_ACR            0x94    /* Analog Control Register */
105 #define         AT91_ADC_ACR_PENDETSENS (0x3 << 0)      /* pull-up resistor */
106 
107 #define AT91_ADC_TSMR           0xB0
108 #define         AT91_ADC_TSMR_TSMODE    (3 << 0)        /* Touch Screen Mode */
109 #define                 AT91_ADC_TSMR_TSMODE_NONE               (0 << 0)
110 #define                 AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS     (1 << 0)
111 #define                 AT91_ADC_TSMR_TSMODE_4WIRE_PRESS        (2 << 0)
112 #define                 AT91_ADC_TSMR_TSMODE_5WIRE              (3 << 0)
113 #define         AT91_ADC_TSMR_TSAV      (3 << 4)        /* Averages samples */
114 #define                 AT91_ADC_TSMR_TSAV_(x)          ((x) << 4)
115 #define         AT91_ADC_TSMR_SCTIM     (0x0f << 16)    /* Switch closure time */
116 #define                 AT91_ADC_TSMR_SCTIM_(x)         ((x) << 16)
117 #define         AT91_ADC_TSMR_PENDBC    (0x0f << 28)    /* Pen Debounce time */
118 #define                 AT91_ADC_TSMR_PENDBC_(x)        ((x) << 28)
119 #define         AT91_ADC_TSMR_NOTSDMA   (1 << 22)       /* No Touchscreen DMA */
120 #define         AT91_ADC_TSMR_PENDET_DIS        (0 << 24)       /* Pen contact detection disable */
121 #define         AT91_ADC_TSMR_PENDET_ENA        (1 << 24)       /* Pen contact detection enable */
122 
123 #define AT91_ADC_TSXPOSR        0xB4
124 #define AT91_ADC_TSYPOSR        0xB8
125 #define AT91_ADC_TSPRESSR       0xBC
126 
127 #define AT91_ADC_TRGR_9260      AT91_ADC_MR
128 #define AT91_ADC_TRGR_9G45      0x08
129 #define AT91_ADC_TRGR_9X5       0xC0
130 
131 /* Trigger Register bit field */
132 #define         AT91_ADC_TRGR_TRGPER    (0xffff << 16)
133 #define                 AT91_ADC_TRGR_TRGPER_(x)        ((x) << 16)
134 #define         AT91_ADC_TRGR_TRGMOD    (0x7 << 0)
135 #define                 AT91_ADC_TRGR_NONE              (0 << 0)
136 #define                 AT91_ADC_TRGR_MOD_PERIOD_TRIG   (5 << 0)
137 
138 #define AT91_ADC_CHAN(st, ch) \
139         (st->registers->channel_base + (ch * 4))
140 #define at91_adc_readl(st, reg) \
141         (readl_relaxed(st->reg_base + reg))
142 #define at91_adc_writel(st, reg, val) \
143         (writel_relaxed(val, st->reg_base + reg))
144 
145 #define DRIVER_NAME             "at91_adc"
146 #define MAX_POS_BITS            12
147 
148 #define TOUCH_SAMPLE_PERIOD_US          2000    /* 2ms */
149 #define TOUCH_PEN_DETECT_DEBOUNCE_US    200
150 
151 #define MAX_RLPOS_BITS         10
152 #define TOUCH_SAMPLE_PERIOD_US_RL      10000   /* 10ms, the SoC can't keep up with 2ms */
153 #define TOUCH_SHTIM                    0xa
154 #define TOUCH_SCTIM_US          10              /* 10us for the Touchscreen Switches Closure Time */
155 
156 /**
157  * struct at91_adc_reg_desc - Various informations relative to registers
158  * @channel_base:       Base offset for the channel data registers
159  * @drdy_mask:          Mask of the DRDY field in the relevant registers
160                         (Interruptions registers mostly)
161  * @status_register:    Offset of the Interrupt Status Register
162  * @trigger_register:   Offset of the Trigger setup register
163  * @mr_prescal_mask:    Mask of the PRESCAL field in the adc MR register
164  * @mr_startup_mask:    Mask of the STARTUP field in the adc MR register
165  */
166 struct at91_adc_reg_desc {
167         u8      channel_base;
168         u32     drdy_mask;
169         u8      status_register;
170         u8      trigger_register;
171         u32     mr_prescal_mask;
172         u32     mr_startup_mask;
173 };
174 
175 struct at91_adc_caps {
176         bool    has_ts;         /* Support touch screen */
177         bool    has_tsmr;       /* only at91sam9x5, sama5d3 have TSMR reg */
178         /*
179          * Numbers of sampling data will be averaged. Can be 0~3.
180          * Hardware can average (2 ^ ts_filter_average) sample data.
181          */
182         u8      ts_filter_average;
183         /* Pen Detection input pull-up resistor, can be 0~3 */
184         u8      ts_pen_detect_sensitivity;
185 
186         /* startup time calculate function */
187         u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
188 
189         u8      num_channels;
190         struct at91_adc_reg_desc registers;
191 };
192 
193 struct at91_adc_state {
194         struct clk              *adc_clk;
195         u16                     *buffer;
196         unsigned long           channels_mask;
197         struct clk              *clk;
198         bool                    done;
199         int                     irq;
200         u16                     last_value;
201         int                     chnb;
202         struct mutex            lock;
203         u8                      num_channels;
204         void __iomem            *reg_base;
205         struct at91_adc_reg_desc *registers;
206         u32                     startup_time;
207         u8                      sample_hold_time;
208         bool                    sleep_mode;
209         struct iio_trigger      **trig;
210         struct at91_adc_trigger *trigger_list;
211         u32                     trigger_number;
212         bool                    use_external;
213         u32                     vref_mv;
214         u32                     res;            /* resolution used for convertions */
215         bool                    low_res;        /* the resolution corresponds to the lowest one */
216         wait_queue_head_t       wq_data_avail;
217         struct at91_adc_caps    *caps;
218 
219         /*
220          * Following ADC channels are shared by touchscreen:
221          *
222          * CH0 -- Touch screen XP/UL
223          * CH1 -- Touch screen XM/UR
224          * CH2 -- Touch screen YP/LL
225          * CH3 -- Touch screen YM/Sense
226          * CH4 -- Touch screen LR(5-wire only)
227          *
228          * The bitfields below represents the reserved channel in the
229          * touchscreen mode.
230          */
231 #define CHAN_MASK_TOUCHSCREEN_4WIRE     (0xf << 0)
232 #define CHAN_MASK_TOUCHSCREEN_5WIRE     (0x1f << 0)
233         enum atmel_adc_ts_type  touchscreen_type;
234         struct input_dev        *ts_input;
235 
236         u16                     ts_sample_period_val;
237         u32                     ts_pressure_threshold;
238         u16                     ts_pendbc;
239 
240         bool                    ts_bufferedmeasure;
241         u32                     ts_prev_absx;
242         u32                     ts_prev_absy;
243 };
244 
245 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
246 {
247         struct iio_poll_func *pf = p;
248         struct iio_dev *idev = pf->indio_dev;
249         struct at91_adc_state *st = iio_priv(idev);
250         int i, j = 0;
251 
252         for (i = 0; i < idev->masklength; i++) {
253                 if (!test_bit(i, idev->active_scan_mask))
254                         continue;
255                 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
256                 j++;
257         }
258 
259         iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
260 
261         iio_trigger_notify_done(idev->trig);
262 
263         /* Needed to ACK the DRDY interruption */
264         at91_adc_readl(st, AT91_ADC_LCDR);
265 
266         enable_irq(st->irq);
267 
268         return IRQ_HANDLED;
269 }
270 
271 /* Handler for classic adc channel eoc trigger */
272 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
273 {
274         struct at91_adc_state *st = iio_priv(idev);
275 
276         if (iio_buffer_enabled(idev)) {
277                 disable_irq_nosync(irq);
278                 iio_trigger_poll(idev->trig);
279         } else {
280                 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
281                 st->done = true;
282                 wake_up_interruptible(&st->wq_data_avail);
283         }
284 }
285 
286 static int at91_ts_sample(struct at91_adc_state *st)
287 {
288         unsigned int xscale, yscale, reg, z1, z2;
289         unsigned int x, y, pres, xpos, ypos;
290         unsigned int rxp = 1;
291         unsigned int factor = 1000;
292         struct iio_dev *idev = iio_priv_to_dev(st);
293 
294         unsigned int xyz_mask_bits = st->res;
295         unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
296 
297         /* calculate position */
298         /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
299         reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
300         xpos = reg & xyz_mask;
301         x = (xpos << MAX_POS_BITS) - xpos;
302         xscale = (reg >> 16) & xyz_mask;
303         if (xscale == 0) {
304                 dev_err(&idev->dev, "Error: xscale == 0!\n");
305                 return -1;
306         }
307         x /= xscale;
308 
309         /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
310         reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
311         ypos = reg & xyz_mask;
312         y = (ypos << MAX_POS_BITS) - ypos;
313         yscale = (reg >> 16) & xyz_mask;
314         if (yscale == 0) {
315                 dev_err(&idev->dev, "Error: yscale == 0!\n");
316                 return -1;
317         }
318         y /= yscale;
319 
320         /* calculate the pressure */
321         reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
322         z1 = reg & xyz_mask;
323         z2 = (reg >> 16) & xyz_mask;
324 
325         if (z1 != 0)
326                 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
327                         / factor;
328         else
329                 pres = st->ts_pressure_threshold;       /* no pen contacted */
330 
331         dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
332                                 xpos, xscale, ypos, yscale, z1, z2, pres);
333 
334         if (pres < st->ts_pressure_threshold) {
335                 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
336                                         x, y, pres / factor);
337                 input_report_abs(st->ts_input, ABS_X, x);
338                 input_report_abs(st->ts_input, ABS_Y, y);
339                 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
340                 input_report_key(st->ts_input, BTN_TOUCH, 1);
341                 input_sync(st->ts_input);
342         } else {
343                 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
344         }
345 
346         return 0;
347 }
348 
349 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
350 {
351         struct iio_dev *idev = private;
352         struct at91_adc_state *st = iio_priv(idev);
353         u32 status = at91_adc_readl(st, st->registers->status_register);
354         unsigned int reg;
355 
356         status &= at91_adc_readl(st, AT91_ADC_IMR);
357         if (status & GENMASK(st->num_channels - 1, 0))
358                 handle_adc_eoc_trigger(irq, idev);
359 
360         if (status & AT91RL_ADC_IER_PEN) {
361                 /* Disabling pen debounce is required to get a NOPEN irq */
362                 reg = at91_adc_readl(st, AT91_ADC_MR);
363                 reg &= ~AT91_ADC_PENDBC;
364                 at91_adc_writel(st, AT91_ADC_MR, reg);
365 
366                 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
367                 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
368                                 | AT91_ADC_EOC(3));
369                 /* Set up period trigger for sampling */
370                 at91_adc_writel(st, st->registers->trigger_register,
371                         AT91_ADC_TRGR_MOD_PERIOD_TRIG |
372                         AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
373         } else if (status & AT91RL_ADC_IER_NOPEN) {
374                 reg = at91_adc_readl(st, AT91_ADC_MR);
375                 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
376                 at91_adc_writel(st, AT91_ADC_MR, reg);
377                 at91_adc_writel(st, st->registers->trigger_register,
378                         AT91_ADC_TRGR_NONE);
379 
380                 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
381                                 | AT91_ADC_EOC(3));
382                 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
383                 st->ts_bufferedmeasure = false;
384                 input_report_key(st->ts_input, BTN_TOUCH, 0);
385                 input_sync(st->ts_input);
386         } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
387                 /* Conversion finished and we've a touchscreen */
388                 if (st->ts_bufferedmeasure) {
389                         /*
390                          * Last measurement is always discarded, since it can
391                          * be erroneous.
392                          * Always report previous measurement
393                          */
394                         input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
395                         input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
396                         input_report_key(st->ts_input, BTN_TOUCH, 1);
397                         input_sync(st->ts_input);
398                 } else
399                         st->ts_bufferedmeasure = true;
400 
401                 /* Now make new measurement */
402                 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
403                                    << MAX_RLPOS_BITS;
404                 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
405 
406                 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
407                                    << MAX_RLPOS_BITS;
408                 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
409         }
410 
411         return IRQ_HANDLED;
412 }
413 
414 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
415 {
416         struct iio_dev *idev = private;
417         struct at91_adc_state *st = iio_priv(idev);
418         u32 status = at91_adc_readl(st, st->registers->status_register);
419         const uint32_t ts_data_irq_mask =
420                 AT91_ADC_IER_XRDY |
421                 AT91_ADC_IER_YRDY |
422                 AT91_ADC_IER_PRDY;
423 
424         if (status & GENMASK(st->num_channels - 1, 0))
425                 handle_adc_eoc_trigger(irq, idev);
426 
427         if (status & AT91_ADC_IER_PEN) {
428                 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
429                 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
430                         ts_data_irq_mask);
431                 /* Set up period trigger for sampling */
432                 at91_adc_writel(st, st->registers->trigger_register,
433                         AT91_ADC_TRGR_MOD_PERIOD_TRIG |
434                         AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
435         } else if (status & AT91_ADC_IER_NOPEN) {
436                 at91_adc_writel(st, st->registers->trigger_register, 0);
437                 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
438                         ts_data_irq_mask);
439                 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
440 
441                 input_report_key(st->ts_input, BTN_TOUCH, 0);
442                 input_sync(st->ts_input);
443         } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
444                 /* Now all touchscreen data is ready */
445 
446                 if (status & AT91_ADC_ISR_PENS) {
447                         /* validate data by pen contact */
448                         at91_ts_sample(st);
449                 } else {
450                         /* triggered by event that is no pen contact, just read
451                          * them to clean the interrupt and discard all.
452                          */
453                         at91_adc_readl(st, AT91_ADC_TSXPOSR);
454                         at91_adc_readl(st, AT91_ADC_TSYPOSR);
455                         at91_adc_readl(st, AT91_ADC_TSPRESSR);
456                 }
457         }
458 
459         return IRQ_HANDLED;
460 }
461 
462 static int at91_adc_channel_init(struct iio_dev *idev)
463 {
464         struct at91_adc_state *st = iio_priv(idev);
465         struct iio_chan_spec *chan_array, *timestamp;
466         int bit, idx = 0;
467         unsigned long rsvd_mask = 0;
468 
469         /* If touchscreen is enable, then reserve the adc channels */
470         if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
471                 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
472         else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
473                 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
474 
475         /* set up the channel mask to reserve touchscreen channels */
476         st->channels_mask &= ~rsvd_mask;
477 
478         idev->num_channels = bitmap_weight(&st->channels_mask,
479                                            st->num_channels) + 1;
480 
481         chan_array = devm_kzalloc(&idev->dev,
482                                   ((idev->num_channels + 1) *
483                                         sizeof(struct iio_chan_spec)),
484                                   GFP_KERNEL);
485 
486         if (!chan_array)
487                 return -ENOMEM;
488 
489         for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
490                 struct iio_chan_spec *chan = chan_array + idx;
491 
492                 chan->type = IIO_VOLTAGE;
493                 chan->indexed = 1;
494                 chan->channel = bit;
495                 chan->scan_index = idx;
496                 chan->scan_type.sign = 'u';
497                 chan->scan_type.realbits = st->res;
498                 chan->scan_type.storagebits = 16;
499                 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
500                 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
501                 idx++;
502         }
503         timestamp = chan_array + idx;
504 
505         timestamp->type = IIO_TIMESTAMP;
506         timestamp->channel = -1;
507         timestamp->scan_index = idx;
508         timestamp->scan_type.sign = 's';
509         timestamp->scan_type.realbits = 64;
510         timestamp->scan_type.storagebits = 64;
511 
512         idev->channels = chan_array;
513         return idev->num_channels;
514 }
515 
516 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
517                                              struct at91_adc_trigger *triggers,
518                                              const char *trigger_name)
519 {
520         struct at91_adc_state *st = iio_priv(idev);
521         int i;
522 
523         for (i = 0; i < st->trigger_number; i++) {
524                 char *name = kasprintf(GFP_KERNEL,
525                                 "%s-dev%d-%s",
526                                 idev->name,
527                                 idev->id,
528                                 triggers[i].name);
529                 if (!name)
530                         return -ENOMEM;
531 
532                 if (strcmp(trigger_name, name) == 0) {
533                         kfree(name);
534                         if (triggers[i].value == 0)
535                                 return -EINVAL;
536                         return triggers[i].value;
537                 }
538 
539                 kfree(name);
540         }
541 
542         return -EINVAL;
543 }
544 
545 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
546 {
547         struct iio_dev *idev = iio_trigger_get_drvdata(trig);
548         struct at91_adc_state *st = iio_priv(idev);
549         struct at91_adc_reg_desc *reg = st->registers;
550         u32 status = at91_adc_readl(st, reg->trigger_register);
551         int value;
552         u8 bit;
553 
554         value = at91_adc_get_trigger_value_by_name(idev,
555                                                    st->trigger_list,
556                                                    idev->trig->name);
557         if (value < 0)
558                 return value;
559 
560         if (state) {
561                 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
562                 if (st->buffer == NULL)
563                         return -ENOMEM;
564 
565                 at91_adc_writel(st, reg->trigger_register,
566                                 status | value);
567 
568                 for_each_set_bit(bit, idev->active_scan_mask,
569                                  st->num_channels) {
570                         struct iio_chan_spec const *chan = idev->channels + bit;
571                         at91_adc_writel(st, AT91_ADC_CHER,
572                                         AT91_ADC_CH(chan->channel));
573                 }
574 
575                 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
576 
577         } else {
578                 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
579 
580                 at91_adc_writel(st, reg->trigger_register,
581                                 status & ~value);
582 
583                 for_each_set_bit(bit, idev->active_scan_mask,
584                                  st->num_channels) {
585                         struct iio_chan_spec const *chan = idev->channels + bit;
586                         at91_adc_writel(st, AT91_ADC_CHDR,
587                                         AT91_ADC_CH(chan->channel));
588                 }
589                 kfree(st->buffer);
590         }
591 
592         return 0;
593 }
594 
595 static const struct iio_trigger_ops at91_adc_trigger_ops = {
596         .owner = THIS_MODULE,
597         .set_trigger_state = &at91_adc_configure_trigger,
598 };
599 
600 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
601                                                      struct at91_adc_trigger *trigger)
602 {
603         struct iio_trigger *trig;
604         int ret;
605 
606         trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
607                                  idev->id, trigger->name);
608         if (trig == NULL)
609                 return NULL;
610 
611         trig->dev.parent = idev->dev.parent;
612         iio_trigger_set_drvdata(trig, idev);
613         trig->ops = &at91_adc_trigger_ops;
614 
615         ret = iio_trigger_register(trig);
616         if (ret)
617                 return NULL;
618 
619         return trig;
620 }
621 
622 static int at91_adc_trigger_init(struct iio_dev *idev)
623 {
624         struct at91_adc_state *st = iio_priv(idev);
625         int i, ret;
626 
627         st->trig = devm_kzalloc(&idev->dev,
628                                 st->trigger_number * sizeof(*st->trig),
629                                 GFP_KERNEL);
630 
631         if (st->trig == NULL) {
632                 ret = -ENOMEM;
633                 goto error_ret;
634         }
635 
636         for (i = 0; i < st->trigger_number; i++) {
637                 if (st->trigger_list[i].is_external && !(st->use_external))
638                         continue;
639 
640                 st->trig[i] = at91_adc_allocate_trigger(idev,
641                                                         st->trigger_list + i);
642                 if (st->trig[i] == NULL) {
643                         dev_err(&idev->dev,
644                                 "Could not allocate trigger %d\n", i);
645                         ret = -ENOMEM;
646                         goto error_trigger;
647                 }
648         }
649 
650         return 0;
651 
652 error_trigger:
653         for (i--; i >= 0; i--) {
654                 iio_trigger_unregister(st->trig[i]);
655                 iio_trigger_free(st->trig[i]);
656         }
657 error_ret:
658         return ret;
659 }
660 
661 static void at91_adc_trigger_remove(struct iio_dev *idev)
662 {
663         struct at91_adc_state *st = iio_priv(idev);
664         int i;
665 
666         for (i = 0; i < st->trigger_number; i++) {
667                 iio_trigger_unregister(st->trig[i]);
668                 iio_trigger_free(st->trig[i]);
669         }
670 }
671 
672 static int at91_adc_buffer_init(struct iio_dev *idev)
673 {
674         return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
675                 &at91_adc_trigger_handler, NULL);
676 }
677 
678 static void at91_adc_buffer_remove(struct iio_dev *idev)
679 {
680         iio_triggered_buffer_cleanup(idev);
681 }
682 
683 static int at91_adc_read_raw(struct iio_dev *idev,
684                              struct iio_chan_spec const *chan,
685                              int *val, int *val2, long mask)
686 {
687         struct at91_adc_state *st = iio_priv(idev);
688         int ret;
689 
690         switch (mask) {
691         case IIO_CHAN_INFO_RAW:
692                 mutex_lock(&st->lock);
693 
694                 st->chnb = chan->channel;
695                 at91_adc_writel(st, AT91_ADC_CHER,
696                                 AT91_ADC_CH(chan->channel));
697                 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
698                 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
699 
700                 ret = wait_event_interruptible_timeout(st->wq_data_avail,
701                                                        st->done,
702                                                        msecs_to_jiffies(1000));
703                 if (ret == 0)
704                         ret = -ETIMEDOUT;
705                 if (ret < 0) {
706                         mutex_unlock(&st->lock);
707                         return ret;
708                 }
709 
710                 *val = st->last_value;
711 
712                 at91_adc_writel(st, AT91_ADC_CHDR,
713                                 AT91_ADC_CH(chan->channel));
714                 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
715 
716                 st->last_value = 0;
717                 st->done = false;
718                 mutex_unlock(&st->lock);
719                 return IIO_VAL_INT;
720 
721         case IIO_CHAN_INFO_SCALE:
722                 *val = st->vref_mv;
723                 *val2 = chan->scan_type.realbits;
724                 return IIO_VAL_FRACTIONAL_LOG2;
725         default:
726                 break;
727         }
728         return -EINVAL;
729 }
730 
731 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
732                                       struct platform_device *pdev)
733 {
734         struct iio_dev *idev = iio_priv_to_dev(st);
735         struct device_node *np = pdev->dev.of_node;
736         int count, i, ret = 0;
737         char *res_name, *s;
738         u32 *resolutions;
739 
740         count = of_property_count_strings(np, "atmel,adc-res-names");
741         if (count < 2) {
742                 dev_err(&idev->dev, "You must specified at least two resolution names for "
743                                     "adc-res-names property in the DT\n");
744                 return count;
745         }
746 
747         resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
748         if (!resolutions)
749                 return -ENOMEM;
750 
751         if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
752                 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
753                 ret = -ENODEV;
754                 goto ret;
755         }
756 
757         if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
758                 res_name = "highres";
759 
760         for (i = 0; i < count; i++) {
761                 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
762                         continue;
763 
764                 if (strcmp(res_name, s))
765                         continue;
766 
767                 st->res = resolutions[i];
768                 if (!strcmp(res_name, "lowres"))
769                         st->low_res = true;
770                 else
771                         st->low_res = false;
772 
773                 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
774                 goto ret;
775         }
776 
777         dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
778 
779 ret:
780         kfree(resolutions);
781         return ret;
782 }
783 
784 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
785 {
786         /*
787          * Number of ticks needed to cover the startup time of the ADC
788          * as defined in the electrical characteristics of the board,
789          * divided by 8. The formula thus is :
790          *   Startup Time = (ticks + 1) * 8 / ADC Clock
791          */
792         return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
793 }
794 
795 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
796 {
797         /*
798          * For sama5d3x and at91sam9x5, the formula changes to:
799          * Startup Time = <lookup_table_value> / ADC Clock
800          */
801         const int startup_lookup[] = {
802                 0,   8,   16,  24,
803                 64,  80,  96,  112,
804                 512, 576, 640, 704,
805                 768, 832, 896, 960
806                 };
807         int i, size = ARRAY_SIZE(startup_lookup);
808         unsigned int ticks;
809 
810         ticks = startup_time * adc_clk_khz / 1000;
811         for (i = 0; i < size; i++)
812                 if (ticks < startup_lookup[i])
813                         break;
814 
815         ticks = i;
816         if (ticks == size)
817                 /* Reach the end of lookup table */
818                 ticks = size - 1;
819 
820         return ticks;
821 }
822 
823 static const struct of_device_id at91_adc_dt_ids[];
824 
825 static int at91_adc_probe_dt_ts(struct device_node *node,
826         struct at91_adc_state *st, struct device *dev)
827 {
828         int ret;
829         u32 prop;
830 
831         ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
832         if (ret) {
833                 dev_info(dev, "ADC Touch screen is disabled.\n");
834                 return 0;
835         }
836 
837         switch (prop) {
838         case 4:
839         case 5:
840                 st->touchscreen_type = prop;
841                 break;
842         default:
843                 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
844                 return -EINVAL;
845         }
846 
847         if (!st->caps->has_tsmr)
848                 return 0;
849         prop = 0;
850         of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
851         st->ts_pressure_threshold = prop;
852         if (st->ts_pressure_threshold) {
853                 return 0;
854         } else {
855                 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
856                 return -EINVAL;
857         }
858 }
859 
860 static int at91_adc_probe_dt(struct at91_adc_state *st,
861                              struct platform_device *pdev)
862 {
863         struct iio_dev *idev = iio_priv_to_dev(st);
864         struct device_node *node = pdev->dev.of_node;
865         struct device_node *trig_node;
866         int i = 0, ret;
867         u32 prop;
868 
869         if (!node)
870                 return -EINVAL;
871 
872         st->caps = (struct at91_adc_caps *)
873                 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
874 
875         st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
876 
877         if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
878                 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
879                 ret = -EINVAL;
880                 goto error_ret;
881         }
882         st->channels_mask = prop;
883 
884         st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
885 
886         if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
887                 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
888                 ret = -EINVAL;
889                 goto error_ret;
890         }
891         st->startup_time = prop;
892 
893         prop = 0;
894         of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
895         st->sample_hold_time = prop;
896 
897         if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
898                 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
899                 ret = -EINVAL;
900                 goto error_ret;
901         }
902         st->vref_mv = prop;
903 
904         ret = at91_adc_of_get_resolution(st, pdev);
905         if (ret)
906                 goto error_ret;
907 
908         st->registers = &st->caps->registers;
909         st->num_channels = st->caps->num_channels;
910         st->trigger_number = of_get_child_count(node);
911         st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
912                                         sizeof(struct at91_adc_trigger),
913                                         GFP_KERNEL);
914         if (!st->trigger_list) {
915                 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
916                 ret = -ENOMEM;
917                 goto error_ret;
918         }
919 
920         for_each_child_of_node(node, trig_node) {
921                 struct at91_adc_trigger *trig = st->trigger_list + i;
922                 const char *name;
923 
924                 if (of_property_read_string(trig_node, "trigger-name", &name)) {
925                         dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
926                         ret = -EINVAL;
927                         goto error_ret;
928                 }
929                 trig->name = name;
930 
931                 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
932                         dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
933                         ret = -EINVAL;
934                         goto error_ret;
935                 }
936                 trig->value = prop;
937                 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
938                 i++;
939         }
940 
941         /* Check if touchscreen is supported. */
942         if (st->caps->has_ts)
943                 return at91_adc_probe_dt_ts(node, st, &idev->dev);
944         else
945                 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
946 
947         return 0;
948 
949 error_ret:
950         return ret;
951 }
952 
953 static int at91_adc_probe_pdata(struct at91_adc_state *st,
954                                 struct platform_device *pdev)
955 {
956         struct at91_adc_data *pdata = pdev->dev.platform_data;
957 
958         if (!pdata)
959                 return -EINVAL;
960 
961         st->caps = (struct at91_adc_caps *)
962                         platform_get_device_id(pdev)->driver_data;
963 
964         st->use_external = pdata->use_external_triggers;
965         st->vref_mv = pdata->vref;
966         st->channels_mask = pdata->channels_used;
967         st->num_channels = st->caps->num_channels;
968         st->startup_time = pdata->startup_time;
969         st->trigger_number = pdata->trigger_number;
970         st->trigger_list = pdata->trigger_list;
971         st->registers = &st->caps->registers;
972         st->touchscreen_type = pdata->touchscreen_type;
973 
974         return 0;
975 }
976 
977 static const struct iio_info at91_adc_info = {
978         .driver_module = THIS_MODULE,
979         .read_raw = &at91_adc_read_raw,
980 };
981 
982 /* Touchscreen related functions */
983 static int atmel_ts_open(struct input_dev *dev)
984 {
985         struct at91_adc_state *st = input_get_drvdata(dev);
986 
987         if (st->caps->has_tsmr)
988                 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
989         else
990                 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
991         return 0;
992 }
993 
994 static void atmel_ts_close(struct input_dev *dev)
995 {
996         struct at91_adc_state *st = input_get_drvdata(dev);
997 
998         if (st->caps->has_tsmr)
999                 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1000         else
1001                 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1002 }
1003 
1004 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1005 {
1006         struct iio_dev *idev = iio_priv_to_dev(st);
1007         u32 reg = 0;
1008         u32 tssctim = 0;
1009         int i = 0;
1010 
1011         /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1012          * pen detect noise.
1013          * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1014          */
1015         st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1016                                  1000, 1);
1017 
1018         while (st->ts_pendbc >> ++i)
1019                 ;       /* Empty! Find the shift offset */
1020         if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1021                 st->ts_pendbc = i;
1022         else
1023                 st->ts_pendbc = i - 1;
1024 
1025         if (!st->caps->has_tsmr) {
1026                 reg = at91_adc_readl(st, AT91_ADC_MR);
1027                 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1028 
1029                 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1030                 at91_adc_writel(st, AT91_ADC_MR, reg);
1031 
1032                 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1033                 at91_adc_writel(st, AT91_ADC_TSR, reg);
1034 
1035                 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1036                                                     adc_clk_khz / 1000) - 1, 1);
1037 
1038                 return 0;
1039         }
1040 
1041         /* Touchscreen Switches Closure time needed for allowing the value to
1042          * stabilize.
1043          * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
1044          */
1045         tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1046         dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1047                 adc_clk_khz, tssctim);
1048 
1049         if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1050                 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1051         else
1052                 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1053 
1054         reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1055         reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1056                & AT91_ADC_TSMR_TSAV;
1057         reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1058         reg |= AT91_ADC_TSMR_NOTSDMA;
1059         reg |= AT91_ADC_TSMR_PENDET_ENA;
1060         reg |= 0x03 << 8;       /* TSFREQ, needs to be bigger than TSAV */
1061 
1062         at91_adc_writel(st, AT91_ADC_TSMR, reg);
1063 
1064         /* Change adc internal resistor value for better pen detection,
1065          * default value is 100 kOhm.
1066          * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1067          * option only available on ES2 and higher
1068          */
1069         at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1070                         & AT91_ADC_ACR_PENDETSENS);
1071 
1072         /* Sample Period Time = (TRGPER + 1) / ADCClock */
1073         st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1074                         adc_clk_khz / 1000) - 1, 1);
1075 
1076         return 0;
1077 }
1078 
1079 static int at91_ts_register(struct at91_adc_state *st,
1080                 struct platform_device *pdev)
1081 {
1082         struct input_dev *input;
1083         struct iio_dev *idev = iio_priv_to_dev(st);
1084         int ret;
1085 
1086         input = input_allocate_device();
1087         if (!input) {
1088                 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1089                 return -ENOMEM;
1090         }
1091 
1092         input->name = DRIVER_NAME;
1093         input->id.bustype = BUS_HOST;
1094         input->dev.parent = &pdev->dev;
1095         input->open = atmel_ts_open;
1096         input->close = atmel_ts_close;
1097 
1098         __set_bit(EV_ABS, input->evbit);
1099         __set_bit(EV_KEY, input->evbit);
1100         __set_bit(BTN_TOUCH, input->keybit);
1101         if (st->caps->has_tsmr) {
1102                 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1103                                      0, 0);
1104                 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1105                                      0, 0);
1106                 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1107         } else {
1108                 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1109                         dev_err(&pdev->dev,
1110                                 "This touchscreen controller only support 4 wires\n");
1111                         ret = -EINVAL;
1112                         goto err;
1113                 }
1114 
1115                 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1116                                      0, 0);
1117                 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1118                                      0, 0);
1119         }
1120 
1121         st->ts_input = input;
1122         input_set_drvdata(input, st);
1123 
1124         ret = input_register_device(input);
1125         if (ret)
1126                 goto err;
1127 
1128         return ret;
1129 
1130 err:
1131         input_free_device(st->ts_input);
1132         return ret;
1133 }
1134 
1135 static void at91_ts_unregister(struct at91_adc_state *st)
1136 {
1137         input_unregister_device(st->ts_input);
1138 }
1139 
1140 static int at91_adc_probe(struct platform_device *pdev)
1141 {
1142         unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1143         int ret;
1144         struct iio_dev *idev;
1145         struct at91_adc_state *st;
1146         struct resource *res;
1147         u32 reg;
1148 
1149         idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1150         if (!idev)
1151                 return -ENOMEM;
1152 
1153         st = iio_priv(idev);
1154 
1155         if (pdev->dev.of_node)
1156                 ret = at91_adc_probe_dt(st, pdev);
1157         else
1158                 ret = at91_adc_probe_pdata(st, pdev);
1159 
1160         if (ret) {
1161                 dev_err(&pdev->dev, "No platform data available.\n");
1162                 return -EINVAL;
1163         }
1164 
1165         platform_set_drvdata(pdev, idev);
1166 
1167         idev->dev.parent = &pdev->dev;
1168         idev->name = dev_name(&pdev->dev);
1169         idev->modes = INDIO_DIRECT_MODE;
1170         idev->info = &at91_adc_info;
1171 
1172         st->irq = platform_get_irq(pdev, 0);
1173         if (st->irq < 0) {
1174                 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1175                 return -ENODEV;
1176         }
1177 
1178         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1179 
1180         st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1181         if (IS_ERR(st->reg_base)) {
1182                 return PTR_ERR(st->reg_base);
1183         }
1184 
1185         /*
1186          * Disable all IRQs before setting up the handler
1187          */
1188         at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1189         at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1190 
1191         if (st->caps->has_tsmr)
1192                 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1193                                   pdev->dev.driver->name, idev);
1194         else
1195                 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1196                                   pdev->dev.driver->name, idev);
1197         if (ret) {
1198                 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1199                 return ret;
1200         }
1201 
1202         st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1203         if (IS_ERR(st->clk)) {
1204                 dev_err(&pdev->dev, "Failed to get the clock.\n");
1205                 ret = PTR_ERR(st->clk);
1206                 goto error_free_irq;
1207         }
1208 
1209         ret = clk_prepare_enable(st->clk);
1210         if (ret) {
1211                 dev_err(&pdev->dev,
1212                         "Could not prepare or enable the clock.\n");
1213                 goto error_free_irq;
1214         }
1215 
1216         st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1217         if (IS_ERR(st->adc_clk)) {
1218                 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1219                 ret = PTR_ERR(st->adc_clk);
1220                 goto error_disable_clk;
1221         }
1222 
1223         ret = clk_prepare_enable(st->adc_clk);
1224         if (ret) {
1225                 dev_err(&pdev->dev,
1226                         "Could not prepare or enable the ADC clock.\n");
1227                 goto error_disable_clk;
1228         }
1229 
1230         /*
1231          * Prescaler rate computation using the formula from the Atmel's
1232          * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1233          * specified by the electrical characteristics of the board.
1234          */
1235         mstrclk = clk_get_rate(st->clk);
1236         adc_clk = clk_get_rate(st->adc_clk);
1237         adc_clk_khz = adc_clk / 1000;
1238 
1239         dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1240                 mstrclk, adc_clk);
1241 
1242         prsc = (mstrclk / (2 * adc_clk)) - 1;
1243 
1244         if (!st->startup_time) {
1245                 dev_err(&pdev->dev, "No startup time available.\n");
1246                 ret = -EINVAL;
1247                 goto error_disable_adc_clk;
1248         }
1249         ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1250 
1251         /*
1252          * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1253          * the best converted final value between two channels selection
1254          * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1255          */
1256         if (st->sample_hold_time > 0)
1257                 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1258                                  - 1, 1);
1259         else
1260                 shtim = 0;
1261 
1262         reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1263         reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1264         if (st->low_res)
1265                 reg |= AT91_ADC_LOWRES;
1266         if (st->sleep_mode)
1267                 reg |= AT91_ADC_SLEEP;
1268         reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1269         at91_adc_writel(st, AT91_ADC_MR, reg);
1270 
1271         /* Setup the ADC channels available on the board */
1272         ret = at91_adc_channel_init(idev);
1273         if (ret < 0) {
1274                 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1275                 goto error_disable_adc_clk;
1276         }
1277 
1278         init_waitqueue_head(&st->wq_data_avail);
1279         mutex_init(&st->lock);
1280 
1281         /*
1282          * Since touch screen will set trigger register as period trigger. So
1283          * when touch screen is enabled, then we have to disable hardware
1284          * trigger for classic adc.
1285          */
1286         if (!st->touchscreen_type) {
1287                 ret = at91_adc_buffer_init(idev);
1288                 if (ret < 0) {
1289                         dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1290                         goto error_disable_adc_clk;
1291                 }
1292 
1293                 ret = at91_adc_trigger_init(idev);
1294                 if (ret < 0) {
1295                         dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1296                         at91_adc_buffer_remove(idev);
1297                         goto error_disable_adc_clk;
1298                 }
1299         } else {
1300                 ret = at91_ts_register(st, pdev);
1301                 if (ret)
1302                         goto error_disable_adc_clk;
1303 
1304                 at91_ts_hw_init(st, adc_clk_khz);
1305         }
1306 
1307         ret = iio_device_register(idev);
1308         if (ret < 0) {
1309                 dev_err(&pdev->dev, "Couldn't register the device.\n");
1310                 goto error_iio_device_register;
1311         }
1312 
1313         return 0;
1314 
1315 error_iio_device_register:
1316         if (!st->touchscreen_type) {
1317                 at91_adc_trigger_remove(idev);
1318                 at91_adc_buffer_remove(idev);
1319         } else {
1320                 at91_ts_unregister(st);
1321         }
1322 error_disable_adc_clk:
1323         clk_disable_unprepare(st->adc_clk);
1324 error_disable_clk:
1325         clk_disable_unprepare(st->clk);
1326 error_free_irq:
1327         free_irq(st->irq, idev);
1328         return ret;
1329 }
1330 
1331 static int at91_adc_remove(struct platform_device *pdev)
1332 {
1333         struct iio_dev *idev = platform_get_drvdata(pdev);
1334         struct at91_adc_state *st = iio_priv(idev);
1335 
1336         iio_device_unregister(idev);
1337         if (!st->touchscreen_type) {
1338                 at91_adc_trigger_remove(idev);
1339                 at91_adc_buffer_remove(idev);
1340         } else {
1341                 at91_ts_unregister(st);
1342         }
1343         clk_disable_unprepare(st->adc_clk);
1344         clk_disable_unprepare(st->clk);
1345         free_irq(st->irq, idev);
1346 
1347         return 0;
1348 }
1349 
1350 static struct at91_adc_caps at91sam9260_caps = {
1351         .calc_startup_ticks = calc_startup_ticks_9260,
1352         .num_channels = 4,
1353         .registers = {
1354                 .channel_base = AT91_ADC_CHR(0),
1355                 .drdy_mask = AT91_ADC_DRDY,
1356                 .status_register = AT91_ADC_SR,
1357                 .trigger_register = AT91_ADC_TRGR_9260,
1358                 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1359                 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1360         },
1361 };
1362 
1363 static struct at91_adc_caps at91sam9rl_caps = {
1364         .has_ts = true,
1365         .calc_startup_ticks = calc_startup_ticks_9260,  /* same as 9260 */
1366         .num_channels = 6,
1367         .registers = {
1368                 .channel_base = AT91_ADC_CHR(0),
1369                 .drdy_mask = AT91_ADC_DRDY,
1370                 .status_register = AT91_ADC_SR,
1371                 .trigger_register = AT91_ADC_TRGR_9G45,
1372                 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1373                 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1374         },
1375 };
1376 
1377 static struct at91_adc_caps at91sam9g45_caps = {
1378         .has_ts = true,
1379         .calc_startup_ticks = calc_startup_ticks_9260,  /* same as 9260 */
1380         .num_channels = 8,
1381         .registers = {
1382                 .channel_base = AT91_ADC_CHR(0),
1383                 .drdy_mask = AT91_ADC_DRDY,
1384                 .status_register = AT91_ADC_SR,
1385                 .trigger_register = AT91_ADC_TRGR_9G45,
1386                 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1387                 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1388         },
1389 };
1390 
1391 static struct at91_adc_caps at91sam9x5_caps = {
1392         .has_ts = true,
1393         .has_tsmr = true,
1394         .ts_filter_average = 3,
1395         .ts_pen_detect_sensitivity = 2,
1396         .calc_startup_ticks = calc_startup_ticks_9x5,
1397         .num_channels = 12,
1398         .registers = {
1399                 .channel_base = AT91_ADC_CDR0_9X5,
1400                 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1401                 .status_register = AT91_ADC_SR_9X5,
1402                 .trigger_register = AT91_ADC_TRGR_9X5,
1403                 /* prescal mask is same as 9G45 */
1404                 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1405                 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1406         },
1407 };
1408 
1409 static const struct of_device_id at91_adc_dt_ids[] = {
1410         { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1411         { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1412         { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1413         { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1414         {},
1415 };
1416 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1417 
1418 static const struct platform_device_id at91_adc_ids[] = {
1419         {
1420                 .name = "at91sam9260-adc",
1421                 .driver_data = (unsigned long)&at91sam9260_caps,
1422         }, {
1423                 .name = "at91sam9rl-adc",
1424                 .driver_data = (unsigned long)&at91sam9rl_caps,
1425         }, {
1426                 .name = "at91sam9g45-adc",
1427                 .driver_data = (unsigned long)&at91sam9g45_caps,
1428         }, {
1429                 .name = "at91sam9x5-adc",
1430                 .driver_data = (unsigned long)&at91sam9x5_caps,
1431         }, {
1432                 /* terminator */
1433         }
1434 };
1435 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1436 
1437 static struct platform_driver at91_adc_driver = {
1438         .probe = at91_adc_probe,
1439         .remove = at91_adc_remove,
1440         .id_table = at91_adc_ids,
1441         .driver = {
1442                    .name = DRIVER_NAME,
1443                    .of_match_table = of_match_ptr(at91_adc_dt_ids),
1444         },
1445 };
1446 
1447 module_platform_driver(at91_adc_driver);
1448 
1449 MODULE_LICENSE("GPL");
1450 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1451 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1452 

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