Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/ide/pmac.c

  1 /*
  2  * Support for IDE interfaces on PowerMacs.
  3  *
  4  * These IDE interfaces are memory-mapped and have a DBDMA channel
  5  * for doing DMA.
  6  *
  7  *  Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
  8  *  Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
  9  *
 10  *  This program is free software; you can redistribute it and/or
 11  *  modify it under the terms of the GNU General Public License
 12  *  as published by the Free Software Foundation; either version
 13  *  2 of the License, or (at your option) any later version.
 14  *
 15  * Some code taken from drivers/ide/ide-dma.c:
 16  *
 17  *  Copyright (c) 1995-1998  Mark Lord
 18  *
 19  * TODO: - Use pre-calculated (kauai) timing tables all the time and
 20  * get rid of the "rounded" tables used previously, so we have the
 21  * same table format for all controllers and can then just have one
 22  * big table
 23  * 
 24  */
 25 #include <linux/types.h>
 26 #include <linux/kernel.h>
 27 #include <linux/init.h>
 28 #include <linux/delay.h>
 29 #include <linux/ide.h>
 30 #include <linux/notifier.h>
 31 #include <linux/module.h>
 32 #include <linux/reboot.h>
 33 #include <linux/pci.h>
 34 #include <linux/adb.h>
 35 #include <linux/pmu.h>
 36 #include <linux/scatterlist.h>
 37 #include <linux/slab.h>
 38 
 39 #include <asm/prom.h>
 40 #include <asm/io.h>
 41 #include <asm/dbdma.h>
 42 #include <asm/ide.h>
 43 #include <asm/machdep.h>
 44 #include <asm/pmac_feature.h>
 45 #include <asm/sections.h>
 46 #include <asm/irq.h>
 47 #include <asm/mediabay.h>
 48 
 49 #define DRV_NAME "ide-pmac"
 50 
 51 #undef IDE_PMAC_DEBUG
 52 
 53 #define DMA_WAIT_TIMEOUT        50
 54 
 55 typedef struct pmac_ide_hwif {
 56         unsigned long                   regbase;
 57         int                             irq;
 58         int                             kind;
 59         int                             aapl_bus_id;
 60         unsigned                        broken_dma : 1;
 61         unsigned                        broken_dma_warn : 1;
 62         struct device_node*             node;
 63         struct macio_dev                *mdev;
 64         u32                             timings[4];
 65         volatile u32 __iomem *          *kauai_fcr;
 66         ide_hwif_t                      *hwif;
 67 
 68         /* Those fields are duplicating what is in hwif. We currently
 69          * can't use the hwif ones because of some assumptions that are
 70          * beeing done by the generic code about the kind of dma controller
 71          * and format of the dma table. This will have to be fixed though.
 72          */
 73         volatile struct dbdma_regs __iomem *    dma_regs;
 74         struct dbdma_cmd*               dma_table_cpu;
 75 } pmac_ide_hwif_t;
 76 
 77 enum {
 78         controller_ohare,       /* OHare based */
 79         controller_heathrow,    /* Heathrow/Paddington */
 80         controller_kl_ata3,     /* KeyLargo ATA-3 */
 81         controller_kl_ata4,     /* KeyLargo ATA-4 */
 82         controller_un_ata6,     /* UniNorth2 ATA-6 */
 83         controller_k2_ata6,     /* K2 ATA-6 */
 84         controller_sh_ata6,     /* Shasta ATA-6 */
 85 };
 86 
 87 static const char* model_name[] = {
 88         "OHare ATA",            /* OHare based */
 89         "Heathrow ATA",         /* Heathrow/Paddington */
 90         "KeyLargo ATA-3",       /* KeyLargo ATA-3 (MDMA only) */
 91         "KeyLargo ATA-4",       /* KeyLargo ATA-4 (UDMA/66) */
 92         "UniNorth ATA-6",       /* UniNorth2 ATA-6 (UDMA/100) */
 93         "K2 ATA-6",             /* K2 ATA-6 (UDMA/100) */
 94         "Shasta ATA-6",         /* Shasta ATA-6 (UDMA/133) */
 95 };
 96 
 97 /*
 98  * Extra registers, both 32-bit little-endian
 99  */
100 #define IDE_TIMING_CONFIG       0x200
101 #define IDE_INTERRUPT           0x300
102 
103 /* Kauai (U2) ATA has different register setup */
104 #define IDE_KAUAI_PIO_CONFIG    0x200
105 #define IDE_KAUAI_ULTRA_CONFIG  0x210
106 #define IDE_KAUAI_POLL_CONFIG   0x220
107 
108 /*
109  * Timing configuration register definitions
110  */
111 
112 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
113 #define SYSCLK_TICKS(t)         (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
114 #define SYSCLK_TICKS_66(t)      (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
115 #define IDE_SYSCLK_NS           30      /* 33Mhz cell */
116 #define IDE_SYSCLK_66_NS        15      /* 66Mhz cell */
117 
118 /* 133Mhz cell, found in shasta.
119  * See comments about 100 Mhz Uninorth 2...
120  * Note that PIO_MASK and MDMA_MASK seem to overlap
121  */
122 #define TR_133_PIOREG_PIO_MASK          0xff000fff
123 #define TR_133_PIOREG_MDMA_MASK         0x00fff800
124 #define TR_133_UDMAREG_UDMA_MASK        0x0003ffff
125 #define TR_133_UDMAREG_UDMA_EN          0x00000001
126 
127 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
128  * this one yet, it appears as a pci device (106b/0033) on uninorth
129  * internal PCI bus and it's clock is controlled like gem or fw. It
130  * appears to be an evolution of keylargo ATA4 with a timing register
131  * extended to 2 32bits registers and a similar DBDMA channel. Other
132  * registers seem to exist but I can't tell much about them.
133  * 
134  * So far, I'm using pre-calculated tables for this extracted from
135  * the values used by the MacOS X driver.
136  * 
137  * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
138  * register controls the UDMA timings. At least, it seems bit 0
139  * of this one enables UDMA vs. MDMA, and bits 4..7 are the
140  * cycle time in units of 10ns. Bits 8..15 are used by I don't
141  * know their meaning yet
142  */
143 #define TR_100_PIOREG_PIO_MASK          0xff000fff
144 #define TR_100_PIOREG_MDMA_MASK         0x00fff000
145 #define TR_100_UDMAREG_UDMA_MASK        0x0000ffff
146 #define TR_100_UDMAREG_UDMA_EN          0x00000001
147 
148 
149 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
150  * 40 connector cable and to 4 on 80 connector one.
151  * Clock unit is 15ns (66Mhz)
152  * 
153  * 3 Values can be programmed:
154  *  - Write data setup, which appears to match the cycle time. They
155  *    also call it DIOW setup.
156  *  - Ready to pause time (from spec)
157  *  - Address setup. That one is weird. I don't see where exactly
158  *    it fits in UDMA cycles, I got it's name from an obscure piece
159  *    of commented out code in Darwin. They leave it to 0, we do as
160  *    well, despite a comment that would lead to think it has a
161  *    min value of 45ns.
162  * Apple also add 60ns to the write data setup (or cycle time ?) on
163  * reads.
164  */
165 #define TR_66_UDMA_MASK                 0xfff00000
166 #define TR_66_UDMA_EN                   0x00100000 /* Enable Ultra mode for DMA */
167 #define TR_66_UDMA_ADDRSETUP_MASK       0xe0000000 /* Address setup */
168 #define TR_66_UDMA_ADDRSETUP_SHIFT      29
169 #define TR_66_UDMA_RDY2PAUS_MASK        0x1e000000 /* Ready 2 pause time */
170 #define TR_66_UDMA_RDY2PAUS_SHIFT       25
171 #define TR_66_UDMA_WRDATASETUP_MASK     0x01e00000 /* Write data setup time */
172 #define TR_66_UDMA_WRDATASETUP_SHIFT    21
173 #define TR_66_MDMA_MASK                 0x000ffc00
174 #define TR_66_MDMA_RECOVERY_MASK        0x000f8000
175 #define TR_66_MDMA_RECOVERY_SHIFT       15
176 #define TR_66_MDMA_ACCESS_MASK          0x00007c00
177 #define TR_66_MDMA_ACCESS_SHIFT         10
178 #define TR_66_PIO_MASK                  0x000003ff
179 #define TR_66_PIO_RECOVERY_MASK         0x000003e0
180 #define TR_66_PIO_RECOVERY_SHIFT        5
181 #define TR_66_PIO_ACCESS_MASK           0x0000001f
182 #define TR_66_PIO_ACCESS_SHIFT          0
183 
184 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
185  * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
186  * 
187  * The access time and recovery time can be programmed. Some older
188  * Darwin code base limit OHare to 150ns cycle time. I decided to do
189  * the same here fore safety against broken old hardware ;)
190  * The HalfTick bit, when set, adds half a clock (15ns) to the access
191  * time and removes one from recovery. It's not supported on KeyLargo
192  * implementation afaik. The E bit appears to be set for PIO mode 0 and
193  * is used to reach long timings used in this mode.
194  */
195 #define TR_33_MDMA_MASK                 0x003ff800
196 #define TR_33_MDMA_RECOVERY_MASK        0x001f0000
197 #define TR_33_MDMA_RECOVERY_SHIFT       16
198 #define TR_33_MDMA_ACCESS_MASK          0x0000f800
199 #define TR_33_MDMA_ACCESS_SHIFT         11
200 #define TR_33_MDMA_HALFTICK             0x00200000
201 #define TR_33_PIO_MASK                  0x000007ff
202 #define TR_33_PIO_E                     0x00000400
203 #define TR_33_PIO_RECOVERY_MASK         0x000003e0
204 #define TR_33_PIO_RECOVERY_SHIFT        5
205 #define TR_33_PIO_ACCESS_MASK           0x0000001f
206 #define TR_33_PIO_ACCESS_SHIFT          0
207 
208 /*
209  * Interrupt register definitions
210  */
211 #define IDE_INTR_DMA                    0x80000000
212 #define IDE_INTR_DEVICE                 0x40000000
213 
214 /*
215  * FCR Register on Kauai. Not sure what bit 0x4 is  ...
216  */
217 #define KAUAI_FCR_UATA_MAGIC            0x00000004
218 #define KAUAI_FCR_UATA_RESET_N          0x00000002
219 #define KAUAI_FCR_UATA_ENABLE           0x00000001
220 
221 /* Rounded Multiword DMA timings
222  * 
223  * I gave up finding a generic formula for all controller
224  * types and instead, built tables based on timing values
225  * used by Apple in Darwin's implementation.
226  */
227 struct mdma_timings_t {
228         int     accessTime;
229         int     recoveryTime;
230         int     cycleTime;
231 };
232 
233 struct mdma_timings_t mdma_timings_33[] =
234 {
235     { 240, 240, 480 },
236     { 180, 180, 360 },
237     { 135, 135, 270 },
238     { 120, 120, 240 },
239     { 105, 105, 210 },
240     {  90,  90, 180 },
241     {  75,  75, 150 },
242     {  75,  45, 120 },
243     {   0,   0,   0 }
244 };
245 
246 struct mdma_timings_t mdma_timings_33k[] =
247 {
248     { 240, 240, 480 },
249     { 180, 180, 360 },
250     { 150, 150, 300 },
251     { 120, 120, 240 },
252     {  90, 120, 210 },
253     {  90,  90, 180 },
254     {  90,  60, 150 },
255     {  90,  30, 120 },
256     {   0,   0,   0 }
257 };
258 
259 struct mdma_timings_t mdma_timings_66[] =
260 {
261     { 240, 240, 480 },
262     { 180, 180, 360 },
263     { 135, 135, 270 },
264     { 120, 120, 240 },
265     { 105, 105, 210 },
266     {  90,  90, 180 },
267     {  90,  75, 165 },
268     {  75,  45, 120 },
269     {   0,   0,   0 }
270 };
271 
272 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
273 struct {
274         int     addrSetup; /* ??? */
275         int     rdy2pause;
276         int     wrDataSetup;
277 } kl66_udma_timings[] =
278 {
279     {   0, 180,  120 }, /* Mode 0 */
280     {   0, 150,  90 },  /*      1 */
281     {   0, 120,  60 },  /*      2 */
282     {   0, 90,   45 },  /*      3 */
283     {   0, 90,   30 }   /*      4 */
284 };
285 
286 /* UniNorth 2 ATA/100 timings */
287 struct kauai_timing {
288         int     cycle_time;
289         u32     timing_reg;
290 };
291 
292 static struct kauai_timing      kauai_pio_timings[] =
293 {
294         { 930   , 0x08000fff },
295         { 600   , 0x08000a92 },
296         { 383   , 0x0800060f },
297         { 360   , 0x08000492 },
298         { 330   , 0x0800048f },
299         { 300   , 0x080003cf },
300         { 270   , 0x080003cc },
301         { 240   , 0x0800038b },
302         { 239   , 0x0800030c },
303         { 180   , 0x05000249 },
304         { 120   , 0x04000148 },
305         { 0     , 0 },
306 };
307 
308 static struct kauai_timing      kauai_mdma_timings[] =
309 {
310         { 1260  , 0x00fff000 },
311         { 480   , 0x00618000 },
312         { 360   , 0x00492000 },
313         { 270   , 0x0038e000 },
314         { 240   , 0x0030c000 },
315         { 210   , 0x002cb000 },
316         { 180   , 0x00249000 },
317         { 150   , 0x00209000 },
318         { 120   , 0x00148000 },
319         { 0     , 0 },
320 };
321 
322 static struct kauai_timing      kauai_udma_timings[] =
323 {
324         { 120   , 0x000070c0 },
325         { 90    , 0x00005d80 },
326         { 60    , 0x00004a60 },
327         { 45    , 0x00003a50 },
328         { 30    , 0x00002a30 },
329         { 20    , 0x00002921 },
330         { 0     , 0 },
331 };
332 
333 static struct kauai_timing      shasta_pio_timings[] =
334 {
335         { 930   , 0x08000fff },
336         { 600   , 0x0A000c97 },
337         { 383   , 0x07000712 },
338         { 360   , 0x040003cd },
339         { 330   , 0x040003cd },
340         { 300   , 0x040003cd },
341         { 270   , 0x040003cd },
342         { 240   , 0x040003cd },
343         { 239   , 0x040003cd },
344         { 180   , 0x0400028b },
345         { 120   , 0x0400010a },
346         { 0     , 0 },
347 };
348 
349 static struct kauai_timing      shasta_mdma_timings[] =
350 {
351         { 1260  , 0x00fff000 },
352         { 480   , 0x00820800 },
353         { 360   , 0x00820800 },
354         { 270   , 0x00820800 },
355         { 240   , 0x00820800 },
356         { 210   , 0x00820800 },
357         { 180   , 0x00820800 },
358         { 150   , 0x0028b000 },
359         { 120   , 0x001ca000 },
360         { 0     , 0 },
361 };
362 
363 static struct kauai_timing      shasta_udma133_timings[] =
364 {
365         { 120   , 0x00035901, },
366         { 90    , 0x000348b1, },
367         { 60    , 0x00033881, },
368         { 45    , 0x00033861, },
369         { 30    , 0x00033841, },
370         { 20    , 0x00033031, },
371         { 15    , 0x00033021, },
372         { 0     , 0 },
373 };
374 
375 
376 static inline u32
377 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
378 {
379         int i;
380         
381         for (i=0; table[i].cycle_time; i++)
382                 if (cycle_time > table[i+1].cycle_time)
383                         return table[i].timing_reg;
384         BUG();
385         return 0;
386 }
387 
388 /* allow up to 256 DBDMA commands per xfer */
389 #define MAX_DCMDS               256
390 
391 /* 
392  * Wait 1s for disk to answer on IDE bus after a hard reset
393  * of the device (via GPIO/FCR).
394  * 
395  * Some devices seem to "pollute" the bus even after dropping
396  * the BSY bit (typically some combo drives slave on the UDMA
397  * bus) after a hard reset. Since we hard reset all drives on
398  * KeyLargo ATA66, we have to keep that delay around. I may end
399  * up not hard resetting anymore on these and keep the delay only
400  * for older interfaces instead (we have to reset when coming
401  * from MacOS...) --BenH. 
402  */
403 #define IDE_WAKEUP_DELAY        (1*HZ)
404 
405 static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
406 
407 #define PMAC_IDE_REG(x) \
408         ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
409 
410 /*
411  * Apply the timings of the proper unit (master/slave) to the shared
412  * timing register when selecting that unit. This version is for
413  * ASICs with a single timing register
414  */
415 static void pmac_ide_apply_timings(ide_drive_t *drive)
416 {
417         ide_hwif_t *hwif = drive->hwif;
418         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
419 
420         if (drive->dn & 1)
421                 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
422         else
423                 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
424         (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
425 }
426 
427 /*
428  * Apply the timings of the proper unit (master/slave) to the shared
429  * timing register when selecting that unit. This version is for
430  * ASICs with a dual timing register (Kauai)
431  */
432 static void pmac_ide_kauai_apply_timings(ide_drive_t *drive)
433 {
434         ide_hwif_t *hwif = drive->hwif;
435         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
436 
437         if (drive->dn & 1) {
438                 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
439                 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
440         } else {
441                 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
442                 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
443         }
444         (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
445 }
446 
447 /*
448  * Force an update of controller timing values for a given drive
449  */
450 static void
451 pmac_ide_do_update_timings(ide_drive_t *drive)
452 {
453         ide_hwif_t *hwif = drive->hwif;
454         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
455 
456         if (pmif->kind == controller_sh_ata6 ||
457             pmif->kind == controller_un_ata6 ||
458             pmif->kind == controller_k2_ata6)
459                 pmac_ide_kauai_apply_timings(drive);
460         else
461                 pmac_ide_apply_timings(drive);
462 }
463 
464 static void pmac_dev_select(ide_drive_t *drive)
465 {
466         pmac_ide_apply_timings(drive);
467 
468         writeb(drive->select | ATA_DEVICE_OBS,
469                (void __iomem *)drive->hwif->io_ports.device_addr);
470 }
471 
472 static void pmac_kauai_dev_select(ide_drive_t *drive)
473 {
474         pmac_ide_kauai_apply_timings(drive);
475 
476         writeb(drive->select | ATA_DEVICE_OBS,
477                (void __iomem *)drive->hwif->io_ports.device_addr);
478 }
479 
480 static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
481 {
482         writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
483         (void)readl((void __iomem *)(hwif->io_ports.data_addr
484                                      + IDE_TIMING_CONFIG));
485 }
486 
487 static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
488 {
489         writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
490         (void)readl((void __iomem *)(hwif->io_ports.data_addr
491                                      + IDE_TIMING_CONFIG));
492 }
493 
494 /*
495  * Old tuning functions (called on hdparm -p), sets up drive PIO timings
496  */
497 static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
498 {
499         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
500         const u8 pio = drive->pio_mode - XFER_PIO_0;
501         struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
502         u32 *timings, t;
503         unsigned accessTicks, recTicks;
504         unsigned accessTime, recTime;
505         unsigned int cycle_time;
506 
507         /* which drive is it ? */
508         timings = &pmif->timings[drive->dn & 1];
509         t = *timings;
510 
511         cycle_time = ide_pio_cycle_time(drive, pio);
512 
513         switch (pmif->kind) {
514         case controller_sh_ata6: {
515                 /* 133Mhz cell */
516                 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
517                 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
518                 break;
519                 }
520         case controller_un_ata6:
521         case controller_k2_ata6: {
522                 /* 100Mhz cell */
523                 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
524                 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
525                 break;
526                 }
527         case controller_kl_ata4:
528                 /* 66Mhz cell */
529                 recTime = cycle_time - tim->active - tim->setup;
530                 recTime = max(recTime, 150U);
531                 accessTime = tim->active;
532                 accessTime = max(accessTime, 150U);
533                 accessTicks = SYSCLK_TICKS_66(accessTime);
534                 accessTicks = min(accessTicks, 0x1fU);
535                 recTicks = SYSCLK_TICKS_66(recTime);
536                 recTicks = min(recTicks, 0x1fU);
537                 t = (t & ~TR_66_PIO_MASK) |
538                         (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
539                         (recTicks << TR_66_PIO_RECOVERY_SHIFT);
540                 break;
541         default: {
542                 /* 33Mhz cell */
543                 int ebit = 0;
544                 recTime = cycle_time - tim->active - tim->setup;
545                 recTime = max(recTime, 150U);
546                 accessTime = tim->active;
547                 accessTime = max(accessTime, 150U);
548                 accessTicks = SYSCLK_TICKS(accessTime);
549                 accessTicks = min(accessTicks, 0x1fU);
550                 accessTicks = max(accessTicks, 4U);
551                 recTicks = SYSCLK_TICKS(recTime);
552                 recTicks = min(recTicks, 0x1fU);
553                 recTicks = max(recTicks, 5U) - 4;
554                 if (recTicks > 9) {
555                         recTicks--; /* guess, but it's only for PIO0, so... */
556                         ebit = 1;
557                 }
558                 t = (t & ~TR_33_PIO_MASK) |
559                                 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
560                                 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
561                 if (ebit)
562                         t |= TR_33_PIO_E;
563                 break;
564                 }
565         }
566 
567 #ifdef IDE_PMAC_DEBUG
568         printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
569                 drive->name, pio,  *timings);
570 #endif  
571 
572         *timings = t;
573         pmac_ide_do_update_timings(drive);
574 }
575 
576 /*
577  * Calculate KeyLargo ATA/66 UDMA timings
578  */
579 static int
580 set_timings_udma_ata4(u32 *timings, u8 speed)
581 {
582         unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
583 
584         if (speed > XFER_UDMA_4)
585                 return 1;
586 
587         rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
588         wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
589         addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
590 
591         *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
592                         (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | 
593                         (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
594                         (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
595                         TR_66_UDMA_EN;
596 #ifdef IDE_PMAC_DEBUG
597         printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
598                 speed & 0xf,  *timings);
599 #endif  
600 
601         return 0;
602 }
603 
604 /*
605  * Calculate Kauai ATA/100 UDMA timings
606  */
607 static int
608 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
609 {
610         struct ide_timing *t = ide_timing_find_mode(speed);
611         u32 tr;
612 
613         if (speed > XFER_UDMA_5 || t == NULL)
614                 return 1;
615         tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
616         *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
617         *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
618 
619         return 0;
620 }
621 
622 /*
623  * Calculate Shasta ATA/133 UDMA timings
624  */
625 static int
626 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
627 {
628         struct ide_timing *t = ide_timing_find_mode(speed);
629         u32 tr;
630 
631         if (speed > XFER_UDMA_6 || t == NULL)
632                 return 1;
633         tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
634         *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
635         *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
636 
637         return 0;
638 }
639 
640 /*
641  * Calculate MDMA timings for all cells
642  */
643 static void
644 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
645                         u8 speed)
646 {
647         u16 *id = drive->id;
648         int cycleTime, accessTime = 0, recTime = 0;
649         unsigned accessTicks, recTicks;
650         struct mdma_timings_t* tm = NULL;
651         int i;
652 
653         /* Get default cycle time for mode */
654         switch(speed & 0xf) {
655                 case 0: cycleTime = 480; break;
656                 case 1: cycleTime = 150; break;
657                 case 2: cycleTime = 120; break;
658                 default:
659                         BUG();
660                         break;
661         }
662 
663         /* Check if drive provides explicit DMA cycle time */
664         if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
665                 cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
666 
667         /* OHare limits according to some old Apple sources */  
668         if ((intf_type == controller_ohare) && (cycleTime < 150))
669                 cycleTime = 150;
670         /* Get the proper timing array for this controller */
671         switch(intf_type) {
672                 case controller_sh_ata6:
673                 case controller_un_ata6:
674                 case controller_k2_ata6:
675                         break;
676                 case controller_kl_ata4:
677                         tm = mdma_timings_66;
678                         break;
679                 case controller_kl_ata3:
680                         tm = mdma_timings_33k;
681                         break;
682                 default:
683                         tm = mdma_timings_33;
684                         break;
685         }
686         if (tm != NULL) {
687                 /* Lookup matching access & recovery times */
688                 i = -1;
689                 for (;;) {
690                         if (tm[i+1].cycleTime < cycleTime)
691                                 break;
692                         i++;
693                 }
694                 cycleTime = tm[i].cycleTime;
695                 accessTime = tm[i].accessTime;
696                 recTime = tm[i].recoveryTime;
697 
698 #ifdef IDE_PMAC_DEBUG
699                 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
700                         drive->name, cycleTime, accessTime, recTime);
701 #endif
702         }
703         switch(intf_type) {
704         case controller_sh_ata6: {
705                 /* 133Mhz cell */
706                 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
707                 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
708                 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
709                 }
710         case controller_un_ata6:
711         case controller_k2_ata6: {
712                 /* 100Mhz cell */
713                 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
714                 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
715                 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
716                 }
717                 break;
718         case controller_kl_ata4:
719                 /* 66Mhz cell */
720                 accessTicks = SYSCLK_TICKS_66(accessTime);
721                 accessTicks = min(accessTicks, 0x1fU);
722                 accessTicks = max(accessTicks, 0x1U);
723                 recTicks = SYSCLK_TICKS_66(recTime);
724                 recTicks = min(recTicks, 0x1fU);
725                 recTicks = max(recTicks, 0x3U);
726                 /* Clear out mdma bits and disable udma */
727                 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
728                         (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
729                         (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
730                 break;
731         case controller_kl_ata3:
732                 /* 33Mhz cell on KeyLargo */
733                 accessTicks = SYSCLK_TICKS(accessTime);
734                 accessTicks = max(accessTicks, 1U);
735                 accessTicks = min(accessTicks, 0x1fU);
736                 accessTime = accessTicks * IDE_SYSCLK_NS;
737                 recTicks = SYSCLK_TICKS(recTime);
738                 recTicks = max(recTicks, 1U);
739                 recTicks = min(recTicks, 0x1fU);
740                 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
741                                 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
742                                 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
743                 break;
744         default: {
745                 /* 33Mhz cell on others */
746                 int halfTick = 0;
747                 int origAccessTime = accessTime;
748                 int origRecTime = recTime;
749                 
750                 accessTicks = SYSCLK_TICKS(accessTime);
751                 accessTicks = max(accessTicks, 1U);
752                 accessTicks = min(accessTicks, 0x1fU);
753                 accessTime = accessTicks * IDE_SYSCLK_NS;
754                 recTicks = SYSCLK_TICKS(recTime);
755                 recTicks = max(recTicks, 2U) - 1;
756                 recTicks = min(recTicks, 0x1fU);
757                 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
758                 if ((accessTicks > 1) &&
759                     ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
760                     ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
761                         halfTick = 1;
762                         accessTicks--;
763                 }
764                 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
765                                 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
766                                 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
767                 if (halfTick)
768                         *timings |= TR_33_MDMA_HALFTICK;
769                 }
770         }
771 #ifdef IDE_PMAC_DEBUG
772         printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
773                 drive->name, speed & 0xf,  *timings);
774 #endif  
775 }
776 
777 static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
778 {
779         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
780         int ret = 0;
781         u32 *timings, *timings2, tl[2];
782         u8 unit = drive->dn & 1;
783         const u8 speed = drive->dma_mode;
784 
785         timings = &pmif->timings[unit];
786         timings2 = &pmif->timings[unit+2];
787 
788         /* Copy timings to local image */
789         tl[0] = *timings;
790         tl[1] = *timings2;
791 
792         if (speed >= XFER_UDMA_0) {
793                 if (pmif->kind == controller_kl_ata4)
794                         ret = set_timings_udma_ata4(&tl[0], speed);
795                 else if (pmif->kind == controller_un_ata6
796                          || pmif->kind == controller_k2_ata6)
797                         ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
798                 else if (pmif->kind == controller_sh_ata6)
799                         ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
800                 else
801                         ret = -1;
802         } else
803                 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
804 
805         if (ret)
806                 return;
807 
808         /* Apply timings to controller */
809         *timings = tl[0];
810         *timings2 = tl[1];
811 
812         pmac_ide_do_update_timings(drive);      
813 }
814 
815 /*
816  * Blast some well known "safe" values to the timing registers at init or
817  * wakeup from sleep time, before we do real calculation
818  */
819 static void
820 sanitize_timings(pmac_ide_hwif_t *pmif)
821 {
822         unsigned int value, value2 = 0;
823         
824         switch(pmif->kind) {
825                 case controller_sh_ata6:
826                         value = 0x0a820c97;
827                         value2 = 0x00033031;
828                         break;
829                 case controller_un_ata6:
830                 case controller_k2_ata6:
831                         value = 0x08618a92;
832                         value2 = 0x00002921;
833                         break;
834                 case controller_kl_ata4:
835                         value = 0x0008438c;
836                         break;
837                 case controller_kl_ata3:
838                         value = 0x00084526;
839                         break;
840                 case controller_heathrow:
841                 case controller_ohare:
842                 default:
843                         value = 0x00074526;
844                         break;
845         }
846         pmif->timings[0] = pmif->timings[1] = value;
847         pmif->timings[2] = pmif->timings[3] = value2;
848 }
849 
850 static int on_media_bay(pmac_ide_hwif_t *pmif)
851 {
852         return pmif->mdev && pmif->mdev->media_bay != NULL;
853 }
854 
855 /* Suspend call back, should be called after the child devices
856  * have actually been suspended
857  */
858 static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
859 {
860         /* We clear the timings */
861         pmif->timings[0] = 0;
862         pmif->timings[1] = 0;
863         
864         disable_irq(pmif->irq);
865 
866         /* The media bay will handle itself just fine */
867         if (on_media_bay(pmif))
868                 return 0;
869         
870         /* Kauai has bus control FCRs directly here */
871         if (pmif->kauai_fcr) {
872                 u32 fcr = readl(pmif->kauai_fcr);
873                 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
874                 writel(fcr, pmif->kauai_fcr);
875         }
876 
877         /* Disable the bus on older machines and the cell on kauai */
878         ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
879                             0);
880 
881         return 0;
882 }
883 
884 /* Resume call back, should be called before the child devices
885  * are resumed
886  */
887 static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
888 {
889         /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
890         if (!on_media_bay(pmif)) {
891                 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
892                 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
893                 msleep(10);
894                 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
895 
896                 /* Kauai has it different */
897                 if (pmif->kauai_fcr) {
898                         u32 fcr = readl(pmif->kauai_fcr);
899                         fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
900                         writel(fcr, pmif->kauai_fcr);
901                 }
902 
903                 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
904         }
905 
906         /* Sanitize drive timings */
907         sanitize_timings(pmif);
908 
909         enable_irq(pmif->irq);
910 
911         return 0;
912 }
913 
914 static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
915 {
916         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
917         struct device_node *np = pmif->node;
918         const char *cable = of_get_property(np, "cable-type", NULL);
919         struct device_node *root = of_find_node_by_path("/");
920         const char *model = of_get_property(root, "model", NULL);
921 
922         /* Get cable type from device-tree. */
923         if (cable && !strncmp(cable, "80-", 3)) {
924                 /* Some drives fail to detect 80c cable in PowerBook */
925                 /* These machine use proprietary short IDE cable anyway */
926                 if (!strncmp(model, "PowerBook", 9))
927                         return ATA_CBL_PATA40_SHORT;
928                 else
929                         return ATA_CBL_PATA80;
930         }
931 
932         /*
933          * G5's seem to have incorrect cable type in device-tree.
934          * Let's assume they have a 80 conductor cable, this seem
935          * to be always the case unless the user mucked around.
936          */
937         if (of_device_is_compatible(np, "K2-UATA") ||
938             of_device_is_compatible(np, "shasta-ata"))
939                 return ATA_CBL_PATA80;
940 
941         return ATA_CBL_PATA40;
942 }
943 
944 static void pmac_ide_init_dev(ide_drive_t *drive)
945 {
946         ide_hwif_t *hwif = drive->hwif;
947         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
948 
949         if (on_media_bay(pmif)) {
950                 if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
951                         drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
952                         return;
953                 }
954                 drive->dev_flags |= IDE_DFLAG_NOPROBE;
955         }
956 }
957 
958 static const struct ide_tp_ops pmac_tp_ops = {
959         .exec_command           = pmac_exec_command,
960         .read_status            = ide_read_status,
961         .read_altstatus         = ide_read_altstatus,
962         .write_devctl           = pmac_write_devctl,
963 
964         .dev_select             = pmac_dev_select,
965         .tf_load                = ide_tf_load,
966         .tf_read                = ide_tf_read,
967 
968         .input_data             = ide_input_data,
969         .output_data            = ide_output_data,
970 };
971 
972 static const struct ide_tp_ops pmac_ata6_tp_ops = {
973         .exec_command           = pmac_exec_command,
974         .read_status            = ide_read_status,
975         .read_altstatus         = ide_read_altstatus,
976         .write_devctl           = pmac_write_devctl,
977 
978         .dev_select             = pmac_kauai_dev_select,
979         .tf_load                = ide_tf_load,
980         .tf_read                = ide_tf_read,
981 
982         .input_data             = ide_input_data,
983         .output_data            = ide_output_data,
984 };
985 
986 static const struct ide_port_ops pmac_ide_ata4_port_ops = {
987         .init_dev               = pmac_ide_init_dev,
988         .set_pio_mode           = pmac_ide_set_pio_mode,
989         .set_dma_mode           = pmac_ide_set_dma_mode,
990         .cable_detect           = pmac_ide_cable_detect,
991 };
992 
993 static const struct ide_port_ops pmac_ide_port_ops = {
994         .init_dev               = pmac_ide_init_dev,
995         .set_pio_mode           = pmac_ide_set_pio_mode,
996         .set_dma_mode           = pmac_ide_set_dma_mode,
997 };
998 
999 static const struct ide_dma_ops pmac_dma_ops;
1000 
1001 static const struct ide_port_info pmac_port_info = {
1002         .name                   = DRV_NAME,
1003         .init_dma               = pmac_ide_init_dma,
1004         .chipset                = ide_pmac,
1005         .tp_ops                 = &pmac_tp_ops,
1006         .port_ops               = &pmac_ide_port_ops,
1007         .dma_ops                = &pmac_dma_ops,
1008         .host_flags             = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1009                                   IDE_HFLAG_POST_SET_MODE |
1010                                   IDE_HFLAG_MMIO |
1011                                   IDE_HFLAG_UNMASK_IRQS,
1012         .pio_mask               = ATA_PIO4,
1013         .mwdma_mask             = ATA_MWDMA2,
1014 };
1015 
1016 /*
1017  * Setup, register & probe an IDE channel driven by this driver, this is
1018  * called by one of the 2 probe functions (macio or PCI).
1019  */
1020 static int pmac_ide_setup_device(pmac_ide_hwif_t *pmif, struct ide_hw *hw)
1021 {
1022         struct device_node *np = pmif->node;
1023         const int *bidp;
1024         struct ide_host *host;
1025         ide_hwif_t *hwif;
1026         struct ide_hw *hws[] = { hw };
1027         struct ide_port_info d = pmac_port_info;
1028         int rc;
1029 
1030         pmif->broken_dma = pmif->broken_dma_warn = 0;
1031         if (of_device_is_compatible(np, "shasta-ata")) {
1032                 pmif->kind = controller_sh_ata6;
1033                 d.tp_ops = &pmac_ata6_tp_ops;
1034                 d.port_ops = &pmac_ide_ata4_port_ops;
1035                 d.udma_mask = ATA_UDMA6;
1036         } else if (of_device_is_compatible(np, "kauai-ata")) {
1037                 pmif->kind = controller_un_ata6;
1038                 d.tp_ops = &pmac_ata6_tp_ops;
1039                 d.port_ops = &pmac_ide_ata4_port_ops;
1040                 d.udma_mask = ATA_UDMA5;
1041         } else if (of_device_is_compatible(np, "K2-UATA")) {
1042                 pmif->kind = controller_k2_ata6;
1043                 d.tp_ops = &pmac_ata6_tp_ops;
1044                 d.port_ops = &pmac_ide_ata4_port_ops;
1045                 d.udma_mask = ATA_UDMA5;
1046         } else if (of_device_is_compatible(np, "keylargo-ata")) {
1047                 if (strcmp(np->name, "ata-4") == 0) {
1048                         pmif->kind = controller_kl_ata4;
1049                         d.port_ops = &pmac_ide_ata4_port_ops;
1050                         d.udma_mask = ATA_UDMA4;
1051                 } else
1052                         pmif->kind = controller_kl_ata3;
1053         } else if (of_device_is_compatible(np, "heathrow-ata")) {
1054                 pmif->kind = controller_heathrow;
1055         } else {
1056                 pmif->kind = controller_ohare;
1057                 pmif->broken_dma = 1;
1058         }
1059 
1060         bidp = of_get_property(np, "AAPL,bus-id", NULL);
1061         pmif->aapl_bus_id =  bidp ? *bidp : 0;
1062 
1063         /* On Kauai-type controllers, we make sure the FCR is correct */
1064         if (pmif->kauai_fcr)
1065                 writel(KAUAI_FCR_UATA_MAGIC |
1066                        KAUAI_FCR_UATA_RESET_N |
1067                        KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1068         
1069         /* Make sure we have sane timings */
1070         sanitize_timings(pmif);
1071 
1072         /* If we are on a media bay, wait for it to settle and lock it */
1073         if (pmif->mdev)
1074                 lock_media_bay(pmif->mdev->media_bay);
1075 
1076         host = ide_host_alloc(&d, hws, 1);
1077         if (host == NULL) {
1078                 rc = -ENOMEM;
1079                 goto bail;
1080         }
1081         hwif = pmif->hwif = host->ports[0];
1082 
1083         if (on_media_bay(pmif)) {
1084                 /* Fixup bus ID for media bay */
1085                 if (!bidp)
1086                         pmif->aapl_bus_id = 1;
1087         } else if (pmif->kind == controller_ohare) {
1088                 /* The code below is having trouble on some ohare machines
1089                  * (timing related ?). Until I can put my hand on one of these
1090                  * units, I keep the old way
1091                  */
1092                 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1093         } else {
1094                 /* This is necessary to enable IDE when net-booting */
1095                 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1096                 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1097                 msleep(10);
1098                 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1099                 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1100         }
1101 
1102         printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1103                "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1104                pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1105                on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
1106 
1107         rc = ide_host_register(host, &d, hws);
1108         if (rc)
1109                 pmif->hwif = NULL;
1110 
1111         if (pmif->mdev)
1112                 unlock_media_bay(pmif->mdev->media_bay);
1113 
1114  bail:
1115         if (rc && host)
1116                 ide_host_free(host);
1117         return rc;
1118 }
1119 
1120 static void pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
1121 {
1122         int i;
1123 
1124         for (i = 0; i < 8; ++i)
1125                 hw->io_ports_array[i] = base + i * 0x10;
1126 
1127         hw->io_ports.ctl_addr = base + 0x160;
1128 }
1129 
1130 /*
1131  * Attach to a macio probed interface
1132  */
1133 static int pmac_ide_macio_attach(struct macio_dev *mdev,
1134                                  const struct of_device_id *match)
1135 {
1136         void __iomem *base;
1137         unsigned long regbase;
1138         pmac_ide_hwif_t *pmif;
1139         int irq, rc;
1140         struct ide_hw hw;
1141 
1142         pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1143         if (pmif == NULL)
1144                 return -ENOMEM;
1145 
1146         if (macio_resource_count(mdev) == 0) {
1147                 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1148                                     mdev->ofdev.dev.of_node->full_name);
1149                 rc = -ENXIO;
1150                 goto out_free_pmif;
1151         }
1152 
1153         /* Request memory resource for IO ports */
1154         if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1155                 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1156                                 "%s!\n", mdev->ofdev.dev.of_node->full_name);
1157                 rc = -EBUSY;
1158                 goto out_free_pmif;
1159         }
1160                         
1161         /* XXX This is bogus. Should be fixed in the registry by checking
1162          * the kind of host interrupt controller, a bit like gatwick
1163          * fixes in irq.c. That works well enough for the single case
1164          * where that happens though...
1165          */
1166         if (macio_irq_count(mdev) == 0) {
1167                 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1168                                     "13\n", mdev->ofdev.dev.of_node->full_name);
1169                 irq = irq_create_mapping(NULL, 13);
1170         } else
1171                 irq = macio_irq(mdev, 0);
1172 
1173         base = ioremap(macio_resource_start(mdev, 0), 0x400);
1174         regbase = (unsigned long) base;
1175 
1176         pmif->mdev = mdev;
1177         pmif->node = mdev->ofdev.dev.of_node;
1178         pmif->regbase = regbase;
1179         pmif->irq = irq;
1180         pmif->kauai_fcr = NULL;
1181 
1182         if (macio_resource_count(mdev) >= 2) {
1183                 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1184                         printk(KERN_WARNING "ide-pmac: can't request DMA "
1185                                             "resource for %s!\n",
1186                                             mdev->ofdev.dev.of_node->full_name);
1187                 else
1188                         pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1189         } else
1190                 pmif->dma_regs = NULL;
1191 
1192         dev_set_drvdata(&mdev->ofdev.dev, pmif);
1193 
1194         memset(&hw, 0, sizeof(hw));
1195         pmac_ide_init_ports(&hw, pmif->regbase);
1196         hw.irq = irq;
1197         hw.dev = &mdev->bus->pdev->dev;
1198         hw.parent = &mdev->ofdev.dev;
1199 
1200         rc = pmac_ide_setup_device(pmif, &hw);
1201         if (rc != 0) {
1202                 /* The inteface is released to the common IDE layer */
1203                 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1204                 iounmap(base);
1205                 if (pmif->dma_regs) {
1206                         iounmap(pmif->dma_regs);
1207                         macio_release_resource(mdev, 1);
1208                 }
1209                 macio_release_resource(mdev, 0);
1210                 kfree(pmif);
1211         }
1212 
1213         return rc;
1214 
1215 out_free_pmif:
1216         kfree(pmif);
1217         return rc;
1218 }
1219 
1220 static int
1221 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1222 {
1223         pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1224         int rc = 0;
1225 
1226         if (mesg.event != mdev->ofdev.dev.power.power_state.event
1227                         && (mesg.event & PM_EVENT_SLEEP)) {
1228                 rc = pmac_ide_do_suspend(pmif);
1229                 if (rc == 0)
1230                         mdev->ofdev.dev.power.power_state = mesg;
1231         }
1232 
1233         return rc;
1234 }
1235 
1236 static int
1237 pmac_ide_macio_resume(struct macio_dev *mdev)
1238 {
1239         pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1240         int rc = 0;
1241 
1242         if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1243                 rc = pmac_ide_do_resume(pmif);
1244                 if (rc == 0)
1245                         mdev->ofdev.dev.power.power_state = PMSG_ON;
1246         }
1247 
1248         return rc;
1249 }
1250 
1251 /*
1252  * Attach to a PCI probed interface
1253  */
1254 static int pmac_ide_pci_attach(struct pci_dev *pdev,
1255                                const struct pci_device_id *id)
1256 {
1257         struct device_node *np;
1258         pmac_ide_hwif_t *pmif;
1259         void __iomem *base;
1260         unsigned long rbase, rlen;
1261         int rc;
1262         struct ide_hw hw;
1263 
1264         np = pci_device_to_OF_node(pdev);
1265         if (np == NULL) {
1266                 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1267                 return -ENODEV;
1268         }
1269 
1270         pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1271         if (pmif == NULL)
1272                 return -ENOMEM;
1273 
1274         if (pci_enable_device(pdev)) {
1275                 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1276                                     "%s\n", np->full_name);
1277                 rc = -ENXIO;
1278                 goto out_free_pmif;
1279         }
1280         pci_set_master(pdev);
1281                         
1282         if (pci_request_regions(pdev, "Kauai ATA")) {
1283                 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1284                                 "%s\n", np->full_name);
1285                 rc = -ENXIO;
1286                 goto out_free_pmif;
1287         }
1288 
1289         pmif->mdev = NULL;
1290         pmif->node = np;
1291 
1292         rbase = pci_resource_start(pdev, 0);
1293         rlen = pci_resource_len(pdev, 0);
1294 
1295         base = ioremap(rbase, rlen);
1296         pmif->regbase = (unsigned long) base + 0x2000;
1297         pmif->dma_regs = base + 0x1000;
1298         pmif->kauai_fcr = base;
1299         pmif->irq = pdev->irq;
1300 
1301         pci_set_drvdata(pdev, pmif);
1302 
1303         memset(&hw, 0, sizeof(hw));
1304         pmac_ide_init_ports(&hw, pmif->regbase);
1305         hw.irq = pdev->irq;
1306         hw.dev = &pdev->dev;
1307 
1308         rc = pmac_ide_setup_device(pmif, &hw);
1309         if (rc != 0) {
1310                 /* The inteface is released to the common IDE layer */
1311                 iounmap(base);
1312                 pci_release_regions(pdev);
1313                 kfree(pmif);
1314         }
1315 
1316         return rc;
1317 
1318 out_free_pmif:
1319         kfree(pmif);
1320         return rc;
1321 }
1322 
1323 static int
1324 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1325 {
1326         pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1327         int rc = 0;
1328 
1329         if (mesg.event != pdev->dev.power.power_state.event
1330                         && (mesg.event & PM_EVENT_SLEEP)) {
1331                 rc = pmac_ide_do_suspend(pmif);
1332                 if (rc == 0)
1333                         pdev->dev.power.power_state = mesg;
1334         }
1335 
1336         return rc;
1337 }
1338 
1339 static int
1340 pmac_ide_pci_resume(struct pci_dev *pdev)
1341 {
1342         pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1343         int rc = 0;
1344 
1345         if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1346                 rc = pmac_ide_do_resume(pmif);
1347                 if (rc == 0)
1348                         pdev->dev.power.power_state = PMSG_ON;
1349         }
1350 
1351         return rc;
1352 }
1353 
1354 #ifdef CONFIG_PMAC_MEDIABAY
1355 static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
1356 {
1357         pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1358 
1359         switch(mb_state) {
1360         case MB_CD:
1361                 if (!pmif->hwif->present)
1362                         ide_port_scan(pmif->hwif);
1363                 break;
1364         default:
1365                 if (pmif->hwif->present)
1366                         ide_port_unregister_devices(pmif->hwif);
1367         }
1368 }
1369 #endif /* CONFIG_PMAC_MEDIABAY */
1370 
1371 
1372 static struct of_device_id pmac_ide_macio_match[] = 
1373 {
1374         {
1375         .name           = "IDE",
1376         },
1377         {
1378         .name           = "ATA",
1379         },
1380         {
1381         .type           = "ide",
1382         },
1383         {
1384         .type           = "ata",
1385         },
1386         {},
1387 };
1388 
1389 static struct macio_driver pmac_ide_macio_driver = 
1390 {
1391         .driver = {
1392                 .name           = "ide-pmac",
1393                 .owner          = THIS_MODULE,
1394                 .of_match_table = pmac_ide_macio_match,
1395         },
1396         .probe          = pmac_ide_macio_attach,
1397         .suspend        = pmac_ide_macio_suspend,
1398         .resume         = pmac_ide_macio_resume,
1399 #ifdef CONFIG_PMAC_MEDIABAY
1400         .mediabay_event = pmac_ide_macio_mb_event,
1401 #endif
1402 };
1403 
1404 static const struct pci_device_id pmac_ide_pci_match[] = {
1405         { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA),    0 },
1406         { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100),  0 },
1407         { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100),    0 },
1408         { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA),       0 },
1409         { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA),    0 },
1410         {},
1411 };
1412 
1413 static struct pci_driver pmac_ide_pci_driver = {
1414         .name           = "ide-pmac",
1415         .id_table       = pmac_ide_pci_match,
1416         .probe          = pmac_ide_pci_attach,
1417         .suspend        = pmac_ide_pci_suspend,
1418         .resume         = pmac_ide_pci_resume,
1419 };
1420 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1421 
1422 int __init pmac_ide_probe(void)
1423 {
1424         int error;
1425 
1426         if (!machine_is(powermac))
1427                 return -ENODEV;
1428 
1429 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1430         error = pci_register_driver(&pmac_ide_pci_driver);
1431         if (error)
1432                 goto out;
1433         error = macio_register_driver(&pmac_ide_macio_driver);
1434         if (error) {
1435                 pci_unregister_driver(&pmac_ide_pci_driver);
1436                 goto out;
1437         }
1438 #else
1439         error = macio_register_driver(&pmac_ide_macio_driver);
1440         if (error)
1441                 goto out;
1442         error = pci_register_driver(&pmac_ide_pci_driver);
1443         if (error) {
1444                 macio_unregister_driver(&pmac_ide_macio_driver);
1445                 goto out;
1446         }
1447 #endif
1448 out:
1449         return error;
1450 }
1451 
1452 /*
1453  * pmac_ide_build_dmatable builds the DBDMA command list
1454  * for a transfer and sets the DBDMA channel to point to it.
1455  */
1456 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
1457 {
1458         ide_hwif_t *hwif = drive->hwif;
1459         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1460         struct dbdma_cmd *table;
1461         volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1462         struct scatterlist *sg;
1463         int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1464         int i = cmd->sg_nents, count = 0;
1465 
1466         /* DMA table is already aligned */
1467         table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1468 
1469         /* Make sure DMA controller is stopped (necessary ?) */
1470         writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1471         while (readl(&dma->status) & RUN)
1472                 udelay(1);
1473 
1474         /* Build DBDMA commands list */
1475         sg = hwif->sg_table;
1476         while (i && sg_dma_len(sg)) {
1477                 u32 cur_addr;
1478                 u32 cur_len;
1479 
1480                 cur_addr = sg_dma_address(sg);
1481                 cur_len = sg_dma_len(sg);
1482 
1483                 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1484                         if (pmif->broken_dma_warn == 0) {
1485                                 printk(KERN_WARNING "%s: DMA on non aligned address, "
1486                                        "switching to PIO on Ohare chipset\n", drive->name);
1487                                 pmif->broken_dma_warn = 1;
1488                         }
1489                         return 0;
1490                 }
1491                 while (cur_len) {
1492                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1493 
1494                         if (count++ >= MAX_DCMDS) {
1495                                 printk(KERN_WARNING "%s: DMA table too small\n",
1496                                        drive->name);
1497                                 return 0;
1498                         }
1499                         table->command = cpu_to_le16(wr? OUTPUT_MORE: INPUT_MORE);
1500                         table->req_count = cpu_to_le16(tc);
1501                         table->phy_addr = cpu_to_le32(cur_addr);
1502                         table->cmd_dep = 0;
1503                         table->xfer_status = 0;
1504                         table->res_count = 0;
1505                         cur_addr += tc;
1506                         cur_len -= tc;
1507                         ++table;
1508                 }
1509                 sg = sg_next(sg);
1510                 i--;
1511         }
1512 
1513         /* convert the last command to an input/output last command */
1514         if (count) {
1515                 table[-1].command = cpu_to_le16(wr? OUTPUT_LAST: INPUT_LAST);
1516                 /* add the stop command to the end of the list */
1517                 memset(table, 0, sizeof(struct dbdma_cmd));
1518                 table->command = cpu_to_le16(DBDMA_STOP);
1519                 mb();
1520                 writel(hwif->dmatable_dma, &dma->cmdptr);
1521                 return 1;
1522         }
1523 
1524         printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1525 
1526         return 0; /* revert to PIO for this request */
1527 }
1528 
1529 /*
1530  * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1531  * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1532  */
1533 static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
1534 {
1535         ide_hwif_t *hwif = drive->hwif;
1536         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1537         u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1538         u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1539 
1540         if (pmac_ide_build_dmatable(drive, cmd) == 0)
1541                 return 1;
1542 
1543         /* Apple adds 60ns to wrDataSetup on reads */
1544         if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1545                 writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
1546                         PMAC_IDE_REG(IDE_TIMING_CONFIG));
1547                 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1548         }
1549 
1550         return 0;
1551 }
1552 
1553 /*
1554  * Kick the DMA controller into life after the DMA command has been issued
1555  * to the drive.
1556  */
1557 static void
1558 pmac_ide_dma_start(ide_drive_t *drive)
1559 {
1560         ide_hwif_t *hwif = drive->hwif;
1561         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1562         volatile struct dbdma_regs __iomem *dma;
1563 
1564         dma = pmif->dma_regs;
1565 
1566         writel((RUN << 16) | RUN, &dma->control);
1567         /* Make sure it gets to the controller right now */
1568         (void)readl(&dma->control);
1569 }
1570 
1571 /*
1572  * After a DMA transfer, make sure the controller is stopped
1573  */
1574 static int
1575 pmac_ide_dma_end (ide_drive_t *drive)
1576 {
1577         ide_hwif_t *hwif = drive->hwif;
1578         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1579         volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1580         u32 dstat;
1581 
1582         dstat = readl(&dma->status);
1583         writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1584 
1585         /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1586          * in theory, but with ATAPI decices doing buffer underruns, that would
1587          * cause us to disable DMA, which isn't what we want
1588          */
1589         return (dstat & (RUN|DEAD)) != RUN;
1590 }
1591 
1592 /*
1593  * Check out that the interrupt we got was for us. We can't always know this
1594  * for sure with those Apple interfaces (well, we could on the recent ones but
1595  * that's not implemented yet), on the other hand, we don't have shared interrupts
1596  * so it's not really a problem
1597  */
1598 static int
1599 pmac_ide_dma_test_irq (ide_drive_t *drive)
1600 {
1601         ide_hwif_t *hwif = drive->hwif;
1602         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1603         volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1604         unsigned long status, timeout;
1605 
1606         /* We have to things to deal with here:
1607          * 
1608          * - The dbdma won't stop if the command was started
1609          * but completed with an error without transferring all
1610          * datas. This happens when bad blocks are met during
1611          * a multi-block transfer.
1612          * 
1613          * - The dbdma fifo hasn't yet finished flushing to
1614          * to system memory when the disk interrupt occurs.
1615          * 
1616          */
1617 
1618         /* If ACTIVE is cleared, the STOP command have passed and
1619          * transfer is complete.
1620          */
1621         status = readl(&dma->status);
1622         if (!(status & ACTIVE))
1623                 return 1;
1624 
1625         /* If dbdma didn't execute the STOP command yet, the
1626          * active bit is still set. We consider that we aren't
1627          * sharing interrupts (which is hopefully the case with
1628          * those controllers) and so we just try to flush the
1629          * channel for pending data in the fifo
1630          */
1631         udelay(1);
1632         writel((FLUSH << 16) | FLUSH, &dma->control);
1633         timeout = 0;
1634         for (;;) {
1635                 udelay(1);
1636                 status = readl(&dma->status);
1637                 if ((status & FLUSH) == 0)
1638                         break;
1639                 if (++timeout > 100) {
1640                         printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
1641                                hwif->index);
1642                         break;
1643                 }
1644         }       
1645         return 1;
1646 }
1647 
1648 static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1649 {
1650 }
1651 
1652 static void
1653 pmac_ide_dma_lost_irq (ide_drive_t *drive)
1654 {
1655         ide_hwif_t *hwif = drive->hwif;
1656         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1657         volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1658         unsigned long status = readl(&dma->status);
1659 
1660         printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1661 }
1662 
1663 static const struct ide_dma_ops pmac_dma_ops = {
1664         .dma_host_set           = pmac_ide_dma_host_set,
1665         .dma_setup              = pmac_ide_dma_setup,
1666         .dma_start              = pmac_ide_dma_start,
1667         .dma_end                = pmac_ide_dma_end,
1668         .dma_test_irq           = pmac_ide_dma_test_irq,
1669         .dma_lost_irq           = pmac_ide_dma_lost_irq,
1670 };
1671 
1672 /*
1673  * Allocate the data structures needed for using DMA with an interface
1674  * and fill the proper list of functions pointers
1675  */
1676 static int pmac_ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
1677 {
1678         pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1679         struct pci_dev *dev = to_pci_dev(hwif->dev);
1680 
1681         /* We won't need pci_dev if we switch to generic consistent
1682          * DMA routines ...
1683          */
1684         if (dev == NULL || pmif->dma_regs == 0)
1685                 return -ENODEV;
1686         /*
1687          * Allocate space for the DBDMA commands.
1688          * The +2 is +1 for the stop command and +1 to allow for
1689          * aligning the start address to a multiple of 16 bytes.
1690          */
1691         pmif->dma_table_cpu = dma_alloc_coherent(&dev->dev,
1692                 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1693                 &hwif->dmatable_dma, GFP_KERNEL);
1694         if (pmif->dma_table_cpu == NULL) {
1695                 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1696                        hwif->name);
1697                 return -ENOMEM;
1698         }
1699 
1700         hwif->sg_max_nents = MAX_DCMDS;
1701 
1702         return 0;
1703 }
1704 
1705 module_init(pmac_ide_probe);
1706 
1707 MODULE_LICENSE("GPL");
1708 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us