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Linux/drivers/ide/palm_bk3710.c

  1 /*
  2  * Palmchip bk3710 IDE controller
  3  *
  4  * Copyright (C) 2006 Texas Instruments.
  5  * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  6  *
  7  * ----------------------------------------------------------------------------
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License as published by
 11  * the Free Software Foundation; either version 2 of the License, or
 12  * (at your option) any later version.
 13  *
 14  * This program is distributed in the hope that it will be useful,
 15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17  * GNU General Public License for more details.
 18  *
 19  *  You should have received a copy of the GNU General Public License
 20  *  along with this program; if not, write to the Free Software
 21  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 22  * ----------------------------------------------------------------------------
 23  *
 24  */
 25 
 26 #include <linux/types.h>
 27 #include <linux/module.h>
 28 #include <linux/kernel.h>
 29 #include <linux/ioport.h>
 30 #include <linux/ide.h>
 31 #include <linux/delay.h>
 32 #include <linux/init.h>
 33 #include <linux/clk.h>
 34 #include <linux/platform_device.h>
 35 
 36 /* Offset of the primary interface registers */
 37 #define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
 38 
 39 /* Primary Control Offset */
 40 #define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
 41 
 42 #define BK3710_BMICP            0x00
 43 #define BK3710_BMISP            0x02
 44 #define BK3710_BMIDTP           0x04
 45 #define BK3710_IDETIMP          0x40
 46 #define BK3710_IDESTATUS        0x47
 47 #define BK3710_UDMACTL          0x48
 48 #define BK3710_MISCCTL          0x50
 49 #define BK3710_REGSTB           0x54
 50 #define BK3710_REGRCVR          0x58
 51 #define BK3710_DATSTB           0x5C
 52 #define BK3710_DATRCVR          0x60
 53 #define BK3710_DMASTB           0x64
 54 #define BK3710_DMARCVR          0x68
 55 #define BK3710_UDMASTB          0x6C
 56 #define BK3710_UDMATRP          0x70
 57 #define BK3710_UDMAENV          0x74
 58 #define BK3710_IORDYTMP         0x78
 59 
 60 static unsigned ideclk_period; /* in nanoseconds */
 61 
 62 struct palm_bk3710_udmatiming {
 63         unsigned int rptime;    /* tRP -- Ready to pause time (nsec) */
 64         unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
 65                                 /* tENV is always a minimum of 20 nsec */
 66 };
 67 
 68 static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
 69         { 160, 240 / 2 },       /* UDMA Mode 0 */
 70         { 125, 160 / 2 },       /* UDMA Mode 1 */
 71         { 100, 120 / 2 },       /* UDMA Mode 2 */
 72         { 100,  90 / 2 },       /* UDMA Mode 3 */
 73         { 100,  60 / 2 },       /* UDMA Mode 4 */
 74         {  85,  40 / 2 },       /* UDMA Mode 5 */
 75 };
 76 
 77 static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
 78                                     unsigned int mode)
 79 {
 80         u8 tenv, trp, t0;
 81         u32 val32;
 82         u16 val16;
 83 
 84         /* DMA Data Setup */
 85         t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
 86                           ideclk_period) - 1;
 87         tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
 88         trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
 89                            ideclk_period) - 1;
 90 
 91         /* udmastb Ultra DMA Access Strobe Width */
 92         val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
 93         val32 |= (t0 << (dev ? 8 : 0));
 94         writel(val32, base + BK3710_UDMASTB);
 95 
 96         /* udmatrp Ultra DMA Ready to Pause Time */
 97         val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
 98         val32 |= (trp << (dev ? 8 : 0));
 99         writel(val32, base + BK3710_UDMATRP);
100 
101         /* udmaenv Ultra DMA envelop Time */
102         val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
103         val32 |= (tenv << (dev ? 8 : 0));
104         writel(val32, base + BK3710_UDMAENV);
105 
106         /* Enable UDMA for Device */
107         val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
108         writew(val16, base + BK3710_UDMACTL);
109 }
110 
111 static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
112                                    unsigned short min_cycle,
113                                    unsigned int mode)
114 {
115         u8 td, tkw, t0;
116         u32 val32;
117         u16 val16;
118         struct ide_timing *t;
119         int cycletime;
120 
121         t = ide_timing_find_mode(mode);
122         cycletime = max_t(int, t->cycle, min_cycle);
123 
124         /* DMA Data Setup */
125         t0 = DIV_ROUND_UP(cycletime, ideclk_period);
126         td = DIV_ROUND_UP(t->active, ideclk_period);
127         tkw = t0 - td - 1;
128         td -= 1;
129 
130         val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
131         val32 |= (td << (dev ? 8 : 0));
132         writel(val32, base + BK3710_DMASTB);
133 
134         val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
135         val32 |= (tkw << (dev ? 8 : 0));
136         writel(val32, base + BK3710_DMARCVR);
137 
138         /* Disable UDMA for Device */
139         val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
140         writew(val16, base + BK3710_UDMACTL);
141 }
142 
143 static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
144                                    unsigned int dev, unsigned int cycletime,
145                                    unsigned int mode)
146 {
147         u8 t2, t2i, t0;
148         u32 val32;
149         struct ide_timing *t;
150 
151         t = ide_timing_find_mode(XFER_PIO_0 + mode);
152 
153         /* PIO Data Setup */
154         t0 = DIV_ROUND_UP(cycletime, ideclk_period);
155         t2 = DIV_ROUND_UP(t->active, ideclk_period);
156 
157         t2i = t0 - t2 - 1;
158         t2 -= 1;
159 
160         val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
161         val32 |= (t2 << (dev ? 8 : 0));
162         writel(val32, base + BK3710_DATSTB);
163 
164         val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
165         val32 |= (t2i << (dev ? 8 : 0));
166         writel(val32, base + BK3710_DATRCVR);
167 
168         if (mate) {
169                 u8 mode2 = mate->pio_mode - XFER_PIO_0;
170 
171                 if (mode2 < mode)
172                         mode = mode2;
173         }
174 
175         /* TASKFILE Setup */
176         t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
177         t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
178 
179         t2i = t0 - t2 - 1;
180         t2 -= 1;
181 
182         val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
183         val32 |= (t2 << (dev ? 8 : 0));
184         writel(val32, base + BK3710_REGSTB);
185 
186         val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
187         val32 |= (t2i << (dev ? 8 : 0));
188         writel(val32, base + BK3710_REGRCVR);
189 }
190 
191 static void palm_bk3710_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
192 {
193         int is_slave = drive->dn & 1;
194         void __iomem *base = (void __iomem *)hwif->dma_base;
195         const u8 xferspeed = drive->dma_mode;
196 
197         if (xferspeed >= XFER_UDMA_0) {
198                 palm_bk3710_setudmamode(base, is_slave,
199                                         xferspeed - XFER_UDMA_0);
200         } else {
201                 palm_bk3710_setdmamode(base, is_slave,
202                                        drive->id[ATA_ID_EIDE_DMA_MIN],
203                                        xferspeed);
204         }
205 }
206 
207 static void palm_bk3710_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
208 {
209         unsigned int cycle_time;
210         int is_slave = drive->dn & 1;
211         ide_drive_t *mate;
212         void __iomem *base = (void __iomem *)hwif->dma_base;
213         const u8 pio = drive->pio_mode - XFER_PIO_0;
214 
215         /*
216          * Obtain the drive PIO data for tuning the Palm Chip registers
217          */
218         cycle_time = ide_pio_cycle_time(drive, pio);
219         mate = ide_get_pair_dev(drive);
220         palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
221 }
222 
223 static void palm_bk3710_chipinit(void __iomem *base)
224 {
225         /*
226          * REVISIT:  the ATA reset signal needs to be managed through a
227          * GPIO, which means it should come from platform_data.  Until
228          * we get and use such information, we have to trust that things
229          * have been reset before we get here.
230          */
231 
232         /*
233          * Program the IDETIMP Register Value based on the following assumptions
234          *
235          * (ATA_IDETIMP_IDEEN           , ENABLE ) |
236          * (ATA_IDETIMP_PREPOST1        , DISABLE) |
237          * (ATA_IDETIMP_PREPOST0        , DISABLE) |
238          *
239          * DM6446 silicon rev 2.1 and earlier have no observed net benefit
240          * from enabling prefetch/postwrite.
241          */
242         writew(BIT(15), base + BK3710_IDETIMP);
243 
244         /*
245          * UDMACTL Ultra-ATA DMA Control
246          * (ATA_UDMACTL_UDMAP1  , 0 ) |
247          * (ATA_UDMACTL_UDMAP0  , 0 )
248          *
249          */
250         writew(0, base + BK3710_UDMACTL);
251 
252         /*
253          * MISCCTL Miscellaneous Conrol Register
254          * (ATA_MISCCTL_HWNHLD1P        , 1 cycle)
255          * (ATA_MISCCTL_HWNHLD0P        , 1 cycle)
256          * (ATA_MISCCTL_TIMORIDE        , 1)
257          */
258         writel(0x001, base + BK3710_MISCCTL);
259 
260         /*
261          * IORDYTMP IORDY Timer for Primary Register
262          * (ATA_IORDYTMP_IORDYTMP     , 0xffff  )
263          */
264         writel(0xFFFF, base + BK3710_IORDYTMP);
265 
266         /*
267          * Configure BMISP Register
268          * (ATA_BMISP_DMAEN1    , DISABLE )     |
269          * (ATA_BMISP_DMAEN0    , DISABLE )     |
270          * (ATA_BMISP_IORDYINT  , CLEAR)        |
271          * (ATA_BMISP_INTRSTAT  , CLEAR)        |
272          * (ATA_BMISP_DMAERROR  , CLEAR)
273          */
274         writew(0, base + BK3710_BMISP);
275 
276         palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
277         palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
278 }
279 
280 static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
281 {
282         return ATA_CBL_PATA80;
283 }
284 
285 static int palm_bk3710_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
286 {
287         printk(KERN_INFO "    %s: MMIO-DMA\n", hwif->name);
288 
289         if (ide_allocate_dma_engine(hwif))
290                 return -1;
291 
292         hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
293 
294         return 0;
295 }
296 
297 static const struct ide_port_ops palm_bk3710_ports_ops = {
298         .set_pio_mode           = palm_bk3710_set_pio_mode,
299         .set_dma_mode           = palm_bk3710_set_dma_mode,
300         .cable_detect           = palm_bk3710_cable_detect,
301 };
302 
303 static struct ide_port_info palm_bk3710_port_info = {
304         .init_dma               = palm_bk3710_init_dma,
305         .port_ops               = &palm_bk3710_ports_ops,
306         .dma_ops                = &sff_dma_ops,
307         .host_flags             = IDE_HFLAG_MMIO,
308         .pio_mask               = ATA_PIO4,
309         .mwdma_mask             = ATA_MWDMA2,
310         .chipset                = ide_palm3710,
311 };
312 
313 static int __init palm_bk3710_probe(struct platform_device *pdev)
314 {
315         struct clk *clk;
316         struct resource *mem, *irq;
317         void __iomem *base;
318         unsigned long rate, mem_size;
319         int i, rc;
320         struct ide_hw hw, *hws[] = { &hw };
321 
322         clk = clk_get(&pdev->dev, NULL);
323         if (IS_ERR(clk))
324                 return -ENODEV;
325 
326         clk_enable(clk);
327         rate = clk_get_rate(clk);
328 
329         /* NOTE:  round *down* to meet minimum timings; we count in clocks */
330         ideclk_period = 1000000000UL / rate;
331 
332         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
333         if (mem == NULL) {
334                 printk(KERN_ERR "failed to get memory region resource\n");
335                 return -ENODEV;
336         }
337 
338         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
339         if (irq == NULL) {
340                 printk(KERN_ERR "failed to get IRQ resource\n");
341                 return -ENODEV;
342         }
343 
344         mem_size = resource_size(mem);
345         if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) {
346                 printk(KERN_ERR "failed to request memory region\n");
347                 return -EBUSY;
348         }
349 
350         base = ioremap(mem->start, mem_size);
351         if (!base) {
352                 printk(KERN_ERR "failed to map IO memory\n");
353                 release_mem_region(mem->start, mem_size);
354                 return -ENOMEM;
355         }
356 
357         /* Configure the Palm Chip controller */
358         palm_bk3710_chipinit(base);
359 
360         memset(&hw, 0, sizeof(hw));
361         for (i = 0; i < IDE_NR_PORTS - 2; i++)
362                 hw.io_ports_array[i] = (unsigned long)
363                                 (base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
364         hw.io_ports.ctl_addr = (unsigned long)
365                         (base + IDE_PALM_ATA_PRI_CTL_OFFSET);
366         hw.irq = irq->start;
367         hw.dev = &pdev->dev;
368 
369         palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
370                                                              ATA_UDMA5;
371 
372         /* Register the IDE interface with Linux */
373         rc = ide_host_add(&palm_bk3710_port_info, hws, 1, NULL);
374         if (rc)
375                 goto out;
376 
377         return 0;
378 out:
379         printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
380         return rc;
381 }
382 
383 /* work with hotplug and coldplug */
384 MODULE_ALIAS("platform:palm_bk3710");
385 
386 static struct platform_driver platform_bk_driver = {
387         .driver = {
388                 .name = "palm_bk3710",
389                 .owner = THIS_MODULE,
390         },
391 };
392 
393 static int __init palm_bk3710_init(void)
394 {
395         return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
396 }
397 
398 module_init(palm_bk3710_init);
399 MODULE_LICENSE("GPL");
400 

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