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Linux/drivers/i2c/busses/i2c-xiic.c

  1 /*
  2  * i2c-xiic.c
  3  * Copyright (c) 2002-2007 Xilinx Inc.
  4  * Copyright (c) 2009-2010 Intel Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  *
 16  * This code was implemented by Mocean Laboratories AB when porting linux
 17  * to the automotive development board Russellville. The copyright holder
 18  * as seen in the header is Intel corporation.
 19  * Mocean Laboratories forked off the GNU/Linux platform work into a
 20  * separate company called Pelagicore AB, which committed the code to the
 21  * kernel.
 22  */
 23 
 24 /* Supports:
 25  * Xilinx IIC
 26  */
 27 #include <linux/kernel.h>
 28 #include <linux/module.h>
 29 #include <linux/errno.h>
 30 #include <linux/err.h>
 31 #include <linux/delay.h>
 32 #include <linux/platform_device.h>
 33 #include <linux/i2c.h>
 34 #include <linux/interrupt.h>
 35 #include <linux/wait.h>
 36 #include <linux/i2c-xiic.h>
 37 #include <linux/io.h>
 38 #include <linux/slab.h>
 39 #include <linux/of.h>
 40 #include <linux/clk.h>
 41 #include <linux/pm_runtime.h>
 42 
 43 #define DRIVER_NAME "xiic-i2c"
 44 
 45 enum xilinx_i2c_state {
 46         STATE_DONE,
 47         STATE_ERROR,
 48         STATE_START
 49 };
 50 
 51 enum xiic_endian {
 52         LITTLE,
 53         BIG
 54 };
 55 
 56 /**
 57  * struct xiic_i2c - Internal representation of the XIIC I2C bus
 58  * @base:       Memory base of the HW registers
 59  * @wait:       Wait queue for callers
 60  * @adap:       Kernel adapter representation
 61  * @tx_msg:     Messages from above to be sent
 62  * @lock:       Mutual exclusion
 63  * @tx_pos:     Current pos in TX message
 64  * @nmsgs:      Number of messages in tx_msg
 65  * @state:      See STATE_
 66  * @rx_msg:     Current RX message
 67  * @rx_pos:     Position within current RX message
 68  * @endianness: big/little-endian byte order
 69  */
 70 struct xiic_i2c {
 71         struct device           *dev;
 72         void __iomem            *base;
 73         wait_queue_head_t       wait;
 74         struct i2c_adapter      adap;
 75         struct i2c_msg          *tx_msg;
 76         struct mutex            lock;
 77         unsigned int            tx_pos;
 78         unsigned int            nmsgs;
 79         enum xilinx_i2c_state   state;
 80         struct i2c_msg          *rx_msg;
 81         int                     rx_pos;
 82         enum xiic_endian        endianness;
 83         struct clk *clk;
 84 };
 85 
 86 
 87 #define XIIC_MSB_OFFSET 0
 88 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
 89 
 90 /*
 91  * Register offsets in bytes from RegisterBase. Three is added to the
 92  * base offset to access LSB (IBM style) of the word
 93  */
 94 #define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET)     /* Control Register   */
 95 #define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET)     /* Status Register    */
 96 #define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)     /* Data Tx Register   */
 97 #define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)     /* Data Rx Register   */
 98 #define XIIC_ADR_REG_OFFSET  (0x10+XIIC_REG_OFFSET)     /* Address Register   */
 99 #define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)     /* Tx FIFO Occupancy  */
100 #define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)     /* Rx FIFO Occupancy  */
101 #define XIIC_TBA_REG_OFFSET  (0x1C+XIIC_REG_OFFSET)     /* 10 Bit Address reg */
102 #define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)     /* Rx FIFO Depth reg  */
103 #define XIIC_GPO_REG_OFFSET  (0x24+XIIC_REG_OFFSET)     /* Output Register    */
104 
105 /* Control Register masks */
106 #define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
107 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
108 #define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
109 #define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
110 #define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
111 #define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
112 #define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
113 
114 /* Status Register masks */
115 #define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
116 #define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
117 #define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
118 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
119 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
120 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
121 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
122 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80  /* 1 = Tx FIFO empty      */
123 
124 /* Interrupt Status Register masks    Interrupt occurs when...       */
125 #define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
126 #define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete */
127 #define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
128 #define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level */
129 #define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
130 #define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
131 #define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
132 #define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
133 
134 /* The following constants specify the depth of the FIFOs */
135 #define IIC_RX_FIFO_DEPTH         16    /* Rx fifo capacity               */
136 #define IIC_TX_FIFO_DEPTH         16    /* Tx fifo capacity               */
137 
138 /* The following constants specify groups of interrupts that are typically
139  * enabled or disables at the same time
140  */
141 #define XIIC_TX_INTERRUPTS                           \
142 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
143 
144 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
145 
146 /* The following constants are used with the following macros to specify the
147  * operation, a read or write operation.
148  */
149 #define XIIC_READ_OPERATION  1
150 #define XIIC_WRITE_OPERATION 0
151 
152 /*
153  * Tx Fifo upper bit masks.
154  */
155 #define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
156 #define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */
157 
158 /*
159  * The following constants define the register offsets for the Interrupt
160  * registers. There are some holes in the memory map for reserved addresses
161  * to allow other registers to be added and still match the memory map of the
162  * interrupt controller registers
163  */
164 #define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
165 #define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
166 #define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
167 #define XIIC_RESETR_OFFSET   0x40 /* Reset Register */
168 
169 #define XIIC_RESET_MASK             0xAUL
170 
171 #define XIIC_PM_TIMEOUT         1000    /* ms */
172 /*
173  * The following constant is used for the device global interrupt enable
174  * register, to enable all interrupts for the device, this is the only bit
175  * in the register
176  */
177 #define XIIC_GINTR_ENABLE_MASK      0x80000000UL
178 
179 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
180 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
181 
182 static void xiic_start_xfer(struct xiic_i2c *i2c);
183 static void __xiic_start_xfer(struct xiic_i2c *i2c);
184 
185 /*
186  * For the register read and write functions, a little-endian and big-endian
187  * version are necessary. Endianness is detected during the probe function.
188  * Only the least significant byte [doublet] of the register are ever
189  * accessed. This requires an offset of 3 [2] from the base address for
190  * big-endian systems.
191  */
192 
193 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
194 {
195         if (i2c->endianness == LITTLE)
196                 iowrite8(value, i2c->base + reg);
197         else
198                 iowrite8(value, i2c->base + reg + 3);
199 }
200 
201 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
202 {
203         u8 ret;
204 
205         if (i2c->endianness == LITTLE)
206                 ret = ioread8(i2c->base + reg);
207         else
208                 ret = ioread8(i2c->base + reg + 3);
209         return ret;
210 }
211 
212 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
213 {
214         if (i2c->endianness == LITTLE)
215                 iowrite16(value, i2c->base + reg);
216         else
217                 iowrite16be(value, i2c->base + reg + 2);
218 }
219 
220 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
221 {
222         if (i2c->endianness == LITTLE)
223                 iowrite32(value, i2c->base + reg);
224         else
225                 iowrite32be(value, i2c->base + reg);
226 }
227 
228 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
229 {
230         u32 ret;
231 
232         if (i2c->endianness == LITTLE)
233                 ret = ioread32(i2c->base + reg);
234         else
235                 ret = ioread32be(i2c->base + reg);
236         return ret;
237 }
238 
239 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
240 {
241         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
242         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
243 }
244 
245 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
246 {
247         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
248         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
249 }
250 
251 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
252 {
253         u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
254         xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
255 }
256 
257 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
258 {
259         xiic_irq_clr(i2c, mask);
260         xiic_irq_en(i2c, mask);
261 }
262 
263 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
264 {
265         u8 sr;
266         for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
267                 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
268                 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
269                 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
270 }
271 
272 static void xiic_reinit(struct xiic_i2c *i2c)
273 {
274         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
275 
276         /* Set receive Fifo depth to maximum (zero based). */
277         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
278 
279         /* Reset Tx Fifo. */
280         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
281 
282         /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
283         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
284 
285         /* make sure RX fifo is empty */
286         xiic_clear_rx_fifo(i2c);
287 
288         /* Enable interrupts */
289         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
290 
291         xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
292 }
293 
294 static void xiic_deinit(struct xiic_i2c *i2c)
295 {
296         u8 cr;
297 
298         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
299 
300         /* Disable IIC Device. */
301         cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
302         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
303 }
304 
305 static void xiic_read_rx(struct xiic_i2c *i2c)
306 {
307         u8 bytes_in_fifo;
308         int i;
309 
310         bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
311 
312         dev_dbg(i2c->adap.dev.parent,
313                 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
314                 __func__, bytes_in_fifo, xiic_rx_space(i2c),
315                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
316                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
317 
318         if (bytes_in_fifo > xiic_rx_space(i2c))
319                 bytes_in_fifo = xiic_rx_space(i2c);
320 
321         for (i = 0; i < bytes_in_fifo; i++)
322                 i2c->rx_msg->buf[i2c->rx_pos++] =
323                         xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
324 
325         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
326                 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
327                 IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);
328 }
329 
330 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
331 {
332         /* return the actual space left in the FIFO */
333         return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
334 }
335 
336 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
337 {
338         u8 fifo_space = xiic_tx_fifo_space(i2c);
339         int len = xiic_tx_space(i2c);
340 
341         len = (len > fifo_space) ? fifo_space : len;
342 
343         dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
344                 __func__, len, fifo_space);
345 
346         while (len--) {
347                 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
348                 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
349                         /* last message in transfer -> STOP */
350                         data |= XIIC_TX_DYN_STOP_MASK;
351                         dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
352                 }
353                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
354         }
355 }
356 
357 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
358 {
359         i2c->tx_msg = NULL;
360         i2c->rx_msg = NULL;
361         i2c->nmsgs = 0;
362         i2c->state = code;
363         wake_up(&i2c->wait);
364 }
365 
366 static irqreturn_t xiic_process(int irq, void *dev_id)
367 {
368         struct xiic_i2c *i2c = dev_id;
369         u32 pend, isr, ier;
370         u32 clr = 0;
371 
372         /* Get the interrupt Status from the IPIF. There is no clearing of
373          * interrupts in the IPIF. Interrupts must be cleared at the source.
374          * To find which interrupts are pending; AND interrupts pending with
375          * interrupts masked.
376          */
377         mutex_lock(&i2c->lock);
378         isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
379         ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
380         pend = isr & ier;
381 
382         dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
383                 __func__, ier, isr, pend);
384         dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
385                 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
386                 i2c->tx_msg, i2c->nmsgs);
387 
388 
389         /* Service requesting interrupt */
390         if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
391                 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
392                 !(pend & XIIC_INTR_RX_FULL_MASK))) {
393                 /* bus arbritration lost, or...
394                  * Transmit error _OR_ RX completed
395                  * if this happens when RX_FULL is not set
396                  * this is probably a TX error
397                  */
398 
399                 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
400 
401                 /* dynamic mode seem to suffer from problems if we just flushes
402                  * fifos and the next message is a TX with len 0 (only addr)
403                  * reset the IP instead of just flush fifos
404                  */
405                 xiic_reinit(i2c);
406 
407                 if (i2c->rx_msg)
408                         xiic_wakeup(i2c, STATE_ERROR);
409                 if (i2c->tx_msg)
410                         xiic_wakeup(i2c, STATE_ERROR);
411         }
412         if (pend & XIIC_INTR_RX_FULL_MASK) {
413                 /* Receive register/FIFO is full */
414 
415                 clr |= XIIC_INTR_RX_FULL_MASK;
416                 if (!i2c->rx_msg) {
417                         dev_dbg(i2c->adap.dev.parent,
418                                 "%s unexpexted RX IRQ\n", __func__);
419                         xiic_clear_rx_fifo(i2c);
420                         goto out;
421                 }
422 
423                 xiic_read_rx(i2c);
424                 if (xiic_rx_space(i2c) == 0) {
425                         /* this is the last part of the message */
426                         i2c->rx_msg = NULL;
427 
428                         /* also clear TX error if there (RX complete) */
429                         clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
430 
431                         dev_dbg(i2c->adap.dev.parent,
432                                 "%s end of message, nmsgs: %d\n",
433                                 __func__, i2c->nmsgs);
434 
435                         /* send next message if this wasn't the last,
436                          * otherwise the transfer will be finialise when
437                          * receiving the bus not busy interrupt
438                          */
439                         if (i2c->nmsgs > 1) {
440                                 i2c->nmsgs--;
441                                 i2c->tx_msg++;
442                                 dev_dbg(i2c->adap.dev.parent,
443                                         "%s will start next...\n", __func__);
444 
445                                 __xiic_start_xfer(i2c);
446                         }
447                 }
448         }
449         if (pend & XIIC_INTR_BNB_MASK) {
450                 /* IIC bus has transitioned to not busy */
451                 clr |= XIIC_INTR_BNB_MASK;
452 
453                 /* The bus is not busy, disable BusNotBusy interrupt */
454                 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
455 
456                 if (!i2c->tx_msg)
457                         goto out;
458 
459                 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
460                         xiic_tx_space(i2c) == 0)
461                         xiic_wakeup(i2c, STATE_DONE);
462                 else
463                         xiic_wakeup(i2c, STATE_ERROR);
464         }
465         if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
466                 /* Transmit register/FIFO is empty or ½ empty */
467 
468                 clr |= (pend &
469                         (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
470 
471                 if (!i2c->tx_msg) {
472                         dev_dbg(i2c->adap.dev.parent,
473                                 "%s unexpexted TX IRQ\n", __func__);
474                         goto out;
475                 }
476 
477                 xiic_fill_tx_fifo(i2c);
478 
479                 /* current message sent and there is space in the fifo */
480                 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
481                         dev_dbg(i2c->adap.dev.parent,
482                                 "%s end of message sent, nmsgs: %d\n",
483                                 __func__, i2c->nmsgs);
484                         if (i2c->nmsgs > 1) {
485                                 i2c->nmsgs--;
486                                 i2c->tx_msg++;
487                                 __xiic_start_xfer(i2c);
488                         } else {
489                                 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
490 
491                                 dev_dbg(i2c->adap.dev.parent,
492                                         "%s Got TX IRQ but no more to do...\n",
493                                         __func__);
494                         }
495                 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
496                         /* current frame is sent and is last,
497                          * make sure to disable tx half
498                          */
499                         xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
500         }
501 out:
502         dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
503 
504         xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
505         mutex_unlock(&i2c->lock);
506         return IRQ_HANDLED;
507 }
508 
509 static int xiic_bus_busy(struct xiic_i2c *i2c)
510 {
511         u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
512 
513         return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
514 }
515 
516 static int xiic_busy(struct xiic_i2c *i2c)
517 {
518         int tries = 3;
519         int err;
520 
521         if (i2c->tx_msg)
522                 return -EBUSY;
523 
524         /* for instance if previous transfer was terminated due to TX error
525          * it might be that the bus is on it's way to become available
526          * give it at most 3 ms to wake
527          */
528         err = xiic_bus_busy(i2c);
529         while (err && tries--) {
530                 msleep(1);
531                 err = xiic_bus_busy(i2c);
532         }
533 
534         return err;
535 }
536 
537 static void xiic_start_recv(struct xiic_i2c *i2c)
538 {
539         u8 rx_watermark;
540         struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
541 
542         /* Clear and enable Rx full interrupt. */
543         xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
544 
545         /* we want to get all but last byte, because the TX_ERROR IRQ is used
546          * to inidicate error ACK on the address, and negative ack on the last
547          * received byte, so to not mix them receive all but last.
548          * In the case where there is only one byte to receive
549          * we can check if ERROR and RX full is set at the same time
550          */
551         rx_watermark = msg->len;
552         if (rx_watermark > IIC_RX_FIFO_DEPTH)
553                 rx_watermark = IIC_RX_FIFO_DEPTH;
554         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
555 
556         if (!(msg->flags & I2C_M_NOSTART))
557                 /* write the address */
558                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
559                         (msg->addr << 1) | XIIC_READ_OPERATION |
560                         XIIC_TX_DYN_START_MASK);
561 
562         xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
563 
564         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
565                 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
566         if (i2c->nmsgs == 1)
567                 /* very last, enable bus not busy as well */
568                 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
569 
570         /* the message is tx:ed */
571         i2c->tx_pos = msg->len;
572 }
573 
574 static void xiic_start_send(struct xiic_i2c *i2c)
575 {
576         struct i2c_msg *msg = i2c->tx_msg;
577 
578         xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
579 
580         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
581                 __func__, msg, msg->len);
582         dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
583                 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
584                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
585 
586         if (!(msg->flags & I2C_M_NOSTART)) {
587                 /* write the address */
588                 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
589                         XIIC_TX_DYN_START_MASK;
590                 if ((i2c->nmsgs == 1) && msg->len == 0)
591                         /* no data and last message -> add STOP */
592                         data |= XIIC_TX_DYN_STOP_MASK;
593 
594                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
595         }
596 
597         xiic_fill_tx_fifo(i2c);
598 
599         /* Clear any pending Tx empty, Tx Error and then enable them. */
600         xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
601                 XIIC_INTR_BNB_MASK);
602 }
603 
604 static irqreturn_t xiic_isr(int irq, void *dev_id)
605 {
606         struct xiic_i2c *i2c = dev_id;
607         u32 pend, isr, ier;
608         irqreturn_t ret = IRQ_NONE;
609         /* Do not processes a devices interrupts if the device has no
610          * interrupts pending
611          */
612 
613         dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
614 
615         isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
616         ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
617         pend = isr & ier;
618         if (pend)
619                 ret = IRQ_WAKE_THREAD;
620 
621         return ret;
622 }
623 
624 static void __xiic_start_xfer(struct xiic_i2c *i2c)
625 {
626         int first = 1;
627         int fifo_space = xiic_tx_fifo_space(i2c);
628         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
629                 __func__, i2c->tx_msg, fifo_space);
630 
631         if (!i2c->tx_msg)
632                 return;
633 
634         i2c->rx_pos = 0;
635         i2c->tx_pos = 0;
636         i2c->state = STATE_START;
637         while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
638                 if (!first) {
639                         i2c->nmsgs--;
640                         i2c->tx_msg++;
641                         i2c->tx_pos = 0;
642                 } else
643                         first = 0;
644 
645                 if (i2c->tx_msg->flags & I2C_M_RD) {
646                         /* we dont date putting several reads in the FIFO */
647                         xiic_start_recv(i2c);
648                         return;
649                 } else {
650                         xiic_start_send(i2c);
651                         if (xiic_tx_space(i2c) != 0) {
652                                 /* the message could not be completely sent */
653                                 break;
654                         }
655                 }
656 
657                 fifo_space = xiic_tx_fifo_space(i2c);
658         }
659 
660         /* there are more messages or the current one could not be completely
661          * put into the FIFO, also enable the half empty interrupt
662          */
663         if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
664                 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
665 
666 }
667 
668 static void xiic_start_xfer(struct xiic_i2c *i2c)
669 {
670         mutex_lock(&i2c->lock);
671         xiic_reinit(i2c);
672         __xiic_start_xfer(i2c);
673         mutex_unlock(&i2c->lock);
674 }
675 
676 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
677 {
678         struct xiic_i2c *i2c = i2c_get_adapdata(adap);
679         int err;
680 
681         dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
682                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
683 
684         err = pm_runtime_get_sync(i2c->dev);
685         if (err < 0)
686                 return err;
687 
688         err = xiic_busy(i2c);
689         if (err)
690                 goto out;
691 
692         i2c->tx_msg = msgs;
693         i2c->nmsgs = num;
694 
695         xiic_start_xfer(i2c);
696 
697         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
698                 (i2c->state == STATE_DONE), HZ)) {
699                 err = (i2c->state == STATE_DONE) ? num : -EIO;
700                 goto out;
701         } else {
702                 i2c->tx_msg = NULL;
703                 i2c->rx_msg = NULL;
704                 i2c->nmsgs = 0;
705                 err = -ETIMEDOUT;
706                 goto out;
707         }
708 out:
709         pm_runtime_mark_last_busy(i2c->dev);
710         pm_runtime_put_autosuspend(i2c->dev);
711         return err;
712 }
713 
714 static u32 xiic_func(struct i2c_adapter *adap)
715 {
716         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
717 }
718 
719 static const struct i2c_algorithm xiic_algorithm = {
720         .master_xfer = xiic_xfer,
721         .functionality = xiic_func,
722 };
723 
724 static struct i2c_adapter xiic_adapter = {
725         .owner = THIS_MODULE,
726         .name = DRIVER_NAME,
727         .class = I2C_CLASS_DEPRECATED,
728         .algo = &xiic_algorithm,
729 };
730 
731 
732 static int xiic_i2c_probe(struct platform_device *pdev)
733 {
734         struct xiic_i2c *i2c;
735         struct xiic_i2c_platform_data *pdata;
736         struct resource *res;
737         int ret, irq;
738         u8 i;
739         u32 sr;
740 
741         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
742         if (!i2c)
743                 return -ENOMEM;
744 
745         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
746         i2c->base = devm_ioremap_resource(&pdev->dev, res);
747         if (IS_ERR(i2c->base))
748                 return PTR_ERR(i2c->base);
749 
750         irq = platform_get_irq(pdev, 0);
751         if (irq < 0)
752                 return irq;
753 
754         pdata = dev_get_platdata(&pdev->dev);
755 
756         /* hook up driver to tree */
757         platform_set_drvdata(pdev, i2c);
758         i2c->adap = xiic_adapter;
759         i2c_set_adapdata(&i2c->adap, i2c);
760         i2c->adap.dev.parent = &pdev->dev;
761         i2c->adap.dev.of_node = pdev->dev.of_node;
762 
763         mutex_init(&i2c->lock);
764         init_waitqueue_head(&i2c->wait);
765 
766         i2c->clk = devm_clk_get(&pdev->dev, NULL);
767         if (IS_ERR(i2c->clk)) {
768                 dev_err(&pdev->dev, "input clock not found.\n");
769                 return PTR_ERR(i2c->clk);
770         }
771         ret = clk_prepare_enable(i2c->clk);
772         if (ret) {
773                 dev_err(&pdev->dev, "Unable to enable clock.\n");
774                 return ret;
775         }
776         i2c->dev = &pdev->dev;
777         pm_runtime_enable(i2c->dev);
778         pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
779         pm_runtime_use_autosuspend(i2c->dev);
780         pm_runtime_set_active(i2c->dev);
781         ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
782                                         xiic_process, IRQF_ONESHOT,
783                                         pdev->name, i2c);
784 
785         if (ret < 0) {
786                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
787                 goto err_clk_dis;
788         }
789 
790         /*
791          * Detect endianness
792          * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
793          * set, assume that the endianness was wrong and swap.
794          */
795         i2c->endianness = LITTLE;
796         xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
797         /* Reset is cleared in xiic_reinit */
798         sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
799         if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
800                 i2c->endianness = BIG;
801 
802         xiic_reinit(i2c);
803 
804         /* add i2c adapter to i2c tree */
805         ret = i2c_add_adapter(&i2c->adap);
806         if (ret) {
807                 dev_err(&pdev->dev, "Failed to add adapter\n");
808                 xiic_deinit(i2c);
809                 goto err_clk_dis;
810         }
811 
812         if (pdata) {
813                 /* add in known devices to the bus */
814                 for (i = 0; i < pdata->num_devices; i++)
815                         i2c_new_device(&i2c->adap, pdata->devices + i);
816         }
817 
818         return 0;
819 
820 err_clk_dis:
821         pm_runtime_set_suspended(&pdev->dev);
822         pm_runtime_disable(&pdev->dev);
823         clk_disable_unprepare(i2c->clk);
824         return ret;
825 }
826 
827 static int xiic_i2c_remove(struct platform_device *pdev)
828 {
829         struct xiic_i2c *i2c = platform_get_drvdata(pdev);
830         int ret;
831 
832         /* remove adapter & data */
833         i2c_del_adapter(&i2c->adap);
834 
835         ret = clk_prepare_enable(i2c->clk);
836         if (ret) {
837                 dev_err(&pdev->dev, "Unable to enable clock.\n");
838                 return ret;
839         }
840         xiic_deinit(i2c);
841         clk_disable_unprepare(i2c->clk);
842         pm_runtime_disable(&pdev->dev);
843 
844         return 0;
845 }
846 
847 #if defined(CONFIG_OF)
848 static const struct of_device_id xiic_of_match[] = {
849         { .compatible = "xlnx,xps-iic-2.00.a", },
850         {},
851 };
852 MODULE_DEVICE_TABLE(of, xiic_of_match);
853 #endif
854 
855 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
856 {
857         struct platform_device *pdev = to_platform_device(dev);
858         struct xiic_i2c *i2c = platform_get_drvdata(pdev);
859 
860         clk_disable(i2c->clk);
861 
862         return 0;
863 }
864 
865 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
866 {
867         struct platform_device *pdev = to_platform_device(dev);
868         struct xiic_i2c *i2c = platform_get_drvdata(pdev);
869         int ret;
870 
871         ret = clk_enable(i2c->clk);
872         if (ret) {
873                 dev_err(dev, "Cannot enable clock.\n");
874                 return ret;
875         }
876 
877         return 0;
878 }
879 
880 static const struct dev_pm_ops xiic_dev_pm_ops = {
881         SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
882                            cdns_i2c_runtime_resume, NULL)
883 };
884 static struct platform_driver xiic_i2c_driver = {
885         .probe   = xiic_i2c_probe,
886         .remove  = xiic_i2c_remove,
887         .driver  = {
888                 .name = DRIVER_NAME,
889                 .of_match_table = of_match_ptr(xiic_of_match),
890                 .pm = &xiic_dev_pm_ops,
891         },
892 };
893 
894 module_platform_driver(xiic_i2c_driver);
895 
896 MODULE_AUTHOR("info@mocean-labs.com");
897 MODULE_DESCRIPTION("Xilinx I2C bus driver");
898 MODULE_LICENSE("GPL v2");
899 MODULE_ALIAS("platform:"DRIVER_NAME);
900 

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