Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/i2c/busses/i2c-xiic.c

  1 /*
  2  * i2c-xiic.c
  3  * Copyright (c) 2002-2007 Xilinx Inc.
  4  * Copyright (c) 2009-2010 Intel Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  *
 16  * This code was implemented by Mocean Laboratories AB when porting linux
 17  * to the automotive development board Russellville. The copyright holder
 18  * as seen in the header is Intel corporation.
 19  * Mocean Laboratories forked off the GNU/Linux platform work into a
 20  * separate company called Pelagicore AB, which committed the code to the
 21  * kernel.
 22  */
 23 
 24 /* Supports:
 25  * Xilinx IIC
 26  */
 27 #include <linux/kernel.h>
 28 #include <linux/module.h>
 29 #include <linux/errno.h>
 30 #include <linux/err.h>
 31 #include <linux/delay.h>
 32 #include <linux/platform_device.h>
 33 #include <linux/i2c.h>
 34 #include <linux/interrupt.h>
 35 #include <linux/wait.h>
 36 #include <linux/i2c-xiic.h>
 37 #include <linux/io.h>
 38 #include <linux/slab.h>
 39 #include <linux/of.h>
 40 
 41 #define DRIVER_NAME "xiic-i2c"
 42 
 43 enum xilinx_i2c_state {
 44         STATE_DONE,
 45         STATE_ERROR,
 46         STATE_START
 47 };
 48 
 49 /**
 50  * struct xiic_i2c - Internal representation of the XIIC I2C bus
 51  * @base:       Memory base of the HW registers
 52  * @wait:       Wait queue for callers
 53  * @adap:       Kernel adapter representation
 54  * @tx_msg:     Messages from above to be sent
 55  * @lock:       Mutual exclusion
 56  * @tx_pos:     Current pos in TX message
 57  * @nmsgs:      Number of messages in tx_msg
 58  * @state:      See STATE_
 59  * @rx_msg:     Current RX message
 60  * @rx_pos:     Position within current RX message
 61  */
 62 struct xiic_i2c {
 63         void __iomem            *base;
 64         wait_queue_head_t       wait;
 65         struct i2c_adapter      adap;
 66         struct i2c_msg          *tx_msg;
 67         spinlock_t              lock;
 68         unsigned int            tx_pos;
 69         unsigned int            nmsgs;
 70         enum xilinx_i2c_state   state;
 71         struct i2c_msg          *rx_msg;
 72         int                     rx_pos;
 73 };
 74 
 75 
 76 #define XIIC_MSB_OFFSET 0
 77 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
 78 
 79 /*
 80  * Register offsets in bytes from RegisterBase. Three is added to the
 81  * base offset to access LSB (IBM style) of the word
 82  */
 83 #define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET)     /* Control Register   */
 84 #define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET)     /* Status Register    */
 85 #define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)     /* Data Tx Register   */
 86 #define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)     /* Data Rx Register   */
 87 #define XIIC_ADR_REG_OFFSET  (0x10+XIIC_REG_OFFSET)     /* Address Register   */
 88 #define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)     /* Tx FIFO Occupancy  */
 89 #define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)     /* Rx FIFO Occupancy  */
 90 #define XIIC_TBA_REG_OFFSET  (0x1C+XIIC_REG_OFFSET)     /* 10 Bit Address reg */
 91 #define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)     /* Rx FIFO Depth reg  */
 92 #define XIIC_GPO_REG_OFFSET  (0x24+XIIC_REG_OFFSET)     /* Output Register    */
 93 
 94 /* Control Register masks */
 95 #define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
 96 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
 97 #define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
 98 #define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
 99 #define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
100 #define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
101 #define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
102 
103 /* Status Register masks */
104 #define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
105 #define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
106 #define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
107 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
108 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
109 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
110 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
111 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80  /* 1 = Tx FIFO empty      */
112 
113 /* Interrupt Status Register masks    Interrupt occurs when...       */
114 #define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
115 #define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete */
116 #define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
117 #define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level */
118 #define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
119 #define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
120 #define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
121 #define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
122 
123 /* The following constants specify the depth of the FIFOs */
124 #define IIC_RX_FIFO_DEPTH         16    /* Rx fifo capacity               */
125 #define IIC_TX_FIFO_DEPTH         16    /* Tx fifo capacity               */
126 
127 /* The following constants specify groups of interrupts that are typically
128  * enabled or disables at the same time
129  */
130 #define XIIC_TX_INTERRUPTS                           \
131 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
132 
133 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
134 
135 /* The following constants are used with the following macros to specify the
136  * operation, a read or write operation.
137  */
138 #define XIIC_READ_OPERATION  1
139 #define XIIC_WRITE_OPERATION 0
140 
141 /*
142  * Tx Fifo upper bit masks.
143  */
144 #define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
145 #define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */
146 
147 /*
148  * The following constants define the register offsets for the Interrupt
149  * registers. There are some holes in the memory map for reserved addresses
150  * to allow other registers to be added and still match the memory map of the
151  * interrupt controller registers
152  */
153 #define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
154 #define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
155 #define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
156 #define XIIC_RESETR_OFFSET   0x40 /* Reset Register */
157 
158 #define XIIC_RESET_MASK             0xAUL
159 
160 /*
161  * The following constant is used for the device global interrupt enable
162  * register, to enable all interrupts for the device, this is the only bit
163  * in the register
164  */
165 #define XIIC_GINTR_ENABLE_MASK      0x80000000UL
166 
167 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
168 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
169 
170 static void xiic_start_xfer(struct xiic_i2c *i2c);
171 static void __xiic_start_xfer(struct xiic_i2c *i2c);
172 
173 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
174 {
175         iowrite8(value, i2c->base + reg);
176 }
177 
178 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
179 {
180         return ioread8(i2c->base + reg);
181 }
182 
183 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
184 {
185         iowrite16(value, i2c->base + reg);
186 }
187 
188 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
189 {
190         iowrite32(value, i2c->base + reg);
191 }
192 
193 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
194 {
195         return ioread32(i2c->base + reg);
196 }
197 
198 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
199 {
200         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
201         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
202 }
203 
204 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
205 {
206         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
207         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
208 }
209 
210 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
211 {
212         u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
213         xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
214 }
215 
216 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
217 {
218         xiic_irq_clr(i2c, mask);
219         xiic_irq_en(i2c, mask);
220 }
221 
222 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
223 {
224         u8 sr;
225         for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
226                 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
227                 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
228                 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
229 }
230 
231 static void xiic_reinit(struct xiic_i2c *i2c)
232 {
233         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
234 
235         /* Set receive Fifo depth to maximum (zero based). */
236         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
237 
238         /* Reset Tx Fifo. */
239         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
240 
241         /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
242         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
243 
244         /* make sure RX fifo is empty */
245         xiic_clear_rx_fifo(i2c);
246 
247         /* Enable interrupts */
248         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
249 
250         xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
251 }
252 
253 static void xiic_deinit(struct xiic_i2c *i2c)
254 {
255         u8 cr;
256 
257         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
258 
259         /* Disable IIC Device. */
260         cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
261         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
262 }
263 
264 static void xiic_read_rx(struct xiic_i2c *i2c)
265 {
266         u8 bytes_in_fifo;
267         int i;
268 
269         bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
270 
271         dev_dbg(i2c->adap.dev.parent,
272                 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
273                 __func__, bytes_in_fifo, xiic_rx_space(i2c),
274                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
275                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
276 
277         if (bytes_in_fifo > xiic_rx_space(i2c))
278                 bytes_in_fifo = xiic_rx_space(i2c);
279 
280         for (i = 0; i < bytes_in_fifo; i++)
281                 i2c->rx_msg->buf[i2c->rx_pos++] =
282                         xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
283 
284         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
285                 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
286                 IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);
287 }
288 
289 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
290 {
291         /* return the actual space left in the FIFO */
292         return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
293 }
294 
295 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
296 {
297         u8 fifo_space = xiic_tx_fifo_space(i2c);
298         int len = xiic_tx_space(i2c);
299 
300         len = (len > fifo_space) ? fifo_space : len;
301 
302         dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
303                 __func__, len, fifo_space);
304 
305         while (len--) {
306                 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
307                 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
308                         /* last message in transfer -> STOP */
309                         data |= XIIC_TX_DYN_STOP_MASK;
310                         dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
311                 }
312                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
313         }
314 }
315 
316 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
317 {
318         i2c->tx_msg = NULL;
319         i2c->rx_msg = NULL;
320         i2c->nmsgs = 0;
321         i2c->state = code;
322         wake_up(&i2c->wait);
323 }
324 
325 static void xiic_process(struct xiic_i2c *i2c)
326 {
327         u32 pend, isr, ier;
328         u32 clr = 0;
329 
330         /* Get the interrupt Status from the IPIF. There is no clearing of
331          * interrupts in the IPIF. Interrupts must be cleared at the source.
332          * To find which interrupts are pending; AND interrupts pending with
333          * interrupts masked.
334          */
335         isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
336         ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
337         pend = isr & ier;
338 
339         dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
340                 __func__, ier, isr, pend);
341         dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
342                 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
343                 i2c->tx_msg, i2c->nmsgs);
344 
345         /* Do not processes a devices interrupts if the device has no
346          * interrupts pending
347          */
348         if (!pend)
349                 return;
350 
351         /* Service requesting interrupt */
352         if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
353                 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
354                 !(pend & XIIC_INTR_RX_FULL_MASK))) {
355                 /* bus arbritration lost, or...
356                  * Transmit error _OR_ RX completed
357                  * if this happens when RX_FULL is not set
358                  * this is probably a TX error
359                  */
360 
361                 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
362 
363                 /* dynamic mode seem to suffer from problems if we just flushes
364                  * fifos and the next message is a TX with len 0 (only addr)
365                  * reset the IP instead of just flush fifos
366                  */
367                 xiic_reinit(i2c);
368 
369                 if (i2c->tx_msg)
370                         xiic_wakeup(i2c, STATE_ERROR);
371 
372         } else if (pend & XIIC_INTR_RX_FULL_MASK) {
373                 /* Receive register/FIFO is full */
374 
375                 clr = XIIC_INTR_RX_FULL_MASK;
376                 if (!i2c->rx_msg) {
377                         dev_dbg(i2c->adap.dev.parent,
378                                 "%s unexpexted RX IRQ\n", __func__);
379                         xiic_clear_rx_fifo(i2c);
380                         goto out;
381                 }
382 
383                 xiic_read_rx(i2c);
384                 if (xiic_rx_space(i2c) == 0) {
385                         /* this is the last part of the message */
386                         i2c->rx_msg = NULL;
387 
388                         /* also clear TX error if there (RX complete) */
389                         clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
390 
391                         dev_dbg(i2c->adap.dev.parent,
392                                 "%s end of message, nmsgs: %d\n",
393                                 __func__, i2c->nmsgs);
394 
395                         /* send next message if this wasn't the last,
396                          * otherwise the transfer will be finialise when
397                          * receiving the bus not busy interrupt
398                          */
399                         if (i2c->nmsgs > 1) {
400                                 i2c->nmsgs--;
401                                 i2c->tx_msg++;
402                                 dev_dbg(i2c->adap.dev.parent,
403                                         "%s will start next...\n", __func__);
404 
405                                 __xiic_start_xfer(i2c);
406                         }
407                 }
408         } else if (pend & XIIC_INTR_BNB_MASK) {
409                 /* IIC bus has transitioned to not busy */
410                 clr = XIIC_INTR_BNB_MASK;
411 
412                 /* The bus is not busy, disable BusNotBusy interrupt */
413                 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
414 
415                 if (!i2c->tx_msg)
416                         goto out;
417 
418                 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
419                         xiic_tx_space(i2c) == 0)
420                         xiic_wakeup(i2c, STATE_DONE);
421                 else
422                         xiic_wakeup(i2c, STATE_ERROR);
423 
424         } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
425                 /* Transmit register/FIFO is empty or ½ empty */
426 
427                 clr = pend &
428                         (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
429 
430                 if (!i2c->tx_msg) {
431                         dev_dbg(i2c->adap.dev.parent,
432                                 "%s unexpexted TX IRQ\n", __func__);
433                         goto out;
434                 }
435 
436                 xiic_fill_tx_fifo(i2c);
437 
438                 /* current message sent and there is space in the fifo */
439                 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
440                         dev_dbg(i2c->adap.dev.parent,
441                                 "%s end of message sent, nmsgs: %d\n",
442                                 __func__, i2c->nmsgs);
443                         if (i2c->nmsgs > 1) {
444                                 i2c->nmsgs--;
445                                 i2c->tx_msg++;
446                                 __xiic_start_xfer(i2c);
447                         } else {
448                                 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
449 
450                                 dev_dbg(i2c->adap.dev.parent,
451                                         "%s Got TX IRQ but no more to do...\n",
452                                         __func__);
453                         }
454                 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
455                         /* current frame is sent and is last,
456                          * make sure to disable tx half
457                          */
458                         xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
459         } else {
460                 /* got IRQ which is not acked */
461                 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
462                         __func__);
463                 clr = pend;
464         }
465 out:
466         dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
467 
468         xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
469 }
470 
471 static int xiic_bus_busy(struct xiic_i2c *i2c)
472 {
473         u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
474 
475         return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
476 }
477 
478 static int xiic_busy(struct xiic_i2c *i2c)
479 {
480         int tries = 3;
481         int err;
482 
483         if (i2c->tx_msg)
484                 return -EBUSY;
485 
486         /* for instance if previous transfer was terminated due to TX error
487          * it might be that the bus is on it's way to become available
488          * give it at most 3 ms to wake
489          */
490         err = xiic_bus_busy(i2c);
491         while (err && tries--) {
492                 mdelay(1);
493                 err = xiic_bus_busy(i2c);
494         }
495 
496         return err;
497 }
498 
499 static void xiic_start_recv(struct xiic_i2c *i2c)
500 {
501         u8 rx_watermark;
502         struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
503 
504         /* Clear and enable Rx full interrupt. */
505         xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
506 
507         /* we want to get all but last byte, because the TX_ERROR IRQ is used
508          * to inidicate error ACK on the address, and negative ack on the last
509          * received byte, so to not mix them receive all but last.
510          * In the case where there is only one byte to receive
511          * we can check if ERROR and RX full is set at the same time
512          */
513         rx_watermark = msg->len;
514         if (rx_watermark > IIC_RX_FIFO_DEPTH)
515                 rx_watermark = IIC_RX_FIFO_DEPTH;
516         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
517 
518         if (!(msg->flags & I2C_M_NOSTART))
519                 /* write the address */
520                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
521                         (msg->addr << 1) | XIIC_READ_OPERATION |
522                         XIIC_TX_DYN_START_MASK);
523 
524         xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
525 
526         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
527                 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
528         if (i2c->nmsgs == 1)
529                 /* very last, enable bus not busy as well */
530                 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
531 
532         /* the message is tx:ed */
533         i2c->tx_pos = msg->len;
534 }
535 
536 static void xiic_start_send(struct xiic_i2c *i2c)
537 {
538         struct i2c_msg *msg = i2c->tx_msg;
539 
540         xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
541 
542         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
543                 __func__, msg, msg->len);
544         dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
545                 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
546                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
547 
548         if (!(msg->flags & I2C_M_NOSTART)) {
549                 /* write the address */
550                 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
551                         XIIC_TX_DYN_START_MASK;
552                 if ((i2c->nmsgs == 1) && msg->len == 0)
553                         /* no data and last message -> add STOP */
554                         data |= XIIC_TX_DYN_STOP_MASK;
555 
556                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
557         }
558 
559         xiic_fill_tx_fifo(i2c);
560 
561         /* Clear any pending Tx empty, Tx Error and then enable them. */
562         xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
563                 XIIC_INTR_BNB_MASK);
564 }
565 
566 static irqreturn_t xiic_isr(int irq, void *dev_id)
567 {
568         struct xiic_i2c *i2c = dev_id;
569 
570         spin_lock(&i2c->lock);
571         /* disable interrupts globally */
572         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
573 
574         dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
575 
576         xiic_process(i2c);
577 
578         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
579         spin_unlock(&i2c->lock);
580 
581         return IRQ_HANDLED;
582 }
583 
584 static void __xiic_start_xfer(struct xiic_i2c *i2c)
585 {
586         int first = 1;
587         int fifo_space = xiic_tx_fifo_space(i2c);
588         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
589                 __func__, i2c->tx_msg, fifo_space);
590 
591         if (!i2c->tx_msg)
592                 return;
593 
594         i2c->rx_pos = 0;
595         i2c->tx_pos = 0;
596         i2c->state = STATE_START;
597         while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
598                 if (!first) {
599                         i2c->nmsgs--;
600                         i2c->tx_msg++;
601                         i2c->tx_pos = 0;
602                 } else
603                         first = 0;
604 
605                 if (i2c->tx_msg->flags & I2C_M_RD) {
606                         /* we dont date putting several reads in the FIFO */
607                         xiic_start_recv(i2c);
608                         return;
609                 } else {
610                         xiic_start_send(i2c);
611                         if (xiic_tx_space(i2c) != 0) {
612                                 /* the message could not be completely sent */
613                                 break;
614                         }
615                 }
616 
617                 fifo_space = xiic_tx_fifo_space(i2c);
618         }
619 
620         /* there are more messages or the current one could not be completely
621          * put into the FIFO, also enable the half empty interrupt
622          */
623         if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
624                 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
625 
626 }
627 
628 static void xiic_start_xfer(struct xiic_i2c *i2c)
629 {
630         unsigned long flags;
631 
632         spin_lock_irqsave(&i2c->lock, flags);
633         xiic_reinit(i2c);
634         /* disable interrupts globally */
635         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
636         spin_unlock_irqrestore(&i2c->lock, flags);
637 
638         __xiic_start_xfer(i2c);
639         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
640 }
641 
642 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
643 {
644         struct xiic_i2c *i2c = i2c_get_adapdata(adap);
645         int err;
646 
647         dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
648                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
649 
650         err = xiic_busy(i2c);
651         if (err)
652                 return err;
653 
654         i2c->tx_msg = msgs;
655         i2c->nmsgs = num;
656 
657         xiic_start_xfer(i2c);
658 
659         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
660                 (i2c->state == STATE_DONE), HZ))
661                 return (i2c->state == STATE_DONE) ? num : -EIO;
662         else {
663                 i2c->tx_msg = NULL;
664                 i2c->rx_msg = NULL;
665                 i2c->nmsgs = 0;
666                 return -ETIMEDOUT;
667         }
668 }
669 
670 static u32 xiic_func(struct i2c_adapter *adap)
671 {
672         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
673 }
674 
675 static const struct i2c_algorithm xiic_algorithm = {
676         .master_xfer = xiic_xfer,
677         .functionality = xiic_func,
678 };
679 
680 static struct i2c_adapter xiic_adapter = {
681         .owner = THIS_MODULE,
682         .name = DRIVER_NAME,
683         .class = I2C_CLASS_DEPRECATED,
684         .algo = &xiic_algorithm,
685 };
686 
687 
688 static int xiic_i2c_probe(struct platform_device *pdev)
689 {
690         struct xiic_i2c *i2c;
691         struct xiic_i2c_platform_data *pdata;
692         struct resource *res;
693         int ret, irq;
694         u8 i;
695 
696         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
697         if (!i2c)
698                 return -ENOMEM;
699 
700         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701         i2c->base = devm_ioremap_resource(&pdev->dev, res);
702         if (IS_ERR(i2c->base))
703                 return PTR_ERR(i2c->base);
704 
705         irq = platform_get_irq(pdev, 0);
706         if (irq < 0)
707                 return irq;
708 
709         pdata = dev_get_platdata(&pdev->dev);
710 
711         /* hook up driver to tree */
712         platform_set_drvdata(pdev, i2c);
713         i2c->adap = xiic_adapter;
714         i2c_set_adapdata(&i2c->adap, i2c);
715         i2c->adap.dev.parent = &pdev->dev;
716         i2c->adap.dev.of_node = pdev->dev.of_node;
717 
718         spin_lock_init(&i2c->lock);
719         init_waitqueue_head(&i2c->wait);
720 
721         ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c);
722         if (ret < 0) {
723                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
724                 return ret;
725         }
726 
727         xiic_reinit(i2c);
728 
729         /* add i2c adapter to i2c tree */
730         ret = i2c_add_adapter(&i2c->adap);
731         if (ret) {
732                 dev_err(&pdev->dev, "Failed to add adapter\n");
733                 xiic_deinit(i2c);
734                 return ret;
735         }
736 
737         if (pdata) {
738                 /* add in known devices to the bus */
739                 for (i = 0; i < pdata->num_devices; i++)
740                         i2c_new_device(&i2c->adap, pdata->devices + i);
741         }
742 
743         return 0;
744 }
745 
746 static int xiic_i2c_remove(struct platform_device *pdev)
747 {
748         struct xiic_i2c *i2c = platform_get_drvdata(pdev);
749 
750         /* remove adapter & data */
751         i2c_del_adapter(&i2c->adap);
752 
753         xiic_deinit(i2c);
754 
755         return 0;
756 }
757 
758 #if defined(CONFIG_OF)
759 static const struct of_device_id xiic_of_match[] = {
760         { .compatible = "xlnx,xps-iic-2.00.a", },
761         {},
762 };
763 MODULE_DEVICE_TABLE(of, xiic_of_match);
764 #endif
765 
766 static struct platform_driver xiic_i2c_driver = {
767         .probe   = xiic_i2c_probe,
768         .remove  = xiic_i2c_remove,
769         .driver  = {
770                 .owner = THIS_MODULE,
771                 .name = DRIVER_NAME,
772                 .of_match_table = of_match_ptr(xiic_of_match),
773         },
774 };
775 
776 module_platform_driver(xiic_i2c_driver);
777 
778 MODULE_AUTHOR("info@mocean-labs.com");
779 MODULE_DESCRIPTION("Xilinx I2C bus driver");
780 MODULE_LICENSE("GPL v2");
781 MODULE_ALIAS("platform:"DRIVER_NAME);
782 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us