Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/i2c/busses/i2c-xiic.c

  1 /*
  2  * i2c-xiic.c
  3  * Copyright (c) 2002-2007 Xilinx Inc.
  4  * Copyright (c) 2009-2010 Intel Corporation
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  *
 15  *
 16  * This code was implemented by Mocean Laboratories AB when porting linux
 17  * to the automotive development board Russellville. The copyright holder
 18  * as seen in the header is Intel corporation.
 19  * Mocean Laboratories forked off the GNU/Linux platform work into a
 20  * separate company called Pelagicore AB, which committed the code to the
 21  * kernel.
 22  */
 23 
 24 /* Supports:
 25  * Xilinx IIC
 26  */
 27 #include <linux/kernel.h>
 28 #include <linux/module.h>
 29 #include <linux/errno.h>
 30 #include <linux/err.h>
 31 #include <linux/delay.h>
 32 #include <linux/platform_device.h>
 33 #include <linux/i2c.h>
 34 #include <linux/interrupt.h>
 35 #include <linux/wait.h>
 36 #include <linux/i2c-xiic.h>
 37 #include <linux/io.h>
 38 #include <linux/slab.h>
 39 #include <linux/of.h>
 40 
 41 #define DRIVER_NAME "xiic-i2c"
 42 
 43 enum xilinx_i2c_state {
 44         STATE_DONE,
 45         STATE_ERROR,
 46         STATE_START
 47 };
 48 
 49 enum xiic_endian {
 50         LITTLE,
 51         BIG
 52 };
 53 
 54 /**
 55  * struct xiic_i2c - Internal representation of the XIIC I2C bus
 56  * @base:       Memory base of the HW registers
 57  * @wait:       Wait queue for callers
 58  * @adap:       Kernel adapter representation
 59  * @tx_msg:     Messages from above to be sent
 60  * @lock:       Mutual exclusion
 61  * @tx_pos:     Current pos in TX message
 62  * @nmsgs:      Number of messages in tx_msg
 63  * @state:      See STATE_
 64  * @rx_msg:     Current RX message
 65  * @rx_pos:     Position within current RX message
 66  */
 67 struct xiic_i2c {
 68         void __iomem            *base;
 69         wait_queue_head_t       wait;
 70         struct i2c_adapter      adap;
 71         struct i2c_msg          *tx_msg;
 72         spinlock_t              lock;
 73         unsigned int            tx_pos;
 74         unsigned int            nmsgs;
 75         enum xilinx_i2c_state   state;
 76         struct i2c_msg          *rx_msg;
 77         int                     rx_pos;
 78         enum xiic_endian        endianness;
 79 };
 80 
 81 
 82 #define XIIC_MSB_OFFSET 0
 83 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
 84 
 85 /*
 86  * Register offsets in bytes from RegisterBase. Three is added to the
 87  * base offset to access LSB (IBM style) of the word
 88  */
 89 #define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET)     /* Control Register   */
 90 #define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET)     /* Status Register    */
 91 #define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)     /* Data Tx Register   */
 92 #define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)     /* Data Rx Register   */
 93 #define XIIC_ADR_REG_OFFSET  (0x10+XIIC_REG_OFFSET)     /* Address Register   */
 94 #define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)     /* Tx FIFO Occupancy  */
 95 #define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)     /* Rx FIFO Occupancy  */
 96 #define XIIC_TBA_REG_OFFSET  (0x1C+XIIC_REG_OFFSET)     /* 10 Bit Address reg */
 97 #define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)     /* Rx FIFO Depth reg  */
 98 #define XIIC_GPO_REG_OFFSET  (0x24+XIIC_REG_OFFSET)     /* Output Register    */
 99 
100 /* Control Register masks */
101 #define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
102 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
103 #define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
104 #define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
105 #define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
106 #define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
107 #define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
108 
109 /* Status Register masks */
110 #define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
111 #define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
112 #define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
113 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
114 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
115 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
116 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
117 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80  /* 1 = Tx FIFO empty      */
118 
119 /* Interrupt Status Register masks    Interrupt occurs when...       */
120 #define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
121 #define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete */
122 #define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
123 #define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level */
124 #define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
125 #define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
126 #define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
127 #define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
128 
129 /* The following constants specify the depth of the FIFOs */
130 #define IIC_RX_FIFO_DEPTH         16    /* Rx fifo capacity               */
131 #define IIC_TX_FIFO_DEPTH         16    /* Tx fifo capacity               */
132 
133 /* The following constants specify groups of interrupts that are typically
134  * enabled or disables at the same time
135  */
136 #define XIIC_TX_INTERRUPTS                           \
137 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
138 
139 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
140 
141 /* The following constants are used with the following macros to specify the
142  * operation, a read or write operation.
143  */
144 #define XIIC_READ_OPERATION  1
145 #define XIIC_WRITE_OPERATION 0
146 
147 /*
148  * Tx Fifo upper bit masks.
149  */
150 #define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
151 #define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */
152 
153 /*
154  * The following constants define the register offsets for the Interrupt
155  * registers. There are some holes in the memory map for reserved addresses
156  * to allow other registers to be added and still match the memory map of the
157  * interrupt controller registers
158  */
159 #define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
160 #define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
161 #define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
162 #define XIIC_RESETR_OFFSET   0x40 /* Reset Register */
163 
164 #define XIIC_RESET_MASK             0xAUL
165 
166 /*
167  * The following constant is used for the device global interrupt enable
168  * register, to enable all interrupts for the device, this is the only bit
169  * in the register
170  */
171 #define XIIC_GINTR_ENABLE_MASK      0x80000000UL
172 
173 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
174 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
175 
176 static void xiic_start_xfer(struct xiic_i2c *i2c);
177 static void __xiic_start_xfer(struct xiic_i2c *i2c);
178 
179 /*
180  * For the register read and write functions, a little-endian and big-endian
181  * version are necessary. Endianness is detected during the probe function.
182  * Only the least significant byte [doublet] of the register are ever
183  * accessed. This requires an offset of 3 [2] from the base address for
184  * big-endian systems.
185  */
186 
187 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
188 {
189         if (i2c->endianness == LITTLE)
190                 iowrite8(value, i2c->base + reg);
191         else
192                 iowrite8(value, i2c->base + reg + 3);
193 }
194 
195 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
196 {
197         u8 ret;
198 
199         if (i2c->endianness == LITTLE)
200                 ret = ioread8(i2c->base + reg);
201         else
202                 ret = ioread8(i2c->base + reg + 3);
203         return ret;
204 }
205 
206 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
207 {
208         if (i2c->endianness == LITTLE)
209                 iowrite16(value, i2c->base + reg);
210         else
211                 iowrite16be(value, i2c->base + reg + 2);
212 }
213 
214 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
215 {
216         if (i2c->endianness == LITTLE)
217                 iowrite32(value, i2c->base + reg);
218         else
219                 iowrite32be(value, i2c->base + reg);
220 }
221 
222 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
223 {
224         u32 ret;
225 
226         if (i2c->endianness == LITTLE)
227                 ret = ioread32(i2c->base + reg);
228         else
229                 ret = ioread32be(i2c->base + reg);
230         return ret;
231 }
232 
233 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
234 {
235         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
236         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
237 }
238 
239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
240 {
241         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
242         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
243 }
244 
245 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
246 {
247         u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
248         xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
249 }
250 
251 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
252 {
253         xiic_irq_clr(i2c, mask);
254         xiic_irq_en(i2c, mask);
255 }
256 
257 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
258 {
259         u8 sr;
260         for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
261                 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
262                 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
263                 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
264 }
265 
266 static void xiic_reinit(struct xiic_i2c *i2c)
267 {
268         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
269 
270         /* Set receive Fifo depth to maximum (zero based). */
271         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
272 
273         /* Reset Tx Fifo. */
274         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
275 
276         /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
277         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
278 
279         /* make sure RX fifo is empty */
280         xiic_clear_rx_fifo(i2c);
281 
282         /* Enable interrupts */
283         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
284 
285         xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
286 }
287 
288 static void xiic_deinit(struct xiic_i2c *i2c)
289 {
290         u8 cr;
291 
292         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
293 
294         /* Disable IIC Device. */
295         cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
296         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
297 }
298 
299 static void xiic_read_rx(struct xiic_i2c *i2c)
300 {
301         u8 bytes_in_fifo;
302         int i;
303 
304         bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
305 
306         dev_dbg(i2c->adap.dev.parent,
307                 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
308                 __func__, bytes_in_fifo, xiic_rx_space(i2c),
309                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
310                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
311 
312         if (bytes_in_fifo > xiic_rx_space(i2c))
313                 bytes_in_fifo = xiic_rx_space(i2c);
314 
315         for (i = 0; i < bytes_in_fifo; i++)
316                 i2c->rx_msg->buf[i2c->rx_pos++] =
317                         xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
318 
319         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
320                 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
321                 IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);
322 }
323 
324 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
325 {
326         /* return the actual space left in the FIFO */
327         return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
328 }
329 
330 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
331 {
332         u8 fifo_space = xiic_tx_fifo_space(i2c);
333         int len = xiic_tx_space(i2c);
334 
335         len = (len > fifo_space) ? fifo_space : len;
336 
337         dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
338                 __func__, len, fifo_space);
339 
340         while (len--) {
341                 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
342                 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
343                         /* last message in transfer -> STOP */
344                         data |= XIIC_TX_DYN_STOP_MASK;
345                         dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
346                 }
347                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
348         }
349 }
350 
351 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
352 {
353         i2c->tx_msg = NULL;
354         i2c->rx_msg = NULL;
355         i2c->nmsgs = 0;
356         i2c->state = code;
357         wake_up(&i2c->wait);
358 }
359 
360 static void xiic_process(struct xiic_i2c *i2c)
361 {
362         u32 pend, isr, ier;
363         u32 clr = 0;
364 
365         /* Get the interrupt Status from the IPIF. There is no clearing of
366          * interrupts in the IPIF. Interrupts must be cleared at the source.
367          * To find which interrupts are pending; AND interrupts pending with
368          * interrupts masked.
369          */
370         isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
371         ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
372         pend = isr & ier;
373 
374         dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
375                 __func__, ier, isr, pend);
376         dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
377                 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
378                 i2c->tx_msg, i2c->nmsgs);
379 
380         /* Do not processes a devices interrupts if the device has no
381          * interrupts pending
382          */
383         if (!pend)
384                 return;
385 
386         /* Service requesting interrupt */
387         if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
388                 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
389                 !(pend & XIIC_INTR_RX_FULL_MASK))) {
390                 /* bus arbritration lost, or...
391                  * Transmit error _OR_ RX completed
392                  * if this happens when RX_FULL is not set
393                  * this is probably a TX error
394                  */
395 
396                 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
397 
398                 /* dynamic mode seem to suffer from problems if we just flushes
399                  * fifos and the next message is a TX with len 0 (only addr)
400                  * reset the IP instead of just flush fifos
401                  */
402                 xiic_reinit(i2c);
403 
404                 if (i2c->tx_msg)
405                         xiic_wakeup(i2c, STATE_ERROR);
406 
407         } else if (pend & XIIC_INTR_RX_FULL_MASK) {
408                 /* Receive register/FIFO is full */
409 
410                 clr = XIIC_INTR_RX_FULL_MASK;
411                 if (!i2c->rx_msg) {
412                         dev_dbg(i2c->adap.dev.parent,
413                                 "%s unexpexted RX IRQ\n", __func__);
414                         xiic_clear_rx_fifo(i2c);
415                         goto out;
416                 }
417 
418                 xiic_read_rx(i2c);
419                 if (xiic_rx_space(i2c) == 0) {
420                         /* this is the last part of the message */
421                         i2c->rx_msg = NULL;
422 
423                         /* also clear TX error if there (RX complete) */
424                         clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
425 
426                         dev_dbg(i2c->adap.dev.parent,
427                                 "%s end of message, nmsgs: %d\n",
428                                 __func__, i2c->nmsgs);
429 
430                         /* send next message if this wasn't the last,
431                          * otherwise the transfer will be finialise when
432                          * receiving the bus not busy interrupt
433                          */
434                         if (i2c->nmsgs > 1) {
435                                 i2c->nmsgs--;
436                                 i2c->tx_msg++;
437                                 dev_dbg(i2c->adap.dev.parent,
438                                         "%s will start next...\n", __func__);
439 
440                                 __xiic_start_xfer(i2c);
441                         }
442                 }
443         } else if (pend & XIIC_INTR_BNB_MASK) {
444                 /* IIC bus has transitioned to not busy */
445                 clr = XIIC_INTR_BNB_MASK;
446 
447                 /* The bus is not busy, disable BusNotBusy interrupt */
448                 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
449 
450                 if (!i2c->tx_msg)
451                         goto out;
452 
453                 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
454                         xiic_tx_space(i2c) == 0)
455                         xiic_wakeup(i2c, STATE_DONE);
456                 else
457                         xiic_wakeup(i2c, STATE_ERROR);
458 
459         } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
460                 /* Transmit register/FIFO is empty or ½ empty */
461 
462                 clr = pend &
463                         (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
464 
465                 if (!i2c->tx_msg) {
466                         dev_dbg(i2c->adap.dev.parent,
467                                 "%s unexpexted TX IRQ\n", __func__);
468                         goto out;
469                 }
470 
471                 xiic_fill_tx_fifo(i2c);
472 
473                 /* current message sent and there is space in the fifo */
474                 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
475                         dev_dbg(i2c->adap.dev.parent,
476                                 "%s end of message sent, nmsgs: %d\n",
477                                 __func__, i2c->nmsgs);
478                         if (i2c->nmsgs > 1) {
479                                 i2c->nmsgs--;
480                                 i2c->tx_msg++;
481                                 __xiic_start_xfer(i2c);
482                         } else {
483                                 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
484 
485                                 dev_dbg(i2c->adap.dev.parent,
486                                         "%s Got TX IRQ but no more to do...\n",
487                                         __func__);
488                         }
489                 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
490                         /* current frame is sent and is last,
491                          * make sure to disable tx half
492                          */
493                         xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
494         } else {
495                 /* got IRQ which is not acked */
496                 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
497                         __func__);
498                 clr = pend;
499         }
500 out:
501         dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
502 
503         xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
504 }
505 
506 static int xiic_bus_busy(struct xiic_i2c *i2c)
507 {
508         u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
509 
510         return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
511 }
512 
513 static int xiic_busy(struct xiic_i2c *i2c)
514 {
515         int tries = 3;
516         int err;
517 
518         if (i2c->tx_msg)
519                 return -EBUSY;
520 
521         /* for instance if previous transfer was terminated due to TX error
522          * it might be that the bus is on it's way to become available
523          * give it at most 3 ms to wake
524          */
525         err = xiic_bus_busy(i2c);
526         while (err && tries--) {
527                 mdelay(1);
528                 err = xiic_bus_busy(i2c);
529         }
530 
531         return err;
532 }
533 
534 static void xiic_start_recv(struct xiic_i2c *i2c)
535 {
536         u8 rx_watermark;
537         struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
538 
539         /* Clear and enable Rx full interrupt. */
540         xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
541 
542         /* we want to get all but last byte, because the TX_ERROR IRQ is used
543          * to inidicate error ACK on the address, and negative ack on the last
544          * received byte, so to not mix them receive all but last.
545          * In the case where there is only one byte to receive
546          * we can check if ERROR and RX full is set at the same time
547          */
548         rx_watermark = msg->len;
549         if (rx_watermark > IIC_RX_FIFO_DEPTH)
550                 rx_watermark = IIC_RX_FIFO_DEPTH;
551         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
552 
553         if (!(msg->flags & I2C_M_NOSTART))
554                 /* write the address */
555                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
556                         (msg->addr << 1) | XIIC_READ_OPERATION |
557                         XIIC_TX_DYN_START_MASK);
558 
559         xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
560 
561         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
562                 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
563         if (i2c->nmsgs == 1)
564                 /* very last, enable bus not busy as well */
565                 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
566 
567         /* the message is tx:ed */
568         i2c->tx_pos = msg->len;
569 }
570 
571 static void xiic_start_send(struct xiic_i2c *i2c)
572 {
573         struct i2c_msg *msg = i2c->tx_msg;
574 
575         xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
576 
577         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
578                 __func__, msg, msg->len);
579         dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
580                 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
581                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
582 
583         if (!(msg->flags & I2C_M_NOSTART)) {
584                 /* write the address */
585                 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
586                         XIIC_TX_DYN_START_MASK;
587                 if ((i2c->nmsgs == 1) && msg->len == 0)
588                         /* no data and last message -> add STOP */
589                         data |= XIIC_TX_DYN_STOP_MASK;
590 
591                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
592         }
593 
594         xiic_fill_tx_fifo(i2c);
595 
596         /* Clear any pending Tx empty, Tx Error and then enable them. */
597         xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
598                 XIIC_INTR_BNB_MASK);
599 }
600 
601 static irqreturn_t xiic_isr(int irq, void *dev_id)
602 {
603         struct xiic_i2c *i2c = dev_id;
604 
605         spin_lock(&i2c->lock);
606         /* disable interrupts globally */
607         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
608 
609         dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
610 
611         xiic_process(i2c);
612 
613         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
614         spin_unlock(&i2c->lock);
615 
616         return IRQ_HANDLED;
617 }
618 
619 static void __xiic_start_xfer(struct xiic_i2c *i2c)
620 {
621         int first = 1;
622         int fifo_space = xiic_tx_fifo_space(i2c);
623         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
624                 __func__, i2c->tx_msg, fifo_space);
625 
626         if (!i2c->tx_msg)
627                 return;
628 
629         i2c->rx_pos = 0;
630         i2c->tx_pos = 0;
631         i2c->state = STATE_START;
632         while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
633                 if (!first) {
634                         i2c->nmsgs--;
635                         i2c->tx_msg++;
636                         i2c->tx_pos = 0;
637                 } else
638                         first = 0;
639 
640                 if (i2c->tx_msg->flags & I2C_M_RD) {
641                         /* we dont date putting several reads in the FIFO */
642                         xiic_start_recv(i2c);
643                         return;
644                 } else {
645                         xiic_start_send(i2c);
646                         if (xiic_tx_space(i2c) != 0) {
647                                 /* the message could not be completely sent */
648                                 break;
649                         }
650                 }
651 
652                 fifo_space = xiic_tx_fifo_space(i2c);
653         }
654 
655         /* there are more messages or the current one could not be completely
656          * put into the FIFO, also enable the half empty interrupt
657          */
658         if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
659                 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
660 
661 }
662 
663 static void xiic_start_xfer(struct xiic_i2c *i2c)
664 {
665         unsigned long flags;
666 
667         spin_lock_irqsave(&i2c->lock, flags);
668         xiic_reinit(i2c);
669         /* disable interrupts globally */
670         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
671         spin_unlock_irqrestore(&i2c->lock, flags);
672 
673         __xiic_start_xfer(i2c);
674         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
675 }
676 
677 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
678 {
679         struct xiic_i2c *i2c = i2c_get_adapdata(adap);
680         int err;
681 
682         dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
683                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
684 
685         err = xiic_busy(i2c);
686         if (err)
687                 return err;
688 
689         i2c->tx_msg = msgs;
690         i2c->nmsgs = num;
691 
692         xiic_start_xfer(i2c);
693 
694         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
695                 (i2c->state == STATE_DONE), HZ))
696                 return (i2c->state == STATE_DONE) ? num : -EIO;
697         else {
698                 i2c->tx_msg = NULL;
699                 i2c->rx_msg = NULL;
700                 i2c->nmsgs = 0;
701                 return -ETIMEDOUT;
702         }
703 }
704 
705 static u32 xiic_func(struct i2c_adapter *adap)
706 {
707         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
708 }
709 
710 static const struct i2c_algorithm xiic_algorithm = {
711         .master_xfer = xiic_xfer,
712         .functionality = xiic_func,
713 };
714 
715 static struct i2c_adapter xiic_adapter = {
716         .owner = THIS_MODULE,
717         .name = DRIVER_NAME,
718         .class = I2C_CLASS_DEPRECATED,
719         .algo = &xiic_algorithm,
720 };
721 
722 
723 static int xiic_i2c_probe(struct platform_device *pdev)
724 {
725         struct xiic_i2c *i2c;
726         struct xiic_i2c_platform_data *pdata;
727         struct resource *res;
728         int ret, irq;
729         u8 i;
730         u32 sr;
731 
732         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
733         if (!i2c)
734                 return -ENOMEM;
735 
736         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
737         i2c->base = devm_ioremap_resource(&pdev->dev, res);
738         if (IS_ERR(i2c->base))
739                 return PTR_ERR(i2c->base);
740 
741         irq = platform_get_irq(pdev, 0);
742         if (irq < 0)
743                 return irq;
744 
745         pdata = dev_get_platdata(&pdev->dev);
746 
747         /* hook up driver to tree */
748         platform_set_drvdata(pdev, i2c);
749         i2c->adap = xiic_adapter;
750         i2c_set_adapdata(&i2c->adap, i2c);
751         i2c->adap.dev.parent = &pdev->dev;
752         i2c->adap.dev.of_node = pdev->dev.of_node;
753 
754         spin_lock_init(&i2c->lock);
755         init_waitqueue_head(&i2c->wait);
756 
757         ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c);
758         if (ret < 0) {
759                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
760                 return ret;
761         }
762 
763         /*
764          * Detect endianness
765          * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
766          * set, assume that the endianness was wrong and swap.
767          */
768         i2c->endianness = LITTLE;
769         xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
770         /* Reset is cleared in xiic_reinit */
771         sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
772         if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
773                 i2c->endianness = BIG;
774 
775         xiic_reinit(i2c);
776 
777         /* add i2c adapter to i2c tree */
778         ret = i2c_add_adapter(&i2c->adap);
779         if (ret) {
780                 dev_err(&pdev->dev, "Failed to add adapter\n");
781                 xiic_deinit(i2c);
782                 return ret;
783         }
784 
785         if (pdata) {
786                 /* add in known devices to the bus */
787                 for (i = 0; i < pdata->num_devices; i++)
788                         i2c_new_device(&i2c->adap, pdata->devices + i);
789         }
790 
791         return 0;
792 }
793 
794 static int xiic_i2c_remove(struct platform_device *pdev)
795 {
796         struct xiic_i2c *i2c = platform_get_drvdata(pdev);
797 
798         /* remove adapter & data */
799         i2c_del_adapter(&i2c->adap);
800 
801         xiic_deinit(i2c);
802 
803         return 0;
804 }
805 
806 #if defined(CONFIG_OF)
807 static const struct of_device_id xiic_of_match[] = {
808         { .compatible = "xlnx,xps-iic-2.00.a", },
809         {},
810 };
811 MODULE_DEVICE_TABLE(of, xiic_of_match);
812 #endif
813 
814 static struct platform_driver xiic_i2c_driver = {
815         .probe   = xiic_i2c_probe,
816         .remove  = xiic_i2c_remove,
817         .driver  = {
818                 .name = DRIVER_NAME,
819                 .of_match_table = of_match_ptr(xiic_of_match),
820         },
821 };
822 
823 module_platform_driver(xiic_i2c_driver);
824 
825 MODULE_AUTHOR("info@mocean-labs.com");
826 MODULE_DESCRIPTION("Xilinx I2C bus driver");
827 MODULE_LICENSE("GPL v2");
828 MODULE_ALIAS("platform:"DRIVER_NAME);
829 

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