Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/i2c/busses/i2c-tegra.c

  1 /*
  2  * drivers/i2c/busses/i2c-tegra.c
  3  *
  4  * Copyright (C) 2010 Google, Inc.
  5  * Author: Colin Cross <ccross@android.com>
  6  *
  7  * This software is licensed under the terms of the GNU General Public
  8  * License version 2, as published by the Free Software Foundation, and
  9  * may be copied, distributed, and modified under those terms.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  */
 17 
 18 #include <linux/kernel.h>
 19 #include <linux/init.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/clk.h>
 22 #include <linux/err.h>
 23 #include <linux/i2c.h>
 24 #include <linux/io.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/delay.h>
 27 #include <linux/slab.h>
 28 #include <linux/of_device.h>
 29 #include <linux/module.h>
 30 #include <linux/reset.h>
 31 #include <linux/pinctrl/consumer.h>
 32 #include <linux/pm_runtime.h>
 33 #include <linux/iopoll.h>
 34 
 35 #include <asm/unaligned.h>
 36 
 37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
 38 #define BYTES_PER_FIFO_WORD 4
 39 
 40 #define I2C_CNFG                                0x000
 41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
 42 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
 43 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
 44 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
 45 #define I2C_STATUS                              0x01C
 46 #define I2C_SL_CNFG                             0x020
 47 #define I2C_SL_CNFG_NACK                        BIT(1)
 48 #define I2C_SL_CNFG_NEWSL                       BIT(2)
 49 #define I2C_SL_ADDR1                            0x02c
 50 #define I2C_SL_ADDR2                            0x030
 51 #define I2C_TX_FIFO                             0x050
 52 #define I2C_RX_FIFO                             0x054
 53 #define I2C_PACKET_TRANSFER_STATUS              0x058
 54 #define I2C_FIFO_CONTROL                        0x05c
 55 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
 56 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
 57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
 58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
 59 #define I2C_FIFO_STATUS                         0x060
 60 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
 61 #define I2C_FIFO_STATUS_TX_SHIFT                4
 62 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
 63 #define I2C_FIFO_STATUS_RX_SHIFT                0
 64 #define I2C_INT_MASK                            0x064
 65 #define I2C_INT_STATUS                          0x068
 66 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
 67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       BIT(6)
 68 #define I2C_INT_TX_FIFO_OVERFLOW                BIT(5)
 69 #define I2C_INT_RX_FIFO_UNDERFLOW               BIT(4)
 70 #define I2C_INT_NO_ACK                          BIT(3)
 71 #define I2C_INT_ARBITRATION_LOST                BIT(2)
 72 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
 73 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
 74 #define I2C_CLK_DIVISOR                         0x06c
 75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
 76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
 77 
 78 #define DVC_CTRL_REG1                           0x000
 79 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
 80 #define DVC_CTRL_REG2                           0x004
 81 #define DVC_CTRL_REG3                           0x008
 82 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
 83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
 84 #define DVC_STATUS                              0x00c
 85 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
 86 
 87 #define I2C_ERR_NONE                            0x00
 88 #define I2C_ERR_NO_ACK                          0x01
 89 #define I2C_ERR_ARBITRATION_LOST                0x02
 90 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
 91 
 92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
 93 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
 94 #define PACKET_HEADER0_CONT_ID_SHIFT            12
 95 #define PACKET_HEADER0_PROTOCOL_I2C             BIT(4)
 96 
 97 #define I2C_HEADER_HIGHSPEED_MODE               BIT(22)
 98 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
 99 #define I2C_HEADER_SEND_START_BYTE              BIT(20)
100 #define I2C_HEADER_READ                         BIT(19)
101 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
102 #define I2C_HEADER_IE_ENABLE                    BIT(17)
103 #define I2C_HEADER_REPEAT_START                 BIT(16)
104 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
105 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
106 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
107 
108 #define I2C_CONFIG_LOAD                         0x08C
109 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
110 #define I2C_SLV_CONFIG_LOAD                     BIT(1)
111 #define I2C_TIMEOUT_CONFIG_LOAD                 BIT(2)
112 
113 #define I2C_CLKEN_OVERRIDE                      0x090
114 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
115 
116 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
117 
118 /*
119  * msg_end_type: The bus control which need to be send at end of transfer.
120  * @MSG_END_STOP: Send stop pulse at end of transfer.
121  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
122  * @MSG_END_CONTINUE: The following on message is coming and so do not send
123  *              stop or repeat start.
124  */
125 enum msg_end_type {
126         MSG_END_STOP,
127         MSG_END_REPEAT_START,
128         MSG_END_CONTINUE,
129 };
130 
131 /**
132  * struct tegra_i2c_hw_feature : Different HW support on Tegra
133  * @has_continue_xfer_support: Continue transfer supports.
134  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
135  *              complete interrupt per packet basis.
136  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
137  *              and earlier Socs has two clock sources i.e. div-clk and
138  *              fast-clk.
139  * @has_config_load_reg: Has the config load register to load the new
140  *              configuration.
141  * @clk_divisor_hs_mode: Clock divisor in HS mode.
142  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
143  *              applicable if there is no fast clock source i.e. single clock
144  *              source.
145  */
146 
147 struct tegra_i2c_hw_feature {
148         bool has_continue_xfer_support;
149         bool has_per_pkt_xfer_complete_irq;
150         bool has_single_clk_source;
151         bool has_config_load_reg;
152         int clk_divisor_hs_mode;
153         int clk_divisor_std_fast_mode;
154         u16 clk_divisor_fast_plus_mode;
155         bool has_multi_master_mode;
156         bool has_slcg_override_reg;
157 };
158 
159 /**
160  * struct tegra_i2c_dev - per device i2c context
161  * @dev: device reference for power management
162  * @hw: Tegra i2c hw feature.
163  * @adapter: core i2c layer adapter information
164  * @div_clk: clock reference for div clock of i2c controller.
165  * @fast_clk: clock reference for fast clock of i2c controller.
166  * @base: ioremapped registers cookie
167  * @cont_id: i2c controller id, used for for packet header
168  * @irq: irq number of transfer complete interrupt
169  * @is_dvc: identifies the DVC i2c controller, has a different register layout
170  * @msg_complete: transfer completion notifier
171  * @msg_err: error code for completed message
172  * @msg_buf: pointer to current message data
173  * @msg_buf_remaining: size of unsent data in the message buffer
174  * @msg_read: identifies read transfers
175  * @bus_clk_rate: current i2c bus clock rate
176  * @is_suspended: prevents i2c controller accesses after suspend is called
177  */
178 struct tegra_i2c_dev {
179         struct device *dev;
180         const struct tegra_i2c_hw_feature *hw;
181         struct i2c_adapter adapter;
182         struct clk *div_clk;
183         struct clk *fast_clk;
184         struct reset_control *rst;
185         void __iomem *base;
186         int cont_id;
187         int irq;
188         bool irq_disabled;
189         int is_dvc;
190         struct completion msg_complete;
191         int msg_err;
192         u8 *msg_buf;
193         size_t msg_buf_remaining;
194         int msg_read;
195         u32 bus_clk_rate;
196         u16 clk_divisor_non_hs_mode;
197         bool is_suspended;
198         bool is_multimaster_mode;
199         spinlock_t xfer_lock;
200 };
201 
202 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
203                        unsigned long reg)
204 {
205         writel(val, i2c_dev->base + reg);
206 }
207 
208 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
209 {
210         return readl(i2c_dev->base + reg);
211 }
212 
213 /*
214  * i2c_writel and i2c_readl will offset the register if necessary to talk
215  * to the I2C block inside the DVC block
216  */
217 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
218         unsigned long reg)
219 {
220         if (i2c_dev->is_dvc)
221                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
222         return reg;
223 }
224 
225 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
226         unsigned long reg)
227 {
228         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
229 
230         /* Read back register to make sure that register writes completed */
231         if (reg != I2C_TX_FIFO)
232                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
233 }
234 
235 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
236 {
237         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
238 }
239 
240 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
241         unsigned long reg, int len)
242 {
243         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
244 }
245 
246 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
247         unsigned long reg, int len)
248 {
249         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
250 }
251 
252 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
253 {
254         u32 int_mask;
255 
256         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
257         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
258 }
259 
260 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
261 {
262         u32 int_mask;
263 
264         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
265         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
266 }
267 
268 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
269 {
270         unsigned long timeout = jiffies + HZ;
271         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
272 
273         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
274         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
275 
276         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
277                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
278                 if (time_after(jiffies, timeout)) {
279                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
280                         return -ETIMEDOUT;
281                 }
282                 msleep(1);
283         }
284         return 0;
285 }
286 
287 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
288 {
289         u32 val;
290         int rx_fifo_avail;
291         u8 *buf = i2c_dev->msg_buf;
292         size_t buf_remaining = i2c_dev->msg_buf_remaining;
293         int words_to_transfer;
294 
295         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
296         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
297                 I2C_FIFO_STATUS_RX_SHIFT;
298 
299         /* Rounds down to not include partial word at the end of buf */
300         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
301         if (words_to_transfer > rx_fifo_avail)
302                 words_to_transfer = rx_fifo_avail;
303 
304         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
305 
306         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
307         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
308         rx_fifo_avail -= words_to_transfer;
309 
310         /*
311          * If there is a partial word at the end of buf, handle it manually to
312          * prevent overwriting past the end of buf
313          */
314         if (rx_fifo_avail > 0 && buf_remaining > 0) {
315                 BUG_ON(buf_remaining > 3);
316                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
317                 val = cpu_to_le32(val);
318                 memcpy(buf, &val, buf_remaining);
319                 buf_remaining = 0;
320                 rx_fifo_avail--;
321         }
322 
323         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
324         i2c_dev->msg_buf_remaining = buf_remaining;
325         i2c_dev->msg_buf = buf;
326         return 0;
327 }
328 
329 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
330 {
331         u32 val;
332         int tx_fifo_avail;
333         u8 *buf = i2c_dev->msg_buf;
334         size_t buf_remaining = i2c_dev->msg_buf_remaining;
335         int words_to_transfer;
336 
337         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
338         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
339                 I2C_FIFO_STATUS_TX_SHIFT;
340 
341         /* Rounds down to not include partial word at the end of buf */
342         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
343 
344         /* It's very common to have < 4 bytes, so optimize that case. */
345         if (words_to_transfer) {
346                 if (words_to_transfer > tx_fifo_avail)
347                         words_to_transfer = tx_fifo_avail;
348 
349                 /*
350                  * Update state before writing to FIFO.  If this casues us
351                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
352                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
353                  * not maskable).  We need to make sure that the isr sees
354                  * buf_remaining as 0 and doesn't call us back re-entrantly.
355                  */
356                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
357                 tx_fifo_avail -= words_to_transfer;
358                 i2c_dev->msg_buf_remaining = buf_remaining;
359                 i2c_dev->msg_buf = buf +
360                         words_to_transfer * BYTES_PER_FIFO_WORD;
361                 barrier();
362 
363                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
364 
365                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
366         }
367 
368         /*
369          * If there is a partial word at the end of buf, handle it manually to
370          * prevent reading past the end of buf, which could cross a page
371          * boundary and fault.
372          */
373         if (tx_fifo_avail > 0 && buf_remaining > 0) {
374                 BUG_ON(buf_remaining > 3);
375                 memcpy(&val, buf, buf_remaining);
376                 val = le32_to_cpu(val);
377 
378                 /* Again update before writing to FIFO to make sure isr sees. */
379                 i2c_dev->msg_buf_remaining = 0;
380                 i2c_dev->msg_buf = NULL;
381                 barrier();
382 
383                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
384         }
385 
386         return 0;
387 }
388 
389 /*
390  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
391  * block.  This block is identical to the rest of the I2C blocks, except that
392  * it only supports master mode, it has registers moved around, and it needs
393  * some extra init to get it into I2C mode.  The register moves are handled
394  * by i2c_readl and i2c_writel
395  */
396 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
397 {
398         u32 val;
399 
400         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
401         val |= DVC_CTRL_REG3_SW_PROG;
402         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
403         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
404 
405         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
406         val |= DVC_CTRL_REG1_INTR_EN;
407         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
408 }
409 
410 static int tegra_i2c_runtime_resume(struct device *dev)
411 {
412         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
413         int ret;
414 
415         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
416         if (ret)
417                 return ret;
418 
419         if (!i2c_dev->hw->has_single_clk_source) {
420                 ret = clk_enable(i2c_dev->fast_clk);
421                 if (ret < 0) {
422                         dev_err(i2c_dev->dev,
423                                 "Enabling fast clk failed, err %d\n", ret);
424                         return ret;
425                 }
426         }
427 
428         ret = clk_enable(i2c_dev->div_clk);
429         if (ret < 0) {
430                 dev_err(i2c_dev->dev,
431                         "Enabling div clk failed, err %d\n", ret);
432                 clk_disable(i2c_dev->fast_clk);
433                 return ret;
434         }
435 
436         return 0;
437 }
438 
439 static int tegra_i2c_runtime_suspend(struct device *dev)
440 {
441         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
442 
443         clk_disable(i2c_dev->div_clk);
444         if (!i2c_dev->hw->has_single_clk_source)
445                 clk_disable(i2c_dev->fast_clk);
446 
447         return pinctrl_pm_select_idle_state(i2c_dev->dev);
448 }
449 
450 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
451 {
452         unsigned long reg_offset;
453         void __iomem *addr;
454         u32 val;
455         int err;
456 
457         if (i2c_dev->hw->has_config_load_reg) {
458                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
459                 addr = i2c_dev->base + reg_offset;
460                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
461                 if (in_interrupt())
462                         err = readl_poll_timeout_atomic(addr, val, val == 0,
463                                         1000, I2C_CONFIG_LOAD_TIMEOUT);
464                 else
465                         err = readl_poll_timeout(addr, val, val == 0,
466                                         1000, I2C_CONFIG_LOAD_TIMEOUT);
467 
468                 if (err) {
469                         dev_warn(i2c_dev->dev,
470                                  "timeout waiting for config load\n");
471                         return err;
472                 }
473         }
474 
475         return 0;
476 }
477 
478 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
479 {
480         u32 val;
481         int err;
482         u32 clk_divisor;
483 
484         err = pm_runtime_get_sync(i2c_dev->dev);
485         if (err < 0) {
486                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
487                 return err;
488         }
489 
490         reset_control_assert(i2c_dev->rst);
491         udelay(2);
492         reset_control_deassert(i2c_dev->rst);
493 
494         if (i2c_dev->is_dvc)
495                 tegra_dvc_init(i2c_dev);
496 
497         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
498                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
499 
500         if (i2c_dev->hw->has_multi_master_mode)
501                 val |= I2C_CNFG_MULTI_MASTER_MODE;
502 
503         i2c_writel(i2c_dev, val, I2C_CNFG);
504         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
505 
506         /* Make sure clock divisor programmed correctly */
507         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
508         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
509                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
510         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
511 
512         if (!i2c_dev->is_dvc) {
513                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
514 
515                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
516                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
517                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
518                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
519         }
520 
521         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
522                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
523         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
524 
525         err = tegra_i2c_flush_fifos(i2c_dev);
526         if (err)
527                 goto err;
528 
529         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
530                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
531 
532         err = tegra_i2c_wait_for_config_load(i2c_dev);
533         if (err)
534                 goto err;
535 
536         if (i2c_dev->irq_disabled) {
537                 i2c_dev->irq_disabled = false;
538                 enable_irq(i2c_dev->irq);
539         }
540 
541 err:
542         pm_runtime_put(i2c_dev->dev);
543         return err;
544 }
545 
546 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
547 {
548         u32 cnfg;
549 
550         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
551         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
552                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
553 
554         return tegra_i2c_wait_for_config_load(i2c_dev);
555 }
556 
557 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
558 {
559         u32 status;
560         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
561         struct tegra_i2c_dev *i2c_dev = dev_id;
562         unsigned long flags;
563 
564         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
565 
566         spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
567         if (status == 0) {
568                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
569                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
570                          i2c_readl(i2c_dev, I2C_STATUS),
571                          i2c_readl(i2c_dev, I2C_CNFG));
572                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
573 
574                 if (!i2c_dev->irq_disabled) {
575                         disable_irq_nosync(i2c_dev->irq);
576                         i2c_dev->irq_disabled = true;
577                 }
578                 goto err;
579         }
580 
581         if (unlikely(status & status_err)) {
582                 tegra_i2c_disable_packet_mode(i2c_dev);
583                 if (status & I2C_INT_NO_ACK)
584                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
585                 if (status & I2C_INT_ARBITRATION_LOST)
586                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
587                 goto err;
588         }
589 
590         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
591                 if (i2c_dev->msg_buf_remaining)
592                         tegra_i2c_empty_rx_fifo(i2c_dev);
593                 else
594                         BUG();
595         }
596 
597         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
598                 if (i2c_dev->msg_buf_remaining)
599                         tegra_i2c_fill_tx_fifo(i2c_dev);
600                 else
601                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
602         }
603 
604         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
605         if (i2c_dev->is_dvc)
606                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
607 
608         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
609                 BUG_ON(i2c_dev->msg_buf_remaining);
610                 complete(&i2c_dev->msg_complete);
611         }
612         goto done;
613 err:
614         /* An error occurred, mask all interrupts */
615         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
616                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
617                 I2C_INT_RX_FIFO_DATA_REQ);
618         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
619         if (i2c_dev->is_dvc)
620                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
621 
622         complete(&i2c_dev->msg_complete);
623 done:
624         spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
625         return IRQ_HANDLED;
626 }
627 
628 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
629         struct i2c_msg *msg, enum msg_end_type end_state)
630 {
631         u32 packet_header;
632         u32 int_mask;
633         unsigned long time_left;
634         unsigned long flags;
635 
636         tegra_i2c_flush_fifos(i2c_dev);
637 
638         if (msg->len == 0)
639                 return -EINVAL;
640 
641         i2c_dev->msg_buf = msg->buf;
642         i2c_dev->msg_buf_remaining = msg->len;
643         i2c_dev->msg_err = I2C_ERR_NONE;
644         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
645         reinit_completion(&i2c_dev->msg_complete);
646 
647         spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
648 
649         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
650         tegra_i2c_unmask_irq(i2c_dev, int_mask);
651 
652         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
653                         PACKET_HEADER0_PROTOCOL_I2C |
654                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
655                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
656         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
657 
658         packet_header = msg->len - 1;
659         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
660 
661         packet_header = I2C_HEADER_IE_ENABLE;
662         if (end_state == MSG_END_CONTINUE)
663                 packet_header |= I2C_HEADER_CONTINUE_XFER;
664         else if (end_state == MSG_END_REPEAT_START)
665                 packet_header |= I2C_HEADER_REPEAT_START;
666         if (msg->flags & I2C_M_TEN) {
667                 packet_header |= msg->addr;
668                 packet_header |= I2C_HEADER_10BIT_ADDR;
669         } else {
670                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
671         }
672         if (msg->flags & I2C_M_IGNORE_NAK)
673                 packet_header |= I2C_HEADER_CONT_ON_NAK;
674         if (msg->flags & I2C_M_RD)
675                 packet_header |= I2C_HEADER_READ;
676         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
677 
678         if (!(msg->flags & I2C_M_RD))
679                 tegra_i2c_fill_tx_fifo(i2c_dev);
680 
681         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
682                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
683         if (msg->flags & I2C_M_RD)
684                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
685         else if (i2c_dev->msg_buf_remaining)
686                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
687 
688         tegra_i2c_unmask_irq(i2c_dev, int_mask);
689         spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
690         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
691                 i2c_readl(i2c_dev, I2C_INT_MASK));
692 
693         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
694                                                 TEGRA_I2C_TIMEOUT);
695         tegra_i2c_mask_irq(i2c_dev, int_mask);
696 
697         if (time_left == 0) {
698                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
699 
700                 tegra_i2c_init(i2c_dev);
701                 return -ETIMEDOUT;
702         }
703 
704         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
705                 time_left, completion_done(&i2c_dev->msg_complete),
706                 i2c_dev->msg_err);
707 
708         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
709                 return 0;
710 
711         /*
712          * NACK interrupt is generated before the I2C controller generates
713          * the STOP condition on the bus. So wait for 2 clock periods
714          * before resetting the controller so that the STOP condition has
715          * been delivered properly.
716          */
717         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
718                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
719 
720         tegra_i2c_init(i2c_dev);
721         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
722                 if (msg->flags & I2C_M_IGNORE_NAK)
723                         return 0;
724                 return -EREMOTEIO;
725         }
726 
727         return -EIO;
728 }
729 
730 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
731         int num)
732 {
733         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
734         int i;
735         int ret = 0;
736 
737         if (i2c_dev->is_suspended)
738                 return -EBUSY;
739 
740         ret = pm_runtime_get_sync(i2c_dev->dev);
741         if (ret < 0) {
742                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
743                 return ret;
744         }
745 
746         for (i = 0; i < num; i++) {
747                 enum msg_end_type end_type = MSG_END_STOP;
748 
749                 if (i < (num - 1)) {
750                         if (msgs[i + 1].flags & I2C_M_NOSTART)
751                                 end_type = MSG_END_CONTINUE;
752                         else
753                                 end_type = MSG_END_REPEAT_START;
754                 }
755                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
756                 if (ret)
757                         break;
758         }
759 
760         pm_runtime_put(i2c_dev->dev);
761 
762         return ret ?: i;
763 }
764 
765 static u32 tegra_i2c_func(struct i2c_adapter *adap)
766 {
767         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
768         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
769                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
770 
771         if (i2c_dev->hw->has_continue_xfer_support)
772                 ret |= I2C_FUNC_NOSTART;
773         return ret;
774 }
775 
776 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
777 {
778         struct device_node *np = i2c_dev->dev->of_node;
779         int ret;
780 
781         ret = of_property_read_u32(np, "clock-frequency",
782                         &i2c_dev->bus_clk_rate);
783         if (ret)
784                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
785 
786         i2c_dev->is_multimaster_mode = of_property_read_bool(np,
787                         "multi-master");
788 }
789 
790 static const struct i2c_algorithm tegra_i2c_algo = {
791         .master_xfer    = tegra_i2c_xfer,
792         .functionality  = tegra_i2c_func,
793 };
794 
795 /* payload size is only 12 bit */
796 static struct i2c_adapter_quirks tegra_i2c_quirks = {
797         .max_read_len = 4096,
798         .max_write_len = 4096,
799 };
800 
801 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
802         .has_continue_xfer_support = false,
803         .has_per_pkt_xfer_complete_irq = false,
804         .has_single_clk_source = false,
805         .clk_divisor_hs_mode = 3,
806         .clk_divisor_std_fast_mode = 0,
807         .clk_divisor_fast_plus_mode = 0,
808         .has_config_load_reg = false,
809         .has_multi_master_mode = false,
810         .has_slcg_override_reg = false,
811 };
812 
813 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
814         .has_continue_xfer_support = true,
815         .has_per_pkt_xfer_complete_irq = false,
816         .has_single_clk_source = false,
817         .clk_divisor_hs_mode = 3,
818         .clk_divisor_std_fast_mode = 0,
819         .clk_divisor_fast_plus_mode = 0,
820         .has_config_load_reg = false,
821         .has_multi_master_mode = false,
822         .has_slcg_override_reg = false,
823 };
824 
825 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
826         .has_continue_xfer_support = true,
827         .has_per_pkt_xfer_complete_irq = true,
828         .has_single_clk_source = true,
829         .clk_divisor_hs_mode = 1,
830         .clk_divisor_std_fast_mode = 0x19,
831         .clk_divisor_fast_plus_mode = 0x10,
832         .has_config_load_reg = false,
833         .has_multi_master_mode = false,
834         .has_slcg_override_reg = false,
835 };
836 
837 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
838         .has_continue_xfer_support = true,
839         .has_per_pkt_xfer_complete_irq = true,
840         .has_single_clk_source = true,
841         .clk_divisor_hs_mode = 1,
842         .clk_divisor_std_fast_mode = 0x19,
843         .clk_divisor_fast_plus_mode = 0x10,
844         .has_config_load_reg = true,
845         .has_multi_master_mode = false,
846         .has_slcg_override_reg = true,
847 };
848 
849 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
850         .has_continue_xfer_support = true,
851         .has_per_pkt_xfer_complete_irq = true,
852         .has_single_clk_source = true,
853         .clk_divisor_hs_mode = 1,
854         .clk_divisor_std_fast_mode = 0x19,
855         .clk_divisor_fast_plus_mode = 0x10,
856         .has_config_load_reg = true,
857         .has_multi_master_mode = true,
858         .has_slcg_override_reg = true,
859 };
860 
861 /* Match table for of_platform binding */
862 static const struct of_device_id tegra_i2c_of_match[] = {
863         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
864         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
865         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
866         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
867         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
868         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
869         {},
870 };
871 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
872 
873 static int tegra_i2c_probe(struct platform_device *pdev)
874 {
875         struct tegra_i2c_dev *i2c_dev;
876         struct resource *res;
877         struct clk *div_clk;
878         struct clk *fast_clk;
879         void __iomem *base;
880         int irq;
881         int ret = 0;
882         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
883 
884         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
885         base = devm_ioremap_resource(&pdev->dev, res);
886         if (IS_ERR(base))
887                 return PTR_ERR(base);
888 
889         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
890         if (!res) {
891                 dev_err(&pdev->dev, "no irq resource\n");
892                 return -EINVAL;
893         }
894         irq = res->start;
895 
896         div_clk = devm_clk_get(&pdev->dev, "div-clk");
897         if (IS_ERR(div_clk)) {
898                 dev_err(&pdev->dev, "missing controller clock\n");
899                 return PTR_ERR(div_clk);
900         }
901 
902         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
903         if (!i2c_dev)
904                 return -ENOMEM;
905 
906         i2c_dev->base = base;
907         i2c_dev->div_clk = div_clk;
908         i2c_dev->adapter.algo = &tegra_i2c_algo;
909         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
910         i2c_dev->irq = irq;
911         i2c_dev->cont_id = pdev->id;
912         i2c_dev->dev = &pdev->dev;
913 
914         i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
915         if (IS_ERR(i2c_dev->rst)) {
916                 dev_err(&pdev->dev, "missing controller reset\n");
917                 return PTR_ERR(i2c_dev->rst);
918         }
919 
920         tegra_i2c_parse_dt(i2c_dev);
921 
922         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
923         i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
924                                                   "nvidia,tegra20-i2c-dvc");
925         init_completion(&i2c_dev->msg_complete);
926         spin_lock_init(&i2c_dev->xfer_lock);
927 
928         if (!i2c_dev->hw->has_single_clk_source) {
929                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
930                 if (IS_ERR(fast_clk)) {
931                         dev_err(&pdev->dev, "missing fast clock\n");
932                         return PTR_ERR(fast_clk);
933                 }
934                 i2c_dev->fast_clk = fast_clk;
935         }
936 
937         platform_set_drvdata(pdev, i2c_dev);
938 
939         if (!i2c_dev->hw->has_single_clk_source) {
940                 ret = clk_prepare(i2c_dev->fast_clk);
941                 if (ret < 0) {
942                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
943                         return ret;
944                 }
945         }
946 
947         i2c_dev->clk_divisor_non_hs_mode =
948                         i2c_dev->hw->clk_divisor_std_fast_mode;
949         if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
950                 (i2c_dev->bus_clk_rate == 1000000))
951                 i2c_dev->clk_divisor_non_hs_mode =
952                         i2c_dev->hw->clk_divisor_fast_plus_mode;
953 
954         clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
955         ret = clk_set_rate(i2c_dev->div_clk,
956                            i2c_dev->bus_clk_rate * clk_multiplier);
957         if (ret) {
958                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
959                 goto unprepare_fast_clk;
960         }
961 
962         ret = clk_prepare(i2c_dev->div_clk);
963         if (ret < 0) {
964                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
965                 goto unprepare_fast_clk;
966         }
967 
968         pm_runtime_enable(&pdev->dev);
969         if (!pm_runtime_enabled(&pdev->dev)) {
970                 ret = tegra_i2c_runtime_resume(&pdev->dev);
971                 if (ret < 0) {
972                         dev_err(&pdev->dev, "runtime resume failed\n");
973                         goto unprepare_div_clk;
974                 }
975         }
976 
977         if (i2c_dev->is_multimaster_mode) {
978                 ret = clk_enable(i2c_dev->div_clk);
979                 if (ret < 0) {
980                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
981                                 ret);
982                         goto disable_rpm;
983                 }
984         }
985 
986         ret = tegra_i2c_init(i2c_dev);
987         if (ret) {
988                 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
989                 goto disable_div_clk;
990         }
991 
992         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
993                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
994         if (ret) {
995                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
996                 goto disable_div_clk;
997         }
998 
999         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1000         i2c_dev->adapter.owner = THIS_MODULE;
1001         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1002         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1003                 sizeof(i2c_dev->adapter.name));
1004         i2c_dev->adapter.dev.parent = &pdev->dev;
1005         i2c_dev->adapter.nr = pdev->id;
1006         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1007 
1008         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1009         if (ret)
1010                 goto disable_div_clk;
1011 
1012         return 0;
1013 
1014 disable_div_clk:
1015         if (i2c_dev->is_multimaster_mode)
1016                 clk_disable(i2c_dev->div_clk);
1017 
1018 disable_rpm:
1019         pm_runtime_disable(&pdev->dev);
1020         if (!pm_runtime_status_suspended(&pdev->dev))
1021                 tegra_i2c_runtime_suspend(&pdev->dev);
1022 
1023 unprepare_div_clk:
1024         clk_unprepare(i2c_dev->div_clk);
1025 
1026 unprepare_fast_clk:
1027         if (!i2c_dev->hw->has_single_clk_source)
1028                 clk_unprepare(i2c_dev->fast_clk);
1029 
1030         return ret;
1031 }
1032 
1033 static int tegra_i2c_remove(struct platform_device *pdev)
1034 {
1035         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1036 
1037         i2c_del_adapter(&i2c_dev->adapter);
1038 
1039         if (i2c_dev->is_multimaster_mode)
1040                 clk_disable(i2c_dev->div_clk);
1041 
1042         pm_runtime_disable(&pdev->dev);
1043         if (!pm_runtime_status_suspended(&pdev->dev))
1044                 tegra_i2c_runtime_suspend(&pdev->dev);
1045 
1046         clk_unprepare(i2c_dev->div_clk);
1047         if (!i2c_dev->hw->has_single_clk_source)
1048                 clk_unprepare(i2c_dev->fast_clk);
1049 
1050         return 0;
1051 }
1052 
1053 #ifdef CONFIG_PM_SLEEP
1054 static int tegra_i2c_suspend(struct device *dev)
1055 {
1056         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1057 
1058         i2c_lock_adapter(&i2c_dev->adapter);
1059         i2c_dev->is_suspended = true;
1060         i2c_unlock_adapter(&i2c_dev->adapter);
1061 
1062         return 0;
1063 }
1064 
1065 static int tegra_i2c_resume(struct device *dev)
1066 {
1067         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1068         int ret;
1069 
1070         i2c_lock_adapter(&i2c_dev->adapter);
1071 
1072         ret = tegra_i2c_init(i2c_dev);
1073         if (!ret)
1074                 i2c_dev->is_suspended = false;
1075 
1076         i2c_unlock_adapter(&i2c_dev->adapter);
1077 
1078         return ret;
1079 }
1080 
1081 static const struct dev_pm_ops tegra_i2c_pm = {
1082         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1083                            NULL)
1084         SET_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1085 };
1086 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1087 #else
1088 #define TEGRA_I2C_PM    NULL
1089 #endif
1090 
1091 static struct platform_driver tegra_i2c_driver = {
1092         .probe   = tegra_i2c_probe,
1093         .remove  = tegra_i2c_remove,
1094         .driver  = {
1095                 .name  = "tegra-i2c",
1096                 .of_match_table = tegra_i2c_of_match,
1097                 .pm    = TEGRA_I2C_PM,
1098         },
1099 };
1100 
1101 static int __init tegra_i2c_init_driver(void)
1102 {
1103         return platform_driver_register(&tegra_i2c_driver);
1104 }
1105 
1106 static void __exit tegra_i2c_exit_driver(void)
1107 {
1108         platform_driver_unregister(&tegra_i2c_driver);
1109 }
1110 
1111 subsys_initcall(tegra_i2c_init_driver);
1112 module_exit(tegra_i2c_exit_driver);
1113 
1114 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1115 MODULE_AUTHOR("Colin Cross");
1116 MODULE_LICENSE("GPL v2");
1117 

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