Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/i2c/busses/i2c-tegra.c

  1 /*
  2  * drivers/i2c/busses/i2c-tegra.c
  3  *
  4  * Copyright (C) 2010 Google, Inc.
  5  * Author: Colin Cross <ccross@android.com>
  6  *
  7  * This software is licensed under the terms of the GNU General Public
  8  * License version 2, as published by the Free Software Foundation, and
  9  * may be copied, distributed, and modified under those terms.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  *
 16  */
 17 
 18 #include <linux/kernel.h>
 19 #include <linux/init.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/clk.h>
 22 #include <linux/err.h>
 23 #include <linux/i2c.h>
 24 #include <linux/io.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/delay.h>
 27 #include <linux/slab.h>
 28 #include <linux/of_device.h>
 29 #include <linux/module.h>
 30 #include <linux/reset.h>
 31 
 32 #include <asm/unaligned.h>
 33 
 34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
 35 #define BYTES_PER_FIFO_WORD 4
 36 
 37 #define I2C_CNFG                                0x000
 38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
 39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
 40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
 41 #define I2C_STATUS                              0x01C
 42 #define I2C_SL_CNFG                             0x020
 43 #define I2C_SL_CNFG_NACK                        (1<<1)
 44 #define I2C_SL_CNFG_NEWSL                       (1<<2)
 45 #define I2C_SL_ADDR1                            0x02c
 46 #define I2C_SL_ADDR2                            0x030
 47 #define I2C_TX_FIFO                             0x050
 48 #define I2C_RX_FIFO                             0x054
 49 #define I2C_PACKET_TRANSFER_STATUS              0x058
 50 #define I2C_FIFO_CONTROL                        0x05c
 51 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
 52 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
 53 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
 54 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
 55 #define I2C_FIFO_STATUS                         0x060
 56 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
 57 #define I2C_FIFO_STATUS_TX_SHIFT                4
 58 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
 59 #define I2C_FIFO_STATUS_RX_SHIFT                0
 60 #define I2C_INT_MASK                            0x064
 61 #define I2C_INT_STATUS                          0x068
 62 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
 63 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
 64 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
 65 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
 66 #define I2C_INT_NO_ACK                          (1<<3)
 67 #define I2C_INT_ARBITRATION_LOST                (1<<2)
 68 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
 69 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
 70 #define I2C_CLK_DIVISOR                         0x06c
 71 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
 72 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
 73 
 74 #define DVC_CTRL_REG1                           0x000
 75 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
 76 #define DVC_CTRL_REG2                           0x004
 77 #define DVC_CTRL_REG3                           0x008
 78 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
 79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
 80 #define DVC_STATUS                              0x00c
 81 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
 82 
 83 #define I2C_ERR_NONE                            0x00
 84 #define I2C_ERR_NO_ACK                          0x01
 85 #define I2C_ERR_ARBITRATION_LOST                0x02
 86 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
 87 
 88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
 89 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
 90 #define PACKET_HEADER0_CONT_ID_SHIFT            12
 91 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
 92 
 93 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
 94 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
 95 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
 96 #define I2C_HEADER_READ                         (1<<19)
 97 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
 98 #define I2C_HEADER_IE_ENABLE                    (1<<17)
 99 #define I2C_HEADER_REPEAT_START                 (1<<16)
100 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
101 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
102 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
103 
104 #define I2C_CONFIG_LOAD                         0x08C
105 #define I2C_MSTR_CONFIG_LOAD                    (1 << 0)
106 #define I2C_SLV_CONFIG_LOAD                     (1 << 1)
107 #define I2C_TIMEOUT_CONFIG_LOAD                 (1 << 2)
108 
109 /*
110  * msg_end_type: The bus control which need to be send at end of transfer.
111  * @MSG_END_STOP: Send stop pulse at end of transfer.
112  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
113  * @MSG_END_CONTINUE: The following on message is coming and so do not send
114  *              stop or repeat start.
115  */
116 enum msg_end_type {
117         MSG_END_STOP,
118         MSG_END_REPEAT_START,
119         MSG_END_CONTINUE,
120 };
121 
122 /**
123  * struct tegra_i2c_hw_feature : Different HW support on Tegra
124  * @has_continue_xfer_support: Continue transfer supports.
125  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
126  *              complete interrupt per packet basis.
127  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
128  *              and earlier Socs has two clock sources i.e. div-clk and
129  *              fast-clk.
130  * @has_config_load_reg: Has the config load register to load the new
131  *              configuration.
132  * @clk_divisor_hs_mode: Clock divisor in HS mode.
133  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
134  *              applicable if there is no fast clock source i.e. single clock
135  *              source.
136  */
137 
138 struct tegra_i2c_hw_feature {
139         bool has_continue_xfer_support;
140         bool has_per_pkt_xfer_complete_irq;
141         bool has_single_clk_source;
142         bool has_config_load_reg;
143         int clk_divisor_hs_mode;
144         int clk_divisor_std_fast_mode;
145         u16 clk_divisor_fast_plus_mode;
146 };
147 
148 /**
149  * struct tegra_i2c_dev - per device i2c context
150  * @dev: device reference for power management
151  * @hw: Tegra i2c hw feature.
152  * @adapter: core i2c layer adapter information
153  * @div_clk: clock reference for div clock of i2c controller.
154  * @fast_clk: clock reference for fast clock of i2c controller.
155  * @base: ioremapped registers cookie
156  * @cont_id: i2c controller id, used for for packet header
157  * @irq: irq number of transfer complete interrupt
158  * @is_dvc: identifies the DVC i2c controller, has a different register layout
159  * @msg_complete: transfer completion notifier
160  * @msg_err: error code for completed message
161  * @msg_buf: pointer to current message data
162  * @msg_buf_remaining: size of unsent data in the message buffer
163  * @msg_read: identifies read transfers
164  * @bus_clk_rate: current i2c bus clock rate
165  * @is_suspended: prevents i2c controller accesses after suspend is called
166  */
167 struct tegra_i2c_dev {
168         struct device *dev;
169         const struct tegra_i2c_hw_feature *hw;
170         struct i2c_adapter adapter;
171         struct clk *div_clk;
172         struct clk *fast_clk;
173         struct reset_control *rst;
174         void __iomem *base;
175         int cont_id;
176         int irq;
177         bool irq_disabled;
178         int is_dvc;
179         struct completion msg_complete;
180         int msg_err;
181         u8 *msg_buf;
182         size_t msg_buf_remaining;
183         int msg_read;
184         u32 bus_clk_rate;
185         u16 clk_divisor_non_hs_mode;
186         bool is_suspended;
187 };
188 
189 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
190 {
191         writel(val, i2c_dev->base + reg);
192 }
193 
194 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
195 {
196         return readl(i2c_dev->base + reg);
197 }
198 
199 /*
200  * i2c_writel and i2c_readl will offset the register if necessary to talk
201  * to the I2C block inside the DVC block
202  */
203 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
204         unsigned long reg)
205 {
206         if (i2c_dev->is_dvc)
207                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
208         return reg;
209 }
210 
211 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
212         unsigned long reg)
213 {
214         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
215 
216         /* Read back register to make sure that register writes completed */
217         if (reg != I2C_TX_FIFO)
218                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
219 }
220 
221 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
222 {
223         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
224 }
225 
226 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
227         unsigned long reg, int len)
228 {
229         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
230 }
231 
232 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
233         unsigned long reg, int len)
234 {
235         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
236 }
237 
238 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
239 {
240         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
241         int_mask &= ~mask;
242         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
243 }
244 
245 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
246 {
247         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
248         int_mask |= mask;
249         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
250 }
251 
252 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
253 {
254         unsigned long timeout = jiffies + HZ;
255         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
256         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
257         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
258 
259         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
260                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
261                 if (time_after(jiffies, timeout)) {
262                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
263                         return -ETIMEDOUT;
264                 }
265                 msleep(1);
266         }
267         return 0;
268 }
269 
270 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
271 {
272         u32 val;
273         int rx_fifo_avail;
274         u8 *buf = i2c_dev->msg_buf;
275         size_t buf_remaining = i2c_dev->msg_buf_remaining;
276         int words_to_transfer;
277 
278         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
279         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
280                 I2C_FIFO_STATUS_RX_SHIFT;
281 
282         /* Rounds down to not include partial word at the end of buf */
283         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
284         if (words_to_transfer > rx_fifo_avail)
285                 words_to_transfer = rx_fifo_avail;
286 
287         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
288 
289         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
290         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
291         rx_fifo_avail -= words_to_transfer;
292 
293         /*
294          * If there is a partial word at the end of buf, handle it manually to
295          * prevent overwriting past the end of buf
296          */
297         if (rx_fifo_avail > 0 && buf_remaining > 0) {
298                 BUG_ON(buf_remaining > 3);
299                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
300                 val = cpu_to_le32(val);
301                 memcpy(buf, &val, buf_remaining);
302                 buf_remaining = 0;
303                 rx_fifo_avail--;
304         }
305 
306         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
307         i2c_dev->msg_buf_remaining = buf_remaining;
308         i2c_dev->msg_buf = buf;
309         return 0;
310 }
311 
312 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
313 {
314         u32 val;
315         int tx_fifo_avail;
316         u8 *buf = i2c_dev->msg_buf;
317         size_t buf_remaining = i2c_dev->msg_buf_remaining;
318         int words_to_transfer;
319 
320         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
321         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
322                 I2C_FIFO_STATUS_TX_SHIFT;
323 
324         /* Rounds down to not include partial word at the end of buf */
325         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
326 
327         /* It's very common to have < 4 bytes, so optimize that case. */
328         if (words_to_transfer) {
329                 if (words_to_transfer > tx_fifo_avail)
330                         words_to_transfer = tx_fifo_avail;
331 
332                 /*
333                  * Update state before writing to FIFO.  If this casues us
334                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
335                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
336                  * not maskable).  We need to make sure that the isr sees
337                  * buf_remaining as 0 and doesn't call us back re-entrantly.
338                  */
339                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
340                 tx_fifo_avail -= words_to_transfer;
341                 i2c_dev->msg_buf_remaining = buf_remaining;
342                 i2c_dev->msg_buf = buf +
343                         words_to_transfer * BYTES_PER_FIFO_WORD;
344                 barrier();
345 
346                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
347 
348                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
349         }
350 
351         /*
352          * If there is a partial word at the end of buf, handle it manually to
353          * prevent reading past the end of buf, which could cross a page
354          * boundary and fault.
355          */
356         if (tx_fifo_avail > 0 && buf_remaining > 0) {
357                 BUG_ON(buf_remaining > 3);
358                 memcpy(&val, buf, buf_remaining);
359                 val = le32_to_cpu(val);
360 
361                 /* Again update before writing to FIFO to make sure isr sees. */
362                 i2c_dev->msg_buf_remaining = 0;
363                 i2c_dev->msg_buf = NULL;
364                 barrier();
365 
366                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
367         }
368 
369         return 0;
370 }
371 
372 /*
373  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
374  * block.  This block is identical to the rest of the I2C blocks, except that
375  * it only supports master mode, it has registers moved around, and it needs
376  * some extra init to get it into I2C mode.  The register moves are handled
377  * by i2c_readl and i2c_writel
378  */
379 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
380 {
381         u32 val = 0;
382         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
383         val |= DVC_CTRL_REG3_SW_PROG;
384         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
385         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
386 
387         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
388         val |= DVC_CTRL_REG1_INTR_EN;
389         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
390 }
391 
392 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
393 {
394         int ret;
395         if (!i2c_dev->hw->has_single_clk_source) {
396                 ret = clk_enable(i2c_dev->fast_clk);
397                 if (ret < 0) {
398                         dev_err(i2c_dev->dev,
399                                 "Enabling fast clk failed, err %d\n", ret);
400                         return ret;
401                 }
402         }
403         ret = clk_enable(i2c_dev->div_clk);
404         if (ret < 0) {
405                 dev_err(i2c_dev->dev,
406                         "Enabling div clk failed, err %d\n", ret);
407                 clk_disable(i2c_dev->fast_clk);
408         }
409         return ret;
410 }
411 
412 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
413 {
414         clk_disable(i2c_dev->div_clk);
415         if (!i2c_dev->hw->has_single_clk_source)
416                 clk_disable(i2c_dev->fast_clk);
417 }
418 
419 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
420 {
421         u32 val;
422         int err = 0;
423         u32 clk_divisor;
424         unsigned long timeout = jiffies + HZ;
425 
426         err = tegra_i2c_clock_enable(i2c_dev);
427         if (err < 0) {
428                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
429                 return err;
430         }
431 
432         reset_control_assert(i2c_dev->rst);
433         udelay(2);
434         reset_control_deassert(i2c_dev->rst);
435 
436         if (i2c_dev->is_dvc)
437                 tegra_dvc_init(i2c_dev);
438 
439         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
440                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
441         i2c_writel(i2c_dev, val, I2C_CNFG);
442         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
443 
444         /* Make sure clock divisor programmed correctly */
445         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
446         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
447                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
448         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
449 
450         if (!i2c_dev->is_dvc) {
451                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
452                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
453                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
454                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
455                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
456 
457         }
458 
459         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
460                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
461         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
462 
463         if (tegra_i2c_flush_fifos(i2c_dev))
464                 err = -ETIMEDOUT;
465 
466         if (i2c_dev->hw->has_config_load_reg) {
467                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
468                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
469                         if (time_after(jiffies, timeout)) {
470                                 dev_warn(i2c_dev->dev,
471                                         "timeout waiting for config load\n");
472                                 return -ETIMEDOUT;
473                         }
474                         msleep(1);
475                 }
476         }
477 
478         tegra_i2c_clock_disable(i2c_dev);
479 
480         if (i2c_dev->irq_disabled) {
481                 i2c_dev->irq_disabled = 0;
482                 enable_irq(i2c_dev->irq);
483         }
484 
485         return err;
486 }
487 
488 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
489 {
490         u32 status;
491         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
492         struct tegra_i2c_dev *i2c_dev = dev_id;
493 
494         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
495 
496         if (status == 0) {
497                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
498                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
499                          i2c_readl(i2c_dev, I2C_STATUS),
500                          i2c_readl(i2c_dev, I2C_CNFG));
501                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
502 
503                 if (!i2c_dev->irq_disabled) {
504                         disable_irq_nosync(i2c_dev->irq);
505                         i2c_dev->irq_disabled = 1;
506                 }
507                 goto err;
508         }
509 
510         if (unlikely(status & status_err)) {
511                 if (status & I2C_INT_NO_ACK)
512                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
513                 if (status & I2C_INT_ARBITRATION_LOST)
514                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
515                 goto err;
516         }
517 
518         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
519                 if (i2c_dev->msg_buf_remaining)
520                         tegra_i2c_empty_rx_fifo(i2c_dev);
521                 else
522                         BUG();
523         }
524 
525         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
526                 if (i2c_dev->msg_buf_remaining)
527                         tegra_i2c_fill_tx_fifo(i2c_dev);
528                 else
529                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
530         }
531 
532         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
533         if (i2c_dev->is_dvc)
534                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
535 
536         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
537                 BUG_ON(i2c_dev->msg_buf_remaining);
538                 complete(&i2c_dev->msg_complete);
539         }
540         return IRQ_HANDLED;
541 err:
542         /* An error occurred, mask all interrupts */
543         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
544                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
545                 I2C_INT_RX_FIFO_DATA_REQ);
546         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
547         if (i2c_dev->is_dvc)
548                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
549 
550         complete(&i2c_dev->msg_complete);
551         return IRQ_HANDLED;
552 }
553 
554 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
555         struct i2c_msg *msg, enum msg_end_type end_state)
556 {
557         u32 packet_header;
558         u32 int_mask;
559         unsigned long time_left;
560 
561         tegra_i2c_flush_fifos(i2c_dev);
562 
563         if (msg->len == 0)
564                 return -EINVAL;
565 
566         i2c_dev->msg_buf = msg->buf;
567         i2c_dev->msg_buf_remaining = msg->len;
568         i2c_dev->msg_err = I2C_ERR_NONE;
569         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
570         reinit_completion(&i2c_dev->msg_complete);
571 
572         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
573                         PACKET_HEADER0_PROTOCOL_I2C |
574                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
575                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
576         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
577 
578         packet_header = msg->len - 1;
579         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
580 
581         packet_header = I2C_HEADER_IE_ENABLE;
582         if (end_state == MSG_END_CONTINUE)
583                 packet_header |= I2C_HEADER_CONTINUE_XFER;
584         else if (end_state == MSG_END_REPEAT_START)
585                 packet_header |= I2C_HEADER_REPEAT_START;
586         if (msg->flags & I2C_M_TEN) {
587                 packet_header |= msg->addr;
588                 packet_header |= I2C_HEADER_10BIT_ADDR;
589         } else {
590                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
591         }
592         if (msg->flags & I2C_M_IGNORE_NAK)
593                 packet_header |= I2C_HEADER_CONT_ON_NAK;
594         if (msg->flags & I2C_M_RD)
595                 packet_header |= I2C_HEADER_READ;
596         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
597 
598         if (!(msg->flags & I2C_M_RD))
599                 tegra_i2c_fill_tx_fifo(i2c_dev);
600 
601         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
602         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
603                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
604         if (msg->flags & I2C_M_RD)
605                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
606         else if (i2c_dev->msg_buf_remaining)
607                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
608         tegra_i2c_unmask_irq(i2c_dev, int_mask);
609         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
610                 i2c_readl(i2c_dev, I2C_INT_MASK));
611 
612         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
613                                                 TEGRA_I2C_TIMEOUT);
614         tegra_i2c_mask_irq(i2c_dev, int_mask);
615 
616         if (time_left == 0) {
617                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
618 
619                 tegra_i2c_init(i2c_dev);
620                 return -ETIMEDOUT;
621         }
622 
623         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
624                 time_left, completion_done(&i2c_dev->msg_complete),
625                 i2c_dev->msg_err);
626 
627         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
628                 return 0;
629 
630         /*
631          * NACK interrupt is generated before the I2C controller generates the
632          * STOP condition on the bus. So wait for 2 clock periods before resetting
633          * the controller so that STOP condition has been delivered properly.
634          */
635         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
636                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
637 
638         tegra_i2c_init(i2c_dev);
639         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
640                 if (msg->flags & I2C_M_IGNORE_NAK)
641                         return 0;
642                 return -EREMOTEIO;
643         }
644 
645         return -EIO;
646 }
647 
648 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
649         int num)
650 {
651         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
652         int i;
653         int ret = 0;
654 
655         if (i2c_dev->is_suspended)
656                 return -EBUSY;
657 
658         ret = tegra_i2c_clock_enable(i2c_dev);
659         if (ret < 0) {
660                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
661                 return ret;
662         }
663 
664         for (i = 0; i < num; i++) {
665                 enum msg_end_type end_type = MSG_END_STOP;
666                 if (i < (num - 1)) {
667                         if (msgs[i + 1].flags & I2C_M_NOSTART)
668                                 end_type = MSG_END_CONTINUE;
669                         else
670                                 end_type = MSG_END_REPEAT_START;
671                 }
672                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
673                 if (ret)
674                         break;
675         }
676         tegra_i2c_clock_disable(i2c_dev);
677         return ret ?: i;
678 }
679 
680 static u32 tegra_i2c_func(struct i2c_adapter *adap)
681 {
682         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
683         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
684                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
685 
686         if (i2c_dev->hw->has_continue_xfer_support)
687                 ret |= I2C_FUNC_NOSTART;
688         return ret;
689 }
690 
691 static const struct i2c_algorithm tegra_i2c_algo = {
692         .master_xfer    = tegra_i2c_xfer,
693         .functionality  = tegra_i2c_func,
694 };
695 
696 /* payload size is only 12 bit */
697 static struct i2c_adapter_quirks tegra_i2c_quirks = {
698         .max_read_len = 4096,
699         .max_write_len = 4096,
700 };
701 
702 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
703         .has_continue_xfer_support = false,
704         .has_per_pkt_xfer_complete_irq = false,
705         .has_single_clk_source = false,
706         .clk_divisor_hs_mode = 3,
707         .clk_divisor_std_fast_mode = 0,
708         .clk_divisor_fast_plus_mode = 0,
709         .has_config_load_reg = false,
710 };
711 
712 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
713         .has_continue_xfer_support = true,
714         .has_per_pkt_xfer_complete_irq = false,
715         .has_single_clk_source = false,
716         .clk_divisor_hs_mode = 3,
717         .clk_divisor_std_fast_mode = 0,
718         .clk_divisor_fast_plus_mode = 0,
719         .has_config_load_reg = false,
720 };
721 
722 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
723         .has_continue_xfer_support = true,
724         .has_per_pkt_xfer_complete_irq = true,
725         .has_single_clk_source = true,
726         .clk_divisor_hs_mode = 1,
727         .clk_divisor_std_fast_mode = 0x19,
728         .clk_divisor_fast_plus_mode = 0x10,
729         .has_config_load_reg = false,
730 };
731 
732 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
733         .has_continue_xfer_support = true,
734         .has_per_pkt_xfer_complete_irq = true,
735         .has_single_clk_source = true,
736         .clk_divisor_hs_mode = 1,
737         .clk_divisor_std_fast_mode = 0x19,
738         .clk_divisor_fast_plus_mode = 0x10,
739         .has_config_load_reg = true,
740 };
741 
742 /* Match table for of_platform binding */
743 static const struct of_device_id tegra_i2c_of_match[] = {
744         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
745         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
746         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
747         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
748         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
749         {},
750 };
751 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
752 
753 static int tegra_i2c_probe(struct platform_device *pdev)
754 {
755         struct tegra_i2c_dev *i2c_dev;
756         struct resource *res;
757         struct clk *div_clk;
758         struct clk *fast_clk;
759         void __iomem *base;
760         int irq;
761         int ret = 0;
762         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
763 
764         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
765         base = devm_ioremap_resource(&pdev->dev, res);
766         if (IS_ERR(base))
767                 return PTR_ERR(base);
768 
769         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
770         if (!res) {
771                 dev_err(&pdev->dev, "no irq resource\n");
772                 return -EINVAL;
773         }
774         irq = res->start;
775 
776         div_clk = devm_clk_get(&pdev->dev, "div-clk");
777         if (IS_ERR(div_clk)) {
778                 dev_err(&pdev->dev, "missing controller clock");
779                 return PTR_ERR(div_clk);
780         }
781 
782         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
783         if (!i2c_dev)
784                 return -ENOMEM;
785 
786         i2c_dev->base = base;
787         i2c_dev->div_clk = div_clk;
788         i2c_dev->adapter.algo = &tegra_i2c_algo;
789         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
790         i2c_dev->irq = irq;
791         i2c_dev->cont_id = pdev->id;
792         i2c_dev->dev = &pdev->dev;
793 
794         i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
795         if (IS_ERR(i2c_dev->rst)) {
796                 dev_err(&pdev->dev, "missing controller reset");
797                 return PTR_ERR(i2c_dev->rst);
798         }
799 
800         ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
801                                         &i2c_dev->bus_clk_rate);
802         if (ret)
803                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
804 
805         i2c_dev->hw = &tegra20_i2c_hw;
806 
807         if (pdev->dev.of_node) {
808                 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
809                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
810                                                 "nvidia,tegra20-i2c-dvc");
811         } else if (pdev->id == 3) {
812                 i2c_dev->is_dvc = 1;
813         }
814         init_completion(&i2c_dev->msg_complete);
815 
816         if (!i2c_dev->hw->has_single_clk_source) {
817                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
818                 if (IS_ERR(fast_clk)) {
819                         dev_err(&pdev->dev, "missing fast clock");
820                         return PTR_ERR(fast_clk);
821                 }
822                 i2c_dev->fast_clk = fast_clk;
823         }
824 
825         platform_set_drvdata(pdev, i2c_dev);
826 
827         if (!i2c_dev->hw->has_single_clk_source) {
828                 ret = clk_prepare(i2c_dev->fast_clk);
829                 if (ret < 0) {
830                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
831                         return ret;
832                 }
833         }
834 
835         i2c_dev->clk_divisor_non_hs_mode =
836                         i2c_dev->hw->clk_divisor_std_fast_mode;
837         if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
838                 (i2c_dev->bus_clk_rate == 1000000))
839                 i2c_dev->clk_divisor_non_hs_mode =
840                         i2c_dev->hw->clk_divisor_fast_plus_mode;
841 
842         clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
843         ret = clk_set_rate(i2c_dev->div_clk,
844                            i2c_dev->bus_clk_rate * clk_multiplier);
845         if (ret) {
846                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
847                 goto unprepare_fast_clk;
848         }
849 
850         ret = clk_prepare(i2c_dev->div_clk);
851         if (ret < 0) {
852                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
853                 goto unprepare_fast_clk;
854         }
855 
856         ret = tegra_i2c_init(i2c_dev);
857         if (ret) {
858                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
859                 goto unprepare_div_clk;
860         }
861 
862         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
863                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
864         if (ret) {
865                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
866                 goto unprepare_div_clk;
867         }
868 
869         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
870         i2c_dev->adapter.owner = THIS_MODULE;
871         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
872         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
873                 sizeof(i2c_dev->adapter.name));
874         i2c_dev->adapter.dev.parent = &pdev->dev;
875         i2c_dev->adapter.nr = pdev->id;
876         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
877 
878         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
879         if (ret) {
880                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
881                 goto unprepare_div_clk;
882         }
883 
884         return 0;
885 
886 unprepare_div_clk:
887         clk_unprepare(i2c_dev->div_clk);
888 
889 unprepare_fast_clk:
890         if (!i2c_dev->hw->has_single_clk_source)
891                 clk_unprepare(i2c_dev->fast_clk);
892 
893         return ret;
894 }
895 
896 static int tegra_i2c_remove(struct platform_device *pdev)
897 {
898         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
899         i2c_del_adapter(&i2c_dev->adapter);
900 
901         clk_unprepare(i2c_dev->div_clk);
902         if (!i2c_dev->hw->has_single_clk_source)
903                 clk_unprepare(i2c_dev->fast_clk);
904 
905         return 0;
906 }
907 
908 #ifdef CONFIG_PM_SLEEP
909 static int tegra_i2c_suspend(struct device *dev)
910 {
911         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
912 
913         i2c_lock_adapter(&i2c_dev->adapter);
914         i2c_dev->is_suspended = true;
915         i2c_unlock_adapter(&i2c_dev->adapter);
916 
917         return 0;
918 }
919 
920 static int tegra_i2c_resume(struct device *dev)
921 {
922         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
923         int ret;
924 
925         i2c_lock_adapter(&i2c_dev->adapter);
926 
927         ret = tegra_i2c_init(i2c_dev);
928 
929         if (ret) {
930                 i2c_unlock_adapter(&i2c_dev->adapter);
931                 return ret;
932         }
933 
934         i2c_dev->is_suspended = false;
935 
936         i2c_unlock_adapter(&i2c_dev->adapter);
937 
938         return 0;
939 }
940 
941 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
942 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
943 #else
944 #define TEGRA_I2C_PM    NULL
945 #endif
946 
947 static struct platform_driver tegra_i2c_driver = {
948         .probe   = tegra_i2c_probe,
949         .remove  = tegra_i2c_remove,
950         .driver  = {
951                 .name  = "tegra-i2c",
952                 .of_match_table = tegra_i2c_of_match,
953                 .pm    = TEGRA_I2C_PM,
954         },
955 };
956 
957 static int __init tegra_i2c_init_driver(void)
958 {
959         return platform_driver_register(&tegra_i2c_driver);
960 }
961 
962 static void __exit tegra_i2c_exit_driver(void)
963 {
964         platform_driver_unregister(&tegra_i2c_driver);
965 }
966 
967 subsys_initcall(tegra_i2c_init_driver);
968 module_exit(tegra_i2c_exit_driver);
969 
970 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
971 MODULE_AUTHOR("Colin Cross");
972 MODULE_LICENSE("GPL v2");
973 

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