Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/i2c/busses/i2c-rcar.c

  1 /*
  2  * Driver for the Renesas RCar I2C unit
  3  *
  4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
  5  *
  6  * Copyright (C) 2012-14 Renesas Solutions Corp.
  7  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  8  *
  9  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 10  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 11  *
 12  * This file used out-of-tree driver i2c-rcar.c
 13  * Copyright (C) 2011-2012 Renesas Electronics Corporation
 14  *
 15  * This program is free software; you can redistribute it and/or modify
 16  * it under the terms of the GNU General Public License as published by
 17  * the Free Software Foundation; version 2 of the License.
 18  *
 19  * This program is distributed in the hope that it will be useful,
 20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 22  * GNU General Public License for more details.
 23  */
 24 #include <linux/clk.h>
 25 #include <linux/delay.h>
 26 #include <linux/err.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/i2c.h>
 30 #include <linux/i2c/i2c-rcar.h>
 31 #include <linux/kernel.h>
 32 #include <linux/module.h>
 33 #include <linux/of_device.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/pm_runtime.h>
 36 #include <linux/slab.h>
 37 #include <linux/spinlock.h>
 38 
 39 /* register offsets */
 40 #define ICSCR   0x00    /* slave ctrl */
 41 #define ICMCR   0x04    /* master ctrl */
 42 #define ICSSR   0x08    /* slave status */
 43 #define ICMSR   0x0C    /* master status */
 44 #define ICSIER  0x10    /* slave irq enable */
 45 #define ICMIER  0x14    /* master irq enable */
 46 #define ICCCR   0x18    /* clock dividers */
 47 #define ICSAR   0x1C    /* slave address */
 48 #define ICMAR   0x20    /* master address */
 49 #define ICRXTX  0x24    /* data port */
 50 
 51 /* ICMCR */
 52 #define MDBS    (1 << 7)        /* non-fifo mode switch */
 53 #define FSCL    (1 << 6)        /* override SCL pin */
 54 #define FSDA    (1 << 5)        /* override SDA pin */
 55 #define OBPC    (1 << 4)        /* override pins */
 56 #define MIE     (1 << 3)        /* master if enable */
 57 #define TSBE    (1 << 2)
 58 #define FSB     (1 << 1)        /* force stop bit */
 59 #define ESG     (1 << 0)        /* en startbit gen */
 60 
 61 /* ICMSR (also for ICMIE) */
 62 #define MNR     (1 << 6)        /* nack received */
 63 #define MAL     (1 << 5)        /* arbitration lost */
 64 #define MST     (1 << 4)        /* sent a stop */
 65 #define MDE     (1 << 3)
 66 #define MDT     (1 << 2)
 67 #define MDR     (1 << 1)
 68 #define MAT     (1 << 0)        /* slave addr xfer done */
 69 
 70 
 71 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
 72 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
 73 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
 74 
 75 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
 76 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
 77 #define RCAR_IRQ_STOP   (MST)
 78 
 79 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE) & 0xFF)
 80 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR) & 0xFF)
 81 
 82 #define ID_LAST_MSG     (1 << 0)
 83 #define ID_IOERROR      (1 << 1)
 84 #define ID_DONE         (1 << 2)
 85 #define ID_ARBLOST      (1 << 3)
 86 #define ID_NACK         (1 << 4)
 87 
 88 enum rcar_i2c_type {
 89         I2C_RCAR_GEN1,
 90         I2C_RCAR_GEN2,
 91 };
 92 
 93 struct rcar_i2c_priv {
 94         void __iomem *io;
 95         struct i2c_adapter adap;
 96         struct i2c_msg  *msg;
 97         struct clk *clk;
 98 
 99         spinlock_t lock;
100         wait_queue_head_t wait;
101 
102         int pos;
103         u32 icccr;
104         u32 flags;
105         enum rcar_i2c_type devtype;
106 };
107 
108 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
109 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
110 
111 #define rcar_i2c_flags_set(p, f)        ((p)->flags |= (f))
112 #define rcar_i2c_flags_has(p, f)        ((p)->flags & (f))
113 
114 #define LOOP_TIMEOUT    1024
115 
116 
117 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
118 {
119         writel(val, priv->io + reg);
120 }
121 
122 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
123 {
124         return readl(priv->io + reg);
125 }
126 
127 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
128 {
129         /*
130          * reset slave mode.
131          * slave mode is not used on this driver
132          */
133         rcar_i2c_write(priv, ICSIER, 0);
134         rcar_i2c_write(priv, ICSAR, 0);
135         rcar_i2c_write(priv, ICSCR, 0);
136         rcar_i2c_write(priv, ICSSR, 0);
137 
138         /* reset master mode */
139         rcar_i2c_write(priv, ICMIER, 0);
140         rcar_i2c_write(priv, ICMCR, 0);
141         rcar_i2c_write(priv, ICMSR, 0);
142         rcar_i2c_write(priv, ICMAR, 0);
143 }
144 
145 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
146 {
147         int i;
148 
149         for (i = 0; i < LOOP_TIMEOUT; i++) {
150                 /* make sure that bus is not busy */
151                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
152                         return 0;
153                 udelay(1);
154         }
155 
156         return -EBUSY;
157 }
158 
159 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
160                                     u32 bus_speed,
161                                     struct device *dev)
162 {
163         u32 scgd, cdf;
164         u32 round, ick;
165         u32 scl;
166         u32 cdf_width;
167         unsigned long rate;
168 
169         switch (priv->devtype) {
170         case I2C_RCAR_GEN1:
171                 cdf_width = 2;
172                 break;
173         case I2C_RCAR_GEN2:
174                 cdf_width = 3;
175                 break;
176         default:
177                 dev_err(dev, "device type error\n");
178                 return -EIO;
179         }
180 
181         /*
182          * calculate SCL clock
183          * see
184          *      ICCCR
185          *
186          * ick  = clkp / (1 + CDF)
187          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
188          *
189          * ick  : I2C internal clock < 20 MHz
190          * ticf : I2C SCL falling time  =  35 ns here
191          * tr   : I2C SCL rising  time  = 200 ns here
192          * intd : LSI internal delay    =  50 ns here
193          * clkp : peripheral_clk
194          * F[]  : integer up-valuation
195          */
196         rate = clk_get_rate(priv->clk);
197         cdf = rate / 20000000;
198         if (cdf >= 1U << cdf_width) {
199                 dev_err(dev, "Input clock %lu too high\n", rate);
200                 return -EIO;
201         }
202         ick = rate / (cdf + 1);
203 
204         /*
205          * it is impossible to calculate large scale
206          * number on u32. separate it
207          *
208          * F[(ticf + tr + intd) * ick]
209          *  = F[(35 + 200 + 50)ns * ick]
210          *  = F[285 * ick / 1000000000]
211          *  = F[(ick / 1000000) * 285 / 1000]
212          */
213         round = (ick + 500000) / 1000000 * 285;
214         round = (round + 500) / 1000;
215 
216         /*
217          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
218          *
219          * Calculation result (= SCL) should be less than
220          * bus_speed for hardware safety
221          *
222          * We could use something along the lines of
223          *      div = ick / (bus_speed + 1) + 1;
224          *      scgd = (div - 20 - round + 7) / 8;
225          *      scl = ick / (20 + (scgd * 8) + round);
226          * (not fully verified) but that would get pretty involved
227          */
228         for (scgd = 0; scgd < 0x40; scgd++) {
229                 scl = ick / (20 + (scgd * 8) + round);
230                 if (scl <= bus_speed)
231                         goto scgd_find;
232         }
233         dev_err(dev, "it is impossible to calculate best SCL\n");
234         return -EIO;
235 
236 scgd_find:
237         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
238                 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
239 
240         /*
241          * keep icccr value
242          */
243         priv->icccr = scgd << cdf_width | cdf;
244 
245         return 0;
246 }
247 
248 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
249 {
250         int read = !!rcar_i2c_is_recv(priv);
251 
252         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
253         rcar_i2c_write(priv, ICMSR, 0);
254         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
255         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
256 }
257 
258 /*
259  *              interrupt functions
260  */
261 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
262 {
263         struct i2c_msg *msg = priv->msg;
264 
265         /*
266          * FIXME
267          * sometimes, unknown interrupt happened.
268          * Do nothing
269          */
270         if (!(msr & MDE))
271                 return 0;
272 
273         /*
274          * If address transfer phase finished,
275          * goto data phase.
276          */
277         if (msr & MAT)
278                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
279 
280         if (priv->pos < msg->len) {
281                 /*
282                  * Prepare next data to ICRXTX register.
283                  * This data will go to _SHIFT_ register.
284                  *
285                  *    *
286                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
287                  */
288                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
289                 priv->pos++;
290 
291         } else {
292                 /*
293                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
294                  * It is on _SHIFT_ register, and will sent to I2C bus.
295                  *
296                  *                *
297                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
298                  */
299 
300                 if (priv->flags & ID_LAST_MSG)
301                         /*
302                          * If current msg is the _LAST_ msg,
303                          * prepare stop condition here.
304                          * ID_DONE will be set on STOP irq.
305                          */
306                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
307                 else
308                         /*
309                          * If current msg is _NOT_ last msg,
310                          * it doesn't call stop phase.
311                          * thus, there is no STOP irq.
312                          * return ID_DONE here.
313                          */
314                         return ID_DONE;
315         }
316 
317         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
318 
319         return 0;
320 }
321 
322 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
323 {
324         struct i2c_msg *msg = priv->msg;
325 
326         /*
327          * FIXME
328          * sometimes, unknown interrupt happened.
329          * Do nothing
330          */
331         if (!(msr & MDR))
332                 return 0;
333 
334         if (msr & MAT) {
335                 /*
336                  * Address transfer phase finished,
337                  * but, there is no data at this point.
338                  * Do nothing.
339                  */
340         } else if (priv->pos < msg->len) {
341                 /*
342                  * get received data
343                  */
344                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
345                 priv->pos++;
346         }
347 
348         /*
349          * If next received data is the _LAST_,
350          * go to STOP phase,
351          * otherwise, go to DATA phase.
352          */
353         if (priv->pos + 1 >= msg->len)
354                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
355         else
356                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
357 
358         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
359 
360         return 0;
361 }
362 
363 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
364 {
365         struct rcar_i2c_priv *priv = ptr;
366         irqreturn_t result = IRQ_HANDLED;
367         u32 msr;
368 
369         /*-------------- spin lock -----------------*/
370         spin_lock(&priv->lock);
371 
372         msr = rcar_i2c_read(priv, ICMSR);
373 
374         /* Only handle interrupts that are currently enabled */
375         msr &= rcar_i2c_read(priv, ICMIER);
376         if (!msr) {
377                 result = IRQ_NONE;
378                 goto exit;
379         }
380 
381         /* Arbitration lost */
382         if (msr & MAL) {
383                 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
384                 goto out;
385         }
386 
387         /* Nack */
388         if (msr & MNR) {
389                 /* go to stop phase */
390                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
391                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
392                 rcar_i2c_flags_set(priv, ID_NACK);
393                 goto out;
394         }
395 
396         /* Stop */
397         if (msr & MST) {
398                 rcar_i2c_flags_set(priv, ID_DONE);
399                 goto out;
400         }
401 
402         if (rcar_i2c_is_recv(priv))
403                 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
404         else
405                 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
406 
407 out:
408         if (rcar_i2c_flags_has(priv, ID_DONE)) {
409                 rcar_i2c_write(priv, ICMIER, 0);
410                 rcar_i2c_write(priv, ICMSR, 0);
411                 wake_up(&priv->wait);
412         }
413 
414 exit:
415         spin_unlock(&priv->lock);
416         /*-------------- spin unlock -----------------*/
417 
418         return result;
419 }
420 
421 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
422                                 struct i2c_msg *msgs,
423                                 int num)
424 {
425         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
426         struct device *dev = rcar_i2c_priv_to_dev(priv);
427         unsigned long flags;
428         int i, ret, timeout;
429 
430         pm_runtime_get_sync(dev);
431 
432         /*-------------- spin lock -----------------*/
433         spin_lock_irqsave(&priv->lock, flags);
434 
435         rcar_i2c_init(priv);
436         /* start clock */
437         rcar_i2c_write(priv, ICCCR, priv->icccr);
438 
439         spin_unlock_irqrestore(&priv->lock, flags);
440         /*-------------- spin unlock -----------------*/
441 
442         ret = rcar_i2c_bus_barrier(priv);
443         if (ret < 0)
444                 goto out;
445 
446         for (i = 0; i < num; i++) {
447                 /* This HW can't send STOP after address phase */
448                 if (msgs[i].len == 0) {
449                         ret = -EOPNOTSUPP;
450                         break;
451                 }
452 
453                 /*-------------- spin lock -----------------*/
454                 spin_lock_irqsave(&priv->lock, flags);
455 
456                 /* init each data */
457                 priv->msg       = &msgs[i];
458                 priv->pos       = 0;
459                 priv->flags     = 0;
460                 if (i == num - 1)
461                         rcar_i2c_flags_set(priv, ID_LAST_MSG);
462 
463                 rcar_i2c_prepare_msg(priv);
464 
465                 spin_unlock_irqrestore(&priv->lock, flags);
466                 /*-------------- spin unlock -----------------*/
467 
468                 timeout = wait_event_timeout(priv->wait,
469                                              rcar_i2c_flags_has(priv, ID_DONE),
470                                              5 * HZ);
471                 if (!timeout) {
472                         ret = -ETIMEDOUT;
473                         break;
474                 }
475 
476                 if (rcar_i2c_flags_has(priv, ID_NACK)) {
477                         ret = -ENXIO;
478                         break;
479                 }
480 
481                 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
482                         ret = -EAGAIN;
483                         break;
484                 }
485 
486                 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
487                         ret = -EIO;
488                         break;
489                 }
490 
491                 ret = i + 1; /* The number of transfer */
492         }
493 out:
494         pm_runtime_put(dev);
495 
496         if (ret < 0 && ret != -ENXIO)
497                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
498 
499         return ret;
500 }
501 
502 static u32 rcar_i2c_func(struct i2c_adapter *adap)
503 {
504         /* This HW can't do SMBUS_QUICK and NOSTART */
505         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
506 }
507 
508 static const struct i2c_algorithm rcar_i2c_algo = {
509         .master_xfer    = rcar_i2c_master_xfer,
510         .functionality  = rcar_i2c_func,
511 };
512 
513 static const struct of_device_id rcar_i2c_dt_ids[] = {
514         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
515         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
516         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
517         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
518         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
519         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
520         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
521         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
522         {},
523 };
524 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
525 
526 static int rcar_i2c_probe(struct platform_device *pdev)
527 {
528         struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
529         struct rcar_i2c_priv *priv;
530         struct i2c_adapter *adap;
531         struct resource *res;
532         struct device *dev = &pdev->dev;
533         u32 bus_speed;
534         int irq, ret;
535 
536         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
537         if (!priv)
538                 return -ENOMEM;
539 
540         priv->clk = devm_clk_get(dev, NULL);
541         if (IS_ERR(priv->clk)) {
542                 dev_err(dev, "cannot get clock\n");
543                 return PTR_ERR(priv->clk);
544         }
545 
546         bus_speed = 100000; /* default 100 kHz */
547         ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
548         if (ret < 0 && pdata && pdata->bus_speed)
549                 bus_speed = pdata->bus_speed;
550 
551         if (pdev->dev.of_node)
552                 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
553                                                       dev)->data;
554         else
555                 priv->devtype = platform_get_device_id(pdev)->driver_data;
556 
557         ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
558         if (ret < 0)
559                 return ret;
560 
561         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
562         priv->io = devm_ioremap_resource(dev, res);
563         if (IS_ERR(priv->io))
564                 return PTR_ERR(priv->io);
565 
566         irq = platform_get_irq(pdev, 0);
567         init_waitqueue_head(&priv->wait);
568         spin_lock_init(&priv->lock);
569 
570         adap = &priv->adap;
571         adap->nr = pdev->id;
572         adap->algo = &rcar_i2c_algo;
573         adap->class = I2C_CLASS_DEPRECATED;
574         adap->retries = 3;
575         adap->dev.parent = dev;
576         adap->dev.of_node = dev->of_node;
577         i2c_set_adapdata(adap, priv);
578         strlcpy(adap->name, pdev->name, sizeof(adap->name));
579 
580         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
581                                dev_name(dev), priv);
582         if (ret < 0) {
583                 dev_err(dev, "cannot get irq %d\n", irq);
584                 return ret;
585         }
586 
587         ret = i2c_add_numbered_adapter(adap);
588         if (ret < 0) {
589                 dev_err(dev, "reg adap failed: %d\n", ret);
590                 return ret;
591         }
592 
593         pm_runtime_enable(dev);
594         platform_set_drvdata(pdev, priv);
595 
596         dev_info(dev, "probed\n");
597 
598         return 0;
599 }
600 
601 static int rcar_i2c_remove(struct platform_device *pdev)
602 {
603         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
604         struct device *dev = &pdev->dev;
605 
606         i2c_del_adapter(&priv->adap);
607         pm_runtime_disable(dev);
608 
609         return 0;
610 }
611 
612 static struct platform_device_id rcar_i2c_id_table[] = {
613         { "i2c-rcar",           I2C_RCAR_GEN1 },
614         { "i2c-rcar_gen1",      I2C_RCAR_GEN1 },
615         { "i2c-rcar_gen2",      I2C_RCAR_GEN2 },
616         {},
617 };
618 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
619 
620 static struct platform_driver rcar_i2c_driver = {
621         .driver = {
622                 .name   = "i2c-rcar",
623                 .owner  = THIS_MODULE,
624                 .of_match_table = rcar_i2c_dt_ids,
625         },
626         .probe          = rcar_i2c_probe,
627         .remove         = rcar_i2c_remove,
628         .id_table       = rcar_i2c_id_table,
629 };
630 
631 module_platform_driver(rcar_i2c_driver);
632 
633 MODULE_LICENSE("GPL v2");
634 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
635 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
636 

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