Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/i2c/busses/i2c-rcar.c

  1 /*
  2  * Driver for the Renesas RCar I2C unit
  3  *
  4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
  5  *
  6  * Copyright (C) 2012-14 Renesas Solutions Corp.
  7  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  8  *
  9  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 10  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 11  *
 12  * This file used out-of-tree driver i2c-rcar.c
 13  * Copyright (C) 2011-2012 Renesas Electronics Corporation
 14  *
 15  * This program is free software; you can redistribute it and/or modify
 16  * it under the terms of the GNU General Public License as published by
 17  * the Free Software Foundation; version 2 of the License.
 18  *
 19  * This program is distributed in the hope that it will be useful,
 20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 22  * GNU General Public License for more details.
 23  */
 24 #include <linux/clk.h>
 25 #include <linux/delay.h>
 26 #include <linux/err.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/i2c.h>
 30 #include <linux/i2c/i2c-rcar.h>
 31 #include <linux/kernel.h>
 32 #include <linux/module.h>
 33 #include <linux/of_device.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/pm_runtime.h>
 36 #include <linux/slab.h>
 37 #include <linux/spinlock.h>
 38 
 39 /* register offsets */
 40 #define ICSCR   0x00    /* slave ctrl */
 41 #define ICMCR   0x04    /* master ctrl */
 42 #define ICSSR   0x08    /* slave status */
 43 #define ICMSR   0x0C    /* master status */
 44 #define ICSIER  0x10    /* slave irq enable */
 45 #define ICMIER  0x14    /* master irq enable */
 46 #define ICCCR   0x18    /* clock dividers */
 47 #define ICSAR   0x1C    /* slave address */
 48 #define ICMAR   0x20    /* master address */
 49 #define ICRXTX  0x24    /* data port */
 50 
 51 /* ICMCR */
 52 #define MDBS    (1 << 7)        /* non-fifo mode switch */
 53 #define FSCL    (1 << 6)        /* override SCL pin */
 54 #define FSDA    (1 << 5)        /* override SDA pin */
 55 #define OBPC    (1 << 4)        /* override pins */
 56 #define MIE     (1 << 3)        /* master if enable */
 57 #define TSBE    (1 << 2)
 58 #define FSB     (1 << 1)        /* force stop bit */
 59 #define ESG     (1 << 0)        /* en startbit gen */
 60 
 61 /* ICMSR (also for ICMIE) */
 62 #define MNR     (1 << 6)        /* nack received */
 63 #define MAL     (1 << 5)        /* arbitration lost */
 64 #define MST     (1 << 4)        /* sent a stop */
 65 #define MDE     (1 << 3)
 66 #define MDT     (1 << 2)
 67 #define MDR     (1 << 1)
 68 #define MAT     (1 << 0)        /* slave addr xfer done */
 69 
 70 
 71 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
 72 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
 73 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
 74 
 75 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
 76 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
 77 #define RCAR_IRQ_STOP   (MST)
 78 
 79 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE) & 0xFF)
 80 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR) & 0xFF)
 81 
 82 #define ID_LAST_MSG     (1 << 0)
 83 #define ID_IOERROR      (1 << 1)
 84 #define ID_DONE         (1 << 2)
 85 #define ID_ARBLOST      (1 << 3)
 86 #define ID_NACK         (1 << 4)
 87 
 88 enum rcar_i2c_type {
 89         I2C_RCAR_GEN1,
 90         I2C_RCAR_GEN2,
 91 };
 92 
 93 struct rcar_i2c_priv {
 94         void __iomem *io;
 95         struct i2c_adapter adap;
 96         struct i2c_msg  *msg;
 97         struct clk *clk;
 98 
 99         spinlock_t lock;
100         wait_queue_head_t wait;
101 
102         int pos;
103         u32 icccr;
104         u32 flags;
105         enum rcar_i2c_type devtype;
106 };
107 
108 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
109 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
110 
111 #define rcar_i2c_flags_set(p, f)        ((p)->flags |= (f))
112 #define rcar_i2c_flags_has(p, f)        ((p)->flags & (f))
113 
114 #define LOOP_TIMEOUT    1024
115 
116 
117 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
118 {
119         writel(val, priv->io + reg);
120 }
121 
122 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
123 {
124         return readl(priv->io + reg);
125 }
126 
127 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
128 {
129         /*
130          * reset slave mode.
131          * slave mode is not used on this driver
132          */
133         rcar_i2c_write(priv, ICSIER, 0);
134         rcar_i2c_write(priv, ICSAR, 0);
135         rcar_i2c_write(priv, ICSCR, 0);
136         rcar_i2c_write(priv, ICSSR, 0);
137 
138         /* reset master mode */
139         rcar_i2c_write(priv, ICMIER, 0);
140         rcar_i2c_write(priv, ICMCR, 0);
141         rcar_i2c_write(priv, ICMSR, 0);
142         rcar_i2c_write(priv, ICMAR, 0);
143 }
144 
145 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
146 {
147         int i;
148 
149         for (i = 0; i < LOOP_TIMEOUT; i++) {
150                 /* make sure that bus is not busy */
151                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
152                         return 0;
153                 udelay(1);
154         }
155 
156         return -EBUSY;
157 }
158 
159 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
160                                     u32 bus_speed,
161                                     struct device *dev)
162 {
163         u32 scgd, cdf;
164         u32 round, ick;
165         u32 scl;
166         u32 cdf_width;
167         unsigned long rate;
168 
169         switch (priv->devtype) {
170         case I2C_RCAR_GEN1:
171                 cdf_width = 2;
172                 break;
173         case I2C_RCAR_GEN2:
174                 cdf_width = 3;
175                 break;
176         default:
177                 dev_err(dev, "device type error\n");
178                 return -EIO;
179         }
180 
181         /*
182          * calculate SCL clock
183          * see
184          *      ICCCR
185          *
186          * ick  = clkp / (1 + CDF)
187          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
188          *
189          * ick  : I2C internal clock < 20 MHz
190          * ticf : I2C SCL falling time  =  35 ns here
191          * tr   : I2C SCL rising  time  = 200 ns here
192          * intd : LSI internal delay    =  50 ns here
193          * clkp : peripheral_clk
194          * F[]  : integer up-valuation
195          */
196         rate = clk_get_rate(priv->clk);
197         cdf = rate / 20000000;
198         if (cdf >= 1 << cdf_width) {
199                 dev_err(dev, "Input clock %lu too high\n", rate);
200                 return -EIO;
201         }
202         ick = rate / (cdf + 1);
203 
204         /*
205          * it is impossible to calculate large scale
206          * number on u32. separate it
207          *
208          * F[(ticf + tr + intd) * ick]
209          *  = F[(35 + 200 + 50)ns * ick]
210          *  = F[285 * ick / 1000000000]
211          *  = F[(ick / 1000000) * 285 / 1000]
212          */
213         round = (ick + 500000) / 1000000 * 285;
214         round = (round + 500) / 1000;
215 
216         /*
217          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
218          *
219          * Calculation result (= SCL) should be less than
220          * bus_speed for hardware safety
221          *
222          * We could use something along the lines of
223          *      div = ick / (bus_speed + 1) + 1;
224          *      scgd = (div - 20 - round + 7) / 8;
225          *      scl = ick / (20 + (scgd * 8) + round);
226          * (not fully verified) but that would get pretty involved
227          */
228         for (scgd = 0; scgd < 0x40; scgd++) {
229                 scl = ick / (20 + (scgd * 8) + round);
230                 if (scl <= bus_speed)
231                         goto scgd_find;
232         }
233         dev_err(dev, "it is impossible to calculate best SCL\n");
234         return -EIO;
235 
236 scgd_find:
237         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
238                 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
239 
240         /*
241          * keep icccr value
242          */
243         priv->icccr = scgd << cdf_width | cdf;
244 
245         return 0;
246 }
247 
248 static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
249 {
250         int read = !!rcar_i2c_is_recv(priv);
251 
252         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
253         rcar_i2c_write(priv, ICMSR, 0);
254         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
255         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
256 
257         return 0;
258 }
259 
260 /*
261  *              interrupt functions
262  */
263 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
264 {
265         struct i2c_msg *msg = priv->msg;
266 
267         /*
268          * FIXME
269          * sometimes, unknown interrupt happened.
270          * Do nothing
271          */
272         if (!(msr & MDE))
273                 return 0;
274 
275         /*
276          * If address transfer phase finished,
277          * goto data phase.
278          */
279         if (msr & MAT)
280                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
281 
282         if (priv->pos < msg->len) {
283                 /*
284                  * Prepare next data to ICRXTX register.
285                  * This data will go to _SHIFT_ register.
286                  *
287                  *    *
288                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
289                  */
290                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
291                 priv->pos++;
292 
293         } else {
294                 /*
295                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
296                  * It is on _SHIFT_ register, and will sent to I2C bus.
297                  *
298                  *                *
299                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
300                  */
301 
302                 if (priv->flags & ID_LAST_MSG)
303                         /*
304                          * If current msg is the _LAST_ msg,
305                          * prepare stop condition here.
306                          * ID_DONE will be set on STOP irq.
307                          */
308                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
309                 else
310                         /*
311                          * If current msg is _NOT_ last msg,
312                          * it doesn't call stop phase.
313                          * thus, there is no STOP irq.
314                          * return ID_DONE here.
315                          */
316                         return ID_DONE;
317         }
318 
319         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
320 
321         return 0;
322 }
323 
324 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
325 {
326         struct i2c_msg *msg = priv->msg;
327 
328         /*
329          * FIXME
330          * sometimes, unknown interrupt happened.
331          * Do nothing
332          */
333         if (!(msr & MDR))
334                 return 0;
335 
336         if (msr & MAT) {
337                 /*
338                  * Address transfer phase finished,
339                  * but, there is no data at this point.
340                  * Do nothing.
341                  */
342         } else if (priv->pos < msg->len) {
343                 /*
344                  * get received data
345                  */
346                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
347                 priv->pos++;
348         }
349 
350         /*
351          * If next received data is the _LAST_,
352          * go to STOP phase,
353          * otherwise, go to DATA phase.
354          */
355         if (priv->pos + 1 >= msg->len)
356                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
357         else
358                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
359 
360         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
361 
362         return 0;
363 }
364 
365 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
366 {
367         struct rcar_i2c_priv *priv = ptr;
368         u32 msr;
369 
370         /*-------------- spin lock -----------------*/
371         spin_lock(&priv->lock);
372 
373         msr = rcar_i2c_read(priv, ICMSR);
374 
375         /* Only handle interrupts that are currently enabled */
376         msr &= rcar_i2c_read(priv, ICMIER);
377 
378         /* Arbitration lost */
379         if (msr & MAL) {
380                 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
381                 goto out;
382         }
383 
384         /* Nack */
385         if (msr & MNR) {
386                 /* go to stop phase */
387                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
388                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
389                 rcar_i2c_flags_set(priv, ID_NACK);
390                 goto out;
391         }
392 
393         /* Stop */
394         if (msr & MST) {
395                 rcar_i2c_flags_set(priv, ID_DONE);
396                 goto out;
397         }
398 
399         if (rcar_i2c_is_recv(priv))
400                 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
401         else
402                 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
403 
404 out:
405         if (rcar_i2c_flags_has(priv, ID_DONE)) {
406                 rcar_i2c_write(priv, ICMIER, 0);
407                 rcar_i2c_write(priv, ICMSR, 0);
408                 wake_up(&priv->wait);
409         }
410 
411         spin_unlock(&priv->lock);
412         /*-------------- spin unlock -----------------*/
413 
414         return IRQ_HANDLED;
415 }
416 
417 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
418                                 struct i2c_msg *msgs,
419                                 int num)
420 {
421         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
422         struct device *dev = rcar_i2c_priv_to_dev(priv);
423         unsigned long flags;
424         int i, ret, timeout;
425 
426         pm_runtime_get_sync(dev);
427 
428         /*-------------- spin lock -----------------*/
429         spin_lock_irqsave(&priv->lock, flags);
430 
431         rcar_i2c_init(priv);
432         /* start clock */
433         rcar_i2c_write(priv, ICCCR, priv->icccr);
434 
435         spin_unlock_irqrestore(&priv->lock, flags);
436         /*-------------- spin unlock -----------------*/
437 
438         ret = rcar_i2c_bus_barrier(priv);
439         if (ret < 0)
440                 goto out;
441 
442         for (i = 0; i < num; i++) {
443                 /* This HW can't send STOP after address phase */
444                 if (msgs[i].len == 0) {
445                         ret = -EOPNOTSUPP;
446                         break;
447                 }
448 
449                 /*-------------- spin lock -----------------*/
450                 spin_lock_irqsave(&priv->lock, flags);
451 
452                 /* init each data */
453                 priv->msg       = &msgs[i];
454                 priv->pos       = 0;
455                 priv->flags     = 0;
456                 if (priv->msg == &msgs[num - 1])
457                         rcar_i2c_flags_set(priv, ID_LAST_MSG);
458 
459                 ret = rcar_i2c_prepare_msg(priv);
460 
461                 spin_unlock_irqrestore(&priv->lock, flags);
462                 /*-------------- spin unlock -----------------*/
463 
464                 if (ret < 0)
465                         break;
466 
467                 timeout = wait_event_timeout(priv->wait,
468                                              rcar_i2c_flags_has(priv, ID_DONE),
469                                              5 * HZ);
470                 if (!timeout) {
471                         ret = -ETIMEDOUT;
472                         break;
473                 }
474 
475                 if (rcar_i2c_flags_has(priv, ID_NACK)) {
476                         ret = -ENXIO;
477                         break;
478                 }
479 
480                 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
481                         ret = -EAGAIN;
482                         break;
483                 }
484 
485                 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
486                         ret = -EIO;
487                         break;
488                 }
489 
490                 ret = i + 1; /* The number of transfer */
491         }
492 out:
493         pm_runtime_put(dev);
494 
495         if (ret < 0 && ret != -ENXIO)
496                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
497 
498         return ret;
499 }
500 
501 static u32 rcar_i2c_func(struct i2c_adapter *adap)
502 {
503         /* This HW can't do SMBUS_QUICK and NOSTART */
504         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
505 }
506 
507 static const struct i2c_algorithm rcar_i2c_algo = {
508         .master_xfer    = rcar_i2c_master_xfer,
509         .functionality  = rcar_i2c_func,
510 };
511 
512 static const struct of_device_id rcar_i2c_dt_ids[] = {
513         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
514         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
515         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
516         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
517         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
518         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
519         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
520         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
521         {},
522 };
523 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
524 
525 static int rcar_i2c_probe(struct platform_device *pdev)
526 {
527         struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
528         struct rcar_i2c_priv *priv;
529         struct i2c_adapter *adap;
530         struct resource *res;
531         struct device *dev = &pdev->dev;
532         u32 bus_speed;
533         int irq, ret;
534 
535         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
536         if (!priv)
537                 return -ENOMEM;
538 
539         priv->clk = devm_clk_get(dev, NULL);
540         if (IS_ERR(priv->clk)) {
541                 dev_err(dev, "cannot get clock\n");
542                 return PTR_ERR(priv->clk);
543         }
544 
545         bus_speed = 100000; /* default 100 kHz */
546         ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
547         if (ret < 0 && pdata && pdata->bus_speed)
548                 bus_speed = pdata->bus_speed;
549 
550         if (pdev->dev.of_node)
551                 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
552                                                       dev)->data;
553         else
554                 priv->devtype = platform_get_device_id(pdev)->driver_data;
555 
556         ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
557         if (ret < 0)
558                 return ret;
559 
560         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561         priv->io = devm_ioremap_resource(dev, res);
562         if (IS_ERR(priv->io))
563                 return PTR_ERR(priv->io);
564 
565         irq = platform_get_irq(pdev, 0);
566         init_waitqueue_head(&priv->wait);
567         spin_lock_init(&priv->lock);
568 
569         adap = &priv->adap;
570         adap->nr = pdev->id;
571         adap->algo = &rcar_i2c_algo;
572         adap->class = I2C_CLASS_DEPRECATED;
573         adap->retries = 3;
574         adap->dev.parent = dev;
575         adap->dev.of_node = dev->of_node;
576         i2c_set_adapdata(adap, priv);
577         strlcpy(adap->name, pdev->name, sizeof(adap->name));
578 
579         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
580                                dev_name(dev), priv);
581         if (ret < 0) {
582                 dev_err(dev, "cannot get irq %d\n", irq);
583                 return ret;
584         }
585 
586         ret = i2c_add_numbered_adapter(adap);
587         if (ret < 0) {
588                 dev_err(dev, "reg adap failed: %d\n", ret);
589                 return ret;
590         }
591 
592         pm_runtime_enable(dev);
593         platform_set_drvdata(pdev, priv);
594 
595         dev_info(dev, "probed\n");
596 
597         return 0;
598 }
599 
600 static int rcar_i2c_remove(struct platform_device *pdev)
601 {
602         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
603         struct device *dev = &pdev->dev;
604 
605         i2c_del_adapter(&priv->adap);
606         pm_runtime_disable(dev);
607 
608         return 0;
609 }
610 
611 static struct platform_device_id rcar_i2c_id_table[] = {
612         { "i2c-rcar",           I2C_RCAR_GEN1 },
613         { "i2c-rcar_gen1",      I2C_RCAR_GEN1 },
614         { "i2c-rcar_gen2",      I2C_RCAR_GEN2 },
615         {},
616 };
617 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
618 
619 static struct platform_driver rcar_i2c_driver = {
620         .driver = {
621                 .name   = "i2c-rcar",
622                 .owner  = THIS_MODULE,
623                 .of_match_table = rcar_i2c_dt_ids,
624         },
625         .probe          = rcar_i2c_probe,
626         .remove         = rcar_i2c_remove,
627         .id_table       = rcar_i2c_id_table,
628 };
629 
630 module_platform_driver(rcar_i2c_driver);
631 
632 MODULE_LICENSE("GPL v2");
633 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
634 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
635 

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