Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/i2c/busses/i2c-rcar.c

  1 /*
  2  * Driver for the Renesas RCar I2C unit
  3  *
  4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
  5  *
  6  * Copyright (C) 2012-14 Renesas Solutions Corp.
  7  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  8  *
  9  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 10  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 11  *
 12  * This file used out-of-tree driver i2c-rcar.c
 13  * Copyright (C) 2011-2012 Renesas Electronics Corporation
 14  *
 15  * This program is free software; you can redistribute it and/or modify
 16  * it under the terms of the GNU General Public License as published by
 17  * the Free Software Foundation; version 2 of the License.
 18  *
 19  * This program is distributed in the hope that it will be useful,
 20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 22  * GNU General Public License for more details.
 23  */
 24 #include <linux/clk.h>
 25 #include <linux/delay.h>
 26 #include <linux/err.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/i2c.h>
 30 #include <linux/i2c/i2c-rcar.h>
 31 #include <linux/kernel.h>
 32 #include <linux/module.h>
 33 #include <linux/of_device.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/pm_runtime.h>
 36 #include <linux/slab.h>
 37 #include <linux/spinlock.h>
 38 
 39 /* register offsets */
 40 #define ICSCR   0x00    /* slave ctrl */
 41 #define ICMCR   0x04    /* master ctrl */
 42 #define ICSSR   0x08    /* slave status */
 43 #define ICMSR   0x0C    /* master status */
 44 #define ICSIER  0x10    /* slave irq enable */
 45 #define ICMIER  0x14    /* master irq enable */
 46 #define ICCCR   0x18    /* clock dividers */
 47 #define ICSAR   0x1C    /* slave address */
 48 #define ICMAR   0x20    /* master address */
 49 #define ICRXTX  0x24    /* data port */
 50 
 51 /* ICSCR */
 52 #define SDBS    (1 << 3)        /* slave data buffer select */
 53 #define SIE     (1 << 2)        /* slave interface enable */
 54 #define GCAE    (1 << 1)        /* general call address enable */
 55 #define FNA     (1 << 0)        /* forced non acknowledgment */
 56 
 57 /* ICMCR */
 58 #define MDBS    (1 << 7)        /* non-fifo mode switch */
 59 #define FSCL    (1 << 6)        /* override SCL pin */
 60 #define FSDA    (1 << 5)        /* override SDA pin */
 61 #define OBPC    (1 << 4)        /* override pins */
 62 #define MIE     (1 << 3)        /* master if enable */
 63 #define TSBE    (1 << 2)
 64 #define FSB     (1 << 1)        /* force stop bit */
 65 #define ESG     (1 << 0)        /* en startbit gen */
 66 
 67 /* ICSSR (also for ICSIER) */
 68 #define GCAR    (1 << 6)        /* general call received */
 69 #define STM     (1 << 5)        /* slave transmit mode */
 70 #define SSR     (1 << 4)        /* stop received */
 71 #define SDE     (1 << 3)        /* slave data empty */
 72 #define SDT     (1 << 2)        /* slave data transmitted */
 73 #define SDR     (1 << 1)        /* slave data received */
 74 #define SAR     (1 << 0)        /* slave addr received */
 75 
 76 /* ICMSR (also for ICMIE) */
 77 #define MNR     (1 << 6)        /* nack received */
 78 #define MAL     (1 << 5)        /* arbitration lost */
 79 #define MST     (1 << 4)        /* sent a stop */
 80 #define MDE     (1 << 3)
 81 #define MDT     (1 << 2)
 82 #define MDR     (1 << 1)
 83 #define MAT     (1 << 0)        /* slave addr xfer done */
 84 
 85 
 86 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
 87 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
 88 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
 89 
 90 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
 91 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
 92 #define RCAR_IRQ_STOP   (MST)
 93 
 94 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE) & 0xFF)
 95 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR) & 0xFF)
 96 
 97 #define ID_LAST_MSG     (1 << 0)
 98 #define ID_IOERROR      (1 << 1)
 99 #define ID_DONE         (1 << 2)
100 #define ID_ARBLOST      (1 << 3)
101 #define ID_NACK         (1 << 4)
102 
103 enum rcar_i2c_type {
104         I2C_RCAR_GEN1,
105         I2C_RCAR_GEN2,
106 };
107 
108 struct rcar_i2c_priv {
109         void __iomem *io;
110         struct i2c_adapter adap;
111         struct i2c_msg  *msg;
112         struct clk *clk;
113 
114         spinlock_t lock;
115         wait_queue_head_t wait;
116 
117         int pos;
118         u32 icccr;
119         u32 flags;
120         enum rcar_i2c_type devtype;
121         struct i2c_client *slave;
122 };
123 
124 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
125 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
126 
127 #define rcar_i2c_flags_set(p, f)        ((p)->flags |= (f))
128 #define rcar_i2c_flags_has(p, f)        ((p)->flags & (f))
129 
130 #define LOOP_TIMEOUT    1024
131 
132 
133 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
134 {
135         writel(val, priv->io + reg);
136 }
137 
138 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
139 {
140         return readl(priv->io + reg);
141 }
142 
143 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
144 {
145         /* reset master mode */
146         rcar_i2c_write(priv, ICMIER, 0);
147         rcar_i2c_write(priv, ICMCR, 0);
148         rcar_i2c_write(priv, ICMSR, 0);
149         rcar_i2c_write(priv, ICMAR, 0);
150 }
151 
152 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
153 {
154         int i;
155 
156         for (i = 0; i < LOOP_TIMEOUT; i++) {
157                 /* make sure that bus is not busy */
158                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
159                         return 0;
160                 udelay(1);
161         }
162 
163         return -EBUSY;
164 }
165 
166 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
167                                     u32 bus_speed,
168                                     struct device *dev)
169 {
170         u32 scgd, cdf;
171         u32 round, ick;
172         u32 scl;
173         u32 cdf_width;
174         unsigned long rate;
175 
176         switch (priv->devtype) {
177         case I2C_RCAR_GEN1:
178                 cdf_width = 2;
179                 break;
180         case I2C_RCAR_GEN2:
181                 cdf_width = 3;
182                 break;
183         default:
184                 dev_err(dev, "device type error\n");
185                 return -EIO;
186         }
187 
188         /*
189          * calculate SCL clock
190          * see
191          *      ICCCR
192          *
193          * ick  = clkp / (1 + CDF)
194          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
195          *
196          * ick  : I2C internal clock < 20 MHz
197          * ticf : I2C SCL falling time  =  35 ns here
198          * tr   : I2C SCL rising  time  = 200 ns here
199          * intd : LSI internal delay    =  50 ns here
200          * clkp : peripheral_clk
201          * F[]  : integer up-valuation
202          */
203         rate = clk_get_rate(priv->clk);
204         cdf = rate / 20000000;
205         if (cdf >= 1U << cdf_width) {
206                 dev_err(dev, "Input clock %lu too high\n", rate);
207                 return -EIO;
208         }
209         ick = rate / (cdf + 1);
210 
211         /*
212          * it is impossible to calculate large scale
213          * number on u32. separate it
214          *
215          * F[(ticf + tr + intd) * ick]
216          *  = F[(35 + 200 + 50)ns * ick]
217          *  = F[285 * ick / 1000000000]
218          *  = F[(ick / 1000000) * 285 / 1000]
219          */
220         round = (ick + 500000) / 1000000 * 285;
221         round = (round + 500) / 1000;
222 
223         /*
224          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
225          *
226          * Calculation result (= SCL) should be less than
227          * bus_speed for hardware safety
228          *
229          * We could use something along the lines of
230          *      div = ick / (bus_speed + 1) + 1;
231          *      scgd = (div - 20 - round + 7) / 8;
232          *      scl = ick / (20 + (scgd * 8) + round);
233          * (not fully verified) but that would get pretty involved
234          */
235         for (scgd = 0; scgd < 0x40; scgd++) {
236                 scl = ick / (20 + (scgd * 8) + round);
237                 if (scl <= bus_speed)
238                         goto scgd_find;
239         }
240         dev_err(dev, "it is impossible to calculate best SCL\n");
241         return -EIO;
242 
243 scgd_find:
244         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
245                 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
246 
247         /*
248          * keep icccr value
249          */
250         priv->icccr = scgd << cdf_width | cdf;
251 
252         return 0;
253 }
254 
255 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
256 {
257         int read = !!rcar_i2c_is_recv(priv);
258 
259         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
260         rcar_i2c_write(priv, ICMSR, 0);
261         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
262         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
263 }
264 
265 /*
266  *              interrupt functions
267  */
268 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
269 {
270         struct i2c_msg *msg = priv->msg;
271 
272         /*
273          * FIXME
274          * sometimes, unknown interrupt happened.
275          * Do nothing
276          */
277         if (!(msr & MDE))
278                 return 0;
279 
280         /*
281          * If address transfer phase finished,
282          * goto data phase.
283          */
284         if (msr & MAT)
285                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
286 
287         if (priv->pos < msg->len) {
288                 /*
289                  * Prepare next data to ICRXTX register.
290                  * This data will go to _SHIFT_ register.
291                  *
292                  *    *
293                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
294                  */
295                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
296                 priv->pos++;
297 
298         } else {
299                 /*
300                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
301                  * It is on _SHIFT_ register, and will sent to I2C bus.
302                  *
303                  *                *
304                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
305                  */
306 
307                 if (priv->flags & ID_LAST_MSG)
308                         /*
309                          * If current msg is the _LAST_ msg,
310                          * prepare stop condition here.
311                          * ID_DONE will be set on STOP irq.
312                          */
313                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
314                 else
315                         /*
316                          * If current msg is _NOT_ last msg,
317                          * it doesn't call stop phase.
318                          * thus, there is no STOP irq.
319                          * return ID_DONE here.
320                          */
321                         return ID_DONE;
322         }
323 
324         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
325 
326         return 0;
327 }
328 
329 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
330 {
331         struct i2c_msg *msg = priv->msg;
332 
333         /*
334          * FIXME
335          * sometimes, unknown interrupt happened.
336          * Do nothing
337          */
338         if (!(msr & MDR))
339                 return 0;
340 
341         if (msr & MAT) {
342                 /*
343                  * Address transfer phase finished,
344                  * but, there is no data at this point.
345                  * Do nothing.
346                  */
347         } else if (priv->pos < msg->len) {
348                 /*
349                  * get received data
350                  */
351                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
352                 priv->pos++;
353         }
354 
355         /*
356          * If next received data is the _LAST_,
357          * go to STOP phase,
358          * otherwise, go to DATA phase.
359          */
360         if (priv->pos + 1 >= msg->len)
361                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
362         else
363                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
364 
365         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
366 
367         return 0;
368 }
369 
370 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
371 {
372         u32 ssr_raw, ssr_filtered;
373         u8 value;
374 
375         ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
376         ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
377 
378         if (!ssr_filtered)
379                 return false;
380 
381         /* address detected */
382         if (ssr_filtered & SAR) {
383                 /* read or write request */
384                 if (ssr_raw & STM) {
385                         i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
386                         rcar_i2c_write(priv, ICRXTX, value);
387                         rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
388                 } else {
389                         i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
390                         rcar_i2c_read(priv, ICRXTX);    /* dummy read */
391                         rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
392                 }
393 
394                 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
395         }
396 
397         /* master sent stop */
398         if (ssr_filtered & SSR) {
399                 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
400                 rcar_i2c_write(priv, ICSIER, SAR | SSR);
401                 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
402         }
403 
404         /* master wants to write to us */
405         if (ssr_filtered & SDR) {
406                 int ret;
407 
408                 value = rcar_i2c_read(priv, ICRXTX);
409                 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
410                 /* Send NACK in case of error */
411                 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
412                 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
413         }
414 
415         /* master wants to read from us */
416         if (ssr_filtered & SDE) {
417                 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
418                 rcar_i2c_write(priv, ICRXTX, value);
419                 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
420         }
421 
422         return true;
423 }
424 
425 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
426 {
427         struct rcar_i2c_priv *priv = ptr;
428         irqreturn_t result = IRQ_HANDLED;
429         u32 msr;
430 
431         /*-------------- spin lock -----------------*/
432         spin_lock(&priv->lock);
433 
434         if (rcar_i2c_slave_irq(priv))
435                 goto exit;
436 
437         msr = rcar_i2c_read(priv, ICMSR);
438 
439         /* Only handle interrupts that are currently enabled */
440         msr &= rcar_i2c_read(priv, ICMIER);
441         if (!msr) {
442                 result = IRQ_NONE;
443                 goto exit;
444         }
445 
446         /* Arbitration lost */
447         if (msr & MAL) {
448                 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
449                 goto out;
450         }
451 
452         /* Nack */
453         if (msr & MNR) {
454                 /* go to stop phase */
455                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
456                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
457                 rcar_i2c_flags_set(priv, ID_NACK);
458                 goto out;
459         }
460 
461         /* Stop */
462         if (msr & MST) {
463                 rcar_i2c_flags_set(priv, ID_DONE);
464                 goto out;
465         }
466 
467         if (rcar_i2c_is_recv(priv))
468                 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
469         else
470                 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
471 
472 out:
473         if (rcar_i2c_flags_has(priv, ID_DONE)) {
474                 rcar_i2c_write(priv, ICMIER, 0);
475                 rcar_i2c_write(priv, ICMSR, 0);
476                 wake_up(&priv->wait);
477         }
478 
479 exit:
480         spin_unlock(&priv->lock);
481         /*-------------- spin unlock -----------------*/
482 
483         return result;
484 }
485 
486 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
487                                 struct i2c_msg *msgs,
488                                 int num)
489 {
490         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
491         struct device *dev = rcar_i2c_priv_to_dev(priv);
492         unsigned long flags;
493         int i, ret, timeout;
494 
495         pm_runtime_get_sync(dev);
496 
497         /*-------------- spin lock -----------------*/
498         spin_lock_irqsave(&priv->lock, flags);
499 
500         rcar_i2c_init(priv);
501         /* start clock */
502         rcar_i2c_write(priv, ICCCR, priv->icccr);
503 
504         spin_unlock_irqrestore(&priv->lock, flags);
505         /*-------------- spin unlock -----------------*/
506 
507         ret = rcar_i2c_bus_barrier(priv);
508         if (ret < 0)
509                 goto out;
510 
511         for (i = 0; i < num; i++) {
512                 /* This HW can't send STOP after address phase */
513                 if (msgs[i].len == 0) {
514                         ret = -EOPNOTSUPP;
515                         break;
516                 }
517 
518                 /*-------------- spin lock -----------------*/
519                 spin_lock_irqsave(&priv->lock, flags);
520 
521                 /* init each data */
522                 priv->msg       = &msgs[i];
523                 priv->pos       = 0;
524                 priv->flags     = 0;
525                 if (i == num - 1)
526                         rcar_i2c_flags_set(priv, ID_LAST_MSG);
527 
528                 rcar_i2c_prepare_msg(priv);
529 
530                 spin_unlock_irqrestore(&priv->lock, flags);
531                 /*-------------- spin unlock -----------------*/
532 
533                 timeout = wait_event_timeout(priv->wait,
534                                              rcar_i2c_flags_has(priv, ID_DONE),
535                                              5 * HZ);
536                 if (!timeout) {
537                         ret = -ETIMEDOUT;
538                         break;
539                 }
540 
541                 if (rcar_i2c_flags_has(priv, ID_NACK)) {
542                         ret = -ENXIO;
543                         break;
544                 }
545 
546                 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
547                         ret = -EAGAIN;
548                         break;
549                 }
550 
551                 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
552                         ret = -EIO;
553                         break;
554                 }
555 
556                 ret = i + 1; /* The number of transfer */
557         }
558 out:
559         pm_runtime_put(dev);
560 
561         if (ret < 0 && ret != -ENXIO)
562                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
563 
564         return ret;
565 }
566 
567 static int rcar_reg_slave(struct i2c_client *slave)
568 {
569         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
570 
571         if (priv->slave)
572                 return -EBUSY;
573 
574         if (slave->flags & I2C_CLIENT_TEN)
575                 return -EAFNOSUPPORT;
576 
577         pm_runtime_forbid(rcar_i2c_priv_to_dev(priv));
578 
579         priv->slave = slave;
580         rcar_i2c_write(priv, ICSAR, slave->addr);
581         rcar_i2c_write(priv, ICSSR, 0);
582         rcar_i2c_write(priv, ICSIER, SAR | SSR);
583         rcar_i2c_write(priv, ICSCR, SIE | SDBS);
584 
585         return 0;
586 }
587 
588 static int rcar_unreg_slave(struct i2c_client *slave)
589 {
590         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
591 
592         WARN_ON(!priv->slave);
593 
594         rcar_i2c_write(priv, ICSIER, 0);
595         rcar_i2c_write(priv, ICSCR, 0);
596 
597         priv->slave = NULL;
598 
599         pm_runtime_allow(rcar_i2c_priv_to_dev(priv));
600 
601         return 0;
602 }
603 
604 static u32 rcar_i2c_func(struct i2c_adapter *adap)
605 {
606         /* This HW can't do SMBUS_QUICK and NOSTART */
607         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
608 }
609 
610 static const struct i2c_algorithm rcar_i2c_algo = {
611         .master_xfer    = rcar_i2c_master_xfer,
612         .functionality  = rcar_i2c_func,
613         .reg_slave      = rcar_reg_slave,
614         .unreg_slave    = rcar_unreg_slave,
615 };
616 
617 static const struct of_device_id rcar_i2c_dt_ids[] = {
618         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
619         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
620         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
621         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
622         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
623         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
624         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
625         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
626         {},
627 };
628 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
629 
630 static int rcar_i2c_probe(struct platform_device *pdev)
631 {
632         struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
633         struct rcar_i2c_priv *priv;
634         struct i2c_adapter *adap;
635         struct resource *res;
636         struct device *dev = &pdev->dev;
637         u32 bus_speed;
638         int irq, ret;
639 
640         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
641         if (!priv)
642                 return -ENOMEM;
643 
644         priv->clk = devm_clk_get(dev, NULL);
645         if (IS_ERR(priv->clk)) {
646                 dev_err(dev, "cannot get clock\n");
647                 return PTR_ERR(priv->clk);
648         }
649 
650         bus_speed = 100000; /* default 100 kHz */
651         ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
652         if (ret < 0 && pdata && pdata->bus_speed)
653                 bus_speed = pdata->bus_speed;
654 
655         if (pdev->dev.of_node)
656                 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
657                                                       dev)->data;
658         else
659                 priv->devtype = platform_get_device_id(pdev)->driver_data;
660 
661         ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
662         if (ret < 0)
663                 return ret;
664 
665         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666         priv->io = devm_ioremap_resource(dev, res);
667         if (IS_ERR(priv->io))
668                 return PTR_ERR(priv->io);
669 
670         irq = platform_get_irq(pdev, 0);
671         init_waitqueue_head(&priv->wait);
672         spin_lock_init(&priv->lock);
673 
674         adap = &priv->adap;
675         adap->nr = pdev->id;
676         adap->algo = &rcar_i2c_algo;
677         adap->class = I2C_CLASS_DEPRECATED;
678         adap->retries = 3;
679         adap->dev.parent = dev;
680         adap->dev.of_node = dev->of_node;
681         i2c_set_adapdata(adap, priv);
682         strlcpy(adap->name, pdev->name, sizeof(adap->name));
683 
684         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
685                                dev_name(dev), priv);
686         if (ret < 0) {
687                 dev_err(dev, "cannot get irq %d\n", irq);
688                 return ret;
689         }
690 
691         ret = i2c_add_numbered_adapter(adap);
692         if (ret < 0) {
693                 dev_err(dev, "reg adap failed: %d\n", ret);
694                 return ret;
695         }
696 
697         pm_runtime_enable(dev);
698         platform_set_drvdata(pdev, priv);
699 
700         dev_info(dev, "probed\n");
701 
702         return 0;
703 }
704 
705 static int rcar_i2c_remove(struct platform_device *pdev)
706 {
707         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
708         struct device *dev = &pdev->dev;
709 
710         i2c_del_adapter(&priv->adap);
711         pm_runtime_disable(dev);
712 
713         return 0;
714 }
715 
716 static struct platform_device_id rcar_i2c_id_table[] = {
717         { "i2c-rcar",           I2C_RCAR_GEN1 },
718         { "i2c-rcar_gen1",      I2C_RCAR_GEN1 },
719         { "i2c-rcar_gen2",      I2C_RCAR_GEN2 },
720         {},
721 };
722 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
723 
724 static struct platform_driver rcar_i2c_driver = {
725         .driver = {
726                 .name   = "i2c-rcar",
727                 .of_match_table = rcar_i2c_dt_ids,
728         },
729         .probe          = rcar_i2c_probe,
730         .remove         = rcar_i2c_remove,
731         .id_table       = rcar_i2c_id_table,
732 };
733 
734 module_platform_driver(rcar_i2c_driver);
735 
736 MODULE_LICENSE("GPL v2");
737 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
738 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
739 

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