Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/i2c/busses/i2c-rcar.c

  1 /*
  2  * Driver for the Renesas RCar I2C unit
  3  *
  4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
  5  *
  6  * Copyright (C) 2012-14 Renesas Solutions Corp.
  7  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  8  *
  9  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
 10  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
 11  *
 12  * This file used out-of-tree driver i2c-rcar.c
 13  * Copyright (C) 2011-2012 Renesas Electronics Corporation
 14  *
 15  * This program is free software; you can redistribute it and/or modify
 16  * it under the terms of the GNU General Public License as published by
 17  * the Free Software Foundation; version 2 of the License.
 18  *
 19  * This program is distributed in the hope that it will be useful,
 20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 22  * GNU General Public License for more details.
 23  */
 24 #include <linux/clk.h>
 25 #include <linux/delay.h>
 26 #include <linux/err.h>
 27 #include <linux/interrupt.h>
 28 #include <linux/io.h>
 29 #include <linux/i2c.h>
 30 #include <linux/i2c/i2c-rcar.h>
 31 #include <linux/kernel.h>
 32 #include <linux/module.h>
 33 #include <linux/of_device.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/pm_runtime.h>
 36 #include <linux/slab.h>
 37 
 38 /* register offsets */
 39 #define ICSCR   0x00    /* slave ctrl */
 40 #define ICMCR   0x04    /* master ctrl */
 41 #define ICSSR   0x08    /* slave status */
 42 #define ICMSR   0x0C    /* master status */
 43 #define ICSIER  0x10    /* slave irq enable */
 44 #define ICMIER  0x14    /* master irq enable */
 45 #define ICCCR   0x18    /* clock dividers */
 46 #define ICSAR   0x1C    /* slave address */
 47 #define ICMAR   0x20    /* master address */
 48 #define ICRXTX  0x24    /* data port */
 49 
 50 /* ICMCR */
 51 #define MDBS    (1 << 7)        /* non-fifo mode switch */
 52 #define FSCL    (1 << 6)        /* override SCL pin */
 53 #define FSDA    (1 << 5)        /* override SDA pin */
 54 #define OBPC    (1 << 4)        /* override pins */
 55 #define MIE     (1 << 3)        /* master if enable */
 56 #define TSBE    (1 << 2)
 57 #define FSB     (1 << 1)        /* force stop bit */
 58 #define ESG     (1 << 0)        /* en startbit gen */
 59 
 60 /* ICMSR (also for ICMIE) */
 61 #define MNR     (1 << 6)        /* nack received */
 62 #define MAL     (1 << 5)        /* arbitration lost */
 63 #define MST     (1 << 4)        /* sent a stop */
 64 #define MDE     (1 << 3)
 65 #define MDT     (1 << 2)
 66 #define MDR     (1 << 1)
 67 #define MAT     (1 << 0)        /* slave addr xfer done */
 68 
 69 
 70 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
 71 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
 72 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
 73 
 74 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
 75 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
 76 #define RCAR_IRQ_STOP   (MST)
 77 
 78 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE))
 79 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR))
 80 
 81 #define ID_LAST_MSG     (1 << 0)
 82 #define ID_IOERROR      (1 << 1)
 83 #define ID_DONE         (1 << 2)
 84 #define ID_ARBLOST      (1 << 3)
 85 #define ID_NACK         (1 << 4)
 86 
 87 enum rcar_i2c_type {
 88         I2C_RCAR_GEN1,
 89         I2C_RCAR_GEN2,
 90 };
 91 
 92 struct rcar_i2c_priv {
 93         void __iomem *io;
 94         struct i2c_adapter adap;
 95         struct i2c_msg  *msg;
 96         struct clk *clk;
 97 
 98         wait_queue_head_t wait;
 99 
100         int pos;
101         u32 icccr;
102         u32 flags;
103         enum rcar_i2c_type devtype;
104 };
105 
106 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
107 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
108 
109 #define rcar_i2c_flags_set(p, f)        ((p)->flags |= (f))
110 #define rcar_i2c_flags_has(p, f)        ((p)->flags & (f))
111 
112 #define LOOP_TIMEOUT    1024
113 
114 
115 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
116 {
117         writel(val, priv->io + reg);
118 }
119 
120 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
121 {
122         return readl(priv->io + reg);
123 }
124 
125 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
126 {
127         /*
128          * reset slave mode.
129          * slave mode is not used on this driver
130          */
131         rcar_i2c_write(priv, ICSIER, 0);
132         rcar_i2c_write(priv, ICSAR, 0);
133         rcar_i2c_write(priv, ICSCR, 0);
134         rcar_i2c_write(priv, ICSSR, 0);
135 
136         /* reset master mode */
137         rcar_i2c_write(priv, ICMIER, 0);
138         rcar_i2c_write(priv, ICMCR, 0);
139         rcar_i2c_write(priv, ICMSR, 0);
140         rcar_i2c_write(priv, ICMAR, 0);
141 }
142 
143 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
144 {
145         int i;
146 
147         for (i = 0; i < LOOP_TIMEOUT; i++) {
148                 /* make sure that bus is not busy */
149                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
150                         return 0;
151                 udelay(1);
152         }
153 
154         return -EBUSY;
155 }
156 
157 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
158                                     u32 bus_speed,
159                                     struct device *dev)
160 {
161         u32 scgd, cdf;
162         u32 round, ick;
163         u32 scl;
164         u32 cdf_width;
165         unsigned long rate;
166 
167         switch (priv->devtype) {
168         case I2C_RCAR_GEN1:
169                 cdf_width = 2;
170                 break;
171         case I2C_RCAR_GEN2:
172                 cdf_width = 3;
173                 break;
174         default:
175                 dev_err(dev, "device type error\n");
176                 return -EIO;
177         }
178 
179         /*
180          * calculate SCL clock
181          * see
182          *      ICCCR
183          *
184          * ick  = clkp / (1 + CDF)
185          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
186          *
187          * ick  : I2C internal clock < 20 MHz
188          * ticf : I2C SCL falling time  =  35 ns here
189          * tr   : I2C SCL rising  time  = 200 ns here
190          * intd : LSI internal delay    =  50 ns here
191          * clkp : peripheral_clk
192          * F[]  : integer up-valuation
193          */
194         rate = clk_get_rate(priv->clk);
195         cdf = rate / 20000000;
196         if (cdf >= 1 << cdf_width) {
197                 dev_err(dev, "Input clock %lu too high\n", rate);
198                 return -EIO;
199         }
200         ick = rate / (cdf + 1);
201 
202         /*
203          * it is impossible to calculate large scale
204          * number on u32. separate it
205          *
206          * F[(ticf + tr + intd) * ick]
207          *  = F[(35 + 200 + 50)ns * ick]
208          *  = F[285 * ick / 1000000000]
209          *  = F[(ick / 1000000) * 285 / 1000]
210          */
211         round = (ick + 500000) / 1000000 * 285;
212         round = (round + 500) / 1000;
213 
214         /*
215          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
216          *
217          * Calculation result (= SCL) should be less than
218          * bus_speed for hardware safety
219          *
220          * We could use something along the lines of
221          *      div = ick / (bus_speed + 1) + 1;
222          *      scgd = (div - 20 - round + 7) / 8;
223          *      scl = ick / (20 + (scgd * 8) + round);
224          * (not fully verified) but that would get pretty involved
225          */
226         for (scgd = 0; scgd < 0x40; scgd++) {
227                 scl = ick / (20 + (scgd * 8) + round);
228                 if (scl <= bus_speed)
229                         goto scgd_find;
230         }
231         dev_err(dev, "it is impossible to calculate best SCL\n");
232         return -EIO;
233 
234 scgd_find:
235         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
236                 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
237 
238         /*
239          * keep icccr value
240          */
241         priv->icccr = scgd << cdf_width | cdf;
242 
243         return 0;
244 }
245 
246 static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
247 {
248         int read = !!rcar_i2c_is_recv(priv);
249 
250         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
251         rcar_i2c_write(priv, ICMSR, 0);
252         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
253         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
254 
255         return 0;
256 }
257 
258 /*
259  *              interrupt functions
260  */
261 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
262 {
263         struct i2c_msg *msg = priv->msg;
264 
265         /*
266          * FIXME
267          * sometimes, unknown interrupt happened.
268          * Do nothing
269          */
270         if (!(msr & MDE))
271                 return 0;
272 
273         /*
274          * If address transfer phase finished,
275          * goto data phase.
276          */
277         if (msr & MAT)
278                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
279 
280         if (priv->pos < msg->len) {
281                 /*
282                  * Prepare next data to ICRXTX register.
283                  * This data will go to _SHIFT_ register.
284                  *
285                  *    *
286                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
287                  */
288                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
289                 priv->pos++;
290 
291         } else {
292                 /*
293                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
294                  * It is on _SHIFT_ register, and will sent to I2C bus.
295                  *
296                  *                *
297                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
298                  */
299 
300                 if (priv->flags & ID_LAST_MSG)
301                         /*
302                          * If current msg is the _LAST_ msg,
303                          * prepare stop condition here.
304                          * ID_DONE will be set on STOP irq.
305                          */
306                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
307                 else
308                         /*
309                          * If current msg is _NOT_ last msg,
310                          * it doesn't call stop phase.
311                          * thus, there is no STOP irq.
312                          * return ID_DONE here.
313                          */
314                         return ID_DONE;
315         }
316 
317         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
318 
319         return 0;
320 }
321 
322 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
323 {
324         struct i2c_msg *msg = priv->msg;
325 
326         /*
327          * FIXME
328          * sometimes, unknown interrupt happened.
329          * Do nothing
330          */
331         if (!(msr & MDR))
332                 return 0;
333 
334         if (msr & MAT) {
335                 /*
336                  * Address transfer phase finished,
337                  * but, there is no data at this point.
338                  * Do nothing.
339                  */
340         } else if (priv->pos < msg->len) {
341                 /*
342                  * get received data
343                  */
344                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
345                 priv->pos++;
346         }
347 
348         /*
349          * If next received data is the _LAST_,
350          * go to STOP phase,
351          * otherwise, go to DATA phase.
352          */
353         if (priv->pos + 1 >= msg->len)
354                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
355         else
356                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
357 
358         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
359 
360         return 0;
361 }
362 
363 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
364 {
365         struct rcar_i2c_priv *priv = ptr;
366         u32 msr;
367 
368         msr = rcar_i2c_read(priv, ICMSR);
369 
370         /* Arbitration lost */
371         if (msr & MAL) {
372                 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
373                 goto out;
374         }
375 
376         /* Stop */
377         if (msr & MST) {
378                 rcar_i2c_flags_set(priv, ID_DONE);
379                 goto out;
380         }
381 
382         /* Nack */
383         if (msr & MNR) {
384                 /* go to stop phase */
385                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
386                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
387                 rcar_i2c_flags_set(priv, ID_NACK);
388                 goto out;
389         }
390 
391         if (rcar_i2c_is_recv(priv))
392                 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
393         else
394                 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
395 
396 out:
397         if (rcar_i2c_flags_has(priv, ID_DONE)) {
398                 rcar_i2c_write(priv, ICMIER, 0);
399                 rcar_i2c_write(priv, ICMSR, 0);
400                 wake_up(&priv->wait);
401         }
402 
403         return IRQ_HANDLED;
404 }
405 
406 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
407                                 struct i2c_msg *msgs,
408                                 int num)
409 {
410         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
411         struct device *dev = rcar_i2c_priv_to_dev(priv);
412         int i, ret, timeout;
413 
414         pm_runtime_get_sync(dev);
415 
416         rcar_i2c_init(priv);
417         /* start clock */
418         rcar_i2c_write(priv, ICCCR, priv->icccr);
419 
420         ret = rcar_i2c_bus_barrier(priv);
421         if (ret < 0)
422                 goto out;
423 
424         for (i = 0; i < num; i++) {
425                 /* This HW can't send STOP after address phase */
426                 if (msgs[i].len == 0) {
427                         ret = -EOPNOTSUPP;
428                         break;
429                 }
430 
431                 /* init each data */
432                 priv->msg       = &msgs[i];
433                 priv->pos       = 0;
434                 priv->flags     = 0;
435                 if (priv->msg == &msgs[num - 1])
436                         rcar_i2c_flags_set(priv, ID_LAST_MSG);
437 
438                 ret = rcar_i2c_prepare_msg(priv);
439 
440                 if (ret < 0)
441                         break;
442 
443                 timeout = wait_event_timeout(priv->wait,
444                                              rcar_i2c_flags_has(priv, ID_DONE),
445                                              5 * HZ);
446                 if (!timeout) {
447                         ret = -ETIMEDOUT;
448                         break;
449                 }
450 
451                 if (rcar_i2c_flags_has(priv, ID_NACK)) {
452                         ret = -ENXIO;
453                         break;
454                 }
455 
456                 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
457                         ret = -EAGAIN;
458                         break;
459                 }
460 
461                 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
462                         ret = -EIO;
463                         break;
464                 }
465 
466                 ret = i + 1; /* The number of transfer */
467         }
468 out:
469         pm_runtime_put(dev);
470 
471         if (ret < 0 && ret != -ENXIO)
472                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
473 
474         return ret;
475 }
476 
477 static u32 rcar_i2c_func(struct i2c_adapter *adap)
478 {
479         /* This HW can't do SMBUS_QUICK and NOSTART */
480         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
481 }
482 
483 static const struct i2c_algorithm rcar_i2c_algo = {
484         .master_xfer    = rcar_i2c_master_xfer,
485         .functionality  = rcar_i2c_func,
486 };
487 
488 static const struct of_device_id rcar_i2c_dt_ids[] = {
489         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
490         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
491         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
492         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
493         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
494         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
495         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
496         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
497         {},
498 };
499 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
500 
501 static int rcar_i2c_probe(struct platform_device *pdev)
502 {
503         struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
504         struct rcar_i2c_priv *priv;
505         struct i2c_adapter *adap;
506         struct resource *res;
507         struct device *dev = &pdev->dev;
508         u32 bus_speed;
509         int irq, ret;
510 
511         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
512         if (!priv)
513                 return -ENOMEM;
514 
515         priv->clk = devm_clk_get(dev, NULL);
516         if (IS_ERR(priv->clk)) {
517                 dev_err(dev, "cannot get clock\n");
518                 return PTR_ERR(priv->clk);
519         }
520 
521         bus_speed = 100000; /* default 100 kHz */
522         ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
523         if (ret < 0 && pdata && pdata->bus_speed)
524                 bus_speed = pdata->bus_speed;
525 
526         if (pdev->dev.of_node)
527                 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
528                                                       dev)->data;
529         else
530                 priv->devtype = platform_get_device_id(pdev)->driver_data;
531 
532         ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
533         if (ret < 0)
534                 return ret;
535 
536         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
537         priv->io = devm_ioremap_resource(dev, res);
538         if (IS_ERR(priv->io))
539                 return PTR_ERR(priv->io);
540 
541         irq = platform_get_irq(pdev, 0);
542         init_waitqueue_head(&priv->wait);
543 
544         adap                    = &priv->adap;
545         adap->nr                = pdev->id;
546         adap->algo              = &rcar_i2c_algo;
547         adap->class             = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED;
548         adap->retries           = 3;
549         adap->dev.parent        = dev;
550         adap->dev.of_node       = dev->of_node;
551         i2c_set_adapdata(adap, priv);
552         strlcpy(adap->name, pdev->name, sizeof(adap->name));
553 
554         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
555                                dev_name(dev), priv);
556         if (ret < 0) {
557                 dev_err(dev, "cannot get irq %d\n", irq);
558                 return ret;
559         }
560 
561         ret = i2c_add_numbered_adapter(adap);
562         if (ret < 0) {
563                 dev_err(dev, "reg adap failed: %d\n", ret);
564                 return ret;
565         }
566 
567         pm_runtime_enable(dev);
568         platform_set_drvdata(pdev, priv);
569 
570         dev_info(dev, "probed\n");
571 
572         return 0;
573 }
574 
575 static int rcar_i2c_remove(struct platform_device *pdev)
576 {
577         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
578         struct device *dev = &pdev->dev;
579 
580         i2c_del_adapter(&priv->adap);
581         pm_runtime_disable(dev);
582 
583         return 0;
584 }
585 
586 static struct platform_device_id rcar_i2c_id_table[] = {
587         { "i2c-rcar",           I2C_RCAR_GEN1 },
588         { "i2c-rcar_gen1",      I2C_RCAR_GEN1 },
589         { "i2c-rcar_gen2",      I2C_RCAR_GEN2 },
590         {},
591 };
592 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
593 
594 static struct platform_driver rcar_i2c_driver = {
595         .driver = {
596                 .name   = "i2c-rcar",
597                 .owner  = THIS_MODULE,
598                 .of_match_table = rcar_i2c_dt_ids,
599         },
600         .probe          = rcar_i2c_probe,
601         .remove         = rcar_i2c_remove,
602         .id_table       = rcar_i2c_id_table,
603 };
604 
605 module_platform_driver(rcar_i2c_driver);
606 
607 MODULE_LICENSE("GPL v2");
608 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
609 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
610 

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