Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/i2c/busses/i2c-pxa.c

  1 /*
  2  *  i2c_adap_pxa.c
  3  *
  4  *  I2C adapter for the PXA I2C bus access.
  5  *
  6  *  Copyright (C) 2002 Intrinsyc Software Inc.
  7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
  8  *
  9  *  This program is free software; you can redistribute it and/or modify
 10  *  it under the terms of the GNU General Public License version 2 as
 11  *  published by the Free Software Foundation.
 12  *
 13  *  History:
 14  *    Apr 2002: Initial version [CS]
 15  *    Jun 2002: Properly separated algo/adap [FB]
 16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
 17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
 18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
 19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
 20  *    Feb 2005: Rework slave mode handling [RMK]
 21  */
 22 #include <linux/kernel.h>
 23 #include <linux/module.h>
 24 #include <linux/i2c.h>
 25 #include <linux/init.h>
 26 #include <linux/time.h>
 27 #include <linux/sched.h>
 28 #include <linux/delay.h>
 29 #include <linux/errno.h>
 30 #include <linux/interrupt.h>
 31 #include <linux/i2c-pxa.h>
 32 #include <linux/of.h>
 33 #include <linux/of_device.h>
 34 #include <linux/platform_device.h>
 35 #include <linux/err.h>
 36 #include <linux/clk.h>
 37 #include <linux/slab.h>
 38 #include <linux/io.h>
 39 #include <linux/i2c/pxa-i2c.h>
 40 
 41 #include <asm/irq.h>
 42 
 43 struct pxa_reg_layout {
 44         u32 ibmr;
 45         u32 idbr;
 46         u32 icr;
 47         u32 isr;
 48         u32 isar;
 49         u32 ilcr;
 50         u32 iwcr;
 51 };
 52 
 53 enum pxa_i2c_types {
 54         REGS_PXA2XX,
 55         REGS_PXA3XX,
 56         REGS_CE4100,
 57         REGS_PXA910,
 58 };
 59 
 60 /*
 61  * I2C registers definitions
 62  */
 63 static struct pxa_reg_layout pxa_reg_layout[] = {
 64         [REGS_PXA2XX] = {
 65                 .ibmr = 0x00,
 66                 .idbr = 0x08,
 67                 .icr =  0x10,
 68                 .isr =  0x18,
 69                 .isar = 0x20,
 70         },
 71         [REGS_PXA3XX] = {
 72                 .ibmr = 0x00,
 73                 .idbr = 0x04,
 74                 .icr =  0x08,
 75                 .isr =  0x0c,
 76                 .isar = 0x10,
 77         },
 78         [REGS_CE4100] = {
 79                 .ibmr = 0x14,
 80                 .idbr = 0x0c,
 81                 .icr =  0x00,
 82                 .isr =  0x04,
 83                 /* no isar register */
 84         },
 85         [REGS_PXA910] = {
 86                 .ibmr = 0x00,
 87                 .idbr = 0x08,
 88                 .icr =  0x10,
 89                 .isr =  0x18,
 90                 .isar = 0x20,
 91                 .ilcr = 0x28,
 92                 .iwcr = 0x30,
 93         },
 94 };
 95 
 96 static const struct platform_device_id i2c_pxa_id_table[] = {
 97         { "pxa2xx-i2c",         REGS_PXA2XX },
 98         { "pxa3xx-pwri2c",      REGS_PXA3XX },
 99         { "ce4100-i2c",         REGS_CE4100 },
100         { "pxa910-i2c",         REGS_PXA910 },
101         { },
102 };
103 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
104 
105 /*
106  * I2C bit definitions
107  */
108 
109 #define ICR_START       (1 << 0)           /* start bit */
110 #define ICR_STOP        (1 << 1)           /* stop bit */
111 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
112 #define ICR_TB          (1 << 3)           /* transfer byte bit */
113 #define ICR_MA          (1 << 4)           /* master abort */
114 #define ICR_SCLE        (1 << 5)           /* master clock enable */
115 #define ICR_IUE         (1 << 6)           /* unit enable */
116 #define ICR_GCD         (1 << 7)           /* general call disable */
117 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
118 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
119 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
120 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
121 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
122 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
123 #define ICR_UR          (1 << 14)          /* unit reset */
124 #define ICR_FM          (1 << 15)          /* fast mode */
125 #define ICR_HS          (1 << 16)          /* High Speed mode */
126 #define ICR_GPIOEN      (1 << 19)          /* enable GPIO mode for SCL in HS */
127 
128 #define ISR_RWM         (1 << 0)           /* read/write mode */
129 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
130 #define ISR_UB          (1 << 2)           /* unit busy */
131 #define ISR_IBB         (1 << 3)           /* bus busy */
132 #define ISR_SSD         (1 << 4)           /* slave stop detected */
133 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
134 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
135 #define ISR_IRF         (1 << 7)           /* rx buffer full */
136 #define ISR_GCAD        (1 << 8)           /* general call address detected */
137 #define ISR_SAD         (1 << 9)           /* slave address detected */
138 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
139 
140 /* bit field shift & mask */
141 #define ILCR_SLV_SHIFT          0
142 #define ILCR_SLV_MASK           (0x1FF << ILCR_SLV_SHIFT)
143 #define ILCR_FLV_SHIFT          9
144 #define ILCR_FLV_MASK           (0x1FF << ILCR_FLV_SHIFT)
145 #define ILCR_HLVL_SHIFT         18
146 #define ILCR_HLVL_MASK          (0x1FF << ILCR_HLVL_SHIFT)
147 #define ILCR_HLVH_SHIFT         27
148 #define ILCR_HLVH_MASK          (0x1F << ILCR_HLVH_SHIFT)
149 
150 #define IWCR_CNT_SHIFT          0
151 #define IWCR_CNT_MASK           (0x1F << IWCR_CNT_SHIFT)
152 #define IWCR_HS_CNT1_SHIFT      5
153 #define IWCR_HS_CNT1_MASK       (0x1F << IWCR_HS_CNT1_SHIFT)
154 #define IWCR_HS_CNT2_SHIFT      10
155 #define IWCR_HS_CNT2_MASK       (0x1F << IWCR_HS_CNT2_SHIFT)
156 
157 struct pxa_i2c {
158         spinlock_t              lock;
159         wait_queue_head_t       wait;
160         struct i2c_msg          *msg;
161         unsigned int            msg_num;
162         unsigned int            msg_idx;
163         unsigned int            msg_ptr;
164         unsigned int            slave_addr;
165         unsigned int            req_slave_addr;
166 
167         struct i2c_adapter      adap;
168         struct clk              *clk;
169 #ifdef CONFIG_I2C_PXA_SLAVE
170         struct i2c_slave_client *slave;
171 #endif
172 
173         unsigned int            irqlogidx;
174         u32                     isrlog[32];
175         u32                     icrlog[32];
176 
177         void __iomem            *reg_base;
178         void __iomem            *reg_ibmr;
179         void __iomem            *reg_idbr;
180         void __iomem            *reg_icr;
181         void __iomem            *reg_isr;
182         void __iomem            *reg_isar;
183         void __iomem            *reg_ilcr;
184         void __iomem            *reg_iwcr;
185 
186         unsigned long           iobase;
187         unsigned long           iosize;
188 
189         int                     irq;
190         unsigned int            use_pio :1;
191         unsigned int            fast_mode :1;
192         unsigned int            high_mode:1;
193         unsigned char           master_code;
194         unsigned long           rate;
195         bool                    highmode_enter;
196 };
197 
198 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
199 #define _IDBR(i2c)      ((i2c)->reg_idbr)
200 #define _ICR(i2c)       ((i2c)->reg_icr)
201 #define _ISR(i2c)       ((i2c)->reg_isr)
202 #define _ISAR(i2c)      ((i2c)->reg_isar)
203 #define _ILCR(i2c)      ((i2c)->reg_ilcr)
204 #define _IWCR(i2c)      ((i2c)->reg_iwcr)
205 
206 /*
207  * I2C Slave mode address
208  */
209 #define I2C_PXA_SLAVE_ADDR      0x1
210 
211 #ifdef DEBUG
212 
213 struct bits {
214         u32     mask;
215         const char *set;
216         const char *unset;
217 };
218 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
219 
220 static inline void
221 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
222 {
223         printk("%s %08x: ", prefix, val);
224         while (num--) {
225                 const char *str = val & bits->mask ? bits->set : bits->unset;
226                 if (str)
227                         printk("%s ", str);
228                 bits++;
229         }
230 }
231 
232 static const struct bits isr_bits[] = {
233         PXA_BIT(ISR_RWM,        "RX",           "TX"),
234         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
235         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
236         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
237         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
238         PXA_BIT(ISR_ALD,        "ALD",          NULL),
239         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
240         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
241         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
242         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
243         PXA_BIT(ISR_BED,        "BusErr",       NULL),
244 };
245 
246 static void decode_ISR(unsigned int val)
247 {
248         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
249         printk("\n");
250 }
251 
252 static const struct bits icr_bits[] = {
253         PXA_BIT(ICR_START,  "START",    NULL),
254         PXA_BIT(ICR_STOP,   "STOP",     NULL),
255         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
256         PXA_BIT(ICR_TB,     "TB",       NULL),
257         PXA_BIT(ICR_MA,     "MA",       NULL),
258         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
259         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
260         PXA_BIT(ICR_GCD,    "GCD",      NULL),
261         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
262         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
263         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
264         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
265         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
266         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
267         PXA_BIT(ICR_UR,     "UR",               "ur"),
268 };
269 
270 #ifdef CONFIG_I2C_PXA_SLAVE
271 static void decode_ICR(unsigned int val)
272 {
273         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
274         printk("\n");
275 }
276 #endif
277 
278 static unsigned int i2c_debug = DEBUG;
279 
280 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
281 {
282         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
283                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
284 }
285 
286 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
287 
288 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
289 {
290         unsigned int i;
291         struct device *dev = &i2c->adap.dev;
292 
293         dev_err(dev, "slave_0x%x error: %s\n",
294                 i2c->req_slave_addr >> 1, why);
295         dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
296                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
297         dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
298                 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
299                 readl(_ISR(i2c)));
300         dev_dbg(dev, "log: ");
301         for (i = 0; i < i2c->irqlogidx; i++)
302                 pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
303 
304         pr_debug("\n");
305 }
306 
307 #else /* ifdef DEBUG */
308 
309 #define i2c_debug       0
310 
311 #define show_state(i2c) do { } while (0)
312 #define decode_ISR(val) do { } while (0)
313 #define decode_ICR(val) do { } while (0)
314 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
315 
316 #endif /* ifdef DEBUG / else */
317 
318 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
319 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
320 
321 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
322 {
323         return !(readl(_ICR(i2c)) & ICR_SCLE);
324 }
325 
326 static void i2c_pxa_abort(struct pxa_i2c *i2c)
327 {
328         int i = 250;
329 
330         if (i2c_pxa_is_slavemode(i2c)) {
331                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
332                 return;
333         }
334 
335         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
336                 unsigned long icr = readl(_ICR(i2c));
337 
338                 icr &= ~ICR_START;
339                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
340 
341                 writel(icr, _ICR(i2c));
342 
343                 show_state(i2c);
344 
345                 mdelay(1);
346                 i --;
347         }
348 
349         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
350                _ICR(i2c));
351 }
352 
353 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
354 {
355         int timeout = DEF_TIMEOUT;
356 
357         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
358                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
359                         timeout += 4;
360 
361                 msleep(2);
362                 show_state(i2c);
363         }
364 
365         if (timeout < 0)
366                 show_state(i2c);
367 
368         return timeout < 0 ? I2C_RETRY : 0;
369 }
370 
371 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
372 {
373         unsigned long timeout = jiffies + HZ*4;
374 
375         while (time_before(jiffies, timeout)) {
376                 if (i2c_debug > 1)
377                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
378                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
379 
380                 if (readl(_ISR(i2c)) & ISR_SAD) {
381                         if (i2c_debug > 0)
382                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
383                         goto out;
384                 }
385 
386                 /* wait for unit and bus being not busy, and we also do a
387                  * quick check of the i2c lines themselves to ensure they've
388                  * gone high...
389                  */
390                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
391                         if (i2c_debug > 0)
392                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
393                         return 1;
394                 }
395 
396                 msleep(1);
397         }
398 
399         if (i2c_debug > 0)
400                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
401  out:
402         return 0;
403 }
404 
405 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
406 {
407         if (i2c_debug)
408                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
409 
410         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
411                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
412                 if (!i2c_pxa_wait_master(i2c)) {
413                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
414                         return I2C_RETRY;
415                 }
416         }
417 
418         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
419         return 0;
420 }
421 
422 #ifdef CONFIG_I2C_PXA_SLAVE
423 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
424 {
425         unsigned long timeout = jiffies + HZ*1;
426 
427         /* wait for stop */
428 
429         show_state(i2c);
430 
431         while (time_before(jiffies, timeout)) {
432                 if (i2c_debug > 1)
433                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
434                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
435 
436                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
437                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
438                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
439                         if (i2c_debug > 1)
440                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
441                         return 1;
442                 }
443 
444                 msleep(1);
445         }
446 
447         if (i2c_debug > 0)
448                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
449         return 0;
450 }
451 
452 /*
453  * clear the hold on the bus, and take of anything else
454  * that has been configured
455  */
456 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
457 {
458         show_state(i2c);
459 
460         if (errcode < 0) {
461                 udelay(100);   /* simple delay */
462         } else {
463                 /* we need to wait for the stop condition to end */
464 
465                 /* if we where in stop, then clear... */
466                 if (readl(_ICR(i2c)) & ICR_STOP) {
467                         udelay(100);
468                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
469                 }
470 
471                 if (!i2c_pxa_wait_slave(i2c)) {
472                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
473                                 __func__);
474                         return;
475                 }
476         }
477 
478         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
479         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
480 
481         if (i2c_debug) {
482                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
483                 decode_ICR(readl(_ICR(i2c)));
484         }
485 }
486 #else
487 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
488 #endif
489 
490 static void i2c_pxa_reset(struct pxa_i2c *i2c)
491 {
492         pr_debug("Resetting I2C Controller Unit\n");
493 
494         /* abort any transfer currently under way */
495         i2c_pxa_abort(i2c);
496 
497         /* reset according to 9.8 */
498         writel(ICR_UR, _ICR(i2c));
499         writel(I2C_ISR_INIT, _ISR(i2c));
500         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
501 
502         if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
503                 writel(i2c->slave_addr, _ISAR(i2c));
504 
505         /* set control register values */
506         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
507         writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
508 
509 #ifdef CONFIG_I2C_PXA_SLAVE
510         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
511         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
512 #endif
513 
514         i2c_pxa_set_slave(i2c, 0);
515 
516         /* enable unit */
517         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
518         udelay(100);
519 }
520 
521 
522 #ifdef CONFIG_I2C_PXA_SLAVE
523 /*
524  * PXA I2C Slave mode
525  */
526 
527 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
528 {
529         if (isr & ISR_BED) {
530                 /* what should we do here? */
531         } else {
532                 int ret = 0;
533 
534                 if (i2c->slave != NULL)
535                         ret = i2c->slave->read(i2c->slave->data);
536 
537                 writel(ret, _IDBR(i2c));
538                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
539         }
540 }
541 
542 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
543 {
544         unsigned int byte = readl(_IDBR(i2c));
545 
546         if (i2c->slave != NULL)
547                 i2c->slave->write(i2c->slave->data, byte);
548 
549         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
550 }
551 
552 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
553 {
554         int timeout;
555 
556         if (i2c_debug > 0)
557                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
558                        (isr & ISR_RWM) ? 'r' : 't');
559 
560         if (i2c->slave != NULL)
561                 i2c->slave->event(i2c->slave->data,
562                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
563 
564         /*
565          * slave could interrupt in the middle of us generating a
566          * start condition... if this happens, we'd better back off
567          * and stop holding the poor thing up
568          */
569         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
570         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
571 
572         timeout = 0x10000;
573 
574         while (1) {
575                 if ((readl(_IBMR(i2c)) & 2) == 2)
576                         break;
577 
578                 timeout--;
579 
580                 if (timeout <= 0) {
581                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
582                         break;
583                 }
584         }
585 
586         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
587 }
588 
589 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
590 {
591         if (i2c_debug > 2)
592                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
593 
594         if (i2c->slave != NULL)
595                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
596 
597         if (i2c_debug > 2)
598                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
599 
600         /*
601          * If we have a master-mode message waiting,
602          * kick it off now that the slave has completed.
603          */
604         if (i2c->msg)
605                 i2c_pxa_master_complete(i2c, I2C_RETRY);
606 }
607 #else
608 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
609 {
610         if (isr & ISR_BED) {
611                 /* what should we do here? */
612         } else {
613                 writel(0, _IDBR(i2c));
614                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
615         }
616 }
617 
618 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
619 {
620         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
621 }
622 
623 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
624 {
625         int timeout;
626 
627         /*
628          * slave could interrupt in the middle of us generating a
629          * start condition... if this happens, we'd better back off
630          * and stop holding the poor thing up
631          */
632         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
633         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
634 
635         timeout = 0x10000;
636 
637         while (1) {
638                 if ((readl(_IBMR(i2c)) & 2) == 2)
639                         break;
640 
641                 timeout--;
642 
643                 if (timeout <= 0) {
644                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
645                         break;
646                 }
647         }
648 
649         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
650 }
651 
652 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
653 {
654         if (i2c->msg)
655                 i2c_pxa_master_complete(i2c, I2C_RETRY);
656 }
657 #endif
658 
659 /*
660  * PXA I2C Master mode
661  */
662 
663 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
664 {
665         unsigned int addr = (msg->addr & 0x7f) << 1;
666 
667         if (msg->flags & I2C_M_RD)
668                 addr |= 1;
669 
670         return addr;
671 }
672 
673 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
674 {
675         u32 icr;
676 
677         /*
678          * Step 1: target slave address into IDBR
679          */
680         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
681         i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
682 
683         /*
684          * Step 2: initiate the write.
685          */
686         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
687         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
688 }
689 
690 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
691 {
692         u32 icr;
693 
694         /*
695          * Clear the STOP and ACK flags
696          */
697         icr = readl(_ICR(i2c));
698         icr &= ~(ICR_STOP | ICR_ACKNAK);
699         writel(icr, _ICR(i2c));
700 }
701 
702 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
703 {
704         /* make timeout the same as for interrupt based functions */
705         long timeout = 2 * DEF_TIMEOUT;
706 
707         /*
708          * Wait for the bus to become free.
709          */
710         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
711                 udelay(1000);
712                 show_state(i2c);
713         }
714 
715         if (timeout < 0) {
716                 show_state(i2c);
717                 dev_err(&i2c->adap.dev,
718                         "i2c_pxa: timeout waiting for bus free\n");
719                 return I2C_RETRY;
720         }
721 
722         /*
723          * Set master mode.
724          */
725         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
726 
727         return 0;
728 }
729 
730 /*
731  * PXA I2C send master code
732  * 1. Load master code to IDBR and send it.
733  *    Note for HS mode, set ICR [GPIOEN].
734  * 2. Wait until win arbitration.
735  */
736 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
737 {
738         u32 icr;
739         long timeout;
740 
741         spin_lock_irq(&i2c->lock);
742         i2c->highmode_enter = true;
743         writel(i2c->master_code, _IDBR(i2c));
744 
745         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
746         icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
747         writel(icr, _ICR(i2c));
748 
749         spin_unlock_irq(&i2c->lock);
750         timeout = wait_event_timeout(i2c->wait,
751                         i2c->highmode_enter == false, HZ * 1);
752 
753         i2c->highmode_enter = false;
754 
755         return (timeout == 0) ? I2C_RETRY : 0;
756 }
757 
758 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
759                                struct i2c_msg *msg, int num)
760 {
761         unsigned long timeout = 500000; /* 5 seconds */
762         int ret = 0;
763 
764         ret = i2c_pxa_pio_set_master(i2c);
765         if (ret)
766                 goto out;
767 
768         i2c->msg = msg;
769         i2c->msg_num = num;
770         i2c->msg_idx = 0;
771         i2c->msg_ptr = 0;
772         i2c->irqlogidx = 0;
773 
774         i2c_pxa_start_message(i2c);
775 
776         while (i2c->msg_num > 0 && --timeout) {
777                 i2c_pxa_handler(0, i2c);
778                 udelay(10);
779         }
780 
781         i2c_pxa_stop_message(i2c);
782 
783         /*
784          * We place the return code in i2c->msg_idx.
785          */
786         ret = i2c->msg_idx;
787 
788 out:
789         if (timeout == 0) {
790                 i2c_pxa_scream_blue_murder(i2c, "timeout");
791                 ret = I2C_RETRY;
792         }
793 
794         return ret;
795 }
796 
797 /*
798  * We are protected by the adapter bus mutex.
799  */
800 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
801 {
802         long timeout;
803         int ret;
804 
805         /*
806          * Wait for the bus to become free.
807          */
808         ret = i2c_pxa_wait_bus_not_busy(i2c);
809         if (ret) {
810                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
811                 goto out;
812         }
813 
814         /*
815          * Set master mode.
816          */
817         ret = i2c_pxa_set_master(i2c);
818         if (ret) {
819                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
820                 goto out;
821         }
822 
823         if (i2c->high_mode) {
824                 ret = i2c_pxa_send_mastercode(i2c);
825                 if (ret) {
826                         dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
827                         goto out;
828                         }
829         }
830 
831         spin_lock_irq(&i2c->lock);
832 
833         i2c->msg = msg;
834         i2c->msg_num = num;
835         i2c->msg_idx = 0;
836         i2c->msg_ptr = 0;
837         i2c->irqlogidx = 0;
838 
839         i2c_pxa_start_message(i2c);
840 
841         spin_unlock_irq(&i2c->lock);
842 
843         /*
844          * The rest of the processing occurs in the interrupt handler.
845          */
846         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
847         i2c_pxa_stop_message(i2c);
848 
849         /*
850          * We place the return code in i2c->msg_idx.
851          */
852         ret = i2c->msg_idx;
853 
854         if (!timeout && i2c->msg_num) {
855                 i2c_pxa_scream_blue_murder(i2c, "timeout");
856                 ret = I2C_RETRY;
857         }
858 
859  out:
860         return ret;
861 }
862 
863 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
864                             struct i2c_msg msgs[], int num)
865 {
866         struct pxa_i2c *i2c = adap->algo_data;
867         int ret, i;
868 
869         /* If the I2C controller is disabled we need to reset it
870           (probably due to a suspend/resume destroying state). We do
871           this here as we can then avoid worrying about resuming the
872           controller before its users. */
873         if (!(readl(_ICR(i2c)) & ICR_IUE))
874                 i2c_pxa_reset(i2c);
875 
876         for (i = adap->retries; i >= 0; i--) {
877                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
878                 if (ret != I2C_RETRY)
879                         goto out;
880 
881                 if (i2c_debug)
882                         dev_dbg(&adap->dev, "Retrying transmission\n");
883                 udelay(100);
884         }
885         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
886         ret = -EREMOTEIO;
887  out:
888         i2c_pxa_set_slave(i2c, ret);
889         return ret;
890 }
891 
892 /*
893  * i2c_pxa_master_complete - complete the message and wake up.
894  */
895 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
896 {
897         i2c->msg_ptr = 0;
898         i2c->msg = NULL;
899         i2c->msg_idx ++;
900         i2c->msg_num = 0;
901         if (ret)
902                 i2c->msg_idx = ret;
903         if (!i2c->use_pio)
904                 wake_up(&i2c->wait);
905 }
906 
907 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
908 {
909         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
910 
911  again:
912         /*
913          * If ISR_ALD is set, we lost arbitration.
914          */
915         if (isr & ISR_ALD) {
916                 /*
917                  * Do we need to do anything here?  The PXA docs
918                  * are vague about what happens.
919                  */
920                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
921 
922                 /*
923                  * We ignore this error.  We seem to see spurious ALDs
924                  * for seemingly no reason.  If we handle them as I think
925                  * they should, we end up causing an I2C error, which
926                  * is painful for some systems.
927                  */
928                 return; /* ignore */
929         }
930 
931         if ((isr & ISR_BED) &&
932                 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
933                         (isr & ISR_ACKNAK)))) {
934                 int ret = BUS_ERROR;
935 
936                 /*
937                  * I2C bus error - either the device NAK'd us, or
938                  * something more serious happened.  If we were NAK'd
939                  * on the initial address phase, we can retry.
940                  */
941                 if (isr & ISR_ACKNAK) {
942                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
943                                 ret = I2C_RETRY;
944                         else
945                                 ret = XFER_NAKED;
946                 }
947                 i2c_pxa_master_complete(i2c, ret);
948         } else if (isr & ISR_RWM) {
949                 /*
950                  * Read mode.  We have just sent the address byte, and
951                  * now we must initiate the transfer.
952                  */
953                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
954                     i2c->msg_idx == i2c->msg_num - 1)
955                         icr |= ICR_STOP | ICR_ACKNAK;
956 
957                 icr |= ICR_ALDIE | ICR_TB;
958         } else if (i2c->msg_ptr < i2c->msg->len) {
959                 /*
960                  * Write mode.  Write the next data byte.
961                  */
962                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
963 
964                 icr |= ICR_ALDIE | ICR_TB;
965 
966                 /*
967                  * If this is the last byte of the last message or last byte
968                  * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
969                  */
970                 if ((i2c->msg_ptr == i2c->msg->len) &&
971                         ((i2c->msg->flags & I2C_M_STOP) ||
972                         (i2c->msg_idx == i2c->msg_num - 1)))
973                                 icr |= ICR_STOP;
974 
975         } else if (i2c->msg_idx < i2c->msg_num - 1) {
976                 /*
977                  * Next segment of the message.
978                  */
979                 i2c->msg_ptr = 0;
980                 i2c->msg_idx ++;
981                 i2c->msg++;
982 
983                 /*
984                  * If we aren't doing a repeated start and address,
985                  * go back and try to send the next byte.  Note that
986                  * we do not support switching the R/W direction here.
987                  */
988                 if (i2c->msg->flags & I2C_M_NOSTART)
989                         goto again;
990 
991                 /*
992                  * Write the next address.
993                  */
994                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
995                 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
996 
997                 /*
998                  * And trigger a repeated start, and send the byte.
999                  */
1000                 icr &= ~ICR_ALDIE;
1001                 icr |= ICR_START | ICR_TB;
1002         } else {
1003                 if (i2c->msg->len == 0) {
1004                         /*
1005                          * Device probes have a message length of zero
1006                          * and need the bus to be reset before it can
1007                          * be used again.
1008                          */
1009                         i2c_pxa_reset(i2c);
1010                 }
1011                 i2c_pxa_master_complete(i2c, 0);
1012         }
1013 
1014         i2c->icrlog[i2c->irqlogidx-1] = icr;
1015 
1016         writel(icr, _ICR(i2c));
1017         show_state(i2c);
1018 }
1019 
1020 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
1021 {
1022         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
1023 
1024         /*
1025          * Read the byte.
1026          */
1027         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
1028 
1029         if (i2c->msg_ptr < i2c->msg->len) {
1030                 /*
1031                  * If this is the last byte of the last
1032                  * message, send a STOP.
1033                  */
1034                 if (i2c->msg_ptr == i2c->msg->len - 1)
1035                         icr |= ICR_STOP | ICR_ACKNAK;
1036 
1037                 icr |= ICR_ALDIE | ICR_TB;
1038         } else {
1039                 i2c_pxa_master_complete(i2c, 0);
1040         }
1041 
1042         i2c->icrlog[i2c->irqlogidx-1] = icr;
1043 
1044         writel(icr, _ICR(i2c));
1045 }
1046 
1047 #define VALID_INT_SOURCE        (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1048                                 ISR_SAD | ISR_BED)
1049 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1050 {
1051         struct pxa_i2c *i2c = dev_id;
1052         u32 isr = readl(_ISR(i2c));
1053 
1054         if (!(isr & VALID_INT_SOURCE))
1055                 return IRQ_NONE;
1056 
1057         if (i2c_debug > 2 && 0) {
1058                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1059                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1060                 decode_ISR(isr);
1061         }
1062 
1063         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1064                 i2c->isrlog[i2c->irqlogidx++] = isr;
1065 
1066         show_state(i2c);
1067 
1068         /*
1069          * Always clear all pending IRQs.
1070          */
1071         writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1072 
1073         if (isr & ISR_SAD)
1074                 i2c_pxa_slave_start(i2c, isr);
1075         if (isr & ISR_SSD)
1076                 i2c_pxa_slave_stop(i2c);
1077 
1078         if (i2c_pxa_is_slavemode(i2c)) {
1079                 if (isr & ISR_ITE)
1080                         i2c_pxa_slave_txempty(i2c, isr);
1081                 if (isr & ISR_IRF)
1082                         i2c_pxa_slave_rxfull(i2c, isr);
1083         } else if (i2c->msg && (!i2c->highmode_enter)) {
1084                 if (isr & ISR_ITE)
1085                         i2c_pxa_irq_txempty(i2c, isr);
1086                 if (isr & ISR_IRF)
1087                         i2c_pxa_irq_rxfull(i2c, isr);
1088         } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1089                 i2c->highmode_enter = false;
1090                 wake_up(&i2c->wait);
1091         } else {
1092                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1093         }
1094 
1095         return IRQ_HANDLED;
1096 }
1097 
1098 
1099 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1100 {
1101         struct pxa_i2c *i2c = adap->algo_data;
1102         int ret, i;
1103 
1104         for (i = adap->retries; i >= 0; i--) {
1105                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1106                 if (ret != I2C_RETRY)
1107                         goto out;
1108 
1109                 if (i2c_debug)
1110                         dev_dbg(&adap->dev, "Retrying transmission\n");
1111                 udelay(100);
1112         }
1113         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1114         ret = -EREMOTEIO;
1115  out:
1116         i2c_pxa_set_slave(i2c, ret);
1117         return ret;
1118 }
1119 
1120 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1121 {
1122         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1123                 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1124 }
1125 
1126 static const struct i2c_algorithm i2c_pxa_algorithm = {
1127         .master_xfer    = i2c_pxa_xfer,
1128         .functionality  = i2c_pxa_functionality,
1129 };
1130 
1131 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1132         .master_xfer    = i2c_pxa_pio_xfer,
1133         .functionality  = i2c_pxa_functionality,
1134 };
1135 
1136 static const struct of_device_id i2c_pxa_dt_ids[] = {
1137         { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1138         { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1139         { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
1140         {}
1141 };
1142 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1143 
1144 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1145                             enum pxa_i2c_types *i2c_types)
1146 {
1147         struct device_node *np = pdev->dev.of_node;
1148         const struct of_device_id *of_id =
1149                         of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1150 
1151         if (!of_id)
1152                 return 1;
1153 
1154         /* For device tree we always use the dynamic or alias-assigned ID */
1155         i2c->adap.nr = -1;
1156 
1157         if (of_get_property(np, "mrvl,i2c-polling", NULL))
1158                 i2c->use_pio = 1;
1159         if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1160                 i2c->fast_mode = 1;
1161 
1162         *i2c_types = (enum pxa_i2c_types)(of_id->data);
1163 
1164         return 0;
1165 }
1166 
1167 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1168                                struct pxa_i2c *i2c,
1169                                enum pxa_i2c_types *i2c_types)
1170 {
1171         struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1172         const struct platform_device_id *id = platform_get_device_id(pdev);
1173 
1174         *i2c_types = id->driver_data;
1175         if (plat) {
1176                 i2c->use_pio = plat->use_pio;
1177                 i2c->fast_mode = plat->fast_mode;
1178                 i2c->high_mode = plat->high_mode;
1179                 i2c->master_code = plat->master_code;
1180                 if (!i2c->master_code)
1181                         i2c->master_code = 0xe;
1182                 i2c->rate = plat->rate;
1183         }
1184         return 0;
1185 }
1186 
1187 static int i2c_pxa_probe(struct platform_device *dev)
1188 {
1189         struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1190         enum pxa_i2c_types i2c_type;
1191         struct pxa_i2c *i2c;
1192         struct resource *res = NULL;
1193         int ret, irq;
1194 
1195         i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1196         if (!i2c)
1197                 return -ENOMEM;
1198 
1199         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1200         i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1201         if (IS_ERR(i2c->reg_base))
1202                 return PTR_ERR(i2c->reg_base);
1203 
1204         irq = platform_get_irq(dev, 0);
1205         if (irq < 0) {
1206                 dev_err(&dev->dev, "no irq resource: %d\n", irq);
1207                 return irq;
1208         }
1209 
1210         /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1211         i2c->adap.nr = dev->id;
1212 
1213         ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1214         if (ret > 0)
1215                 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1216         if (ret < 0)
1217                 return ret;
1218 
1219         i2c->adap.owner   = THIS_MODULE;
1220         i2c->adap.retries = 5;
1221 
1222         spin_lock_init(&i2c->lock);
1223         init_waitqueue_head(&i2c->wait);
1224 
1225         strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1226 
1227         i2c->clk = devm_clk_get(&dev->dev, NULL);
1228         if (IS_ERR(i2c->clk)) {
1229                 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1230                 return PTR_ERR(i2c->clk);
1231         }
1232 
1233         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1234         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1235         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1236         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1237         if (i2c_type != REGS_CE4100)
1238                 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1239 
1240         if (i2c_type == REGS_PXA910) {
1241                 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1242                 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1243         }
1244 
1245         i2c->iobase = res->start;
1246         i2c->iosize = resource_size(res);
1247 
1248         i2c->irq = irq;
1249 
1250         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1251         i2c->highmode_enter = false;
1252 
1253         if (plat) {
1254 #ifdef CONFIG_I2C_PXA_SLAVE
1255                 i2c->slave_addr = plat->slave_addr;
1256                 i2c->slave = plat->slave;
1257 #endif
1258                 i2c->adap.class = plat->class;
1259         }
1260 
1261         if (i2c->high_mode) {
1262                 if (i2c->rate) {
1263                         clk_set_rate(i2c->clk, i2c->rate);
1264                         pr_info("i2c: <%s> set rate to %ld\n",
1265                                 i2c->adap.name, clk_get_rate(i2c->clk));
1266                 } else
1267                         pr_warn("i2c: <%s> clock rate not set\n",
1268                                 i2c->adap.name);
1269         }
1270 
1271         clk_prepare_enable(i2c->clk);
1272 
1273         if (i2c->use_pio) {
1274                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1275         } else {
1276                 i2c->adap.algo = &i2c_pxa_algorithm;
1277                 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1278                                 IRQF_SHARED | IRQF_NO_SUSPEND,
1279                                 dev_name(&dev->dev), i2c);
1280                 if (ret) {
1281                         dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1282                         goto ereqirq;
1283                 }
1284         }
1285 
1286         i2c_pxa_reset(i2c);
1287 
1288         i2c->adap.algo_data = i2c;
1289         i2c->adap.dev.parent = &dev->dev;
1290 #ifdef CONFIG_OF
1291         i2c->adap.dev.of_node = dev->dev.of_node;
1292 #endif
1293 
1294         ret = i2c_add_numbered_adapter(&i2c->adap);
1295         if (ret < 0) {
1296                 dev_err(&dev->dev, "failed to add bus: %d\n", ret);
1297                 goto ereqirq;
1298         }
1299 
1300         platform_set_drvdata(dev, i2c);
1301 
1302 #ifdef CONFIG_I2C_PXA_SLAVE
1303         dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1304                 i2c->slave_addr);
1305 #else
1306         dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1307 #endif
1308         return 0;
1309 
1310 ereqirq:
1311         clk_disable_unprepare(i2c->clk);
1312         return ret;
1313 }
1314 
1315 static int i2c_pxa_remove(struct platform_device *dev)
1316 {
1317         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1318 
1319         i2c_del_adapter(&i2c->adap);
1320 
1321         clk_disable_unprepare(i2c->clk);
1322 
1323         return 0;
1324 }
1325 
1326 #ifdef CONFIG_PM
1327 static int i2c_pxa_suspend_noirq(struct device *dev)
1328 {
1329         struct platform_device *pdev = to_platform_device(dev);
1330         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1331 
1332         clk_disable(i2c->clk);
1333 
1334         return 0;
1335 }
1336 
1337 static int i2c_pxa_resume_noirq(struct device *dev)
1338 {
1339         struct platform_device *pdev = to_platform_device(dev);
1340         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1341 
1342         clk_enable(i2c->clk);
1343         i2c_pxa_reset(i2c);
1344 
1345         return 0;
1346 }
1347 
1348 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1349         .suspend_noirq = i2c_pxa_suspend_noirq,
1350         .resume_noirq = i2c_pxa_resume_noirq,
1351 };
1352 
1353 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1354 #else
1355 #define I2C_PXA_DEV_PM_OPS NULL
1356 #endif
1357 
1358 static struct platform_driver i2c_pxa_driver = {
1359         .probe          = i2c_pxa_probe,
1360         .remove         = i2c_pxa_remove,
1361         .driver         = {
1362                 .name   = "pxa2xx-i2c",
1363                 .pm     = I2C_PXA_DEV_PM_OPS,
1364                 .of_match_table = i2c_pxa_dt_ids,
1365         },
1366         .id_table       = i2c_pxa_id_table,
1367 };
1368 
1369 static int __init i2c_adap_pxa_init(void)
1370 {
1371         return platform_driver_register(&i2c_pxa_driver);
1372 }
1373 
1374 static void __exit i2c_adap_pxa_exit(void)
1375 {
1376         platform_driver_unregister(&i2c_pxa_driver);
1377 }
1378 
1379 MODULE_LICENSE("GPL");
1380 MODULE_ALIAS("platform:pxa2xx-i2c");
1381 
1382 subsys_initcall(i2c_adap_pxa_init);
1383 module_exit(i2c_adap_pxa_exit);
1384 

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