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Linux/drivers/i2c/busses/i2c-mpc.c

  1 /*
  2  * (C) Copyright 2003-2004
  3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
  4 
  5  * This is a combined i2c adapter and algorithm driver for the
  6  * MPC107/Tsi107 PowerPC northbridge and processors that include
  7  * the same I2C unit (8240, 8245, 85xx).
  8  *
  9  * Release 0.8
 10  *
 11  * This file is licensed under the terms of the GNU General Public
 12  * License version 2. This program is licensed "as is" without any
 13  * warranty of any kind, whether express or implied.
 14  */
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/module.h>
 18 #include <linux/sched.h>
 19 #include <linux/of_address.h>
 20 #include <linux/of_irq.h>
 21 #include <linux/of_platform.h>
 22 #include <linux/slab.h>
 23 
 24 #include <linux/clk.h>
 25 #include <linux/io.h>
 26 #include <linux/fsl_devices.h>
 27 #include <linux/i2c.h>
 28 #include <linux/interrupt.h>
 29 #include <linux/delay.h>
 30 
 31 #include <asm/mpc52xx.h>
 32 #include <sysdev/fsl_soc.h>
 33 
 34 #define DRV_NAME "mpc-i2c"
 35 
 36 #define MPC_I2C_CLOCK_LEGACY   0
 37 #define MPC_I2C_CLOCK_PRESERVE (~0U)
 38 
 39 #define MPC_I2C_FDR   0x04
 40 #define MPC_I2C_CR    0x08
 41 #define MPC_I2C_SR    0x0c
 42 #define MPC_I2C_DR    0x10
 43 #define MPC_I2C_DFSRR 0x14
 44 
 45 #define CCR_MEN  0x80
 46 #define CCR_MIEN 0x40
 47 #define CCR_MSTA 0x20
 48 #define CCR_MTX  0x10
 49 #define CCR_TXAK 0x08
 50 #define CCR_RSTA 0x04
 51 
 52 #define CSR_MCF  0x80
 53 #define CSR_MAAS 0x40
 54 #define CSR_MBB  0x20
 55 #define CSR_MAL  0x10
 56 #define CSR_SRW  0x04
 57 #define CSR_MIF  0x02
 58 #define CSR_RXAK 0x01
 59 
 60 struct mpc_i2c {
 61         struct device *dev;
 62         void __iomem *base;
 63         u32 interrupt;
 64         wait_queue_head_t queue;
 65         struct i2c_adapter adap;
 66         int irq;
 67         u32 real_clk;
 68 #ifdef CONFIG_PM_SLEEP
 69         u8 fdr, dfsrr;
 70 #endif
 71         struct clk *clk_per;
 72 };
 73 
 74 struct mpc_i2c_divider {
 75         u16 divider;
 76         u16 fdr;        /* including dfsrr */
 77 };
 78 
 79 struct mpc_i2c_data {
 80         void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
 81                       u32 clock, u32 prescaler);
 82         u32 prescaler;
 83 };
 84 
 85 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
 86 {
 87         writeb(x, i2c->base + MPC_I2C_CR);
 88 }
 89 
 90 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
 91 {
 92         struct mpc_i2c *i2c = dev_id;
 93         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
 94                 /* Read again to allow register to stabilise */
 95                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
 96                 writeb(0, i2c->base + MPC_I2C_SR);
 97                 wake_up(&i2c->queue);
 98         }
 99         return IRQ_HANDLED;
100 }
101 
102 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
103  * the bus, because it wants to send ACK.
104  * Following sequence of enabling/disabling and sending start/stop generates
105  * the 9 pulses, so it's all OK.
106  */
107 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
108 {
109         int k;
110         u32 delay_val = 1000000 / i2c->real_clk + 1;
111 
112         if (delay_val < 2)
113                 delay_val = 2;
114 
115         for (k = 9; k; k--) {
116                 writeccr(i2c, 0);
117                 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
118                 readb(i2c->base + MPC_I2C_DR);
119                 writeccr(i2c, CCR_MEN);
120                 udelay(delay_val << 1);
121         }
122 }
123 
124 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
125 {
126         unsigned long orig_jiffies = jiffies;
127         u32 x;
128         int result = 0;
129 
130         if (!i2c->irq) {
131                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
132                         schedule();
133                         if (time_after(jiffies, orig_jiffies + timeout)) {
134                                 dev_dbg(i2c->dev, "timeout\n");
135                                 writeccr(i2c, 0);
136                                 result = -EIO;
137                                 break;
138                         }
139                 }
140                 x = readb(i2c->base + MPC_I2C_SR);
141                 writeb(0, i2c->base + MPC_I2C_SR);
142         } else {
143                 /* Interrupt mode */
144                 result = wait_event_timeout(i2c->queue,
145                         (i2c->interrupt & CSR_MIF), timeout);
146 
147                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
148                         dev_dbg(i2c->dev, "wait timeout\n");
149                         writeccr(i2c, 0);
150                         result = -ETIMEDOUT;
151                 }
152 
153                 x = i2c->interrupt;
154                 i2c->interrupt = 0;
155         }
156 
157         if (result < 0)
158                 return result;
159 
160         if (!(x & CSR_MCF)) {
161                 dev_dbg(i2c->dev, "unfinished\n");
162                 return -EIO;
163         }
164 
165         if (x & CSR_MAL) {
166                 dev_dbg(i2c->dev, "MAL\n");
167                 return -EIO;
168         }
169 
170         if (writing && (x & CSR_RXAK)) {
171                 dev_dbg(i2c->dev, "No RXAK\n");
172                 /* generate stop */
173                 writeccr(i2c, CCR_MEN);
174                 return -EIO;
175         }
176         return 0;
177 }
178 
179 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
180 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
181         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
182         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
183         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
184         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
185         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
186         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
187         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
188         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
189         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
190         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
191         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
192         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
193         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
194         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
195         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
196         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
197         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
198         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
199 };
200 
201 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
202                                           int prescaler, u32 *real_clk)
203 {
204         const struct mpc_i2c_divider *div = NULL;
205         unsigned int pvr = mfspr(SPRN_PVR);
206         u32 divider;
207         int i;
208 
209         if (clock == MPC_I2C_CLOCK_LEGACY) {
210                 /* see below - default fdr = 0x3f -> div = 2048 */
211                 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
212                 return -EINVAL;
213         }
214 
215         /* Determine divider value */
216         divider = mpc5xxx_get_bus_frequency(node) / clock;
217 
218         /*
219          * We want to choose an FDR/DFSR that generates an I2C bus speed that
220          * is equal to or lower than the requested speed.
221          */
222         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
223                 div = &mpc_i2c_dividers_52xx[i];
224                 /* Old MPC5200 rev A CPUs do not support the high bits */
225                 if (div->fdr & 0xc0 && pvr == 0x80822011)
226                         continue;
227                 if (div->divider >= divider)
228                         break;
229         }
230 
231         *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
232         return (int)div->fdr;
233 }
234 
235 static void mpc_i2c_setup_52xx(struct device_node *node,
236                                          struct mpc_i2c *i2c,
237                                          u32 clock, u32 prescaler)
238 {
239         int ret, fdr;
240 
241         if (clock == MPC_I2C_CLOCK_PRESERVE) {
242                 dev_dbg(i2c->dev, "using fdr %d\n",
243                         readb(i2c->base + MPC_I2C_FDR));
244                 return;
245         }
246 
247         ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
248         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
249 
250         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
251 
252         if (ret >= 0)
253                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
254                          fdr);
255 }
256 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
257 static void mpc_i2c_setup_52xx(struct device_node *node,
258                                          struct mpc_i2c *i2c,
259                                          u32 clock, u32 prescaler)
260 {
261 }
262 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
263 
264 #ifdef CONFIG_PPC_MPC512x
265 static void mpc_i2c_setup_512x(struct device_node *node,
266                                          struct mpc_i2c *i2c,
267                                          u32 clock, u32 prescaler)
268 {
269         struct device_node *node_ctrl;
270         void __iomem *ctrl;
271         const u32 *pval;
272         u32 idx;
273 
274         /* Enable I2C interrupts for mpc5121 */
275         node_ctrl = of_find_compatible_node(NULL, NULL,
276                                             "fsl,mpc5121-i2c-ctrl");
277         if (node_ctrl) {
278                 ctrl = of_iomap(node_ctrl, 0);
279                 if (ctrl) {
280                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
281                         pval = of_get_property(node, "reg", NULL);
282                         idx = (*pval & 0xff) / 0x20;
283                         setbits32(ctrl, 1 << (24 + idx * 2));
284                         iounmap(ctrl);
285                 }
286                 of_node_put(node_ctrl);
287         }
288 
289         /* The clock setup for the 52xx works also fine for the 512x */
290         mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
291 }
292 #else /* CONFIG_PPC_MPC512x */
293 static void mpc_i2c_setup_512x(struct device_node *node,
294                                          struct mpc_i2c *i2c,
295                                          u32 clock, u32 prescaler)
296 {
297 }
298 #endif /* CONFIG_PPC_MPC512x */
299 
300 #ifdef CONFIG_FSL_SOC
301 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
302         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
303         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
304         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
305         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
306         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
307         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
308         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
309         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
310         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
311         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
312         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
313         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
314         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
315         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
316         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
317         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
318         {49152, 0x011e}, {61440, 0x011f}
319 };
320 
321 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
322 {
323         struct device_node *node = NULL;
324         u32 __iomem *reg;
325         u32 val = 0;
326 
327         node = of_find_node_by_name(NULL, "global-utilities");
328         if (node) {
329                 const u32 *prop = of_get_property(node, "reg", NULL);
330                 if (prop) {
331                         /*
332                          * Map and check POR Device Status Register 2
333                          * (PORDEVSR2) at 0xE0014
334                          */
335                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
336                         if (!reg)
337                                 printk(KERN_ERR
338                                        "Error: couldn't map PORDEVSR2\n");
339                         else
340                                 val = in_be32(reg) & 0x00000080; /* sec-cfg */
341                         iounmap(reg);
342                 }
343         }
344         if (node)
345                 of_node_put(node);
346 
347         return val;
348 }
349 
350 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
351                                           u32 prescaler, u32 *real_clk)
352 {
353         const struct mpc_i2c_divider *div = NULL;
354         u32 divider;
355         int i;
356 
357         if (clock == MPC_I2C_CLOCK_LEGACY) {
358                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
359                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
360                 return -EINVAL;
361         }
362 
363         /* Determine proper divider value */
364         if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
365                 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
366         if (!prescaler)
367                 prescaler = 1;
368 
369         divider = fsl_get_sys_freq() / clock / prescaler;
370 
371         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
372                  fsl_get_sys_freq(), clock, divider);
373 
374         /*
375          * We want to choose an FDR/DFSR that generates an I2C bus speed that
376          * is equal to or lower than the requested speed.
377          */
378         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
379                 div = &mpc_i2c_dividers_8xxx[i];
380                 if (div->divider >= divider)
381                         break;
382         }
383 
384         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
385         return div ? (int)div->fdr : -EINVAL;
386 }
387 
388 static void mpc_i2c_setup_8xxx(struct device_node *node,
389                                          struct mpc_i2c *i2c,
390                                          u32 clock, u32 prescaler)
391 {
392         int ret, fdr;
393 
394         if (clock == MPC_I2C_CLOCK_PRESERVE) {
395                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
396                         readb(i2c->base + MPC_I2C_DFSRR),
397                         readb(i2c->base + MPC_I2C_FDR));
398                 return;
399         }
400 
401         ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
402         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
403 
404         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
405         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
406 
407         if (ret >= 0)
408                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
409                          i2c->real_clk, fdr >> 8, fdr & 0xff);
410 }
411 
412 #else /* !CONFIG_FSL_SOC */
413 static void mpc_i2c_setup_8xxx(struct device_node *node,
414                                          struct mpc_i2c *i2c,
415                                          u32 clock, u32 prescaler)
416 {
417 }
418 #endif /* CONFIG_FSL_SOC */
419 
420 static void mpc_i2c_start(struct mpc_i2c *i2c)
421 {
422         /* Clear arbitration */
423         writeb(0, i2c->base + MPC_I2C_SR);
424         /* Start with MEN */
425         writeccr(i2c, CCR_MEN);
426 }
427 
428 static void mpc_i2c_stop(struct mpc_i2c *i2c)
429 {
430         writeccr(i2c, CCR_MEN);
431 }
432 
433 static int mpc_write(struct mpc_i2c *i2c, int target,
434                      const u8 *data, int length, int restart)
435 {
436         int i, result;
437         unsigned timeout = i2c->adap.timeout;
438         u32 flags = restart ? CCR_RSTA : 0;
439 
440         /* Start as master */
441         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
442         /* Write target byte */
443         writeb((target << 1), i2c->base + MPC_I2C_DR);
444 
445         result = i2c_wait(i2c, timeout, 1);
446         if (result < 0)
447                 return result;
448 
449         for (i = 0; i < length; i++) {
450                 /* Write data byte */
451                 writeb(data[i], i2c->base + MPC_I2C_DR);
452 
453                 result = i2c_wait(i2c, timeout, 1);
454                 if (result < 0)
455                         return result;
456         }
457 
458         return 0;
459 }
460 
461 static int mpc_read(struct mpc_i2c *i2c, int target,
462                     u8 *data, int length, int restart, bool recv_len)
463 {
464         unsigned timeout = i2c->adap.timeout;
465         int i, result;
466         u32 flags = restart ? CCR_RSTA : 0;
467 
468         /* Switch to read - restart */
469         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
470         /* Write target address byte - this time with the read flag set */
471         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
472 
473         result = i2c_wait(i2c, timeout, 1);
474         if (result < 0)
475                 return result;
476 
477         if (length) {
478                 if (length == 1 && !recv_len)
479                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
480                 else
481                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
482                 /* Dummy read */
483                 readb(i2c->base + MPC_I2C_DR);
484         }
485 
486         for (i = 0; i < length; i++) {
487                 u8 byte;
488 
489                 result = i2c_wait(i2c, timeout, 0);
490                 if (result < 0)
491                         return result;
492 
493                 /*
494                  * For block reads, we have to know the total length (1st byte)
495                  * before we can determine if we are done.
496                  */
497                 if (i || !recv_len) {
498                         /* Generate txack on next to last byte */
499                         if (i == length - 2)
500                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
501                                          | CCR_TXAK);
502                         /* Do not generate stop on last byte */
503                         if (i == length - 1)
504                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
505                                          | CCR_MTX);
506                 }
507 
508                 byte = readb(i2c->base + MPC_I2C_DR);
509 
510                 /*
511                  * Adjust length if first received byte is length.
512                  * The length is 1 length byte plus actually data length
513                  */
514                 if (i == 0 && recv_len) {
515                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
516                                 return -EPROTO;
517                         length += byte;
518                         /*
519                          * For block reads, generate txack here if data length
520                          * is 1 byte (total length is 2 bytes).
521                          */
522                         if (length == 2)
523                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
524                                          | CCR_TXAK);
525                 }
526                 data[i] = byte;
527         }
528 
529         return length;
530 }
531 
532 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
533 {
534         struct i2c_msg *pmsg;
535         int i;
536         int ret = 0;
537         unsigned long orig_jiffies = jiffies;
538         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
539 
540         mpc_i2c_start(i2c);
541 
542         /* Allow bus up to 1s to become not busy */
543         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
544                 if (signal_pending(current)) {
545                         dev_dbg(i2c->dev, "Interrupted\n");
546                         writeccr(i2c, 0);
547                         return -EINTR;
548                 }
549                 if (time_after(jiffies, orig_jiffies + HZ)) {
550                         u8 status = readb(i2c->base + MPC_I2C_SR);
551 
552                         dev_dbg(i2c->dev, "timeout\n");
553                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
554                                 writeb(status & ~CSR_MAL,
555                                        i2c->base + MPC_I2C_SR);
556                                 mpc_i2c_fixup(i2c);
557                         }
558                         return -EIO;
559                 }
560                 schedule();
561         }
562 
563         for (i = 0; ret >= 0 && i < num; i++) {
564                 pmsg = &msgs[i];
565                 dev_dbg(i2c->dev,
566                         "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
567                         pmsg->flags & I2C_M_RD ? "read" : "write",
568                         pmsg->len, pmsg->addr, i + 1, num);
569                 if (pmsg->flags & I2C_M_RD) {
570                         bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
571 
572                         ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
573                                        recv_len);
574                         if (recv_len && ret > 0)
575                                 pmsg->len = ret;
576                 } else {
577                         ret =
578                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
579                 }
580         }
581         mpc_i2c_stop(i2c); /* Initiate STOP */
582         orig_jiffies = jiffies;
583         /* Wait until STOP is seen, allow up to 1 s */
584         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
585                 if (time_after(jiffies, orig_jiffies + HZ)) {
586                         u8 status = readb(i2c->base + MPC_I2C_SR);
587 
588                         dev_dbg(i2c->dev, "timeout\n");
589                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
590                                 writeb(status & ~CSR_MAL,
591                                        i2c->base + MPC_I2C_SR);
592                                 mpc_i2c_fixup(i2c);
593                         }
594                         return -EIO;
595                 }
596                 cond_resched();
597         }
598         return (ret < 0) ? ret : num;
599 }
600 
601 static u32 mpc_functionality(struct i2c_adapter *adap)
602 {
603         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
604           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
605 }
606 
607 static const struct i2c_algorithm mpc_algo = {
608         .master_xfer = mpc_xfer,
609         .functionality = mpc_functionality,
610 };
611 
612 static struct i2c_adapter mpc_ops = {
613         .owner = THIS_MODULE,
614         .algo = &mpc_algo,
615         .timeout = HZ,
616 };
617 
618 static const struct of_device_id mpc_i2c_of_match[];
619 static int fsl_i2c_probe(struct platform_device *op)
620 {
621         const struct of_device_id *match;
622         struct mpc_i2c *i2c;
623         const u32 *prop;
624         u32 clock = MPC_I2C_CLOCK_LEGACY;
625         int result = 0;
626         int plen;
627         struct resource res;
628         struct clk *clk;
629         int err;
630 
631         match = of_match_device(mpc_i2c_of_match, &op->dev);
632         if (!match)
633                 return -EINVAL;
634 
635         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
636         if (!i2c)
637                 return -ENOMEM;
638 
639         i2c->dev = &op->dev; /* for debug and error output */
640 
641         init_waitqueue_head(&i2c->queue);
642 
643         i2c->base = of_iomap(op->dev.of_node, 0);
644         if (!i2c->base) {
645                 dev_err(i2c->dev, "failed to map controller\n");
646                 result = -ENOMEM;
647                 goto fail_map;
648         }
649 
650         i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
651         if (i2c->irq) { /* no i2c->irq implies polling */
652                 result = request_irq(i2c->irq, mpc_i2c_isr,
653                                      IRQF_SHARED, "i2c-mpc", i2c);
654                 if (result < 0) {
655                         dev_err(i2c->dev, "failed to attach interrupt\n");
656                         goto fail_request;
657                 }
658         }
659 
660         /*
661          * enable clock for the I2C peripheral (non fatal),
662          * keep a reference upon successful allocation
663          */
664         clk = devm_clk_get(&op->dev, NULL);
665         if (!IS_ERR(clk)) {
666                 err = clk_prepare_enable(clk);
667                 if (err) {
668                         dev_err(&op->dev, "failed to enable clock\n");
669                         goto fail_request;
670                 } else {
671                         i2c->clk_per = clk;
672                 }
673         }
674 
675         if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
676                 clock = MPC_I2C_CLOCK_PRESERVE;
677         } else {
678                 prop = of_get_property(op->dev.of_node, "clock-frequency",
679                                         &plen);
680                 if (prop && plen == sizeof(u32))
681                         clock = *prop;
682         }
683 
684         if (match->data) {
685                 const struct mpc_i2c_data *data = match->data;
686                 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
687         } else {
688                 /* Backwards compatibility */
689                 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
690                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
691         }
692 
693         prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
694         if (prop && plen == sizeof(u32)) {
695                 mpc_ops.timeout = *prop * HZ / 1000000;
696                 if (mpc_ops.timeout < 5)
697                         mpc_ops.timeout = 5;
698         }
699         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
700 
701         platform_set_drvdata(op, i2c);
702 
703         i2c->adap = mpc_ops;
704         of_address_to_resource(op->dev.of_node, 0, &res);
705         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
706                   "MPC adapter at 0x%llx", (unsigned long long)res.start);
707         i2c_set_adapdata(&i2c->adap, i2c);
708         i2c->adap.dev.parent = &op->dev;
709         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
710 
711         result = i2c_add_adapter(&i2c->adap);
712         if (result < 0) {
713                 dev_err(i2c->dev, "failed to add adapter\n");
714                 goto fail_add;
715         }
716 
717         return result;
718 
719  fail_add:
720         if (i2c->clk_per)
721                 clk_disable_unprepare(i2c->clk_per);
722         free_irq(i2c->irq, i2c);
723  fail_request:
724         irq_dispose_mapping(i2c->irq);
725         iounmap(i2c->base);
726  fail_map:
727         kfree(i2c);
728         return result;
729 };
730 
731 static int fsl_i2c_remove(struct platform_device *op)
732 {
733         struct mpc_i2c *i2c = platform_get_drvdata(op);
734 
735         i2c_del_adapter(&i2c->adap);
736 
737         if (i2c->clk_per)
738                 clk_disable_unprepare(i2c->clk_per);
739 
740         if (i2c->irq)
741                 free_irq(i2c->irq, i2c);
742 
743         irq_dispose_mapping(i2c->irq);
744         iounmap(i2c->base);
745         kfree(i2c);
746         return 0;
747 };
748 
749 #ifdef CONFIG_PM_SLEEP
750 static int mpc_i2c_suspend(struct device *dev)
751 {
752         struct mpc_i2c *i2c = dev_get_drvdata(dev);
753 
754         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
755         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
756 
757         return 0;
758 }
759 
760 static int mpc_i2c_resume(struct device *dev)
761 {
762         struct mpc_i2c *i2c = dev_get_drvdata(dev);
763 
764         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
765         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
766 
767         return 0;
768 }
769 
770 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
771 #define MPC_I2C_PM_OPS  (&mpc_i2c_pm_ops)
772 #else
773 #define MPC_I2C_PM_OPS  NULL
774 #endif
775 
776 static const struct mpc_i2c_data mpc_i2c_data_512x = {
777         .setup = mpc_i2c_setup_512x,
778 };
779 
780 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
781         .setup = mpc_i2c_setup_52xx,
782 };
783 
784 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
785         .setup = mpc_i2c_setup_8xxx,
786 };
787 
788 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
789         .setup = mpc_i2c_setup_8xxx,
790         .prescaler = 2,
791 };
792 
793 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
794         .setup = mpc_i2c_setup_8xxx,
795         .prescaler = 3,
796 };
797 
798 static const struct of_device_id mpc_i2c_of_match[] = {
799         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
800         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
801         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
802         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
803         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
804         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
805         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
806         /* Backward compatibility */
807         {.compatible = "fsl-i2c", },
808         {},
809 };
810 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
811 
812 /* Structure for a device driver */
813 static struct platform_driver mpc_i2c_driver = {
814         .probe          = fsl_i2c_probe,
815         .remove         = fsl_i2c_remove,
816         .driver = {
817                 .owner = THIS_MODULE,
818                 .name = DRV_NAME,
819                 .of_match_table = mpc_i2c_of_match,
820                 .pm = MPC_I2C_PM_OPS,
821         },
822 };
823 
824 module_platform_driver(mpc_i2c_driver);
825 
826 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
827 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
828                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
829 MODULE_LICENSE("GPL");
830 

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