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Linux/drivers/i2c/busses/i2c-isch.c

  1 /*
  2     i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
  3     - Based on i2c-piix4.c
  4     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
  5     Philip Edelbrock <phil@netroedge.com>
  6     - Intel SCH support
  7     Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
  8 
  9     This program is free software; you can redistribute it and/or modify
 10     it under the terms of the GNU General Public License version 2 as
 11     published by the Free Software Foundation.
 12 
 13     This program is distributed in the hope that it will be useful,
 14     but WITHOUT ANY WARRANTY; without even the implied warranty of
 15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16     GNU General Public License for more details.
 17 
 18     You should have received a copy of the GNU General Public License
 19     along with this program; if not, write to the Free Software
 20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21 */
 22 
 23 /*
 24    Supports:
 25         Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
 26    Note: we assume there can only be one device, with one SMBus interface.
 27 */
 28 
 29 #include <linux/module.h>
 30 #include <linux/platform_device.h>
 31 #include <linux/kernel.h>
 32 #include <linux/delay.h>
 33 #include <linux/stddef.h>
 34 #include <linux/ioport.h>
 35 #include <linux/i2c.h>
 36 #include <linux/io.h>
 37 #include <linux/acpi.h>
 38 
 39 /* SCH SMBus address offsets */
 40 #define SMBHSTCNT       (0 + sch_smba)
 41 #define SMBHSTSTS       (1 + sch_smba)
 42 #define SMBHSTCLK       (2 + sch_smba)
 43 #define SMBHSTADD       (4 + sch_smba) /* TSA */
 44 #define SMBHSTCMD       (5 + sch_smba)
 45 #define SMBHSTDAT0      (6 + sch_smba)
 46 #define SMBHSTDAT1      (7 + sch_smba)
 47 #define SMBBLKDAT       (0x20 + sch_smba)
 48 
 49 /* Other settings */
 50 #define MAX_RETRIES     5000
 51 
 52 /* I2C constants */
 53 #define SCH_QUICK               0x00
 54 #define SCH_BYTE                0x01
 55 #define SCH_BYTE_DATA           0x02
 56 #define SCH_WORD_DATA           0x03
 57 #define SCH_BLOCK_DATA          0x05
 58 
 59 static unsigned short sch_smba;
 60 static struct i2c_adapter sch_adapter;
 61 static int backbone_speed = 33000; /* backbone speed in kHz */
 62 module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
 63 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
 64 
 65 /*
 66  * Start the i2c transaction -- the i2c_access will prepare the transaction
 67  * and this function will execute it.
 68  * return 0 for success and others for failure.
 69  */
 70 static int sch_transaction(void)
 71 {
 72         int temp;
 73         int result = 0;
 74         int retries = 0;
 75 
 76         dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 77                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
 78                 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
 79                 inb(SMBHSTDAT1));
 80 
 81         /* Make sure the SMBus host is ready to start transmitting */
 82         temp = inb(SMBHSTSTS) & 0x0f;
 83         if (temp) {
 84                 /* Can not be busy since we checked it in sch_access */
 85                 if (temp & 0x01) {
 86                         dev_dbg(&sch_adapter.dev, "Completion (%02x). "
 87                                 "Clear...\n", temp);
 88                 }
 89                 if (temp & 0x06) {
 90                         dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
 91                                 "Resetting...\n", temp);
 92                 }
 93                 outb(temp, SMBHSTSTS);
 94                 temp = inb(SMBHSTSTS) & 0x0f;
 95                 if (temp) {
 96                         dev_err(&sch_adapter.dev,
 97                                 "SMBus is not ready: (%02x)\n", temp);
 98                         return -EAGAIN;
 99                 }
100         }
101 
102         /* start the transaction by setting bit 4 */
103         outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
104 
105         do {
106                 usleep_range(100, 200);
107                 temp = inb(SMBHSTSTS) & 0x0f;
108         } while ((temp & 0x08) && (retries++ < MAX_RETRIES));
109 
110         /* If the SMBus is still busy, we give up */
111         if (retries > MAX_RETRIES) {
112                 dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
113                 result = -ETIMEDOUT;
114         }
115         if (temp & 0x04) {
116                 result = -EIO;
117                 dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
118                         "locked until next hard reset. (sorry!)\n");
119                 /* Clock stops and slave is stuck in mid-transmission */
120         } else if (temp & 0x02) {
121                 result = -EIO;
122                 dev_err(&sch_adapter.dev, "Error: no response!\n");
123         } else if (temp & 0x01) {
124                 dev_dbg(&sch_adapter.dev, "Post complete!\n");
125                 outb(temp, SMBHSTSTS);
126                 temp = inb(SMBHSTSTS) & 0x07;
127                 if (temp & 0x06) {
128                         /* Completion clear failed */
129                         dev_dbg(&sch_adapter.dev, "Failed reset at end of "
130                                 "transaction (%02x), Bus error!\n", temp);
131                 }
132         } else {
133                 result = -ENXIO;
134                 dev_dbg(&sch_adapter.dev, "No such address.\n");
135         }
136         dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
137                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
138                 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
139                 inb(SMBHSTDAT1));
140         return result;
141 }
142 
143 /*
144  * This is the main access entry for i2c-sch access
145  * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
146  * (0 for read and 1 for write), size is i2c transaction type and data is the
147  * union of transaction for data to be transferred or data read from bus.
148  * return 0 for success and others for failure.
149  */
150 static s32 sch_access(struct i2c_adapter *adap, u16 addr,
151                  unsigned short flags, char read_write,
152                  u8 command, int size, union i2c_smbus_data *data)
153 {
154         int i, len, temp, rc;
155 
156         /* Make sure the SMBus host is not busy */
157         temp = inb(SMBHSTSTS) & 0x0f;
158         if (temp & 0x08) {
159                 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
160                 return -EAGAIN;
161         }
162         temp = inw(SMBHSTCLK);
163         if (!temp) {
164                 /*
165                  * We can't determine if we have 33 or 25 MHz clock for
166                  * SMBus, so expect 33 MHz and calculate a bus clock of
167                  * 100 kHz. If we actually run at 25 MHz the bus will be
168                  * run ~75 kHz instead which should do no harm.
169                  */
170                 dev_notice(&sch_adapter.dev,
171                         "Clock divider unitialized. Setting defaults\n");
172                 outw(backbone_speed / (4 * 100), SMBHSTCLK);
173         }
174 
175         dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
176                 (read_write)?"READ":"WRITE");
177         switch (size) {
178         case I2C_SMBUS_QUICK:
179                 outb((addr << 1) | read_write, SMBHSTADD);
180                 size = SCH_QUICK;
181                 break;
182         case I2C_SMBUS_BYTE:
183                 outb((addr << 1) | read_write, SMBHSTADD);
184                 if (read_write == I2C_SMBUS_WRITE)
185                         outb(command, SMBHSTCMD);
186                 size = SCH_BYTE;
187                 break;
188         case I2C_SMBUS_BYTE_DATA:
189                 outb((addr << 1) | read_write, SMBHSTADD);
190                 outb(command, SMBHSTCMD);
191                 if (read_write == I2C_SMBUS_WRITE)
192                         outb(data->byte, SMBHSTDAT0);
193                 size = SCH_BYTE_DATA;
194                 break;
195         case I2C_SMBUS_WORD_DATA:
196                 outb((addr << 1) | read_write, SMBHSTADD);
197                 outb(command, SMBHSTCMD);
198                 if (read_write == I2C_SMBUS_WRITE) {
199                         outb(data->word & 0xff, SMBHSTDAT0);
200                         outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
201                 }
202                 size = SCH_WORD_DATA;
203                 break;
204         case I2C_SMBUS_BLOCK_DATA:
205                 outb((addr << 1) | read_write, SMBHSTADD);
206                 outb(command, SMBHSTCMD);
207                 if (read_write == I2C_SMBUS_WRITE) {
208                         len = data->block[0];
209                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
210                                 return -EINVAL;
211                         outb(len, SMBHSTDAT0);
212                         for (i = 1; i <= len; i++)
213                                 outb(data->block[i], SMBBLKDAT+i-1);
214                 }
215                 size = SCH_BLOCK_DATA;
216                 break;
217         default:
218                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
219                 return -EOPNOTSUPP;
220         }
221         dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
222         outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
223 
224         rc = sch_transaction();
225         if (rc) /* Error in transaction */
226                 return rc;
227 
228         if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
229                 return 0;
230 
231         switch (size) {
232         case SCH_BYTE:
233         case SCH_BYTE_DATA:
234                 data->byte = inb(SMBHSTDAT0);
235                 break;
236         case SCH_WORD_DATA:
237                 data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
238                 break;
239         case SCH_BLOCK_DATA:
240                 data->block[0] = inb(SMBHSTDAT0);
241                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
242                         return -EPROTO;
243                 for (i = 1; i <= data->block[0]; i++)
244                         data->block[i] = inb(SMBBLKDAT+i-1);
245                 break;
246         }
247         return 0;
248 }
249 
250 static u32 sch_func(struct i2c_adapter *adapter)
251 {
252         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
253             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
254             I2C_FUNC_SMBUS_BLOCK_DATA;
255 }
256 
257 static const struct i2c_algorithm smbus_algorithm = {
258         .smbus_xfer     = sch_access,
259         .functionality  = sch_func,
260 };
261 
262 static struct i2c_adapter sch_adapter = {
263         .owner          = THIS_MODULE,
264         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
265         .algo           = &smbus_algorithm,
266 };
267 
268 static int smbus_sch_probe(struct platform_device *dev)
269 {
270         struct resource *res;
271         int retval;
272 
273         res = platform_get_resource(dev, IORESOURCE_IO, 0);
274         if (!res)
275                 return -EBUSY;
276 
277         if (!devm_request_region(&dev->dev, res->start, resource_size(res),
278                                  dev->name)) {
279                 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
280                         sch_smba);
281                 return -EBUSY;
282         }
283 
284         sch_smba = res->start;
285 
286         dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
287 
288         /* set up the sysfs linkage to our parent device */
289         sch_adapter.dev.parent = &dev->dev;
290 
291         snprintf(sch_adapter.name, sizeof(sch_adapter.name),
292                 "SMBus SCH adapter at %04x", sch_smba);
293 
294         retval = i2c_add_adapter(&sch_adapter);
295         if (retval) {
296                 dev_err(&dev->dev, "Couldn't register adapter!\n");
297                 sch_smba = 0;
298         }
299 
300         return retval;
301 }
302 
303 static int smbus_sch_remove(struct platform_device *pdev)
304 {
305         if (sch_smba) {
306                 i2c_del_adapter(&sch_adapter);
307                 sch_smba = 0;
308         }
309 
310         return 0;
311 }
312 
313 static struct platform_driver smbus_sch_driver = {
314         .driver = {
315                 .name = "isch_smbus",
316                 .owner = THIS_MODULE,
317         },
318         .probe          = smbus_sch_probe,
319         .remove         = smbus_sch_remove,
320 };
321 
322 module_platform_driver(smbus_sch_driver);
323 
324 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
325 MODULE_DESCRIPTION("Intel SCH SMBus driver");
326 MODULE_LICENSE("GPL");
327 MODULE_ALIAS("platform:isch_smbus");
328 

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