Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

  1 /**************************************************************************
  2  *
  3  * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA
  4  * All Rights Reserved.
  5  *
  6  * Permission is hereby granted, free of charge, to any person obtaining a
  7  * copy of this software and associated documentation files (the
  8  * "Software"), to deal in the Software without restriction, including
  9  * without limitation the rights to use, copy, modify, merge, publish,
 10  * distribute, sub license, and/or sell copies of the Software, and to
 11  * permit persons to whom the Software is furnished to do so, subject to
 12  * the following conditions:
 13  *
 14  * The above copyright notice and this permission notice (including the
 15  * next paragraph) shall be included in all copies or substantial portions
 16  * of the Software.
 17  *
 18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
 25  *
 26  **************************************************************************/
 27 #include <linux/module.h>
 28 #include <linux/console.h>
 29 
 30 #include <drm/drmP.h>
 31 #include "vmwgfx_drv.h"
 32 #include "vmwgfx_binding.h"
 33 #include <drm/ttm/ttm_placement.h>
 34 #include <drm/ttm/ttm_bo_driver.h>
 35 #include <drm/ttm/ttm_object.h>
 36 #include <drm/ttm/ttm_module.h>
 37 #include <linux/dma_remapping.h>
 38 
 39 #define VMWGFX_DRIVER_NAME "vmwgfx"
 40 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
 41 #define VMWGFX_CHIP_SVGAII 0
 42 #define VMW_FB_RESERVATION 0
 43 
 44 #define VMW_MIN_INITIAL_WIDTH 800
 45 #define VMW_MIN_INITIAL_HEIGHT 600
 46 
 47 #ifndef VMWGFX_GIT_VERSION
 48 #define VMWGFX_GIT_VERSION "Unknown"
 49 #endif
 50 
 51 #define VMWGFX_REPO "In Tree"
 52 
 53 
 54 /**
 55  * Fully encoded drm commands. Might move to vmw_drm.h
 56  */
 57 
 58 #define DRM_IOCTL_VMW_GET_PARAM                                 \
 59         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
 60                  struct drm_vmw_getparam_arg)
 61 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
 62         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
 63                 union drm_vmw_alloc_dmabuf_arg)
 64 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
 65         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
 66                 struct drm_vmw_unref_dmabuf_arg)
 67 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
 68         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
 69                  struct drm_vmw_cursor_bypass_arg)
 70 
 71 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
 72         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
 73                  struct drm_vmw_control_stream_arg)
 74 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
 75         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
 76                  struct drm_vmw_stream_arg)
 77 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
 78         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
 79                  struct drm_vmw_stream_arg)
 80 
 81 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
 82         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
 83                 struct drm_vmw_context_arg)
 84 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
 85         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
 86                 struct drm_vmw_context_arg)
 87 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
 88         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
 89                  union drm_vmw_surface_create_arg)
 90 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
 91         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
 92                  struct drm_vmw_surface_arg)
 93 #define DRM_IOCTL_VMW_REF_SURFACE                               \
 94         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
 95                  union drm_vmw_surface_reference_arg)
 96 #define DRM_IOCTL_VMW_EXECBUF                                   \
 97         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
 98                 struct drm_vmw_execbuf_arg)
 99 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
100         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
101                  struct drm_vmw_get_3d_cap_arg)
102 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
103         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
104                  struct drm_vmw_fence_wait_arg)
105 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
106         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
107                  struct drm_vmw_fence_signaled_arg)
108 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
109         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
110                  struct drm_vmw_fence_arg)
111 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
112         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
113                  struct drm_vmw_fence_event_arg)
114 #define DRM_IOCTL_VMW_PRESENT                                   \
115         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
116                  struct drm_vmw_present_arg)
117 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
118         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
119                  struct drm_vmw_present_readback_arg)
120 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
121         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
122                  struct drm_vmw_update_layout_arg)
123 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
124         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
125                  struct drm_vmw_shader_create_arg)
126 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
127         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
128                  struct drm_vmw_shader_arg)
129 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
130         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
131                  union drm_vmw_gb_surface_create_arg)
132 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
133         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
134                  union drm_vmw_gb_surface_reference_arg)
135 #define DRM_IOCTL_VMW_SYNCCPU                                   \
136         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
137                  struct drm_vmw_synccpu_arg)
138 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT                   \
139         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,    \
140                 struct drm_vmw_context_arg)
141 
142 /**
143  * The core DRM version of this macro doesn't account for
144  * DRM_COMMAND_BASE.
145  */
146 
147 #define VMW_IOCTL_DEF(ioctl, func, flags) \
148   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
149 
150 /**
151  * Ioctl definitions.
152  */
153 
154 static const struct drm_ioctl_desc vmw_ioctls[] = {
155         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
156                       DRM_AUTH | DRM_RENDER_ALLOW),
157         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
158                       DRM_AUTH | DRM_RENDER_ALLOW),
159         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
160                       DRM_RENDER_ALLOW),
161         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
162                       vmw_kms_cursor_bypass_ioctl,
163                       DRM_MASTER | DRM_CONTROL_ALLOW),
164 
165         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
166                       DRM_MASTER | DRM_CONTROL_ALLOW),
167         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
168                       DRM_MASTER | DRM_CONTROL_ALLOW),
169         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
170                       DRM_MASTER | DRM_CONTROL_ALLOW),
171 
172         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
173                       DRM_AUTH | DRM_RENDER_ALLOW),
174         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
175                       DRM_RENDER_ALLOW),
176         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
177                       DRM_AUTH | DRM_RENDER_ALLOW),
178         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
179                       DRM_RENDER_ALLOW),
180         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
181                       DRM_AUTH | DRM_RENDER_ALLOW),
182         VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
183                       DRM_RENDER_ALLOW),
184         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
185                       DRM_RENDER_ALLOW),
186         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
187                       vmw_fence_obj_signaled_ioctl,
188                       DRM_RENDER_ALLOW),
189         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
190                       DRM_RENDER_ALLOW),
191         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
192                       DRM_AUTH | DRM_RENDER_ALLOW),
193         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
194                       DRM_AUTH | DRM_RENDER_ALLOW),
195 
196         /* these allow direct access to the framebuffers mark as master only */
197         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
198                       DRM_MASTER | DRM_AUTH),
199         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
200                       vmw_present_readback_ioctl,
201                       DRM_MASTER | DRM_AUTH),
202         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
203                       vmw_kms_update_layout_ioctl,
204                       DRM_MASTER | DRM_CONTROL_ALLOW),
205         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
206                       vmw_shader_define_ioctl,
207                       DRM_AUTH | DRM_RENDER_ALLOW),
208         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
209                       vmw_shader_destroy_ioctl,
210                       DRM_RENDER_ALLOW),
211         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
212                       vmw_gb_surface_define_ioctl,
213                       DRM_AUTH | DRM_RENDER_ALLOW),
214         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
215                       vmw_gb_surface_reference_ioctl,
216                       DRM_AUTH | DRM_RENDER_ALLOW),
217         VMW_IOCTL_DEF(VMW_SYNCCPU,
218                       vmw_user_dmabuf_synccpu_ioctl,
219                       DRM_RENDER_ALLOW),
220         VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
221                       vmw_extended_context_define_ioctl,
222                       DRM_AUTH | DRM_RENDER_ALLOW),
223 };
224 
225 static struct pci_device_id vmw_pci_id_list[] = {
226         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
227         {0, 0, 0}
228 };
229 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
230 
231 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
232 static int vmw_force_iommu;
233 static int vmw_restrict_iommu;
234 static int vmw_force_coherent;
235 static int vmw_restrict_dma_mask;
236 static int vmw_assume_16bpp;
237 
238 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
239 static void vmw_master_init(struct vmw_master *);
240 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
241                               void *ptr);
242 
243 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
244 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
245 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
246 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
247 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
248 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
249 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
250 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
251 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
252 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
253 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
254 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
255 
256 
257 static void vmw_print_capabilities(uint32_t capabilities)
258 {
259         DRM_INFO("Capabilities:\n");
260         if (capabilities & SVGA_CAP_RECT_COPY)
261                 DRM_INFO("  Rect copy.\n");
262         if (capabilities & SVGA_CAP_CURSOR)
263                 DRM_INFO("  Cursor.\n");
264         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
265                 DRM_INFO("  Cursor bypass.\n");
266         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
267                 DRM_INFO("  Cursor bypass 2.\n");
268         if (capabilities & SVGA_CAP_8BIT_EMULATION)
269                 DRM_INFO("  8bit emulation.\n");
270         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
271                 DRM_INFO("  Alpha cursor.\n");
272         if (capabilities & SVGA_CAP_3D)
273                 DRM_INFO("  3D.\n");
274         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
275                 DRM_INFO("  Extended Fifo.\n");
276         if (capabilities & SVGA_CAP_MULTIMON)
277                 DRM_INFO("  Multimon.\n");
278         if (capabilities & SVGA_CAP_PITCHLOCK)
279                 DRM_INFO("  Pitchlock.\n");
280         if (capabilities & SVGA_CAP_IRQMASK)
281                 DRM_INFO("  Irq mask.\n");
282         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
283                 DRM_INFO("  Display Topology.\n");
284         if (capabilities & SVGA_CAP_GMR)
285                 DRM_INFO("  GMR.\n");
286         if (capabilities & SVGA_CAP_TRACES)
287                 DRM_INFO("  Traces.\n");
288         if (capabilities & SVGA_CAP_GMR2)
289                 DRM_INFO("  GMR2.\n");
290         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
291                 DRM_INFO("  Screen Object 2.\n");
292         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
293                 DRM_INFO("  Command Buffers.\n");
294         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
295                 DRM_INFO("  Command Buffers 2.\n");
296         if (capabilities & SVGA_CAP_GBOBJECTS)
297                 DRM_INFO("  Guest Backed Resources.\n");
298         if (capabilities & SVGA_CAP_DX)
299                 DRM_INFO("  DX Features.\n");
300 }
301 
302 /**
303  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
304  *
305  * @dev_priv: A device private structure.
306  *
307  * This function creates a small buffer object that holds the query
308  * result for dummy queries emitted as query barriers.
309  * The function will then map the first page and initialize a pending
310  * occlusion query result structure, Finally it will unmap the buffer.
311  * No interruptible waits are done within this function.
312  *
313  * Returns an error if bo creation or initialization fails.
314  */
315 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
316 {
317         int ret;
318         struct vmw_dma_buffer *vbo;
319         struct ttm_bo_kmap_obj map;
320         volatile SVGA3dQueryResult *result;
321         bool dummy;
322 
323         /*
324          * Create the vbo as pinned, so that a tryreserve will
325          * immediately succeed. This is because we're the only
326          * user of the bo currently.
327          */
328         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
329         if (!vbo)
330                 return -ENOMEM;
331 
332         ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
333                               &vmw_sys_ne_placement, false,
334                               &vmw_dmabuf_bo_free);
335         if (unlikely(ret != 0))
336                 return ret;
337 
338         ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
339         BUG_ON(ret != 0);
340         vmw_bo_pin_reserved(vbo, true);
341 
342         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
343         if (likely(ret == 0)) {
344                 result = ttm_kmap_obj_virtual(&map, &dummy);
345                 result->totalSize = sizeof(*result);
346                 result->state = SVGA3D_QUERYSTATE_PENDING;
347                 result->result32 = 0xff;
348                 ttm_bo_kunmap(&map);
349         }
350         vmw_bo_pin_reserved(vbo, false);
351         ttm_bo_unreserve(&vbo->base);
352 
353         if (unlikely(ret != 0)) {
354                 DRM_ERROR("Dummy query buffer map failed.\n");
355                 vmw_dmabuf_unreference(&vbo);
356         } else
357                 dev_priv->dummy_query_bo = vbo;
358 
359         return ret;
360 }
361 
362 /**
363  * vmw_request_device_late - Perform late device setup
364  *
365  * @dev_priv: Pointer to device private.
366  *
367  * This function performs setup of otables and enables large command
368  * buffer submission. These tasks are split out to a separate function
369  * because it reverts vmw_release_device_early and is intended to be used
370  * by an error path in the hibernation code.
371  */
372 static int vmw_request_device_late(struct vmw_private *dev_priv)
373 {
374         int ret;
375 
376         if (dev_priv->has_mob) {
377                 ret = vmw_otables_setup(dev_priv);
378                 if (unlikely(ret != 0)) {
379                         DRM_ERROR("Unable to initialize "
380                                   "guest Memory OBjects.\n");
381                         return ret;
382                 }
383         }
384 
385         if (dev_priv->cman) {
386                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
387                                                256*4096, 2*4096);
388                 if (ret) {
389                         struct vmw_cmdbuf_man *man = dev_priv->cman;
390 
391                         dev_priv->cman = NULL;
392                         vmw_cmdbuf_man_destroy(man);
393                 }
394         }
395 
396         return 0;
397 }
398 
399 static int vmw_request_device(struct vmw_private *dev_priv)
400 {
401         int ret;
402 
403         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
404         if (unlikely(ret != 0)) {
405                 DRM_ERROR("Unable to initialize FIFO.\n");
406                 return ret;
407         }
408         vmw_fence_fifo_up(dev_priv->fman);
409         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
410         if (IS_ERR(dev_priv->cman)) {
411                 dev_priv->cman = NULL;
412                 dev_priv->has_dx = false;
413         }
414 
415         ret = vmw_request_device_late(dev_priv);
416         if (ret)
417                 goto out_no_mob;
418 
419         ret = vmw_dummy_query_bo_create(dev_priv);
420         if (unlikely(ret != 0))
421                 goto out_no_query_bo;
422 
423         return 0;
424 
425 out_no_query_bo:
426         if (dev_priv->cman)
427                 vmw_cmdbuf_remove_pool(dev_priv->cman);
428         if (dev_priv->has_mob) {
429                 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
430                 vmw_otables_takedown(dev_priv);
431         }
432         if (dev_priv->cman)
433                 vmw_cmdbuf_man_destroy(dev_priv->cman);
434 out_no_mob:
435         vmw_fence_fifo_down(dev_priv->fman);
436         vmw_fifo_release(dev_priv, &dev_priv->fifo);
437         return ret;
438 }
439 
440 /**
441  * vmw_release_device_early - Early part of fifo takedown.
442  *
443  * @dev_priv: Pointer to device private struct.
444  *
445  * This is the first part of command submission takedown, to be called before
446  * buffer management is taken down.
447  */
448 static void vmw_release_device_early(struct vmw_private *dev_priv)
449 {
450         /*
451          * Previous destructions should've released
452          * the pinned bo.
453          */
454 
455         BUG_ON(dev_priv->pinned_bo != NULL);
456 
457         vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
458         if (dev_priv->cman)
459                 vmw_cmdbuf_remove_pool(dev_priv->cman);
460 
461         if (dev_priv->has_mob) {
462                 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
463                 vmw_otables_takedown(dev_priv);
464         }
465 }
466 
467 /**
468  * vmw_release_device_late - Late part of fifo takedown.
469  *
470  * @dev_priv: Pointer to device private struct.
471  *
472  * This is the last part of the command submission takedown, to be called when
473  * command submission is no longer needed. It may wait on pending fences.
474  */
475 static void vmw_release_device_late(struct vmw_private *dev_priv)
476 {
477         vmw_fence_fifo_down(dev_priv->fman);
478         if (dev_priv->cman)
479                 vmw_cmdbuf_man_destroy(dev_priv->cman);
480 
481         vmw_fifo_release(dev_priv, &dev_priv->fifo);
482 }
483 
484 /**
485  * Sets the initial_[width|height] fields on the given vmw_private.
486  *
487  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
488  * clamping the value to fb_max_[width|height] fields and the
489  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
490  * If the values appear to be invalid, set them to
491  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
492  */
493 static void vmw_get_initial_size(struct vmw_private *dev_priv)
494 {
495         uint32_t width;
496         uint32_t height;
497 
498         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
499         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
500 
501         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
502         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
503 
504         if (width > dev_priv->fb_max_width ||
505             height > dev_priv->fb_max_height) {
506 
507                 /*
508                  * This is a host error and shouldn't occur.
509                  */
510 
511                 width = VMW_MIN_INITIAL_WIDTH;
512                 height = VMW_MIN_INITIAL_HEIGHT;
513         }
514 
515         dev_priv->initial_width = width;
516         dev_priv->initial_height = height;
517 }
518 
519 /**
520  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
521  * system.
522  *
523  * @dev_priv: Pointer to a struct vmw_private
524  *
525  * This functions tries to determine the IOMMU setup and what actions
526  * need to be taken by the driver to make system pages visible to the
527  * device.
528  * If this function decides that DMA is not possible, it returns -EINVAL.
529  * The driver may then try to disable features of the device that require
530  * DMA.
531  */
532 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
533 {
534         static const char *names[vmw_dma_map_max] = {
535                 [vmw_dma_phys] = "Using physical TTM page addresses.",
536                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
537                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
538                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
539 #ifdef CONFIG_X86
540         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
541 
542 #ifdef CONFIG_INTEL_IOMMU
543         if (intel_iommu_enabled) {
544                 dev_priv->map_mode = vmw_dma_map_populate;
545                 goto out_fixup;
546         }
547 #endif
548 
549         if (!(vmw_force_iommu || vmw_force_coherent)) {
550                 dev_priv->map_mode = vmw_dma_phys;
551                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
552                 return 0;
553         }
554 
555         dev_priv->map_mode = vmw_dma_map_populate;
556 
557         if (dma_ops->sync_single_for_cpu)
558                 dev_priv->map_mode = vmw_dma_alloc_coherent;
559 #ifdef CONFIG_SWIOTLB
560         if (swiotlb_nr_tbl() == 0)
561                 dev_priv->map_mode = vmw_dma_map_populate;
562 #endif
563 
564 #ifdef CONFIG_INTEL_IOMMU
565 out_fixup:
566 #endif
567         if (dev_priv->map_mode == vmw_dma_map_populate &&
568             vmw_restrict_iommu)
569                 dev_priv->map_mode = vmw_dma_map_bind;
570 
571         if (vmw_force_coherent)
572                 dev_priv->map_mode = vmw_dma_alloc_coherent;
573 
574 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
575         /*
576          * No coherent page pool
577          */
578         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
579                 return -EINVAL;
580 #endif
581 
582 #else /* CONFIG_X86 */
583         dev_priv->map_mode = vmw_dma_map_populate;
584 #endif /* CONFIG_X86 */
585 
586         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
587 
588         return 0;
589 }
590 
591 /**
592  * vmw_dma_masks - set required page- and dma masks
593  *
594  * @dev: Pointer to struct drm-device
595  *
596  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
597  * restriction also for 64-bit systems.
598  */
599 #ifdef CONFIG_INTEL_IOMMU
600 static int vmw_dma_masks(struct vmw_private *dev_priv)
601 {
602         struct drm_device *dev = dev_priv->dev;
603 
604         if (intel_iommu_enabled &&
605             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
606                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
607                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
608         }
609         return 0;
610 }
611 #else
612 static int vmw_dma_masks(struct vmw_private *dev_priv)
613 {
614         return 0;
615 }
616 #endif
617 
618 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
619 {
620         struct vmw_private *dev_priv;
621         int ret;
622         uint32_t svga_id;
623         enum vmw_res_type i;
624         bool refuse_dma = false;
625         char host_log[100] = {0};
626 
627         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
628         if (unlikely(dev_priv == NULL)) {
629                 DRM_ERROR("Failed allocating a device private struct.\n");
630                 return -ENOMEM;
631         }
632 
633         pci_set_master(dev->pdev);
634 
635         dev_priv->dev = dev;
636         dev_priv->vmw_chipset = chipset;
637         dev_priv->last_read_seqno = (uint32_t) -100;
638         mutex_init(&dev_priv->cmdbuf_mutex);
639         mutex_init(&dev_priv->release_mutex);
640         mutex_init(&dev_priv->binding_mutex);
641         mutex_init(&dev_priv->global_kms_state_mutex);
642         rwlock_init(&dev_priv->resource_lock);
643         ttm_lock_init(&dev_priv->reservation_sem);
644         spin_lock_init(&dev_priv->hw_lock);
645         spin_lock_init(&dev_priv->waiter_lock);
646         spin_lock_init(&dev_priv->cap_lock);
647         spin_lock_init(&dev_priv->svga_lock);
648 
649         for (i = vmw_res_context; i < vmw_res_max; ++i) {
650                 idr_init(&dev_priv->res_idr[i]);
651                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
652         }
653 
654         mutex_init(&dev_priv->init_mutex);
655         init_waitqueue_head(&dev_priv->fence_queue);
656         init_waitqueue_head(&dev_priv->fifo_queue);
657         dev_priv->fence_queue_waiters = 0;
658         dev_priv->fifo_queue_waiters = 0;
659 
660         dev_priv->used_memory_size = 0;
661 
662         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
663         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
664         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
665 
666         dev_priv->assume_16bpp = !!vmw_assume_16bpp;
667 
668         dev_priv->enable_fb = enable_fbdev;
669 
670         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
671         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
672         if (svga_id != SVGA_ID_2) {
673                 ret = -ENOSYS;
674                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
675                 goto out_err0;
676         }
677 
678         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
679         ret = vmw_dma_select_mode(dev_priv);
680         if (unlikely(ret != 0)) {
681                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
682                 refuse_dma = true;
683         }
684 
685         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
686         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
687         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
688         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
689 
690         vmw_get_initial_size(dev_priv);
691 
692         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
693                 dev_priv->max_gmr_ids =
694                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
695                 dev_priv->max_gmr_pages =
696                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
697                 dev_priv->memory_size =
698                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
699                 dev_priv->memory_size -= dev_priv->vram_size;
700         } else {
701                 /*
702                  * An arbitrary limit of 512MiB on surface
703                  * memory. But all HWV8 hardware supports GMR2.
704                  */
705                 dev_priv->memory_size = 512*1024*1024;
706         }
707         dev_priv->max_mob_pages = 0;
708         dev_priv->max_mob_size = 0;
709         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
710                 uint64_t mem_size =
711                         vmw_read(dev_priv,
712                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
713 
714                 /*
715                  * Workaround for low memory 2D VMs to compensate for the
716                  * allocation taken by fbdev
717                  */
718                 if (!(dev_priv->capabilities & SVGA_CAP_3D))
719                         mem_size *= 2;
720 
721                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
722                 dev_priv->prim_bb_mem =
723                         vmw_read(dev_priv,
724                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
725                 dev_priv->max_mob_size =
726                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
727                 dev_priv->stdu_max_width =
728                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
729                 dev_priv->stdu_max_height =
730                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
731 
732                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
733                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
734                 dev_priv->texture_max_width = vmw_read(dev_priv,
735                                                        SVGA_REG_DEV_CAP);
736                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
737                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
738                 dev_priv->texture_max_height = vmw_read(dev_priv,
739                                                         SVGA_REG_DEV_CAP);
740         } else {
741                 dev_priv->texture_max_width = 8192;
742                 dev_priv->texture_max_height = 8192;
743                 dev_priv->prim_bb_mem = dev_priv->vram_size;
744         }
745 
746         vmw_print_capabilities(dev_priv->capabilities);
747 
748         ret = vmw_dma_masks(dev_priv);
749         if (unlikely(ret != 0))
750                 goto out_err0;
751 
752         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
753                 DRM_INFO("Max GMR ids is %u\n",
754                          (unsigned)dev_priv->max_gmr_ids);
755                 DRM_INFO("Max number of GMR pages is %u\n",
756                          (unsigned)dev_priv->max_gmr_pages);
757                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
758                          (unsigned)dev_priv->memory_size / 1024);
759         }
760         DRM_INFO("Maximum display memory size is %u kiB\n",
761                  dev_priv->prim_bb_mem / 1024);
762         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
763                  dev_priv->vram_start, dev_priv->vram_size / 1024);
764         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
765                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
766 
767         ret = vmw_ttm_global_init(dev_priv);
768         if (unlikely(ret != 0))
769                 goto out_err0;
770 
771 
772         vmw_master_init(&dev_priv->fbdev_master);
773         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
774         dev_priv->active_master = &dev_priv->fbdev_master;
775 
776         dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
777                                        dev_priv->mmio_size, MEMREMAP_WB);
778 
779         if (unlikely(dev_priv->mmio_virt == NULL)) {
780                 ret = -ENOMEM;
781                 DRM_ERROR("Failed mapping MMIO.\n");
782                 goto out_err3;
783         }
784 
785         /* Need mmio memory to check for fifo pitchlock cap. */
786         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
787             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
788             !vmw_fifo_have_pitchlock(dev_priv)) {
789                 ret = -ENOSYS;
790                 DRM_ERROR("Hardware has no pitchlock\n");
791                 goto out_err4;
792         }
793 
794         dev_priv->tdev = ttm_object_device_init
795                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
796 
797         if (unlikely(dev_priv->tdev == NULL)) {
798                 DRM_ERROR("Unable to initialize TTM object management.\n");
799                 ret = -ENOMEM;
800                 goto out_err4;
801         }
802 
803         dev->dev_private = dev_priv;
804 
805         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
806         dev_priv->stealth = (ret != 0);
807         if (dev_priv->stealth) {
808                 /**
809                  * Request at least the mmio PCI resource.
810                  */
811 
812                 DRM_INFO("It appears like vesafb is loaded. "
813                          "Ignore above error if any.\n");
814                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
815                 if (unlikely(ret != 0)) {
816                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
817                         goto out_no_device;
818                 }
819         }
820 
821         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
822                 ret = drm_irq_install(dev, dev->pdev->irq);
823                 if (ret != 0) {
824                         DRM_ERROR("Failed installing irq: %d\n", ret);
825                         goto out_no_irq;
826                 }
827         }
828 
829         dev_priv->fman = vmw_fence_manager_init(dev_priv);
830         if (unlikely(dev_priv->fman == NULL)) {
831                 ret = -ENOMEM;
832                 goto out_no_fman;
833         }
834 
835         ret = ttm_bo_device_init(&dev_priv->bdev,
836                                  dev_priv->bo_global_ref.ref.object,
837                                  &vmw_bo_driver,
838                                  dev->anon_inode->i_mapping,
839                                  VMWGFX_FILE_PAGE_OFFSET,
840                                  false);
841         if (unlikely(ret != 0)) {
842                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
843                 goto out_no_bdev;
844         }
845 
846         /*
847          * Enable VRAM, but initially don't use it until SVGA is enabled and
848          * unhidden.
849          */
850         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
851                              (dev_priv->vram_size >> PAGE_SHIFT));
852         if (unlikely(ret != 0)) {
853                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
854                 goto out_no_vram;
855         }
856         dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
857 
858         dev_priv->has_gmr = true;
859         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
860             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
861                                          VMW_PL_GMR) != 0) {
862                 DRM_INFO("No GMR memory available. "
863                          "Graphics memory resources are very limited.\n");
864                 dev_priv->has_gmr = false;
865         }
866 
867         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
868                 dev_priv->has_mob = true;
869                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
870                                    VMW_PL_MOB) != 0) {
871                         DRM_INFO("No MOB memory available. "
872                                  "3D will be disabled.\n");
873                         dev_priv->has_mob = false;
874                 }
875         }
876 
877         if (dev_priv->has_mob) {
878                 spin_lock(&dev_priv->cap_lock);
879                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
880                 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
881                 spin_unlock(&dev_priv->cap_lock);
882         }
883 
884 
885         ret = vmw_kms_init(dev_priv);
886         if (unlikely(ret != 0))
887                 goto out_no_kms;
888         vmw_overlay_init(dev_priv);
889 
890         ret = vmw_request_device(dev_priv);
891         if (ret)
892                 goto out_no_fifo;
893 
894         DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
895 
896         snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
897                 VMWGFX_REPO, VMWGFX_GIT_VERSION);
898         vmw_host_log(host_log);
899 
900         memset(host_log, 0, sizeof(host_log));
901         snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
902                 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
903                 VMWGFX_DRIVER_PATCHLEVEL);
904         vmw_host_log(host_log);
905 
906         if (dev_priv->enable_fb) {
907                 vmw_fifo_resource_inc(dev_priv);
908                 vmw_svga_enable(dev_priv);
909                 vmw_fb_init(dev_priv);
910         }
911 
912         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
913         register_pm_notifier(&dev_priv->pm_nb);
914 
915         return 0;
916 
917 out_no_fifo:
918         vmw_overlay_close(dev_priv);
919         vmw_kms_close(dev_priv);
920 out_no_kms:
921         if (dev_priv->has_mob)
922                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
923         if (dev_priv->has_gmr)
924                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
925         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
926 out_no_vram:
927         (void)ttm_bo_device_release(&dev_priv->bdev);
928 out_no_bdev:
929         vmw_fence_manager_takedown(dev_priv->fman);
930 out_no_fman:
931         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
932                 drm_irq_uninstall(dev_priv->dev);
933 out_no_irq:
934         if (dev_priv->stealth)
935                 pci_release_region(dev->pdev, 2);
936         else
937                 pci_release_regions(dev->pdev);
938 out_no_device:
939         ttm_object_device_release(&dev_priv->tdev);
940 out_err4:
941         memunmap(dev_priv->mmio_virt);
942 out_err3:
943         vmw_ttm_global_release(dev_priv);
944 out_err0:
945         for (i = vmw_res_context; i < vmw_res_max; ++i)
946                 idr_destroy(&dev_priv->res_idr[i]);
947 
948         if (dev_priv->ctx.staged_bindings)
949                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
950         kfree(dev_priv);
951         return ret;
952 }
953 
954 static int vmw_driver_unload(struct drm_device *dev)
955 {
956         struct vmw_private *dev_priv = vmw_priv(dev);
957         enum vmw_res_type i;
958 
959         unregister_pm_notifier(&dev_priv->pm_nb);
960 
961         if (dev_priv->ctx.res_ht_initialized)
962                 drm_ht_remove(&dev_priv->ctx.res_ht);
963         vfree(dev_priv->ctx.cmd_bounce);
964         if (dev_priv->enable_fb) {
965                 vmw_fb_off(dev_priv);
966                 vmw_fb_close(dev_priv);
967                 vmw_fifo_resource_dec(dev_priv);
968                 vmw_svga_disable(dev_priv);
969         }
970 
971         vmw_kms_close(dev_priv);
972         vmw_overlay_close(dev_priv);
973 
974         if (dev_priv->has_gmr)
975                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
976         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
977 
978         vmw_release_device_early(dev_priv);
979         if (dev_priv->has_mob)
980                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
981         (void) ttm_bo_device_release(&dev_priv->bdev);
982         vmw_release_device_late(dev_priv);
983         vmw_fence_manager_takedown(dev_priv->fman);
984         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
985                 drm_irq_uninstall(dev_priv->dev);
986         if (dev_priv->stealth)
987                 pci_release_region(dev->pdev, 2);
988         else
989                 pci_release_regions(dev->pdev);
990 
991         ttm_object_device_release(&dev_priv->tdev);
992         memunmap(dev_priv->mmio_virt);
993         if (dev_priv->ctx.staged_bindings)
994                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
995         vmw_ttm_global_release(dev_priv);
996 
997         for (i = vmw_res_context; i < vmw_res_max; ++i)
998                 idr_destroy(&dev_priv->res_idr[i]);
999 
1000         kfree(dev_priv);
1001 
1002         return 0;
1003 }
1004 
1005 static void vmw_postclose(struct drm_device *dev,
1006                          struct drm_file *file_priv)
1007 {
1008         struct vmw_fpriv *vmw_fp;
1009 
1010         vmw_fp = vmw_fpriv(file_priv);
1011 
1012         if (vmw_fp->locked_master) {
1013                 struct vmw_master *vmaster =
1014                         vmw_master(vmw_fp->locked_master);
1015 
1016                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1017                 ttm_vt_unlock(&vmaster->lock);
1018                 drm_master_put(&vmw_fp->locked_master);
1019         }
1020 
1021         ttm_object_file_release(&vmw_fp->tfile);
1022         kfree(vmw_fp);
1023 }
1024 
1025 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1026 {
1027         struct vmw_private *dev_priv = vmw_priv(dev);
1028         struct vmw_fpriv *vmw_fp;
1029         int ret = -ENOMEM;
1030 
1031         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1032         if (unlikely(vmw_fp == NULL))
1033                 return ret;
1034 
1035         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1036         if (unlikely(vmw_fp->tfile == NULL))
1037                 goto out_no_tfile;
1038 
1039         file_priv->driver_priv = vmw_fp;
1040 
1041         return 0;
1042 
1043 out_no_tfile:
1044         kfree(vmw_fp);
1045         return ret;
1046 }
1047 
1048 static struct vmw_master *vmw_master_check(struct drm_device *dev,
1049                                            struct drm_file *file_priv,
1050                                            unsigned int flags)
1051 {
1052         int ret;
1053         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1054         struct vmw_master *vmaster;
1055 
1056         if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1057                 return NULL;
1058 
1059         ret = mutex_lock_interruptible(&dev->master_mutex);
1060         if (unlikely(ret != 0))
1061                 return ERR_PTR(-ERESTARTSYS);
1062 
1063         if (drm_is_current_master(file_priv)) {
1064                 mutex_unlock(&dev->master_mutex);
1065                 return NULL;
1066         }
1067 
1068         /*
1069          * Check if we were previously master, but now dropped. In that
1070          * case, allow at least render node functionality.
1071          */
1072         if (vmw_fp->locked_master) {
1073                 mutex_unlock(&dev->master_mutex);
1074 
1075                 if (flags & DRM_RENDER_ALLOW)
1076                         return NULL;
1077 
1078                 DRM_ERROR("Dropped master trying to access ioctl that "
1079                           "requires authentication.\n");
1080                 return ERR_PTR(-EACCES);
1081         }
1082         mutex_unlock(&dev->master_mutex);
1083 
1084         /*
1085          * Take the TTM lock. Possibly sleep waiting for the authenticating
1086          * master to become master again, or for a SIGTERM if the
1087          * authenticating master exits.
1088          */
1089         vmaster = vmw_master(file_priv->master);
1090         ret = ttm_read_lock(&vmaster->lock, true);
1091         if (unlikely(ret != 0))
1092                 vmaster = ERR_PTR(ret);
1093 
1094         return vmaster;
1095 }
1096 
1097 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1098                               unsigned long arg,
1099                               long (*ioctl_func)(struct file *, unsigned int,
1100                                                  unsigned long))
1101 {
1102         struct drm_file *file_priv = filp->private_data;
1103         struct drm_device *dev = file_priv->minor->dev;
1104         unsigned int nr = DRM_IOCTL_NR(cmd);
1105         struct vmw_master *vmaster;
1106         unsigned int flags;
1107         long ret;
1108 
1109         /*
1110          * Do extra checking on driver private ioctls.
1111          */
1112 
1113         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1114             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1115                 const struct drm_ioctl_desc *ioctl =
1116                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1117 
1118                 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1119                         ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1120                         if (unlikely(ret != 0))
1121                                 return ret;
1122 
1123                         if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1124                                 goto out_io_encoding;
1125 
1126                         return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1127                                                         _IOC_SIZE(cmd));
1128                 }
1129 
1130                 if (unlikely(ioctl->cmd != cmd))
1131                         goto out_io_encoding;
1132 
1133                 flags = ioctl->flags;
1134         } else if (!drm_ioctl_flags(nr, &flags))
1135                 return -EINVAL;
1136 
1137         vmaster = vmw_master_check(dev, file_priv, flags);
1138         if (IS_ERR(vmaster)) {
1139                 ret = PTR_ERR(vmaster);
1140 
1141                 if (ret != -ERESTARTSYS)
1142                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1143                                  nr, ret);
1144                 return ret;
1145         }
1146 
1147         ret = ioctl_func(filp, cmd, arg);
1148         if (vmaster)
1149                 ttm_read_unlock(&vmaster->lock);
1150 
1151         return ret;
1152 
1153 out_io_encoding:
1154         DRM_ERROR("Invalid command format, ioctl %d\n",
1155                   nr - DRM_COMMAND_BASE);
1156 
1157         return -EINVAL;
1158 }
1159 
1160 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1161                                unsigned long arg)
1162 {
1163         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1164 }
1165 
1166 #ifdef CONFIG_COMPAT
1167 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1168                              unsigned long arg)
1169 {
1170         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1171 }
1172 #endif
1173 
1174 static void vmw_lastclose(struct drm_device *dev)
1175 {
1176 }
1177 
1178 static void vmw_master_init(struct vmw_master *vmaster)
1179 {
1180         ttm_lock_init(&vmaster->lock);
1181 }
1182 
1183 static int vmw_master_create(struct drm_device *dev,
1184                              struct drm_master *master)
1185 {
1186         struct vmw_master *vmaster;
1187 
1188         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1189         if (unlikely(vmaster == NULL))
1190                 return -ENOMEM;
1191 
1192         vmw_master_init(vmaster);
1193         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1194         master->driver_priv = vmaster;
1195 
1196         return 0;
1197 }
1198 
1199 static void vmw_master_destroy(struct drm_device *dev,
1200                                struct drm_master *master)
1201 {
1202         struct vmw_master *vmaster = vmw_master(master);
1203 
1204         master->driver_priv = NULL;
1205         kfree(vmaster);
1206 }
1207 
1208 static int vmw_master_set(struct drm_device *dev,
1209                           struct drm_file *file_priv,
1210                           bool from_open)
1211 {
1212         struct vmw_private *dev_priv = vmw_priv(dev);
1213         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1214         struct vmw_master *active = dev_priv->active_master;
1215         struct vmw_master *vmaster = vmw_master(file_priv->master);
1216         int ret = 0;
1217 
1218         if (active) {
1219                 BUG_ON(active != &dev_priv->fbdev_master);
1220                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1221                 if (unlikely(ret != 0))
1222                         return ret;
1223 
1224                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1225                 dev_priv->active_master = NULL;
1226         }
1227 
1228         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1229         if (!from_open) {
1230                 ttm_vt_unlock(&vmaster->lock);
1231                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1232                 drm_master_put(&vmw_fp->locked_master);
1233         }
1234 
1235         dev_priv->active_master = vmaster;
1236         drm_sysfs_hotplug_event(dev);
1237 
1238         return 0;
1239 }
1240 
1241 static void vmw_master_drop(struct drm_device *dev,
1242                             struct drm_file *file_priv)
1243 {
1244         struct vmw_private *dev_priv = vmw_priv(dev);
1245         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1246         struct vmw_master *vmaster = vmw_master(file_priv->master);
1247         int ret;
1248 
1249         /**
1250          * Make sure the master doesn't disappear while we have
1251          * it locked.
1252          */
1253 
1254         vmw_fp->locked_master = drm_master_get(file_priv->master);
1255         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1256         vmw_kms_legacy_hotspot_clear(dev_priv);
1257         if (unlikely((ret != 0))) {
1258                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1259                 drm_master_put(&vmw_fp->locked_master);
1260         }
1261 
1262         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1263 
1264         if (!dev_priv->enable_fb)
1265                 vmw_svga_disable(dev_priv);
1266 
1267         dev_priv->active_master = &dev_priv->fbdev_master;
1268         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1269         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1270 
1271         if (dev_priv->enable_fb)
1272                 vmw_fb_on(dev_priv);
1273 }
1274 
1275 /**
1276  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1277  *
1278  * @dev_priv: Pointer to device private struct.
1279  * Needs the reservation sem to be held in non-exclusive mode.
1280  */
1281 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1282 {
1283         spin_lock(&dev_priv->svga_lock);
1284         if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1285                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1286                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1287         }
1288         spin_unlock(&dev_priv->svga_lock);
1289 }
1290 
1291 /**
1292  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1293  *
1294  * @dev_priv: Pointer to device private struct.
1295  */
1296 void vmw_svga_enable(struct vmw_private *dev_priv)
1297 {
1298         ttm_read_lock(&dev_priv->reservation_sem, false);
1299         __vmw_svga_enable(dev_priv);
1300         ttm_read_unlock(&dev_priv->reservation_sem);
1301 }
1302 
1303 /**
1304  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1305  *
1306  * @dev_priv: Pointer to device private struct.
1307  * Needs the reservation sem to be held in exclusive mode.
1308  * Will not empty VRAM. VRAM must be emptied by caller.
1309  */
1310 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1311 {
1312         spin_lock(&dev_priv->svga_lock);
1313         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1314                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1315                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1316                           SVGA_REG_ENABLE_HIDE |
1317                           SVGA_REG_ENABLE_ENABLE);
1318         }
1319         spin_unlock(&dev_priv->svga_lock);
1320 }
1321 
1322 /**
1323  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1324  * running.
1325  *
1326  * @dev_priv: Pointer to device private struct.
1327  * Will empty VRAM.
1328  */
1329 void vmw_svga_disable(struct vmw_private *dev_priv)
1330 {
1331         ttm_write_lock(&dev_priv->reservation_sem, false);
1332         spin_lock(&dev_priv->svga_lock);
1333         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1334                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1335                 spin_unlock(&dev_priv->svga_lock);
1336                 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1337                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1338                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1339                           SVGA_REG_ENABLE_HIDE |
1340                           SVGA_REG_ENABLE_ENABLE);
1341         } else
1342                 spin_unlock(&dev_priv->svga_lock);
1343         ttm_write_unlock(&dev_priv->reservation_sem);
1344 }
1345 
1346 static void vmw_remove(struct pci_dev *pdev)
1347 {
1348         struct drm_device *dev = pci_get_drvdata(pdev);
1349 
1350         pci_disable_device(pdev);
1351         drm_put_dev(dev);
1352 }
1353 
1354 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1355                               void *ptr)
1356 {
1357         struct vmw_private *dev_priv =
1358                 container_of(nb, struct vmw_private, pm_nb);
1359 
1360         switch (val) {
1361         case PM_HIBERNATION_PREPARE:
1362                 if (dev_priv->enable_fb)
1363                         vmw_fb_off(dev_priv);
1364                 ttm_suspend_lock(&dev_priv->reservation_sem);
1365 
1366                 /*
1367                  * This empties VRAM and unbinds all GMR bindings.
1368                  * Buffer contents is moved to swappable memory.
1369                  */
1370                 vmw_execbuf_release_pinned_bo(dev_priv);
1371                 vmw_resource_evict_all(dev_priv);
1372                 vmw_release_device_early(dev_priv);
1373                 ttm_bo_swapout_all(&dev_priv->bdev);
1374                 vmw_fence_fifo_down(dev_priv->fman);
1375                 break;
1376         case PM_POST_HIBERNATION:
1377         case PM_POST_RESTORE:
1378                 vmw_fence_fifo_up(dev_priv->fman);
1379                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1380                 if (dev_priv->enable_fb)
1381                         vmw_fb_on(dev_priv);
1382                 break;
1383         case PM_RESTORE_PREPARE:
1384                 break;
1385         default:
1386                 break;
1387         }
1388         return 0;
1389 }
1390 
1391 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1392 {
1393         struct drm_device *dev = pci_get_drvdata(pdev);
1394         struct vmw_private *dev_priv = vmw_priv(dev);
1395 
1396         if (dev_priv->refuse_hibernation)
1397                 return -EBUSY;
1398 
1399         pci_save_state(pdev);
1400         pci_disable_device(pdev);
1401         pci_set_power_state(pdev, PCI_D3hot);
1402         return 0;
1403 }
1404 
1405 static int vmw_pci_resume(struct pci_dev *pdev)
1406 {
1407         pci_set_power_state(pdev, PCI_D0);
1408         pci_restore_state(pdev);
1409         return pci_enable_device(pdev);
1410 }
1411 
1412 static int vmw_pm_suspend(struct device *kdev)
1413 {
1414         struct pci_dev *pdev = to_pci_dev(kdev);
1415         struct pm_message dummy;
1416 
1417         dummy.event = 0;
1418 
1419         return vmw_pci_suspend(pdev, dummy);
1420 }
1421 
1422 static int vmw_pm_resume(struct device *kdev)
1423 {
1424         struct pci_dev *pdev = to_pci_dev(kdev);
1425 
1426         return vmw_pci_resume(pdev);
1427 }
1428 
1429 static int vmw_pm_freeze(struct device *kdev)
1430 {
1431         struct pci_dev *pdev = to_pci_dev(kdev);
1432         struct drm_device *dev = pci_get_drvdata(pdev);
1433         struct vmw_private *dev_priv = vmw_priv(dev);
1434 
1435         dev_priv->suspended = true;
1436         if (dev_priv->enable_fb)
1437                 vmw_fifo_resource_dec(dev_priv);
1438 
1439         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1440                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1441                 if (dev_priv->enable_fb)
1442                         vmw_fifo_resource_inc(dev_priv);
1443                 WARN_ON(vmw_request_device_late(dev_priv));
1444                 dev_priv->suspended = false;
1445                 return -EBUSY;
1446         }
1447 
1448         if (dev_priv->enable_fb)
1449                 __vmw_svga_disable(dev_priv);
1450         
1451         vmw_release_device_late(dev_priv);
1452 
1453         return 0;
1454 }
1455 
1456 static int vmw_pm_restore(struct device *kdev)
1457 {
1458         struct pci_dev *pdev = to_pci_dev(kdev);
1459         struct drm_device *dev = pci_get_drvdata(pdev);
1460         struct vmw_private *dev_priv = vmw_priv(dev);
1461         int ret;
1462 
1463         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1464         (void) vmw_read(dev_priv, SVGA_REG_ID);
1465 
1466         if (dev_priv->enable_fb)
1467                 vmw_fifo_resource_inc(dev_priv);
1468 
1469         ret = vmw_request_device(dev_priv);
1470         if (ret)
1471                 return ret;
1472 
1473         if (dev_priv->enable_fb)
1474                 __vmw_svga_enable(dev_priv);
1475 
1476         dev_priv->suspended = false;
1477 
1478         return 0;
1479 }
1480 
1481 static const struct dev_pm_ops vmw_pm_ops = {
1482         .freeze = vmw_pm_freeze,
1483         .thaw = vmw_pm_restore,
1484         .restore = vmw_pm_restore,
1485         .suspend = vmw_pm_suspend,
1486         .resume = vmw_pm_resume,
1487 };
1488 
1489 static const struct file_operations vmwgfx_driver_fops = {
1490         .owner = THIS_MODULE,
1491         .open = drm_open,
1492         .release = drm_release,
1493         .unlocked_ioctl = vmw_unlocked_ioctl,
1494         .mmap = vmw_mmap,
1495         .poll = vmw_fops_poll,
1496         .read = vmw_fops_read,
1497 #if defined(CONFIG_COMPAT)
1498         .compat_ioctl = vmw_compat_ioctl,
1499 #endif
1500         .llseek = noop_llseek,
1501 };
1502 
1503 static struct drm_driver driver = {
1504         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1505         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1506         .load = vmw_driver_load,
1507         .unload = vmw_driver_unload,
1508         .lastclose = vmw_lastclose,
1509         .irq_preinstall = vmw_irq_preinstall,
1510         .irq_postinstall = vmw_irq_postinstall,
1511         .irq_uninstall = vmw_irq_uninstall,
1512         .irq_handler = vmw_irq_handler,
1513         .get_vblank_counter = vmw_get_vblank_counter,
1514         .enable_vblank = vmw_enable_vblank,
1515         .disable_vblank = vmw_disable_vblank,
1516         .ioctls = vmw_ioctls,
1517         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1518         .master_create = vmw_master_create,
1519         .master_destroy = vmw_master_destroy,
1520         .master_set = vmw_master_set,
1521         .master_drop = vmw_master_drop,
1522         .open = vmw_driver_open,
1523         .postclose = vmw_postclose,
1524         .set_busid = drm_pci_set_busid,
1525 
1526         .dumb_create = vmw_dumb_create,
1527         .dumb_map_offset = vmw_dumb_map_offset,
1528         .dumb_destroy = vmw_dumb_destroy,
1529 
1530         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1531         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1532 
1533         .fops = &vmwgfx_driver_fops,
1534         .name = VMWGFX_DRIVER_NAME,
1535         .desc = VMWGFX_DRIVER_DESC,
1536         .date = VMWGFX_DRIVER_DATE,
1537         .major = VMWGFX_DRIVER_MAJOR,
1538         .minor = VMWGFX_DRIVER_MINOR,
1539         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1540 };
1541 
1542 static struct pci_driver vmw_pci_driver = {
1543         .name = VMWGFX_DRIVER_NAME,
1544         .id_table = vmw_pci_id_list,
1545         .probe = vmw_probe,
1546         .remove = vmw_remove,
1547         .driver = {
1548                 .pm = &vmw_pm_ops
1549         }
1550 };
1551 
1552 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1553 {
1554         return drm_get_pci_dev(pdev, ent, &driver);
1555 }
1556 
1557 static int __init vmwgfx_init(void)
1558 {
1559         int ret;
1560 
1561         if (vgacon_text_force())
1562                 return -EINVAL;
1563 
1564         ret = drm_pci_init(&driver, &vmw_pci_driver);
1565         if (ret)
1566                 DRM_ERROR("Failed initializing DRM.\n");
1567         return ret;
1568 }
1569 
1570 static void __exit vmwgfx_exit(void)
1571 {
1572         drm_pci_exit(&driver, &vmw_pci_driver);
1573 }
1574 
1575 module_init(vmwgfx_init);
1576 module_exit(vmwgfx_exit);
1577 
1578 MODULE_AUTHOR("VMware Inc. and others");
1579 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1580 MODULE_LICENSE("GPL and additional rights");
1581 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1582                __stringify(VMWGFX_DRIVER_MINOR) "."
1583                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1584                "");
1585 

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