Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

  1 /**************************************************************************
  2  *
  3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4  * All Rights Reserved.
  5  *
  6  * Permission is hereby granted, free of charge, to any person obtaining a
  7  * copy of this software and associated documentation files (the
  8  * "Software"), to deal in the Software without restriction, including
  9  * without limitation the rights to use, copy, modify, merge, publish,
 10  * distribute, sub license, and/or sell copies of the Software, and to
 11  * permit persons to whom the Software is furnished to do so, subject to
 12  * the following conditions:
 13  *
 14  * The above copyright notice and this permission notice (including the
 15  * next paragraph) shall be included in all copies or substantial portions
 16  * of the Software.
 17  *
 18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
 25  *
 26  **************************************************************************/
 27 #include <linux/module.h>
 28 
 29 #include <drm/drmP.h>
 30 #include "vmwgfx_drv.h"
 31 #include <drm/ttm/ttm_placement.h>
 32 #include <drm/ttm/ttm_bo_driver.h>
 33 #include <drm/ttm/ttm_object.h>
 34 #include <drm/ttm/ttm_module.h>
 35 #include <linux/dma_remapping.h>
 36 
 37 #define VMWGFX_DRIVER_NAME "vmwgfx"
 38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
 39 #define VMWGFX_CHIP_SVGAII 0
 40 #define VMW_FB_RESERVATION 0
 41 
 42 #define VMW_MIN_INITIAL_WIDTH 800
 43 #define VMW_MIN_INITIAL_HEIGHT 600
 44 
 45 
 46 /**
 47  * Fully encoded drm commands. Might move to vmw_drm.h
 48  */
 49 
 50 #define DRM_IOCTL_VMW_GET_PARAM                                 \
 51         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
 52                  struct drm_vmw_getparam_arg)
 53 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
 54         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
 55                 union drm_vmw_alloc_dmabuf_arg)
 56 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
 57         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
 58                 struct drm_vmw_unref_dmabuf_arg)
 59 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
 60         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
 61                  struct drm_vmw_cursor_bypass_arg)
 62 
 63 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
 64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
 65                  struct drm_vmw_control_stream_arg)
 66 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
 67         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
 68                  struct drm_vmw_stream_arg)
 69 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
 70         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
 71                  struct drm_vmw_stream_arg)
 72 
 73 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
 74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
 75                 struct drm_vmw_context_arg)
 76 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
 77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
 78                 struct drm_vmw_context_arg)
 79 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
 80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
 81                  union drm_vmw_surface_create_arg)
 82 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
 83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
 84                  struct drm_vmw_surface_arg)
 85 #define DRM_IOCTL_VMW_REF_SURFACE                               \
 86         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
 87                  union drm_vmw_surface_reference_arg)
 88 #define DRM_IOCTL_VMW_EXECBUF                                   \
 89         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
 90                 struct drm_vmw_execbuf_arg)
 91 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
 92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
 93                  struct drm_vmw_get_3d_cap_arg)
 94 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
 95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
 96                  struct drm_vmw_fence_wait_arg)
 97 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
 98         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
 99                  struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
102                  struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
104         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
105                  struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT                                   \
107         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
108                  struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
111                  struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
114                  struct drm_vmw_update_layout_arg)
115 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
116         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
117                  struct drm_vmw_shader_create_arg)
118 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
119         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
120                  struct drm_vmw_shader_arg)
121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
122         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
123                  union drm_vmw_gb_surface_create_arg)
124 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
125         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
126                  union drm_vmw_gb_surface_reference_arg)
127 #define DRM_IOCTL_VMW_SYNCCPU                                   \
128         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
129                  struct drm_vmw_synccpu_arg)
130 
131 /**
132  * The core DRM version of this macro doesn't account for
133  * DRM_COMMAND_BASE.
134  */
135 
136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
137   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
138 
139 /**
140  * Ioctl definitions.
141  */
142 
143 static const struct drm_ioctl_desc vmw_ioctls[] = {
144         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
145                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
146         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
147                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
148         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
149                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
150         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
151                       vmw_kms_cursor_bypass_ioctl,
152                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
153 
154         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
155                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
156         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
157                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
158         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
159                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
160 
161         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
162                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
163         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
164                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
165         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
166                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
167         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
168                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
169         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
170                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
171         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
172                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
173         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
174                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
175         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176                       vmw_fence_obj_signaled_ioctl,
177                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
178         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
179                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
180         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
181                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
182         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
183                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
184 
185         /* these allow direct access to the framebuffers mark as master only */
186         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
187                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
188         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
189                       vmw_present_readback_ioctl,
190                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
191         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
192                       vmw_kms_update_layout_ioctl,
193                       DRM_MASTER | DRM_UNLOCKED),
194         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
195                       vmw_shader_define_ioctl,
196                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
197         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
198                       vmw_shader_destroy_ioctl,
199                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
200         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
201                       vmw_gb_surface_define_ioctl,
202                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
203         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
204                       vmw_gb_surface_reference_ioctl,
205                       DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
206         VMW_IOCTL_DEF(VMW_SYNCCPU,
207                       vmw_user_dmabuf_synccpu_ioctl,
208                       DRM_UNLOCKED | DRM_RENDER_ALLOW),
209 };
210 
211 static struct pci_device_id vmw_pci_id_list[] = {
212         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
213         {0, 0, 0}
214 };
215 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
216 
217 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
218 static int vmw_force_iommu;
219 static int vmw_restrict_iommu;
220 static int vmw_force_coherent;
221 static int vmw_restrict_dma_mask;
222 
223 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
224 static void vmw_master_init(struct vmw_master *);
225 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
226                               void *ptr);
227 
228 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
229 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
230 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
231 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
232 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
233 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
234 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
235 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
236 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
237 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
238 
239 
240 static void vmw_print_capabilities(uint32_t capabilities)
241 {
242         DRM_INFO("Capabilities:\n");
243         if (capabilities & SVGA_CAP_RECT_COPY)
244                 DRM_INFO("  Rect copy.\n");
245         if (capabilities & SVGA_CAP_CURSOR)
246                 DRM_INFO("  Cursor.\n");
247         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
248                 DRM_INFO("  Cursor bypass.\n");
249         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
250                 DRM_INFO("  Cursor bypass 2.\n");
251         if (capabilities & SVGA_CAP_8BIT_EMULATION)
252                 DRM_INFO("  8bit emulation.\n");
253         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
254                 DRM_INFO("  Alpha cursor.\n");
255         if (capabilities & SVGA_CAP_3D)
256                 DRM_INFO("  3D.\n");
257         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
258                 DRM_INFO("  Extended Fifo.\n");
259         if (capabilities & SVGA_CAP_MULTIMON)
260                 DRM_INFO("  Multimon.\n");
261         if (capabilities & SVGA_CAP_PITCHLOCK)
262                 DRM_INFO("  Pitchlock.\n");
263         if (capabilities & SVGA_CAP_IRQMASK)
264                 DRM_INFO("  Irq mask.\n");
265         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
266                 DRM_INFO("  Display Topology.\n");
267         if (capabilities & SVGA_CAP_GMR)
268                 DRM_INFO("  GMR.\n");
269         if (capabilities & SVGA_CAP_TRACES)
270                 DRM_INFO("  Traces.\n");
271         if (capabilities & SVGA_CAP_GMR2)
272                 DRM_INFO("  GMR2.\n");
273         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
274                 DRM_INFO("  Screen Object 2.\n");
275         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
276                 DRM_INFO("  Command Buffers.\n");
277         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
278                 DRM_INFO("  Command Buffers 2.\n");
279         if (capabilities & SVGA_CAP_GBOBJECTS)
280                 DRM_INFO("  Guest Backed Resources.\n");
281 }
282 
283 /**
284  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
285  *
286  * @dev_priv: A device private structure.
287  *
288  * This function creates a small buffer object that holds the query
289  * result for dummy queries emitted as query barriers.
290  * The function will then map the first page and initialize a pending
291  * occlusion query result structure, Finally it will unmap the buffer.
292  * No interruptible waits are done within this function.
293  *
294  * Returns an error if bo creation or initialization fails.
295  */
296 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
297 {
298         int ret;
299         struct ttm_buffer_object *bo;
300         struct ttm_bo_kmap_obj map;
301         volatile SVGA3dQueryResult *result;
302         bool dummy;
303 
304         /*
305          * Create the bo as pinned, so that a tryreserve will
306          * immediately succeed. This is because we're the only
307          * user of the bo currently.
308          */
309         ret = ttm_bo_create(&dev_priv->bdev,
310                             PAGE_SIZE,
311                             ttm_bo_type_device,
312                             &vmw_sys_ne_placement,
313                             0, false, NULL,
314                             &bo);
315 
316         if (unlikely(ret != 0))
317                 return ret;
318 
319         ret = ttm_bo_reserve(bo, false, true, false, NULL);
320         BUG_ON(ret != 0);
321 
322         ret = ttm_bo_kmap(bo, 0, 1, &map);
323         if (likely(ret == 0)) {
324                 result = ttm_kmap_obj_virtual(&map, &dummy);
325                 result->totalSize = sizeof(*result);
326                 result->state = SVGA3D_QUERYSTATE_PENDING;
327                 result->result32 = 0xff;
328                 ttm_bo_kunmap(&map);
329         }
330         vmw_bo_pin(bo, false);
331         ttm_bo_unreserve(bo);
332 
333         if (unlikely(ret != 0)) {
334                 DRM_ERROR("Dummy query buffer map failed.\n");
335                 ttm_bo_unref(&bo);
336         } else
337                 dev_priv->dummy_query_bo = bo;
338 
339         return ret;
340 }
341 
342 static int vmw_request_device(struct vmw_private *dev_priv)
343 {
344         int ret;
345 
346         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
347         if (unlikely(ret != 0)) {
348                 DRM_ERROR("Unable to initialize FIFO.\n");
349                 return ret;
350         }
351         vmw_fence_fifo_up(dev_priv->fman);
352         if (dev_priv->has_mob) {
353                 ret = vmw_otables_setup(dev_priv);
354                 if (unlikely(ret != 0)) {
355                         DRM_ERROR("Unable to initialize "
356                                   "guest Memory OBjects.\n");
357                         goto out_no_mob;
358                 }
359         }
360         ret = vmw_dummy_query_bo_create(dev_priv);
361         if (unlikely(ret != 0))
362                 goto out_no_query_bo;
363 
364         return 0;
365 
366 out_no_query_bo:
367         if (dev_priv->has_mob)
368                 vmw_otables_takedown(dev_priv);
369 out_no_mob:
370         vmw_fence_fifo_down(dev_priv->fman);
371         vmw_fifo_release(dev_priv, &dev_priv->fifo);
372         return ret;
373 }
374 
375 static void vmw_release_device(struct vmw_private *dev_priv)
376 {
377         /*
378          * Previous destructions should've released
379          * the pinned bo.
380          */
381 
382         BUG_ON(dev_priv->pinned_bo != NULL);
383 
384         ttm_bo_unref(&dev_priv->dummy_query_bo);
385         if (dev_priv->has_mob)
386                 vmw_otables_takedown(dev_priv);
387         vmw_fence_fifo_down(dev_priv->fman);
388         vmw_fifo_release(dev_priv, &dev_priv->fifo);
389 }
390 
391 
392 /**
393  * Increase the 3d resource refcount.
394  * If the count was prevously zero, initialize the fifo, switching to svga
395  * mode. Note that the master holds a ref as well, and may request an
396  * explicit switch to svga mode if fb is not running, using @unhide_svga.
397  */
398 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
399                         bool unhide_svga)
400 {
401         int ret = 0;
402 
403         mutex_lock(&dev_priv->release_mutex);
404         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
405                 ret = vmw_request_device(dev_priv);
406                 if (unlikely(ret != 0))
407                         --dev_priv->num_3d_resources;
408         } else if (unhide_svga) {
409                 vmw_write(dev_priv, SVGA_REG_ENABLE,
410                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
411                           ~SVGA_REG_ENABLE_HIDE);
412         }
413 
414         mutex_unlock(&dev_priv->release_mutex);
415         return ret;
416 }
417 
418 /**
419  * Decrease the 3d resource refcount.
420  * If the count reaches zero, disable the fifo, switching to vga mode.
421  * Note that the master holds a refcount as well, and may request an
422  * explicit switch to vga mode when it releases its refcount to account
423  * for the situation of an X server vt switch to VGA with 3d resources
424  * active.
425  */
426 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
427                          bool hide_svga)
428 {
429         int32_t n3d;
430 
431         mutex_lock(&dev_priv->release_mutex);
432         if (unlikely(--dev_priv->num_3d_resources == 0))
433                 vmw_release_device(dev_priv);
434         else if (hide_svga)
435                 vmw_write(dev_priv, SVGA_REG_ENABLE,
436                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
437                           SVGA_REG_ENABLE_HIDE);
438 
439         n3d = (int32_t) dev_priv->num_3d_resources;
440         mutex_unlock(&dev_priv->release_mutex);
441 
442         BUG_ON(n3d < 0);
443 }
444 
445 /**
446  * Sets the initial_[width|height] fields on the given vmw_private.
447  *
448  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
449  * clamping the value to fb_max_[width|height] fields and the
450  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
451  * If the values appear to be invalid, set them to
452  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
453  */
454 static void vmw_get_initial_size(struct vmw_private *dev_priv)
455 {
456         uint32_t width;
457         uint32_t height;
458 
459         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
460         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
461 
462         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
463         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
464 
465         if (width > dev_priv->fb_max_width ||
466             height > dev_priv->fb_max_height) {
467 
468                 /*
469                  * This is a host error and shouldn't occur.
470                  */
471 
472                 width = VMW_MIN_INITIAL_WIDTH;
473                 height = VMW_MIN_INITIAL_HEIGHT;
474         }
475 
476         dev_priv->initial_width = width;
477         dev_priv->initial_height = height;
478 }
479 
480 /**
481  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
482  * system.
483  *
484  * @dev_priv: Pointer to a struct vmw_private
485  *
486  * This functions tries to determine the IOMMU setup and what actions
487  * need to be taken by the driver to make system pages visible to the
488  * device.
489  * If this function decides that DMA is not possible, it returns -EINVAL.
490  * The driver may then try to disable features of the device that require
491  * DMA.
492  */
493 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
494 {
495         static const char *names[vmw_dma_map_max] = {
496                 [vmw_dma_phys] = "Using physical TTM page addresses.",
497                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
498                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
499                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
500 #ifdef CONFIG_X86
501         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
502 
503 #ifdef CONFIG_INTEL_IOMMU
504         if (intel_iommu_enabled) {
505                 dev_priv->map_mode = vmw_dma_map_populate;
506                 goto out_fixup;
507         }
508 #endif
509 
510         if (!(vmw_force_iommu || vmw_force_coherent)) {
511                 dev_priv->map_mode = vmw_dma_phys;
512                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
513                 return 0;
514         }
515 
516         dev_priv->map_mode = vmw_dma_map_populate;
517 
518         if (dma_ops->sync_single_for_cpu)
519                 dev_priv->map_mode = vmw_dma_alloc_coherent;
520 #ifdef CONFIG_SWIOTLB
521         if (swiotlb_nr_tbl() == 0)
522                 dev_priv->map_mode = vmw_dma_map_populate;
523 #endif
524 
525 #ifdef CONFIG_INTEL_IOMMU
526 out_fixup:
527 #endif
528         if (dev_priv->map_mode == vmw_dma_map_populate &&
529             vmw_restrict_iommu)
530                 dev_priv->map_mode = vmw_dma_map_bind;
531 
532         if (vmw_force_coherent)
533                 dev_priv->map_mode = vmw_dma_alloc_coherent;
534 
535 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
536         /*
537          * No coherent page pool
538          */
539         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
540                 return -EINVAL;
541 #endif
542 
543 #else /* CONFIG_X86 */
544         dev_priv->map_mode = vmw_dma_map_populate;
545 #endif /* CONFIG_X86 */
546 
547         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
548 
549         return 0;
550 }
551 
552 /**
553  * vmw_dma_masks - set required page- and dma masks
554  *
555  * @dev: Pointer to struct drm-device
556  *
557  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
558  * restriction also for 64-bit systems.
559  */
560 #ifdef CONFIG_INTEL_IOMMU
561 static int vmw_dma_masks(struct vmw_private *dev_priv)
562 {
563         struct drm_device *dev = dev_priv->dev;
564 
565         if (intel_iommu_enabled &&
566             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
567                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
568                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
569         }
570         return 0;
571 }
572 #else
573 static int vmw_dma_masks(struct vmw_private *dev_priv)
574 {
575         return 0;
576 }
577 #endif
578 
579 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
580 {
581         struct vmw_private *dev_priv;
582         int ret;
583         uint32_t svga_id;
584         enum vmw_res_type i;
585         bool refuse_dma = false;
586 
587         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
588         if (unlikely(dev_priv == NULL)) {
589                 DRM_ERROR("Failed allocating a device private struct.\n");
590                 return -ENOMEM;
591         }
592 
593         pci_set_master(dev->pdev);
594 
595         dev_priv->dev = dev;
596         dev_priv->vmw_chipset = chipset;
597         dev_priv->last_read_seqno = (uint32_t) -100;
598         mutex_init(&dev_priv->cmdbuf_mutex);
599         mutex_init(&dev_priv->release_mutex);
600         mutex_init(&dev_priv->binding_mutex);
601         rwlock_init(&dev_priv->resource_lock);
602         ttm_lock_init(&dev_priv->reservation_sem);
603         spin_lock_init(&dev_priv->hw_lock);
604         spin_lock_init(&dev_priv->waiter_lock);
605         spin_lock_init(&dev_priv->cap_lock);
606 
607         for (i = vmw_res_context; i < vmw_res_max; ++i) {
608                 idr_init(&dev_priv->res_idr[i]);
609                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
610         }
611 
612         mutex_init(&dev_priv->init_mutex);
613         init_waitqueue_head(&dev_priv->fence_queue);
614         init_waitqueue_head(&dev_priv->fifo_queue);
615         dev_priv->fence_queue_waiters = 0;
616         atomic_set(&dev_priv->fifo_queue_waiters, 0);
617 
618         dev_priv->used_memory_size = 0;
619 
620         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
621         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
622         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
623 
624         dev_priv->enable_fb = enable_fbdev;
625 
626         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
627         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
628         if (svga_id != SVGA_ID_2) {
629                 ret = -ENOSYS;
630                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
631                 goto out_err0;
632         }
633 
634         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
635         ret = vmw_dma_select_mode(dev_priv);
636         if (unlikely(ret != 0)) {
637                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
638                 refuse_dma = true;
639         }
640 
641         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
642         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
643         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
644         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
645 
646         vmw_get_initial_size(dev_priv);
647 
648         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
649                 dev_priv->max_gmr_ids =
650                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
651                 dev_priv->max_gmr_pages =
652                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
653                 dev_priv->memory_size =
654                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
655                 dev_priv->memory_size -= dev_priv->vram_size;
656         } else {
657                 /*
658                  * An arbitrary limit of 512MiB on surface
659                  * memory. But all HWV8 hardware supports GMR2.
660                  */
661                 dev_priv->memory_size = 512*1024*1024;
662         }
663         dev_priv->max_mob_pages = 0;
664         dev_priv->max_mob_size = 0;
665         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
666                 uint64_t mem_size =
667                         vmw_read(dev_priv,
668                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
669 
670                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
671                 dev_priv->prim_bb_mem =
672                         vmw_read(dev_priv,
673                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
674                 dev_priv->max_mob_size =
675                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
676         } else
677                 dev_priv->prim_bb_mem = dev_priv->vram_size;
678 
679         ret = vmw_dma_masks(dev_priv);
680         if (unlikely(ret != 0))
681                 goto out_err0;
682 
683         /*
684          * Limit back buffer size to VRAM size.  Remove this once
685          * screen targets are implemented.
686          */
687         if (dev_priv->prim_bb_mem > dev_priv->vram_size)
688                 dev_priv->prim_bb_mem = dev_priv->vram_size;
689 
690         vmw_print_capabilities(dev_priv->capabilities);
691 
692         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
693                 DRM_INFO("Max GMR ids is %u\n",
694                          (unsigned)dev_priv->max_gmr_ids);
695                 DRM_INFO("Max number of GMR pages is %u\n",
696                          (unsigned)dev_priv->max_gmr_pages);
697                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
698                          (unsigned)dev_priv->memory_size / 1024);
699         }
700         DRM_INFO("Maximum display memory size is %u kiB\n",
701                  dev_priv->prim_bb_mem / 1024);
702         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
703                  dev_priv->vram_start, dev_priv->vram_size / 1024);
704         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
705                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
706 
707         ret = vmw_ttm_global_init(dev_priv);
708         if (unlikely(ret != 0))
709                 goto out_err0;
710 
711 
712         vmw_master_init(&dev_priv->fbdev_master);
713         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
714         dev_priv->active_master = &dev_priv->fbdev_master;
715 
716 
717         ret = ttm_bo_device_init(&dev_priv->bdev,
718                                  dev_priv->bo_global_ref.ref.object,
719                                  &vmw_bo_driver,
720                                  dev->anon_inode->i_mapping,
721                                  VMWGFX_FILE_PAGE_OFFSET,
722                                  false);
723         if (unlikely(ret != 0)) {
724                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
725                 goto out_err1;
726         }
727 
728         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
729                              (dev_priv->vram_size >> PAGE_SHIFT));
730         if (unlikely(ret != 0)) {
731                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
732                 goto out_err2;
733         }
734 
735         dev_priv->has_gmr = true;
736         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
737             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
738                                          VMW_PL_GMR) != 0) {
739                 DRM_INFO("No GMR memory available. "
740                          "Graphics memory resources are very limited.\n");
741                 dev_priv->has_gmr = false;
742         }
743 
744         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
745                 dev_priv->has_mob = true;
746                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
747                                    VMW_PL_MOB) != 0) {
748                         DRM_INFO("No MOB memory available. "
749                                  "3D will be disabled.\n");
750                         dev_priv->has_mob = false;
751                 }
752         }
753 
754         dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
755                                                dev_priv->mmio_size);
756 
757         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
758                                          dev_priv->mmio_size);
759 
760         if (unlikely(dev_priv->mmio_virt == NULL)) {
761                 ret = -ENOMEM;
762                 DRM_ERROR("Failed mapping MMIO.\n");
763                 goto out_err3;
764         }
765 
766         /* Need mmio memory to check for fifo pitchlock cap. */
767         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
768             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
769             !vmw_fifo_have_pitchlock(dev_priv)) {
770                 ret = -ENOSYS;
771                 DRM_ERROR("Hardware has no pitchlock\n");
772                 goto out_err4;
773         }
774 
775         dev_priv->tdev = ttm_object_device_init
776                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
777 
778         if (unlikely(dev_priv->tdev == NULL)) {
779                 DRM_ERROR("Unable to initialize TTM object management.\n");
780                 ret = -ENOMEM;
781                 goto out_err4;
782         }
783 
784         dev->dev_private = dev_priv;
785 
786         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
787         dev_priv->stealth = (ret != 0);
788         if (dev_priv->stealth) {
789                 /**
790                  * Request at least the mmio PCI resource.
791                  */
792 
793                 DRM_INFO("It appears like vesafb is loaded. "
794                          "Ignore above error if any.\n");
795                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
796                 if (unlikely(ret != 0)) {
797                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
798                         goto out_no_device;
799                 }
800         }
801 
802         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
803                 ret = drm_irq_install(dev, dev->pdev->irq);
804                 if (ret != 0) {
805                         DRM_ERROR("Failed installing irq: %d\n", ret);
806                         goto out_no_irq;
807                 }
808         }
809 
810         dev_priv->fman = vmw_fence_manager_init(dev_priv);
811         if (unlikely(dev_priv->fman == NULL)) {
812                 ret = -ENOMEM;
813                 goto out_no_fman;
814         }
815 
816         vmw_kms_save_vga(dev_priv);
817 
818         /* Start kms and overlay systems, needs fifo. */
819         ret = vmw_kms_init(dev_priv);
820         if (unlikely(ret != 0))
821                 goto out_no_kms;
822         vmw_overlay_init(dev_priv);
823 
824         if (dev_priv->enable_fb) {
825                 ret = vmw_3d_resource_inc(dev_priv, true);
826                 if (unlikely(ret != 0))
827                         goto out_no_fifo;
828                 vmw_fb_init(dev_priv);
829         }
830 
831         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
832         register_pm_notifier(&dev_priv->pm_nb);
833 
834         return 0;
835 
836 out_no_fifo:
837         vmw_overlay_close(dev_priv);
838         vmw_kms_close(dev_priv);
839 out_no_kms:
840         vmw_kms_restore_vga(dev_priv);
841         vmw_fence_manager_takedown(dev_priv->fman);
842 out_no_fman:
843         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
844                 drm_irq_uninstall(dev_priv->dev);
845 out_no_irq:
846         if (dev_priv->stealth)
847                 pci_release_region(dev->pdev, 2);
848         else
849                 pci_release_regions(dev->pdev);
850 out_no_device:
851         ttm_object_device_release(&dev_priv->tdev);
852 out_err4:
853         iounmap(dev_priv->mmio_virt);
854 out_err3:
855         arch_phys_wc_del(dev_priv->mmio_mtrr);
856         if (dev_priv->has_mob)
857                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
858         if (dev_priv->has_gmr)
859                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
860         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
861 out_err2:
862         (void)ttm_bo_device_release(&dev_priv->bdev);
863 out_err1:
864         vmw_ttm_global_release(dev_priv);
865 out_err0:
866         for (i = vmw_res_context; i < vmw_res_max; ++i)
867                 idr_destroy(&dev_priv->res_idr[i]);
868 
869         kfree(dev_priv);
870         return ret;
871 }
872 
873 static int vmw_driver_unload(struct drm_device *dev)
874 {
875         struct vmw_private *dev_priv = vmw_priv(dev);
876         enum vmw_res_type i;
877 
878         unregister_pm_notifier(&dev_priv->pm_nb);
879 
880         if (dev_priv->ctx.res_ht_initialized)
881                 drm_ht_remove(&dev_priv->ctx.res_ht);
882         vfree(dev_priv->ctx.cmd_bounce);
883         if (dev_priv->enable_fb) {
884                 vmw_fb_close(dev_priv);
885                 vmw_kms_restore_vga(dev_priv);
886                 vmw_3d_resource_dec(dev_priv, false);
887         }
888         vmw_kms_close(dev_priv);
889         vmw_overlay_close(dev_priv);
890         vmw_fence_manager_takedown(dev_priv->fman);
891         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
892                 drm_irq_uninstall(dev_priv->dev);
893         if (dev_priv->stealth)
894                 pci_release_region(dev->pdev, 2);
895         else
896                 pci_release_regions(dev->pdev);
897 
898         ttm_object_device_release(&dev_priv->tdev);
899         iounmap(dev_priv->mmio_virt);
900         arch_phys_wc_del(dev_priv->mmio_mtrr);
901         if (dev_priv->has_mob)
902                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
903         if (dev_priv->has_gmr)
904                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
905         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
906         (void)ttm_bo_device_release(&dev_priv->bdev);
907         vmw_ttm_global_release(dev_priv);
908 
909         for (i = vmw_res_context; i < vmw_res_max; ++i)
910                 idr_destroy(&dev_priv->res_idr[i]);
911 
912         kfree(dev_priv);
913 
914         return 0;
915 }
916 
917 static void vmw_preclose(struct drm_device *dev,
918                          struct drm_file *file_priv)
919 {
920         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
921         struct vmw_private *dev_priv = vmw_priv(dev);
922 
923         vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
924 }
925 
926 static void vmw_postclose(struct drm_device *dev,
927                          struct drm_file *file_priv)
928 {
929         struct vmw_fpriv *vmw_fp;
930 
931         vmw_fp = vmw_fpriv(file_priv);
932 
933         if (vmw_fp->locked_master) {
934                 struct vmw_master *vmaster =
935                         vmw_master(vmw_fp->locked_master);
936 
937                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
938                 ttm_vt_unlock(&vmaster->lock);
939                 drm_master_put(&vmw_fp->locked_master);
940         }
941 
942         ttm_object_file_release(&vmw_fp->tfile);
943         kfree(vmw_fp);
944 }
945 
946 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
947 {
948         struct vmw_private *dev_priv = vmw_priv(dev);
949         struct vmw_fpriv *vmw_fp;
950         int ret = -ENOMEM;
951 
952         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
953         if (unlikely(vmw_fp == NULL))
954                 return ret;
955 
956         INIT_LIST_HEAD(&vmw_fp->fence_events);
957         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
958         if (unlikely(vmw_fp->tfile == NULL))
959                 goto out_no_tfile;
960 
961         file_priv->driver_priv = vmw_fp;
962 
963         return 0;
964 
965 out_no_tfile:
966         kfree(vmw_fp);
967         return ret;
968 }
969 
970 static struct vmw_master *vmw_master_check(struct drm_device *dev,
971                                            struct drm_file *file_priv,
972                                            unsigned int flags)
973 {
974         int ret;
975         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
976         struct vmw_master *vmaster;
977 
978         if (file_priv->minor->type != DRM_MINOR_LEGACY ||
979             !(flags & DRM_AUTH))
980                 return NULL;
981 
982         ret = mutex_lock_interruptible(&dev->master_mutex);
983         if (unlikely(ret != 0))
984                 return ERR_PTR(-ERESTARTSYS);
985 
986         if (file_priv->is_master) {
987                 mutex_unlock(&dev->master_mutex);
988                 return NULL;
989         }
990 
991         /*
992          * Check if we were previously master, but now dropped.
993          */
994         if (vmw_fp->locked_master) {
995                 mutex_unlock(&dev->master_mutex);
996                 DRM_ERROR("Dropped master trying to access ioctl that "
997                           "requires authentication.\n");
998                 return ERR_PTR(-EACCES);
999         }
1000         mutex_unlock(&dev->master_mutex);
1001 
1002         /*
1003          * Taking the drm_global_mutex after the TTM lock might deadlock
1004          */
1005         if (!(flags & DRM_UNLOCKED)) {
1006                 DRM_ERROR("Refusing locked ioctl access.\n");
1007                 return ERR_PTR(-EDEADLK);
1008         }
1009 
1010         /*
1011          * Take the TTM lock. Possibly sleep waiting for the authenticating
1012          * master to become master again, or for a SIGTERM if the
1013          * authenticating master exits.
1014          */
1015         vmaster = vmw_master(file_priv->master);
1016         ret = ttm_read_lock(&vmaster->lock, true);
1017         if (unlikely(ret != 0))
1018                 vmaster = ERR_PTR(ret);
1019 
1020         return vmaster;
1021 }
1022 
1023 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1024                               unsigned long arg,
1025                               long (*ioctl_func)(struct file *, unsigned int,
1026                                                  unsigned long))
1027 {
1028         struct drm_file *file_priv = filp->private_data;
1029         struct drm_device *dev = file_priv->minor->dev;
1030         unsigned int nr = DRM_IOCTL_NR(cmd);
1031         struct vmw_master *vmaster;
1032         unsigned int flags;
1033         long ret;
1034 
1035         /*
1036          * Do extra checking on driver private ioctls.
1037          */
1038 
1039         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1040             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1041                 const struct drm_ioctl_desc *ioctl =
1042                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1043 
1044                 if (unlikely(ioctl->cmd_drv != cmd)) {
1045                         DRM_ERROR("Invalid command format, ioctl %d\n",
1046                                   nr - DRM_COMMAND_BASE);
1047                         return -EINVAL;
1048                 }
1049                 flags = ioctl->flags;
1050         } else if (!drm_ioctl_flags(nr, &flags))
1051                 return -EINVAL;
1052 
1053         vmaster = vmw_master_check(dev, file_priv, flags);
1054         if (unlikely(IS_ERR(vmaster))) {
1055                 ret = PTR_ERR(vmaster);
1056 
1057                 if (ret != -ERESTARTSYS)
1058                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1059                                  nr, ret);
1060                 return ret;
1061         }
1062 
1063         ret = ioctl_func(filp, cmd, arg);
1064         if (vmaster)
1065                 ttm_read_unlock(&vmaster->lock);
1066 
1067         return ret;
1068 }
1069 
1070 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1071                                unsigned long arg)
1072 {
1073         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1074 }
1075 
1076 #ifdef CONFIG_COMPAT
1077 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1078                              unsigned long arg)
1079 {
1080         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1081 }
1082 #endif
1083 
1084 static void vmw_lastclose(struct drm_device *dev)
1085 {
1086         struct drm_crtc *crtc;
1087         struct drm_mode_set set;
1088         int ret;
1089 
1090         set.x = 0;
1091         set.y = 0;
1092         set.fb = NULL;
1093         set.mode = NULL;
1094         set.connectors = NULL;
1095         set.num_connectors = 0;
1096 
1097         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1098                 set.crtc = crtc;
1099                 ret = drm_mode_set_config_internal(&set);
1100                 WARN_ON(ret != 0);
1101         }
1102 
1103 }
1104 
1105 static void vmw_master_init(struct vmw_master *vmaster)
1106 {
1107         ttm_lock_init(&vmaster->lock);
1108         INIT_LIST_HEAD(&vmaster->fb_surf);
1109         mutex_init(&vmaster->fb_surf_mutex);
1110 }
1111 
1112 static int vmw_master_create(struct drm_device *dev,
1113                              struct drm_master *master)
1114 {
1115         struct vmw_master *vmaster;
1116 
1117         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1118         if (unlikely(vmaster == NULL))
1119                 return -ENOMEM;
1120 
1121         vmw_master_init(vmaster);
1122         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1123         master->driver_priv = vmaster;
1124 
1125         return 0;
1126 }
1127 
1128 static void vmw_master_destroy(struct drm_device *dev,
1129                                struct drm_master *master)
1130 {
1131         struct vmw_master *vmaster = vmw_master(master);
1132 
1133         master->driver_priv = NULL;
1134         kfree(vmaster);
1135 }
1136 
1137 
1138 static int vmw_master_set(struct drm_device *dev,
1139                           struct drm_file *file_priv,
1140                           bool from_open)
1141 {
1142         struct vmw_private *dev_priv = vmw_priv(dev);
1143         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1144         struct vmw_master *active = dev_priv->active_master;
1145         struct vmw_master *vmaster = vmw_master(file_priv->master);
1146         int ret = 0;
1147 
1148         if (!dev_priv->enable_fb) {
1149                 ret = vmw_3d_resource_inc(dev_priv, true);
1150                 if (unlikely(ret != 0))
1151                         return ret;
1152                 vmw_kms_save_vga(dev_priv);
1153                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1154         }
1155 
1156         if (active) {
1157                 BUG_ON(active != &dev_priv->fbdev_master);
1158                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1159                 if (unlikely(ret != 0))
1160                         goto out_no_active_lock;
1161 
1162                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1163                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1164                 if (unlikely(ret != 0)) {
1165                         DRM_ERROR("Unable to clean VRAM on "
1166                                   "master drop.\n");
1167                 }
1168 
1169                 dev_priv->active_master = NULL;
1170         }
1171 
1172         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1173         if (!from_open) {
1174                 ttm_vt_unlock(&vmaster->lock);
1175                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1176                 drm_master_put(&vmw_fp->locked_master);
1177         }
1178 
1179         dev_priv->active_master = vmaster;
1180 
1181         return 0;
1182 
1183 out_no_active_lock:
1184         if (!dev_priv->enable_fb) {
1185                 vmw_kms_restore_vga(dev_priv);
1186                 vmw_3d_resource_dec(dev_priv, true);
1187                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1188         }
1189         return ret;
1190 }
1191 
1192 static void vmw_master_drop(struct drm_device *dev,
1193                             struct drm_file *file_priv,
1194                             bool from_release)
1195 {
1196         struct vmw_private *dev_priv = vmw_priv(dev);
1197         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1198         struct vmw_master *vmaster = vmw_master(file_priv->master);
1199         int ret;
1200 
1201         /**
1202          * Make sure the master doesn't disappear while we have
1203          * it locked.
1204          */
1205 
1206         vmw_fp->locked_master = drm_master_get(file_priv->master);
1207         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1208         if (unlikely((ret != 0))) {
1209                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1210                 drm_master_put(&vmw_fp->locked_master);
1211         }
1212 
1213         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1214         vmw_execbuf_release_pinned_bo(dev_priv);
1215 
1216         if (!dev_priv->enable_fb) {
1217                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1218                 if (unlikely(ret != 0))
1219                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
1220                 vmw_kms_restore_vga(dev_priv);
1221                 vmw_3d_resource_dec(dev_priv, true);
1222                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1223         }
1224 
1225         dev_priv->active_master = &dev_priv->fbdev_master;
1226         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1227         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1228 
1229         if (dev_priv->enable_fb)
1230                 vmw_fb_on(dev_priv);
1231 }
1232 
1233 
1234 static void vmw_remove(struct pci_dev *pdev)
1235 {
1236         struct drm_device *dev = pci_get_drvdata(pdev);
1237 
1238         drm_put_dev(dev);
1239 }
1240 
1241 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1242                               void *ptr)
1243 {
1244         struct vmw_private *dev_priv =
1245                 container_of(nb, struct vmw_private, pm_nb);
1246 
1247         switch (val) {
1248         case PM_HIBERNATION_PREPARE:
1249         case PM_SUSPEND_PREPARE:
1250                 ttm_suspend_lock(&dev_priv->reservation_sem);
1251 
1252                 /**
1253                  * This empties VRAM and unbinds all GMR bindings.
1254                  * Buffer contents is moved to swappable memory.
1255                  */
1256                 vmw_execbuf_release_pinned_bo(dev_priv);
1257                 vmw_resource_evict_all(dev_priv);
1258                 ttm_bo_swapout_all(&dev_priv->bdev);
1259 
1260                 break;
1261         case PM_POST_HIBERNATION:
1262         case PM_POST_SUSPEND:
1263         case PM_POST_RESTORE:
1264                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1265 
1266                 break;
1267         case PM_RESTORE_PREPARE:
1268                 break;
1269         default:
1270                 break;
1271         }
1272         return 0;
1273 }
1274 
1275 /**
1276  * These might not be needed with the virtual SVGA device.
1277  */
1278 
1279 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1280 {
1281         struct drm_device *dev = pci_get_drvdata(pdev);
1282         struct vmw_private *dev_priv = vmw_priv(dev);
1283 
1284         if (dev_priv->num_3d_resources != 0) {
1285                 DRM_INFO("Can't suspend or hibernate "
1286                          "while 3D resources are active.\n");
1287                 return -EBUSY;
1288         }
1289 
1290         pci_save_state(pdev);
1291         pci_disable_device(pdev);
1292         pci_set_power_state(pdev, PCI_D3hot);
1293         return 0;
1294 }
1295 
1296 static int vmw_pci_resume(struct pci_dev *pdev)
1297 {
1298         pci_set_power_state(pdev, PCI_D0);
1299         pci_restore_state(pdev);
1300         return pci_enable_device(pdev);
1301 }
1302 
1303 static int vmw_pm_suspend(struct device *kdev)
1304 {
1305         struct pci_dev *pdev = to_pci_dev(kdev);
1306         struct pm_message dummy;
1307 
1308         dummy.event = 0;
1309 
1310         return vmw_pci_suspend(pdev, dummy);
1311 }
1312 
1313 static int vmw_pm_resume(struct device *kdev)
1314 {
1315         struct pci_dev *pdev = to_pci_dev(kdev);
1316 
1317         return vmw_pci_resume(pdev);
1318 }
1319 
1320 static int vmw_pm_prepare(struct device *kdev)
1321 {
1322         struct pci_dev *pdev = to_pci_dev(kdev);
1323         struct drm_device *dev = pci_get_drvdata(pdev);
1324         struct vmw_private *dev_priv = vmw_priv(dev);
1325 
1326         /**
1327          * Release 3d reference held by fbdev and potentially
1328          * stop fifo.
1329          */
1330         dev_priv->suspended = true;
1331         if (dev_priv->enable_fb)
1332                         vmw_3d_resource_dec(dev_priv, true);
1333 
1334         if (dev_priv->num_3d_resources != 0) {
1335 
1336                 DRM_INFO("Can't suspend or hibernate "
1337                          "while 3D resources are active.\n");
1338 
1339                 if (dev_priv->enable_fb)
1340                         vmw_3d_resource_inc(dev_priv, true);
1341                 dev_priv->suspended = false;
1342                 return -EBUSY;
1343         }
1344 
1345         return 0;
1346 }
1347 
1348 static void vmw_pm_complete(struct device *kdev)
1349 {
1350         struct pci_dev *pdev = to_pci_dev(kdev);
1351         struct drm_device *dev = pci_get_drvdata(pdev);
1352         struct vmw_private *dev_priv = vmw_priv(dev);
1353 
1354         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1355         (void) vmw_read(dev_priv, SVGA_REG_ID);
1356 
1357         /**
1358          * Reclaim 3d reference held by fbdev and potentially
1359          * start fifo.
1360          */
1361         if (dev_priv->enable_fb)
1362                         vmw_3d_resource_inc(dev_priv, false);
1363 
1364         dev_priv->suspended = false;
1365 }
1366 
1367 static const struct dev_pm_ops vmw_pm_ops = {
1368         .prepare = vmw_pm_prepare,
1369         .complete = vmw_pm_complete,
1370         .suspend = vmw_pm_suspend,
1371         .resume = vmw_pm_resume,
1372 };
1373 
1374 static const struct file_operations vmwgfx_driver_fops = {
1375         .owner = THIS_MODULE,
1376         .open = drm_open,
1377         .release = drm_release,
1378         .unlocked_ioctl = vmw_unlocked_ioctl,
1379         .mmap = vmw_mmap,
1380         .poll = vmw_fops_poll,
1381         .read = vmw_fops_read,
1382 #if defined(CONFIG_COMPAT)
1383         .compat_ioctl = vmw_compat_ioctl,
1384 #endif
1385         .llseek = noop_llseek,
1386 };
1387 
1388 static struct drm_driver driver = {
1389         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1390         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1391         .load = vmw_driver_load,
1392         .unload = vmw_driver_unload,
1393         .lastclose = vmw_lastclose,
1394         .irq_preinstall = vmw_irq_preinstall,
1395         .irq_postinstall = vmw_irq_postinstall,
1396         .irq_uninstall = vmw_irq_uninstall,
1397         .irq_handler = vmw_irq_handler,
1398         .get_vblank_counter = vmw_get_vblank_counter,
1399         .enable_vblank = vmw_enable_vblank,
1400         .disable_vblank = vmw_disable_vblank,
1401         .ioctls = vmw_ioctls,
1402         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1403         .master_create = vmw_master_create,
1404         .master_destroy = vmw_master_destroy,
1405         .master_set = vmw_master_set,
1406         .master_drop = vmw_master_drop,
1407         .open = vmw_driver_open,
1408         .preclose = vmw_preclose,
1409         .postclose = vmw_postclose,
1410         .set_busid = drm_pci_set_busid,
1411 
1412         .dumb_create = vmw_dumb_create,
1413         .dumb_map_offset = vmw_dumb_map_offset,
1414         .dumb_destroy = vmw_dumb_destroy,
1415 
1416         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1417         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1418 
1419         .fops = &vmwgfx_driver_fops,
1420         .name = VMWGFX_DRIVER_NAME,
1421         .desc = VMWGFX_DRIVER_DESC,
1422         .date = VMWGFX_DRIVER_DATE,
1423         .major = VMWGFX_DRIVER_MAJOR,
1424         .minor = VMWGFX_DRIVER_MINOR,
1425         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1426 };
1427 
1428 static struct pci_driver vmw_pci_driver = {
1429         .name = VMWGFX_DRIVER_NAME,
1430         .id_table = vmw_pci_id_list,
1431         .probe = vmw_probe,
1432         .remove = vmw_remove,
1433         .driver = {
1434                 .pm = &vmw_pm_ops
1435         }
1436 };
1437 
1438 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1439 {
1440         return drm_get_pci_dev(pdev, ent, &driver);
1441 }
1442 
1443 static int __init vmwgfx_init(void)
1444 {
1445         int ret;
1446         ret = drm_pci_init(&driver, &vmw_pci_driver);
1447         if (ret)
1448                 DRM_ERROR("Failed initializing DRM.\n");
1449         return ret;
1450 }
1451 
1452 static void __exit vmwgfx_exit(void)
1453 {
1454         drm_pci_exit(&driver, &vmw_pci_driver);
1455 }
1456 
1457 module_init(vmwgfx_init);
1458 module_exit(vmwgfx_exit);
1459 
1460 MODULE_AUTHOR("VMware Inc. and others");
1461 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1462 MODULE_LICENSE("GPL and additional rights");
1463 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1464                __stringify(VMWGFX_DRIVER_MINOR) "."
1465                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1466                "");
1467 

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