Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/gpu/drm/tilcdc/tilcdc_drv.c

  1 /*
  2  * Copyright (C) 2012 Texas Instruments
  3  * Author: Rob Clark <robdclark@gmail.com>
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 as published by
  7  * the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  *
 14  * You should have received a copy of the GNU General Public License along with
 15  * this program.  If not, see <http://www.gnu.org/licenses/>.
 16  */
 17 
 18 /* LCDC DRM driver, based on da8xx-fb */
 19 
 20 #include <linux/component.h>
 21 #include <linux/pinctrl/consumer.h>
 22 #include <linux/suspend.h>
 23 #include <drm/drm_atomic.h>
 24 #include <drm/drm_atomic_helper.h>
 25 
 26 #include "tilcdc_drv.h"
 27 #include "tilcdc_regs.h"
 28 #include "tilcdc_tfp410.h"
 29 #include "tilcdc_panel.h"
 30 #include "tilcdc_external.h"
 31 
 32 #include "drm_fb_helper.h"
 33 
 34 static LIST_HEAD(module_list);
 35 
 36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
 37 
 38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
 39                                                DRM_FORMAT_BGR888,
 40                                                DRM_FORMAT_XBGR8888 };
 41 
 42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
 43                                               DRM_FORMAT_RGB888,
 44                                               DRM_FORMAT_XRGB8888 };
 45 
 46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
 47                                              DRM_FORMAT_RGB888,
 48                                              DRM_FORMAT_XRGB8888 };
 49 
 50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
 51                 const struct tilcdc_module_ops *funcs)
 52 {
 53         mod->name = name;
 54         mod->funcs = funcs;
 55         INIT_LIST_HEAD(&mod->list);
 56         list_add(&mod->list, &module_list);
 57 }
 58 
 59 void tilcdc_module_cleanup(struct tilcdc_module *mod)
 60 {
 61         list_del(&mod->list);
 62 }
 63 
 64 static struct of_device_id tilcdc_of_match[];
 65 
 66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
 67                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
 68 {
 69         return drm_fb_cma_create(dev, file_priv, mode_cmd);
 70 }
 71 
 72 static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
 73 {
 74         struct tilcdc_drm_private *priv = dev->dev_private;
 75         drm_fbdev_cma_hotplug_event(priv->fbdev);
 76 }
 77 
 78 static int tilcdc_atomic_check(struct drm_device *dev,
 79                                struct drm_atomic_state *state)
 80 {
 81         int ret;
 82 
 83         ret = drm_atomic_helper_check_modeset(dev, state);
 84         if (ret)
 85                 return ret;
 86 
 87         ret = drm_atomic_helper_check_planes(dev, state);
 88         if (ret)
 89                 return ret;
 90 
 91         /*
 92          * tilcdc ->atomic_check can update ->mode_changed if pixel format
 93          * changes, hence will we check modeset changes again.
 94          */
 95         ret = drm_atomic_helper_check_modeset(dev, state);
 96         if (ret)
 97                 return ret;
 98 
 99         return ret;
100 }
101 
102 static int tilcdc_commit(struct drm_device *dev,
103                   struct drm_atomic_state *state,
104                   bool async)
105 {
106         int ret;
107 
108         ret = drm_atomic_helper_prepare_planes(dev, state);
109         if (ret)
110                 return ret;
111 
112         drm_atomic_helper_swap_state(state, true);
113 
114         /*
115          * Everything below can be run asynchronously without the need to grab
116          * any modeset locks at all under one condition: It must be guaranteed
117          * that the asynchronous work has either been cancelled (if the driver
118          * supports it, which at least requires that the framebuffers get
119          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
120          * before the new state gets committed on the software side with
121          * drm_atomic_helper_swap_state().
122          *
123          * This scheme allows new atomic state updates to be prepared and
124          * checked in parallel to the asynchronous completion of the previous
125          * update. Which is important since compositors need to figure out the
126          * composition of the next frame right after having submitted the
127          * current layout.
128          */
129 
130         /* Keep HW on while we commit the state. */
131         pm_runtime_get_sync(dev->dev);
132 
133         drm_atomic_helper_commit_modeset_disables(dev, state);
134 
135         drm_atomic_helper_commit_planes(dev, state, 0);
136 
137         drm_atomic_helper_commit_modeset_enables(dev, state);
138 
139         /* Now HW should remain on if need becase the crtc is enabled */
140         pm_runtime_put_sync(dev->dev);
141 
142         drm_atomic_helper_wait_for_vblanks(dev, state);
143 
144         drm_atomic_helper_cleanup_planes(dev, state);
145 
146         drm_atomic_state_free(state);
147 
148         return 0;
149 }
150 
151 static const struct drm_mode_config_funcs mode_config_funcs = {
152         .fb_create = tilcdc_fb_create,
153         .output_poll_changed = tilcdc_fb_output_poll_changed,
154         .atomic_check = tilcdc_atomic_check,
155         .atomic_commit = tilcdc_commit,
156 };
157 
158 static int modeset_init(struct drm_device *dev)
159 {
160         struct tilcdc_drm_private *priv = dev->dev_private;
161         struct tilcdc_module *mod;
162 
163         drm_mode_config_init(dev);
164 
165         priv->crtc = tilcdc_crtc_create(dev);
166 
167         list_for_each_entry(mod, &module_list, list) {
168                 DBG("loading module: %s", mod->name);
169                 mod->funcs->modeset_init(mod, dev);
170         }
171 
172         dev->mode_config.min_width = 0;
173         dev->mode_config.min_height = 0;
174         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
175         dev->mode_config.max_height = 2048;
176         dev->mode_config.funcs = &mode_config_funcs;
177 
178         return 0;
179 }
180 
181 #ifdef CONFIG_CPU_FREQ
182 static int cpufreq_transition(struct notifier_block *nb,
183                                      unsigned long val, void *data)
184 {
185         struct tilcdc_drm_private *priv = container_of(nb,
186                         struct tilcdc_drm_private, freq_transition);
187 
188         if (val == CPUFREQ_POSTCHANGE)
189                 tilcdc_crtc_update_clk(priv->crtc);
190 
191         return 0;
192 }
193 #endif
194 
195 /*
196  * DRM operations:
197  */
198 
199 static int tilcdc_unload(struct drm_device *dev)
200 {
201         struct tilcdc_drm_private *priv = dev->dev_private;
202 
203         tilcdc_remove_external_encoders(dev);
204 
205         drm_fbdev_cma_fini(priv->fbdev);
206         drm_kms_helper_poll_fini(dev);
207         drm_mode_config_cleanup(dev);
208         drm_vblank_cleanup(dev);
209 
210         drm_irq_uninstall(dev);
211 
212 #ifdef CONFIG_CPU_FREQ
213         cpufreq_unregister_notifier(&priv->freq_transition,
214                         CPUFREQ_TRANSITION_NOTIFIER);
215 #endif
216 
217         if (priv->clk)
218                 clk_put(priv->clk);
219 
220         if (priv->mmio)
221                 iounmap(priv->mmio);
222 
223         flush_workqueue(priv->wq);
224         destroy_workqueue(priv->wq);
225 
226         dev->dev_private = NULL;
227 
228         pm_runtime_disable(dev->dev);
229 
230         return 0;
231 }
232 
233 static int tilcdc_load(struct drm_device *dev, unsigned long flags)
234 {
235         struct platform_device *pdev = dev->platformdev;
236         struct device_node *node = pdev->dev.of_node;
237         struct tilcdc_drm_private *priv;
238         struct resource *res;
239         u32 bpp = 0;
240         int ret;
241 
242         priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
243         if (!priv) {
244                 dev_err(dev->dev, "failed to allocate private data\n");
245                 return -ENOMEM;
246         }
247 
248         dev->dev_private = priv;
249 
250         priv->is_componentized =
251                 tilcdc_get_external_components(dev->dev, NULL) > 0;
252 
253         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
254         if (!priv->wq) {
255                 ret = -ENOMEM;
256                 goto fail_unset_priv;
257         }
258 
259         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
260         if (!res) {
261                 dev_err(dev->dev, "failed to get memory resource\n");
262                 ret = -EINVAL;
263                 goto fail_free_wq;
264         }
265 
266         priv->mmio = ioremap_nocache(res->start, resource_size(res));
267         if (!priv->mmio) {
268                 dev_err(dev->dev, "failed to ioremap\n");
269                 ret = -ENOMEM;
270                 goto fail_free_wq;
271         }
272 
273         priv->clk = clk_get(dev->dev, "fck");
274         if (IS_ERR(priv->clk)) {
275                 dev_err(dev->dev, "failed to get functional clock\n");
276                 ret = -ENODEV;
277                 goto fail_iounmap;
278         }
279 
280 #ifdef CONFIG_CPU_FREQ
281         priv->freq_transition.notifier_call = cpufreq_transition;
282         ret = cpufreq_register_notifier(&priv->freq_transition,
283                         CPUFREQ_TRANSITION_NOTIFIER);
284         if (ret) {
285                 dev_err(dev->dev, "failed to register cpufreq notifier\n");
286                 goto fail_put_clk;
287         }
288 #endif
289 
290         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
291                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
292 
293         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
294 
295         if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
296                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
297 
298         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
299 
300         if (of_property_read_u32(node, "ti,max-pixelclock",
301                                         &priv->max_pixelclock))
302                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
303 
304         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
305 
306         pm_runtime_enable(dev->dev);
307 
308         /* Determine LCD IP Version */
309         pm_runtime_get_sync(dev->dev);
310         switch (tilcdc_read(dev, LCDC_PID_REG)) {
311         case 0x4c100102:
312                 priv->rev = 1;
313                 break;
314         case 0x4f200800:
315         case 0x4f201000:
316                 priv->rev = 2;
317                 break;
318         default:
319                 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
320                                 "defaulting to LCD revision 1\n",
321                                 tilcdc_read(dev, LCDC_PID_REG));
322                 priv->rev = 1;
323                 break;
324         }
325 
326         pm_runtime_put_sync(dev->dev);
327 
328         if (priv->rev == 1) {
329                 DBG("Revision 1 LCDC supports only RGB565 format");
330                 priv->pixelformats = tilcdc_rev1_formats;
331                 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
332                 bpp = 16;
333         } else {
334                 const char *str = "\0";
335 
336                 of_property_read_string(node, "blue-and-red-wiring", &str);
337                 if (0 == strcmp(str, "crossed")) {
338                         DBG("Configured for crossed blue and red wires");
339                         priv->pixelformats = tilcdc_crossed_formats;
340                         priv->num_pixelformats =
341                                 ARRAY_SIZE(tilcdc_crossed_formats);
342                         bpp = 32; /* Choose bpp with RGB support for fbdef */
343                 } else if (0 == strcmp(str, "straight")) {
344                         DBG("Configured for straight blue and red wires");
345                         priv->pixelformats = tilcdc_straight_formats;
346                         priv->num_pixelformats =
347                                 ARRAY_SIZE(tilcdc_straight_formats);
348                         bpp = 16; /* Choose bpp with RGB support for fbdef */
349                 } else {
350                         DBG("Blue and red wiring '%s' unknown, use legacy mode",
351                             str);
352                         priv->pixelformats = tilcdc_legacy_formats;
353                         priv->num_pixelformats =
354                                 ARRAY_SIZE(tilcdc_legacy_formats);
355                         bpp = 16; /* This is just a guess */
356                 }
357         }
358 
359         ret = modeset_init(dev);
360         if (ret < 0) {
361                 dev_err(dev->dev, "failed to initialize mode setting\n");
362                 goto fail_cpufreq_unregister;
363         }
364 
365         platform_set_drvdata(pdev, dev);
366 
367         if (priv->is_componentized) {
368                 ret = component_bind_all(dev->dev, dev);
369                 if (ret < 0)
370                         goto fail_mode_config_cleanup;
371 
372                 ret = tilcdc_add_external_encoders(dev);
373                 if (ret < 0)
374                         goto fail_component_cleanup;
375         }
376 
377         if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
378                 dev_err(dev->dev, "no encoders/connectors found\n");
379                 ret = -ENXIO;
380                 goto fail_external_cleanup;
381         }
382 
383         ret = drm_vblank_init(dev, 1);
384         if (ret < 0) {
385                 dev_err(dev->dev, "failed to initialize vblank\n");
386                 goto fail_external_cleanup;
387         }
388 
389         ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
390         if (ret < 0) {
391                 dev_err(dev->dev, "failed to install IRQ handler\n");
392                 goto fail_vblank_cleanup;
393         }
394 
395         drm_mode_config_reset(dev);
396 
397         priv->fbdev = drm_fbdev_cma_init(dev, bpp,
398                         dev->mode_config.num_crtc,
399                         dev->mode_config.num_connector);
400         if (IS_ERR(priv->fbdev)) {
401                 ret = PTR_ERR(priv->fbdev);
402                 goto fail_irq_uninstall;
403         }
404 
405         drm_kms_helper_poll_init(dev);
406 
407         return 0;
408 
409 fail_irq_uninstall:
410         drm_irq_uninstall(dev);
411 
412 fail_vblank_cleanup:
413         drm_vblank_cleanup(dev);
414 
415 fail_component_cleanup:
416         if (priv->is_componentized)
417                 component_unbind_all(dev->dev, dev);
418 
419 fail_mode_config_cleanup:
420         drm_mode_config_cleanup(dev);
421 
422 fail_external_cleanup:
423         tilcdc_remove_external_encoders(dev);
424 
425 fail_cpufreq_unregister:
426         pm_runtime_disable(dev->dev);
427 #ifdef CONFIG_CPU_FREQ
428         cpufreq_unregister_notifier(&priv->freq_transition,
429                         CPUFREQ_TRANSITION_NOTIFIER);
430 
431 fail_put_clk:
432 #endif
433         clk_put(priv->clk);
434 
435 fail_iounmap:
436         iounmap(priv->mmio);
437 
438 fail_free_wq:
439         flush_workqueue(priv->wq);
440         destroy_workqueue(priv->wq);
441 
442 fail_unset_priv:
443         dev->dev_private = NULL;
444 
445         return ret;
446 }
447 
448 static void tilcdc_lastclose(struct drm_device *dev)
449 {
450         struct tilcdc_drm_private *priv = dev->dev_private;
451         drm_fbdev_cma_restore_mode(priv->fbdev);
452 }
453 
454 static irqreturn_t tilcdc_irq(int irq, void *arg)
455 {
456         struct drm_device *dev = arg;
457         struct tilcdc_drm_private *priv = dev->dev_private;
458         return tilcdc_crtc_irq(priv->crtc);
459 }
460 
461 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
462 {
463         return 0;
464 }
465 
466 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
467 {
468         return;
469 }
470 
471 #if defined(CONFIG_DEBUG_FS)
472 static const struct {
473         const char *name;
474         uint8_t  rev;
475         uint8_t  save;
476         uint32_t reg;
477 } registers[] =         {
478 #define REG(rev, save, reg) { #reg, rev, save, reg }
479                 /* exists in revision 1: */
480                 REG(1, false, LCDC_PID_REG),
481                 REG(1, true,  LCDC_CTRL_REG),
482                 REG(1, false, LCDC_STAT_REG),
483                 REG(1, true,  LCDC_RASTER_CTRL_REG),
484                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
485                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
486                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
487                 REG(1, true,  LCDC_DMA_CTRL_REG),
488                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
489                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
490                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
491                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
492                 /* new in revision 2: */
493                 REG(2, false, LCDC_RAW_STAT_REG),
494                 REG(2, false, LCDC_MASKED_STAT_REG),
495                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
496                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
497                 REG(2, false, LCDC_END_OF_INT_IND_REG),
498                 REG(2, true,  LCDC_CLK_ENABLE_REG),
499 #undef REG
500 };
501 
502 #endif
503 
504 #ifdef CONFIG_DEBUG_FS
505 static int tilcdc_regs_show(struct seq_file *m, void *arg)
506 {
507         struct drm_info_node *node = (struct drm_info_node *) m->private;
508         struct drm_device *dev = node->minor->dev;
509         struct tilcdc_drm_private *priv = dev->dev_private;
510         unsigned i;
511 
512         pm_runtime_get_sync(dev->dev);
513 
514         seq_printf(m, "revision: %d\n", priv->rev);
515 
516         for (i = 0; i < ARRAY_SIZE(registers); i++)
517                 if (priv->rev >= registers[i].rev)
518                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
519                                         tilcdc_read(dev, registers[i].reg));
520 
521         pm_runtime_put_sync(dev->dev);
522 
523         return 0;
524 }
525 
526 static int tilcdc_mm_show(struct seq_file *m, void *arg)
527 {
528         struct drm_info_node *node = (struct drm_info_node *) m->private;
529         struct drm_device *dev = node->minor->dev;
530         return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
531 }
532 
533 static struct drm_info_list tilcdc_debugfs_list[] = {
534                 { "regs", tilcdc_regs_show, 0 },
535                 { "mm",   tilcdc_mm_show,   0 },
536                 { "fb",   drm_fb_cma_debugfs_show, 0 },
537 };
538 
539 static int tilcdc_debugfs_init(struct drm_minor *minor)
540 {
541         struct drm_device *dev = minor->dev;
542         struct tilcdc_module *mod;
543         int ret;
544 
545         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
546                         ARRAY_SIZE(tilcdc_debugfs_list),
547                         minor->debugfs_root, minor);
548 
549         list_for_each_entry(mod, &module_list, list)
550                 if (mod->funcs->debugfs_init)
551                         mod->funcs->debugfs_init(mod, minor);
552 
553         if (ret) {
554                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
555                 return ret;
556         }
557 
558         return ret;
559 }
560 
561 static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
562 {
563         struct tilcdc_module *mod;
564         drm_debugfs_remove_files(tilcdc_debugfs_list,
565                         ARRAY_SIZE(tilcdc_debugfs_list), minor);
566 
567         list_for_each_entry(mod, &module_list, list)
568                 if (mod->funcs->debugfs_cleanup)
569                         mod->funcs->debugfs_cleanup(mod, minor);
570 }
571 #endif
572 
573 static const struct file_operations fops = {
574         .owner              = THIS_MODULE,
575         .open               = drm_open,
576         .release            = drm_release,
577         .unlocked_ioctl     = drm_ioctl,
578 #ifdef CONFIG_COMPAT
579         .compat_ioctl       = drm_compat_ioctl,
580 #endif
581         .poll               = drm_poll,
582         .read               = drm_read,
583         .llseek             = no_llseek,
584         .mmap               = drm_gem_cma_mmap,
585 };
586 
587 static struct drm_driver tilcdc_driver = {
588         .driver_features    = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
589                                DRIVER_PRIME | DRIVER_ATOMIC),
590         .load               = tilcdc_load,
591         .unload             = tilcdc_unload,
592         .lastclose          = tilcdc_lastclose,
593         .irq_handler        = tilcdc_irq,
594         .get_vblank_counter = drm_vblank_no_hw_counter,
595         .enable_vblank      = tilcdc_enable_vblank,
596         .disable_vblank     = tilcdc_disable_vblank,
597         .gem_free_object_unlocked = drm_gem_cma_free_object,
598         .gem_vm_ops         = &drm_gem_cma_vm_ops,
599         .dumb_create        = drm_gem_cma_dumb_create,
600         .dumb_map_offset    = drm_gem_cma_dumb_map_offset,
601         .dumb_destroy       = drm_gem_dumb_destroy,
602 
603         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
604         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
605         .gem_prime_import       = drm_gem_prime_import,
606         .gem_prime_export       = drm_gem_prime_export,
607         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
608         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
609         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
610         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
611         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
612 #ifdef CONFIG_DEBUG_FS
613         .debugfs_init       = tilcdc_debugfs_init,
614         .debugfs_cleanup    = tilcdc_debugfs_cleanup,
615 #endif
616         .fops               = &fops,
617         .name               = "tilcdc",
618         .desc               = "TI LCD Controller DRM",
619         .date               = "20121205",
620         .major              = 1,
621         .minor              = 0,
622 };
623 
624 /*
625  * Power management:
626  */
627 
628 #ifdef CONFIG_PM_SLEEP
629 static int tilcdc_pm_suspend(struct device *dev)
630 {
631         struct drm_device *ddev = dev_get_drvdata(dev);
632         struct tilcdc_drm_private *priv = ddev->dev_private;
633 
634         priv->saved_state = drm_atomic_helper_suspend(ddev);
635 
636         /* Select sleep pin state */
637         pinctrl_pm_select_sleep_state(dev);
638 
639         return 0;
640 }
641 
642 static int tilcdc_pm_resume(struct device *dev)
643 {
644         struct drm_device *ddev = dev_get_drvdata(dev);
645         struct tilcdc_drm_private *priv = ddev->dev_private;
646         int ret = 0;
647 
648         /* Select default pin state */
649         pinctrl_pm_select_default_state(dev);
650 
651         if (priv->saved_state)
652                 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
653 
654         return ret;
655 }
656 #endif
657 
658 static const struct dev_pm_ops tilcdc_pm_ops = {
659         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
660 };
661 
662 /*
663  * Platform driver:
664  */
665 
666 static int tilcdc_bind(struct device *dev)
667 {
668         return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
669 }
670 
671 static void tilcdc_unbind(struct device *dev)
672 {
673         struct drm_device *ddev = dev_get_drvdata(dev);
674 
675         /* Check if a subcomponent has already triggered the unloading. */
676         if (!ddev->dev_private)
677                 return;
678 
679         drm_put_dev(dev_get_drvdata(dev));
680 }
681 
682 static const struct component_master_ops tilcdc_comp_ops = {
683         .bind = tilcdc_bind,
684         .unbind = tilcdc_unbind,
685 };
686 
687 static int tilcdc_pdev_probe(struct platform_device *pdev)
688 {
689         struct component_match *match = NULL;
690         int ret;
691 
692         /* bail out early if no DT data: */
693         if (!pdev->dev.of_node) {
694                 dev_err(&pdev->dev, "device-tree data is missing\n");
695                 return -ENXIO;
696         }
697 
698         ret = tilcdc_get_external_components(&pdev->dev, &match);
699         if (ret < 0)
700                 return ret;
701         else if (ret == 0)
702                 return drm_platform_init(&tilcdc_driver, pdev);
703         else
704                 return component_master_add_with_match(&pdev->dev,
705                                                        &tilcdc_comp_ops,
706                                                        match);
707 }
708 
709 static int tilcdc_pdev_remove(struct platform_device *pdev)
710 {
711         int ret;
712 
713         ret = tilcdc_get_external_components(&pdev->dev, NULL);
714         if (ret < 0)
715                 return ret;
716         else if (ret == 0)
717                 drm_put_dev(platform_get_drvdata(pdev));
718         else
719                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
720 
721         return 0;
722 }
723 
724 static struct of_device_id tilcdc_of_match[] = {
725                 { .compatible = "ti,am33xx-tilcdc", },
726                 { },
727 };
728 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
729 
730 static struct platform_driver tilcdc_platform_driver = {
731         .probe      = tilcdc_pdev_probe,
732         .remove     = tilcdc_pdev_remove,
733         .driver     = {
734                 .name   = "tilcdc",
735                 .pm     = &tilcdc_pm_ops,
736                 .of_match_table = tilcdc_of_match,
737         },
738 };
739 
740 static int __init tilcdc_drm_init(void)
741 {
742         DBG("init");
743         tilcdc_tfp410_init();
744         tilcdc_panel_init();
745         return platform_driver_register(&tilcdc_platform_driver);
746 }
747 
748 static void __exit tilcdc_drm_fini(void)
749 {
750         DBG("fini");
751         platform_driver_unregister(&tilcdc_platform_driver);
752         tilcdc_panel_fini();
753         tilcdc_tfp410_fini();
754 }
755 
756 module_init(tilcdc_drm_init);
757 module_exit(tilcdc_drm_fini);
758 
759 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
760 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
761 MODULE_LICENSE("GPL");
762 

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