Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/drivers/gpu/drm/tegra/dsi.c

  1 /*
  2  * Copyright (C) 2013 NVIDIA Corporation
  3  *
  4  * Permission to use, copy, modify, distribute, and sell this software and its
  5  * documentation for any purpose is hereby granted without fee, provided that
  6  * the above copyright notice appear in all copies and that both that copyright
  7  * notice and this permission notice appear in supporting documentation, and
  8  * that the name of the copyright holders not be used in advertising or
  9  * publicity pertaining to distribution of the software without specific,
 10  * written prior permission.  The copyright holders make no representations
 11  * about the suitability of this software for any purpose.  It is provided "as
 12  * is" without express or implied warranty.
 13  *
 14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
 20  * OF THIS SOFTWARE.
 21  */
 22 
 23 #include <linux/clk.h>
 24 #include <linux/debugfs.h>
 25 #include <linux/host1x.h>
 26 #include <linux/module.h>
 27 #include <linux/of.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/reset.h>
 30 
 31 #include <drm/drm_mipi_dsi.h>
 32 #include <drm/drm_panel.h>
 33 
 34 #include <video/mipi_display.h>
 35 
 36 #include "dc.h"
 37 #include "drm.h"
 38 #include "dsi.h"
 39 #include "mipi-phy.h"
 40 
 41 #define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
 42 #define DSI_HOST_FIFO_DEPTH 64
 43 
 44 struct tegra_dsi {
 45         struct host1x_client client;
 46         struct tegra_output output;
 47         struct device *dev;
 48 
 49         void __iomem *regs;
 50 
 51         struct reset_control *rst;
 52         struct clk *clk_parent;
 53         struct clk *clk_lp;
 54         struct clk *clk;
 55 
 56         struct drm_info_list *debugfs_files;
 57         struct drm_minor *minor;
 58         struct dentry *debugfs;
 59 
 60         enum mipi_dsi_pixel_format format;
 61         unsigned int lanes;
 62 
 63         struct tegra_mipi_device *mipi;
 64         struct mipi_dsi_host host;
 65 };
 66 
 67 static inline struct tegra_dsi *
 68 host1x_client_to_dsi(struct host1x_client *client)
 69 {
 70         return container_of(client, struct tegra_dsi, client);
 71 }
 72 
 73 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
 74 {
 75         return container_of(host, struct tegra_dsi, host);
 76 }
 77 
 78 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
 79 {
 80         return container_of(output, struct tegra_dsi, output);
 81 }
 82 
 83 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
 84                                             unsigned long reg)
 85 {
 86         return readl(dsi->regs + (reg << 2));
 87 }
 88 
 89 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
 90                                     unsigned long reg)
 91 {
 92         writel(value, dsi->regs + (reg << 2));
 93 }
 94 
 95 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
 96 {
 97         struct drm_info_node *node = s->private;
 98         struct tegra_dsi *dsi = node->info_ent->data;
 99 
100 #define DUMP_REG(name)                                          \
101         seq_printf(s, "%-32s %#05x %08lx\n", #name, name,       \
102                    tegra_dsi_readl(dsi, name))
103 
104         DUMP_REG(DSI_INCR_SYNCPT);
105         DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
106         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
107         DUMP_REG(DSI_CTXSW);
108         DUMP_REG(DSI_RD_DATA);
109         DUMP_REG(DSI_WR_DATA);
110         DUMP_REG(DSI_POWER_CONTROL);
111         DUMP_REG(DSI_INT_ENABLE);
112         DUMP_REG(DSI_INT_STATUS);
113         DUMP_REG(DSI_INT_MASK);
114         DUMP_REG(DSI_HOST_CONTROL);
115         DUMP_REG(DSI_CONTROL);
116         DUMP_REG(DSI_SOL_DELAY);
117         DUMP_REG(DSI_MAX_THRESHOLD);
118         DUMP_REG(DSI_TRIGGER);
119         DUMP_REG(DSI_TX_CRC);
120         DUMP_REG(DSI_STATUS);
121 
122         DUMP_REG(DSI_INIT_SEQ_CONTROL);
123         DUMP_REG(DSI_INIT_SEQ_DATA_0);
124         DUMP_REG(DSI_INIT_SEQ_DATA_1);
125         DUMP_REG(DSI_INIT_SEQ_DATA_2);
126         DUMP_REG(DSI_INIT_SEQ_DATA_3);
127         DUMP_REG(DSI_INIT_SEQ_DATA_4);
128         DUMP_REG(DSI_INIT_SEQ_DATA_5);
129         DUMP_REG(DSI_INIT_SEQ_DATA_6);
130         DUMP_REG(DSI_INIT_SEQ_DATA_7);
131 
132         DUMP_REG(DSI_PKT_SEQ_0_LO);
133         DUMP_REG(DSI_PKT_SEQ_0_HI);
134         DUMP_REG(DSI_PKT_SEQ_1_LO);
135         DUMP_REG(DSI_PKT_SEQ_1_HI);
136         DUMP_REG(DSI_PKT_SEQ_2_LO);
137         DUMP_REG(DSI_PKT_SEQ_2_HI);
138         DUMP_REG(DSI_PKT_SEQ_3_LO);
139         DUMP_REG(DSI_PKT_SEQ_3_HI);
140         DUMP_REG(DSI_PKT_SEQ_4_LO);
141         DUMP_REG(DSI_PKT_SEQ_4_HI);
142         DUMP_REG(DSI_PKT_SEQ_5_LO);
143         DUMP_REG(DSI_PKT_SEQ_5_HI);
144 
145         DUMP_REG(DSI_DCS_CMDS);
146 
147         DUMP_REG(DSI_PKT_LEN_0_1);
148         DUMP_REG(DSI_PKT_LEN_2_3);
149         DUMP_REG(DSI_PKT_LEN_4_5);
150         DUMP_REG(DSI_PKT_LEN_6_7);
151 
152         DUMP_REG(DSI_PHY_TIMING_0);
153         DUMP_REG(DSI_PHY_TIMING_1);
154         DUMP_REG(DSI_PHY_TIMING_2);
155         DUMP_REG(DSI_BTA_TIMING);
156 
157         DUMP_REG(DSI_TIMEOUT_0);
158         DUMP_REG(DSI_TIMEOUT_1);
159         DUMP_REG(DSI_TO_TALLY);
160 
161         DUMP_REG(DSI_PAD_CONTROL_0);
162         DUMP_REG(DSI_PAD_CONTROL_CD);
163         DUMP_REG(DSI_PAD_CD_STATUS);
164         DUMP_REG(DSI_VIDEO_MODE_CONTROL);
165         DUMP_REG(DSI_PAD_CONTROL_1);
166         DUMP_REG(DSI_PAD_CONTROL_2);
167         DUMP_REG(DSI_PAD_CONTROL_3);
168         DUMP_REG(DSI_PAD_CONTROL_4);
169 
170         DUMP_REG(DSI_GANGED_MODE_CONTROL);
171         DUMP_REG(DSI_GANGED_MODE_START);
172         DUMP_REG(DSI_GANGED_MODE_SIZE);
173 
174         DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
175         DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
176 
177         DUMP_REG(DSI_INIT_SEQ_DATA_8);
178         DUMP_REG(DSI_INIT_SEQ_DATA_9);
179         DUMP_REG(DSI_INIT_SEQ_DATA_10);
180         DUMP_REG(DSI_INIT_SEQ_DATA_11);
181         DUMP_REG(DSI_INIT_SEQ_DATA_12);
182         DUMP_REG(DSI_INIT_SEQ_DATA_13);
183         DUMP_REG(DSI_INIT_SEQ_DATA_14);
184         DUMP_REG(DSI_INIT_SEQ_DATA_15);
185 
186 #undef DUMP_REG
187 
188         return 0;
189 }
190 
191 static struct drm_info_list debugfs_files[] = {
192         { "regs", tegra_dsi_show_regs, 0, NULL },
193 };
194 
195 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
196                                   struct drm_minor *minor)
197 {
198         const char *name = dev_name(dsi->dev);
199         unsigned int i;
200         int err;
201 
202         dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
203         if (!dsi->debugfs)
204                 return -ENOMEM;
205 
206         dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
207                                      GFP_KERNEL);
208         if (!dsi->debugfs_files) {
209                 err = -ENOMEM;
210                 goto remove;
211         }
212 
213         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
214                 dsi->debugfs_files[i].data = dsi;
215 
216         err = drm_debugfs_create_files(dsi->debugfs_files,
217                                        ARRAY_SIZE(debugfs_files),
218                                        dsi->debugfs, minor);
219         if (err < 0)
220                 goto free;
221 
222         dsi->minor = minor;
223 
224         return 0;
225 
226 free:
227         kfree(dsi->debugfs_files);
228         dsi->debugfs_files = NULL;
229 remove:
230         debugfs_remove(dsi->debugfs);
231         dsi->debugfs = NULL;
232 
233         return err;
234 }
235 
236 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
237 {
238         drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
239                                  dsi->minor);
240         dsi->minor = NULL;
241 
242         kfree(dsi->debugfs_files);
243         dsi->debugfs_files = NULL;
244 
245         debugfs_remove(dsi->debugfs);
246         dsi->debugfs = NULL;
247 
248         return 0;
249 }
250 
251 #define PKT_ID0(id)     ((((id) & 0x3f) <<  3) | (1 <<  9))
252 #define PKT_LEN0(len)   (((len) & 0x07) <<  0)
253 #define PKT_ID1(id)     ((((id) & 0x3f) << 13) | (1 << 19))
254 #define PKT_LEN1(len)   (((len) & 0x07) << 10)
255 #define PKT_ID2(id)     ((((id) & 0x3f) << 23) | (1 << 29))
256 #define PKT_LEN2(len)   (((len) & 0x07) << 20)
257 
258 #define PKT_LP          (1 << 30)
259 #define NUM_PKT_SEQ     12
260 
261 /* non-burst mode with sync-end */
262 static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = {
263         [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
264                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
265                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
266                PKT_LP,
267         [ 1] = 0,
268         [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
269                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
270                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
271                PKT_LP,
272         [ 3] = 0,
273         [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
274                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
275                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
276                PKT_LP,
277         [ 5] = 0,
278         [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
279                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
280                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
281         [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
282                PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
283                PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
284         [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
285                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
286                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
287                PKT_LP,
288         [ 9] = 0,
289         [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
290                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
291                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
292         [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
293                PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
294                PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
295 };
296 
297 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
298 {
299         struct mipi_dphy_timing timing;
300         unsigned long value, period;
301         long rate;
302         int err;
303 
304         rate = clk_get_rate(dsi->clk);
305         if (rate < 0)
306                 return rate;
307 
308         period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
309 
310         err = mipi_dphy_timing_get_default(&timing, period);
311         if (err < 0)
312                 return err;
313 
314         err = mipi_dphy_timing_validate(&timing, period);
315         if (err < 0) {
316                 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
317                 return err;
318         }
319 
320         /*
321          * The D-PHY timing fields below are expressed in byte-clock cycles,
322          * so multiply the period by 8.
323          */
324         period *= 8;
325 
326         value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
327                 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
328                 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
329                 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
330         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
331 
332         value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
333                 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
334                 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
335                 DSI_TIMING_FIELD(timing.lpx, period, 1);
336         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
337 
338         value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
339                 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
340                 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
341         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
342 
343         value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
344                 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
345                 DSI_TIMING_FIELD(timing.tago, period, 1);
346         tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
347 
348         return 0;
349 }
350 
351 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
352                                 unsigned int *mulp, unsigned int *divp)
353 {
354         switch (format) {
355         case MIPI_DSI_FMT_RGB666_PACKED:
356         case MIPI_DSI_FMT_RGB888:
357                 *mulp = 3;
358                 *divp = 1;
359                 break;
360 
361         case MIPI_DSI_FMT_RGB565:
362                 *mulp = 2;
363                 *divp = 1;
364                 break;
365 
366         case MIPI_DSI_FMT_RGB666:
367                 *mulp = 9;
368                 *divp = 4;
369                 break;
370 
371         default:
372                 return -EINVAL;
373         }
374 
375         return 0;
376 }
377 
378 static int tegra_output_dsi_enable(struct tegra_output *output)
379 {
380         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
381         struct drm_display_mode *mode = &dc->base.mode;
382         unsigned int hact, hsw, hbp, hfp, i, mul, div;
383         struct tegra_dsi *dsi = to_dsi(output);
384         /* FIXME: don't hardcode this */
385         const u32 *pkt_seq = pkt_seq_vnb_syne;
386         unsigned long value;
387         int err;
388 
389         err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
390         if (err < 0)
391                 return err;
392 
393         err = clk_enable(dsi->clk);
394         if (err < 0)
395                 return err;
396 
397         reset_control_deassert(dsi->rst);
398 
399         value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(dsi->format) |
400                 DSI_CONTROL_LANES(dsi->lanes - 1) |
401                 DSI_CONTROL_SOURCE(dc->pipe);
402         tegra_dsi_writel(dsi, value, DSI_CONTROL);
403 
404         tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
405 
406         value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
407                 DSI_HOST_CONTROL_ECC;
408         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
409 
410         value = tegra_dsi_readl(dsi, DSI_CONTROL);
411         value |= DSI_CONTROL_HS_CLK_CTRL;
412         value &= ~DSI_CONTROL_TX_TRIG(3);
413         value &= ~DSI_CONTROL_DCS_ENABLE;
414         value |= DSI_CONTROL_VIDEO_ENABLE;
415         value &= ~DSI_CONTROL_HOST_ENABLE;
416         tegra_dsi_writel(dsi, value, DSI_CONTROL);
417 
418         err = tegra_dsi_set_phy_timing(dsi);
419         if (err < 0)
420                 return err;
421 
422         for (i = 0; i < NUM_PKT_SEQ; i++)
423                 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
424 
425         /* horizontal active pixels */
426         hact = mode->hdisplay * mul / div;
427 
428         /* horizontal sync width */
429         hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
430         hsw -= 10;
431 
432         /* horizontal back porch */
433         hbp = (mode->htotal - mode->hsync_end) * mul / div;
434         hbp -= 14;
435 
436         /* horizontal front porch */
437         hfp = (mode->hsync_start  - mode->hdisplay) * mul / div;
438         hfp -= 8;
439 
440         tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
441         tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
442         tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
443         tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
444 
445         /* set SOL delay */
446         tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
447 
448         /* enable display controller */
449         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
450         value |= DSI_ENABLE;
451         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
452 
453         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
454         value &= ~DISP_CTRL_MODE_MASK;
455         value |= DISP_CTRL_MODE_C_DISPLAY;
456         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
457 
458         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
459         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
460                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
461         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
462 
463         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
464         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
465 
466         /* enable DSI controller */
467         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468         value |= DSI_POWER_CONTROL_ENABLE;
469         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470 
471         return 0;
472 }
473 
474 static int tegra_output_dsi_disable(struct tegra_output *output)
475 {
476         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
477         struct tegra_dsi *dsi = to_dsi(output);
478         unsigned long value;
479 
480         /* disable DSI controller */
481         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
482         value &= DSI_POWER_CONTROL_ENABLE;
483         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
484 
485         /*
486          * The following accesses registers of the display controller, so make
487          * sure it's only executed when the output is attached to one.
488          */
489         if (dc) {
490                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
491                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
492                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
493                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
494 
495                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
496                 value &= ~DISP_CTRL_MODE_MASK;
497                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
498 
499                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
500                 value &= ~DSI_ENABLE;
501                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
502 
503                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
504                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
505         }
506 
507         clk_disable(dsi->clk);
508 
509         return 0;
510 }
511 
512 static int tegra_output_dsi_setup_clock(struct tegra_output *output,
513                                         struct clk *clk, unsigned long pclk)
514 {
515         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
516         struct drm_display_mode *mode = &dc->base.mode;
517         unsigned int timeout, mul, div, vrefresh;
518         struct tegra_dsi *dsi = to_dsi(output);
519         unsigned long bclk, plld, value;
520         struct clk *base;
521         int err;
522 
523         err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
524         if (err < 0)
525                 return err;
526 
527         vrefresh = drm_mode_vrefresh(mode);
528 
529         pclk = mode->htotal * mode->vtotal * vrefresh;
530         bclk = (pclk * mul) / (div * dsi->lanes);
531         plld = DIV_ROUND_UP(bclk * 8, 1000000);
532         pclk = (plld * 1000000) / 2;
533 
534         err = clk_set_parent(clk, dsi->clk_parent);
535         if (err < 0) {
536                 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
537                 return err;
538         }
539 
540         base = clk_get_parent(dsi->clk_parent);
541 
542         /*
543          * This assumes that the parent clock is pll_d_out0 or pll_d2_out
544          * respectively, each of which divides the base pll_d by 2.
545          */
546         err = clk_set_rate(base, pclk * 2);
547         if (err < 0) {
548                 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
549                         pclk * 2);
550                 return err;
551         }
552 
553         /*
554          * XXX: Move the below somewhere else so that we don't need to have
555          * access to the vrefresh in this function?
556          */
557 
558         /* one frame high-speed transmission timeout */
559         timeout = (bclk / vrefresh) / 512;
560         value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
561         tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
562 
563         /* 2 ms peripheral timeout for panel */
564         timeout = 2 * bclk / 512 * 1000;
565         value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
566         tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
567 
568         value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
569         tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
570 
571         return 0;
572 }
573 
574 static int tegra_output_dsi_check_mode(struct tegra_output *output,
575                                        struct drm_display_mode *mode,
576                                        enum drm_mode_status *status)
577 {
578         /*
579          * FIXME: For now, always assume that the mode is okay.
580          */
581 
582         *status = MODE_OK;
583 
584         return 0;
585 }
586 
587 static const struct tegra_output_ops dsi_ops = {
588         .enable = tegra_output_dsi_enable,
589         .disable = tegra_output_dsi_disable,
590         .setup_clock = tegra_output_dsi_setup_clock,
591         .check_mode = tegra_output_dsi_check_mode,
592 };
593 
594 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
595 {
596         unsigned long value;
597 
598         value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
599         tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
600 
601         return 0;
602 }
603 
604 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
605 {
606         unsigned long value;
607 
608         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
609         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
610         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
611         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
612         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
613 
614         /* start calibration */
615         tegra_dsi_pad_enable(dsi);
616 
617         value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
618                 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
619                 DSI_PAD_OUT_CLK(0x0);
620         tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
621 
622         return tegra_mipi_calibrate(dsi->mipi);
623 }
624 
625 static int tegra_dsi_init(struct host1x_client *client)
626 {
627         struct tegra_drm *tegra = dev_get_drvdata(client->parent);
628         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
629         unsigned long value, i;
630         int err;
631 
632         dsi->output.type = TEGRA_OUTPUT_DSI;
633         dsi->output.dev = client->dev;
634         dsi->output.ops = &dsi_ops;
635 
636         err = tegra_output_init(tegra->drm, &dsi->output);
637         if (err < 0) {
638                 dev_err(client->dev, "output setup failed: %d\n", err);
639                 return err;
640         }
641 
642         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
643                 err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary);
644                 if (err < 0)
645                         dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
646         }
647 
648         /*
649          * enable high-speed mode, checksum generation, ECC generation and
650          * disable raw mode
651          */
652         value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
653         value |= DSI_HOST_CONTROL_ECC | DSI_HOST_CONTROL_CS |
654                  DSI_HOST_CONTROL_HS;
655         value &= ~DSI_HOST_CONTROL_RAW;
656         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
657 
658         tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
659         tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
660 
661         tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
662 
663         for (i = 0; i < 8; i++) {
664                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
665                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
666         }
667 
668         for (i = 0; i < 12; i++)
669                 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
670 
671         tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
672 
673         err = tegra_dsi_pad_calibrate(dsi);
674         if (err < 0) {
675                 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
676                 return err;
677         }
678 
679         tegra_dsi_writel(dsi, DSI_POWER_CONTROL_ENABLE, DSI_POWER_CONTROL);
680         usleep_range(300, 1000);
681 
682         return 0;
683 }
684 
685 static int tegra_dsi_exit(struct host1x_client *client)
686 {
687         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
688         int err;
689 
690         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
691                 err = tegra_dsi_debugfs_exit(dsi);
692                 if (err < 0)
693                         dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
694         }
695 
696         err = tegra_output_disable(&dsi->output);
697         if (err < 0) {
698                 dev_err(client->dev, "output failed to disable: %d\n", err);
699                 return err;
700         }
701 
702         err = tegra_output_exit(&dsi->output);
703         if (err < 0) {
704                 dev_err(client->dev, "output cleanup failed: %d\n", err);
705                 return err;
706         }
707 
708         return 0;
709 }
710 
711 static const struct host1x_client_ops dsi_client_ops = {
712         .init = tegra_dsi_init,
713         .exit = tegra_dsi_exit,
714 };
715 
716 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
717 {
718         struct clk *parent;
719         int err;
720 
721         parent = clk_get_parent(dsi->clk);
722         if (!parent)
723                 return -EINVAL;
724 
725         err = clk_set_parent(parent, dsi->clk_parent);
726         if (err < 0)
727                 return err;
728 
729         return 0;
730 }
731 
732 static void tegra_dsi_initialize(struct tegra_dsi *dsi)
733 {
734         unsigned int i;
735 
736         tegra_dsi_writel(dsi, 0, DSI_POWER_CONTROL);
737 
738         tegra_dsi_writel(dsi, 0, DSI_INT_ENABLE);
739         tegra_dsi_writel(dsi, 0, DSI_INT_STATUS);
740         tegra_dsi_writel(dsi, 0, DSI_INT_MASK);
741 
742         tegra_dsi_writel(dsi, 0, DSI_HOST_CONTROL);
743         tegra_dsi_writel(dsi, 0, DSI_CONTROL);
744 
745         tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
746         tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
747 
748         tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
749 
750         for (i = 0; i < 8; i++) {
751                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
752                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
753         }
754 
755         for (i = 0; i < 12; i++)
756                 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
757 
758         tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
759 
760         for (i = 0; i < 4; i++)
761                 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1 + i);
762 
763         tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_0);
764         tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_1);
765         tegra_dsi_writel(dsi, 0x000000ff, DSI_PHY_TIMING_2);
766         tegra_dsi_writel(dsi, 0x00000000, DSI_BTA_TIMING);
767 
768         tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_0);
769         tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_1);
770         tegra_dsi_writel(dsi, 0, DSI_TO_TALLY);
771 
772         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
773         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_CD);
774         tegra_dsi_writel(dsi, 0, DSI_PAD_CD_STATUS);
775         tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL);
776         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
777         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
778         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
779         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
780 
781         tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
782         tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
783         tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
784 }
785 
786 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
787                                  struct mipi_dsi_device *device)
788 {
789         struct tegra_dsi *dsi = host_to_tegra(host);
790         struct tegra_output *output = &dsi->output;
791 
792         dsi->format = device->format;
793         dsi->lanes = device->lanes;
794 
795         output->panel = of_drm_find_panel(device->dev.of_node);
796         if (output->panel) {
797                 if (output->connector.dev)
798                         drm_helper_hpd_irq_event(output->connector.dev);
799         }
800 
801         return 0;
802 }
803 
804 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
805                                  struct mipi_dsi_device *device)
806 {
807         struct tegra_dsi *dsi = host_to_tegra(host);
808         struct tegra_output *output = &dsi->output;
809 
810         if (output->panel && &device->dev == output->panel->dev) {
811                 if (output->connector.dev)
812                         drm_helper_hpd_irq_event(output->connector.dev);
813 
814                 output->panel = NULL;
815         }
816 
817         return 0;
818 }
819 
820 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
821         .attach = tegra_dsi_host_attach,
822         .detach = tegra_dsi_host_detach,
823 };
824 
825 static int tegra_dsi_probe(struct platform_device *pdev)
826 {
827         struct tegra_dsi *dsi;
828         struct resource *regs;
829         int err;
830 
831         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
832         if (!dsi)
833                 return -ENOMEM;
834 
835         dsi->output.dev = dsi->dev = &pdev->dev;
836 
837         err = tegra_output_probe(&dsi->output);
838         if (err < 0)
839                 return err;
840 
841         /*
842          * Assume these values by default. When a DSI peripheral driver
843          * attaches to the DSI host, the parameters will be taken from
844          * the attached device.
845          */
846         dsi->format = MIPI_DSI_FMT_RGB888;
847         dsi->lanes = 4;
848 
849         dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
850         if (IS_ERR(dsi->rst))
851                 return PTR_ERR(dsi->rst);
852 
853         dsi->clk = devm_clk_get(&pdev->dev, NULL);
854         if (IS_ERR(dsi->clk)) {
855                 dev_err(&pdev->dev, "cannot get DSI clock\n");
856                 return PTR_ERR(dsi->clk);
857         }
858 
859         err = clk_prepare_enable(dsi->clk);
860         if (err < 0) {
861                 dev_err(&pdev->dev, "cannot enable DSI clock\n");
862                 return err;
863         }
864 
865         dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
866         if (IS_ERR(dsi->clk_lp)) {
867                 dev_err(&pdev->dev, "cannot get low-power clock\n");
868                 return PTR_ERR(dsi->clk_lp);
869         }
870 
871         err = clk_prepare_enable(dsi->clk_lp);
872         if (err < 0) {
873                 dev_err(&pdev->dev, "cannot enable low-power clock\n");
874                 return err;
875         }
876 
877         dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
878         if (IS_ERR(dsi->clk_parent)) {
879                 dev_err(&pdev->dev, "cannot get parent clock\n");
880                 return PTR_ERR(dsi->clk_parent);
881         }
882 
883         err = clk_prepare_enable(dsi->clk_parent);
884         if (err < 0) {
885                 dev_err(&pdev->dev, "cannot enable parent clock\n");
886                 return err;
887         }
888 
889         err = tegra_dsi_setup_clocks(dsi);
890         if (err < 0) {
891                 dev_err(&pdev->dev, "cannot setup clocks\n");
892                 return err;
893         }
894 
895         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
896         dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
897         if (IS_ERR(dsi->regs))
898                 return PTR_ERR(dsi->regs);
899 
900         tegra_dsi_initialize(dsi);
901 
902         dsi->mipi = tegra_mipi_request(&pdev->dev);
903         if (IS_ERR(dsi->mipi))
904                 return PTR_ERR(dsi->mipi);
905 
906         dsi->host.ops = &tegra_dsi_host_ops;
907         dsi->host.dev = &pdev->dev;
908 
909         err = mipi_dsi_host_register(&dsi->host);
910         if (err < 0) {
911                 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
912                 return err;
913         }
914 
915         INIT_LIST_HEAD(&dsi->client.list);
916         dsi->client.ops = &dsi_client_ops;
917         dsi->client.dev = &pdev->dev;
918 
919         err = host1x_client_register(&dsi->client);
920         if (err < 0) {
921                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
922                         err);
923                 return err;
924         }
925 
926         platform_set_drvdata(pdev, dsi);
927 
928         return 0;
929 }
930 
931 static int tegra_dsi_remove(struct platform_device *pdev)
932 {
933         struct tegra_dsi *dsi = platform_get_drvdata(pdev);
934         int err;
935 
936         err = host1x_client_unregister(&dsi->client);
937         if (err < 0) {
938                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
939                         err);
940                 return err;
941         }
942 
943         mipi_dsi_host_unregister(&dsi->host);
944         tegra_mipi_free(dsi->mipi);
945 
946         clk_disable_unprepare(dsi->clk_parent);
947         clk_disable_unprepare(dsi->clk_lp);
948         clk_disable_unprepare(dsi->clk);
949 
950         err = tegra_output_remove(&dsi->output);
951         if (err < 0) {
952                 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
953                 return err;
954         }
955 
956         return 0;
957 }
958 
959 static const struct of_device_id tegra_dsi_of_match[] = {
960         { .compatible = "nvidia,tegra114-dsi", },
961         { },
962 };
963 
964 struct platform_driver tegra_dsi_driver = {
965         .driver = {
966                 .name = "tegra-dsi",
967                 .of_match_table = tegra_dsi_of_match,
968         },
969         .probe = tegra_dsi_probe,
970         .remove = tegra_dsi_remove,
971 };
972 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us