Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/gpu/drm/tegra/dsi.c

  1 /*
  2  * Copyright (C) 2013 NVIDIA Corporation
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  */
  8 
  9 #include <linux/clk.h>
 10 #include <linux/debugfs.h>
 11 #include <linux/host1x.h>
 12 #include <linux/module.h>
 13 #include <linux/of.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/reset.h>
 16 
 17 #include <linux/regulator/consumer.h>
 18 
 19 #include <drm/drm_mipi_dsi.h>
 20 #include <drm/drm_panel.h>
 21 
 22 #include <video/mipi_display.h>
 23 
 24 #include "dc.h"
 25 #include "drm.h"
 26 #include "dsi.h"
 27 #include "mipi-phy.h"
 28 
 29 #define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
 30 #define DSI_HOST_FIFO_DEPTH 64
 31 
 32 struct tegra_dsi {
 33         struct host1x_client client;
 34         struct tegra_output output;
 35         struct device *dev;
 36 
 37         void __iomem *regs;
 38 
 39         struct reset_control *rst;
 40         struct clk *clk_parent;
 41         struct clk *clk_lp;
 42         struct clk *clk;
 43 
 44         struct drm_info_list *debugfs_files;
 45         struct drm_minor *minor;
 46         struct dentry *debugfs;
 47 
 48         unsigned long flags;
 49         enum mipi_dsi_pixel_format format;
 50         unsigned int lanes;
 51 
 52         struct tegra_mipi_device *mipi;
 53         struct mipi_dsi_host host;
 54 
 55         struct regulator *vdd;
 56         bool enabled;
 57 };
 58 
 59 static inline struct tegra_dsi *
 60 host1x_client_to_dsi(struct host1x_client *client)
 61 {
 62         return container_of(client, struct tegra_dsi, client);
 63 }
 64 
 65 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
 66 {
 67         return container_of(host, struct tegra_dsi, host);
 68 }
 69 
 70 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
 71 {
 72         return container_of(output, struct tegra_dsi, output);
 73 }
 74 
 75 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
 76                                             unsigned long reg)
 77 {
 78         return readl(dsi->regs + (reg << 2));
 79 }
 80 
 81 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
 82                                     unsigned long reg)
 83 {
 84         writel(value, dsi->regs + (reg << 2));
 85 }
 86 
 87 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
 88 {
 89         struct drm_info_node *node = s->private;
 90         struct tegra_dsi *dsi = node->info_ent->data;
 91 
 92 #define DUMP_REG(name)                                          \
 93         seq_printf(s, "%-32s %#05x %08lx\n", #name, name,       \
 94                    tegra_dsi_readl(dsi, name))
 95 
 96         DUMP_REG(DSI_INCR_SYNCPT);
 97         DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
 98         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
 99         DUMP_REG(DSI_CTXSW);
100         DUMP_REG(DSI_RD_DATA);
101         DUMP_REG(DSI_WR_DATA);
102         DUMP_REG(DSI_POWER_CONTROL);
103         DUMP_REG(DSI_INT_ENABLE);
104         DUMP_REG(DSI_INT_STATUS);
105         DUMP_REG(DSI_INT_MASK);
106         DUMP_REG(DSI_HOST_CONTROL);
107         DUMP_REG(DSI_CONTROL);
108         DUMP_REG(DSI_SOL_DELAY);
109         DUMP_REG(DSI_MAX_THRESHOLD);
110         DUMP_REG(DSI_TRIGGER);
111         DUMP_REG(DSI_TX_CRC);
112         DUMP_REG(DSI_STATUS);
113 
114         DUMP_REG(DSI_INIT_SEQ_CONTROL);
115         DUMP_REG(DSI_INIT_SEQ_DATA_0);
116         DUMP_REG(DSI_INIT_SEQ_DATA_1);
117         DUMP_REG(DSI_INIT_SEQ_DATA_2);
118         DUMP_REG(DSI_INIT_SEQ_DATA_3);
119         DUMP_REG(DSI_INIT_SEQ_DATA_4);
120         DUMP_REG(DSI_INIT_SEQ_DATA_5);
121         DUMP_REG(DSI_INIT_SEQ_DATA_6);
122         DUMP_REG(DSI_INIT_SEQ_DATA_7);
123 
124         DUMP_REG(DSI_PKT_SEQ_0_LO);
125         DUMP_REG(DSI_PKT_SEQ_0_HI);
126         DUMP_REG(DSI_PKT_SEQ_1_LO);
127         DUMP_REG(DSI_PKT_SEQ_1_HI);
128         DUMP_REG(DSI_PKT_SEQ_2_LO);
129         DUMP_REG(DSI_PKT_SEQ_2_HI);
130         DUMP_REG(DSI_PKT_SEQ_3_LO);
131         DUMP_REG(DSI_PKT_SEQ_3_HI);
132         DUMP_REG(DSI_PKT_SEQ_4_LO);
133         DUMP_REG(DSI_PKT_SEQ_4_HI);
134         DUMP_REG(DSI_PKT_SEQ_5_LO);
135         DUMP_REG(DSI_PKT_SEQ_5_HI);
136 
137         DUMP_REG(DSI_DCS_CMDS);
138 
139         DUMP_REG(DSI_PKT_LEN_0_1);
140         DUMP_REG(DSI_PKT_LEN_2_3);
141         DUMP_REG(DSI_PKT_LEN_4_5);
142         DUMP_REG(DSI_PKT_LEN_6_7);
143 
144         DUMP_REG(DSI_PHY_TIMING_0);
145         DUMP_REG(DSI_PHY_TIMING_1);
146         DUMP_REG(DSI_PHY_TIMING_2);
147         DUMP_REG(DSI_BTA_TIMING);
148 
149         DUMP_REG(DSI_TIMEOUT_0);
150         DUMP_REG(DSI_TIMEOUT_1);
151         DUMP_REG(DSI_TO_TALLY);
152 
153         DUMP_REG(DSI_PAD_CONTROL_0);
154         DUMP_REG(DSI_PAD_CONTROL_CD);
155         DUMP_REG(DSI_PAD_CD_STATUS);
156         DUMP_REG(DSI_VIDEO_MODE_CONTROL);
157         DUMP_REG(DSI_PAD_CONTROL_1);
158         DUMP_REG(DSI_PAD_CONTROL_2);
159         DUMP_REG(DSI_PAD_CONTROL_3);
160         DUMP_REG(DSI_PAD_CONTROL_4);
161 
162         DUMP_REG(DSI_GANGED_MODE_CONTROL);
163         DUMP_REG(DSI_GANGED_MODE_START);
164         DUMP_REG(DSI_GANGED_MODE_SIZE);
165 
166         DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
167         DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
168 
169         DUMP_REG(DSI_INIT_SEQ_DATA_8);
170         DUMP_REG(DSI_INIT_SEQ_DATA_9);
171         DUMP_REG(DSI_INIT_SEQ_DATA_10);
172         DUMP_REG(DSI_INIT_SEQ_DATA_11);
173         DUMP_REG(DSI_INIT_SEQ_DATA_12);
174         DUMP_REG(DSI_INIT_SEQ_DATA_13);
175         DUMP_REG(DSI_INIT_SEQ_DATA_14);
176         DUMP_REG(DSI_INIT_SEQ_DATA_15);
177 
178 #undef DUMP_REG
179 
180         return 0;
181 }
182 
183 static struct drm_info_list debugfs_files[] = {
184         { "regs", tegra_dsi_show_regs, 0, NULL },
185 };
186 
187 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
188                                   struct drm_minor *minor)
189 {
190         const char *name = dev_name(dsi->dev);
191         unsigned int i;
192         int err;
193 
194         dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
195         if (!dsi->debugfs)
196                 return -ENOMEM;
197 
198         dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
199                                      GFP_KERNEL);
200         if (!dsi->debugfs_files) {
201                 err = -ENOMEM;
202                 goto remove;
203         }
204 
205         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
206                 dsi->debugfs_files[i].data = dsi;
207 
208         err = drm_debugfs_create_files(dsi->debugfs_files,
209                                        ARRAY_SIZE(debugfs_files),
210                                        dsi->debugfs, minor);
211         if (err < 0)
212                 goto free;
213 
214         dsi->minor = minor;
215 
216         return 0;
217 
218 free:
219         kfree(dsi->debugfs_files);
220         dsi->debugfs_files = NULL;
221 remove:
222         debugfs_remove(dsi->debugfs);
223         dsi->debugfs = NULL;
224 
225         return err;
226 }
227 
228 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
229 {
230         drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
231                                  dsi->minor);
232         dsi->minor = NULL;
233 
234         kfree(dsi->debugfs_files);
235         dsi->debugfs_files = NULL;
236 
237         debugfs_remove(dsi->debugfs);
238         dsi->debugfs = NULL;
239 
240         return 0;
241 }
242 
243 #define PKT_ID0(id)     ((((id) & 0x3f) <<  3) | (1 <<  9))
244 #define PKT_LEN0(len)   (((len) & 0x07) <<  0)
245 #define PKT_ID1(id)     ((((id) & 0x3f) << 13) | (1 << 19))
246 #define PKT_LEN1(len)   (((len) & 0x07) << 10)
247 #define PKT_ID2(id)     ((((id) & 0x3f) << 23) | (1 << 29))
248 #define PKT_LEN2(len)   (((len) & 0x07) << 20)
249 
250 #define PKT_LP          (1 << 30)
251 #define NUM_PKT_SEQ     12
252 
253 /*
254  * non-burst mode with sync pulses
255  */
256 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
257         [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
258                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
259                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
260                PKT_LP,
261         [ 1] = 0,
262         [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
263                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
264                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
265                PKT_LP,
266         [ 3] = 0,
267         [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
268                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
269                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
270                PKT_LP,
271         [ 5] = 0,
272         [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
273                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
274                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
275         [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
276                PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
277                PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
278         [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
279                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
280                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
281                PKT_LP,
282         [ 9] = 0,
283         [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
284                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
285                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
286         [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
287                PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
288                PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
289 };
290 
291 /*
292  * non-burst mode with sync events
293  */
294 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
295         [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
296                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
297                PKT_LP,
298         [ 1] = 0,
299         [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
300                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
301                PKT_LP,
302         [ 3] = 0,
303         [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
304                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
305                PKT_LP,
306         [ 5] = 0,
307         [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
309                PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
310         [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
311         [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
312                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
313                PKT_LP,
314         [ 9] = 0,
315         [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
316                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
317                PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
318         [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
319 };
320 
321 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
322 {
323         struct mipi_dphy_timing timing;
324         unsigned long value, period;
325         long rate;
326         int err;
327 
328         rate = clk_get_rate(dsi->clk);
329         if (rate < 0)
330                 return rate;
331 
332         period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
333 
334         err = mipi_dphy_timing_get_default(&timing, period);
335         if (err < 0)
336                 return err;
337 
338         err = mipi_dphy_timing_validate(&timing, period);
339         if (err < 0) {
340                 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
341                 return err;
342         }
343 
344         /*
345          * The D-PHY timing fields below are expressed in byte-clock cycles,
346          * so multiply the period by 8.
347          */
348         period *= 8;
349 
350         value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
351                 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
352                 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
353                 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
354         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
355 
356         value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
357                 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
358                 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
359                 DSI_TIMING_FIELD(timing.lpx, period, 1);
360         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
361 
362         value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
363                 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
364                 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
365         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
366 
367         value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
368                 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
369                 DSI_TIMING_FIELD(timing.tago, period, 1);
370         tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
371 
372         return 0;
373 }
374 
375 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
376                                 unsigned int *mulp, unsigned int *divp)
377 {
378         switch (format) {
379         case MIPI_DSI_FMT_RGB666_PACKED:
380         case MIPI_DSI_FMT_RGB888:
381                 *mulp = 3;
382                 *divp = 1;
383                 break;
384 
385         case MIPI_DSI_FMT_RGB565:
386                 *mulp = 2;
387                 *divp = 1;
388                 break;
389 
390         case MIPI_DSI_FMT_RGB666:
391                 *mulp = 9;
392                 *divp = 4;
393                 break;
394 
395         default:
396                 return -EINVAL;
397         }
398 
399         return 0;
400 }
401 
402 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
403                                 enum tegra_dsi_format *fmt)
404 {
405         switch (format) {
406         case MIPI_DSI_FMT_RGB888:
407                 *fmt = TEGRA_DSI_FORMAT_24P;
408                 break;
409 
410         case MIPI_DSI_FMT_RGB666:
411                 *fmt = TEGRA_DSI_FORMAT_18NP;
412                 break;
413 
414         case MIPI_DSI_FMT_RGB666_PACKED:
415                 *fmt = TEGRA_DSI_FORMAT_18P;
416                 break;
417 
418         case MIPI_DSI_FMT_RGB565:
419                 *fmt = TEGRA_DSI_FORMAT_16P;
420                 break;
421 
422         default:
423                 return -EINVAL;
424         }
425 
426         return 0;
427 }
428 
429 static int tegra_output_dsi_enable(struct tegra_output *output)
430 {
431         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
432         struct drm_display_mode *mode = &dc->base.mode;
433         unsigned int hact, hsw, hbp, hfp, i, mul, div;
434         struct tegra_dsi *dsi = to_dsi(output);
435         enum tegra_dsi_format format;
436         unsigned long value;
437         const u32 *pkt_seq;
438         int err;
439 
440         if (dsi->enabled)
441                 return 0;
442 
443         if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
444                 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
445                 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
446         } else {
447                 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
448                 pkt_seq = pkt_seq_video_non_burst_sync_events;
449         }
450 
451         err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
452         if (err < 0)
453                 return err;
454 
455         err = tegra_dsi_get_format(dsi->format, &format);
456         if (err < 0)
457                 return err;
458 
459         err = clk_enable(dsi->clk);
460         if (err < 0)
461                 return err;
462 
463         reset_control_deassert(dsi->rst);
464 
465         value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
466                 DSI_CONTROL_LANES(dsi->lanes - 1) |
467                 DSI_CONTROL_SOURCE(dc->pipe);
468         tegra_dsi_writel(dsi, value, DSI_CONTROL);
469 
470         tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
471 
472         value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
473                 DSI_HOST_CONTROL_ECC;
474         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
475 
476         value = tegra_dsi_readl(dsi, DSI_CONTROL);
477         value |= DSI_CONTROL_HS_CLK_CTRL;
478         value &= ~DSI_CONTROL_TX_TRIG(3);
479         value &= ~DSI_CONTROL_DCS_ENABLE;
480         value |= DSI_CONTROL_VIDEO_ENABLE;
481         value &= ~DSI_CONTROL_HOST_ENABLE;
482         tegra_dsi_writel(dsi, value, DSI_CONTROL);
483 
484         err = tegra_dsi_set_phy_timing(dsi);
485         if (err < 0)
486                 return err;
487 
488         for (i = 0; i < NUM_PKT_SEQ; i++)
489                 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
490 
491         /* horizontal active pixels */
492         hact = mode->hdisplay * mul / div;
493 
494         /* horizontal sync width */
495         hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
496         hsw -= 10;
497 
498         /* horizontal back porch */
499         hbp = (mode->htotal - mode->hsync_end) * mul / div;
500         hbp -= 14;
501 
502         /* horizontal front porch */
503         hfp = (mode->hsync_start  - mode->hdisplay) * mul / div;
504         hfp -= 8;
505 
506         tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
507         tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
508         tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
509         tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
510 
511         /* set SOL delay */
512         tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
513 
514         /* enable display controller */
515         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
516         value |= DSI_ENABLE;
517         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
518 
519         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
520         value &= ~DISP_CTRL_MODE_MASK;
521         value |= DISP_CTRL_MODE_C_DISPLAY;
522         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
523 
524         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
525         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
526                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
527         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
528 
529         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
530         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
531 
532         /* enable DSI controller */
533         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
534         value |= DSI_POWER_CONTROL_ENABLE;
535         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
536 
537         dsi->enabled = true;
538 
539         return 0;
540 }
541 
542 static int tegra_output_dsi_disable(struct tegra_output *output)
543 {
544         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
545         struct tegra_dsi *dsi = to_dsi(output);
546         unsigned long value;
547 
548         if (!dsi->enabled)
549                 return 0;
550 
551         /* disable DSI controller */
552         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
553         value &= ~DSI_POWER_CONTROL_ENABLE;
554         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
555 
556         /*
557          * The following accesses registers of the display controller, so make
558          * sure it's only executed when the output is attached to one.
559          */
560         if (dc) {
561                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
562                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
563                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
564                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
565 
566                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
567                 value &= ~DISP_CTRL_MODE_MASK;
568                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
569 
570                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
571                 value &= ~DSI_ENABLE;
572                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
573 
574                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
575                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
576         }
577 
578         clk_disable(dsi->clk);
579 
580         dsi->enabled = false;
581 
582         return 0;
583 }
584 
585 static int tegra_output_dsi_setup_clock(struct tegra_output *output,
586                                         struct clk *clk, unsigned long pclk,
587                                         unsigned int *divp)
588 {
589         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
590         struct drm_display_mode *mode = &dc->base.mode;
591         unsigned int timeout, mul, div, vrefresh;
592         struct tegra_dsi *dsi = to_dsi(output);
593         unsigned long bclk, plld, value;
594         int err;
595 
596         err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
597         if (err < 0)
598                 return err;
599 
600         DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, dsi->lanes);
601         vrefresh = drm_mode_vrefresh(mode);
602         DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
603 
604         /* compute byte clock */
605         bclk = (pclk * mul) / (div * dsi->lanes);
606 
607         /*
608          * Compute bit clock and round up to the next MHz.
609          */
610         plld = DIV_ROUND_UP(bclk * 8, 1000000) * 1000000;
611 
612         /*
613          * We divide the frequency by two here, but we make up for that by
614          * setting the shift clock divider (further below) to half of the
615          * correct value.
616          */
617         plld /= 2;
618 
619         err = clk_set_parent(clk, dsi->clk_parent);
620         if (err < 0) {
621                 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
622                 return err;
623         }
624 
625         err = clk_set_rate(dsi->clk_parent, plld);
626         if (err < 0) {
627                 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
628                         plld);
629                 return err;
630         }
631 
632         /*
633          * Derive pixel clock from bit clock using the shift clock divider.
634          * Note that this is only half of what we would expect, but we need
635          * that to make up for the fact that we divided the bit clock by a
636          * factor of two above.
637          *
638          * It's not clear exactly why this is necessary, but the display is
639          * not working properly otherwise. Perhaps the PLLs cannot generate
640          * frequencies sufficiently high.
641          */
642         *divp = ((8 * mul) / (div * dsi->lanes)) - 2;
643 
644         /*
645          * XXX: Move the below somewhere else so that we don't need to have
646          * access to the vrefresh in this function?
647          */
648 
649         /* one frame high-speed transmission timeout */
650         timeout = (bclk / vrefresh) / 512;
651         value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
652         tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
653 
654         /* 2 ms peripheral timeout for panel */
655         timeout = 2 * bclk / 512 * 1000;
656         value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
657         tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
658 
659         value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
660         tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
661 
662         return 0;
663 }
664 
665 static int tegra_output_dsi_check_mode(struct tegra_output *output,
666                                        struct drm_display_mode *mode,
667                                        enum drm_mode_status *status)
668 {
669         /*
670          * FIXME: For now, always assume that the mode is okay.
671          */
672 
673         *status = MODE_OK;
674 
675         return 0;
676 }
677 
678 static const struct tegra_output_ops dsi_ops = {
679         .enable = tegra_output_dsi_enable,
680         .disable = tegra_output_dsi_disable,
681         .setup_clock = tegra_output_dsi_setup_clock,
682         .check_mode = tegra_output_dsi_check_mode,
683 };
684 
685 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
686 {
687         unsigned long value;
688 
689         value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
690         tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
691 
692         return 0;
693 }
694 
695 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
696 {
697         unsigned long value;
698 
699         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
700         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
701         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
702         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
703         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
704 
705         /* start calibration */
706         tegra_dsi_pad_enable(dsi);
707 
708         value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
709                 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
710                 DSI_PAD_OUT_CLK(0x0);
711         tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
712 
713         return tegra_mipi_calibrate(dsi->mipi);
714 }
715 
716 static int tegra_dsi_init(struct host1x_client *client)
717 {
718         struct drm_device *drm = dev_get_drvdata(client->parent);
719         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
720         int err;
721 
722         dsi->output.type = TEGRA_OUTPUT_DSI;
723         dsi->output.dev = client->dev;
724         dsi->output.ops = &dsi_ops;
725 
726         err = tegra_output_init(drm, &dsi->output);
727         if (err < 0) {
728                 dev_err(client->dev, "output setup failed: %d\n", err);
729                 return err;
730         }
731 
732         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
733                 err = tegra_dsi_debugfs_init(dsi, drm->primary);
734                 if (err < 0)
735                         dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
736         }
737 
738         err = tegra_dsi_pad_calibrate(dsi);
739         if (err < 0) {
740                 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
741                 return err;
742         }
743 
744         return 0;
745 }
746 
747 static int tegra_dsi_exit(struct host1x_client *client)
748 {
749         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
750         int err;
751 
752         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
753                 err = tegra_dsi_debugfs_exit(dsi);
754                 if (err < 0)
755                         dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
756         }
757 
758         err = tegra_output_disable(&dsi->output);
759         if (err < 0) {
760                 dev_err(client->dev, "output failed to disable: %d\n", err);
761                 return err;
762         }
763 
764         err = tegra_output_exit(&dsi->output);
765         if (err < 0) {
766                 dev_err(client->dev, "output cleanup failed: %d\n", err);
767                 return err;
768         }
769 
770         return 0;
771 }
772 
773 static const struct host1x_client_ops dsi_client_ops = {
774         .init = tegra_dsi_init,
775         .exit = tegra_dsi_exit,
776 };
777 
778 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
779 {
780         struct clk *parent;
781         int err;
782 
783         parent = clk_get_parent(dsi->clk);
784         if (!parent)
785                 return -EINVAL;
786 
787         err = clk_set_parent(parent, dsi->clk_parent);
788         if (err < 0)
789                 return err;
790 
791         return 0;
792 }
793 
794 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
795                                  struct mipi_dsi_device *device)
796 {
797         struct tegra_dsi *dsi = host_to_tegra(host);
798         struct tegra_output *output = &dsi->output;
799 
800         dsi->flags = device->mode_flags;
801         dsi->format = device->format;
802         dsi->lanes = device->lanes;
803 
804         output->panel = of_drm_find_panel(device->dev.of_node);
805         if (output->panel) {
806                 if (output->connector.dev)
807                         drm_helper_hpd_irq_event(output->connector.dev);
808         }
809 
810         return 0;
811 }
812 
813 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
814                                  struct mipi_dsi_device *device)
815 {
816         struct tegra_dsi *dsi = host_to_tegra(host);
817         struct tegra_output *output = &dsi->output;
818 
819         if (output->panel && &device->dev == output->panel->dev) {
820                 if (output->connector.dev)
821                         drm_helper_hpd_irq_event(output->connector.dev);
822 
823                 output->panel = NULL;
824         }
825 
826         return 0;
827 }
828 
829 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
830         .attach = tegra_dsi_host_attach,
831         .detach = tegra_dsi_host_detach,
832 };
833 
834 static int tegra_dsi_probe(struct platform_device *pdev)
835 {
836         struct tegra_dsi *dsi;
837         struct resource *regs;
838         int err;
839 
840         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
841         if (!dsi)
842                 return -ENOMEM;
843 
844         dsi->output.dev = dsi->dev = &pdev->dev;
845 
846         err = tegra_output_probe(&dsi->output);
847         if (err < 0)
848                 return err;
849 
850         /*
851          * Assume these values by default. When a DSI peripheral driver
852          * attaches to the DSI host, the parameters will be taken from
853          * the attached device.
854          */
855         dsi->flags = MIPI_DSI_MODE_VIDEO;
856         dsi->format = MIPI_DSI_FMT_RGB888;
857         dsi->lanes = 4;
858 
859         dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
860         if (IS_ERR(dsi->rst))
861                 return PTR_ERR(dsi->rst);
862 
863         dsi->clk = devm_clk_get(&pdev->dev, NULL);
864         if (IS_ERR(dsi->clk)) {
865                 dev_err(&pdev->dev, "cannot get DSI clock\n");
866                 return PTR_ERR(dsi->clk);
867         }
868 
869         err = clk_prepare_enable(dsi->clk);
870         if (err < 0) {
871                 dev_err(&pdev->dev, "cannot enable DSI clock\n");
872                 return err;
873         }
874 
875         dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
876         if (IS_ERR(dsi->clk_lp)) {
877                 dev_err(&pdev->dev, "cannot get low-power clock\n");
878                 return PTR_ERR(dsi->clk_lp);
879         }
880 
881         err = clk_prepare_enable(dsi->clk_lp);
882         if (err < 0) {
883                 dev_err(&pdev->dev, "cannot enable low-power clock\n");
884                 return err;
885         }
886 
887         dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
888         if (IS_ERR(dsi->clk_parent)) {
889                 dev_err(&pdev->dev, "cannot get parent clock\n");
890                 return PTR_ERR(dsi->clk_parent);
891         }
892 
893         err = clk_prepare_enable(dsi->clk_parent);
894         if (err < 0) {
895                 dev_err(&pdev->dev, "cannot enable parent clock\n");
896                 return err;
897         }
898 
899         dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
900         if (IS_ERR(dsi->vdd)) {
901                 dev_err(&pdev->dev, "cannot get VDD supply\n");
902                 return PTR_ERR(dsi->vdd);
903         }
904 
905         err = regulator_enable(dsi->vdd);
906         if (err < 0) {
907                 dev_err(&pdev->dev, "cannot enable VDD supply\n");
908                 return err;
909         }
910 
911         err = tegra_dsi_setup_clocks(dsi);
912         if (err < 0) {
913                 dev_err(&pdev->dev, "cannot setup clocks\n");
914                 return err;
915         }
916 
917         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918         dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
919         if (IS_ERR(dsi->regs))
920                 return PTR_ERR(dsi->regs);
921 
922         dsi->mipi = tegra_mipi_request(&pdev->dev);
923         if (IS_ERR(dsi->mipi))
924                 return PTR_ERR(dsi->mipi);
925 
926         dsi->host.ops = &tegra_dsi_host_ops;
927         dsi->host.dev = &pdev->dev;
928 
929         err = mipi_dsi_host_register(&dsi->host);
930         if (err < 0) {
931                 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
932                 return err;
933         }
934 
935         INIT_LIST_HEAD(&dsi->client.list);
936         dsi->client.ops = &dsi_client_ops;
937         dsi->client.dev = &pdev->dev;
938 
939         err = host1x_client_register(&dsi->client);
940         if (err < 0) {
941                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
942                         err);
943                 return err;
944         }
945 
946         platform_set_drvdata(pdev, dsi);
947 
948         return 0;
949 }
950 
951 static int tegra_dsi_remove(struct platform_device *pdev)
952 {
953         struct tegra_dsi *dsi = platform_get_drvdata(pdev);
954         int err;
955 
956         err = host1x_client_unregister(&dsi->client);
957         if (err < 0) {
958                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
959                         err);
960                 return err;
961         }
962 
963         mipi_dsi_host_unregister(&dsi->host);
964         tegra_mipi_free(dsi->mipi);
965 
966         regulator_disable(dsi->vdd);
967         clk_disable_unprepare(dsi->clk_parent);
968         clk_disable_unprepare(dsi->clk_lp);
969         clk_disable_unprepare(dsi->clk);
970         reset_control_assert(dsi->rst);
971 
972         err = tegra_output_remove(&dsi->output);
973         if (err < 0) {
974                 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
975                 return err;
976         }
977 
978         return 0;
979 }
980 
981 static const struct of_device_id tegra_dsi_of_match[] = {
982         { .compatible = "nvidia,tegra114-dsi", },
983         { },
984 };
985 
986 struct platform_driver tegra_dsi_driver = {
987         .driver = {
988                 .name = "tegra-dsi",
989                 .of_match_table = tegra_dsi_of_match,
990         },
991         .probe = tegra_dsi_probe,
992         .remove = tegra_dsi_remove,
993 };
994 

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