Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/gpu/drm/tegra/dsi.c

  1 /*
  2  * Copyright (C) 2013 NVIDIA Corporation
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  */
  8 
  9 #include <linux/clk.h>
 10 #include <linux/debugfs.h>
 11 #include <linux/host1x.h>
 12 #include <linux/module.h>
 13 #include <linux/of.h>
 14 #include <linux/of_platform.h>
 15 #include <linux/platform_device.h>
 16 #include <linux/reset.h>
 17 
 18 #include <linux/regulator/consumer.h>
 19 
 20 #include <drm/drm_mipi_dsi.h>
 21 #include <drm/drm_panel.h>
 22 
 23 #include <video/mipi_display.h>
 24 
 25 #include "dc.h"
 26 #include "drm.h"
 27 #include "dsi.h"
 28 #include "mipi-phy.h"
 29 
 30 struct tegra_dsi {
 31         struct host1x_client client;
 32         struct tegra_output output;
 33         struct device *dev;
 34 
 35         void __iomem *regs;
 36 
 37         struct reset_control *rst;
 38         struct clk *clk_parent;
 39         struct clk *clk_lp;
 40         struct clk *clk;
 41 
 42         struct drm_info_list *debugfs_files;
 43         struct drm_minor *minor;
 44         struct dentry *debugfs;
 45 
 46         unsigned long flags;
 47         enum mipi_dsi_pixel_format format;
 48         unsigned int lanes;
 49 
 50         struct tegra_mipi_device *mipi;
 51         struct mipi_dsi_host host;
 52 
 53         struct regulator *vdd;
 54         bool enabled;
 55 
 56         unsigned int video_fifo_depth;
 57         unsigned int host_fifo_depth;
 58 
 59         /* for ganged-mode support */
 60         struct tegra_dsi *master;
 61         struct tegra_dsi *slave;
 62 };
 63 
 64 static inline struct tegra_dsi *
 65 host1x_client_to_dsi(struct host1x_client *client)
 66 {
 67         return container_of(client, struct tegra_dsi, client);
 68 }
 69 
 70 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
 71 {
 72         return container_of(host, struct tegra_dsi, host);
 73 }
 74 
 75 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
 76 {
 77         return container_of(output, struct tegra_dsi, output);
 78 }
 79 
 80 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
 81                                             unsigned long reg)
 82 {
 83         return readl(dsi->regs + (reg << 2));
 84 }
 85 
 86 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
 87                                     unsigned long reg)
 88 {
 89         writel(value, dsi->regs + (reg << 2));
 90 }
 91 
 92 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
 93 {
 94         struct drm_info_node *node = s->private;
 95         struct tegra_dsi *dsi = node->info_ent->data;
 96 
 97 #define DUMP_REG(name)                                          \
 98         seq_printf(s, "%-32s %#05x %08lx\n", #name, name,       \
 99                    tegra_dsi_readl(dsi, name))
100 
101         DUMP_REG(DSI_INCR_SYNCPT);
102         DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
103         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
104         DUMP_REG(DSI_CTXSW);
105         DUMP_REG(DSI_RD_DATA);
106         DUMP_REG(DSI_WR_DATA);
107         DUMP_REG(DSI_POWER_CONTROL);
108         DUMP_REG(DSI_INT_ENABLE);
109         DUMP_REG(DSI_INT_STATUS);
110         DUMP_REG(DSI_INT_MASK);
111         DUMP_REG(DSI_HOST_CONTROL);
112         DUMP_REG(DSI_CONTROL);
113         DUMP_REG(DSI_SOL_DELAY);
114         DUMP_REG(DSI_MAX_THRESHOLD);
115         DUMP_REG(DSI_TRIGGER);
116         DUMP_REG(DSI_TX_CRC);
117         DUMP_REG(DSI_STATUS);
118 
119         DUMP_REG(DSI_INIT_SEQ_CONTROL);
120         DUMP_REG(DSI_INIT_SEQ_DATA_0);
121         DUMP_REG(DSI_INIT_SEQ_DATA_1);
122         DUMP_REG(DSI_INIT_SEQ_DATA_2);
123         DUMP_REG(DSI_INIT_SEQ_DATA_3);
124         DUMP_REG(DSI_INIT_SEQ_DATA_4);
125         DUMP_REG(DSI_INIT_SEQ_DATA_5);
126         DUMP_REG(DSI_INIT_SEQ_DATA_6);
127         DUMP_REG(DSI_INIT_SEQ_DATA_7);
128 
129         DUMP_REG(DSI_PKT_SEQ_0_LO);
130         DUMP_REG(DSI_PKT_SEQ_0_HI);
131         DUMP_REG(DSI_PKT_SEQ_1_LO);
132         DUMP_REG(DSI_PKT_SEQ_1_HI);
133         DUMP_REG(DSI_PKT_SEQ_2_LO);
134         DUMP_REG(DSI_PKT_SEQ_2_HI);
135         DUMP_REG(DSI_PKT_SEQ_3_LO);
136         DUMP_REG(DSI_PKT_SEQ_3_HI);
137         DUMP_REG(DSI_PKT_SEQ_4_LO);
138         DUMP_REG(DSI_PKT_SEQ_4_HI);
139         DUMP_REG(DSI_PKT_SEQ_5_LO);
140         DUMP_REG(DSI_PKT_SEQ_5_HI);
141 
142         DUMP_REG(DSI_DCS_CMDS);
143 
144         DUMP_REG(DSI_PKT_LEN_0_1);
145         DUMP_REG(DSI_PKT_LEN_2_3);
146         DUMP_REG(DSI_PKT_LEN_4_5);
147         DUMP_REG(DSI_PKT_LEN_6_7);
148 
149         DUMP_REG(DSI_PHY_TIMING_0);
150         DUMP_REG(DSI_PHY_TIMING_1);
151         DUMP_REG(DSI_PHY_TIMING_2);
152         DUMP_REG(DSI_BTA_TIMING);
153 
154         DUMP_REG(DSI_TIMEOUT_0);
155         DUMP_REG(DSI_TIMEOUT_1);
156         DUMP_REG(DSI_TO_TALLY);
157 
158         DUMP_REG(DSI_PAD_CONTROL_0);
159         DUMP_REG(DSI_PAD_CONTROL_CD);
160         DUMP_REG(DSI_PAD_CD_STATUS);
161         DUMP_REG(DSI_VIDEO_MODE_CONTROL);
162         DUMP_REG(DSI_PAD_CONTROL_1);
163         DUMP_REG(DSI_PAD_CONTROL_2);
164         DUMP_REG(DSI_PAD_CONTROL_3);
165         DUMP_REG(DSI_PAD_CONTROL_4);
166 
167         DUMP_REG(DSI_GANGED_MODE_CONTROL);
168         DUMP_REG(DSI_GANGED_MODE_START);
169         DUMP_REG(DSI_GANGED_MODE_SIZE);
170 
171         DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
172         DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
173 
174         DUMP_REG(DSI_INIT_SEQ_DATA_8);
175         DUMP_REG(DSI_INIT_SEQ_DATA_9);
176         DUMP_REG(DSI_INIT_SEQ_DATA_10);
177         DUMP_REG(DSI_INIT_SEQ_DATA_11);
178         DUMP_REG(DSI_INIT_SEQ_DATA_12);
179         DUMP_REG(DSI_INIT_SEQ_DATA_13);
180         DUMP_REG(DSI_INIT_SEQ_DATA_14);
181         DUMP_REG(DSI_INIT_SEQ_DATA_15);
182 
183 #undef DUMP_REG
184 
185         return 0;
186 }
187 
188 static struct drm_info_list debugfs_files[] = {
189         { "regs", tegra_dsi_show_regs, 0, NULL },
190 };
191 
192 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
193                                   struct drm_minor *minor)
194 {
195         const char *name = dev_name(dsi->dev);
196         unsigned int i;
197         int err;
198 
199         dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
200         if (!dsi->debugfs)
201                 return -ENOMEM;
202 
203         dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
204                                      GFP_KERNEL);
205         if (!dsi->debugfs_files) {
206                 err = -ENOMEM;
207                 goto remove;
208         }
209 
210         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
211                 dsi->debugfs_files[i].data = dsi;
212 
213         err = drm_debugfs_create_files(dsi->debugfs_files,
214                                        ARRAY_SIZE(debugfs_files),
215                                        dsi->debugfs, minor);
216         if (err < 0)
217                 goto free;
218 
219         dsi->minor = minor;
220 
221         return 0;
222 
223 free:
224         kfree(dsi->debugfs_files);
225         dsi->debugfs_files = NULL;
226 remove:
227         debugfs_remove(dsi->debugfs);
228         dsi->debugfs = NULL;
229 
230         return err;
231 }
232 
233 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
234 {
235         drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
236                                  dsi->minor);
237         dsi->minor = NULL;
238 
239         kfree(dsi->debugfs_files);
240         dsi->debugfs_files = NULL;
241 
242         debugfs_remove(dsi->debugfs);
243         dsi->debugfs = NULL;
244 
245         return 0;
246 }
247 
248 #define PKT_ID0(id)     ((((id) & 0x3f) <<  3) | (1 <<  9))
249 #define PKT_LEN0(len)   (((len) & 0x07) <<  0)
250 #define PKT_ID1(id)     ((((id) & 0x3f) << 13) | (1 << 19))
251 #define PKT_LEN1(len)   (((len) & 0x07) << 10)
252 #define PKT_ID2(id)     ((((id) & 0x3f) << 23) | (1 << 29))
253 #define PKT_LEN2(len)   (((len) & 0x07) << 20)
254 
255 #define PKT_LP          (1 << 30)
256 #define NUM_PKT_SEQ     12
257 
258 /*
259  * non-burst mode with sync pulses
260  */
261 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
262         [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
263                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
264                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
265                PKT_LP,
266         [ 1] = 0,
267         [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
268                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
269                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
270                PKT_LP,
271         [ 3] = 0,
272         [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
273                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
274                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
275                PKT_LP,
276         [ 5] = 0,
277         [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
278                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
279                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
280         [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
281                PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
282                PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
283         [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
284                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
285                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
286                PKT_LP,
287         [ 9] = 0,
288         [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
289                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
290                PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
291         [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
292                PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
293                PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
294 };
295 
296 /*
297  * non-burst mode with sync events
298  */
299 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
300         [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
301                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
302                PKT_LP,
303         [ 1] = 0,
304         [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
305                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
306                PKT_LP,
307         [ 3] = 0,
308         [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
309                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
310                PKT_LP,
311         [ 5] = 0,
312         [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
313                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
314                PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
315         [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
316         [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
317                PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
318                PKT_LP,
319         [ 9] = 0,
320         [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
321                PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
322                PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
323         [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
324 };
325 
326 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
327         [ 0] = 0,
328         [ 1] = 0,
329         [ 2] = 0,
330         [ 3] = 0,
331         [ 4] = 0,
332         [ 5] = 0,
333         [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
334         [ 7] = 0,
335         [ 8] = 0,
336         [ 9] = 0,
337         [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
338         [11] = 0,
339 };
340 
341 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
342 {
343         struct mipi_dphy_timing timing;
344         unsigned long value, period;
345         long rate;
346         int err;
347 
348         rate = clk_get_rate(dsi->clk);
349         if (rate < 0)
350                 return rate;
351 
352         period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate * 2);
353 
354         err = mipi_dphy_timing_get_default(&timing, period);
355         if (err < 0)
356                 return err;
357 
358         err = mipi_dphy_timing_validate(&timing, period);
359         if (err < 0) {
360                 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
361                 return err;
362         }
363 
364         /*
365          * The D-PHY timing fields below are expressed in byte-clock cycles,
366          * so multiply the period by 8.
367          */
368         period *= 8;
369 
370         value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
371                 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
372                 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
373                 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
374         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
375 
376         value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
377                 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
378                 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
379                 DSI_TIMING_FIELD(timing.lpx, period, 1);
380         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
381 
382         value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
383                 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
384                 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
385         tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
386 
387         value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
388                 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
389                 DSI_TIMING_FIELD(timing.tago, period, 1);
390         tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
391 
392         if (dsi->slave)
393                 return tegra_dsi_set_phy_timing(dsi->slave);
394 
395         return 0;
396 }
397 
398 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
399                                 unsigned int *mulp, unsigned int *divp)
400 {
401         switch (format) {
402         case MIPI_DSI_FMT_RGB666_PACKED:
403         case MIPI_DSI_FMT_RGB888:
404                 *mulp = 3;
405                 *divp = 1;
406                 break;
407 
408         case MIPI_DSI_FMT_RGB565:
409                 *mulp = 2;
410                 *divp = 1;
411                 break;
412 
413         case MIPI_DSI_FMT_RGB666:
414                 *mulp = 9;
415                 *divp = 4;
416                 break;
417 
418         default:
419                 return -EINVAL;
420         }
421 
422         return 0;
423 }
424 
425 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
426                                 enum tegra_dsi_format *fmt)
427 {
428         switch (format) {
429         case MIPI_DSI_FMT_RGB888:
430                 *fmt = TEGRA_DSI_FORMAT_24P;
431                 break;
432 
433         case MIPI_DSI_FMT_RGB666:
434                 *fmt = TEGRA_DSI_FORMAT_18NP;
435                 break;
436 
437         case MIPI_DSI_FMT_RGB666_PACKED:
438                 *fmt = TEGRA_DSI_FORMAT_18P;
439                 break;
440 
441         case MIPI_DSI_FMT_RGB565:
442                 *fmt = TEGRA_DSI_FORMAT_16P;
443                 break;
444 
445         default:
446                 return -EINVAL;
447         }
448 
449         return 0;
450 }
451 
452 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
453                                     unsigned int size)
454 {
455         u32 value;
456 
457         tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
458         tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
459 
460         value = DSI_GANGED_MODE_CONTROL_ENABLE;
461         tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
462 }
463 
464 static void tegra_dsi_enable(struct tegra_dsi *dsi)
465 {
466         u32 value;
467 
468         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
469         value |= DSI_POWER_CONTROL_ENABLE;
470         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
471 
472         if (dsi->slave)
473                 tegra_dsi_enable(dsi->slave);
474 }
475 
476 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
477 {
478         if (dsi->master)
479                 return dsi->master->lanes + dsi->lanes;
480 
481         if (dsi->slave)
482                 return dsi->lanes + dsi->slave->lanes;
483 
484         return dsi->lanes;
485 }
486 
487 static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
488                                const struct drm_display_mode *mode)
489 {
490         unsigned int hact, hsw, hbp, hfp, i, mul, div;
491         enum tegra_dsi_format format;
492         const u32 *pkt_seq;
493         u32 value;
494         int err;
495 
496         if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
497                 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
498                 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
499         } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
500                 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
501                 pkt_seq = pkt_seq_video_non_burst_sync_events;
502         } else {
503                 DRM_DEBUG_KMS("Command mode\n");
504                 pkt_seq = pkt_seq_command_mode;
505         }
506 
507         err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
508         if (err < 0)
509                 return err;
510 
511         err = tegra_dsi_get_format(dsi->format, &format);
512         if (err < 0)
513                 return err;
514 
515         value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
516                 DSI_CONTROL_LANES(dsi->lanes - 1) |
517                 DSI_CONTROL_SOURCE(pipe);
518         tegra_dsi_writel(dsi, value, DSI_CONTROL);
519 
520         tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
521 
522         value = DSI_HOST_CONTROL_HS;
523         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
524 
525         value = tegra_dsi_readl(dsi, DSI_CONTROL);
526 
527         if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
528                 value |= DSI_CONTROL_HS_CLK_CTRL;
529 
530         value &= ~DSI_CONTROL_TX_TRIG(3);
531 
532         /* enable DCS commands for command mode */
533         if (dsi->flags & MIPI_DSI_MODE_VIDEO)
534                 value &= ~DSI_CONTROL_DCS_ENABLE;
535         else
536                 value |= DSI_CONTROL_DCS_ENABLE;
537 
538         value |= DSI_CONTROL_VIDEO_ENABLE;
539         value &= ~DSI_CONTROL_HOST_ENABLE;
540         tegra_dsi_writel(dsi, value, DSI_CONTROL);
541 
542         for (i = 0; i < NUM_PKT_SEQ; i++)
543                 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
544 
545         if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
546                 /* horizontal active pixels */
547                 hact = mode->hdisplay * mul / div;
548 
549                 /* horizontal sync width */
550                 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
551                 hsw -= 10;
552 
553                 /* horizontal back porch */
554                 hbp = (mode->htotal - mode->hsync_end) * mul / div;
555                 hbp -= 14;
556 
557                 /* horizontal front porch */
558                 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
559                 hfp -= 8;
560 
561                 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
562                 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
563                 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
564                 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
565 
566                 /* set SOL delay (for non-burst mode only) */
567                 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
568 
569                 /* TODO: implement ganged mode */
570         } else {
571                 u16 bytes;
572 
573                 if (dsi->master || dsi->slave) {
574                         /*
575                          * For ganged mode, assume symmetric left-right mode.
576                          */
577                         bytes = 1 + (mode->hdisplay / 2) * mul / div;
578                 } else {
579                         /* 1 byte (DCS command) + pixel data */
580                         bytes = 1 + mode->hdisplay * mul / div;
581                 }
582 
583                 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
584                 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
585                 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
586                 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
587 
588                 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
589                         MIPI_DCS_WRITE_MEMORY_CONTINUE;
590                 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
591 
592                 /* set SOL delay */
593                 if (dsi->master || dsi->slave) {
594                         unsigned int lanes = tegra_dsi_get_lanes(dsi);
595                         unsigned long delay, bclk, bclk_ganged;
596 
597                         /* SOL to valid, valid to FIFO and FIFO write delay */
598                         delay = 4 + 4 + 2;
599                         delay = DIV_ROUND_UP(delay * mul, div * lanes);
600                         /* FIFO read delay */
601                         delay = delay + 6;
602 
603                         bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
604                         bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
605                         value = bclk - bclk_ganged + delay + 20;
606                 } else {
607                         /* TODO: revisit for non-ganged mode */
608                         value = 8 * mul / div;
609                 }
610 
611                 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
612         }
613 
614         if (dsi->slave) {
615                 err = tegra_dsi_configure(dsi->slave, pipe, mode);
616                 if (err < 0)
617                         return err;
618 
619                 /*
620                  * TODO: Support modes other than symmetrical left-right
621                  * split.
622                  */
623                 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
624                 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
625                                         mode->hdisplay / 2);
626         }
627 
628         return 0;
629 }
630 
631 static int tegra_output_dsi_enable(struct tegra_output *output)
632 {
633         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
634         const struct drm_display_mode *mode = &dc->base.mode;
635         struct tegra_dsi *dsi = to_dsi(output);
636         u32 value;
637         int err;
638 
639         if (dsi->enabled)
640                 return 0;
641 
642         err = tegra_dsi_configure(dsi, dc->pipe, mode);
643         if (err < 0)
644                 return err;
645 
646         /* enable display controller */
647         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
648         value |= DSI_ENABLE;
649         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
650 
651         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
652         value &= ~DISP_CTRL_MODE_MASK;
653         value |= DISP_CTRL_MODE_C_DISPLAY;
654         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
655 
656         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
657         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
658                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
659         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
660 
661         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
662         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
663 
664         /* enable DSI controller */
665         tegra_dsi_enable(dsi);
666 
667         dsi->enabled = true;
668 
669         return 0;
670 }
671 
672 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
673 {
674         u32 value;
675 
676         timeout = jiffies + msecs_to_jiffies(timeout);
677 
678         while (time_before(jiffies, timeout)) {
679                 value = tegra_dsi_readl(dsi, DSI_STATUS);
680                 if (value & DSI_STATUS_IDLE)
681                         return 0;
682 
683                 usleep_range(1000, 2000);
684         }
685 
686         return -ETIMEDOUT;
687 }
688 
689 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
690 {
691         u32 value;
692 
693         value = tegra_dsi_readl(dsi, DSI_CONTROL);
694         value &= ~DSI_CONTROL_VIDEO_ENABLE;
695         tegra_dsi_writel(dsi, value, DSI_CONTROL);
696 
697         if (dsi->slave)
698                 tegra_dsi_video_disable(dsi->slave);
699 }
700 
701 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
702 {
703         tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
704         tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
705         tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
706 }
707 
708 static void tegra_dsi_disable(struct tegra_dsi *dsi)
709 {
710         u32 value;
711 
712         if (dsi->slave) {
713                 tegra_dsi_ganged_disable(dsi->slave);
714                 tegra_dsi_ganged_disable(dsi);
715         }
716 
717         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
718         value &= ~DSI_POWER_CONTROL_ENABLE;
719         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
720 
721         if (dsi->slave)
722                 tegra_dsi_disable(dsi->slave);
723 
724         usleep_range(5000, 10000);
725 }
726 
727 static int tegra_output_dsi_disable(struct tegra_output *output)
728 {
729         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
730         struct tegra_dsi *dsi = to_dsi(output);
731         unsigned long value;
732         int err;
733 
734         if (!dsi->enabled)
735                 return 0;
736 
737         tegra_dsi_video_disable(dsi);
738 
739         /*
740          * The following accesses registers of the display controller, so make
741          * sure it's only executed when the output is attached to one.
742          */
743         if (dc) {
744                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
745                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
746                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
747                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
748 
749                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
750                 value &= ~DISP_CTRL_MODE_MASK;
751                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
752 
753                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
754                 value &= ~DSI_ENABLE;
755                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
756 
757                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
758                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
759         }
760 
761         err = tegra_dsi_wait_idle(dsi, 100);
762         if (err < 0)
763                 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
764 
765         tegra_dsi_disable(dsi);
766 
767         dsi->enabled = false;
768 
769         return 0;
770 }
771 
772 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
773                                   unsigned int vrefresh)
774 {
775         unsigned int timeout;
776         u32 value;
777 
778         /* one frame high-speed transmission timeout */
779         timeout = (bclk / vrefresh) / 512;
780         value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
781         tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
782 
783         /* 2 ms peripheral timeout for panel */
784         timeout = 2 * bclk / 512 * 1000;
785         value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
786         tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
787 
788         value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
789         tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
790 
791         if (dsi->slave)
792                 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
793 }
794 
795 static int tegra_output_dsi_setup_clock(struct tegra_output *output,
796                                         struct clk *clk, unsigned long pclk,
797                                         unsigned int *divp)
798 {
799         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
800         struct drm_display_mode *mode = &dc->base.mode;
801         struct tegra_dsi *dsi = to_dsi(output);
802         unsigned int mul, div, vrefresh, lanes;
803         unsigned long bclk, plld;
804         int err;
805 
806         lanes = tegra_dsi_get_lanes(dsi);
807 
808         err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
809         if (err < 0)
810                 return err;
811 
812         DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, lanes);
813         vrefresh = drm_mode_vrefresh(mode);
814         DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
815 
816         /* compute byte clock */
817         bclk = (pclk * mul) / (div * lanes);
818 
819         /*
820          * Compute bit clock and round up to the next MHz.
821          */
822         plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
823 
824         /*
825          * We divide the frequency by two here, but we make up for that by
826          * setting the shift clock divider (further below) to half of the
827          * correct value.
828          */
829         plld /= 2;
830 
831         err = clk_set_parent(clk, dsi->clk_parent);
832         if (err < 0) {
833                 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
834                 return err;
835         }
836 
837         err = clk_set_rate(dsi->clk_parent, plld);
838         if (err < 0) {
839                 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
840                         plld);
841                 return err;
842         }
843 
844         /*
845          * Derive pixel clock from bit clock using the shift clock divider.
846          * Note that this is only half of what we would expect, but we need
847          * that to make up for the fact that we divided the bit clock by a
848          * factor of two above.
849          *
850          * It's not clear exactly why this is necessary, but the display is
851          * not working properly otherwise. Perhaps the PLLs cannot generate
852          * frequencies sufficiently high.
853          */
854         *divp = ((8 * mul) / (div * lanes)) - 2;
855 
856         /*
857          * XXX: Move the below somewhere else so that we don't need to have
858          * access to the vrefresh in this function?
859          */
860         tegra_dsi_set_timeout(dsi, bclk, vrefresh);
861 
862         err = tegra_dsi_set_phy_timing(dsi);
863         if (err < 0)
864                 return err;
865 
866         return 0;
867 }
868 
869 static int tegra_output_dsi_check_mode(struct tegra_output *output,
870                                        struct drm_display_mode *mode,
871                                        enum drm_mode_status *status)
872 {
873         /*
874          * FIXME: For now, always assume that the mode is okay.
875          */
876 
877         *status = MODE_OK;
878 
879         return 0;
880 }
881 
882 static const struct tegra_output_ops dsi_ops = {
883         .enable = tegra_output_dsi_enable,
884         .disable = tegra_output_dsi_disable,
885         .setup_clock = tegra_output_dsi_setup_clock,
886         .check_mode = tegra_output_dsi_check_mode,
887 };
888 
889 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
890 {
891         unsigned long value;
892 
893         value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
894         tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
895 
896         return 0;
897 }
898 
899 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
900 {
901         u32 value;
902 
903         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
904         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
905         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
906         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
907         tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
908 
909         /* start calibration */
910         tegra_dsi_pad_enable(dsi);
911 
912         value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
913                 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
914                 DSI_PAD_OUT_CLK(0x0);
915         tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
916 
917         return tegra_mipi_calibrate(dsi->mipi);
918 }
919 
920 static int tegra_dsi_init(struct host1x_client *client)
921 {
922         struct drm_device *drm = dev_get_drvdata(client->parent);
923         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
924         int err;
925 
926         /* Gangsters must not register their own outputs. */
927         if (!dsi->master) {
928                 dsi->output.type = TEGRA_OUTPUT_DSI;
929                 dsi->output.dev = client->dev;
930                 dsi->output.ops = &dsi_ops;
931 
932                 err = tegra_output_init(drm, &dsi->output);
933                 if (err < 0) {
934                         dev_err(client->dev, "output setup failed: %d\n", err);
935                         return err;
936                 }
937         }
938 
939         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
940                 err = tegra_dsi_debugfs_init(dsi, drm->primary);
941                 if (err < 0)
942                         dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
943         }
944 
945         return 0;
946 }
947 
948 static int tegra_dsi_exit(struct host1x_client *client)
949 {
950         struct tegra_dsi *dsi = host1x_client_to_dsi(client);
951         int err;
952 
953         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
954                 err = tegra_dsi_debugfs_exit(dsi);
955                 if (err < 0)
956                         dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
957         }
958 
959         if (!dsi->master) {
960                 err = tegra_output_disable(&dsi->output);
961                 if (err < 0) {
962                         dev_err(client->dev, "output failed to disable: %d\n",
963                                 err);
964                         return err;
965                 }
966 
967                 err = tegra_output_exit(&dsi->output);
968                 if (err < 0) {
969                         dev_err(client->dev, "output cleanup failed: %d\n",
970                                 err);
971                         return err;
972                 }
973         }
974 
975         return 0;
976 }
977 
978 static const struct host1x_client_ops dsi_client_ops = {
979         .init = tegra_dsi_init,
980         .exit = tegra_dsi_exit,
981 };
982 
983 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
984 {
985         struct clk *parent;
986         int err;
987 
988         parent = clk_get_parent(dsi->clk);
989         if (!parent)
990                 return -EINVAL;
991 
992         err = clk_set_parent(parent, dsi->clk_parent);
993         if (err < 0)
994                 return err;
995 
996         return 0;
997 }
998 
999 static const char * const error_report[16] = {
1000         "SoT Error",
1001         "SoT Sync Error",
1002         "EoT Sync Error",
1003         "Escape Mode Entry Command Error",
1004         "Low-Power Transmit Sync Error",
1005         "Peripheral Timeout Error",
1006         "False Control Error",
1007         "Contention Detected",
1008         "ECC Error, single-bit",
1009         "ECC Error, multi-bit",
1010         "Checksum Error",
1011         "DSI Data Type Not Recognized",
1012         "DSI VC ID Invalid",
1013         "Invalid Transmission Length",
1014         "Reserved",
1015         "DSI Protocol Violation",
1016 };
1017 
1018 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1019                                        const struct mipi_dsi_msg *msg,
1020                                        size_t count)
1021 {
1022         u8 *rx = msg->rx_buf;
1023         unsigned int i, j, k;
1024         size_t size = 0;
1025         u16 errors;
1026         u32 value;
1027 
1028         /* read and parse packet header */
1029         value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1030 
1031         switch (value & 0x3f) {
1032         case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1033                 errors = (value >> 8) & 0xffff;
1034                 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1035                         errors);
1036                 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1037                         if (errors & BIT(i))
1038                                 dev_dbg(dsi->dev, "  %2u: %s\n", i,
1039                                         error_report[i]);
1040                 break;
1041 
1042         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1043                 rx[0] = (value >> 8) & 0xff;
1044                 size = 1;
1045                 break;
1046 
1047         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1048                 rx[0] = (value >>  8) & 0xff;
1049                 rx[1] = (value >> 16) & 0xff;
1050                 size = 2;
1051                 break;
1052 
1053         case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1054                 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1055                 break;
1056 
1057         case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1058                 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1059                 break;
1060 
1061         default:
1062                 dev_err(dsi->dev, "unhandled response type: %02x\n",
1063                         value & 0x3f);
1064                 return -EPROTO;
1065         }
1066 
1067         size = min(size, msg->rx_len);
1068 
1069         if (msg->rx_buf && size > 0) {
1070                 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1071                         u8 *rx = msg->rx_buf + j;
1072 
1073                         value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1074 
1075                         for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1076                                 rx[j + k] = (value >> (k << 3)) & 0xff;
1077                 }
1078         }
1079 
1080         return size;
1081 }
1082 
1083 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1084 {
1085         tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1086 
1087         timeout = jiffies + msecs_to_jiffies(timeout);
1088 
1089         while (time_before(jiffies, timeout)) {
1090                 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1091                 if ((value & DSI_TRIGGER_HOST) == 0)
1092                         return 0;
1093 
1094                 usleep_range(1000, 2000);
1095         }
1096 
1097         DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1098         return -ETIMEDOUT;
1099 }
1100 
1101 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1102                                        unsigned long timeout)
1103 {
1104         timeout = jiffies + msecs_to_jiffies(250);
1105 
1106         while (time_before(jiffies, timeout)) {
1107                 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1108                 u8 count = value & 0x1f;
1109 
1110                 if (count > 0)
1111                         return count;
1112 
1113                 usleep_range(1000, 2000);
1114         }
1115 
1116         DRM_DEBUG_KMS("peripheral returned no data\n");
1117         return -ETIMEDOUT;
1118 }
1119 
1120 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1121                               const void *buffer, size_t size)
1122 {
1123         const u8 *buf = buffer;
1124         size_t i, j;
1125         u32 value;
1126 
1127         for (j = 0; j < size; j += 4) {
1128                 value = 0;
1129 
1130                 for (i = 0; i < 4 && j + i < size; i++)
1131                         value |= buf[j + i] << (i << 3);
1132 
1133                 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1134         }
1135 }
1136 
1137 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1138                                        const struct mipi_dsi_msg *msg)
1139 {
1140         struct tegra_dsi *dsi = host_to_tegra(host);
1141         struct mipi_dsi_packet packet;
1142         const u8 *header;
1143         size_t count;
1144         ssize_t err;
1145         u32 value;
1146 
1147         err = mipi_dsi_create_packet(&packet, msg);
1148         if (err < 0)
1149                 return err;
1150 
1151         header = packet.header;
1152 
1153         /* maximum FIFO depth is 1920 words */
1154         if (packet.size > dsi->video_fifo_depth * 4)
1155                 return -ENOSPC;
1156 
1157         /* reset underflow/overflow flags */
1158         value = tegra_dsi_readl(dsi, DSI_STATUS);
1159         if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1160                 value = DSI_HOST_CONTROL_FIFO_RESET;
1161                 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1162                 usleep_range(10, 20);
1163         }
1164 
1165         value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1166         value |= DSI_POWER_CONTROL_ENABLE;
1167         tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1168 
1169         usleep_range(5000, 10000);
1170 
1171         value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1172                 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1173 
1174         if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1175                 value |= DSI_HOST_CONTROL_HS;
1176 
1177         /*
1178          * The host FIFO has a maximum of 64 words, so larger transmissions
1179          * need to use the video FIFO.
1180          */
1181         if (packet.size > dsi->host_fifo_depth * 4)
1182                 value |= DSI_HOST_CONTROL_FIFO_SEL;
1183 
1184         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1185 
1186         /*
1187          * For reads and messages with explicitly requested ACK, generate a
1188          * BTA sequence after the transmission of the packet.
1189          */
1190         if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1191             (msg->rx_buf && msg->rx_len > 0)) {
1192                 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1193                 value |= DSI_HOST_CONTROL_PKT_BTA;
1194                 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1195         }
1196 
1197         value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1198         tegra_dsi_writel(dsi, value, DSI_CONTROL);
1199 
1200         /* write packet header, ECC is generated by hardware */
1201         value = header[2] << 16 | header[1] << 8 | header[0];
1202         tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1203 
1204         /* write payload (if any) */
1205         if (packet.payload_length > 0)
1206                 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1207                                   packet.payload_length);
1208 
1209         err = tegra_dsi_transmit(dsi, 250);
1210         if (err < 0)
1211                 return err;
1212 
1213         if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1214             (msg->rx_buf && msg->rx_len > 0)) {
1215                 err = tegra_dsi_wait_for_response(dsi, 250);
1216                 if (err < 0)
1217                         return err;
1218 
1219                 count = err;
1220 
1221                 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1222                 switch (value) {
1223                 case 0x84:
1224                         /*
1225                         dev_dbg(dsi->dev, "ACK\n");
1226                         */
1227                         break;
1228 
1229                 case 0x87:
1230                         /*
1231                         dev_dbg(dsi->dev, "ESCAPE\n");
1232                         */
1233                         break;
1234 
1235                 default:
1236                         dev_err(dsi->dev, "unknown status: %08x\n", value);
1237                         break;
1238                 }
1239 
1240                 if (count > 1) {
1241                         err = tegra_dsi_read_response(dsi, msg, count);
1242                         if (err < 0)
1243                                 dev_err(dsi->dev,
1244                                         "failed to parse response: %zd\n",
1245                                         err);
1246                         else {
1247                                 /*
1248                                  * For read commands, return the number of
1249                                  * bytes returned by the peripheral.
1250                                  */
1251                                 count = err;
1252                         }
1253                 }
1254         } else {
1255                 /*
1256                  * For write commands, we have transmitted the 4-byte header
1257                  * plus the variable-length payload.
1258                  */
1259                 count = 4 + packet.payload_length;
1260         }
1261 
1262         return count;
1263 }
1264 
1265 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1266 {
1267         struct clk *parent;
1268         int err;
1269 
1270         /* make sure both DSI controllers share the same PLL */
1271         parent = clk_get_parent(dsi->slave->clk);
1272         if (!parent)
1273                 return -EINVAL;
1274 
1275         err = clk_set_parent(parent, dsi->clk_parent);
1276         if (err < 0)
1277                 return err;
1278 
1279         return 0;
1280 }
1281 
1282 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1283                                  struct mipi_dsi_device *device)
1284 {
1285         struct tegra_dsi *dsi = host_to_tegra(host);
1286 
1287         dsi->flags = device->mode_flags;
1288         dsi->format = device->format;
1289         dsi->lanes = device->lanes;
1290 
1291         if (dsi->slave) {
1292                 int err;
1293 
1294                 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1295                         dev_name(&device->dev));
1296 
1297                 err = tegra_dsi_ganged_setup(dsi);
1298                 if (err < 0) {
1299                         dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1300                                 err);
1301                         return err;
1302                 }
1303         }
1304 
1305         /*
1306          * Slaves don't have a panel associated with them, so they provide
1307          * merely the second channel.
1308          */
1309         if (!dsi->master) {
1310                 struct tegra_output *output = &dsi->output;
1311 
1312                 output->panel = of_drm_find_panel(device->dev.of_node);
1313                 if (output->panel && output->connector.dev) {
1314                         drm_panel_attach(output->panel, &output->connector);
1315                         drm_helper_hpd_irq_event(output->connector.dev);
1316                 }
1317         }
1318 
1319         return 0;
1320 }
1321 
1322 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1323                                  struct mipi_dsi_device *device)
1324 {
1325         struct tegra_dsi *dsi = host_to_tegra(host);
1326         struct tegra_output *output = &dsi->output;
1327 
1328         if (output->panel && &device->dev == output->panel->dev) {
1329                 output->panel = NULL;
1330 
1331                 if (output->connector.dev)
1332                         drm_helper_hpd_irq_event(output->connector.dev);
1333         }
1334 
1335         return 0;
1336 }
1337 
1338 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1339         .attach = tegra_dsi_host_attach,
1340         .detach = tegra_dsi_host_detach,
1341         .transfer = tegra_dsi_host_transfer,
1342 };
1343 
1344 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1345 {
1346         struct device_node *np;
1347 
1348         np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1349         if (np) {
1350                 struct platform_device *gangster = of_find_device_by_node(np);
1351 
1352                 dsi->slave = platform_get_drvdata(gangster);
1353                 of_node_put(np);
1354 
1355                 if (!dsi->slave)
1356                         return -EPROBE_DEFER;
1357 
1358                 dsi->slave->master = dsi;
1359         }
1360 
1361         return 0;
1362 }
1363 
1364 static int tegra_dsi_probe(struct platform_device *pdev)
1365 {
1366         struct tegra_dsi *dsi;
1367         struct resource *regs;
1368         int err;
1369 
1370         dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1371         if (!dsi)
1372                 return -ENOMEM;
1373 
1374         dsi->output.dev = dsi->dev = &pdev->dev;
1375         dsi->video_fifo_depth = 1920;
1376         dsi->host_fifo_depth = 64;
1377 
1378         err = tegra_dsi_ganged_probe(dsi);
1379         if (err < 0)
1380                 return err;
1381 
1382         err = tegra_output_probe(&dsi->output);
1383         if (err < 0)
1384                 return err;
1385 
1386         dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1387 
1388         /*
1389          * Assume these values by default. When a DSI peripheral driver
1390          * attaches to the DSI host, the parameters will be taken from
1391          * the attached device.
1392          */
1393         dsi->flags = MIPI_DSI_MODE_VIDEO;
1394         dsi->format = MIPI_DSI_FMT_RGB888;
1395         dsi->lanes = 4;
1396 
1397         dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1398         if (IS_ERR(dsi->rst))
1399                 return PTR_ERR(dsi->rst);
1400 
1401         err = reset_control_deassert(dsi->rst);
1402         if (err < 0) {
1403                 dev_err(&pdev->dev, "failed to bring DSI out of reset: %d\n",
1404                         err);
1405                 return err;
1406         }
1407 
1408         dsi->clk = devm_clk_get(&pdev->dev, NULL);
1409         if (IS_ERR(dsi->clk)) {
1410                 dev_err(&pdev->dev, "cannot get DSI clock\n");
1411                 err = PTR_ERR(dsi->clk);
1412                 goto reset;
1413         }
1414 
1415         err = clk_prepare_enable(dsi->clk);
1416         if (err < 0) {
1417                 dev_err(&pdev->dev, "cannot enable DSI clock\n");
1418                 goto reset;
1419         }
1420 
1421         dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1422         if (IS_ERR(dsi->clk_lp)) {
1423                 dev_err(&pdev->dev, "cannot get low-power clock\n");
1424                 err = PTR_ERR(dsi->clk_lp);
1425                 goto disable_clk;
1426         }
1427 
1428         err = clk_prepare_enable(dsi->clk_lp);
1429         if (err < 0) {
1430                 dev_err(&pdev->dev, "cannot enable low-power clock\n");
1431                 goto disable_clk;
1432         }
1433 
1434         dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1435         if (IS_ERR(dsi->clk_parent)) {
1436                 dev_err(&pdev->dev, "cannot get parent clock\n");
1437                 err = PTR_ERR(dsi->clk_parent);
1438                 goto disable_clk_lp;
1439         }
1440 
1441         dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1442         if (IS_ERR(dsi->vdd)) {
1443                 dev_err(&pdev->dev, "cannot get VDD supply\n");
1444                 err = PTR_ERR(dsi->vdd);
1445                 goto disable_clk_lp;
1446         }
1447 
1448         err = regulator_enable(dsi->vdd);
1449         if (err < 0) {
1450                 dev_err(&pdev->dev, "cannot enable VDD supply\n");
1451                 goto disable_clk_lp;
1452         }
1453 
1454         err = tegra_dsi_setup_clocks(dsi);
1455         if (err < 0) {
1456                 dev_err(&pdev->dev, "cannot setup clocks\n");
1457                 goto disable_vdd;
1458         }
1459 
1460         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1461         dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1462         if (IS_ERR(dsi->regs)) {
1463                 err = PTR_ERR(dsi->regs);
1464                 goto disable_vdd;
1465         }
1466 
1467         dsi->mipi = tegra_mipi_request(&pdev->dev);
1468         if (IS_ERR(dsi->mipi)) {
1469                 err = PTR_ERR(dsi->mipi);
1470                 goto disable_vdd;
1471         }
1472 
1473         err = tegra_dsi_pad_calibrate(dsi);
1474         if (err < 0) {
1475                 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
1476                 goto mipi_free;
1477         }
1478 
1479         dsi->host.ops = &tegra_dsi_host_ops;
1480         dsi->host.dev = &pdev->dev;
1481 
1482         err = mipi_dsi_host_register(&dsi->host);
1483         if (err < 0) {
1484                 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1485                 goto mipi_free;
1486         }
1487 
1488         INIT_LIST_HEAD(&dsi->client.list);
1489         dsi->client.ops = &dsi_client_ops;
1490         dsi->client.dev = &pdev->dev;
1491 
1492         err = host1x_client_register(&dsi->client);
1493         if (err < 0) {
1494                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1495                         err);
1496                 goto unregister;
1497         }
1498 
1499         platform_set_drvdata(pdev, dsi);
1500 
1501         return 0;
1502 
1503 unregister:
1504         mipi_dsi_host_unregister(&dsi->host);
1505 mipi_free:
1506         tegra_mipi_free(dsi->mipi);
1507 disable_vdd:
1508         regulator_disable(dsi->vdd);
1509 disable_clk_lp:
1510         clk_disable_unprepare(dsi->clk_lp);
1511 disable_clk:
1512         clk_disable_unprepare(dsi->clk);
1513 reset:
1514         reset_control_assert(dsi->rst);
1515         return err;
1516 }
1517 
1518 static int tegra_dsi_remove(struct platform_device *pdev)
1519 {
1520         struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1521         int err;
1522 
1523         err = host1x_client_unregister(&dsi->client);
1524         if (err < 0) {
1525                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1526                         err);
1527                 return err;
1528         }
1529 
1530         mipi_dsi_host_unregister(&dsi->host);
1531         tegra_mipi_free(dsi->mipi);
1532 
1533         regulator_disable(dsi->vdd);
1534         clk_disable_unprepare(dsi->clk_lp);
1535         clk_disable_unprepare(dsi->clk);
1536         reset_control_assert(dsi->rst);
1537 
1538         err = tegra_output_remove(&dsi->output);
1539         if (err < 0) {
1540                 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1541                 return err;
1542         }
1543 
1544         return 0;
1545 }
1546 
1547 static const struct of_device_id tegra_dsi_of_match[] = {
1548         { .compatible = "nvidia,tegra114-dsi", },
1549         { },
1550 };
1551 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1552 
1553 struct platform_driver tegra_dsi_driver = {
1554         .driver = {
1555                 .name = "tegra-dsi",
1556                 .of_match_table = tegra_dsi_of_match,
1557         },
1558         .probe = tegra_dsi_probe,
1559         .remove = tegra_dsi_remove,
1560 };
1561 

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