Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/gpu/drm/tegra/dc.c

  1 /*
  2  * Copyright (C) 2012 Avionic Design GmbH
  3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License version 2 as
  7  * published by the Free Software Foundation.
  8  */
  9 
 10 #include <linux/clk.h>
 11 #include <linux/debugfs.h>
 12 #include <linux/iommu.h>
 13 #include <linux/reset.h>
 14 
 15 #include <soc/tegra/pmc.h>
 16 
 17 #include "dc.h"
 18 #include "drm.h"
 19 #include "gem.h"
 20 
 21 #include <drm/drm_atomic.h>
 22 #include <drm/drm_atomic_helper.h>
 23 #include <drm/drm_plane_helper.h>
 24 
 25 struct tegra_dc_soc_info {
 26         bool supports_border_color;
 27         bool supports_interlacing;
 28         bool supports_cursor;
 29         bool supports_block_linear;
 30         unsigned int pitch_align;
 31         bool has_powergate;
 32 };
 33 
 34 struct tegra_plane {
 35         struct drm_plane base;
 36         unsigned int index;
 37 };
 38 
 39 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
 40 {
 41         return container_of(plane, struct tegra_plane, base);
 42 }
 43 
 44 struct tegra_dc_state {
 45         struct drm_crtc_state base;
 46 
 47         struct clk *clk;
 48         unsigned long pclk;
 49         unsigned int div;
 50 
 51         u32 planes;
 52 };
 53 
 54 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
 55 {
 56         if (state)
 57                 return container_of(state, struct tegra_dc_state, base);
 58 
 59         return NULL;
 60 }
 61 
 62 struct tegra_plane_state {
 63         struct drm_plane_state base;
 64 
 65         struct tegra_bo_tiling tiling;
 66         u32 format;
 67         u32 swap;
 68 };
 69 
 70 static inline struct tegra_plane_state *
 71 to_tegra_plane_state(struct drm_plane_state *state)
 72 {
 73         if (state)
 74                 return container_of(state, struct tegra_plane_state, base);
 75 
 76         return NULL;
 77 }
 78 
 79 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
 80 {
 81         stats->frames = 0;
 82         stats->vblank = 0;
 83         stats->underflow = 0;
 84         stats->overflow = 0;
 85 }
 86 
 87 /*
 88  * Reads the active copy of a register. This takes the dc->lock spinlock to
 89  * prevent races with the VBLANK processing which also needs access to the
 90  * active copy of some registers.
 91  */
 92 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
 93 {
 94         unsigned long flags;
 95         u32 value;
 96 
 97         spin_lock_irqsave(&dc->lock, flags);
 98 
 99         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
100         value = tegra_dc_readl(dc, offset);
101         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
102 
103         spin_unlock_irqrestore(&dc->lock, flags);
104         return value;
105 }
106 
107 /*
108  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
110  * Latching happens mmediately if the display controller is in STOP mode or
111  * on the next frame boundary otherwise.
112  *
113  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
114  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
115  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
116  * into the ACTIVE copy, either immediately if the display controller is in
117  * STOP mode, or at the next frame boundary otherwise.
118  */
119 void tegra_dc_commit(struct tegra_dc *dc)
120 {
121         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
122         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
123 }
124 
125 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
126 {
127         /* assume no swapping of fetched data */
128         if (swap)
129                 *swap = BYTE_SWAP_NOSWAP;
130 
131         switch (fourcc) {
132         case DRM_FORMAT_XBGR8888:
133                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
134                 break;
135 
136         case DRM_FORMAT_XRGB8888:
137                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
138                 break;
139 
140         case DRM_FORMAT_RGB565:
141                 *format = WIN_COLOR_DEPTH_B5G6R5;
142                 break;
143 
144         case DRM_FORMAT_UYVY:
145                 *format = WIN_COLOR_DEPTH_YCbCr422;
146                 break;
147 
148         case DRM_FORMAT_YUYV:
149                 if (swap)
150                         *swap = BYTE_SWAP_SWAP2;
151 
152                 *format = WIN_COLOR_DEPTH_YCbCr422;
153                 break;
154 
155         case DRM_FORMAT_YUV420:
156                 *format = WIN_COLOR_DEPTH_YCbCr420P;
157                 break;
158 
159         case DRM_FORMAT_YUV422:
160                 *format = WIN_COLOR_DEPTH_YCbCr422P;
161                 break;
162 
163         default:
164                 return -EINVAL;
165         }
166 
167         return 0;
168 }
169 
170 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
171 {
172         switch (format) {
173         case WIN_COLOR_DEPTH_YCbCr422:
174         case WIN_COLOR_DEPTH_YUV422:
175                 if (planar)
176                         *planar = false;
177 
178                 return true;
179 
180         case WIN_COLOR_DEPTH_YCbCr420P:
181         case WIN_COLOR_DEPTH_YUV420P:
182         case WIN_COLOR_DEPTH_YCbCr422P:
183         case WIN_COLOR_DEPTH_YUV422P:
184         case WIN_COLOR_DEPTH_YCbCr422R:
185         case WIN_COLOR_DEPTH_YUV422R:
186         case WIN_COLOR_DEPTH_YCbCr422RA:
187         case WIN_COLOR_DEPTH_YUV422RA:
188                 if (planar)
189                         *planar = true;
190 
191                 return true;
192         }
193 
194         if (planar)
195                 *planar = false;
196 
197         return false;
198 }
199 
200 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
201                                   unsigned int bpp)
202 {
203         fixed20_12 outf = dfixed_init(out);
204         fixed20_12 inf = dfixed_init(in);
205         u32 dda_inc;
206         int max;
207 
208         if (v)
209                 max = 15;
210         else {
211                 switch (bpp) {
212                 case 2:
213                         max = 8;
214                         break;
215 
216                 default:
217                         WARN_ON_ONCE(1);
218                         /* fallthrough */
219                 case 4:
220                         max = 4;
221                         break;
222                 }
223         }
224 
225         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
226         inf.full -= dfixed_const(1);
227 
228         dda_inc = dfixed_div(inf, outf);
229         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
230 
231         return dda_inc;
232 }
233 
234 static inline u32 compute_initial_dda(unsigned int in)
235 {
236         fixed20_12 inf = dfixed_init(in);
237         return dfixed_frac(inf);
238 }
239 
240 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
241                                   const struct tegra_dc_window *window)
242 {
243         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
244         unsigned long value, flags;
245         bool yuv, planar;
246 
247         /*
248          * For YUV planar modes, the number of bytes per pixel takes into
249          * account only the luma component and therefore is 1.
250          */
251         yuv = tegra_dc_format_is_yuv(window->format, &planar);
252         if (!yuv)
253                 bpp = window->bits_per_pixel / 8;
254         else
255                 bpp = planar ? 1 : 2;
256 
257         spin_lock_irqsave(&dc->lock, flags);
258 
259         value = WINDOW_A_SELECT << index;
260         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
261 
262         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
263         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
264 
265         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
266         tegra_dc_writel(dc, value, DC_WIN_POSITION);
267 
268         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
269         tegra_dc_writel(dc, value, DC_WIN_SIZE);
270 
271         h_offset = window->src.x * bpp;
272         v_offset = window->src.y;
273         h_size = window->src.w * bpp;
274         v_size = window->src.h;
275 
276         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
277         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
278 
279         /*
280          * For DDA computations the number of bytes per pixel for YUV planar
281          * modes needs to take into account all Y, U and V components.
282          */
283         if (yuv && planar)
284                 bpp = 2;
285 
286         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
287         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
288 
289         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
290         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
291 
292         h_dda = compute_initial_dda(window->src.x);
293         v_dda = compute_initial_dda(window->src.y);
294 
295         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
296         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
297 
298         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
299         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
300 
301         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
302 
303         if (yuv && planar) {
304                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
305                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
306                 value = window->stride[1] << 16 | window->stride[0];
307                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
308         } else {
309                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
310         }
311 
312         if (window->bottom_up)
313                 v_offset += window->src.h - 1;
314 
315         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
316         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
317 
318         if (dc->soc->supports_block_linear) {
319                 unsigned long height = window->tiling.value;
320 
321                 switch (window->tiling.mode) {
322                 case TEGRA_BO_TILING_MODE_PITCH:
323                         value = DC_WINBUF_SURFACE_KIND_PITCH;
324                         break;
325 
326                 case TEGRA_BO_TILING_MODE_TILED:
327                         value = DC_WINBUF_SURFACE_KIND_TILED;
328                         break;
329 
330                 case TEGRA_BO_TILING_MODE_BLOCK:
331                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
332                                 DC_WINBUF_SURFACE_KIND_BLOCK;
333                         break;
334                 }
335 
336                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
337         } else {
338                 switch (window->tiling.mode) {
339                 case TEGRA_BO_TILING_MODE_PITCH:
340                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
341                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
342                         break;
343 
344                 case TEGRA_BO_TILING_MODE_TILED:
345                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
346                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
347                         break;
348 
349                 case TEGRA_BO_TILING_MODE_BLOCK:
350                         /*
351                          * No need to handle this here because ->atomic_check
352                          * will already have filtered it out.
353                          */
354                         break;
355                 }
356 
357                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
358         }
359 
360         value = WIN_ENABLE;
361 
362         if (yuv) {
363                 /* setup default colorspace conversion coefficients */
364                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
365                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
366                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
367                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
368                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
369                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
370                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
371                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
372 
373                 value |= CSC_ENABLE;
374         } else if (window->bits_per_pixel < 24) {
375                 value |= COLOR_EXPAND;
376         }
377 
378         if (window->bottom_up)
379                 value |= V_DIRECTION;
380 
381         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
382 
383         /*
384          * Disable blending and assume Window A is the bottom-most window,
385          * Window C is the top-most window and Window B is in the middle.
386          */
387         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
388         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
389 
390         switch (index) {
391         case 0:
392                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
393                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
394                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
395                 break;
396 
397         case 1:
398                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
399                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
400                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
401                 break;
402 
403         case 2:
404                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
405                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
406                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
407                 break;
408         }
409 
410         spin_unlock_irqrestore(&dc->lock, flags);
411 }
412 
413 static void tegra_plane_destroy(struct drm_plane *plane)
414 {
415         struct tegra_plane *p = to_tegra_plane(plane);
416 
417         drm_plane_cleanup(plane);
418         kfree(p);
419 }
420 
421 static const u32 tegra_primary_plane_formats[] = {
422         DRM_FORMAT_XBGR8888,
423         DRM_FORMAT_XRGB8888,
424         DRM_FORMAT_RGB565,
425 };
426 
427 static void tegra_primary_plane_destroy(struct drm_plane *plane)
428 {
429         tegra_plane_destroy(plane);
430 }
431 
432 static void tegra_plane_reset(struct drm_plane *plane)
433 {
434         struct tegra_plane_state *state;
435 
436         if (plane->state)
437                 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
438 
439         kfree(plane->state);
440         plane->state = NULL;
441 
442         state = kzalloc(sizeof(*state), GFP_KERNEL);
443         if (state) {
444                 plane->state = &state->base;
445                 plane->state->plane = plane;
446         }
447 }
448 
449 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
450 {
451         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
452         struct tegra_plane_state *copy;
453 
454         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
455         if (!copy)
456                 return NULL;
457 
458         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
459         copy->tiling = state->tiling;
460         copy->format = state->format;
461         copy->swap = state->swap;
462 
463         return &copy->base;
464 }
465 
466 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
467                                              struct drm_plane_state *state)
468 {
469         __drm_atomic_helper_plane_destroy_state(plane, state);
470         kfree(state);
471 }
472 
473 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
474         .update_plane = drm_atomic_helper_update_plane,
475         .disable_plane = drm_atomic_helper_disable_plane,
476         .destroy = tegra_primary_plane_destroy,
477         .reset = tegra_plane_reset,
478         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
479         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
480 };
481 
482 static int tegra_plane_prepare_fb(struct drm_plane *plane,
483                                   const struct drm_plane_state *new_state)
484 {
485         return 0;
486 }
487 
488 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
489                                    const struct drm_plane_state *old_fb)
490 {
491 }
492 
493 static int tegra_plane_state_add(struct tegra_plane *plane,
494                                  struct drm_plane_state *state)
495 {
496         struct drm_crtc_state *crtc_state;
497         struct tegra_dc_state *tegra;
498 
499         /* Propagate errors from allocation or locking failures. */
500         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
501         if (IS_ERR(crtc_state))
502                 return PTR_ERR(crtc_state);
503 
504         tegra = to_dc_state(crtc_state);
505 
506         tegra->planes |= WIN_A_ACT_REQ << plane->index;
507 
508         return 0;
509 }
510 
511 static int tegra_plane_atomic_check(struct drm_plane *plane,
512                                     struct drm_plane_state *state)
513 {
514         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
515         struct tegra_bo_tiling *tiling = &plane_state->tiling;
516         struct tegra_plane *tegra = to_tegra_plane(plane);
517         struct tegra_dc *dc = to_tegra_dc(state->crtc);
518         int err;
519 
520         /* no need for further checks if the plane is being disabled */
521         if (!state->crtc)
522                 return 0;
523 
524         err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
525                               &plane_state->swap);
526         if (err < 0)
527                 return err;
528 
529         err = tegra_fb_get_tiling(state->fb, tiling);
530         if (err < 0)
531                 return err;
532 
533         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
534             !dc->soc->supports_block_linear) {
535                 DRM_ERROR("hardware doesn't support block linear mode\n");
536                 return -EINVAL;
537         }
538 
539         /*
540          * Tegra doesn't support different strides for U and V planes so we
541          * error out if the user tries to display a framebuffer with such a
542          * configuration.
543          */
544         if (drm_format_num_planes(state->fb->pixel_format) > 2) {
545                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
546                         DRM_ERROR("unsupported UV-plane configuration\n");
547                         return -EINVAL;
548                 }
549         }
550 
551         err = tegra_plane_state_add(tegra, state);
552         if (err < 0)
553                 return err;
554 
555         return 0;
556 }
557 
558 static void tegra_plane_atomic_update(struct drm_plane *plane,
559                                       struct drm_plane_state *old_state)
560 {
561         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
562         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
563         struct drm_framebuffer *fb = plane->state->fb;
564         struct tegra_plane *p = to_tegra_plane(plane);
565         struct tegra_dc_window window;
566         unsigned int i;
567 
568         /* rien ne va plus */
569         if (!plane->state->crtc || !plane->state->fb)
570                 return;
571 
572         memset(&window, 0, sizeof(window));
573         window.src.x = plane->state->src_x >> 16;
574         window.src.y = plane->state->src_y >> 16;
575         window.src.w = plane->state->src_w >> 16;
576         window.src.h = plane->state->src_h >> 16;
577         window.dst.x = plane->state->crtc_x;
578         window.dst.y = plane->state->crtc_y;
579         window.dst.w = plane->state->crtc_w;
580         window.dst.h = plane->state->crtc_h;
581         window.bits_per_pixel = fb->bits_per_pixel;
582         window.bottom_up = tegra_fb_is_bottom_up(fb);
583 
584         /* copy from state */
585         window.tiling = state->tiling;
586         window.format = state->format;
587         window.swap = state->swap;
588 
589         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
590                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
591 
592                 window.base[i] = bo->paddr + fb->offsets[i];
593                 window.stride[i] = fb->pitches[i];
594         }
595 
596         tegra_dc_setup_window(dc, p->index, &window);
597 }
598 
599 static void tegra_plane_atomic_disable(struct drm_plane *plane,
600                                        struct drm_plane_state *old_state)
601 {
602         struct tegra_plane *p = to_tegra_plane(plane);
603         struct tegra_dc *dc;
604         unsigned long flags;
605         u32 value;
606 
607         /* rien ne va plus */
608         if (!old_state || !old_state->crtc)
609                 return;
610 
611         dc = to_tegra_dc(old_state->crtc);
612 
613         spin_lock_irqsave(&dc->lock, flags);
614 
615         value = WINDOW_A_SELECT << p->index;
616         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
617 
618         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
619         value &= ~WIN_ENABLE;
620         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
621 
622         spin_unlock_irqrestore(&dc->lock, flags);
623 }
624 
625 static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
626         .prepare_fb = tegra_plane_prepare_fb,
627         .cleanup_fb = tegra_plane_cleanup_fb,
628         .atomic_check = tegra_plane_atomic_check,
629         .atomic_update = tegra_plane_atomic_update,
630         .atomic_disable = tegra_plane_atomic_disable,
631 };
632 
633 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
634                                                        struct tegra_dc *dc)
635 {
636         /*
637          * Ideally this would use drm_crtc_mask(), but that would require the
638          * CRTC to already be in the mode_config's list of CRTCs. However, it
639          * will only be added to that list in the drm_crtc_init_with_planes()
640          * (in tegra_dc_init()), which in turn requires registration of these
641          * planes. So we have ourselves a nice little chicken and egg problem
642          * here.
643          *
644          * We work around this by manually creating the mask from the number
645          * of CRTCs that have been registered, and should therefore always be
646          * the same as drm_crtc_index() after registration.
647          */
648         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
649         struct tegra_plane *plane;
650         unsigned int num_formats;
651         const u32 *formats;
652         int err;
653 
654         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
655         if (!plane)
656                 return ERR_PTR(-ENOMEM);
657 
658         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
659         formats = tegra_primary_plane_formats;
660 
661         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
662                                        &tegra_primary_plane_funcs, formats,
663                                        num_formats, DRM_PLANE_TYPE_PRIMARY,
664                                        NULL);
665         if (err < 0) {
666                 kfree(plane);
667                 return ERR_PTR(err);
668         }
669 
670         drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
671 
672         return &plane->base;
673 }
674 
675 static const u32 tegra_cursor_plane_formats[] = {
676         DRM_FORMAT_RGBA8888,
677 };
678 
679 static int tegra_cursor_atomic_check(struct drm_plane *plane,
680                                      struct drm_plane_state *state)
681 {
682         struct tegra_plane *tegra = to_tegra_plane(plane);
683         int err;
684 
685         /* no need for further checks if the plane is being disabled */
686         if (!state->crtc)
687                 return 0;
688 
689         /* scaling not supported for cursor */
690         if ((state->src_w >> 16 != state->crtc_w) ||
691             (state->src_h >> 16 != state->crtc_h))
692                 return -EINVAL;
693 
694         /* only square cursors supported */
695         if (state->src_w != state->src_h)
696                 return -EINVAL;
697 
698         if (state->crtc_w != 32 && state->crtc_w != 64 &&
699             state->crtc_w != 128 && state->crtc_w != 256)
700                 return -EINVAL;
701 
702         err = tegra_plane_state_add(tegra, state);
703         if (err < 0)
704                 return err;
705 
706         return 0;
707 }
708 
709 static void tegra_cursor_atomic_update(struct drm_plane *plane,
710                                        struct drm_plane_state *old_state)
711 {
712         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
713         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
714         struct drm_plane_state *state = plane->state;
715         u32 value = CURSOR_CLIP_DISPLAY;
716 
717         /* rien ne va plus */
718         if (!plane->state->crtc || !plane->state->fb)
719                 return;
720 
721         switch (state->crtc_w) {
722         case 32:
723                 value |= CURSOR_SIZE_32x32;
724                 break;
725 
726         case 64:
727                 value |= CURSOR_SIZE_64x64;
728                 break;
729 
730         case 128:
731                 value |= CURSOR_SIZE_128x128;
732                 break;
733 
734         case 256:
735                 value |= CURSOR_SIZE_256x256;
736                 break;
737 
738         default:
739                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
740                      state->crtc_h);
741                 return;
742         }
743 
744         value |= (bo->paddr >> 10) & 0x3fffff;
745         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
746 
747 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
748         value = (bo->paddr >> 32) & 0x3;
749         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
750 #endif
751 
752         /* enable cursor and set blend mode */
753         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
754         value |= CURSOR_ENABLE;
755         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
756 
757         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
758         value &= ~CURSOR_DST_BLEND_MASK;
759         value &= ~CURSOR_SRC_BLEND_MASK;
760         value |= CURSOR_MODE_NORMAL;
761         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
762         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
763         value |= CURSOR_ALPHA;
764         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
765 
766         /* position the cursor */
767         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
768         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
769 }
770 
771 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
772                                         struct drm_plane_state *old_state)
773 {
774         struct tegra_dc *dc;
775         u32 value;
776 
777         /* rien ne va plus */
778         if (!old_state || !old_state->crtc)
779                 return;
780 
781         dc = to_tegra_dc(old_state->crtc);
782 
783         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
784         value &= ~CURSOR_ENABLE;
785         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
786 }
787 
788 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
789         .update_plane = drm_atomic_helper_update_plane,
790         .disable_plane = drm_atomic_helper_disable_plane,
791         .destroy = tegra_plane_destroy,
792         .reset = tegra_plane_reset,
793         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
794         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
795 };
796 
797 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
798         .prepare_fb = tegra_plane_prepare_fb,
799         .cleanup_fb = tegra_plane_cleanup_fb,
800         .atomic_check = tegra_cursor_atomic_check,
801         .atomic_update = tegra_cursor_atomic_update,
802         .atomic_disable = tegra_cursor_atomic_disable,
803 };
804 
805 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
806                                                       struct tegra_dc *dc)
807 {
808         struct tegra_plane *plane;
809         unsigned int num_formats;
810         const u32 *formats;
811         int err;
812 
813         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814         if (!plane)
815                 return ERR_PTR(-ENOMEM);
816 
817         /*
818          * This index is kind of fake. The cursor isn't a regular plane, but
819          * its update and activation request bits in DC_CMD_STATE_CONTROL do
820          * use the same programming. Setting this fake index here allows the
821          * code in tegra_add_plane_state() to do the right thing without the
822          * need to special-casing the cursor plane.
823          */
824         plane->index = 6;
825 
826         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
827         formats = tegra_cursor_plane_formats;
828 
829         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
830                                        &tegra_cursor_plane_funcs, formats,
831                                        num_formats, DRM_PLANE_TYPE_CURSOR,
832                                        NULL);
833         if (err < 0) {
834                 kfree(plane);
835                 return ERR_PTR(err);
836         }
837 
838         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
839 
840         return &plane->base;
841 }
842 
843 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
844 {
845         tegra_plane_destroy(plane);
846 }
847 
848 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
849         .update_plane = drm_atomic_helper_update_plane,
850         .disable_plane = drm_atomic_helper_disable_plane,
851         .destroy = tegra_overlay_plane_destroy,
852         .reset = tegra_plane_reset,
853         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
854         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
855 };
856 
857 static const uint32_t tegra_overlay_plane_formats[] = {
858         DRM_FORMAT_XBGR8888,
859         DRM_FORMAT_XRGB8888,
860         DRM_FORMAT_RGB565,
861         DRM_FORMAT_UYVY,
862         DRM_FORMAT_YUYV,
863         DRM_FORMAT_YUV420,
864         DRM_FORMAT_YUV422,
865 };
866 
867 static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
868         .prepare_fb = tegra_plane_prepare_fb,
869         .cleanup_fb = tegra_plane_cleanup_fb,
870         .atomic_check = tegra_plane_atomic_check,
871         .atomic_update = tegra_plane_atomic_update,
872         .atomic_disable = tegra_plane_atomic_disable,
873 };
874 
875 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
876                                                        struct tegra_dc *dc,
877                                                        unsigned int index)
878 {
879         struct tegra_plane *plane;
880         unsigned int num_formats;
881         const u32 *formats;
882         int err;
883 
884         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
885         if (!plane)
886                 return ERR_PTR(-ENOMEM);
887 
888         plane->index = index;
889 
890         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
891         formats = tegra_overlay_plane_formats;
892 
893         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
894                                        &tegra_overlay_plane_funcs, formats,
895                                        num_formats, DRM_PLANE_TYPE_OVERLAY,
896                                        NULL);
897         if (err < 0) {
898                 kfree(plane);
899                 return ERR_PTR(err);
900         }
901 
902         drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
903 
904         return &plane->base;
905 }
906 
907 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
908 {
909         struct drm_plane *plane;
910         unsigned int i;
911 
912         for (i = 0; i < 2; i++) {
913                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
914                 if (IS_ERR(plane))
915                         return PTR_ERR(plane);
916         }
917 
918         return 0;
919 }
920 
921 u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
922 {
923         if (dc->syncpt)
924                 return host1x_syncpt_read(dc->syncpt);
925 
926         /* fallback to software emulated VBLANK counter */
927         return drm_crtc_vblank_count(&dc->base);
928 }
929 
930 void tegra_dc_enable_vblank(struct tegra_dc *dc)
931 {
932         unsigned long value, flags;
933 
934         spin_lock_irqsave(&dc->lock, flags);
935 
936         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
937         value |= VBLANK_INT;
938         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
939 
940         spin_unlock_irqrestore(&dc->lock, flags);
941 }
942 
943 void tegra_dc_disable_vblank(struct tegra_dc *dc)
944 {
945         unsigned long value, flags;
946 
947         spin_lock_irqsave(&dc->lock, flags);
948 
949         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
950         value &= ~VBLANK_INT;
951         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
952 
953         spin_unlock_irqrestore(&dc->lock, flags);
954 }
955 
956 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
957 {
958         struct drm_device *drm = dc->base.dev;
959         struct drm_crtc *crtc = &dc->base;
960         unsigned long flags, base;
961         struct tegra_bo *bo;
962 
963         spin_lock_irqsave(&drm->event_lock, flags);
964 
965         if (!dc->event) {
966                 spin_unlock_irqrestore(&drm->event_lock, flags);
967                 return;
968         }
969 
970         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
971 
972         spin_lock(&dc->lock);
973 
974         /* check if new start address has been latched */
975         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
976         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
977         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
978         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
979 
980         spin_unlock(&dc->lock);
981 
982         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
983                 drm_crtc_send_vblank_event(crtc, dc->event);
984                 drm_crtc_vblank_put(crtc);
985                 dc->event = NULL;
986         }
987 
988         spin_unlock_irqrestore(&drm->event_lock, flags);
989 }
990 
991 static void tegra_dc_destroy(struct drm_crtc *crtc)
992 {
993         drm_crtc_cleanup(crtc);
994 }
995 
996 static void tegra_crtc_reset(struct drm_crtc *crtc)
997 {
998         struct tegra_dc_state *state;
999 
1000         if (crtc->state)
1001                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1002 
1003         kfree(crtc->state);
1004         crtc->state = NULL;
1005 
1006         state = kzalloc(sizeof(*state), GFP_KERNEL);
1007         if (state) {
1008                 crtc->state = &state->base;
1009                 crtc->state->crtc = crtc;
1010         }
1011 
1012         drm_crtc_vblank_reset(crtc);
1013 }
1014 
1015 static struct drm_crtc_state *
1016 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1017 {
1018         struct tegra_dc_state *state = to_dc_state(crtc->state);
1019         struct tegra_dc_state *copy;
1020 
1021         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1022         if (!copy)
1023                 return NULL;
1024 
1025         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1026         copy->clk = state->clk;
1027         copy->pclk = state->pclk;
1028         copy->div = state->div;
1029         copy->planes = state->planes;
1030 
1031         return &copy->base;
1032 }
1033 
1034 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1035                                             struct drm_crtc_state *state)
1036 {
1037         __drm_atomic_helper_crtc_destroy_state(crtc, state);
1038         kfree(state);
1039 }
1040 
1041 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1042         .page_flip = drm_atomic_helper_page_flip,
1043         .set_config = drm_atomic_helper_set_config,
1044         .destroy = tegra_dc_destroy,
1045         .reset = tegra_crtc_reset,
1046         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1047         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1048 };
1049 
1050 static int tegra_dc_set_timings(struct tegra_dc *dc,
1051                                 struct drm_display_mode *mode)
1052 {
1053         unsigned int h_ref_to_sync = 1;
1054         unsigned int v_ref_to_sync = 1;
1055         unsigned long value;
1056 
1057         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058 
1059         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061 
1062         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063                 ((mode->hsync_end - mode->hsync_start) <<  0);
1064         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065 
1066         value = ((mode->vtotal - mode->vsync_end) << 16) |
1067                 ((mode->htotal - mode->hsync_end) <<  0);
1068         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069 
1070         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071                 ((mode->hsync_start - mode->hdisplay) <<  0);
1072         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073 
1074         value = (mode->vdisplay << 16) | mode->hdisplay;
1075         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076 
1077         return 0;
1078 }
1079 
1080 /**
1081  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082  *     state
1083  * @dc: display controller
1084  * @crtc_state: CRTC atomic state
1085  * @clk: parent clock for display controller
1086  * @pclk: pixel clock
1087  * @div: shift clock divider
1088  *
1089  * Returns:
1090  * 0 on success or a negative error-code on failure.
1091  */
1092 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093                                struct drm_crtc_state *crtc_state,
1094                                struct clk *clk, unsigned long pclk,
1095                                unsigned int div)
1096 {
1097         struct tegra_dc_state *state = to_dc_state(crtc_state);
1098 
1099         if (!clk_has_parent(dc->clk, clk))
1100                 return -EINVAL;
1101 
1102         state->clk = clk;
1103         state->pclk = pclk;
1104         state->div = div;
1105 
1106         return 0;
1107 }
1108 
1109 static void tegra_dc_commit_state(struct tegra_dc *dc,
1110                                   struct tegra_dc_state *state)
1111 {
1112         u32 value;
1113         int err;
1114 
1115         err = clk_set_parent(dc->clk, state->clk);
1116         if (err < 0)
1117                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118 
1119         /*
1120          * Outputs may not want to change the parent clock rate. This is only
1121          * relevant to Tegra20 where only a single display PLL is available.
1122          * Since that PLL would typically be used for HDMI, an internal LVDS
1123          * panel would need to be driven by some other clock such as PLL_P
1124          * which is shared with other peripherals. Changing the clock rate
1125          * should therefore be avoided.
1126          */
1127         if (state->pclk > 0) {
1128                 err = clk_set_rate(state->clk, state->pclk);
1129                 if (err < 0)
1130                         dev_err(dc->dev,
1131                                 "failed to set clock rate to %lu Hz\n",
1132                                 state->pclk);
1133         }
1134 
1135         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136                       state->div);
1137         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138 
1139         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1141 }
1142 
1143 static void tegra_dc_stop(struct tegra_dc *dc)
1144 {
1145         u32 value;
1146 
1147         /* stop the display controller */
1148         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1149         value &= ~DISP_CTRL_MODE_MASK;
1150         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1151 
1152         tegra_dc_commit(dc);
1153 }
1154 
1155 static bool tegra_dc_idle(struct tegra_dc *dc)
1156 {
1157         u32 value;
1158 
1159         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1160 
1161         return (value & DISP_CTRL_MODE_MASK) == 0;
1162 }
1163 
1164 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1165 {
1166         timeout = jiffies + msecs_to_jiffies(timeout);
1167 
1168         while (time_before(jiffies, timeout)) {
1169                 if (tegra_dc_idle(dc))
1170                         return 0;
1171 
1172                 usleep_range(1000, 2000);
1173         }
1174 
1175         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1176         return -ETIMEDOUT;
1177 }
1178 
1179 static void tegra_crtc_disable(struct drm_crtc *crtc)
1180 {
1181         struct tegra_dc *dc = to_tegra_dc(crtc);
1182         u32 value;
1183 
1184         if (!tegra_dc_idle(dc)) {
1185                 tegra_dc_stop(dc);
1186 
1187                 /*
1188                  * Ignore the return value, there isn't anything useful to do
1189                  * in case this fails.
1190                  */
1191                 tegra_dc_wait_idle(dc, 100);
1192         }
1193 
1194         /*
1195          * This should really be part of the RGB encoder driver, but clearing
1196          * these bits has the side-effect of stopping the display controller.
1197          * When that happens no VBLANK interrupts will be raised. At the same
1198          * time the encoder is disabled before the display controller, so the
1199          * above code is always going to timeout waiting for the controller
1200          * to go idle.
1201          *
1202          * Given the close coupling between the RGB encoder and the display
1203          * controller doing it here is still kind of okay. None of the other
1204          * encoder drivers require these bits to be cleared.
1205          *
1206          * XXX: Perhaps given that the display controller is switched off at
1207          * this point anyway maybe clearing these bits isn't even useful for
1208          * the RGB encoder?
1209          */
1210         if (dc->rgb) {
1211                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1212                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1213                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1214                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1215         }
1216 
1217         tegra_dc_stats_reset(&dc->stats);
1218         drm_crtc_vblank_off(crtc);
1219 }
1220 
1221 static void tegra_crtc_enable(struct drm_crtc *crtc)
1222 {
1223         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1224         struct tegra_dc_state *state = to_dc_state(crtc->state);
1225         struct tegra_dc *dc = to_tegra_dc(crtc);
1226         u32 value;
1227 
1228         tegra_dc_commit_state(dc, state);
1229 
1230         /* program display mode */
1231         tegra_dc_set_timings(dc, mode);
1232 
1233         /* interlacing isn't supported yet, so disable it */
1234         if (dc->soc->supports_interlacing) {
1235                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236                 value &= ~INTERLACE_ENABLE;
1237                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1238         }
1239 
1240         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241         value &= ~DISP_CTRL_MODE_MASK;
1242         value |= DISP_CTRL_MODE_C_DISPLAY;
1243         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1244 
1245         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1249 
1250         tegra_dc_commit(dc);
1251 
1252         drm_crtc_vblank_on(crtc);
1253 }
1254 
1255 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1256                                    struct drm_crtc_state *state)
1257 {
1258         return 0;
1259 }
1260 
1261 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1262                                     struct drm_crtc_state *old_crtc_state)
1263 {
1264         struct tegra_dc *dc = to_tegra_dc(crtc);
1265 
1266         if (crtc->state->event) {
1267                 crtc->state->event->pipe = drm_crtc_index(crtc);
1268 
1269                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1270 
1271                 dc->event = crtc->state->event;
1272                 crtc->state->event = NULL;
1273         }
1274 }
1275 
1276 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1277                                     struct drm_crtc_state *old_crtc_state)
1278 {
1279         struct tegra_dc_state *state = to_dc_state(crtc->state);
1280         struct tegra_dc *dc = to_tegra_dc(crtc);
1281 
1282         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1283         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1284 }
1285 
1286 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1287         .disable = tegra_crtc_disable,
1288         .enable = tegra_crtc_enable,
1289         .atomic_check = tegra_crtc_atomic_check,
1290         .atomic_begin = tegra_crtc_atomic_begin,
1291         .atomic_flush = tegra_crtc_atomic_flush,
1292 };
1293 
1294 static irqreturn_t tegra_dc_irq(int irq, void *data)
1295 {
1296         struct tegra_dc *dc = data;
1297         unsigned long status;
1298 
1299         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1300         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1301 
1302         if (status & FRAME_END_INT) {
1303                 /*
1304                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1305                 */
1306                 dc->stats.frames++;
1307         }
1308 
1309         if (status & VBLANK_INT) {
1310                 /*
1311                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1312                 */
1313                 drm_crtc_handle_vblank(&dc->base);
1314                 tegra_dc_finish_page_flip(dc);
1315                 dc->stats.vblank++;
1316         }
1317 
1318         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1319                 /*
1320                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1321                 */
1322                 dc->stats.underflow++;
1323         }
1324 
1325         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1326                 /*
1327                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1328                 */
1329                 dc->stats.overflow++;
1330         }
1331 
1332         return IRQ_HANDLED;
1333 }
1334 
1335 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1336 {
1337         struct drm_info_node *node = s->private;
1338         struct tegra_dc *dc = node->info_ent->data;
1339         int err = 0;
1340 
1341         drm_modeset_lock_crtc(&dc->base, NULL);
1342 
1343         if (!dc->base.state->active) {
1344                 err = -EBUSY;
1345                 goto unlock;
1346         }
1347 
1348 #define DUMP_REG(name)                                          \
1349         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1350                    tegra_dc_readl(dc, name))
1351 
1352         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1353         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1354         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1355         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1356         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1357         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1358         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1359         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1360         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1361         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1362         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1363         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1364         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1365         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1366         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1367         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1368         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1369         DUMP_REG(DC_CMD_INT_STATUS);
1370         DUMP_REG(DC_CMD_INT_MASK);
1371         DUMP_REG(DC_CMD_INT_ENABLE);
1372         DUMP_REG(DC_CMD_INT_TYPE);
1373         DUMP_REG(DC_CMD_INT_POLARITY);
1374         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1375         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1376         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1377         DUMP_REG(DC_CMD_STATE_ACCESS);
1378         DUMP_REG(DC_CMD_STATE_CONTROL);
1379         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1380         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1381         DUMP_REG(DC_COM_CRC_CONTROL);
1382         DUMP_REG(DC_COM_CRC_CHECKSUM);
1383         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1384         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1385         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1386         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1387         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1388         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1389         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1390         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1391         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1392         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1393         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1394         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1395         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1396         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1397         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1398         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1399         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1400         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1401         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1402         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1403         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1404         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1405         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1406         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1407         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1408         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1409         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1410         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1411         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1412         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1413         DUMP_REG(DC_COM_SPI_CONTROL);
1414         DUMP_REG(DC_COM_SPI_START_BYTE);
1415         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1416         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1417         DUMP_REG(DC_COM_HSPI_CS_DC);
1418         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1419         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1420         DUMP_REG(DC_COM_GPIO_CTRL);
1421         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1422         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1423         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1424         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1425         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1426         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1427         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1428         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1429         DUMP_REG(DC_DISP_REF_TO_SYNC);
1430         DUMP_REG(DC_DISP_SYNC_WIDTH);
1431         DUMP_REG(DC_DISP_BACK_PORCH);
1432         DUMP_REG(DC_DISP_ACTIVE);
1433         DUMP_REG(DC_DISP_FRONT_PORCH);
1434         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1435         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1436         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1437         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1438         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1439         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1440         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1441         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1442         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1443         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1444         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1445         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1446         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1447         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1448         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1449         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1450         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1451         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1452         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1453         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1454         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1455         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1456         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1457         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1458         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1459         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1460         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1461         DUMP_REG(DC_DISP_M0_CONTROL);
1462         DUMP_REG(DC_DISP_M1_CONTROL);
1463         DUMP_REG(DC_DISP_DI_CONTROL);
1464         DUMP_REG(DC_DISP_PP_CONTROL);
1465         DUMP_REG(DC_DISP_PP_SELECT_A);
1466         DUMP_REG(DC_DISP_PP_SELECT_B);
1467         DUMP_REG(DC_DISP_PP_SELECT_C);
1468         DUMP_REG(DC_DISP_PP_SELECT_D);
1469         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1470         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1471         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1472         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1473         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1474         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1475         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1476         DUMP_REG(DC_DISP_BORDER_COLOR);
1477         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1478         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1479         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1480         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1481         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1482         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1483         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1484         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1485         DUMP_REG(DC_DISP_CURSOR_POSITION);
1486         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1487         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1488         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1489         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1490         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1491         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1492         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1493         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1494         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1495         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1496         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1497         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1498         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1499         DUMP_REG(DC_DISP_SD_CONTROL);
1500         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1501         DUMP_REG(DC_DISP_SD_LUT(0));
1502         DUMP_REG(DC_DISP_SD_LUT(1));
1503         DUMP_REG(DC_DISP_SD_LUT(2));
1504         DUMP_REG(DC_DISP_SD_LUT(3));
1505         DUMP_REG(DC_DISP_SD_LUT(4));
1506         DUMP_REG(DC_DISP_SD_LUT(5));
1507         DUMP_REG(DC_DISP_SD_LUT(6));
1508         DUMP_REG(DC_DISP_SD_LUT(7));
1509         DUMP_REG(DC_DISP_SD_LUT(8));
1510         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1511         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1512         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1513         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1514         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1515         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1516         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1517         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1518         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1519         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1520         DUMP_REG(DC_DISP_SD_BL_TF(0));
1521         DUMP_REG(DC_DISP_SD_BL_TF(1));
1522         DUMP_REG(DC_DISP_SD_BL_TF(2));
1523         DUMP_REG(DC_DISP_SD_BL_TF(3));
1524         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1525         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1526         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1527         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1528         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1529         DUMP_REG(DC_WIN_WIN_OPTIONS);
1530         DUMP_REG(DC_WIN_BYTE_SWAP);
1531         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1532         DUMP_REG(DC_WIN_COLOR_DEPTH);
1533         DUMP_REG(DC_WIN_POSITION);
1534         DUMP_REG(DC_WIN_SIZE);
1535         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1536         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1537         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1538         DUMP_REG(DC_WIN_DDA_INC);
1539         DUMP_REG(DC_WIN_LINE_STRIDE);
1540         DUMP_REG(DC_WIN_BUF_STRIDE);
1541         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1542         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1543         DUMP_REG(DC_WIN_DV_CONTROL);
1544         DUMP_REG(DC_WIN_BLEND_NOKEY);
1545         DUMP_REG(DC_WIN_BLEND_1WIN);
1546         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1547         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1548         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1549         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1550         DUMP_REG(DC_WINBUF_START_ADDR);
1551         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1552         DUMP_REG(DC_WINBUF_START_ADDR_U);
1553         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1554         DUMP_REG(DC_WINBUF_START_ADDR_V);
1555         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1556         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1557         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1558         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1559         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1560         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1561         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1562         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1563         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1564 
1565 #undef DUMP_REG
1566 
1567 unlock:
1568         drm_modeset_unlock_crtc(&dc->base);
1569         return err;
1570 }
1571 
1572 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1573 {
1574         struct drm_info_node *node = s->private;
1575         struct tegra_dc *dc = node->info_ent->data;
1576         int err = 0;
1577         u32 value;
1578 
1579         drm_modeset_lock_crtc(&dc->base, NULL);
1580 
1581         if (!dc->base.state->active) {
1582                 err = -EBUSY;
1583                 goto unlock;
1584         }
1585 
1586         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1587         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1588         tegra_dc_commit(dc);
1589 
1590         drm_crtc_wait_one_vblank(&dc->base);
1591         drm_crtc_wait_one_vblank(&dc->base);
1592 
1593         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1594         seq_printf(s, "%08x\n", value);
1595 
1596         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1597 
1598 unlock:
1599         drm_modeset_unlock_crtc(&dc->base);
1600         return err;
1601 }
1602 
1603 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1604 {
1605         struct drm_info_node *node = s->private;
1606         struct tegra_dc *dc = node->info_ent->data;
1607 
1608         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1609         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1610         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1611         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1612 
1613         return 0;
1614 }
1615 
1616 static struct drm_info_list debugfs_files[] = {
1617         { "regs", tegra_dc_show_regs, 0, NULL },
1618         { "crc", tegra_dc_show_crc, 0, NULL },
1619         { "stats", tegra_dc_show_stats, 0, NULL },
1620 };
1621 
1622 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1623 {
1624         unsigned int i;
1625         char *name;
1626         int err;
1627 
1628         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1629         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1630         kfree(name);
1631 
1632         if (!dc->debugfs)
1633                 return -ENOMEM;
1634 
1635         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1636                                     GFP_KERNEL);
1637         if (!dc->debugfs_files) {
1638                 err = -ENOMEM;
1639                 goto remove;
1640         }
1641 
1642         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1643                 dc->debugfs_files[i].data = dc;
1644 
1645         err = drm_debugfs_create_files(dc->debugfs_files,
1646                                        ARRAY_SIZE(debugfs_files),
1647                                        dc->debugfs, minor);
1648         if (err < 0)
1649                 goto free;
1650 
1651         dc->minor = minor;
1652 
1653         return 0;
1654 
1655 free:
1656         kfree(dc->debugfs_files);
1657         dc->debugfs_files = NULL;
1658 remove:
1659         debugfs_remove(dc->debugfs);
1660         dc->debugfs = NULL;
1661 
1662         return err;
1663 }
1664 
1665 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1666 {
1667         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1668                                  dc->minor);
1669         dc->minor = NULL;
1670 
1671         kfree(dc->debugfs_files);
1672         dc->debugfs_files = NULL;
1673 
1674         debugfs_remove(dc->debugfs);
1675         dc->debugfs = NULL;
1676 
1677         return 0;
1678 }
1679 
1680 static int tegra_dc_init(struct host1x_client *client)
1681 {
1682         struct drm_device *drm = dev_get_drvdata(client->parent);
1683         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1684         struct tegra_dc *dc = host1x_client_to_dc(client);
1685         struct tegra_drm *tegra = drm->dev_private;
1686         struct drm_plane *primary = NULL;
1687         struct drm_plane *cursor = NULL;
1688         u32 value;
1689         int err;
1690 
1691         dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1692         if (!dc->syncpt)
1693                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1694 
1695         if (tegra->domain) {
1696                 err = iommu_attach_device(tegra->domain, dc->dev);
1697                 if (err < 0) {
1698                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1699                                 err);
1700                         return err;
1701                 }
1702 
1703                 dc->domain = tegra->domain;
1704         }
1705 
1706         primary = tegra_dc_primary_plane_create(drm, dc);
1707         if (IS_ERR(primary)) {
1708                 err = PTR_ERR(primary);
1709                 goto cleanup;
1710         }
1711 
1712         if (dc->soc->supports_cursor) {
1713                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1714                 if (IS_ERR(cursor)) {
1715                         err = PTR_ERR(cursor);
1716                         goto cleanup;
1717                 }
1718         }
1719 
1720         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1721                                         &tegra_crtc_funcs, NULL);
1722         if (err < 0)
1723                 goto cleanup;
1724 
1725         drm_mode_crtc_set_gamma_size(&dc->base, 256);
1726         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1727 
1728         /*
1729          * Keep track of the minimum pitch alignment across all display
1730          * controllers.
1731          */
1732         if (dc->soc->pitch_align > tegra->pitch_align)
1733                 tegra->pitch_align = dc->soc->pitch_align;
1734 
1735         err = tegra_dc_rgb_init(drm, dc);
1736         if (err < 0 && err != -ENODEV) {
1737                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1738                 goto cleanup;
1739         }
1740 
1741         err = tegra_dc_add_planes(drm, dc);
1742         if (err < 0)
1743                 goto cleanup;
1744 
1745         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1746                 err = tegra_dc_debugfs_init(dc, drm->primary);
1747                 if (err < 0)
1748                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1749         }
1750 
1751         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1752                                dev_name(dc->dev), dc);
1753         if (err < 0) {
1754                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1755                         err);
1756                 goto cleanup;
1757         }
1758 
1759         /* initialize display controller */
1760         if (dc->syncpt) {
1761                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1762 
1763                 value = SYNCPT_CNTRL_NO_STALL;
1764                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1765 
1766                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1767                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1768         }
1769 
1770         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1771                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1772         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1773 
1774         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1775                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1776         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1777 
1778         /* initialize timer */
1779         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1780                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1781         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1782 
1783         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1784                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1785         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1786 
1787         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1788                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1789         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1790 
1791         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1792                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1793         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1794 
1795         if (dc->soc->supports_border_color)
1796                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1797 
1798         tegra_dc_stats_reset(&dc->stats);
1799 
1800         return 0;
1801 
1802 cleanup:
1803         if (cursor)
1804                 drm_plane_cleanup(cursor);
1805 
1806         if (primary)
1807                 drm_plane_cleanup(primary);
1808 
1809         if (tegra->domain) {
1810                 iommu_detach_device(tegra->domain, dc->dev);
1811                 dc->domain = NULL;
1812         }
1813 
1814         return err;
1815 }
1816 
1817 static int tegra_dc_exit(struct host1x_client *client)
1818 {
1819         struct tegra_dc *dc = host1x_client_to_dc(client);
1820         int err;
1821 
1822         devm_free_irq(dc->dev, dc->irq, dc);
1823 
1824         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1825                 err = tegra_dc_debugfs_exit(dc);
1826                 if (err < 0)
1827                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1828         }
1829 
1830         err = tegra_dc_rgb_exit(dc);
1831         if (err) {
1832                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1833                 return err;
1834         }
1835 
1836         if (dc->domain) {
1837                 iommu_detach_device(dc->domain, dc->dev);
1838                 dc->domain = NULL;
1839         }
1840 
1841         host1x_syncpt_free(dc->syncpt);
1842 
1843         return 0;
1844 }
1845 
1846 static const struct host1x_client_ops dc_client_ops = {
1847         .init = tegra_dc_init,
1848         .exit = tegra_dc_exit,
1849 };
1850 
1851 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1852         .supports_border_color = true,
1853         .supports_interlacing = false,
1854         .supports_cursor = false,
1855         .supports_block_linear = false,
1856         .pitch_align = 8,
1857         .has_powergate = false,
1858 };
1859 
1860 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1861         .supports_border_color = true,
1862         .supports_interlacing = false,
1863         .supports_cursor = false,
1864         .supports_block_linear = false,
1865         .pitch_align = 8,
1866         .has_powergate = false,
1867 };
1868 
1869 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1870         .supports_border_color = true,
1871         .supports_interlacing = false,
1872         .supports_cursor = false,
1873         .supports_block_linear = false,
1874         .pitch_align = 64,
1875         .has_powergate = true,
1876 };
1877 
1878 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1879         .supports_border_color = false,
1880         .supports_interlacing = true,
1881         .supports_cursor = true,
1882         .supports_block_linear = true,
1883         .pitch_align = 64,
1884         .has_powergate = true,
1885 };
1886 
1887 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1888         .supports_border_color = false,
1889         .supports_interlacing = true,
1890         .supports_cursor = true,
1891         .supports_block_linear = true,
1892         .pitch_align = 64,
1893         .has_powergate = true,
1894 };
1895 
1896 static const struct of_device_id tegra_dc_of_match[] = {
1897         {
1898                 .compatible = "nvidia,tegra210-dc",
1899                 .data = &tegra210_dc_soc_info,
1900         }, {
1901                 .compatible = "nvidia,tegra124-dc",
1902                 .data = &tegra124_dc_soc_info,
1903         }, {
1904                 .compatible = "nvidia,tegra114-dc",
1905                 .data = &tegra114_dc_soc_info,
1906         }, {
1907                 .compatible = "nvidia,tegra30-dc",
1908                 .data = &tegra30_dc_soc_info,
1909         }, {
1910                 .compatible = "nvidia,tegra20-dc",
1911                 .data = &tegra20_dc_soc_info,
1912         }, {
1913                 /* sentinel */
1914         }
1915 };
1916 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1917 
1918 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1919 {
1920         struct device_node *np;
1921         u32 value = 0;
1922         int err;
1923 
1924         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1925         if (err < 0) {
1926                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1927 
1928                 /*
1929                  * If the nvidia,head property isn't present, try to find the
1930                  * correct head number by looking up the position of this
1931                  * display controller's node within the device tree. Assuming
1932                  * that the nodes are ordered properly in the DTS file and
1933                  * that the translation into a flattened device tree blob
1934                  * preserves that ordering this will actually yield the right
1935                  * head number.
1936                  *
1937                  * If those assumptions don't hold, this will still work for
1938                  * cases where only a single display controller is used.
1939                  */
1940                 for_each_matching_node(np, tegra_dc_of_match) {
1941                         if (np == dc->dev->of_node) {
1942                                 of_node_put(np);
1943                                 break;
1944                         }
1945 
1946                         value++;
1947                 }
1948         }
1949 
1950         dc->pipe = value;
1951 
1952         return 0;
1953 }
1954 
1955 static int tegra_dc_probe(struct platform_device *pdev)
1956 {
1957         const struct of_device_id *id;
1958         struct resource *regs;
1959         struct tegra_dc *dc;
1960         int err;
1961 
1962         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1963         if (!dc)
1964                 return -ENOMEM;
1965 
1966         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1967         if (!id)
1968                 return -ENODEV;
1969 
1970         spin_lock_init(&dc->lock);
1971         INIT_LIST_HEAD(&dc->list);
1972         dc->dev = &pdev->dev;
1973         dc->soc = id->data;
1974 
1975         err = tegra_dc_parse_dt(dc);
1976         if (err < 0)
1977                 return err;
1978 
1979         dc->clk = devm_clk_get(&pdev->dev, NULL);
1980         if (IS_ERR(dc->clk)) {
1981                 dev_err(&pdev->dev, "failed to get clock\n");
1982                 return PTR_ERR(dc->clk);
1983         }
1984 
1985         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1986         if (IS_ERR(dc->rst)) {
1987                 dev_err(&pdev->dev, "failed to get reset\n");
1988                 return PTR_ERR(dc->rst);
1989         }
1990 
1991         if (dc->soc->has_powergate) {
1992                 if (dc->pipe == 0)
1993                         dc->powergate = TEGRA_POWERGATE_DIS;
1994                 else
1995                         dc->powergate = TEGRA_POWERGATE_DISB;
1996 
1997                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1998                                                         dc->rst);
1999                 if (err < 0) {
2000                         dev_err(&pdev->dev, "failed to power partition: %d\n",
2001                                 err);
2002                         return err;
2003                 }
2004         } else {
2005                 err = clk_prepare_enable(dc->clk);
2006                 if (err < 0) {
2007                         dev_err(&pdev->dev, "failed to enable clock: %d\n",
2008                                 err);
2009                         return err;
2010                 }
2011 
2012                 err = reset_control_deassert(dc->rst);
2013                 if (err < 0) {
2014                         dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2015                                 err);
2016                         return err;
2017                 }
2018         }
2019 
2020         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2022         if (IS_ERR(dc->regs))
2023                 return PTR_ERR(dc->regs);
2024 
2025         dc->irq = platform_get_irq(pdev, 0);
2026         if (dc->irq < 0) {
2027                 dev_err(&pdev->dev, "failed to get IRQ\n");
2028                 return -ENXIO;
2029         }
2030 
2031         INIT_LIST_HEAD(&dc->client.list);
2032         dc->client.ops = &dc_client_ops;
2033         dc->client.dev = &pdev->dev;
2034 
2035         err = tegra_dc_rgb_probe(dc);
2036         if (err < 0 && err != -ENODEV) {
2037                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2038                 return err;
2039         }
2040 
2041         err = host1x_client_register(&dc->client);
2042         if (err < 0) {
2043                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2044                         err);
2045                 return err;
2046         }
2047 
2048         platform_set_drvdata(pdev, dc);
2049 
2050         return 0;
2051 }
2052 
2053 static int tegra_dc_remove(struct platform_device *pdev)
2054 {
2055         struct tegra_dc *dc = platform_get_drvdata(pdev);
2056         int err;
2057 
2058         err = host1x_client_unregister(&dc->client);
2059         if (err < 0) {
2060                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2061                         err);
2062                 return err;
2063         }
2064 
2065         err = tegra_dc_rgb_remove(dc);
2066         if (err < 0) {
2067                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2068                 return err;
2069         }
2070 
2071         reset_control_assert(dc->rst);
2072 
2073         if (dc->soc->has_powergate)
2074                 tegra_powergate_power_off(dc->powergate);
2075 
2076         clk_disable_unprepare(dc->clk);
2077 
2078         return 0;
2079 }
2080 
2081 struct platform_driver tegra_dc_driver = {
2082         .driver = {
2083                 .name = "tegra-dc",
2084                 .of_match_table = tegra_dc_of_match,
2085         },
2086         .probe = tegra_dc_probe,
2087         .remove = tegra_dc_remove,
2088 };
2089 

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