Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_atomic.h>
 41 #include <drm/drm_atomic_helper.h>
 42 #include <drm/drm_dp_helper.h>
 43 #include <drm/drm_crtc_helper.h>
 44 #include <drm/drm_plane_helper.h>
 45 #include <drm/drm_rect.h>
 46 #include <linux/dma_remapping.h>
 47 
 48 /* Primary plane formats supported by all gen */
 49 #define COMMON_PRIMARY_FORMATS \
 50         DRM_FORMAT_C8, \
 51         DRM_FORMAT_RGB565, \
 52         DRM_FORMAT_XRGB8888, \
 53         DRM_FORMAT_ARGB8888
 54 
 55 /* Primary plane formats for gen <= 3 */
 56 static const uint32_t intel_primary_formats_gen2[] = {
 57         COMMON_PRIMARY_FORMATS,
 58         DRM_FORMAT_XRGB1555,
 59         DRM_FORMAT_ARGB1555,
 60 };
 61 
 62 /* Primary plane formats for gen >= 4 */
 63 static const uint32_t intel_primary_formats_gen4[] = {
 64         COMMON_PRIMARY_FORMATS, \
 65         DRM_FORMAT_XBGR8888,
 66         DRM_FORMAT_ABGR8888,
 67         DRM_FORMAT_XRGB2101010,
 68         DRM_FORMAT_ARGB2101010,
 69         DRM_FORMAT_XBGR2101010,
 70         DRM_FORMAT_ABGR2101010,
 71 };
 72 
 73 /* Cursor formats */
 74 static const uint32_t intel_cursor_formats[] = {
 75         DRM_FORMAT_ARGB8888,
 76 };
 77 
 78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 79 
 80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 81                                 struct intel_crtc_state *pipe_config);
 82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 83                                    struct intel_crtc_state *pipe_config);
 84 
 85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 86                           int x, int y, struct drm_framebuffer *old_fb);
 87 static int intel_framebuffer_init(struct drm_device *dev,
 88                                   struct intel_framebuffer *ifb,
 89                                   struct drm_mode_fb_cmd2 *mode_cmd,
 90                                   struct drm_i915_gem_object *obj);
 91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 94                                          struct intel_link_m_n *m_n,
 95                                          struct intel_link_m_n *m2_n2);
 96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100                             const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102                             const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108         if (!connector->mst_port)
109                 return connector->encoder;
110         else
111                 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113 
114 typedef struct {
115         int     min, max;
116 } intel_range_t;
117 
118 typedef struct {
119         int     dot_limit;
120         int     p2_slow, p2_fast;
121 } intel_p2_t;
122 
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
126         intel_p2_t          p2;
127 };
128 
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132         struct drm_i915_private *dev_priv = dev->dev_private;
133 
134         WARN_ON(!HAS_PCH_SPLIT(dev));
135 
136         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138 
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142         if (IS_GEN5(dev)) {
143                 struct drm_i915_private *dev_priv = dev->dev_private;
144                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145         } else
146                 return 27;
147 }
148 
149 static const intel_limit_t intel_limits_i8xx_dac = {
150         .dot = { .min = 25000, .max = 350000 },
151         .vco = { .min = 908000, .max = 1512000 },
152         .n = { .min = 2, .max = 16 },
153         .m = { .min = 96, .max = 140 },
154         .m1 = { .min = 18, .max = 26 },
155         .m2 = { .min = 6, .max = 16 },
156         .p = { .min = 4, .max = 128 },
157         .p1 = { .min = 2, .max = 33 },
158         .p2 = { .dot_limit = 165000,
159                 .p2_slow = 4, .p2_fast = 2 },
160 };
161 
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163         .dot = { .min = 25000, .max = 350000 },
164         .vco = { .min = 908000, .max = 1512000 },
165         .n = { .min = 2, .max = 16 },
166         .m = { .min = 96, .max = 140 },
167         .m1 = { .min = 18, .max = 26 },
168         .m2 = { .min = 6, .max = 16 },
169         .p = { .min = 4, .max = 128 },
170         .p1 = { .min = 2, .max = 33 },
171         .p2 = { .dot_limit = 165000,
172                 .p2_slow = 4, .p2_fast = 4 },
173 };
174 
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176         .dot = { .min = 25000, .max = 350000 },
177         .vco = { .min = 908000, .max = 1512000 },
178         .n = { .min = 2, .max = 16 },
179         .m = { .min = 96, .max = 140 },
180         .m1 = { .min = 18, .max = 26 },
181         .m2 = { .min = 6, .max = 16 },
182         .p = { .min = 4, .max = 128 },
183         .p1 = { .min = 1, .max = 6 },
184         .p2 = { .dot_limit = 165000,
185                 .p2_slow = 14, .p2_fast = 7 },
186 };
187 
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189         .dot = { .min = 20000, .max = 400000 },
190         .vco = { .min = 1400000, .max = 2800000 },
191         .n = { .min = 1, .max = 6 },
192         .m = { .min = 70, .max = 120 },
193         .m1 = { .min = 8, .max = 18 },
194         .m2 = { .min = 3, .max = 7 },
195         .p = { .min = 5, .max = 80 },
196         .p1 = { .min = 1, .max = 8 },
197         .p2 = { .dot_limit = 200000,
198                 .p2_slow = 10, .p2_fast = 5 },
199 };
200 
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202         .dot = { .min = 20000, .max = 400000 },
203         .vco = { .min = 1400000, .max = 2800000 },
204         .n = { .min = 1, .max = 6 },
205         .m = { .min = 70, .max = 120 },
206         .m1 = { .min = 8, .max = 18 },
207         .m2 = { .min = 3, .max = 7 },
208         .p = { .min = 7, .max = 98 },
209         .p1 = { .min = 1, .max = 8 },
210         .p2 = { .dot_limit = 112000,
211                 .p2_slow = 14, .p2_fast = 7 },
212 };
213 
214 
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216         .dot = { .min = 25000, .max = 270000 },
217         .vco = { .min = 1750000, .max = 3500000},
218         .n = { .min = 1, .max = 4 },
219         .m = { .min = 104, .max = 138 },
220         .m1 = { .min = 17, .max = 23 },
221         .m2 = { .min = 5, .max = 11 },
222         .p = { .min = 10, .max = 30 },
223         .p1 = { .min = 1, .max = 3},
224         .p2 = { .dot_limit = 270000,
225                 .p2_slow = 10,
226                 .p2_fast = 10
227         },
228 };
229 
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231         .dot = { .min = 22000, .max = 400000 },
232         .vco = { .min = 1750000, .max = 3500000},
233         .n = { .min = 1, .max = 4 },
234         .m = { .min = 104, .max = 138 },
235         .m1 = { .min = 16, .max = 23 },
236         .m2 = { .min = 5, .max = 11 },
237         .p = { .min = 5, .max = 80 },
238         .p1 = { .min = 1, .max = 8},
239         .p2 = { .dot_limit = 165000,
240                 .p2_slow = 10, .p2_fast = 5 },
241 };
242 
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244         .dot = { .min = 20000, .max = 115000 },
245         .vco = { .min = 1750000, .max = 3500000 },
246         .n = { .min = 1, .max = 3 },
247         .m = { .min = 104, .max = 138 },
248         .m1 = { .min = 17, .max = 23 },
249         .m2 = { .min = 5, .max = 11 },
250         .p = { .min = 28, .max = 112 },
251         .p1 = { .min = 2, .max = 8 },
252         .p2 = { .dot_limit = 0,
253                 .p2_slow = 14, .p2_fast = 14
254         },
255 };
256 
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258         .dot = { .min = 80000, .max = 224000 },
259         .vco = { .min = 1750000, .max = 3500000 },
260         .n = { .min = 1, .max = 3 },
261         .m = { .min = 104, .max = 138 },
262         .m1 = { .min = 17, .max = 23 },
263         .m2 = { .min = 5, .max = 11 },
264         .p = { .min = 14, .max = 42 },
265         .p1 = { .min = 2, .max = 6 },
266         .p2 = { .dot_limit = 0,
267                 .p2_slow = 7, .p2_fast = 7
268         },
269 };
270 
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272         .dot = { .min = 20000, .max = 400000},
273         .vco = { .min = 1700000, .max = 3500000 },
274         /* Pineview's Ncounter is a ring counter */
275         .n = { .min = 3, .max = 6 },
276         .m = { .min = 2, .max = 256 },
277         /* Pineview only has one combined m divider, which we treat as m2. */
278         .m1 = { .min = 0, .max = 0 },
279         .m2 = { .min = 0, .max = 254 },
280         .p = { .min = 5, .max = 80 },
281         .p1 = { .min = 1, .max = 8 },
282         .p2 = { .dot_limit = 200000,
283                 .p2_slow = 10, .p2_fast = 5 },
284 };
285 
286 static const intel_limit_t intel_limits_pineview_lvds = {
287         .dot = { .min = 20000, .max = 400000 },
288         .vco = { .min = 1700000, .max = 3500000 },
289         .n = { .min = 3, .max = 6 },
290         .m = { .min = 2, .max = 256 },
291         .m1 = { .min = 0, .max = 0 },
292         .m2 = { .min = 0, .max = 254 },
293         .p = { .min = 7, .max = 112 },
294         .p1 = { .min = 1, .max = 8 },
295         .p2 = { .dot_limit = 112000,
296                 .p2_slow = 14, .p2_fast = 14 },
297 };
298 
299 /* Ironlake / Sandybridge
300  *
301  * We calculate clock using (register_value + 2) for N/M1/M2, so here
302  * the range value for them is (actual_value - 2).
303  */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305         .dot = { .min = 25000, .max = 350000 },
306         .vco = { .min = 1760000, .max = 3510000 },
307         .n = { .min = 1, .max = 5 },
308         .m = { .min = 79, .max = 127 },
309         .m1 = { .min = 12, .max = 22 },
310         .m2 = { .min = 5, .max = 9 },
311         .p = { .min = 5, .max = 80 },
312         .p1 = { .min = 1, .max = 8 },
313         .p2 = { .dot_limit = 225000,
314                 .p2_slow = 10, .p2_fast = 5 },
315 };
316 
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318         .dot = { .min = 25000, .max = 350000 },
319         .vco = { .min = 1760000, .max = 3510000 },
320         .n = { .min = 1, .max = 3 },
321         .m = { .min = 79, .max = 118 },
322         .m1 = { .min = 12, .max = 22 },
323         .m2 = { .min = 5, .max = 9 },
324         .p = { .min = 28, .max = 112 },
325         .p1 = { .min = 2, .max = 8 },
326         .p2 = { .dot_limit = 225000,
327                 .p2_slow = 14, .p2_fast = 14 },
328 };
329 
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331         .dot = { .min = 25000, .max = 350000 },
332         .vco = { .min = 1760000, .max = 3510000 },
333         .n = { .min = 1, .max = 3 },
334         .m = { .min = 79, .max = 127 },
335         .m1 = { .min = 12, .max = 22 },
336         .m2 = { .min = 5, .max = 9 },
337         .p = { .min = 14, .max = 56 },
338         .p1 = { .min = 2, .max = 8 },
339         .p2 = { .dot_limit = 225000,
340                 .p2_slow = 7, .p2_fast = 7 },
341 };
342 
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345         .dot = { .min = 25000, .max = 350000 },
346         .vco = { .min = 1760000, .max = 3510000 },
347         .n = { .min = 1, .max = 2 },
348         .m = { .min = 79, .max = 126 },
349         .m1 = { .min = 12, .max = 22 },
350         .m2 = { .min = 5, .max = 9 },
351         .p = { .min = 28, .max = 112 },
352         .p1 = { .min = 2, .max = 8 },
353         .p2 = { .dot_limit = 225000,
354                 .p2_slow = 14, .p2_fast = 14 },
355 };
356 
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358         .dot = { .min = 25000, .max = 350000 },
359         .vco = { .min = 1760000, .max = 3510000 },
360         .n = { .min = 1, .max = 3 },
361         .m = { .min = 79, .max = 126 },
362         .m1 = { .min = 12, .max = 22 },
363         .m2 = { .min = 5, .max = 9 },
364         .p = { .min = 14, .max = 42 },
365         .p1 = { .min = 2, .max = 6 },
366         .p2 = { .dot_limit = 225000,
367                 .p2_slow = 7, .p2_fast = 7 },
368 };
369 
370 static const intel_limit_t intel_limits_vlv = {
371          /*
372           * These are the data rate limits (measured in fast clocks)
373           * since those are the strictest limits we have. The fast
374           * clock and actual rate limits are more relaxed, so checking
375           * them would make no difference.
376           */
377         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378         .vco = { .min = 4000000, .max = 6000000 },
379         .n = { .min = 1, .max = 7 },
380         .m1 = { .min = 2, .max = 3 },
381         .m2 = { .min = 11, .max = 156 },
382         .p1 = { .min = 2, .max = 3 },
383         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385 
386 static const intel_limit_t intel_limits_chv = {
387         /*
388          * These are the data rate limits (measured in fast clocks)
389          * since those are the strictest limits we have.  The fast
390          * clock and actual rate limits are more relaxed, so checking
391          * them would make no difference.
392          */
393         .dot = { .min = 25000 * 5, .max = 540000 * 5},
394         .vco = { .min = 4860000, .max = 6700000 },
395         .n = { .min = 1, .max = 1 },
396         .m1 = { .min = 2, .max = 2 },
397         .m2 = { .min = 24 << 22, .max = 175 << 22 },
398         .p1 = { .min = 2, .max = 4 },
399         .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401 
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404         clock->m = clock->m1 * clock->m2;
405         clock->p = clock->p1 * clock->p2;
406         if (WARN_ON(clock->n == 0 || clock->p == 0))
407                 return;
408         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411 
412 /**
413  * Returns whether any output on the specified pipe is of the specified type
414  */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417         struct drm_device *dev = crtc->base.dev;
418         struct intel_encoder *encoder;
419 
420         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421                 if (encoder->type == type)
422                         return true;
423 
424         return false;
425 }
426 
427 /**
428  * Returns whether any output on the specified pipe will have the specified
429  * type after a staged modeset is complete, i.e., the same as
430  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431  * encoder->crtc.
432  */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435         struct drm_device *dev = crtc->base.dev;
436         struct intel_encoder *encoder;
437 
438         for_each_intel_encoder(dev, encoder)
439                 if (encoder->new_crtc == crtc && encoder->type == type)
440                         return true;
441 
442         return false;
443 }
444 
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446                                                 int refclk)
447 {
448         struct drm_device *dev = crtc->base.dev;
449         const intel_limit_t *limit;
450 
451         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452                 if (intel_is_dual_link_lvds(dev)) {
453                         if (refclk == 100000)
454                                 limit = &intel_limits_ironlake_dual_lvds_100m;
455                         else
456                                 limit = &intel_limits_ironlake_dual_lvds;
457                 } else {
458                         if (refclk == 100000)
459                                 limit = &intel_limits_ironlake_single_lvds_100m;
460                         else
461                                 limit = &intel_limits_ironlake_single_lvds;
462                 }
463         } else
464                 limit = &intel_limits_ironlake_dac;
465 
466         return limit;
467 }
468 
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471         struct drm_device *dev = crtc->base.dev;
472         const intel_limit_t *limit;
473 
474         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475                 if (intel_is_dual_link_lvds(dev))
476                         limit = &intel_limits_g4x_dual_channel_lvds;
477                 else
478                         limit = &intel_limits_g4x_single_channel_lvds;
479         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481                 limit = &intel_limits_g4x_hdmi;
482         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483                 limit = &intel_limits_g4x_sdvo;
484         } else /* The option is for other outputs */
485                 limit = &intel_limits_i9xx_sdvo;
486 
487         return limit;
488 }
489 
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492         struct drm_device *dev = crtc->base.dev;
493         const intel_limit_t *limit;
494 
495         if (HAS_PCH_SPLIT(dev))
496                 limit = intel_ironlake_limit(crtc, refclk);
497         else if (IS_G4X(dev)) {
498                 limit = intel_g4x_limit(crtc);
499         } else if (IS_PINEVIEW(dev)) {
500                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501                         limit = &intel_limits_pineview_lvds;
502                 else
503                         limit = &intel_limits_pineview_sdvo;
504         } else if (IS_CHERRYVIEW(dev)) {
505                 limit = &intel_limits_chv;
506         } else if (IS_VALLEYVIEW(dev)) {
507                 limit = &intel_limits_vlv;
508         } else if (!IS_GEN2(dev)) {
509                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510                         limit = &intel_limits_i9xx_lvds;
511                 else
512                         limit = &intel_limits_i9xx_sdvo;
513         } else {
514                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515                         limit = &intel_limits_i8xx_lvds;
516                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517                         limit = &intel_limits_i8xx_dvo;
518                 else
519                         limit = &intel_limits_i8xx_dac;
520         }
521         return limit;
522 }
523 
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527         clock->m = clock->m2 + 2;
528         clock->p = clock->p1 * clock->p2;
529         if (WARN_ON(clock->n == 0 || clock->p == 0))
530                 return;
531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534 
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539 
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542         clock->m = i9xx_dpll_compute_m(clock);
543         clock->p = clock->p1 * clock->p2;
544         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545                 return;
546         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549 
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552         clock->m = clock->m1 * clock->m2;
553         clock->p = clock->p1 * clock->p2;
554         if (WARN_ON(clock->n == 0 || clock->p == 0))
555                 return;
556         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557                         clock->n << 22);
558         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560 
561 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563  * Returns whether the given set of divisors are valid for a given refclk with
564  * the given connectors.
565  */
566 
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568                                const intel_limit_t *limit,
569                                const intel_clock_t *clock)
570 {
571         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
572                 INTELPllInvalid("n out of range\n");
573         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
574                 INTELPllInvalid("p1 out of range\n");
575         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
576                 INTELPllInvalid("m2 out of range\n");
577         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
578                 INTELPllInvalid("m1 out of range\n");
579 
580         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581                 if (clock->m1 <= clock->m2)
582                         INTELPllInvalid("m1 <= m2\n");
583 
584         if (!IS_VALLEYVIEW(dev)) {
585                 if (clock->p < limit->p.min || limit->p.max < clock->p)
586                         INTELPllInvalid("p out of range\n");
587                 if (clock->m < limit->m.min || limit->m.max < clock->m)
588                         INTELPllInvalid("m out of range\n");
589         }
590 
591         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592                 INTELPllInvalid("vco out of range\n");
593         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594          * connector, etc., rather than just a single range.
595          */
596         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597                 INTELPllInvalid("dot out of range\n");
598 
599         return true;
600 }
601 
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604                     int target, int refclk, intel_clock_t *match_clock,
605                     intel_clock_t *best_clock)
606 {
607         struct drm_device *dev = crtc->base.dev;
608         intel_clock_t clock;
609         int err = target;
610 
611         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612                 /*
613                  * For LVDS just rely on its current settings for dual-channel.
614                  * We haven't figured out how to reliably set up different
615                  * single/dual channel state, if we even can.
616                  */
617                 if (intel_is_dual_link_lvds(dev))
618                         clock.p2 = limit->p2.p2_fast;
619                 else
620                         clock.p2 = limit->p2.p2_slow;
621         } else {
622                 if (target < limit->p2.dot_limit)
623                         clock.p2 = limit->p2.p2_slow;
624                 else
625                         clock.p2 = limit->p2.p2_fast;
626         }
627 
628         memset(best_clock, 0, sizeof(*best_clock));
629 
630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631              clock.m1++) {
632                 for (clock.m2 = limit->m2.min;
633                      clock.m2 <= limit->m2.max; clock.m2++) {
634                         if (clock.m2 >= clock.m1)
635                                 break;
636                         for (clock.n = limit->n.min;
637                              clock.n <= limit->n.max; clock.n++) {
638                                 for (clock.p1 = limit->p1.min;
639                                         clock.p1 <= limit->p1.max; clock.p1++) {
640                                         int this_err;
641 
642                                         i9xx_clock(refclk, &clock);
643                                         if (!intel_PLL_is_valid(dev, limit,
644                                                                 &clock))
645                                                 continue;
646                                         if (match_clock &&
647                                             clock.p != match_clock->p)
648                                                 continue;
649 
650                                         this_err = abs(clock.dot - target);
651                                         if (this_err < err) {
652                                                 *best_clock = clock;
653                                                 err = this_err;
654                                         }
655                                 }
656                         }
657                 }
658         }
659 
660         return (err != target);
661 }
662 
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665                    int target, int refclk, intel_clock_t *match_clock,
666                    intel_clock_t *best_clock)
667 {
668         struct drm_device *dev = crtc->base.dev;
669         intel_clock_t clock;
670         int err = target;
671 
672         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673                 /*
674                  * For LVDS just rely on its current settings for dual-channel.
675                  * We haven't figured out how to reliably set up different
676                  * single/dual channel state, if we even can.
677                  */
678                 if (intel_is_dual_link_lvds(dev))
679                         clock.p2 = limit->p2.p2_fast;
680                 else
681                         clock.p2 = limit->p2.p2_slow;
682         } else {
683                 if (target < limit->p2.dot_limit)
684                         clock.p2 = limit->p2.p2_slow;
685                 else
686                         clock.p2 = limit->p2.p2_fast;
687         }
688 
689         memset(best_clock, 0, sizeof(*best_clock));
690 
691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692              clock.m1++) {
693                 for (clock.m2 = limit->m2.min;
694                      clock.m2 <= limit->m2.max; clock.m2++) {
695                         for (clock.n = limit->n.min;
696                              clock.n <= limit->n.max; clock.n++) {
697                                 for (clock.p1 = limit->p1.min;
698                                         clock.p1 <= limit->p1.max; clock.p1++) {
699                                         int this_err;
700 
701                                         pineview_clock(refclk, &clock);
702                                         if (!intel_PLL_is_valid(dev, limit,
703                                                                 &clock))
704                                                 continue;
705                                         if (match_clock &&
706                                             clock.p != match_clock->p)
707                                                 continue;
708 
709                                         this_err = abs(clock.dot - target);
710                                         if (this_err < err) {
711                                                 *best_clock = clock;
712                                                 err = this_err;
713                                         }
714                                 }
715                         }
716                 }
717         }
718 
719         return (err != target);
720 }
721 
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724                    int target, int refclk, intel_clock_t *match_clock,
725                    intel_clock_t *best_clock)
726 {
727         struct drm_device *dev = crtc->base.dev;
728         intel_clock_t clock;
729         int max_n;
730         bool found;
731         /* approximately equals target * 0.00585 */
732         int err_most = (target >> 8) + (target >> 9);
733         found = false;
734 
735         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736                 if (intel_is_dual_link_lvds(dev))
737                         clock.p2 = limit->p2.p2_fast;
738                 else
739                         clock.p2 = limit->p2.p2_slow;
740         } else {
741                 if (target < limit->p2.dot_limit)
742                         clock.p2 = limit->p2.p2_slow;
743                 else
744                         clock.p2 = limit->p2.p2_fast;
745         }
746 
747         memset(best_clock, 0, sizeof(*best_clock));
748         max_n = limit->n.max;
749         /* based on hardware requirement, prefer smaller n to precision */
750         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751                 /* based on hardware requirement, prefere larger m1,m2 */
752                 for (clock.m1 = limit->m1.max;
753                      clock.m1 >= limit->m1.min; clock.m1--) {
754                         for (clock.m2 = limit->m2.max;
755                              clock.m2 >= limit->m2.min; clock.m2--) {
756                                 for (clock.p1 = limit->p1.max;
757                                      clock.p1 >= limit->p1.min; clock.p1--) {
758                                         int this_err;
759 
760                                         i9xx_clock(refclk, &clock);
761                                         if (!intel_PLL_is_valid(dev, limit,
762                                                                 &clock))
763                                                 continue;
764 
765                                         this_err = abs(clock.dot - target);
766                                         if (this_err < err_most) {
767                                                 *best_clock = clock;
768                                                 err_most = this_err;
769                                                 max_n = clock.n;
770                                                 found = true;
771                                         }
772                                 }
773                         }
774                 }
775         }
776         return found;
777 }
778 
779 static bool
780 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
781                    int target, int refclk, intel_clock_t *match_clock,
782                    intel_clock_t *best_clock)
783 {
784         struct drm_device *dev = crtc->base.dev;
785         intel_clock_t clock;
786         unsigned int bestppm = 1000000;
787         /* min update 19.2 MHz */
788         int max_n = min(limit->n.max, refclk / 19200);
789         bool found = false;
790 
791         target *= 5; /* fast clock */
792 
793         memset(best_clock, 0, sizeof(*best_clock));
794 
795         /* based on hardware requirement, prefer smaller n to precision */
796         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
798                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
799                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
800                                 clock.p = clock.p1 * clock.p2;
801                                 /* based on hardware requirement, prefer bigger m1,m2 values */
802                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
803                                         unsigned int ppm, diff;
804 
805                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
806                                                                      refclk * clock.m1);
807 
808                                         vlv_clock(refclk, &clock);
809 
810                                         if (!intel_PLL_is_valid(dev, limit,
811                                                                 &clock))
812                                                 continue;
813 
814                                         diff = abs(clock.dot - target);
815                                         ppm = div_u64(1000000ULL * diff, target);
816 
817                                         if (ppm < 100 && clock.p > best_clock->p) {
818                                                 bestppm = 0;
819                                                 *best_clock = clock;
820                                                 found = true;
821                                         }
822 
823                                         if (bestppm >= 10 && ppm < bestppm - 10) {
824                                                 bestppm = ppm;
825                                                 *best_clock = clock;
826                                                 found = true;
827                                         }
828                                 }
829                         }
830                 }
831         }
832 
833         return found;
834 }
835 
836 static bool
837 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
838                    int target, int refclk, intel_clock_t *match_clock,
839                    intel_clock_t *best_clock)
840 {
841         struct drm_device *dev = crtc->base.dev;
842         intel_clock_t clock;
843         uint64_t m2;
844         int found = false;
845 
846         memset(best_clock, 0, sizeof(*best_clock));
847 
848         /*
849          * Based on hardware doc, the n always set to 1, and m1 always
850          * set to 2.  If requires to support 200Mhz refclk, we need to
851          * revisit this because n may not 1 anymore.
852          */
853         clock.n = 1, clock.m1 = 2;
854         target *= 5;    /* fast clock */
855 
856         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
857                 for (clock.p2 = limit->p2.p2_fast;
858                                 clock.p2 >= limit->p2.p2_slow;
859                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
860 
861                         clock.p = clock.p1 * clock.p2;
862 
863                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
864                                         clock.n) << 22, refclk * clock.m1);
865 
866                         if (m2 > INT_MAX/clock.m1)
867                                 continue;
868 
869                         clock.m2 = m2;
870 
871                         chv_clock(refclk, &clock);
872 
873                         if (!intel_PLL_is_valid(dev, limit, &clock))
874                                 continue;
875 
876                         /* based on hardware requirement, prefer bigger p
877                          */
878                         if (clock.p > best_clock->p) {
879                                 *best_clock = clock;
880                                 found = true;
881                         }
882                 }
883         }
884 
885         return found;
886 }
887 
888 bool intel_crtc_active(struct drm_crtc *crtc)
889 {
890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891 
892         /* Be paranoid as we can arrive here with only partial
893          * state retrieved from the hardware during setup.
894          *
895          * We can ditch the adjusted_mode.crtc_clock check as soon
896          * as Haswell has gained clock readout/fastboot support.
897          *
898          * We can ditch the crtc->primary->fb check as soon as we can
899          * properly reconstruct framebuffers.
900          */
901         return intel_crtc->active && crtc->primary->fb &&
902                 intel_crtc->config->base.adjusted_mode.crtc_clock;
903 }
904 
905 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
906                                              enum pipe pipe)
907 {
908         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
910 
911         return intel_crtc->config->cpu_transcoder;
912 }
913 
914 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
915 {
916         struct drm_i915_private *dev_priv = dev->dev_private;
917         u32 reg = PIPEDSL(pipe);
918         u32 line1, line2;
919         u32 line_mask;
920 
921         if (IS_GEN2(dev))
922                 line_mask = DSL_LINEMASK_GEN2;
923         else
924                 line_mask = DSL_LINEMASK_GEN3;
925 
926         line1 = I915_READ(reg) & line_mask;
927         mdelay(5);
928         line2 = I915_READ(reg) & line_mask;
929 
930         return line1 == line2;
931 }
932 
933 /*
934  * intel_wait_for_pipe_off - wait for pipe to turn off
935  * @crtc: crtc whose pipe to wait for
936  *
937  * After disabling a pipe, we can't wait for vblank in the usual way,
938  * spinning on the vblank interrupt status bit, since we won't actually
939  * see an interrupt when the pipe is disabled.
940  *
941  * On Gen4 and above:
942  *   wait for the pipe register state bit to turn off
943  *
944  * Otherwise:
945  *   wait for the display line value to settle (it usually
946  *   ends up stopping at the start of the next frame).
947  *
948  */
949 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
950 {
951         struct drm_device *dev = crtc->base.dev;
952         struct drm_i915_private *dev_priv = dev->dev_private;
953         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
954         enum pipe pipe = crtc->pipe;
955 
956         if (INTEL_INFO(dev)->gen >= 4) {
957                 int reg = PIPECONF(cpu_transcoder);
958 
959                 /* Wait for the Pipe State to go off */
960                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
961                              100))
962                         WARN(1, "pipe_off wait timed out\n");
963         } else {
964                 /* Wait for the display line to settle */
965                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
966                         WARN(1, "pipe_off wait timed out\n");
967         }
968 }
969 
970 /*
971  * ibx_digital_port_connected - is the specified port connected?
972  * @dev_priv: i915 private structure
973  * @port: the port to test
974  *
975  * Returns true if @port is connected, false otherwise.
976  */
977 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
978                                 struct intel_digital_port *port)
979 {
980         u32 bit;
981 
982         if (HAS_PCH_IBX(dev_priv->dev)) {
983                 switch (port->port) {
984                 case PORT_B:
985                         bit = SDE_PORTB_HOTPLUG;
986                         break;
987                 case PORT_C:
988                         bit = SDE_PORTC_HOTPLUG;
989                         break;
990                 case PORT_D:
991                         bit = SDE_PORTD_HOTPLUG;
992                         break;
993                 default:
994                         return true;
995                 }
996         } else {
997                 switch (port->port) {
998                 case PORT_B:
999                         bit = SDE_PORTB_HOTPLUG_CPT;
1000                         break;
1001                 case PORT_C:
1002                         bit = SDE_PORTC_HOTPLUG_CPT;
1003                         break;
1004                 case PORT_D:
1005                         bit = SDE_PORTD_HOTPLUG_CPT;
1006                         break;
1007                 default:
1008                         return true;
1009                 }
1010         }
1011 
1012         return I915_READ(SDEISR) & bit;
1013 }
1014 
1015 static const char *state_string(bool enabled)
1016 {
1017         return enabled ? "on" : "off";
1018 }
1019 
1020 /* Only for pre-ILK configs */
1021 void assert_pll(struct drm_i915_private *dev_priv,
1022                 enum pipe pipe, bool state)
1023 {
1024         int reg;
1025         u32 val;
1026         bool cur_state;
1027 
1028         reg = DPLL(pipe);
1029         val = I915_READ(reg);
1030         cur_state = !!(val & DPLL_VCO_ENABLE);
1031         I915_STATE_WARN(cur_state != state,
1032              "PLL state assertion failure (expected %s, current %s)\n",
1033              state_string(state), state_string(cur_state));
1034 }
1035 
1036 /* XXX: the dsi pll is shared between MIPI DSI ports */
1037 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1038 {
1039         u32 val;
1040         bool cur_state;
1041 
1042         mutex_lock(&dev_priv->dpio_lock);
1043         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1044         mutex_unlock(&dev_priv->dpio_lock);
1045 
1046         cur_state = val & DSI_PLL_VCO_EN;
1047         I915_STATE_WARN(cur_state != state,
1048              "DSI PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1052 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1053 
1054 struct intel_shared_dpll *
1055 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1056 {
1057         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1058 
1059         if (crtc->config->shared_dpll < 0)
1060                 return NULL;
1061 
1062         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1063 }
1064 
1065 /* For ILK+ */
1066 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1067                         struct intel_shared_dpll *pll,
1068                         bool state)
1069 {
1070         bool cur_state;
1071         struct intel_dpll_hw_state hw_state;
1072 
1073         if (WARN (!pll,
1074                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1075                 return;
1076 
1077         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1078         I915_STATE_WARN(cur_state != state,
1079              "%s assertion failure (expected %s, current %s)\n",
1080              pll->name, state_string(state), state_string(cur_state));
1081 }
1082 
1083 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1084                           enum pipe pipe, bool state)
1085 {
1086         int reg;
1087         u32 val;
1088         bool cur_state;
1089         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1090                                                                       pipe);
1091 
1092         if (HAS_DDI(dev_priv->dev)) {
1093                 /* DDI does not have a specific FDI_TX register */
1094                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097         } else {
1098                 reg = FDI_TX_CTL(pipe);
1099                 val = I915_READ(reg);
1100                 cur_state = !!(val & FDI_TX_ENABLE);
1101         }
1102         I915_STATE_WARN(cur_state != state,
1103              "FDI TX state assertion failure (expected %s, current %s)\n",
1104              state_string(state), state_string(cur_state));
1105 }
1106 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1107 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1108 
1109 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1110                           enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115 
1116         reg = FDI_RX_CTL(pipe);
1117         val = I915_READ(reg);
1118         cur_state = !!(val & FDI_RX_ENABLE);
1119         I915_STATE_WARN(cur_state != state,
1120              "FDI RX state assertion failure (expected %s, current %s)\n",
1121              state_string(state), state_string(cur_state));
1122 }
1123 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1124 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1125 
1126 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1127                                       enum pipe pipe)
1128 {
1129         int reg;
1130         u32 val;
1131 
1132         /* ILK FDI PLL is always enabled */
1133         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1134                 return;
1135 
1136         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1137         if (HAS_DDI(dev_priv->dev))
1138                 return;
1139 
1140         reg = FDI_TX_CTL(pipe);
1141         val = I915_READ(reg);
1142         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1143 }
1144 
1145 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1146                        enum pipe pipe, bool state)
1147 {
1148         int reg;
1149         u32 val;
1150         bool cur_state;
1151 
1152         reg = FDI_RX_CTL(pipe);
1153         val = I915_READ(reg);
1154         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1155         I915_STATE_WARN(cur_state != state,
1156              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1157              state_string(state), state_string(cur_state));
1158 }
1159 
1160 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1161                            enum pipe pipe)
1162 {
1163         struct drm_device *dev = dev_priv->dev;
1164         int pp_reg;
1165         u32 val;
1166         enum pipe panel_pipe = PIPE_A;
1167         bool locked = true;
1168 
1169         if (WARN_ON(HAS_DDI(dev)))
1170                 return;
1171 
1172         if (HAS_PCH_SPLIT(dev)) {
1173                 u32 port_sel;
1174 
1175                 pp_reg = PCH_PP_CONTROL;
1176                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1177 
1178                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1179                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1180                         panel_pipe = PIPE_B;
1181                 /* XXX: else fix for eDP */
1182         } else if (IS_VALLEYVIEW(dev)) {
1183                 /* presumably write lock depends on pipe, not port select */
1184                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1185                 panel_pipe = pipe;
1186         } else {
1187                 pp_reg = PP_CONTROL;
1188                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1189                         panel_pipe = PIPE_B;
1190         }
1191 
1192         val = I915_READ(pp_reg);
1193         if (!(val & PANEL_POWER_ON) ||
1194             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1195                 locked = false;
1196 
1197         I915_STATE_WARN(panel_pipe == pipe && locked,
1198              "panel assertion failure, pipe %c regs locked\n",
1199              pipe_name(pipe));
1200 }
1201 
1202 static void assert_cursor(struct drm_i915_private *dev_priv,
1203                           enum pipe pipe, bool state)
1204 {
1205         struct drm_device *dev = dev_priv->dev;
1206         bool cur_state;
1207 
1208         if (IS_845G(dev) || IS_I865G(dev))
1209                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1210         else
1211                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1212 
1213         I915_STATE_WARN(cur_state != state,
1214              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1215              pipe_name(pipe), state_string(state), state_string(cur_state));
1216 }
1217 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1218 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1219 
1220 void assert_pipe(struct drm_i915_private *dev_priv,
1221                  enum pipe pipe, bool state)
1222 {
1223         int reg;
1224         u32 val;
1225         bool cur_state;
1226         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1227                                                                       pipe);
1228 
1229         /* if we need the pipe quirk it must be always on */
1230         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1231             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1232                 state = true;
1233 
1234         if (!intel_display_power_is_enabled(dev_priv,
1235                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1236                 cur_state = false;
1237         } else {
1238                 reg = PIPECONF(cpu_transcoder);
1239                 val = I915_READ(reg);
1240                 cur_state = !!(val & PIPECONF_ENABLE);
1241         }
1242 
1243         I915_STATE_WARN(cur_state != state,
1244              "pipe %c assertion failure (expected %s, current %s)\n",
1245              pipe_name(pipe), state_string(state), state_string(cur_state));
1246 }
1247 
1248 static void assert_plane(struct drm_i915_private *dev_priv,
1249                          enum plane plane, bool state)
1250 {
1251         int reg;
1252         u32 val;
1253         bool cur_state;
1254 
1255         reg = DSPCNTR(plane);
1256         val = I915_READ(reg);
1257         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1258         I915_STATE_WARN(cur_state != state,
1259              "plane %c assertion failure (expected %s, current %s)\n",
1260              plane_name(plane), state_string(state), state_string(cur_state));
1261 }
1262 
1263 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1264 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1265 
1266 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1267                                    enum pipe pipe)
1268 {
1269         struct drm_device *dev = dev_priv->dev;
1270         int reg, i;
1271         u32 val;
1272         int cur_pipe;
1273 
1274         /* Primary planes are fixed to pipes on gen4+ */
1275         if (INTEL_INFO(dev)->gen >= 4) {
1276                 reg = DSPCNTR(pipe);
1277                 val = I915_READ(reg);
1278                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1279                      "plane %c assertion failure, should be disabled but not\n",
1280                      plane_name(pipe));
1281                 return;
1282         }
1283 
1284         /* Need to check both planes against the pipe */
1285         for_each_pipe(dev_priv, i) {
1286                 reg = DSPCNTR(i);
1287                 val = I915_READ(reg);
1288                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1289                         DISPPLANE_SEL_PIPE_SHIFT;
1290                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1291                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1292                      plane_name(i), pipe_name(pipe));
1293         }
1294 }
1295 
1296 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1297                                     enum pipe pipe)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         int reg, sprite;
1301         u32 val;
1302 
1303         if (INTEL_INFO(dev)->gen >= 9) {
1304                 for_each_sprite(pipe, sprite) {
1305                         val = I915_READ(PLANE_CTL(pipe, sprite));
1306                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1307                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1308                              sprite, pipe_name(pipe));
1309                 }
1310         } else if (IS_VALLEYVIEW(dev)) {
1311                 for_each_sprite(pipe, sprite) {
1312                         reg = SPCNTR(pipe, sprite);
1313                         val = I915_READ(reg);
1314                         I915_STATE_WARN(val & SP_ENABLE,
1315                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1316                              sprite_name(pipe, sprite), pipe_name(pipe));
1317                 }
1318         } else if (INTEL_INFO(dev)->gen >= 7) {
1319                 reg = SPRCTL(pipe);
1320                 val = I915_READ(reg);
1321                 I915_STATE_WARN(val & SPRITE_ENABLE,
1322                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1323                      plane_name(pipe), pipe_name(pipe));
1324         } else if (INTEL_INFO(dev)->gen >= 5) {
1325                 reg = DVSCNTR(pipe);
1326                 val = I915_READ(reg);
1327                 I915_STATE_WARN(val & DVS_ENABLE,
1328                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1329                      plane_name(pipe), pipe_name(pipe));
1330         }
1331 }
1332 
1333 static void assert_vblank_disabled(struct drm_crtc *crtc)
1334 {
1335         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1336                 drm_crtc_vblank_put(crtc);
1337 }
1338 
1339 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1340 {
1341         u32 val;
1342         bool enabled;
1343 
1344         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1345 
1346         val = I915_READ(PCH_DREF_CONTROL);
1347         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1348                             DREF_SUPERSPREAD_SOURCE_MASK));
1349         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1350 }
1351 
1352 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1353                                            enum pipe pipe)
1354 {
1355         int reg;
1356         u32 val;
1357         bool enabled;
1358 
1359         reg = PCH_TRANSCONF(pipe);
1360         val = I915_READ(reg);
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366 
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372 
1373         if (HAS_PCH_CPT(dev_priv->dev)) {
1374                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1375                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1376                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1377                         return false;
1378         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1379                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1380                         return false;
1381         } else {
1382                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1383                         return false;
1384         }
1385         return true;
1386 }
1387 
1388 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1389                               enum pipe pipe, u32 val)
1390 {
1391         if ((val & SDVO_ENABLE) == 0)
1392                 return false;
1393 
1394         if (HAS_PCH_CPT(dev_priv->dev)) {
1395                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1396                         return false;
1397         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1399                         return false;
1400         } else {
1401                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1402                         return false;
1403         }
1404         return true;
1405 }
1406 
1407 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1408                               enum pipe pipe, u32 val)
1409 {
1410         if ((val & LVDS_PORT_EN) == 0)
1411                 return false;
1412 
1413         if (HAS_PCH_CPT(dev_priv->dev)) {
1414                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1415                         return false;
1416         } else {
1417                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1418                         return false;
1419         }
1420         return true;
1421 }
1422 
1423 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1424                               enum pipe pipe, u32 val)
1425 {
1426         if ((val & ADPA_DAC_ENABLE) == 0)
1427                 return false;
1428         if (HAS_PCH_CPT(dev_priv->dev)) {
1429                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1430                         return false;
1431         } else {
1432                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1433                         return false;
1434         }
1435         return true;
1436 }
1437 
1438 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1439                                    enum pipe pipe, int reg, u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              reg, pipe_name(pipe));
1445 
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450 
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, int reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              reg, pipe_name(pipe));
1458 
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463 
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         int reg;
1468         u32 val;
1469 
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1472         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1473 
1474         reg = PCH_ADPA;
1475         val = I915_READ(reg);
1476         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1477              "PCH VGA enabled on transcoder %c, should be disabled\n",
1478              pipe_name(pipe));
1479 
1480         reg = PCH_LVDS;
1481         val = I915_READ(reg);
1482         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1483              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1484              pipe_name(pipe));
1485 
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1489 }
1490 
1491 static void intel_init_dpio(struct drm_device *dev)
1492 {
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494 
1495         if (!IS_VALLEYVIEW(dev))
1496                 return;
1497 
1498         /*
1499          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1500          * CHV x1 PHY (DP/HDMI D)
1501          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1502          */
1503         if (IS_CHERRYVIEW(dev)) {
1504                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1505                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1506         } else {
1507                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1508         }
1509 }
1510 
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_device *dev = crtc->base.dev;
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516         int reg = DPLL(crtc->pipe);
1517         u32 dpll = pipe_config->dpll_hw_state.dpll;
1518 
1519         assert_pipe_disabled(dev_priv, crtc->pipe);
1520 
1521         /* No really, not for ILK+ */
1522         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1523 
1524         /* PLL is protected by panel, make sure we can write it */
1525         if (IS_MOBILE(dev_priv->dev))
1526                 assert_panel_unlocked(dev_priv, crtc->pipe);
1527 
1528         I915_WRITE(reg, dpll);
1529         POSTING_READ(reg);
1530         udelay(150);
1531 
1532         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1533                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1534 
1535         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1536         POSTING_READ(DPLL_MD(crtc->pipe));
1537 
1538         /* We do this three times for luck */
1539         I915_WRITE(reg, dpll);
1540         POSTING_READ(reg);
1541         udelay(150); /* wait for warmup */
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150); /* wait for warmup */
1545         I915_WRITE(reg, dpll);
1546         POSTING_READ(reg);
1547         udelay(150); /* wait for warmup */
1548 }
1549 
1550 static void chv_enable_pll(struct intel_crtc *crtc,
1551                            const struct intel_crtc_state *pipe_config)
1552 {
1553         struct drm_device *dev = crtc->base.dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         int pipe = crtc->pipe;
1556         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1557         u32 tmp;
1558 
1559         assert_pipe_disabled(dev_priv, crtc->pipe);
1560 
1561         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1562 
1563         mutex_lock(&dev_priv->dpio_lock);
1564 
1565         /* Enable back the 10bit clock to display controller */
1566         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1567         tmp |= DPIO_DCLKP_EN;
1568         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1569 
1570         /*
1571          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572          */
1573         udelay(1);
1574 
1575         /* Enable PLL */
1576         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1577 
1578         /* Check PLL is locked */
1579         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1580                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1581 
1582         /* not sure when this should be written */
1583         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1584         POSTING_READ(DPLL_MD(pipe));
1585 
1586         mutex_unlock(&dev_priv->dpio_lock);
1587 }
1588 
1589 static int intel_num_dvo_pipes(struct drm_device *dev)
1590 {
1591         struct intel_crtc *crtc;
1592         int count = 0;
1593 
1594         for_each_intel_crtc(dev, crtc)
1595                 count += crtc->active &&
1596                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1597 
1598         return count;
1599 }
1600 
1601 static void i9xx_enable_pll(struct intel_crtc *crtc)
1602 {
1603         struct drm_device *dev = crtc->base.dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         int reg = DPLL(crtc->pipe);
1606         u32 dpll = crtc->config->dpll_hw_state.dpll;
1607 
1608         assert_pipe_disabled(dev_priv, crtc->pipe);
1609 
1610         /* No really, not for ILK+ */
1611         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1612 
1613         /* PLL is protected by panel, make sure we can write it */
1614         if (IS_MOBILE(dev) && !IS_I830(dev))
1615                 assert_panel_unlocked(dev_priv, crtc->pipe);
1616 
1617         /* Enable DVO 2x clock on both PLLs if necessary */
1618         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1619                 /*
1620                  * It appears to be important that we don't enable this
1621                  * for the current pipe before otherwise configuring the
1622                  * PLL. No idea how this should be handled if multiple
1623                  * DVO outputs are enabled simultaneosly.
1624                  */
1625                 dpll |= DPLL_DVO_2X_MODE;
1626                 I915_WRITE(DPLL(!crtc->pipe),
1627                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1628         }
1629 
1630         /* Wait for the clocks to stabilize. */
1631         POSTING_READ(reg);
1632         udelay(150);
1633 
1634         if (INTEL_INFO(dev)->gen >= 4) {
1635                 I915_WRITE(DPLL_MD(crtc->pipe),
1636                            crtc->config->dpll_hw_state.dpll_md);
1637         } else {
1638                 /* The pixel multiplier can only be updated once the
1639                  * DPLL is enabled and the clocks are stable.
1640                  *
1641                  * So write it again.
1642                  */
1643                 I915_WRITE(reg, dpll);
1644         }
1645 
1646         /* We do this three times for luck */
1647         I915_WRITE(reg, dpll);
1648         POSTING_READ(reg);
1649         udelay(150); /* wait for warmup */
1650         I915_WRITE(reg, dpll);
1651         POSTING_READ(reg);
1652         udelay(150); /* wait for warmup */
1653         I915_WRITE(reg, dpll);
1654         POSTING_READ(reg);
1655         udelay(150); /* wait for warmup */
1656 }
1657 
1658 /**
1659  * i9xx_disable_pll - disable a PLL
1660  * @dev_priv: i915 private structure
1661  * @pipe: pipe PLL to disable
1662  *
1663  * Disable the PLL for @pipe, making sure the pipe is off first.
1664  *
1665  * Note!  This is for pre-ILK only.
1666  */
1667 static void i9xx_disable_pll(struct intel_crtc *crtc)
1668 {
1669         struct drm_device *dev = crtc->base.dev;
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         enum pipe pipe = crtc->pipe;
1672 
1673         /* Disable DVO 2x clock on both PLLs if necessary */
1674         if (IS_I830(dev) &&
1675             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1676             intel_num_dvo_pipes(dev) == 1) {
1677                 I915_WRITE(DPLL(PIPE_B),
1678                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1679                 I915_WRITE(DPLL(PIPE_A),
1680                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1681         }
1682 
1683         /* Don't disable pipe or pipe PLLs if needed */
1684         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1685             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1686                 return;
1687 
1688         /* Make sure the pipe isn't still relying on us */
1689         assert_pipe_disabled(dev_priv, pipe);
1690 
1691         I915_WRITE(DPLL(pipe), 0);
1692         POSTING_READ(DPLL(pipe));
1693 }
1694 
1695 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697         u32 val = 0;
1698 
1699         /* Make sure the pipe isn't still relying on us */
1700         assert_pipe_disabled(dev_priv, pipe);
1701 
1702         /*
1703          * Leave integrated clock source and reference clock enabled for pipe B.
1704          * The latter is needed for VGA hotplug / manual detection.
1705          */
1706         if (pipe == PIPE_B)
1707                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1708         I915_WRITE(DPLL(pipe), val);
1709         POSTING_READ(DPLL(pipe));
1710 
1711 }
1712 
1713 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1714 {
1715         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1716         u32 val;
1717 
1718         /* Make sure the pipe isn't still relying on us */
1719         assert_pipe_disabled(dev_priv, pipe);
1720 
1721         /* Set PLL en = 0 */
1722         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1723         if (pipe != PIPE_A)
1724                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1725         I915_WRITE(DPLL(pipe), val);
1726         POSTING_READ(DPLL(pipe));
1727 
1728         mutex_lock(&dev_priv->dpio_lock);
1729 
1730         /* Disable 10bit clock to display controller */
1731         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1732         val &= ~DPIO_DCLKP_EN;
1733         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1734 
1735         /* disable left/right clock distribution */
1736         if (pipe != PIPE_B) {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1738                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1740         } else {
1741                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1742                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1743                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1744         }
1745 
1746         mutex_unlock(&dev_priv->dpio_lock);
1747 }
1748 
1749 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1750                 struct intel_digital_port *dport)
1751 {
1752         u32 port_mask;
1753         int dpll_reg;
1754 
1755         switch (dport->port) {
1756         case PORT_B:
1757                 port_mask = DPLL_PORTB_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_C:
1761                 port_mask = DPLL_PORTC_READY_MASK;
1762                 dpll_reg = DPLL(0);
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771 
1772         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1773                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1774                      port_name(dport->port), I915_READ(dpll_reg));
1775 }
1776 
1777 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1778 {
1779         struct drm_device *dev = crtc->base.dev;
1780         struct drm_i915_private *dev_priv = dev->dev_private;
1781         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1782 
1783         if (WARN_ON(pll == NULL))
1784                 return;
1785 
1786         WARN_ON(!pll->config.crtc_mask);
1787         if (pll->active == 0) {
1788                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1789                 WARN_ON(pll->on);
1790                 assert_shared_dpll_disabled(dev_priv, pll);
1791 
1792                 pll->mode_set(dev_priv, pll);
1793         }
1794 }
1795 
1796 /**
1797  * intel_enable_shared_dpll - enable PCH PLL
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe PLL to enable
1800  *
1801  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1802  * drives the transcoder clock.
1803  */
1804 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1805 {
1806         struct drm_device *dev = crtc->base.dev;
1807         struct drm_i915_private *dev_priv = dev->dev_private;
1808         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1809 
1810         if (WARN_ON(pll == NULL))
1811                 return;
1812 
1813         if (WARN_ON(pll->config.crtc_mask == 0))
1814                 return;
1815 
1816         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1817                       pll->name, pll->active, pll->on,
1818                       crtc->base.base.id);
1819 
1820         if (pll->active++) {
1821                 WARN_ON(!pll->on);
1822                 assert_shared_dpll_enabled(dev_priv, pll);
1823                 return;
1824         }
1825         WARN_ON(pll->on);
1826 
1827         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1828 
1829         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1830         pll->enable(dev_priv, pll);
1831         pll->on = true;
1832 }
1833 
1834 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1835 {
1836         struct drm_device *dev = crtc->base.dev;
1837         struct drm_i915_private *dev_priv = dev->dev_private;
1838         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1839 
1840         /* PCH only available on ILK+ */
1841         BUG_ON(INTEL_INFO(dev)->gen < 5);
1842         if (WARN_ON(pll == NULL))
1843                return;
1844 
1845         if (WARN_ON(pll->config.crtc_mask == 0))
1846                 return;
1847 
1848         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1849                       pll->name, pll->active, pll->on,
1850                       crtc->base.base.id);
1851 
1852         if (WARN_ON(pll->active == 0)) {
1853                 assert_shared_dpll_disabled(dev_priv, pll);
1854                 return;
1855         }
1856 
1857         assert_shared_dpll_enabled(dev_priv, pll);
1858         WARN_ON(!pll->on);
1859         if (--pll->active)
1860                 return;
1861 
1862         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1863         pll->disable(dev_priv, pll);
1864         pll->on = false;
1865 
1866         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1867 }
1868 
1869 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                            enum pipe pipe)
1871 {
1872         struct drm_device *dev = dev_priv->dev;
1873         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1875         uint32_t reg, val, pipeconf_val;
1876 
1877         /* PCH only available on ILK+ */
1878         BUG_ON(!HAS_PCH_SPLIT(dev));
1879 
1880         /* Make sure PCH DPLL is enabled */
1881         assert_shared_dpll_enabled(dev_priv,
1882                                    intel_crtc_to_shared_dpll(intel_crtc));
1883 
1884         /* FDI must be feeding us bits for PCH ports */
1885         assert_fdi_tx_enabled(dev_priv, pipe);
1886         assert_fdi_rx_enabled(dev_priv, pipe);
1887 
1888         if (HAS_PCH_CPT(dev)) {
1889                 /* Workaround: Set the timing override bit before enabling the
1890                  * pch transcoder. */
1891                 reg = TRANS_CHICKEN2(pipe);
1892                 val = I915_READ(reg);
1893                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1894                 I915_WRITE(reg, val);
1895         }
1896 
1897         reg = PCH_TRANSCONF(pipe);
1898         val = I915_READ(reg);
1899         pipeconf_val = I915_READ(PIPECONF(pipe));
1900 
1901         if (HAS_PCH_IBX(dev_priv->dev)) {
1902                 /*
1903                  * make the BPC in transcoder be consistent with
1904                  * that in pipeconf reg.
1905                  */
1906                 val &= ~PIPECONF_BPC_MASK;
1907                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1908         }
1909 
1910         val &= ~TRANS_INTERLACE_MASK;
1911         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1912                 if (HAS_PCH_IBX(dev_priv->dev) &&
1913                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1914                         val |= TRANS_LEGACY_INTERLACED_ILK;
1915                 else
1916                         val |= TRANS_INTERLACED;
1917         else
1918                 val |= TRANS_PROGRESSIVE;
1919 
1920         I915_WRITE(reg, val | TRANS_ENABLE);
1921         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1922                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1923 }
1924 
1925 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1926                                       enum transcoder cpu_transcoder)
1927 {
1928         u32 val, pipeconf_val;
1929 
1930         /* PCH only available on ILK+ */
1931         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1932 
1933         /* FDI must be feeding us bits for PCH ports */
1934         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1935         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1936 
1937         /* Workaround: set timing override bit. */
1938         val = I915_READ(_TRANSA_CHICKEN2);
1939         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1940         I915_WRITE(_TRANSA_CHICKEN2, val);
1941 
1942         val = TRANS_ENABLE;
1943         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1944 
1945         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1946             PIPECONF_INTERLACED_ILK)
1947                 val |= TRANS_INTERLACED;
1948         else
1949                 val |= TRANS_PROGRESSIVE;
1950 
1951         I915_WRITE(LPT_TRANSCONF, val);
1952         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1953                 DRM_ERROR("Failed to enable PCH transcoder\n");
1954 }
1955 
1956 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1957                                             enum pipe pipe)
1958 {
1959         struct drm_device *dev = dev_priv->dev;
1960         uint32_t reg, val;
1961 
1962         /* FDI relies on the transcoder */
1963         assert_fdi_tx_disabled(dev_priv, pipe);
1964         assert_fdi_rx_disabled(dev_priv, pipe);
1965 
1966         /* Ports must be off as well */
1967         assert_pch_ports_disabled(dev_priv, pipe);
1968 
1969         reg = PCH_TRANSCONF(pipe);
1970         val = I915_READ(reg);
1971         val &= ~TRANS_ENABLE;
1972         I915_WRITE(reg, val);
1973         /* wait for PCH transcoder off, transcoder state */
1974         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1975                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1976 
1977         if (!HAS_PCH_IBX(dev)) {
1978                 /* Workaround: Clear the timing override chicken bit again. */
1979                 reg = TRANS_CHICKEN2(pipe);
1980                 val = I915_READ(reg);
1981                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1982                 I915_WRITE(reg, val);
1983         }
1984 }
1985 
1986 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1987 {
1988         u32 val;
1989 
1990         val = I915_READ(LPT_TRANSCONF);
1991         val &= ~TRANS_ENABLE;
1992         I915_WRITE(LPT_TRANSCONF, val);
1993         /* wait for PCH transcoder off, transcoder state */
1994         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1995                 DRM_ERROR("Failed to disable PCH transcoder\n");
1996 
1997         /* Workaround: clear timing override bit. */
1998         val = I915_READ(_TRANSA_CHICKEN2);
1999         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2000         I915_WRITE(_TRANSA_CHICKEN2, val);
2001 }
2002 
2003 /**
2004  * intel_enable_pipe - enable a pipe, asserting requirements
2005  * @crtc: crtc responsible for the pipe
2006  *
2007  * Enable @crtc's pipe, making sure that various hardware specific requirements
2008  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2009  */
2010 static void intel_enable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_device *dev = crtc->base.dev;
2013         struct drm_i915_private *dev_priv = dev->dev_private;
2014         enum pipe pipe = crtc->pipe;
2015         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2016                                                                       pipe);
2017         enum pipe pch_transcoder;
2018         int reg;
2019         u32 val;
2020 
2021         assert_planes_disabled(dev_priv, pipe);
2022         assert_cursor_disabled(dev_priv, pipe);
2023         assert_sprites_disabled(dev_priv, pipe);
2024 
2025         if (HAS_PCH_LPT(dev_priv->dev))
2026                 pch_transcoder = TRANSCODER_A;
2027         else
2028                 pch_transcoder = pipe;
2029 
2030         /*
2031          * A pipe without a PLL won't actually be able to drive bits from
2032          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2033          * need the check.
2034          */
2035         if (!HAS_PCH_SPLIT(dev_priv->dev))
2036                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2037                         assert_dsi_pll_enabled(dev_priv);
2038                 else
2039                         assert_pll_enabled(dev_priv, pipe);
2040         else {
2041                 if (crtc->config->has_pch_encoder) {
2042                         /* if driving the PCH, we need FDI enabled */
2043                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2044                         assert_fdi_tx_pll_enabled(dev_priv,
2045                                                   (enum pipe) cpu_transcoder);
2046                 }
2047                 /* FIXME: assert CPU port conditions for SNB+ */
2048         }
2049 
2050         reg = PIPECONF(cpu_transcoder);
2051         val = I915_READ(reg);
2052         if (val & PIPECONF_ENABLE) {
2053                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2054                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2055                 return;
2056         }
2057 
2058         I915_WRITE(reg, val | PIPECONF_ENABLE);
2059         POSTING_READ(reg);
2060 }
2061 
2062 /**
2063  * intel_disable_pipe - disable a pipe, asserting requirements
2064  * @crtc: crtc whose pipes is to be disabled
2065  *
2066  * Disable the pipe of @crtc, making sure that various hardware
2067  * specific requirements are met, if applicable, e.g. plane
2068  * disabled, panel fitter off, etc.
2069  *
2070  * Will wait until the pipe has shut down before returning.
2071  */
2072 static void intel_disable_pipe(struct intel_crtc *crtc)
2073 {
2074         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2076         enum pipe pipe = crtc->pipe;
2077         int reg;
2078         u32 val;
2079 
2080         /*
2081          * Make sure planes won't keep trying to pump pixels to us,
2082          * or we might hang the display.
2083          */
2084         assert_planes_disabled(dev_priv, pipe);
2085         assert_cursor_disabled(dev_priv, pipe);
2086         assert_sprites_disabled(dev_priv, pipe);
2087 
2088         reg = PIPECONF(cpu_transcoder);
2089         val = I915_READ(reg);
2090         if ((val & PIPECONF_ENABLE) == 0)
2091                 return;
2092 
2093         /*
2094          * Double wide has implications for planes
2095          * so best keep it disabled when not needed.
2096          */
2097         if (crtc->config->double_wide)
2098                 val &= ~PIPECONF_DOUBLE_WIDE;
2099 
2100         /* Don't disable pipe or pipe PLLs if needed */
2101         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2102             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2103                 val &= ~PIPECONF_ENABLE;
2104 
2105         I915_WRITE(reg, val);
2106         if ((val & PIPECONF_ENABLE) == 0)
2107                 intel_wait_for_pipe_off(crtc);
2108 }
2109 
2110 /*
2111  * Plane regs are double buffered, going from enabled->disabled needs a
2112  * trigger in order to latch.  The display address reg provides this.
2113  */
2114 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2115                                enum plane plane)
2116 {
2117         struct drm_device *dev = dev_priv->dev;
2118         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2119 
2120         I915_WRITE(reg, I915_READ(reg));
2121         POSTING_READ(reg);
2122 }
2123 
2124 /**
2125  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2126  * @plane:  plane to be enabled
2127  * @crtc: crtc for the plane
2128  *
2129  * Enable @plane on @crtc, making sure that the pipe is running first.
2130  */
2131 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2132                                           struct drm_crtc *crtc)
2133 {
2134         struct drm_device *dev = plane->dev;
2135         struct drm_i915_private *dev_priv = dev->dev_private;
2136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 
2138         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2139         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2140 
2141         if (intel_crtc->primary_enabled)
2142                 return;
2143 
2144         intel_crtc->primary_enabled = true;
2145 
2146         dev_priv->display.update_primary_plane(crtc, plane->fb,
2147                                                crtc->x, crtc->y);
2148 
2149         /*
2150          * BDW signals flip done immediately if the plane
2151          * is disabled, even if the plane enable is already
2152          * armed to occur at the next vblank :(
2153          */
2154         if (IS_BROADWELL(dev))
2155                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2156 }
2157 
2158 /**
2159  * intel_disable_primary_hw_plane - disable the primary hardware plane
2160  * @plane: plane to be disabled
2161  * @crtc: crtc for the plane
2162  *
2163  * Disable @plane on @crtc, making sure that the pipe is running first.
2164  */
2165 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2166                                            struct drm_crtc *crtc)
2167 {
2168         struct drm_device *dev = plane->dev;
2169         struct drm_i915_private *dev_priv = dev->dev_private;
2170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171 
2172         if (WARN_ON(!intel_crtc->active))
2173                 return;
2174 
2175         if (!intel_crtc->primary_enabled)
2176                 return;
2177 
2178         intel_crtc->primary_enabled = false;
2179 
2180         dev_priv->display.update_primary_plane(crtc, plane->fb,
2181                                                crtc->x, crtc->y);
2182 }
2183 
2184 static bool need_vtd_wa(struct drm_device *dev)
2185 {
2186 #ifdef CONFIG_INTEL_IOMMU
2187         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2188                 return true;
2189 #endif
2190         return false;
2191 }
2192 
2193 int
2194 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2195 {
2196         int tile_height;
2197 
2198         tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2199         return ALIGN(height, tile_height);
2200 }
2201 
2202 int
2203 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2204                            struct drm_framebuffer *fb,
2205                            struct intel_engine_cs *pipelined)
2206 {
2207         struct drm_device *dev = fb->dev;
2208         struct drm_i915_private *dev_priv = dev->dev_private;
2209         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2210         u32 alignment;
2211         int ret;
2212 
2213         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2214 
2215         switch (obj->tiling_mode) {
2216         case I915_TILING_NONE:
2217                 if (INTEL_INFO(dev)->gen >= 9)
2218                         alignment = 256 * 1024;
2219                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2220                         alignment = 128 * 1024;
2221                 else if (INTEL_INFO(dev)->gen >= 4)
2222                         alignment = 4 * 1024;
2223                 else
2224                         alignment = 64 * 1024;
2225                 break;
2226         case I915_TILING_X:
2227                 if (INTEL_INFO(dev)->gen >= 9)
2228                         alignment = 256 * 1024;
2229                 else {
2230                         /* pin() will align the object as required by fence */
2231                         alignment = 0;
2232                 }
2233                 break;
2234         case I915_TILING_Y:
2235                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2236                 return -EINVAL;
2237         default:
2238                 BUG();
2239         }
2240 
2241         /* Note that the w/a also requires 64 PTE of padding following the
2242          * bo. We currently fill all unused PTE with the shadow page and so
2243          * we should always have valid PTE following the scanout preventing
2244          * the VT-d warning.
2245          */
2246         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2247                 alignment = 256 * 1024;
2248 
2249         /*
2250          * Global gtt pte registers are special registers which actually forward
2251          * writes to a chunk of system memory. Which means that there is no risk
2252          * that the register values disappear as soon as we call
2253          * intel_runtime_pm_put(), so it is correct to wrap only the
2254          * pin/unpin/fence and not more.
2255          */
2256         intel_runtime_pm_get(dev_priv);
2257 
2258         dev_priv->mm.interruptible = false;
2259         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2260         if (ret)
2261                 goto err_interruptible;
2262 
2263         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2264          * fence, whereas 965+ only requires a fence if using
2265          * framebuffer compression.  For simplicity, we always install
2266          * a fence as the cost is not that onerous.
2267          */
2268         ret = i915_gem_object_get_fence(obj);
2269         if (ret)
2270                 goto err_unpin;
2271 
2272         i915_gem_object_pin_fence(obj);
2273 
2274         dev_priv->mm.interruptible = true;
2275         intel_runtime_pm_put(dev_priv);
2276         return 0;
2277 
2278 err_unpin:
2279         i915_gem_object_unpin_from_display_plane(obj);
2280 err_interruptible:
2281         dev_priv->mm.interruptible = true;
2282         intel_runtime_pm_put(dev_priv);
2283         return ret;
2284 }
2285 
2286 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2287 {
2288         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2289 
2290         i915_gem_object_unpin_fence(obj);
2291         i915_gem_object_unpin_from_display_plane(obj);
2292 }
2293 
2294 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2295  * is assumed to be a power-of-two. */
2296 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2297                                              unsigned int tiling_mode,
2298                                              unsigned int cpp,
2299                                              unsigned int pitch)
2300 {
2301         if (tiling_mode != I915_TILING_NONE) {
2302                 unsigned int tile_rows, tiles;
2303 
2304                 tile_rows = *y / 8;
2305                 *y %= 8;
2306 
2307                 tiles = *x / (512/cpp);
2308                 *x %= 512/cpp;
2309 
2310                 return tile_rows * pitch * 8 + tiles * 4096;
2311         } else {
2312                 unsigned int offset;
2313 
2314                 offset = *y * pitch + *x * cpp;
2315                 *y = 0;
2316                 *x = (offset & 4095) / cpp;
2317                 return offset & -4096;
2318         }
2319 }
2320 
2321 static int i9xx_format_to_fourcc(int format)
2322 {
2323         switch (format) {
2324         case DISPPLANE_8BPP:
2325                 return DRM_FORMAT_C8;
2326         case DISPPLANE_BGRX555:
2327                 return DRM_FORMAT_XRGB1555;
2328         case DISPPLANE_BGRX565:
2329                 return DRM_FORMAT_RGB565;
2330         default:
2331         case DISPPLANE_BGRX888:
2332                 return DRM_FORMAT_XRGB8888;
2333         case DISPPLANE_RGBX888:
2334                 return DRM_FORMAT_XBGR8888;
2335         case DISPPLANE_BGRX101010:
2336                 return DRM_FORMAT_XRGB2101010;
2337         case DISPPLANE_RGBX101010:
2338                 return DRM_FORMAT_XBGR2101010;
2339         }
2340 }
2341 
2342 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2343 {
2344         switch (format) {
2345         case PLANE_CTL_FORMAT_RGB_565:
2346                 return DRM_FORMAT_RGB565;
2347         default:
2348         case PLANE_CTL_FORMAT_XRGB_8888:
2349                 if (rgb_order) {
2350                         if (alpha)
2351                                 return DRM_FORMAT_ABGR8888;
2352                         else
2353                                 return DRM_FORMAT_XBGR8888;
2354                 } else {
2355                         if (alpha)
2356                                 return DRM_FORMAT_ARGB8888;
2357                         else
2358                                 return DRM_FORMAT_XRGB8888;
2359                 }
2360         case PLANE_CTL_FORMAT_XRGB_2101010:
2361                 if (rgb_order)
2362                         return DRM_FORMAT_XBGR2101010;
2363                 else
2364                         return DRM_FORMAT_XRGB2101010;
2365         }
2366 }
2367 
2368 static bool
2369 intel_alloc_plane_obj(struct intel_crtc *crtc,
2370                       struct intel_initial_plane_config *plane_config)
2371 {
2372         struct drm_device *dev = crtc->base.dev;
2373         struct drm_i915_gem_object *obj = NULL;
2374         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2375         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2376         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2377                                     PAGE_SIZE);
2378 
2379         size_aligned -= base_aligned;
2380 
2381         if (plane_config->size == 0)
2382                 return false;
2383 
2384         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2385                                                              base_aligned,
2386                                                              base_aligned,
2387                                                              size_aligned);
2388         if (!obj)
2389                 return false;
2390 
2391         obj->tiling_mode = plane_config->tiling;
2392         if (obj->tiling_mode == I915_TILING_X)
2393                 obj->stride = crtc->base.primary->fb->pitches[0];
2394 
2395         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2396         mode_cmd.width = crtc->base.primary->fb->width;
2397         mode_cmd.height = crtc->base.primary->fb->height;
2398         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2399 
2400         mutex_lock(&dev->struct_mutex);
2401 
2402         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2403                                    &mode_cmd, obj)) {
2404                 DRM_DEBUG_KMS("intel fb init failed\n");
2405                 goto out_unref_obj;
2406         }
2407 
2408         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2409         mutex_unlock(&dev->struct_mutex);
2410 
2411         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2412         return true;
2413 
2414 out_unref_obj:
2415         drm_gem_object_unreference(&obj->base);
2416         mutex_unlock(&dev->struct_mutex);
2417         return false;
2418 }
2419 
2420 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2421 static void
2422 update_state_fb(struct drm_plane *plane)
2423 {
2424         if (plane->fb != plane->state->fb)
2425                 drm_atomic_set_fb_for_plane(plane->state, plane->fb);
2426 }
2427 
2428 static void
2429 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2430                      struct intel_initial_plane_config *plane_config)
2431 {
2432         struct drm_device *dev = intel_crtc->base.dev;
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434         struct drm_crtc *c;
2435         struct intel_crtc *i;
2436         struct drm_i915_gem_object *obj;
2437 
2438         if (!intel_crtc->base.primary->fb)
2439                 return;
2440 
2441         if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2442                 struct drm_plane *primary = intel_crtc->base.primary;
2443 
2444                 primary->state->crtc = &intel_crtc->base;
2445                 primary->crtc = &intel_crtc->base;
2446                 update_state_fb(primary);
2447 
2448                 return;
2449         }
2450 
2451         kfree(intel_crtc->base.primary->fb);
2452         intel_crtc->base.primary->fb = NULL;
2453 
2454         /*
2455          * Failed to alloc the obj, check to see if we should share
2456          * an fb with another CRTC instead
2457          */
2458         for_each_crtc(dev, c) {
2459                 i = to_intel_crtc(c);
2460 
2461                 if (c == &intel_crtc->base)
2462                         continue;
2463 
2464                 if (!i->active)
2465                         continue;
2466 
2467                 obj = intel_fb_obj(c->primary->fb);
2468                 if (obj == NULL)
2469                         continue;
2470 
2471                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2472                         struct drm_plane *primary = intel_crtc->base.primary;
2473 
2474                         if (obj->tiling_mode != I915_TILING_NONE)
2475                                 dev_priv->preserve_bios_swizzle = true;
2476 
2477                         drm_framebuffer_reference(c->primary->fb);
2478                         primary->fb = c->primary->fb;
2479                         primary->state->crtc = &intel_crtc->base;
2480                         primary->crtc = &intel_crtc->base;
2481                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2482                         break;
2483                 }
2484         }
2485 
2486         update_state_fb(intel_crtc->base.primary);
2487 }
2488 
2489 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2490                                       struct drm_framebuffer *fb,
2491                                       int x, int y)
2492 {
2493         struct drm_device *dev = crtc->dev;
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2496         struct drm_i915_gem_object *obj;
2497         int plane = intel_crtc->plane;
2498         unsigned long linear_offset;
2499         u32 dspcntr;
2500         u32 reg = DSPCNTR(plane);
2501         int pixel_size;
2502 
2503         if (!intel_crtc->primary_enabled) {
2504                 I915_WRITE(reg, 0);
2505                 if (INTEL_INFO(dev)->gen >= 4)
2506                         I915_WRITE(DSPSURF(plane), 0);
2507                 else
2508                         I915_WRITE(DSPADDR(plane), 0);
2509                 POSTING_READ(reg);
2510                 return;
2511         }
2512 
2513         obj = intel_fb_obj(fb);
2514         if (WARN_ON(obj == NULL))
2515                 return;
2516 
2517         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2518 
2519         dspcntr = DISPPLANE_GAMMA_ENABLE;
2520 
2521         dspcntr |= DISPLAY_PLANE_ENABLE;
2522 
2523         if (INTEL_INFO(dev)->gen < 4) {
2524                 if (intel_crtc->pipe == PIPE_B)
2525                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2526 
2527                 /* pipesrc and dspsize control the size that is scaled from,
2528                  * which should always be the user's requested size.
2529                  */
2530                 I915_WRITE(DSPSIZE(plane),
2531                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2532                            (intel_crtc->config->pipe_src_w - 1));
2533                 I915_WRITE(DSPPOS(plane), 0);
2534         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2535                 I915_WRITE(PRIMSIZE(plane),
2536                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2537                            (intel_crtc->config->pipe_src_w - 1));
2538                 I915_WRITE(PRIMPOS(plane), 0);
2539                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2540         }
2541 
2542         switch (fb->pixel_format) {
2543         case DRM_FORMAT_C8:
2544                 dspcntr |= DISPPLANE_8BPP;
2545                 break;
2546         case DRM_FORMAT_XRGB1555:
2547         case DRM_FORMAT_ARGB1555:
2548                 dspcntr |= DISPPLANE_BGRX555;
2549                 break;
2550         case DRM_FORMAT_RGB565:
2551                 dspcntr |= DISPPLANE_BGRX565;
2552                 break;
2553         case DRM_FORMAT_XRGB8888:
2554         case DRM_FORMAT_ARGB8888:
2555                 dspcntr |= DISPPLANE_BGRX888;
2556                 break;
2557         case DRM_FORMAT_XBGR8888:
2558         case DRM_FORMAT_ABGR8888:
2559                 dspcntr |= DISPPLANE_RGBX888;
2560                 break;
2561         case DRM_FORMAT_XRGB2101010:
2562         case DRM_FORMAT_ARGB2101010:
2563                 dspcntr |= DISPPLANE_BGRX101010;
2564                 break;
2565         case DRM_FORMAT_XBGR2101010:
2566         case DRM_FORMAT_ABGR2101010:
2567                 dspcntr |= DISPPLANE_RGBX101010;
2568                 break;
2569         default:
2570                 BUG();
2571         }
2572 
2573         if (INTEL_INFO(dev)->gen >= 4 &&
2574             obj->tiling_mode != I915_TILING_NONE)
2575                 dspcntr |= DISPPLANE_TILED;
2576 
2577         if (IS_G4X(dev))
2578                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2579 
2580         linear_offset = y * fb->pitches[0] + x * pixel_size;
2581 
2582         if (INTEL_INFO(dev)->gen >= 4) {
2583                 intel_crtc->dspaddr_offset =
2584                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2585                                                        pixel_size,
2586                                                        fb->pitches[0]);
2587                 linear_offset -= intel_crtc->dspaddr_offset;
2588         } else {
2589                 intel_crtc->dspaddr_offset = linear_offset;
2590         }
2591 
2592         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2593                 dspcntr |= DISPPLANE_ROTATE_180;
2594 
2595                 x += (intel_crtc->config->pipe_src_w - 1);
2596                 y += (intel_crtc->config->pipe_src_h - 1);
2597 
2598                 /* Finding the last pixel of the last line of the display
2599                 data and adding to linear_offset*/
2600                 linear_offset +=
2601                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2602                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2603         }
2604 
2605         I915_WRITE(reg, dspcntr);
2606 
2607         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2608                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2609                       fb->pitches[0]);
2610         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2611         if (INTEL_INFO(dev)->gen >= 4) {
2612                 I915_WRITE(DSPSURF(plane),
2613                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2614                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2615                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2616         } else
2617                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2618         POSTING_READ(reg);
2619 }
2620 
2621 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2622                                           struct drm_framebuffer *fb,
2623                                           int x, int y)
2624 {
2625         struct drm_device *dev = crtc->dev;
2626         struct drm_i915_private *dev_priv = dev->dev_private;
2627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2628         struct drm_i915_gem_object *obj;
2629         int plane = intel_crtc->plane;
2630         unsigned long linear_offset;
2631         u32 dspcntr;
2632         u32 reg = DSPCNTR(plane);
2633         int pixel_size;
2634 
2635         if (!intel_crtc->primary_enabled) {
2636                 I915_WRITE(reg, 0);
2637                 I915_WRITE(DSPSURF(plane), 0);
2638                 POSTING_READ(reg);
2639                 return;
2640         }
2641 
2642         obj = intel_fb_obj(fb);
2643         if (WARN_ON(obj == NULL))
2644                 return;
2645 
2646         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2647 
2648         dspcntr = DISPPLANE_GAMMA_ENABLE;
2649 
2650         dspcntr |= DISPLAY_PLANE_ENABLE;
2651 
2652         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2653                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2654 
2655         switch (fb->pixel_format) {
2656         case DRM_FORMAT_C8:
2657                 dspcntr |= DISPPLANE_8BPP;
2658                 break;
2659         case DRM_FORMAT_RGB565:
2660                 dspcntr |= DISPPLANE_BGRX565;
2661                 break;
2662         case DRM_FORMAT_XRGB8888:
2663         case DRM_FORMAT_ARGB8888:
2664                 dspcntr |= DISPPLANE_BGRX888;
2665                 break;
2666         case DRM_FORMAT_XBGR8888:
2667         case DRM_FORMAT_ABGR8888:
2668                 dspcntr |= DISPPLANE_RGBX888;
2669                 break;
2670         case DRM_FORMAT_XRGB2101010:
2671         case DRM_FORMAT_ARGB2101010:
2672                 dspcntr |= DISPPLANE_BGRX101010;
2673                 break;
2674         case DRM_FORMAT_XBGR2101010:
2675         case DRM_FORMAT_ABGR2101010:
2676                 dspcntr |= DISPPLANE_RGBX101010;
2677                 break;
2678         default:
2679                 BUG();
2680         }
2681 
2682         if (obj->tiling_mode != I915_TILING_NONE)
2683                 dspcntr |= DISPPLANE_TILED;
2684 
2685         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2686                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2687 
2688         linear_offset = y * fb->pitches[0] + x * pixel_size;
2689         intel_crtc->dspaddr_offset =
2690                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2691                                                pixel_size,
2692                                                fb->pitches[0]);
2693         linear_offset -= intel_crtc->dspaddr_offset;
2694         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2695                 dspcntr |= DISPPLANE_ROTATE_180;
2696 
2697                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2698                         x += (intel_crtc->config->pipe_src_w - 1);
2699                         y += (intel_crtc->config->pipe_src_h - 1);
2700 
2701                         /* Finding the last pixel of the last line of the display
2702                         data and adding to linear_offset*/
2703                         linear_offset +=
2704                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2705                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2706                 }
2707         }
2708 
2709         I915_WRITE(reg, dspcntr);
2710 
2711         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2712                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2713                       fb->pitches[0]);
2714         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2715         I915_WRITE(DSPSURF(plane),
2716                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2717         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2718                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2719         } else {
2720                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2721                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2722         }
2723         POSTING_READ(reg);
2724 }
2725 
2726 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2727                                          struct drm_framebuffer *fb,
2728                                          int x, int y)
2729 {
2730         struct drm_device *dev = crtc->dev;
2731         struct drm_i915_private *dev_priv = dev->dev_private;
2732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733         struct intel_framebuffer *intel_fb;
2734         struct drm_i915_gem_object *obj;
2735         int pipe = intel_crtc->pipe;
2736         u32 plane_ctl, stride;
2737 
2738         if (!intel_crtc->primary_enabled) {
2739                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2740                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2741                 POSTING_READ(PLANE_CTL(pipe, 0));
2742                 return;
2743         }
2744 
2745         plane_ctl = PLANE_CTL_ENABLE |
2746                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2747                     PLANE_CTL_PIPE_CSC_ENABLE;
2748 
2749         switch (fb->pixel_format) {
2750         case DRM_FORMAT_RGB565:
2751                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2752                 break;
2753         case DRM_FORMAT_XRGB8888:
2754                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2755                 break;
2756         case DRM_FORMAT_ARGB8888:
2757                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2758                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2759                 break;
2760         case DRM_FORMAT_XBGR8888:
2761                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2762                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2763                 break;
2764         case DRM_FORMAT_ABGR8888:
2765                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2766                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2767                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2768                 break;
2769         case DRM_FORMAT_XRGB2101010:
2770                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2771                 break;
2772         case DRM_FORMAT_XBGR2101010:
2773                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2774                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2775                 break;
2776         default:
2777                 BUG();
2778         }
2779 
2780         intel_fb = to_intel_framebuffer(fb);
2781         obj = intel_fb->obj;
2782 
2783         /*
2784          * The stride is either expressed as a multiple of 64 bytes chunks for
2785          * linear buffers or in number of tiles for tiled buffers.
2786          */
2787         switch (obj->tiling_mode) {
2788         case I915_TILING_NONE:
2789                 stride = fb->pitches[0] >> 6;
2790                 break;
2791         case I915_TILING_X:
2792                 plane_ctl |= PLANE_CTL_TILED_X;
2793                 stride = fb->pitches[0] >> 9;
2794                 break;
2795         default:
2796                 BUG();
2797         }
2798 
2799         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2800         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2801                 plane_ctl |= PLANE_CTL_ROTATE_180;
2802 
2803         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2804 
2805         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2806                       i915_gem_obj_ggtt_offset(obj),
2807                       x, y, fb->width, fb->height,
2808                       fb->pitches[0]);
2809 
2810         I915_WRITE(PLANE_POS(pipe, 0), 0);
2811         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2812         I915_WRITE(PLANE_SIZE(pipe, 0),
2813                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2814                    (intel_crtc->config->pipe_src_w - 1));
2815         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2816         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2817 
2818         POSTING_READ(PLANE_SURF(pipe, 0));
2819 }
2820 
2821 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2822 static int
2823 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2824                            int x, int y, enum mode_set_atomic state)
2825 {
2826         struct drm_device *dev = crtc->dev;
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828 
2829         if (dev_priv->display.disable_fbc)
2830                 dev_priv->display.disable_fbc(dev);
2831 
2832         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2833 
2834         return 0;
2835 }
2836 
2837 static void intel_complete_page_flips(struct drm_device *dev)
2838 {
2839         struct drm_crtc *crtc;
2840 
2841         for_each_crtc(dev, crtc) {
2842                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2843                 enum plane plane = intel_crtc->plane;
2844 
2845                 intel_prepare_page_flip(dev, plane);
2846                 intel_finish_page_flip_plane(dev, plane);
2847         }
2848 }
2849 
2850 static void intel_update_primary_planes(struct drm_device *dev)
2851 {
2852         struct drm_i915_private *dev_priv = dev->dev_private;
2853         struct drm_crtc *crtc;
2854 
2855         for_each_crtc(dev, crtc) {
2856                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2857 
2858                 drm_modeset_lock(&crtc->mutex, NULL);
2859                 /*
2860                  * FIXME: Once we have proper support for primary planes (and
2861                  * disabling them without disabling the entire crtc) allow again
2862                  * a NULL crtc->primary->fb.
2863                  */
2864                 if (intel_crtc->active && crtc->primary->fb)
2865                         dev_priv->display.update_primary_plane(crtc,
2866                                                                crtc->primary->fb,
2867                                                                crtc->x,
2868                                                                crtc->y);
2869                 drm_modeset_unlock(&crtc->mutex);
2870         }
2871 }
2872 
2873 void intel_prepare_reset(struct drm_device *dev)
2874 {
2875         struct drm_i915_private *dev_priv = to_i915(dev);
2876         struct intel_crtc *crtc;
2877 
2878         /* no reset support for gen2 */
2879         if (IS_GEN2(dev))
2880                 return;
2881 
2882         /* reset doesn't touch the display */
2883         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2884                 return;
2885 
2886         drm_modeset_lock_all(dev);
2887 
2888         /*
2889          * Disabling the crtcs gracefully seems nicer. Also the
2890          * g33 docs say we should at least disable all the planes.
2891          */
2892         for_each_intel_crtc(dev, crtc) {
2893                 if (crtc->active)
2894                         dev_priv->display.crtc_disable(&crtc->base);
2895         }
2896 }
2897 
2898 void intel_finish_reset(struct drm_device *dev)
2899 {
2900         struct drm_i915_private *dev_priv = to_i915(dev);
2901 
2902         /*
2903          * Flips in the rings will be nuked by the reset,
2904          * so complete all pending flips so that user space
2905          * will get its events and not get stuck.
2906          */
2907         intel_complete_page_flips(dev);
2908 
2909         /* no reset support for gen2 */
2910         if (IS_GEN2(dev))
2911                 return;
2912 
2913         /* reset doesn't touch the display */
2914         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2915                 /*
2916                  * Flips in the rings have been nuked by the reset,
2917                  * so update the base address of all primary
2918                  * planes to the the last fb to make sure we're
2919                  * showing the correct fb after a reset.
2920                  */
2921                 intel_update_primary_planes(dev);
2922                 return;
2923         }
2924 
2925         /*
2926          * The display has been reset as well,
2927          * so need a full re-initialization.
2928          */
2929         intel_runtime_pm_disable_interrupts(dev_priv);
2930         intel_runtime_pm_enable_interrupts(dev_priv);
2931 
2932         intel_modeset_init_hw(dev);
2933 
2934         spin_lock_irq(&dev_priv->irq_lock);
2935         if (dev_priv->display.hpd_irq_setup)
2936                 dev_priv->display.hpd_irq_setup(dev);
2937         spin_unlock_irq(&dev_priv->irq_lock);
2938 
2939         intel_modeset_setup_hw_state(dev, true);
2940 
2941         intel_hpd_init(dev_priv);
2942 
2943         drm_modeset_unlock_all(dev);
2944 }
2945 
2946 static int
2947 intel_finish_fb(struct drm_framebuffer *old_fb)
2948 {
2949         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2950         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2951         bool was_interruptible = dev_priv->mm.interruptible;
2952         int ret;
2953 
2954         /* Big Hammer, we also need to ensure that any pending
2955          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2956          * current scanout is retired before unpinning the old
2957          * framebuffer.
2958          *
2959          * This should only fail upon a hung GPU, in which case we
2960          * can safely continue.
2961          */
2962         dev_priv->mm.interruptible = false;
2963         ret = i915_gem_object_finish_gpu(obj);
2964         dev_priv->mm.interruptible = was_interruptible;
2965 
2966         return ret;
2967 }
2968 
2969 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2970 {
2971         struct drm_device *dev = crtc->dev;
2972         struct drm_i915_private *dev_priv = dev->dev_private;
2973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2974         bool pending;
2975 
2976         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2977             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2978                 return false;
2979 
2980         spin_lock_irq(&dev->event_lock);
2981         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2982         spin_unlock_irq(&dev->event_lock);
2983 
2984         return pending;
2985 }
2986 
2987 static void intel_update_pipe_size(struct intel_crtc *crtc)
2988 {
2989         struct drm_device *dev = crtc->base.dev;
2990         struct drm_i915_private *dev_priv = dev->dev_private;
2991         const struct drm_display_mode *adjusted_mode;
2992 
2993         if (!i915.fastboot)
2994                 return;
2995 
2996         /*
2997          * Update pipe size and adjust fitter if needed: the reason for this is
2998          * that in compute_mode_changes we check the native mode (not the pfit
2999          * mode) to see if we can flip rather than do a full mode set. In the
3000          * fastboot case, we'll flip, but if we don't update the pipesrc and
3001          * pfit state, we'll end up with a big fb scanned out into the wrong
3002          * sized surface.
3003          *
3004          * To fix this properly, we need to hoist the checks up into
3005          * compute_mode_changes (or above), check the actual pfit state and
3006          * whether the platform allows pfit disable with pipe active, and only
3007          * then update the pipesrc and pfit state, even on the flip path.
3008          */
3009 
3010         adjusted_mode = &crtc->config->base.adjusted_mode;
3011 
3012         I915_WRITE(PIPESRC(crtc->pipe),
3013                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3014                    (adjusted_mode->crtc_vdisplay - 1));
3015         if (!crtc->config->pch_pfit.enabled &&
3016             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3017              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3018                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3019                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3020                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3021         }
3022         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3023         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3024 }
3025 
3026 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3027 {
3028         struct drm_device *dev = crtc->dev;
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031         int pipe = intel_crtc->pipe;
3032         u32 reg, temp;
3033 
3034         /* enable normal train */
3035         reg = FDI_TX_CTL(pipe);
3036         temp = I915_READ(reg);
3037         if (IS_IVYBRIDGE(dev)) {
3038                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3039                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3040         } else {
3041                 temp &= ~FDI_LINK_TRAIN_NONE;
3042                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3043         }
3044         I915_WRITE(reg, temp);
3045 
3046         reg = FDI_RX_CTL(pipe);
3047         temp = I915_READ(reg);
3048         if (HAS_PCH_CPT(dev)) {
3049                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3050                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3051         } else {
3052                 temp &= ~FDI_LINK_TRAIN_NONE;
3053                 temp |= FDI_LINK_TRAIN_NONE;
3054         }
3055         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3056 
3057         /* wait one idle pattern time */
3058         POSTING_READ(reg);
3059         udelay(1000);
3060 
3061         /* IVB wants error correction enabled */
3062         if (IS_IVYBRIDGE(dev))
3063                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3064                            FDI_FE_ERRC_ENABLE);
3065 }
3066 
3067 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3068 {
3069         return crtc->base.enabled && crtc->active &&
3070                 crtc->config->has_pch_encoder;
3071 }
3072 
3073 static void ivb_modeset_global_resources(struct drm_device *dev)
3074 {
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         struct intel_crtc *pipe_B_crtc =
3077                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3078         struct intel_crtc *pipe_C_crtc =
3079                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3080         uint32_t temp;
3081 
3082         /*
3083          * When everything is off disable fdi C so that we could enable fdi B
3084          * with all lanes. Note that we don't care about enabled pipes without
3085          * an enabled pch encoder.
3086          */
3087         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3088             !pipe_has_enabled_pch(pipe_C_crtc)) {
3089                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3090                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3091 
3092                 temp = I915_READ(SOUTH_CHICKEN1);
3093                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3094                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3095                 I915_WRITE(SOUTH_CHICKEN1, temp);
3096         }
3097 }
3098 
3099 /* The FDI link training functions for ILK/Ibexpeak. */
3100 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3101 {
3102         struct drm_device *dev = crtc->dev;
3103         struct drm_i915_private *dev_priv = dev->dev_private;
3104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3105         int pipe = intel_crtc->pipe;
3106         u32 reg, temp, tries;
3107 
3108         /* FDI needs bits from pipe first */
3109         assert_pipe_enabled(dev_priv, pipe);
3110 
3111         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3112            for train result */
3113         reg = FDI_RX_IMR(pipe);
3114         temp = I915_READ(reg);
3115         temp &= ~FDI_RX_SYMBOL_LOCK;
3116         temp &= ~FDI_RX_BIT_LOCK;
3117         I915_WRITE(reg, temp);
3118         I915_READ(reg);
3119         udelay(150);
3120 
3121         /* enable CPU FDI TX and PCH FDI RX */
3122         reg = FDI_TX_CTL(pipe);
3123         temp = I915_READ(reg);
3124         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3125         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3126         temp &= ~FDI_LINK_TRAIN_NONE;
3127         temp |= FDI_LINK_TRAIN_PATTERN_1;
3128         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3129 
3130         reg = FDI_RX_CTL(pipe);
3131         temp = I915_READ(reg);
3132         temp &= ~FDI_LINK_TRAIN_NONE;
3133         temp |= FDI_LINK_TRAIN_PATTERN_1;
3134         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3135 
3136         POSTING_READ(reg);
3137         udelay(150);
3138 
3139         /* Ironlake workaround, enable clock pointer after FDI enable*/
3140         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3141         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3142                    FDI_RX_PHASE_SYNC_POINTER_EN);
3143 
3144         reg = FDI_RX_IIR(pipe);
3145         for (tries = 0; tries < 5; tries++) {
3146                 temp = I915_READ(reg);
3147                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3148 
3149                 if ((temp & FDI_RX_BIT_LOCK)) {
3150                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3151                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3152                         break;
3153                 }
3154         }
3155         if (tries == 5)
3156                 DRM_ERROR("FDI train 1 fail!\n");
3157 
3158         /* Train 2 */
3159         reg = FDI_TX_CTL(pipe);
3160         temp = I915_READ(reg);
3161         temp &= ~FDI_LINK_TRAIN_NONE;
3162         temp |= FDI_LINK_TRAIN_PATTERN_2;
3163         I915_WRITE(reg, temp);
3164 
3165         reg = FDI_RX_CTL(pipe);
3166         temp = I915_READ(reg);
3167         temp &= ~FDI_LINK_TRAIN_NONE;
3168         temp |= FDI_LINK_TRAIN_PATTERN_2;
3169         I915_WRITE(reg, temp);
3170 
3171         POSTING_READ(reg);
3172         udelay(150);
3173 
3174         reg = FDI_RX_IIR(pipe);
3175         for (tries = 0; tries < 5; tries++) {
3176                 temp = I915_READ(reg);
3177                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3178 
3179                 if (temp & FDI_RX_SYMBOL_LOCK) {
3180                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3181                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3182                         break;
3183                 }
3184         }
3185         if (tries == 5)
3186                 DRM_ERROR("FDI train 2 fail!\n");
3187 
3188         DRM_DEBUG_KMS("FDI train done\n");
3189 
3190 }
3191 
3192 static const int snb_b_fdi_train_param[] = {
3193         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3194         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3195         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3196         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3197 };
3198 
3199 /* The FDI link training functions for SNB/Cougarpoint. */
3200 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205         int pipe = intel_crtc->pipe;
3206         u32 reg, temp, i, retry;
3207 
3208         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3209            for train result */
3210         reg = FDI_RX_IMR(pipe);
3211         temp = I915_READ(reg);
3212         temp &= ~FDI_RX_SYMBOL_LOCK;
3213         temp &= ~FDI_RX_BIT_LOCK;
3214         I915_WRITE(reg, temp);
3215 
3216         POSTING_READ(reg);
3217         udelay(150);
3218 
3219         /* enable CPU FDI TX and PCH FDI RX */
3220         reg = FDI_TX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3223         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3224         temp &= ~FDI_LINK_TRAIN_NONE;
3225         temp |= FDI_LINK_TRAIN_PATTERN_1;
3226         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3227         /* SNB-B */
3228         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3229         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3230 
3231         I915_WRITE(FDI_RX_MISC(pipe),
3232                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3233 
3234         reg = FDI_RX_CTL(pipe);
3235         temp = I915_READ(reg);
3236         if (HAS_PCH_CPT(dev)) {
3237                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3238                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3239         } else {
3240                 temp &= ~FDI_LINK_TRAIN_NONE;
3241                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3242         }
3243         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3244 
3245         POSTING_READ(reg);
3246         udelay(150);
3247 
3248         for (i = 0; i < 4; i++) {
3249                 reg = FDI_TX_CTL(pipe);
3250                 temp = I915_READ(reg);
3251                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3252                 temp |= snb_b_fdi_train_param[i];
3253                 I915_WRITE(reg, temp);
3254 
3255                 POSTING_READ(reg);
3256                 udelay(500);
3257 
3258                 for (retry = 0; retry < 5; retry++) {
3259                         reg = FDI_RX_IIR(pipe);
3260                         temp = I915_READ(reg);
3261                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3262                         if (temp & FDI_RX_BIT_LOCK) {
3263                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3264                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3265                                 break;
3266                         }
3267                         udelay(50);
3268                 }
3269                 if (retry < 5)
3270                         break;
3271         }
3272         if (i == 4)
3273                 DRM_ERROR("FDI train 1 fail!\n");
3274 
3275         /* Train 2 */
3276         reg = FDI_TX_CTL(pipe);
3277         temp = I915_READ(reg);
3278         temp &= ~FDI_LINK_TRAIN_NONE;
3279         temp |= FDI_LINK_TRAIN_PATTERN_2;
3280         if (IS_GEN6(dev)) {
3281                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3282                 /* SNB-B */
3283                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3284         }
3285         I915_WRITE(reg, temp);
3286 
3287         reg = FDI_RX_CTL(pipe);
3288         temp = I915_READ(reg);
3289         if (HAS_PCH_CPT(dev)) {
3290                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3291                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3292         } else {
3293                 temp &= ~FDI_LINK_TRAIN_NONE;
3294                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3295         }
3296         I915_WRITE(reg, temp);
3297 
3298         POSTING_READ(reg);
3299         udelay(150);
3300 
3301         for (i = 0; i < 4; i++) {
3302                 reg = FDI_TX_CTL(pipe);
3303                 temp = I915_READ(reg);
3304                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3305                 temp |= snb_b_fdi_train_param[i];
3306                 I915_WRITE(reg, temp);
3307 
3308                 POSTING_READ(reg);
3309                 udelay(500);
3310 
3311                 for (retry = 0; retry < 5; retry++) {
3312                         reg = FDI_RX_IIR(pipe);
3313                         temp = I915_READ(reg);
3314                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3315                         if (temp & FDI_RX_SYMBOL_LOCK) {
3316                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3317                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3318                                 break;
3319                         }
3320                         udelay(50);
3321                 }
3322                 if (retry < 5)
3323                         break;
3324         }
3325         if (i == 4)
3326                 DRM_ERROR("FDI train 2 fail!\n");
3327 
3328         DRM_DEBUG_KMS("FDI train done.\n");
3329 }
3330 
3331 /* Manual link training for Ivy Bridge A0 parts */
3332 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3333 {
3334         struct drm_device *dev = crtc->dev;
3335         struct drm_i915_private *dev_priv = dev->dev_private;
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         int pipe = intel_crtc->pipe;
3338         u32 reg, temp, i, j;
3339 
3340         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3341            for train result */
3342         reg = FDI_RX_IMR(pipe);
3343         temp = I915_READ(reg);
3344         temp &= ~FDI_RX_SYMBOL_LOCK;
3345         temp &= ~FDI_RX_BIT_LOCK;
3346         I915_WRITE(reg, temp);
3347 
3348         POSTING_READ(reg);
3349         udelay(150);
3350 
3351         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3352                       I915_READ(FDI_RX_IIR(pipe)));
3353 
3354         /* Try each vswing and preemphasis setting twice before moving on */
3355         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3356                 /* disable first in case we need to retry */
3357                 reg = FDI_TX_CTL(pipe);
3358                 temp = I915_READ(reg);
3359                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3360                 temp &= ~FDI_TX_ENABLE;
3361                 I915_WRITE(reg, temp);
3362 
3363                 reg = FDI_RX_CTL(pipe);
3364                 temp = I915_READ(reg);
3365                 temp &= ~FDI_LINK_TRAIN_AUTO;
3366                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3367                 temp &= ~FDI_RX_ENABLE;
3368                 I915_WRITE(reg, temp);
3369 
3370                 /* enable CPU FDI TX and PCH FDI RX */
3371                 reg = FDI_TX_CTL(pipe);
3372                 temp = I915_READ(reg);
3373                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3374                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3375                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3376                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3377                 temp |= snb_b_fdi_train_param[j/2];
3378                 temp |= FDI_COMPOSITE_SYNC;
3379                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3380 
3381                 I915_WRITE(FDI_RX_MISC(pipe),
3382                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3383 
3384                 reg = FDI_RX_CTL(pipe);
3385                 temp = I915_READ(reg);
3386                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3387                 temp |= FDI_COMPOSITE_SYNC;
3388                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3389 
3390                 POSTING_READ(reg);
3391                 udelay(1); /* should be 0.5us */
3392 
3393                 for (i = 0; i < 4; i++) {
3394                         reg = FDI_RX_IIR(pipe);
3395                         temp = I915_READ(reg);
3396                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3397 
3398                         if (temp & FDI_RX_BIT_LOCK ||
3399                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3400                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3401                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3402                                               i);
3403                                 break;
3404                         }
3405                         udelay(1); /* should be 0.5us */
3406                 }
3407                 if (i == 4) {
3408                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3409                         continue;
3410                 }
3411 
3412                 /* Train 2 */
3413                 reg = FDI_TX_CTL(pipe);
3414                 temp = I915_READ(reg);
3415                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3416                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3417                 I915_WRITE(reg, temp);
3418 
3419                 reg = FDI_RX_CTL(pipe);
3420                 temp = I915_READ(reg);
3421                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3422                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3423                 I915_WRITE(reg, temp);
3424 
3425                 POSTING_READ(reg);
3426                 udelay(2); /* should be 1.5us */
3427 
3428                 for (i = 0; i < 4; i++) {
3429                         reg = FDI_RX_IIR(pipe);
3430                         temp = I915_READ(reg);
3431                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3432 
3433                         if (temp & FDI_RX_SYMBOL_LOCK ||
3434                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3435                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3436                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3437                                               i);
3438                                 goto train_done;
3439                         }
3440                         udelay(2); /* should be 1.5us */
3441                 }
3442                 if (i == 4)
3443                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3444         }
3445 
3446 train_done:
3447         DRM_DEBUG_KMS("FDI train done.\n");
3448 }
3449 
3450 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3451 {
3452         struct drm_device *dev = intel_crtc->base.dev;
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456 
3457 
3458         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3462         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3463         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3464         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3465 
3466         POSTING_READ(reg);
3467         udelay(200);
3468 
3469         /* Switch from Rawclk to PCDclk */
3470         temp = I915_READ(reg);
3471         I915_WRITE(reg, temp | FDI_PCDCLK);
3472 
3473         POSTING_READ(reg);
3474         udelay(200);
3475 
3476         /* Enable CPU FDI TX PLL, always on for Ironlake */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3480                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3481 
3482                 POSTING_READ(reg);
3483                 udelay(100);
3484         }
3485 }
3486 
3487 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3488 {
3489         struct drm_device *dev = intel_crtc->base.dev;
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         int pipe = intel_crtc->pipe;
3492         u32 reg, temp;
3493 
3494         /* Switch from PCDclk to Rawclk */
3495         reg = FDI_RX_CTL(pipe);
3496         temp = I915_READ(reg);
3497         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3498 
3499         /* Disable CPU FDI TX PLL */
3500         reg = FDI_TX_CTL(pipe);
3501         temp = I915_READ(reg);
3502         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3503 
3504         POSTING_READ(reg);
3505         udelay(100);
3506 
3507         reg = FDI_RX_CTL(pipe);
3508         temp = I915_READ(reg);
3509         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3510 
3511         /* Wait for the clocks to turn off. */
3512         POSTING_READ(reg);
3513         udelay(100);
3514 }
3515 
3516 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3517 {
3518         struct drm_device *dev = crtc->dev;
3519         struct drm_i915_private *dev_priv = dev->dev_private;
3520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3521         int pipe = intel_crtc->pipe;
3522         u32 reg, temp;
3523 
3524         /* disable CPU FDI tx and PCH FDI rx */
3525         reg = FDI_TX_CTL(pipe);
3526         temp = I915_READ(reg);
3527         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3528         POSTING_READ(reg);
3529 
3530         reg = FDI_RX_CTL(pipe);
3531         temp = I915_READ(reg);
3532         temp &= ~(0x7 << 16);
3533         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3534         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3535 
3536         POSTING_READ(reg);
3537         udelay(100);
3538 
3539         /* Ironlake workaround, disable clock pointer after downing FDI */
3540         if (HAS_PCH_IBX(dev))
3541                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3542 
3543         /* still set train pattern 1 */
3544         reg = FDI_TX_CTL(pipe);
3545         temp = I915_READ(reg);
3546         temp &= ~FDI_LINK_TRAIN_NONE;
3547         temp |= FDI_LINK_TRAIN_PATTERN_1;
3548         I915_WRITE(reg, temp);
3549 
3550         reg = FDI_RX_CTL(pipe);
3551         temp = I915_READ(reg);
3552         if (HAS_PCH_CPT(dev)) {
3553                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3554                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3555         } else {
3556                 temp &= ~FDI_LINK_TRAIN_NONE;
3557                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3558         }
3559         /* BPC in FDI rx is consistent with that in PIPECONF */
3560         temp &= ~(0x07 << 16);
3561         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3562         I915_WRITE(reg, temp);
3563 
3564         POSTING_READ(reg);
3565         udelay(100);
3566 }
3567 
3568 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3569 {
3570         struct intel_crtc *crtc;
3571 
3572         /* Note that we don't need to be called with mode_config.lock here
3573          * as our list of CRTC objects is static for the lifetime of the
3574          * device and so cannot disappear as we iterate. Similarly, we can
3575          * happily treat the predicates as racy, atomic checks as userspace
3576          * cannot claim and pin a new fb without at least acquring the
3577          * struct_mutex and so serialising with us.
3578          */
3579         for_each_intel_crtc(dev, crtc) {
3580                 if (atomic_read(&crtc->unpin_work_count) == 0)
3581                         continue;
3582 
3583                 if (crtc->unpin_work)
3584                         intel_wait_for_vblank(dev, crtc->pipe);
3585 
3586                 return true;
3587         }
3588 
3589         return false;
3590 }
3591 
3592 static void page_flip_completed(struct intel_crtc *intel_crtc)
3593 {
3594         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3595         struct intel_unpin_work *work = intel_crtc->unpin_work;
3596 
3597         /* ensure that the unpin work is consistent wrt ->pending. */
3598         smp_rmb();
3599         intel_crtc->unpin_work = NULL;
3600 
3601         if (work->event)
3602                 drm_send_vblank_event(intel_crtc->base.dev,
3603                                       intel_crtc->pipe,
3604                                       work->event);
3605 
3606         drm_crtc_vblank_put(&intel_crtc->base);
3607 
3608         wake_up_all(&dev_priv->pending_flip_queue);
3609         queue_work(dev_priv->wq, &work->work);
3610 
3611         trace_i915_flip_complete(intel_crtc->plane,
3612                                  work->pending_flip_obj);
3613 }
3614 
3615 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3616 {
3617         struct drm_device *dev = crtc->dev;
3618         struct drm_i915_private *dev_priv = dev->dev_private;
3619 
3620         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3621         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3622                                        !intel_crtc_has_pending_flip(crtc),
3623                                        60*HZ) == 0)) {
3624                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625 
3626                 spin_lock_irq(&dev->event_lock);
3627                 if (intel_crtc->unpin_work) {
3628                         WARN_ONCE(1, "Removing stuck page flip\n");
3629                         page_flip_completed(intel_crtc);
3630                 }
3631                 spin_unlock_irq(&dev->event_lock);
3632         }
3633 
3634         if (crtc->primary->fb) {
3635                 mutex_lock(&dev->struct_mutex);
3636                 intel_finish_fb(crtc->primary->fb);
3637                 mutex_unlock(&dev->struct_mutex);
3638         }
3639 }
3640 
3641 /* Program iCLKIP clock to the desired frequency */
3642 static void lpt_program_iclkip(struct drm_crtc *crtc)
3643 {
3644         struct drm_device *dev = crtc->dev;
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3647         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3648         u32 temp;
3649 
3650         mutex_lock(&dev_priv->dpio_lock);
3651 
3652         /* It is necessary to ungate the pixclk gate prior to programming
3653          * the divisors, and gate it back when it is done.
3654          */
3655         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3656 
3657         /* Disable SSCCTL */
3658         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3659                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3660                                 SBI_SSCCTL_DISABLE,
3661                         SBI_ICLK);
3662 
3663         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3664         if (clock == 20000) {
3665                 auxdiv = 1;
3666                 divsel = 0x41;
3667                 phaseinc = 0x20;
3668         } else {
3669                 /* The iCLK virtual clock root frequency is in MHz,
3670                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3671                  * divisors, it is necessary to divide one by another, so we
3672                  * convert the virtual clock precision to KHz here for higher
3673                  * precision.
3674                  */
3675                 u32 iclk_virtual_root_freq = 172800 * 1000;
3676                 u32 iclk_pi_range = 64;
3677                 u32 desired_divisor, msb_divisor_value, pi_value;
3678 
3679                 desired_divisor = (iclk_virtual_root_freq / clock);
3680                 msb_divisor_value = desired_divisor / iclk_pi_range;
3681                 pi_value = desired_divisor % iclk_pi_range;
3682 
3683                 auxdiv = 0;
3684                 divsel = msb_divisor_value - 2;
3685                 phaseinc = pi_value;
3686         }
3687 
3688         /* This should not happen with any sane values */
3689         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3690                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3691         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3692                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3693 
3694         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3695                         clock,
3696                         auxdiv,
3697                         divsel,
3698                         phasedir,
3699                         phaseinc);
3700 
3701         /* Program SSCDIVINTPHASE6 */
3702         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3703         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3704         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3705         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3706         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3707         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3708         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3709         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3710 
3711         /* Program SSCAUXDIV */
3712         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3713         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3714         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3715         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3716 
3717         /* Enable modulator and associated divider */
3718         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3719         temp &= ~SBI_SSCCTL_DISABLE;
3720         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3721 
3722         /* Wait for initialization time */
3723         udelay(24);
3724 
3725         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3726 
3727         mutex_unlock(&dev_priv->dpio_lock);
3728 }
3729 
3730 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3731                                                 enum pipe pch_transcoder)
3732 {
3733         struct drm_device *dev = crtc->base.dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3736 
3737         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3738                    I915_READ(HTOTAL(cpu_transcoder)));
3739         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3740                    I915_READ(HBLANK(cpu_transcoder)));
3741         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3742                    I915_READ(HSYNC(cpu_transcoder)));
3743 
3744         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3745                    I915_READ(VTOTAL(cpu_transcoder)));
3746         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3747                    I915_READ(VBLANK(cpu_transcoder)));
3748         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3749                    I915_READ(VSYNC(cpu_transcoder)));
3750         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3751                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3752 }
3753 
3754 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3755 {
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         uint32_t temp;
3758 
3759         temp = I915_READ(SOUTH_CHICKEN1);
3760         if (temp & FDI_BC_BIFURCATION_SELECT)
3761                 return;
3762 
3763         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3764         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3765 
3766         temp |= FDI_BC_BIFURCATION_SELECT;
3767         DRM_DEBUG_KMS("enabling fdi C rx\n");
3768         I915_WRITE(SOUTH_CHICKEN1, temp);
3769         POSTING_READ(SOUTH_CHICKEN1);
3770 }
3771 
3772 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3773 {
3774         struct drm_device *dev = intel_crtc->base.dev;
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776 
3777         switch (intel_crtc->pipe) {
3778         case PIPE_A:
3779                 break;
3780         case PIPE_B:
3781                 if (intel_crtc->config->fdi_lanes > 2)
3782                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3783                 else
3784                         cpt_enable_fdi_bc_bifurcation(dev);
3785 
3786                 break;
3787         case PIPE_C:
3788                 cpt_enable_fdi_bc_bifurcation(dev);
3789 
3790                 break;
3791         default:
3792                 BUG();
3793         }
3794 }
3795 
3796 /*
3797  * Enable PCH resources required for PCH ports:
3798  *   - PCH PLLs
3799  *   - FDI training & RX/TX
3800  *   - update transcoder timings
3801  *   - DP transcoding bits
3802  *   - transcoder
3803  */
3804 static void ironlake_pch_enable(struct drm_crtc *crtc)
3805 {
3806         struct drm_device *dev = crtc->dev;
3807         struct drm_i915_private *dev_priv = dev->dev_private;
3808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809         int pipe = intel_crtc->pipe;
3810         u32 reg, temp;
3811 
3812         assert_pch_transcoder_disabled(dev_priv, pipe);
3813 
3814         if (IS_IVYBRIDGE(dev))
3815                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3816 
3817         /* Write the TU size bits before fdi link training, so that error
3818          * detection works. */
3819         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3820                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3821 
3822         /* For PCH output, training FDI link */
3823         dev_priv->display.fdi_link_train(crtc);
3824 
3825         /* We need to program the right clock selection before writing the pixel
3826          * mutliplier into the DPLL. */
3827         if (HAS_PCH_CPT(dev)) {
3828                 u32 sel;
3829 
3830                 temp = I915_READ(PCH_DPLL_SEL);
3831                 temp |= TRANS_DPLL_ENABLE(pipe);
3832                 sel = TRANS_DPLLB_SEL(pipe);
3833                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3834                         temp |= sel;
3835                 else
3836                         temp &= ~sel;
3837                 I915_WRITE(PCH_DPLL_SEL, temp);
3838         }
3839 
3840         /* XXX: pch pll's can be enabled any time before we enable the PCH
3841          * transcoder, and we actually should do this to not upset any PCH
3842          * transcoder that already use the clock when we share it.
3843          *
3844          * Note that enable_shared_dpll tries to do the right thing, but
3845          * get_shared_dpll unconditionally resets the pll - we need that to have
3846          * the right LVDS enable sequence. */
3847         intel_enable_shared_dpll(intel_crtc);
3848 
3849         /* set transcoder timing, panel must allow it */
3850         assert_panel_unlocked(dev_priv, pipe);
3851         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3852 
3853         intel_fdi_normal_train(crtc);
3854 
3855         /* For PCH DP, enable TRANS_DP_CTL */
3856         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3857                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3858                 reg = TRANS_DP_CTL(pipe);
3859                 temp = I915_READ(reg);
3860                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3861                           TRANS_DP_SYNC_MASK |
3862                           TRANS_DP_BPC_MASK);
3863                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3864                          TRANS_DP_ENH_FRAMING);
3865                 temp |= bpc << 9; /* same format but at 11:9 */
3866 
3867                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3868                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3869                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3870                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3871 
3872                 switch (intel_trans_dp_port_sel(crtc)) {
3873                 case PCH_DP_B:
3874                         temp |= TRANS_DP_PORT_SEL_B;
3875                         break;
3876                 case PCH_DP_C:
3877                         temp |= TRANS_DP_PORT_SEL_C;
3878                         break;
3879                 case PCH_DP_D:
3880                         temp |= TRANS_DP_PORT_SEL_D;
3881                         break;
3882                 default:
3883                         BUG();
3884                 }
3885 
3886                 I915_WRITE(reg, temp);
3887         }
3888 
3889         ironlake_enable_pch_transcoder(dev_priv, pipe);
3890 }
3891 
3892 static void lpt_pch_enable(struct drm_crtc *crtc)
3893 {
3894         struct drm_device *dev = crtc->dev;
3895         struct drm_i915_private *dev_priv = dev->dev_private;
3896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3898 
3899         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3900 
3901         lpt_program_iclkip(crtc);
3902 
3903         /* Set transcoder timing. */
3904         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3905 
3906         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3907 }
3908 
3909 void intel_put_shared_dpll(struct intel_crtc *crtc)
3910 {
3911         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3912 
3913         if (pll == NULL)
3914                 return;
3915 
3916         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3917                 WARN(1, "bad %s crtc mask\n", pll->name);
3918                 return;
3919         }
3920 
3921         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3922         if (pll->config.crtc_mask == 0) {
3923                 WARN_ON(pll->on);
3924                 WARN_ON(pll->active);
3925         }
3926 
3927         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3928 }
3929 
3930 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3931                                                 struct intel_crtc_state *crtc_state)
3932 {
3933         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3934         struct intel_shared_dpll *pll;
3935         enum intel_dpll_id i;
3936 
3937         if (HAS_PCH_IBX(dev_priv->dev)) {
3938                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3939                 i = (enum intel_dpll_id) crtc->pipe;
3940                 pll = &dev_priv->shared_dplls[i];
3941 
3942                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3943                               crtc->base.base.id, pll->name);
3944 
3945                 WARN_ON(pll->new_config->crtc_mask);
3946 
3947                 goto found;
3948         }
3949 
3950         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3951                 pll = &dev_priv->shared_dplls[i];
3952 
3953                 /* Only want to check enabled timings first */
3954                 if (pll->new_config->crtc_mask == 0)
3955                         continue;
3956 
3957                 if (memcmp(&crtc_state->dpll_hw_state,
3958                            &pll->new_config->hw_state,
3959                            sizeof(pll->new_config->hw_state)) == 0) {
3960                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3961                                       crtc->base.base.id, pll->name,
3962                                       pll->new_config->crtc_mask,
3963                                       pll->active);
3964                         goto found;
3965                 }
3966         }
3967 
3968         /* Ok no matching timings, maybe there's a free one? */
3969         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3970                 pll = &dev_priv->shared_dplls[i];
3971                 if (pll->new_config->crtc_mask == 0) {
3972                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3973                                       crtc->base.base.id, pll->name);
3974                         goto found;
3975                 }
3976         }
3977 
3978         return NULL;
3979 
3980 found:
3981         if (pll->new_config->crtc_mask == 0)
3982                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3983 
3984         crtc_state->shared_dpll = i;
3985         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3986                          pipe_name(crtc->pipe));
3987 
3988         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3989 
3990         return pll;
3991 }
3992 
3993 /**
3994  * intel_shared_dpll_start_config - start a new PLL staged config
3995  * @dev_priv: DRM device
3996  * @clear_pipes: mask of pipes that will have their PLLs freed
3997  *
3998  * Starts a new PLL staged config, copying the current config but
3999  * releasing the references of pipes specified in clear_pipes.
4000  */
4001 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4002                                           unsigned clear_pipes)
4003 {
4004         struct intel_shared_dpll *pll;
4005         enum intel_dpll_id i;
4006 
4007         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4008                 pll = &dev_priv->shared_dplls[i];
4009 
4010                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4011                                           GFP_KERNEL);
4012                 if (!pll->new_config)
4013                         goto cleanup;
4014 
4015                 pll->new_config->crtc_mask &= ~clear_pipes;
4016         }
4017 
4018         return 0;
4019 
4020 cleanup:
4021         while (--i >= 0) {
4022                 pll = &dev_priv->shared_dplls[i];
4023                 kfree(pll->new_config);
4024                 pll->new_config = NULL;
4025         }
4026 
4027         return -ENOMEM;
4028 }
4029 
4030 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4031 {
4032         struct intel_shared_dpll *pll;
4033         enum intel_dpll_id i;
4034 
4035         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4036                 pll = &dev_priv->shared_dplls[i];
4037 
4038                 WARN_ON(pll->new_config == &pll->config);
4039 
4040                 pll->config = *pll->new_config;
4041                 kfree(pll->new_config);
4042                 pll->new_config = NULL;
4043         }
4044 }
4045 
4046 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4047 {
4048         struct intel_shared_dpll *pll;
4049         enum intel_dpll_id i;
4050 
4051         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4052                 pll = &dev_priv->shared_dplls[i];
4053 
4054                 WARN_ON(pll->new_config == &pll->config);
4055 
4056                 kfree(pll->new_config);
4057                 pll->new_config = NULL;
4058         }
4059 }
4060 
4061 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4062 {
4063         struct drm_i915_private *dev_priv = dev->dev_private;
4064         int dslreg = PIPEDSL(pipe);
4065         u32 temp;
4066 
4067         temp = I915_READ(dslreg);
4068         udelay(500);
4069         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4070                 if (wait_for(I915_READ(dslreg) != temp, 5))
4071                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4072         }
4073 }
4074 
4075 static void skylake_pfit_enable(struct intel_crtc *crtc)
4076 {
4077         struct drm_device *dev = crtc->base.dev;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         int pipe = crtc->pipe;
4080 
4081         if (crtc->config->pch_pfit.enabled) {
4082                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4083                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4084                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4085         }
4086 }
4087 
4088 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4089 {
4090         struct drm_device *dev = crtc->base.dev;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092         int pipe = crtc->pipe;
4093 
4094         if (crtc->config->pch_pfit.enabled) {
4095                 /* Force use of hard-coded filter coefficients
4096                  * as some pre-programmed values are broken,
4097                  * e.g. x201.
4098                  */
4099                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4100                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4101                                                  PF_PIPE_SEL_IVB(pipe));
4102                 else
4103                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4104                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4105                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4106         }
4107 }
4108 
4109 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4110 {
4111         struct drm_device *dev = crtc->dev;
4112         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4113         struct drm_plane *plane;
4114         struct intel_plane *intel_plane;
4115 
4116         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4117                 intel_plane = to_intel_plane(plane);
4118                 if (intel_plane->pipe == pipe)
4119                         intel_plane_restore(&intel_plane->base);
4120         }
4121 }
4122 
4123 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4124 {
4125         struct drm_device *dev = crtc->dev;
4126         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4127         struct drm_plane *plane;
4128         struct intel_plane *intel_plane;
4129 
4130         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4131                 intel_plane = to_intel_plane(plane);
4132                 if (intel_plane->pipe == pipe)
4133                         plane->funcs->disable_plane(plane);
4134         }
4135 }
4136 
4137 void hsw_enable_ips(struct intel_crtc *crtc)
4138 {
4139         struct drm_device *dev = crtc->base.dev;
4140         struct drm_i915_private *dev_priv = dev->dev_private;
4141 
4142         if (!crtc->config->ips_enabled)
4143                 return;
4144 
4145         /* We can only enable IPS after we enable a plane and wait for a vblank */
4146         intel_wait_for_vblank(dev, crtc->pipe);
4147 
4148         assert_plane_enabled(dev_priv, crtc->plane);
4149         if (IS_BROADWELL(dev)) {
4150                 mutex_lock(&dev_priv->rps.hw_lock);
4151                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4152                 mutex_unlock(&dev_priv->rps.hw_lock);
4153                 /* Quoting Art Runyan: "its not safe to expect any particular
4154                  * value in IPS_CTL bit 31 after enabling IPS through the
4155                  * mailbox." Moreover, the mailbox may return a bogus state,
4156                  * so we need to just enable it and continue on.
4157                  */
4158         } else {
4159                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4160                 /* The bit only becomes 1 in the next vblank, so this wait here
4161                  * is essentially intel_wait_for_vblank. If we don't have this
4162                  * and don't wait for vblanks until the end of crtc_enable, then
4163                  * the HW state readout code will complain that the expected
4164                  * IPS_CTL value is not the one we read. */
4165                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4166                         DRM_ERROR("Timed out waiting for IPS enable\n");
4167         }
4168 }
4169 
4170 void hsw_disable_ips(struct intel_crtc *crtc)
4171 {
4172         struct drm_device *dev = crtc->base.dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174 
4175         if (!crtc->config->ips_enabled)
4176                 return;
4177 
4178         assert_plane_enabled(dev_priv, crtc->plane);
4179         if (IS_BROADWELL(dev)) {
4180                 mutex_lock(&dev_priv->rps.hw_lock);
4181                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4182                 mutex_unlock(&dev_priv->rps.hw_lock);
4183                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4184                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4185                         DRM_ERROR("Timed out waiting for IPS disable\n");
4186         } else {
4187                 I915_WRITE(IPS_CTL, 0);
4188                 POSTING_READ(IPS_CTL);
4189         }
4190 
4191         /* We need to wait for a vblank before we can disable the plane. */
4192         intel_wait_for_vblank(dev, crtc->pipe);
4193 }
4194 
4195 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4196 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4197 {
4198         struct drm_device *dev = crtc->dev;
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201         enum pipe pipe = intel_crtc->pipe;
4202         int palreg = PALETTE(pipe);
4203         int i;
4204         bool reenable_ips = false;
4205 
4206         /* The clocks have to be on to load the palette. */
4207         if (!crtc->enabled || !intel_crtc->active)
4208                 return;
4209 
4210         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4211                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4212                         assert_dsi_pll_enabled(dev_priv);
4213                 else
4214                         assert_pll_enabled(dev_priv, pipe);
4215         }
4216 
4217         /* use legacy palette for Ironlake */
4218         if (!HAS_GMCH_DISPLAY(dev))
4219                 palreg = LGC_PALETTE(pipe);
4220 
4221         /* Workaround : Do not read or write the pipe palette/gamma data while
4222          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4223          */
4224         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4225             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4226              GAMMA_MODE_MODE_SPLIT)) {
4227                 hsw_disable_ips(intel_crtc);
4228                 reenable_ips = true;
4229         }
4230 
4231         for (i = 0; i < 256; i++) {
4232                 I915_WRITE(palreg + 4 * i,
4233                            (intel_crtc->lut_r[i] << 16) |
4234                            (intel_crtc->lut_g[i] << 8) |
4235                            intel_crtc->lut_b[i]);
4236         }
4237 
4238         if (reenable_ips)
4239                 hsw_enable_ips(intel_crtc);
4240 }
4241 
4242 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4243 {
4244         if (!enable && intel_crtc->overlay) {
4245                 struct drm_device *dev = intel_crtc->base.dev;
4246                 struct drm_i915_private *dev_priv = dev->dev_private;
4247 
4248                 mutex_lock(&dev->struct_mutex);
4249                 dev_priv->mm.interruptible = false;
4250                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4251                 dev_priv->mm.interruptible = true;
4252                 mutex_unlock(&dev->struct_mutex);
4253         }
4254 
4255         /* Let userspace switch the overlay on again. In most cases userspace
4256          * has to recompute where to put it anyway.
4257          */
4258 }
4259 
4260 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4261 {
4262         struct drm_device *dev = crtc->dev;
4263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4264         int pipe = intel_crtc->pipe;
4265 
4266         intel_enable_primary_hw_plane(crtc->primary, crtc);
4267         intel_enable_sprite_planes(crtc);
4268         intel_crtc_update_cursor(crtc, true);
4269         intel_crtc_dpms_overlay(intel_crtc, true);
4270 
4271         hsw_enable_ips(intel_crtc);
4272 
4273         mutex_lock(&dev->struct_mutex);
4274         intel_fbc_update(dev);
4275         mutex_unlock(&dev->struct_mutex);
4276 
4277         /*
4278          * FIXME: Once we grow proper nuclear flip support out of this we need
4279          * to compute the mask of flip planes precisely. For the time being
4280          * consider this a flip from a NULL plane.
4281          */
4282         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4283 }
4284 
4285 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4286 {
4287         struct drm_device *dev = crtc->dev;
4288         struct drm_i915_private *dev_priv = dev->dev_private;
4289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4290         int pipe = intel_crtc->pipe;
4291         int plane = intel_crtc->plane;
4292 
4293         intel_crtc_wait_for_pending_flips(crtc);
4294 
4295         if (dev_priv->fbc.plane == plane)
4296                 intel_fbc_disable(dev);
4297 
4298         hsw_disable_ips(intel_crtc);
4299 
4300         intel_crtc_dpms_overlay(intel_crtc, false);
4301         intel_crtc_update_cursor(crtc, false);
4302         intel_disable_sprite_planes(crtc);
4303         intel_disable_primary_hw_plane(crtc->primary, crtc);
4304 
4305         /*
4306          * FIXME: Once we grow proper nuclear flip support out of this we need
4307          * to compute the mask of flip planes precisely. For the time being
4308          * consider this a flip to a NULL plane.
4309          */
4310         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4311 }
4312 
4313 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4314 {
4315         struct drm_device *dev = crtc->dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4318         struct intel_encoder *encoder;
4319         int pipe = intel_crtc->pipe;
4320 
4321         WARN_ON(!crtc->enabled);
4322 
4323         if (intel_crtc->active)
4324                 return;
4325 
4326         if (intel_crtc->config->has_pch_encoder)
4327                 intel_prepare_shared_dpll(intel_crtc);
4328 
4329         if (intel_crtc->config->has_dp_encoder)
4330                 intel_dp_set_m_n(intel_crtc);
4331 
4332         intel_set_pipe_timings(intel_crtc);
4333 
4334         if (intel_crtc->config->has_pch_encoder) {
4335                 intel_cpu_transcoder_set_m_n(intel_crtc,
4336                                      &intel_crtc->config->fdi_m_n, NULL);
4337         }
4338 
4339         ironlake_set_pipeconf(crtc);
4340 
4341         intel_crtc->active = true;
4342 
4343         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4344         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4345 
4346         for_each_encoder_on_crtc(dev, crtc, encoder)
4347                 if (encoder->pre_enable)
4348                         encoder->pre_enable(encoder);
4349 
4350         if (intel_crtc->config->has_pch_encoder) {
4351                 /* Note: FDI PLL enabling _must_ be done before we enable the
4352                  * cpu pipes, hence this is separate from all the other fdi/pch
4353                  * enabling. */
4354                 ironlake_fdi_pll_enable(intel_crtc);
4355         } else {
4356                 assert_fdi_tx_disabled(dev_priv, pipe);
4357                 assert_fdi_rx_disabled(dev_priv, pipe);
4358         }
4359 
4360         ironlake_pfit_enable(intel_crtc);
4361 
4362         /*
4363          * On ILK+ LUT must be loaded before the pipe is running but with
4364          * clocks enabled
4365          */
4366         intel_crtc_load_lut(crtc);
4367 
4368         intel_update_watermarks(crtc);
4369         intel_enable_pipe(intel_crtc);
4370 
4371         if (intel_crtc->config->has_pch_encoder)
4372                 ironlake_pch_enable(crtc);
4373 
4374         assert_vblank_disabled(crtc);
4375         drm_crtc_vblank_on(crtc);
4376 
4377         for_each_encoder_on_crtc(dev, crtc, encoder)
4378                 encoder->enable(encoder);
4379 
4380         if (HAS_PCH_CPT(dev))
4381                 cpt_verify_modeset(dev, intel_crtc->pipe);
4382 
4383         intel_crtc_enable_planes(crtc);
4384 }
4385 
4386 /* IPS only exists on ULT machines and is tied to pipe A. */
4387 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4388 {
4389         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4390 }
4391 
4392 /*
4393  * This implements the workaround described in the "notes" section of the mode
4394  * set sequence documentation. When going from no pipes or single pipe to
4395  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4396  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4397  */
4398 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4399 {
4400         struct drm_device *dev = crtc->base.dev;
4401         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4402 
4403         /* We want to get the other_active_crtc only if there's only 1 other
4404          * active crtc. */
4405         for_each_intel_crtc(dev, crtc_it) {
4406                 if (!crtc_it->active || crtc_it == crtc)
4407                         continue;
4408 
4409                 if (other_active_crtc)
4410                         return;
4411 
4412                 other_active_crtc = crtc_it;
4413         }
4414         if (!other_active_crtc)
4415                 return;
4416 
4417         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4418         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4419 }
4420 
4421 static void haswell_crtc_enable(struct drm_crtc *crtc)
4422 {
4423         struct drm_device *dev = crtc->dev;
4424         struct drm_i915_private *dev_priv = dev->dev_private;
4425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4426         struct intel_encoder *encoder;
4427         int pipe = intel_crtc->pipe;
4428 
4429         WARN_ON(!crtc->enabled);
4430 
4431         if (intel_crtc->active)
4432                 return;
4433 
4434         if (intel_crtc_to_shared_dpll(intel_crtc))
4435                 intel_enable_shared_dpll(intel_crtc);
4436 
4437         if (intel_crtc->config->has_dp_encoder)
4438                 intel_dp_set_m_n(intel_crtc);
4439 
4440         intel_set_pipe_timings(intel_crtc);
4441 
4442         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4443                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4444                            intel_crtc->config->pixel_multiplier - 1);
4445         }
4446 
4447         if (intel_crtc->config->has_pch_encoder) {
4448                 intel_cpu_transcoder_set_m_n(intel_crtc,
4449                                      &intel_crtc->config->fdi_m_n, NULL);
4450         }
4451 
4452         haswell_set_pipeconf(crtc);
4453 
4454         intel_set_pipe_csc(crtc);
4455 
4456         intel_crtc->active = true;
4457 
4458         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4459         for_each_encoder_on_crtc(dev, crtc, encoder)
4460                 if (encoder->pre_enable)
4461                         encoder->pre_enable(encoder);
4462 
4463         if (intel_crtc->config->has_pch_encoder) {
4464                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4465                                                       true);
4466                 dev_priv->display.fdi_link_train(crtc);
4467         }
4468 
4469         intel_ddi_enable_pipe_clock(intel_crtc);
4470 
4471         if (IS_SKYLAKE(dev))
4472                 skylake_pfit_enable(intel_crtc);
4473         else
4474                 ironlake_pfit_enable(intel_crtc);
4475 
4476         /*
4477          * On ILK+ LUT must be loaded before the pipe is running but with
4478          * clocks enabled
4479          */
4480         intel_crtc_load_lut(crtc);
4481 
4482         intel_ddi_set_pipe_settings(crtc);
4483         intel_ddi_enable_transcoder_func(crtc);
4484 
4485         intel_update_watermarks(crtc);
4486         intel_enable_pipe(intel_crtc);
4487 
4488         if (intel_crtc->config->has_pch_encoder)
4489                 lpt_pch_enable(crtc);
4490 
4491         if (intel_crtc->config->dp_encoder_is_mst)
4492                 intel_ddi_set_vc_payload_alloc(crtc, true);
4493 
4494         assert_vblank_disabled(crtc);
4495         drm_crtc_vblank_on(crtc);
4496 
4497         for_each_encoder_on_crtc(dev, crtc, encoder) {
4498                 encoder->enable(encoder);
4499                 intel_opregion_notify_encoder(encoder, true);
4500         }
4501 
4502         /* If we change the relative order between pipe/planes enabling, we need
4503          * to change the workaround. */
4504         haswell_mode_set_planes_workaround(intel_crtc);
4505         intel_crtc_enable_planes(crtc);
4506 }
4507 
4508 static void skylake_pfit_disable(struct intel_crtc *crtc)
4509 {
4510         struct drm_device *dev = crtc->base.dev;
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512         int pipe = crtc->pipe;
4513 
4514         /* To avoid upsetting the power well on haswell only disable the pfit if
4515          * it's in use. The hw state code will make sure we get this right. */
4516         if (crtc->config->pch_pfit.enabled) {
4517                 I915_WRITE(PS_CTL(pipe), 0);
4518                 I915_WRITE(PS_WIN_POS(pipe), 0);
4519                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4520         }
4521 }
4522 
4523 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4524 {
4525         struct drm_device *dev = crtc->base.dev;
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         int pipe = crtc->pipe;
4528 
4529         /* To avoid upsetting the power well on haswell only disable the pfit if
4530          * it's in use. The hw state code will make sure we get this right. */
4531         if (crtc->config->pch_pfit.enabled) {
4532                 I915_WRITE(PF_CTL(pipe), 0);
4533                 I915_WRITE(PF_WIN_POS(pipe), 0);
4534                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4535         }
4536 }
4537 
4538 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4539 {
4540         struct drm_device *dev = crtc->dev;
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4543         struct intel_encoder *encoder;
4544         int pipe = intel_crtc->pipe;
4545         u32 reg, temp;
4546 
4547         if (!intel_crtc->active)
4548                 return;
4549 
4550         intel_crtc_disable_planes(crtc);
4551 
4552         for_each_encoder_on_crtc(dev, crtc, encoder)
4553                 encoder->disable(encoder);
4554 
4555         drm_crtc_vblank_off(crtc);
4556         assert_vblank_disabled(crtc);
4557 
4558         if (intel_crtc->config->has_pch_encoder)
4559                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4560 
4561         intel_disable_pipe(intel_crtc);
4562 
4563         ironlake_pfit_disable(intel_crtc);
4564 
4565         for_each_encoder_on_crtc(dev, crtc, encoder)
4566                 if (encoder->post_disable)
4567                         encoder->post_disable(encoder);
4568 
4569         if (intel_crtc->config->has_pch_encoder) {
4570                 ironlake_fdi_disable(crtc);
4571 
4572                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4573 
4574                 if (HAS_PCH_CPT(dev)) {
4575                         /* disable TRANS_DP_CTL */
4576                         reg = TRANS_DP_CTL(pipe);
4577                         temp = I915_READ(reg);
4578                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4579                                   TRANS_DP_PORT_SEL_MASK);
4580                         temp |= TRANS_DP_PORT_SEL_NONE;
4581                         I915_WRITE(reg, temp);
4582 
4583                         /* disable DPLL_SEL */
4584                         temp = I915_READ(PCH_DPLL_SEL);
4585                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4586                         I915_WRITE(PCH_DPLL_SEL, temp);
4587                 }
4588 
4589                 /* disable PCH DPLL */
4590                 intel_disable_shared_dpll(intel_crtc);
4591 
4592                 ironlake_fdi_pll_disable(intel_crtc);
4593         }
4594 
4595         intel_crtc->active = false;
4596         intel_update_watermarks(crtc);
4597 
4598         mutex_lock(&dev->struct_mutex);
4599         intel_fbc_update(dev);
4600         mutex_unlock(&dev->struct_mutex);
4601 }
4602 
4603 static void haswell_crtc_disable(struct drm_crtc *crtc)
4604 {
4605         struct drm_device *dev = crtc->dev;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4608         struct intel_encoder *encoder;
4609         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4610 
4611         if (!intel_crtc->active)
4612                 return;
4613 
4614         intel_crtc_disable_planes(crtc);
4615 
4616         for_each_encoder_on_crtc(dev, crtc, encoder) {
4617                 intel_opregion_notify_encoder(encoder, false);
4618                 encoder->disable(encoder);
4619         }
4620 
4621         drm_crtc_vblank_off(crtc);
4622         assert_vblank_disabled(crtc);
4623 
4624         if (intel_crtc->config->has_pch_encoder)
4625                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4626                                                       false);
4627         intel_disable_pipe(intel_crtc);
4628 
4629         if (intel_crtc->config->dp_encoder_is_mst)
4630                 intel_ddi_set_vc_payload_alloc(crtc, false);
4631 
4632         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4633 
4634         if (IS_SKYLAKE(dev))
4635                 skylake_pfit_disable(intel_crtc);
4636         else
4637                 ironlake_pfit_disable(intel_crtc);
4638 
4639         intel_ddi_disable_pipe_clock(intel_crtc);
4640 
4641         if (intel_crtc->config->has_pch_encoder) {
4642                 lpt_disable_pch_transcoder(dev_priv);
4643                 intel_ddi_fdi_disable(crtc);
4644         }
4645 
4646         for_each_encoder_on_crtc(dev, crtc, encoder)
4647                 if (encoder->post_disable)
4648                         encoder->post_disable(encoder);
4649 
4650         intel_crtc->active = false;
4651         intel_update_watermarks(crtc);
4652 
4653         mutex_lock(&dev->struct_mutex);
4654         intel_fbc_update(dev);
4655         mutex_unlock(&dev->struct_mutex);
4656 
4657         if (intel_crtc_to_shared_dpll(intel_crtc))
4658                 intel_disable_shared_dpll(intel_crtc);
4659 }
4660 
4661 static void ironlake_crtc_off(struct drm_crtc *crtc)
4662 {
4663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664         intel_put_shared_dpll(intel_crtc);
4665 }
4666 
4667 
4668 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4669 {
4670         struct drm_device *dev = crtc->base.dev;
4671         struct drm_i915_private *dev_priv = dev->dev_private;
4672         struct intel_crtc_state *pipe_config = crtc->config;
4673 
4674         if (!pipe_config->gmch_pfit.control)
4675                 return;
4676 
4677         /*
4678          * The panel fitter should only be adjusted whilst the pipe is disabled,
4679          * according to register description and PRM.
4680          */
4681         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4682         assert_pipe_disabled(dev_priv, crtc->pipe);
4683 
4684         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4685         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4686 
4687         /* Border color in case we don't scale up to the full screen. Black by
4688          * default, change to something else for debugging. */
4689         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4690 }
4691 
4692 static enum intel_display_power_domain port_to_power_domain(enum port port)
4693 {
4694         switch (port) {
4695         case PORT_A:
4696                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4697         case PORT_B:
4698                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4699         case PORT_C:
4700                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4701         case PORT_D:
4702                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4703         default:
4704                 WARN_ON_ONCE(1);
4705                 return POWER_DOMAIN_PORT_OTHER;
4706         }
4707 }
4708 
4709 #define for_each_power_domain(domain, mask)                             \
4710         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4711                 if ((1 << (domain)) & (mask))
4712 
4713 enum intel_display_power_domain
4714 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4715 {
4716         struct drm_device *dev = intel_encoder->base.dev;
4717         struct intel_digital_port *intel_dig_port;
4718 
4719         switch (intel_encoder->type) {
4720         case INTEL_OUTPUT_UNKNOWN:
4721                 /* Only DDI platforms should ever use this output type */
4722                 WARN_ON_ONCE(!HAS_DDI(dev));
4723         case INTEL_OUTPUT_DISPLAYPORT:
4724         case INTEL_OUTPUT_HDMI:
4725         case INTEL_OUTPUT_EDP:
4726                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4727                 return port_to_power_domain(intel_dig_port->port);
4728         case INTEL_OUTPUT_DP_MST:
4729                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4730                 return port_to_power_domain(intel_dig_port->port);
4731         case INTEL_OUTPUT_ANALOG:
4732                 return POWER_DOMAIN_PORT_CRT;
4733         case INTEL_OUTPUT_DSI:
4734                 return POWER_DOMAIN_PORT_DSI;
4735         default:
4736                 return POWER_DOMAIN_PORT_OTHER;
4737         }
4738 }
4739 
4740 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4741 {
4742         struct drm_device *dev = crtc->dev;
4743         struct intel_encoder *intel_encoder;
4744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4745         enum pipe pipe = intel_crtc->pipe;
4746         unsigned long mask;
4747         enum transcoder transcoder;
4748 
4749         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4750 
4751         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4752         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4753         if (intel_crtc->config->pch_pfit.enabled ||
4754             intel_crtc->config->pch_pfit.force_thru)
4755                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4756 
4757         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4758                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4759 
4760         return mask;
4761 }
4762 
4763 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4764 {
4765         struct drm_i915_private *dev_priv = dev->dev_private;
4766         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4767         struct intel_crtc *crtc;
4768 
4769         /*
4770          * First get all needed power domains, then put all unneeded, to avoid
4771          * any unnecessary toggling of the power wells.
4772          */
4773         for_each_intel_crtc(dev, crtc) {
4774                 enum intel_display_power_domain domain;
4775 
4776                 if (!crtc->base.enabled)
4777                         continue;
4778 
4779                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4780 
4781                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4782                         intel_display_power_get(dev_priv, domain);
4783         }
4784 
4785         if (dev_priv->display.modeset_global_resources)
4786                 dev_priv->display.modeset_global_resources(dev);
4787 
4788         for_each_intel_crtc(dev, crtc) {
4789                 enum intel_display_power_domain domain;
4790 
4791                 for_each_power_domain(domain, crtc->enabled_power_domains)
4792                         intel_display_power_put(dev_priv, domain);
4793 
4794                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4795         }
4796 
4797         intel_display_set_init_power(dev_priv, false);
4798 }
4799 
4800 /* returns HPLL frequency in kHz */
4801 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4802 {
4803         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4804 
4805         /* Obtain SKU information */
4806         mutex_lock(&dev_priv->dpio_lock);
4807         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4808                 CCK_FUSE_HPLL_FREQ_MASK;
4809         mutex_unlock(&dev_priv->dpio_lock);
4810 
4811         return vco_freq[hpll_freq] * 1000;
4812 }
4813 
4814 static void vlv_update_cdclk(struct drm_device *dev)
4815 {
4816         struct drm_i915_private *dev_priv = dev->dev_private;
4817 
4818         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4819         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4820                          dev_priv->vlv_cdclk_freq);
4821 
4822         /*
4823          * Program the gmbus_freq based on the cdclk frequency.
4824          * BSpec erroneously claims we should aim for 4MHz, but
4825          * in fact 1MHz is the correct frequency.
4826          */
4827         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4828 }
4829 
4830 /* Adjust CDclk dividers to allow high res or save power if possible */
4831 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4832 {
4833         struct drm_i915_private *dev_priv = dev->dev_private;
4834         u32 val, cmd;
4835 
4836         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4837 
4838         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4839                 cmd = 2;
4840         else if (cdclk == 266667)
4841                 cmd = 1;
4842         else
4843                 cmd = 0;
4844 
4845         mutex_lock(&dev_priv->rps.hw_lock);
4846         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4847         val &= ~DSPFREQGUAR_MASK;
4848         val |= (cmd << DSPFREQGUAR_SHIFT);
4849         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4850         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4851                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4852                      50)) {
4853                 DRM_ERROR("timed out waiting for CDclk change\n");
4854         }
4855         mutex_unlock(&dev_priv->rps.hw_lock);
4856 
4857         if (cdclk == 400000) {
4858                 u32 divider;
4859 
4860                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4861 
4862                 mutex_lock(&dev_priv->dpio_lock);
4863                 /* adjust cdclk divider */
4864                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4865                 val &= ~DISPLAY_FREQUENCY_VALUES;
4866                 val |= divider;
4867                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4868 
4869                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4870                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4871                              50))
4872                         DRM_ERROR("timed out waiting for CDclk change\n");
4873                 mutex_unlock(&dev_priv->dpio_lock);
4874         }
4875 
4876         mutex_lock(&dev_priv->dpio_lock);
4877         /* adjust self-refresh exit latency value */
4878         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4879         val &= ~0x7f;
4880 
4881         /*
4882          * For high bandwidth configs, we set a higher latency in the bunit
4883          * so that the core display fetch happens in time to avoid underruns.
4884          */
4885         if (cdclk == 400000)
4886                 val |= 4500 / 250; /* 4.5 usec */
4887         else
4888                 val |= 3000 / 250; /* 3.0 usec */
4889         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4890         mutex_unlock(&dev_priv->dpio_lock);
4891 
4892         vlv_update_cdclk(dev);
4893 }
4894 
4895 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4896 {
4897         struct drm_i915_private *dev_priv = dev->dev_private;
4898         u32 val, cmd;
4899 
4900         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4901 
4902         switch (cdclk) {
4903         case 400000:
4904                 cmd = 3;
4905                 break;
4906         case 333333:
4907         case 320000:
4908                 cmd = 2;
4909                 break;
4910         case 266667:
4911                 cmd = 1;
4912                 break;
4913         case 200000:
4914                 cmd = 0;
4915                 break;
4916         default:
4917                 MISSING_CASE(cdclk);
4918                 return;
4919         }
4920 
4921         mutex_lock(&dev_priv->rps.hw_lock);
4922         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4923         val &= ~DSPFREQGUAR_MASK_CHV;
4924         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4925         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4926         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4927                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4928                      50)) {
4929                 DRM_ERROR("timed out waiting for CDclk change\n");
4930         }
4931         mutex_unlock(&dev_priv->rps.hw_lock);
4932 
4933         vlv_update_cdclk(dev);
4934 }
4935 
4936 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4937                                  int max_pixclk)
4938 {
4939         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4940 
4941         /* FIXME: Punit isn't quite ready yet */
4942         if (IS_CHERRYVIEW(dev_priv->dev))
4943                 return 400000;
4944 
4945         /*
4946          * Really only a few cases to deal with, as only 4 CDclks are supported:
4947          *   200MHz
4948          *   267MHz
4949          *   320/333MHz (depends on HPLL freq)
4950          *   400MHz
4951          * So we check to see whether we're above 90% of the lower bin and
4952          * adjust if needed.
4953          *
4954          * We seem to get an unstable or solid color picture at 200MHz.
4955          * Not sure what's wrong. For now use 200MHz only when all pipes
4956          * are off.
4957          */
4958         if (max_pixclk > freq_320*9/10)
4959                 return 400000;
4960         else if (max_pixclk > 266667*9/10)
4961                 return freq_320;
4962         else if (max_pixclk > 0)
4963                 return 266667;
4964         else
4965                 return 200000;
4966 }
4967 
4968 /* compute the max pixel clock for new configuration */
4969 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4970 {
4971         struct drm_device *dev = dev_priv->dev;
4972         struct intel_crtc *intel_crtc;
4973         int max_pixclk = 0;
4974 
4975         for_each_intel_crtc(dev, intel_crtc) {
4976                 if (intel_crtc->new_enabled)
4977                         max_pixclk = max(max_pixclk,
4978                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4979         }
4980 
4981         return max_pixclk;
4982 }
4983 
4984 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4985                                             unsigned *prepare_pipes)
4986 {
4987         struct drm_i915_private *dev_priv = dev->dev_private;
4988         struct intel_crtc *intel_crtc;
4989         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4990 
4991         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4992             dev_priv->vlv_cdclk_freq)
4993                 return;
4994 
4995         /* disable/enable all currently active pipes while we change cdclk */
4996         for_each_intel_crtc(dev, intel_crtc)
4997                 if (intel_crtc->base.enabled)
4998                         *prepare_pipes |= (1 << intel_crtc->pipe);
4999 }
5000 
5001 static void valleyview_modeset_global_resources(struct drm_device *dev)
5002 {
5003         struct drm_i915_private *dev_priv = dev->dev_private;
5004         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5005         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5006 
5007         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5008                 /*
5009                  * FIXME: We can end up here with all power domains off, yet
5010                  * with a CDCLK frequency other than the minimum. To account
5011                  * for this take the PIPE-A power domain, which covers the HW
5012                  * blocks needed for the following programming. This can be
5013                  * removed once it's guaranteed that we get here either with
5014                  * the minimum CDCLK set, or the required power domains
5015                  * enabled.
5016                  */
5017                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5018 
5019                 if (IS_CHERRYVIEW(dev))
5020                         cherryview_set_cdclk(dev, req_cdclk);
5021                 else
5022                         valleyview_set_cdclk(dev, req_cdclk);
5023 
5024                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5025         }
5026 }
5027 
5028 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5029 {
5030         struct drm_device *dev = crtc->dev;
5031         struct drm_i915_private *dev_priv = to_i915(dev);
5032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033         struct intel_encoder *encoder;
5034         int pipe = intel_crtc->pipe;
5035         bool is_dsi;
5036 
5037         WARN_ON(!crtc->enabled);
5038 
5039         if (intel_crtc->active)
5040                 return;
5041 
5042         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5043 
5044         if (!is_dsi) {
5045                 if (IS_CHERRYVIEW(dev))
5046                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5047                 else
5048                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5049         }
5050 
5051         if (intel_crtc->config->has_dp_encoder)
5052                 intel_dp_set_m_n(intel_crtc);
5053 
5054         intel_set_pipe_timings(intel_crtc);
5055 
5056         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5057                 struct drm_i915_private *dev_priv = dev->dev_private;
5058 
5059                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5060                 I915_WRITE(CHV_CANVAS(pipe), 0);
5061         }
5062 
5063         i9xx_set_pipeconf(intel_crtc);
5064 
5065         intel_crtc->active = true;
5066 
5067         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5068 
5069         for_each_encoder_on_crtc(dev, crtc, encoder)
5070                 if (encoder->pre_pll_enable)
5071                         encoder->pre_pll_enable(encoder);
5072 
5073         if (!is_dsi) {
5074                 if (IS_CHERRYVIEW(dev))
5075                         chv_enable_pll(intel_crtc, intel_crtc->config);
5076                 else
5077                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5078         }
5079 
5080         for_each_encoder_on_crtc(dev, crtc, encoder)
5081                 if (encoder->pre_enable)
5082                         encoder->pre_enable(encoder);
5083 
5084         i9xx_pfit_enable(intel_crtc);
5085 
5086         intel_crtc_load_lut(crtc);
5087 
5088         intel_update_watermarks(crtc);
5089         intel_enable_pipe(intel_crtc);
5090 
5091         assert_vblank_disabled(crtc);
5092         drm_crtc_vblank_on(crtc);
5093 
5094         for_each_encoder_on_crtc(dev, crtc, encoder)
5095                 encoder->enable(encoder);
5096 
5097         intel_crtc_enable_planes(crtc);
5098 
5099         /* Underruns don't raise interrupts, so check manually. */
5100         i9xx_check_fifo_underruns(dev_priv);
5101 }
5102 
5103 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5104 {
5105         struct drm_device *dev = crtc->base.dev;
5106         struct drm_i915_private *dev_priv = dev->dev_private;
5107 
5108         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5109         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5110 }
5111 
5112 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5113 {
5114         struct drm_device *dev = crtc->dev;
5115         struct drm_i915_private *dev_priv = to_i915(dev);
5116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5117         struct intel_encoder *encoder;
5118         int pipe = intel_crtc->pipe;
5119 
5120         WARN_ON(!crtc->enabled);
5121 
5122         if (intel_crtc->active)
5123                 return;
5124 
5125         i9xx_set_pll_dividers(intel_crtc);
5126 
5127         if (intel_crtc->config->has_dp_encoder)
5128                 intel_dp_set_m_n(intel_crtc);
5129 
5130         intel_set_pipe_timings(intel_crtc);
5131 
5132         i9xx_set_pipeconf(intel_crtc);
5133 
5134         intel_crtc->active = true;
5135 
5136         if (!IS_GEN2(dev))
5137                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5138 
5139         for_each_encoder_on_crtc(dev, crtc, encoder)
5140                 if (encoder->pre_enable)
5141                         encoder->pre_enable(encoder);
5142 
5143         i9xx_enable_pll(intel_crtc);
5144 
5145         i9xx_pfit_enable(intel_crtc);
5146 
5147         intel_crtc_load_lut(crtc);
5148 
5149         intel_update_watermarks(crtc);
5150         intel_enable_pipe(intel_crtc);
5151 
5152         assert_vblank_disabled(crtc);
5153         drm_crtc_vblank_on(crtc);
5154 
5155         for_each_encoder_on_crtc(dev, crtc, encoder)
5156                 encoder->enable(encoder);
5157 
5158         intel_crtc_enable_planes(crtc);
5159 
5160         /*
5161          * Gen2 reports pipe underruns whenever all planes are disabled.
5162          * So don't enable underrun reporting before at least some planes
5163          * are enabled.
5164          * FIXME: Need to fix the logic to work when we turn off all planes
5165          * but leave the pipe running.
5166          */
5167         if (IS_GEN2(dev))
5168                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5169 
5170         /* Underruns don't raise interrupts, so check manually. */
5171         i9xx_check_fifo_underruns(dev_priv);
5172 }
5173 
5174 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5175 {
5176         struct drm_device *dev = crtc->base.dev;
5177         struct drm_i915_private *dev_priv = dev->dev_private;
5178 
5179         if (!crtc->config->gmch_pfit.control)
5180                 return;
5181 
5182         assert_pipe_disabled(dev_priv, crtc->pipe);
5183 
5184         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5185                          I915_READ(PFIT_CONTROL));
5186         I915_WRITE(PFIT_CONTROL, 0);
5187 }
5188 
5189 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5190 {
5191         struct drm_device *dev = crtc->dev;
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194         struct intel_encoder *encoder;
5195         int pipe = intel_crtc->pipe;
5196 
5197         if (!intel_crtc->active)
5198                 return;
5199 
5200         /*
5201          * Gen2 reports pipe underruns whenever all planes are disabled.
5202          * So diasble underrun reporting before all the planes get disabled.
5203          * FIXME: Need to fix the logic to work when we turn off all planes
5204          * but leave the pipe running.
5205          */
5206         if (IS_GEN2(dev))
5207                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5208 
5209         /*
5210          * Vblank time updates from the shadow to live plane control register
5211          * are blocked if the memory self-refresh mode is active at that
5212          * moment. So to make sure the plane gets truly disabled, disable
5213          * first the self-refresh mode. The self-refresh enable bit in turn
5214          * will be checked/applied by the HW only at the next frame start
5215          * event which is after the vblank start event, so we need to have a
5216          * wait-for-vblank between disabling the plane and the pipe.
5217          */
5218         intel_set_memory_cxsr(dev_priv, false);
5219         intel_crtc_disable_planes(crtc);
5220 
5221         /*
5222          * On gen2 planes are double buffered but the pipe isn't, so we must
5223          * wait for planes to fully turn off before disabling the pipe.
5224          * We also need to wait on all gmch platforms because of the
5225          * self-refresh mode constraint explained above.
5226          */
5227         intel_wait_for_vblank(dev, pipe);
5228 
5229         for_each_encoder_on_crtc(dev, crtc, encoder)
5230                 encoder->disable(encoder);
5231 
5232         drm_crtc_vblank_off(crtc);
5233         assert_vblank_disabled(crtc);
5234 
5235         intel_disable_pipe(intel_crtc);
5236 
5237         i9xx_pfit_disable(intel_crtc);
5238 
5239         for_each_encoder_on_crtc(dev, crtc, encoder)
5240                 if (encoder->post_disable)
5241                         encoder->post_disable(encoder);
5242 
5243         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5244                 if (IS_CHERRYVIEW(dev))
5245                         chv_disable_pll(dev_priv, pipe);
5246                 else if (IS_VALLEYVIEW(dev))
5247                         vlv_disable_pll(dev_priv, pipe);
5248                 else
5249                         i9xx_disable_pll(intel_crtc);
5250         }
5251 
5252         if (!IS_GEN2(dev))
5253                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5254 
5255         intel_crtc->active = false;
5256         intel_update_watermarks(crtc);
5257 
5258         mutex_lock(&dev->struct_mutex);
5259         intel_fbc_update(dev);
5260         mutex_unlock(&dev->struct_mutex);
5261 }
5262 
5263 static void i9xx_crtc_off(struct drm_crtc *crtc)
5264 {
5265 }
5266 
5267 /* Master function to enable/disable CRTC and corresponding power wells */
5268 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5269 {
5270         struct drm_device *dev = crtc->dev;
5271         struct drm_i915_private *dev_priv = dev->dev_private;
5272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273         enum intel_display_power_domain domain;
5274         unsigned long domains;
5275 
5276         if (enable) {
5277                 if (!intel_crtc->active) {
5278                         domains = get_crtc_power_domains(crtc);
5279                         for_each_power_domain(domain, domains)
5280                                 intel_display_power_get(dev_priv, domain);
5281                         intel_crtc->enabled_power_domains = domains;
5282 
5283                         dev_priv->display.crtc_enable(crtc);
5284                 }
5285         } else {
5286                 if (intel_crtc->active) {
5287                         dev_priv->display.crtc_disable(crtc);
5288 
5289                         domains = intel_crtc->enabled_power_domains;
5290                         for_each_power_domain(domain, domains)
5291                                 intel_display_power_put(dev_priv, domain);
5292                         intel_crtc->enabled_power_domains = 0;
5293                 }
5294         }
5295 }
5296 
5297 /**
5298  * Sets the power management mode of the pipe and plane.
5299  */
5300 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5301 {
5302         struct drm_device *dev = crtc->dev;
5303         struct intel_encoder *intel_encoder;
5304         bool enable = false;
5305 
5306         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5307                 enable |= intel_encoder->connectors_active;
5308 
5309         intel_crtc_control(crtc, enable);
5310 }
5311 
5312 static void intel_crtc_disable(struct drm_crtc *crtc)
5313 {
5314         struct drm_device *dev = crtc->dev;
5315         struct drm_connector *connector;
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317 
5318         /* crtc should still be enabled when we disable it. */
5319         WARN_ON(!crtc->enabled);
5320 
5321         dev_priv->display.crtc_disable(crtc);
5322         dev_priv->display.off(crtc);
5323 
5324         crtc->primary->funcs->disable_plane(crtc->primary);
5325 
5326         /* Update computed state. */
5327         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5328                 if (!connector->encoder || !connector->encoder->crtc)
5329                         continue;
5330 
5331                 if (connector->encoder->crtc != crtc)
5332                         continue;
5333 
5334                 connector->dpms = DRM_MODE_DPMS_OFF;
5335                 to_intel_encoder(connector->encoder)->connectors_active = false;
5336         }
5337 }
5338 
5339 void intel_encoder_destroy(struct drm_encoder *encoder)
5340 {
5341         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5342 
5343         drm_encoder_cleanup(encoder);
5344         kfree(intel_encoder);
5345 }
5346 
5347 /* Simple dpms helper for encoders with just one connector, no cloning and only
5348  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5349  * state of the entire output pipe. */
5350 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5351 {
5352         if (mode == DRM_MODE_DPMS_ON) {
5353                 encoder->connectors_active = true;
5354 
5355                 intel_crtc_update_dpms(encoder->base.crtc);
5356         } else {
5357                 encoder->connectors_active = false;
5358 
5359                 intel_crtc_update_dpms(encoder->base.crtc);
5360         }
5361 }
5362 
5363 /* Cross check the actual hw state with our own modeset state tracking (and it's
5364  * internal consistency). */
5365 static void intel_connector_check_state(struct intel_connector *connector)
5366 {
5367         if (connector->get_hw_state(connector)) {
5368                 struct intel_encoder *encoder = connector->encoder;
5369                 struct drm_crtc *crtc;
5370                 bool encoder_enabled;
5371                 enum pipe pipe;
5372 
5373                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5374                               connector->base.base.id,
5375                               connector->base.name);
5376 
5377                 /* there is no real hw state for MST connectors */
5378                 if (connector->mst_port)
5379                         return;
5380 
5381                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5382                      "wrong connector dpms state\n");
5383                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5384                      "active connector not linked to encoder\n");
5385 
5386                 if (encoder) {
5387                         I915_STATE_WARN(!encoder->connectors_active,
5388                              "encoder->connectors_active not set\n");
5389 
5390                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5391                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5392                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5393                                 return;
5394 
5395                         crtc = encoder->base.crtc;
5396 
5397                         I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5398                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5399                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5400                              "encoder active on the wrong pipe\n");
5401                 }
5402         }
5403 }
5404 
5405 /* Even simpler default implementation, if there's really no special case to
5406  * consider. */
5407 void intel_connector_dpms(struct drm_connector *connector, int mode)
5408 {
5409         /* All the simple cases only support two dpms states. */
5410         if (mode != DRM_MODE_DPMS_ON)
5411                 mode = DRM_MODE_DPMS_OFF;
5412 
5413         if (mode == connector->dpms)
5414                 return;
5415 
5416         connector->dpms = mode;
5417 
5418         /* Only need to change hw state when actually enabled */
5419         if (connector->encoder)
5420                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5421 
5422         intel_modeset_check_state(connector->dev);
5423 }
5424 
5425 /* Simple connector->get_hw_state implementation for encoders that support only
5426  * one connector and no cloning and hence the encoder state determines the state
5427  * of the connector. */
5428 bool intel_connector_get_hw_state(struct intel_connector *connector)
5429 {
5430         enum pipe pipe = 0;
5431         struct intel_encoder *encoder = connector->encoder;
5432 
5433         return encoder->get_hw_state(encoder, &pipe);
5434 }
5435 
5436 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5437                                      struct intel_crtc_state *pipe_config)
5438 {
5439         struct drm_i915_private *dev_priv = dev->dev_private;
5440         struct intel_crtc *pipe_B_crtc =
5441                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5442 
5443         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5444                       pipe_name(pipe), pipe_config->fdi_lanes);
5445         if (pipe_config->fdi_lanes > 4) {
5446                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5447                               pipe_name(pipe), pipe_config->fdi_lanes);
5448                 return false;
5449         }
5450 
5451         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5452                 if (pipe_config->fdi_lanes > 2) {
5453                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5454                                       pipe_config->fdi_lanes);
5455                         return false;
5456                 } else {
5457                         return true;
5458                 }
5459         }
5460 
5461         if (INTEL_INFO(dev)->num_pipes == 2)
5462                 return true;
5463 
5464         /* Ivybridge 3 pipe is really complicated */
5465         switch (pipe) {
5466         case PIPE_A:
5467                 return true;
5468         case PIPE_B:
5469                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5470                     pipe_config->fdi_lanes > 2) {
5471                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5472                                       pipe_name(pipe), pipe_config->fdi_lanes);
5473                         return false;
5474                 }
5475                 return true;
5476         case PIPE_C:
5477                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5478                     pipe_B_crtc->config->fdi_lanes <= 2) {
5479                         if (pipe_config->fdi_lanes > 2) {
5480                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5481                                               pipe_name(pipe), pipe_config->fdi_lanes);
5482                                 return false;
5483                         }
5484                 } else {
5485                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5486                         return false;
5487                 }
5488                 return true;
5489         default:
5490                 BUG();
5491         }
5492 }
5493 
5494 #define RETRY 1
5495 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5496                                        struct intel_crtc_state *pipe_config)
5497 {
5498         struct drm_device *dev = intel_crtc->base.dev;
5499         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5500         int lane, link_bw, fdi_dotclock;
5501         bool setup_ok, needs_recompute = false;
5502 
5503 retry:
5504         /* FDI is a binary signal running at ~2.7GHz, encoding
5505          * each output octet as 10 bits. The actual frequency
5506          * is stored as a divider into a 100MHz clock, and the
5507          * mode pixel clock is stored in units of 1KHz.
5508          * Hence the bw of each lane in terms of the mode signal
5509          * is:
5510          */
5511         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5512 
5513         fdi_dotclock = adjusted_mode->crtc_clock;
5514 
5515         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5516                                            pipe_config->pipe_bpp);
5517 
5518         pipe_config->fdi_lanes = lane;
5519 
5520         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5521                                link_bw, &pipe_config->fdi_m_n);
5522 
5523         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5524                                             intel_crtc->pipe, pipe_config);
5525         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5526                 pipe_config->pipe_bpp -= 2*3;
5527                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5528                               pipe_config->pipe_bpp);
5529                 needs_recompute = true;
5530                 pipe_config->bw_constrained = true;
5531 
5532                 goto retry;
5533         }
5534 
5535         if (needs_recompute)
5536                 return RETRY;
5537 
5538         return setup_ok ? 0 : -EINVAL;
5539 }
5540 
5541 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5542                                    struct intel_crtc_state *pipe_config)
5543 {
5544         pipe_config->ips_enabled = i915.enable_ips &&
5545                                    hsw_crtc_supports_ips(crtc) &&
5546                                    pipe_config->pipe_bpp <= 24;
5547 }
5548 
5549 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5550                                      struct intel_crtc_state *pipe_config)
5551 {
5552         struct drm_device *dev = crtc->base.dev;
5553         struct drm_i915_private *dev_priv = dev->dev_private;
5554         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5555 
5556         /* FIXME should check pixel clock limits on all platforms */
5557         if (INTEL_INFO(dev)->gen < 4) {
5558                 int clock_limit =
5559                         dev_priv->display.get_display_clock_speed(dev);
5560 
5561                 /*
5562                  * Enable pixel doubling when the dot clock
5563                  * is > 90% of the (display) core speed.
5564                  *
5565                  * GDG double wide on either pipe,
5566                  * otherwise pipe A only.
5567                  */
5568                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5569                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5570                         clock_limit *= 2;
5571                         pipe_config->double_wide = true;
5572                 }
5573 
5574                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5575                         return -EINVAL;
5576         }
5577 
5578         /*
5579          * Pipe horizontal size must be even in:
5580          * - DVO ganged mode
5581          * - LVDS dual channel mode
5582          * - Double wide pipe
5583          */
5584         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5585              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5586                 pipe_config->pipe_src_w &= ~1;
5587 
5588         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5589          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5590          */
5591         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5592                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5593                 return -EINVAL;
5594 
5595         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5596                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5597         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5598                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5599                  * for lvds. */
5600                 pipe_config->pipe_bpp = 8*3;
5601         }
5602 
5603         if (HAS_IPS(dev))
5604                 hsw_compute_ips_config(crtc, pipe_config);
5605 
5606         if (pipe_config->has_pch_encoder)
5607                 return ironlake_fdi_compute_config(crtc, pipe_config);
5608 
5609         return 0;
5610 }
5611 
5612 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5613 {
5614         struct drm_i915_private *dev_priv = dev->dev_private;
5615         u32 val;
5616         int divider;
5617 
5618         /* FIXME: Punit isn't quite ready yet */
5619         if (IS_CHERRYVIEW(dev))
5620                 return 400000;
5621 
5622         if (dev_priv->hpll_freq == 0)
5623                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5624 
5625         mutex_lock(&dev_priv->dpio_lock);
5626         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5627         mutex_unlock(&dev_priv->dpio_lock);
5628 
5629         divider = val & DISPLAY_FREQUENCY_VALUES;
5630 
5631         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5632              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5633              "cdclk change in progress\n");
5634 
5635         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5636 }
5637 
5638 static int i945_get_display_clock_speed(struct drm_device *dev)
5639 {
5640         return 400000;
5641 }
5642 
5643 static int i915_get_display_clock_speed(struct drm_device *dev)
5644 {
5645         return 333000;
5646 }
5647 
5648 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5649 {
5650         return 200000;
5651 }
5652 
5653 static int pnv_get_display_clock_speed(struct drm_device *dev)
5654 {
5655         u16 gcfgc = 0;
5656 
5657         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5658 
5659         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5660         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5661                 return 267000;
5662         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5663                 return 333000;
5664         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5665                 return 444000;
5666         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5667                 return 200000;
5668         default:
5669                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5670         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5671                 return 133000;
5672         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5673                 return 167000;
5674         }
5675 }
5676 
5677 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5678 {
5679         u16 gcfgc = 0;
5680 
5681         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5682 
5683         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5684                 return 133000;
5685         else {
5686                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5687                 case GC_DISPLAY_CLOCK_333_MHZ:
5688                         return 333000;
5689                 default:
5690                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5691                         return 190000;
5692                 }
5693         }
5694 }
5695 
5696 static int i865_get_display_clock_speed(struct drm_device *dev)
5697 {
5698         return 266000;
5699 }
5700 
5701 static int i855_get_display_clock_speed(struct drm_device *dev)
5702 {
5703         u16 hpllcc = 0;
5704         /* Assume that the hardware is in the high speed state.  This
5705          * should be the default.
5706          */
5707         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5708         case GC_CLOCK_133_200:
5709         case GC_CLOCK_100_200:
5710                 return 200000;
5711         case GC_CLOCK_166_250:
5712                 return 250000;
5713         case GC_CLOCK_100_133:
5714                 return 133000;
5715         }
5716 
5717         /* Shouldn't happen */
5718         return 0;
5719 }
5720 
5721 static int i830_get_display_clock_speed(struct drm_device *dev)
5722 {
5723         return 133000;
5724 }
5725 
5726 static void
5727 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5728 {
5729         while (*num > DATA_LINK_M_N_MASK ||
5730                *den > DATA_LINK_M_N_MASK) {
5731                 *num >>= 1;
5732                 *den >>= 1;
5733         }
5734 }
5735 
5736 static void compute_m_n(unsigned int m, unsigned int n,
5737                         uint32_t *ret_m, uint32_t *ret_n)
5738 {
5739         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5740         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5741         intel_reduce_m_n_ratio(ret_m, ret_n);
5742 }
5743 
5744 void
5745 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5746                        int pixel_clock, int link_clock,
5747                        struct intel_link_m_n *m_n)
5748 {
5749         m_n->tu = 64;
5750 
5751         compute_m_n(bits_per_pixel * pixel_clock,
5752                     link_clock * nlanes * 8,
5753                     &m_n->gmch_m, &m_n->gmch_n);
5754 
5755         compute_m_n(pixel_clock, link_clock,
5756                     &m_n->link_m, &m_n->link_n);
5757 }
5758 
5759 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5760 {
5761         if (i915.panel_use_ssc >= 0)
5762                 return i915.panel_use_ssc != 0;
5763         return dev_priv->vbt.lvds_use_ssc
5764                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5765 }
5766 
5767 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5768 {
5769         struct drm_device *dev = crtc->base.dev;
5770         struct drm_i915_private *dev_priv = dev->dev_private;
5771         int refclk;
5772 
5773         if (IS_VALLEYVIEW(dev)) {
5774                 refclk = 100000;
5775         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5776             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5777                 refclk = dev_priv->vbt.lvds_ssc_freq;
5778                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5779         } else if (!IS_GEN2(dev)) {
5780                 refclk = 96000;
5781         } else {
5782                 refclk = 48000;
5783         }
5784 
5785         return refclk;
5786 }
5787 
5788 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5789 {
5790         return (1 << dpll->n) << 16 | dpll->m2;
5791 }
5792 
5793 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5794 {
5795         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5796 }
5797 
5798 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5799                                      struct intel_crtc_state *crtc_state,
5800                                      intel_clock_t *reduced_clock)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         u32 fp, fp2 = 0;
5804 
5805         if (IS_PINEVIEW(dev)) {
5806                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5807                 if (reduced_clock)
5808                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5809         } else {
5810                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5811                 if (reduced_clock)
5812                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5813         }
5814 
5815         crtc_state->dpll_hw_state.fp0 = fp;
5816 
5817         crtc->lowfreq_avail = false;
5818         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5819             reduced_clock && i915.powersave) {
5820                 crtc_state->dpll_hw_state.fp1 = fp2;
5821                 crtc->lowfreq_avail = true;
5822         } else {
5823                 crtc_state->dpll_hw_state.fp1 = fp;
5824         }
5825 }
5826 
5827 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5828                 pipe)
5829 {
5830         u32 reg_val;
5831 
5832         /*
5833          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5834          * and set it to a reasonable value instead.
5835          */
5836         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5837         reg_val &= 0xffffff00;
5838         reg_val |= 0x00000030;
5839         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5840 
5841         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5842         reg_val &= 0x8cffffff;
5843         reg_val = 0x8c000000;
5844         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5845 
5846         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5847         reg_val &= 0xffffff00;
5848         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5849 
5850         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5851         reg_val &= 0x00ffffff;
5852         reg_val |= 0xb0000000;
5853         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5854 }
5855 
5856 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5857                                          struct intel_link_m_n *m_n)
5858 {
5859         struct drm_device *dev = crtc->base.dev;
5860         struct drm_i915_private *dev_priv = dev->dev_private;
5861         int pipe = crtc->pipe;
5862 
5863         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5864         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5865         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5866         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5867 }
5868 
5869 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5870                                          struct intel_link_m_n *m_n,
5871                                          struct intel_link_m_n *m2_n2)
5872 {
5873         struct drm_device *dev = crtc->base.dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         int pipe = crtc->pipe;
5876         enum transcoder transcoder = crtc->config->cpu_transcoder;
5877 
5878         if (INTEL_INFO(dev)->gen >= 5) {
5879                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5880                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5881                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5882                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5883                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5884                  * for gen < 8) and if DRRS is supported (to make sure the
5885                  * registers are not unnecessarily accessed).
5886                  */
5887                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5888                         crtc->config->has_drrs) {
5889                         I915_WRITE(PIPE_DATA_M2(transcoder),
5890                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5891                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5892                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5893                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5894                 }
5895         } else {
5896                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5897                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5898                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5899                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5900         }
5901 }
5902 
5903 void intel_dp_set_m_n(struct intel_crtc *crtc)
5904 {
5905         if (crtc->config->has_pch_encoder)
5906                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5907         else
5908                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5909                                                    &crtc->config->dp_m2_n2);
5910 }
5911 
5912 static void vlv_update_pll(struct intel_crtc *crtc,
5913                            struct intel_crtc_state *pipe_config)
5914 {
5915         u32 dpll, dpll_md;
5916 
5917         /*
5918          * Enable DPIO clock input. We should never disable the reference
5919          * clock for pipe B, since VGA hotplug / manual detection depends
5920          * on it.
5921          */
5922         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5923                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5924         /* We should never disable this, set it here for state tracking */
5925         if (crtc->pipe == PIPE_B)
5926                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5927         dpll |= DPLL_VCO_ENABLE;
5928         pipe_config->dpll_hw_state.dpll = dpll;
5929 
5930         dpll_md = (pipe_config->pixel_multiplier - 1)
5931                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5932         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5933 }
5934 
5935 static void vlv_prepare_pll(struct intel_crtc *crtc,
5936                             const struct intel_crtc_state *pipe_config)
5937 {
5938         struct drm_device *dev = crtc->base.dev;
5939         struct drm_i915_private *dev_priv = dev->dev_private;
5940         int pipe = crtc->pipe;
5941         u32 mdiv;
5942         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5943         u32 coreclk, reg_val;
5944 
5945         mutex_lock(&dev_priv->dpio_lock);
5946 
5947         bestn = pipe_config->dpll.n;
5948         bestm1 = pipe_config->dpll.m1;
5949         bestm2 = pipe_config->dpll.m2;
5950         bestp1 = pipe_config->dpll.p1;
5951         bestp2 = pipe_config->dpll.p2;
5952 
5953         /* See eDP HDMI DPIO driver vbios notes doc */
5954 
5955         /* PLL B needs special handling */
5956         if (pipe == PIPE_B)
5957                 vlv_pllb_recal_opamp(dev_priv, pipe);
5958 
5959         /* Set up Tx target for periodic Rcomp update */
5960         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5961 
5962         /* Disable target IRef on PLL */
5963         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5964         reg_val &= 0x00ffffff;
5965         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5966 
5967         /* Disable fast lock */
5968         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5969 
5970         /* Set idtafcrecal before PLL is enabled */
5971         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5972         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5973         mdiv |= ((bestn << DPIO_N_SHIFT));
5974         mdiv |= (1 << DPIO_K_SHIFT);
5975 
5976         /*
5977          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5978          * but we don't support that).
5979          * Note: don't use the DAC post divider as it seems unstable.
5980          */
5981         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5982         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5983 
5984         mdiv |= DPIO_ENABLE_CALIBRATION;
5985         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5986 
5987         /* Set HBR and RBR LPF coefficients */
5988         if (pipe_config->port_clock == 162000 ||
5989             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5990             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5991                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5992                                  0x009f0003);
5993         else
5994                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5995                                  0x00d0000f);
5996 
5997         if (pipe_config->has_dp_encoder) {
5998                 /* Use SSC source */
5999                 if (pipe == PIPE_A)
6000                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6001                                          0x0df40000);
6002                 else
6003                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6004                                          0x0df70000);
6005         } else { /* HDMI or VGA */
6006                 /* Use bend source */
6007                 if (pipe == PIPE_A)
6008                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6009                                          0x0df70000);
6010                 else
6011                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6012                                          0x0df40000);
6013         }
6014 
6015         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6016         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6017         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6018             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6019                 coreclk |= 0x01000000;
6020         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6021 
6022         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6023         mutex_unlock(&dev_priv->dpio_lock);
6024 }
6025 
6026 static void chv_update_pll(struct intel_crtc *crtc,
6027                            struct intel_crtc_state *pipe_config)
6028 {
6029         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6030                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6031                 DPLL_VCO_ENABLE;
6032         if (crtc->pipe != PIPE_A)
6033                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6034 
6035         pipe_config->dpll_hw_state.dpll_md =
6036                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6037 }
6038 
6039 static void chv_prepare_pll(struct intel_crtc *crtc,
6040                             const struct intel_crtc_state *pipe_config)
6041 {
6042         struct drm_device *dev = crtc->base.dev;
6043         struct drm_i915_private *dev_priv = dev->dev_private;
6044         int pipe = crtc->pipe;
6045         int dpll_reg = DPLL(crtc->pipe);
6046         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6047         u32 loopfilter, intcoeff;
6048         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6049         int refclk;
6050 
6051         bestn = pipe_config->dpll.n;
6052         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6053         bestm1 = pipe_config->dpll.m1;
6054         bestm2 = pipe_config->dpll.m2 >> 22;
6055         bestp1 = pipe_config->dpll.p1;
6056         bestp2 = pipe_config->dpll.p2;
6057 
6058         /*
6059          * Enable Refclk and SSC
6060          */
6061         I915_WRITE(dpll_reg,
6062                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6063 
6064         mutex_lock(&dev_priv->dpio_lock);
6065 
6066         /* p1 and p2 divider */
6067         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6068                         5 << DPIO_CHV_S1_DIV_SHIFT |
6069                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6070                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6071                         1 << DPIO_CHV_K_DIV_SHIFT);
6072 
6073         /* Feedback post-divider - m2 */
6074         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6075 
6076         /* Feedback refclk divider - n and m1 */
6077         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6078                         DPIO_CHV_M1_DIV_BY_2 |
6079                         1 << DPIO_CHV_N_DIV_SHIFT);
6080 
6081         /* M2 fraction division */
6082         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6083 
6084         /* M2 fraction division enable */
6085         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6086                        DPIO_CHV_FRAC_DIV_EN |
6087                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6088 
6089         /* Loop filter */
6090         refclk = i9xx_get_refclk(crtc, 0);
6091         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6092                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6093         if (refclk == 100000)
6094                 intcoeff = 11;
6095         else if (refclk == 38400)
6096                 intcoeff = 10;
6097         else
6098                 intcoeff = 9;
6099         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6100         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6101 
6102         /* AFC Recal */
6103         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6104                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6105                         DPIO_AFC_RECAL);
6106 
6107         mutex_unlock(&dev_priv->dpio_lock);
6108 }
6109 
6110 /**
6111  * vlv_force_pll_on - forcibly enable just the PLL
6112  * @dev_priv: i915 private structure
6113  * @pipe: pipe PLL to enable
6114  * @dpll: PLL configuration
6115  *
6116  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6117  * in cases where we need the PLL enabled even when @pipe is not going to
6118  * be enabled.
6119  */
6120 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6121                       const struct dpll *dpll)
6122 {
6123         struct intel_crtc *crtc =
6124                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6125         struct intel_crtc_state pipe_config = {
6126                 .pixel_multiplier = 1,
6127                 .dpll = *dpll,
6128         };
6129 
6130         if (IS_CHERRYVIEW(dev)) {
6131                 chv_update_pll(crtc, &pipe_config);
6132                 chv_prepare_pll(crtc, &pipe_config);
6133                 chv_enable_pll(crtc, &pipe_config);
6134         } else {
6135                 vlv_update_pll(crtc, &pipe_config);
6136                 vlv_prepare_pll(crtc, &pipe_config);
6137                 vlv_enable_pll(crtc, &pipe_config);
6138         }
6139 }
6140 
6141 /**
6142  * vlv_force_pll_off - forcibly disable just the PLL
6143  * @dev_priv: i915 private structure
6144  * @pipe: pipe PLL to disable
6145  *
6146  * Disable the PLL for @pipe. To be used in cases where we need
6147  * the PLL enabled even when @pipe is not going to be enabled.
6148  */
6149 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6150 {
6151         if (IS_CHERRYVIEW(dev))
6152                 chv_disable_pll(to_i915(dev), pipe);
6153         else
6154                 vlv_disable_pll(to_i915(dev), pipe);
6155 }
6156 
6157 static void i9xx_update_pll(struct intel_crtc *crtc,
6158                             struct intel_crtc_state *crtc_state,
6159                             intel_clock_t *reduced_clock,
6160                             int num_connectors)
6161 {
6162         struct drm_device *dev = crtc->base.dev;
6163         struct drm_i915_private *dev_priv = dev->dev_private;
6164         u32 dpll;
6165         bool is_sdvo;
6166         struct dpll *clock = &crtc_state->dpll;
6167 
6168         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6169 
6170         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6171                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6172 
6173         dpll = DPLL_VGA_MODE_DIS;
6174 
6175         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6176                 dpll |= DPLLB_MODE_LVDS;
6177         else
6178                 dpll |= DPLLB_MODE_DAC_SERIAL;
6179 
6180         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6181                 dpll |= (crtc_state->pixel_multiplier - 1)
6182                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6183         }
6184 
6185         if (is_sdvo)
6186                 dpll |= DPLL_SDVO_HIGH_SPEED;
6187 
6188         if (crtc_state->has_dp_encoder)
6189                 dpll |= DPLL_SDVO_HIGH_SPEED;
6190 
6191         /* compute bitmask from p1 value */
6192         if (IS_PINEVIEW(dev))
6193                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6194         else {
6195                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6196                 if (IS_G4X(dev) && reduced_clock)
6197                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6198         }
6199         switch (clock->p2) {
6200         case 5:
6201                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6202                 break;
6203         case 7:
6204                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6205                 break;
6206         case 10:
6207                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6208                 break;
6209         case 14:
6210                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6211                 break;
6212         }
6213         if (INTEL_INFO(dev)->gen >= 4)
6214                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6215 
6216         if (crtc_state->sdvo_tv_clock)
6217                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6218         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6219                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6220                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6221         else
6222                 dpll |= PLL_REF_INPUT_DREFCLK;
6223 
6224         dpll |= DPLL_VCO_ENABLE;
6225         crtc_state->dpll_hw_state.dpll = dpll;
6226 
6227         if (INTEL_INFO(dev)->gen >= 4) {
6228                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6229                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6230                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6231         }
6232 }
6233 
6234 static void i8xx_update_pll(struct intel_crtc *crtc,
6235                             struct intel_crtc_state *crtc_state,
6236                             intel_clock_t *reduced_clock,
6237                             int num_connectors)
6238 {
6239         struct drm_device *dev = crtc->base.dev;
6240         struct drm_i915_private *dev_priv = dev->dev_private;
6241         u32 dpll;
6242         struct dpll *clock = &crtc_state->dpll;
6243 
6244         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6245 
6246         dpll = DPLL_VGA_MODE_DIS;
6247 
6248         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6249                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6250         } else {
6251                 if (clock->p1 == 2)
6252                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6253                 else
6254                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6255                 if (clock->p2 == 4)
6256                         dpll |= PLL_P2_DIVIDE_BY_4;
6257         }
6258 
6259         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6260                 dpll |= DPLL_DVO_2X_MODE;
6261 
6262         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6263                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6264                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6265         else
6266                 dpll |= PLL_REF_INPUT_DREFCLK;
6267 
6268         dpll |= DPLL_VCO_ENABLE;
6269         crtc_state->dpll_hw_state.dpll = dpll;
6270 }
6271 
6272 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6273 {
6274         struct drm_device *dev = intel_crtc->base.dev;
6275         struct drm_i915_private *dev_priv = dev->dev_private;
6276         enum pipe pipe = intel_crtc->pipe;
6277         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6278         struct drm_display_mode *adjusted_mode =
6279                 &intel_crtc->config->base.adjusted_mode;
6280         uint32_t crtc_vtotal, crtc_vblank_end;
6281         int vsyncshift = 0;
6282 
6283         /* We need to be careful not to changed the adjusted mode, for otherwise
6284          * the hw state checker will get angry at the mismatch. */
6285         crtc_vtotal = adjusted_mode->crtc_vtotal;
6286         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6287 
6288         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6289                 /* the chip adds 2 halflines automatically */
6290                 crtc_vtotal -= 1;
6291                 crtc_vblank_end -= 1;
6292 
6293                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6294                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6295                 else
6296                         vsyncshift = adjusted_mode->crtc_hsync_start -
6297                                 adjusted_mode->crtc_htotal / 2;
6298                 if (vsyncshift < 0)
6299                         vsyncshift += adjusted_mode->crtc_htotal;
6300         }
6301 
6302         if (INTEL_INFO(dev)->gen > 3)
6303                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6304 
6305         I915_WRITE(HTOTAL(cpu_transcoder),
6306                    (adjusted_mode->crtc_hdisplay - 1) |
6307                    ((adjusted_mode->crtc_htotal - 1) << 16));
6308         I915_WRITE(HBLANK(cpu_transcoder),
6309                    (adjusted_mode->crtc_hblank_start - 1) |
6310                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6311         I915_WRITE(HSYNC(cpu_transcoder),
6312                    (adjusted_mode->crtc_hsync_start - 1) |
6313                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6314 
6315         I915_WRITE(VTOTAL(cpu_transcoder),
6316                    (adjusted_mode->crtc_vdisplay - 1) |
6317                    ((crtc_vtotal - 1) << 16));
6318         I915_WRITE(VBLANK(cpu_transcoder),
6319                    (adjusted_mode->crtc_vblank_start - 1) |
6320                    ((crtc_vblank_end - 1) << 16));
6321         I915_WRITE(VSYNC(cpu_transcoder),
6322                    (adjusted_mode->crtc_vsync_start - 1) |
6323                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6324 
6325         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6326          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6327          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6328          * bits. */
6329         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6330             (pipe == PIPE_B || pipe == PIPE_C))
6331                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6332 
6333         /* pipesrc controls the size that is scaled from, which should
6334          * always be the user's requested size.
6335          */
6336         I915_WRITE(PIPESRC(pipe),
6337                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6338                    (intel_crtc->config->pipe_src_h - 1));
6339 }
6340 
6341 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6342                                    struct intel_crtc_state *pipe_config)
6343 {
6344         struct drm_device *dev = crtc->base.dev;
6345         struct drm_i915_private *dev_priv = dev->dev_private;
6346         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6347         uint32_t tmp;
6348 
6349         tmp = I915_READ(HTOTAL(cpu_transcoder));
6350         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6351         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6352         tmp = I915_READ(HBLANK(cpu_transcoder));
6353         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6354         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6355         tmp = I915_READ(HSYNC(cpu_transcoder));
6356         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6357         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6358 
6359         tmp = I915_READ(VTOTAL(cpu_transcoder));
6360         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6361         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6362         tmp = I915_READ(VBLANK(cpu_transcoder));
6363         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6364         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6365         tmp = I915_READ(VSYNC(cpu_transcoder));
6366         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6367         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6368 
6369         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6370                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6371                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6372                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6373         }
6374 
6375         tmp = I915_READ(PIPESRC(crtc->pipe));
6376         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6377         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6378 
6379         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6380         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6381 }
6382 
6383 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6384                                  struct intel_crtc_state *pipe_config)
6385 {
6386         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6387         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6388         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6389         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6390 
6391         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6392         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6393         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6394         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6395 
6396         mode->flags = pipe_config->base.adjusted_mode.flags;
6397 
6398         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6399         mode->flags |= pipe_config->base.adjusted_mode.flags;
6400 }
6401 
6402 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6403 {
6404         struct drm_device *dev = intel_crtc->base.dev;
6405         struct drm_i915_private *dev_priv = dev->dev_private;
6406