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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_dp_helper.h>
 41 #include <drm/drm_crtc_helper.h>
 42 #include <linux/dma_remapping.h>
 43 
 44 static void intel_increase_pllclock(struct drm_crtc *crtc);
 45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 46 
 47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 48                                 struct intel_crtc_config *pipe_config);
 49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 50                                    struct intel_crtc_config *pipe_config);
 51 
 52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 53                           int x, int y, struct drm_framebuffer *old_fb);
 54 
 55 
 56 typedef struct {
 57         int     min, max;
 58 } intel_range_t;
 59 
 60 typedef struct {
 61         int     dot_limit;
 62         int     p2_slow, p2_fast;
 63 } intel_p2_t;
 64 
 65 typedef struct intel_limit intel_limit_t;
 66 struct intel_limit {
 67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 68         intel_p2_t          p2;
 69 };
 70 
 71 int
 72 intel_pch_rawclk(struct drm_device *dev)
 73 {
 74         struct drm_i915_private *dev_priv = dev->dev_private;
 75 
 76         WARN_ON(!HAS_PCH_SPLIT(dev));
 77 
 78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 79 }
 80 
 81 static inline u32 /* units of 100MHz */
 82 intel_fdi_link_freq(struct drm_device *dev)
 83 {
 84         if (IS_GEN5(dev)) {
 85                 struct drm_i915_private *dev_priv = dev->dev_private;
 86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 87         } else
 88                 return 27;
 89 }
 90 
 91 static const intel_limit_t intel_limits_i8xx_dac = {
 92         .dot = { .min = 25000, .max = 350000 },
 93         .vco = { .min = 908000, .max = 1512000 },
 94         .n = { .min = 2, .max = 16 },
 95         .m = { .min = 96, .max = 140 },
 96         .m1 = { .min = 18, .max = 26 },
 97         .m2 = { .min = 6, .max = 16 },
 98         .p = { .min = 4, .max = 128 },
 99         .p1 = { .min = 2, .max = 33 },
100         .p2 = { .dot_limit = 165000,
101                 .p2_slow = 4, .p2_fast = 2 },
102 };
103 
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105         .dot = { .min = 25000, .max = 350000 },
106         .vco = { .min = 908000, .max = 1512000 },
107         .n = { .min = 2, .max = 16 },
108         .m = { .min = 96, .max = 140 },
109         .m1 = { .min = 18, .max = 26 },
110         .m2 = { .min = 6, .max = 16 },
111         .p = { .min = 4, .max = 128 },
112         .p1 = { .min = 2, .max = 33 },
113         .p2 = { .dot_limit = 165000,
114                 .p2_slow = 4, .p2_fast = 4 },
115 };
116 
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118         .dot = { .min = 25000, .max = 350000 },
119         .vco = { .min = 908000, .max = 1512000 },
120         .n = { .min = 2, .max = 16 },
121         .m = { .min = 96, .max = 140 },
122         .m1 = { .min = 18, .max = 26 },
123         .m2 = { .min = 6, .max = 16 },
124         .p = { .min = 4, .max = 128 },
125         .p1 = { .min = 1, .max = 6 },
126         .p2 = { .dot_limit = 165000,
127                 .p2_slow = 14, .p2_fast = 7 },
128 };
129 
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131         .dot = { .min = 20000, .max = 400000 },
132         .vco = { .min = 1400000, .max = 2800000 },
133         .n = { .min = 1, .max = 6 },
134         .m = { .min = 70, .max = 120 },
135         .m1 = { .min = 8, .max = 18 },
136         .m2 = { .min = 3, .max = 7 },
137         .p = { .min = 5, .max = 80 },
138         .p1 = { .min = 1, .max = 8 },
139         .p2 = { .dot_limit = 200000,
140                 .p2_slow = 10, .p2_fast = 5 },
141 };
142 
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144         .dot = { .min = 20000, .max = 400000 },
145         .vco = { .min = 1400000, .max = 2800000 },
146         .n = { .min = 1, .max = 6 },
147         .m = { .min = 70, .max = 120 },
148         .m1 = { .min = 8, .max = 18 },
149         .m2 = { .min = 3, .max = 7 },
150         .p = { .min = 7, .max = 98 },
151         .p1 = { .min = 1, .max = 8 },
152         .p2 = { .dot_limit = 112000,
153                 .p2_slow = 14, .p2_fast = 7 },
154 };
155 
156 
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158         .dot = { .min = 25000, .max = 270000 },
159         .vco = { .min = 1750000, .max = 3500000},
160         .n = { .min = 1, .max = 4 },
161         .m = { .min = 104, .max = 138 },
162         .m1 = { .min = 17, .max = 23 },
163         .m2 = { .min = 5, .max = 11 },
164         .p = { .min = 10, .max = 30 },
165         .p1 = { .min = 1, .max = 3},
166         .p2 = { .dot_limit = 270000,
167                 .p2_slow = 10,
168                 .p2_fast = 10
169         },
170 };
171 
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173         .dot = { .min = 22000, .max = 400000 },
174         .vco = { .min = 1750000, .max = 3500000},
175         .n = { .min = 1, .max = 4 },
176         .m = { .min = 104, .max = 138 },
177         .m1 = { .min = 16, .max = 23 },
178         .m2 = { .min = 5, .max = 11 },
179         .p = { .min = 5, .max = 80 },
180         .p1 = { .min = 1, .max = 8},
181         .p2 = { .dot_limit = 165000,
182                 .p2_slow = 10, .p2_fast = 5 },
183 };
184 
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186         .dot = { .min = 20000, .max = 115000 },
187         .vco = { .min = 1750000, .max = 3500000 },
188         .n = { .min = 1, .max = 3 },
189         .m = { .min = 104, .max = 138 },
190         .m1 = { .min = 17, .max = 23 },
191         .m2 = { .min = 5, .max = 11 },
192         .p = { .min = 28, .max = 112 },
193         .p1 = { .min = 2, .max = 8 },
194         .p2 = { .dot_limit = 0,
195                 .p2_slow = 14, .p2_fast = 14
196         },
197 };
198 
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200         .dot = { .min = 80000, .max = 224000 },
201         .vco = { .min = 1750000, .max = 3500000 },
202         .n = { .min = 1, .max = 3 },
203         .m = { .min = 104, .max = 138 },
204         .m1 = { .min = 17, .max = 23 },
205         .m2 = { .min = 5, .max = 11 },
206         .p = { .min = 14, .max = 42 },
207         .p1 = { .min = 2, .max = 6 },
208         .p2 = { .dot_limit = 0,
209                 .p2_slow = 7, .p2_fast = 7
210         },
211 };
212 
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214         .dot = { .min = 20000, .max = 400000},
215         .vco = { .min = 1700000, .max = 3500000 },
216         /* Pineview's Ncounter is a ring counter */
217         .n = { .min = 3, .max = 6 },
218         .m = { .min = 2, .max = 256 },
219         /* Pineview only has one combined m divider, which we treat as m2. */
220         .m1 = { .min = 0, .max = 0 },
221         .m2 = { .min = 0, .max = 254 },
222         .p = { .min = 5, .max = 80 },
223         .p1 = { .min = 1, .max = 8 },
224         .p2 = { .dot_limit = 200000,
225                 .p2_slow = 10, .p2_fast = 5 },
226 };
227 
228 static const intel_limit_t intel_limits_pineview_lvds = {
229         .dot = { .min = 20000, .max = 400000 },
230         .vco = { .min = 1700000, .max = 3500000 },
231         .n = { .min = 3, .max = 6 },
232         .m = { .min = 2, .max = 256 },
233         .m1 = { .min = 0, .max = 0 },
234         .m2 = { .min = 0, .max = 254 },
235         .p = { .min = 7, .max = 112 },
236         .p1 = { .min = 1, .max = 8 },
237         .p2 = { .dot_limit = 112000,
238                 .p2_slow = 14, .p2_fast = 14 },
239 };
240 
241 /* Ironlake / Sandybridge
242  *
243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
244  * the range value for them is (actual_value - 2).
245  */
246 static const intel_limit_t intel_limits_ironlake_dac = {
247         .dot = { .min = 25000, .max = 350000 },
248         .vco = { .min = 1760000, .max = 3510000 },
249         .n = { .min = 1, .max = 5 },
250         .m = { .min = 79, .max = 127 },
251         .m1 = { .min = 12, .max = 22 },
252         .m2 = { .min = 5, .max = 9 },
253         .p = { .min = 5, .max = 80 },
254         .p1 = { .min = 1, .max = 8 },
255         .p2 = { .dot_limit = 225000,
256                 .p2_slow = 10, .p2_fast = 5 },
257 };
258 
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260         .dot = { .min = 25000, .max = 350000 },
261         .vco = { .min = 1760000, .max = 3510000 },
262         .n = { .min = 1, .max = 3 },
263         .m = { .min = 79, .max = 118 },
264         .m1 = { .min = 12, .max = 22 },
265         .m2 = { .min = 5, .max = 9 },
266         .p = { .min = 28, .max = 112 },
267         .p1 = { .min = 2, .max = 8 },
268         .p2 = { .dot_limit = 225000,
269                 .p2_slow = 14, .p2_fast = 14 },
270 };
271 
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273         .dot = { .min = 25000, .max = 350000 },
274         .vco = { .min = 1760000, .max = 3510000 },
275         .n = { .min = 1, .max = 3 },
276         .m = { .min = 79, .max = 127 },
277         .m1 = { .min = 12, .max = 22 },
278         .m2 = { .min = 5, .max = 9 },
279         .p = { .min = 14, .max = 56 },
280         .p1 = { .min = 2, .max = 8 },
281         .p2 = { .dot_limit = 225000,
282                 .p2_slow = 7, .p2_fast = 7 },
283 };
284 
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287         .dot = { .min = 25000, .max = 350000 },
288         .vco = { .min = 1760000, .max = 3510000 },
289         .n = { .min = 1, .max = 2 },
290         .m = { .min = 79, .max = 126 },
291         .m1 = { .min = 12, .max = 22 },
292         .m2 = { .min = 5, .max = 9 },
293         .p = { .min = 28, .max = 112 },
294         .p1 = { .min = 2, .max = 8 },
295         .p2 = { .dot_limit = 225000,
296                 .p2_slow = 14, .p2_fast = 14 },
297 };
298 
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300         .dot = { .min = 25000, .max = 350000 },
301         .vco = { .min = 1760000, .max = 3510000 },
302         .n = { .min = 1, .max = 3 },
303         .m = { .min = 79, .max = 126 },
304         .m1 = { .min = 12, .max = 22 },
305         .m2 = { .min = 5, .max = 9 },
306         .p = { .min = 14, .max = 42 },
307         .p1 = { .min = 2, .max = 6 },
308         .p2 = { .dot_limit = 225000,
309                 .p2_slow = 7, .p2_fast = 7 },
310 };
311 
312 static const intel_limit_t intel_limits_vlv = {
313          /*
314           * These are the data rate limits (measured in fast clocks)
315           * since those are the strictest limits we have. The fast
316           * clock and actual rate limits are more relaxed, so checking
317           * them would make no difference.
318           */
319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320         .vco = { .min = 4000000, .max = 6000000 },
321         .n = { .min = 1, .max = 7 },
322         .m1 = { .min = 2, .max = 3 },
323         .m2 = { .min = 11, .max = 156 },
324         .p1 = { .min = 2, .max = 3 },
325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
326 };
327 
328 static void vlv_clock(int refclk, intel_clock_t *clock)
329 {
330         clock->m = clock->m1 * clock->m2;
331         clock->p = clock->p1 * clock->p2;
332         if (WARN_ON(clock->n == 0 || clock->p == 0))
333                 return;
334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
336 }
337 
338 /**
339  * Returns whether any output on the specified pipe is of the specified type
340  */
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342 {
343         struct drm_device *dev = crtc->dev;
344         struct intel_encoder *encoder;
345 
346         for_each_encoder_on_crtc(dev, crtc, encoder)
347                 if (encoder->type == type)
348                         return true;
349 
350         return false;
351 }
352 
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354                                                 int refclk)
355 {
356         struct drm_device *dev = crtc->dev;
357         const intel_limit_t *limit;
358 
359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360                 if (intel_is_dual_link_lvds(dev)) {
361                         if (refclk == 100000)
362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
363                         else
364                                 limit = &intel_limits_ironlake_dual_lvds;
365                 } else {
366                         if (refclk == 100000)
367                                 limit = &intel_limits_ironlake_single_lvds_100m;
368                         else
369                                 limit = &intel_limits_ironlake_single_lvds;
370                 }
371         } else
372                 limit = &intel_limits_ironlake_dac;
373 
374         return limit;
375 }
376 
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378 {
379         struct drm_device *dev = crtc->dev;
380         const intel_limit_t *limit;
381 
382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383                 if (intel_is_dual_link_lvds(dev))
384                         limit = &intel_limits_g4x_dual_channel_lvds;
385                 else
386                         limit = &intel_limits_g4x_single_channel_lvds;
387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389                 limit = &intel_limits_g4x_hdmi;
390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391                 limit = &intel_limits_g4x_sdvo;
392         } else /* The option is for other outputs */
393                 limit = &intel_limits_i9xx_sdvo;
394 
395         return limit;
396 }
397 
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
399 {
400         struct drm_device *dev = crtc->dev;
401         const intel_limit_t *limit;
402 
403         if (HAS_PCH_SPLIT(dev))
404                 limit = intel_ironlake_limit(crtc, refclk);
405         else if (IS_G4X(dev)) {
406                 limit = intel_g4x_limit(crtc);
407         } else if (IS_PINEVIEW(dev)) {
408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409                         limit = &intel_limits_pineview_lvds;
410                 else
411                         limit = &intel_limits_pineview_sdvo;
412         } else if (IS_VALLEYVIEW(dev)) {
413                 limit = &intel_limits_vlv;
414         } else if (!IS_GEN2(dev)) {
415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416                         limit = &intel_limits_i9xx_lvds;
417                 else
418                         limit = &intel_limits_i9xx_sdvo;
419         } else {
420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421                         limit = &intel_limits_i8xx_lvds;
422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423                         limit = &intel_limits_i8xx_dvo;
424                 else
425                         limit = &intel_limits_i8xx_dac;
426         }
427         return limit;
428 }
429 
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
432 {
433         clock->m = clock->m2 + 2;
434         clock->p = clock->p1 * clock->p2;
435         if (WARN_ON(clock->n == 0 || clock->p == 0))
436                 return;
437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
439 }
440 
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
442 {
443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
444 }
445 
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
447 {
448         clock->m = i9xx_dpll_compute_m(clock);
449         clock->p = clock->p1 * clock->p2;
450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
451                 return;
452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
454 }
455 
456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
457 /**
458  * Returns whether the given set of divisors are valid for a given refclk with
459  * the given connectors.
460  */
461 
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463                                const intel_limit_t *limit,
464                                const intel_clock_t *clock)
465 {
466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
467                 INTELPllInvalid("n out of range\n");
468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
469                 INTELPllInvalid("p1 out of range\n");
470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
471                 INTELPllInvalid("m2 out of range\n");
472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
473                 INTELPllInvalid("m1 out of range\n");
474 
475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476                 if (clock->m1 <= clock->m2)
477                         INTELPllInvalid("m1 <= m2\n");
478 
479         if (!IS_VALLEYVIEW(dev)) {
480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
481                         INTELPllInvalid("p out of range\n");
482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
483                         INTELPllInvalid("m out of range\n");
484         }
485 
486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487                 INTELPllInvalid("vco out of range\n");
488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489          * connector, etc., rather than just a single range.
490          */
491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492                 INTELPllInvalid("dot out of range\n");
493 
494         return true;
495 }
496 
497 static bool
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499                     int target, int refclk, intel_clock_t *match_clock,
500                     intel_clock_t *best_clock)
501 {
502         struct drm_device *dev = crtc->dev;
503         intel_clock_t clock;
504         int err = target;
505 
506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
507                 /*
508                  * For LVDS just rely on its current settings for dual-channel.
509                  * We haven't figured out how to reliably set up different
510                  * single/dual channel state, if we even can.
511                  */
512                 if (intel_is_dual_link_lvds(dev))
513                         clock.p2 = limit->p2.p2_fast;
514                 else
515                         clock.p2 = limit->p2.p2_slow;
516         } else {
517                 if (target < limit->p2.dot_limit)
518                         clock.p2 = limit->p2.p2_slow;
519                 else
520                         clock.p2 = limit->p2.p2_fast;
521         }
522 
523         memset(best_clock, 0, sizeof(*best_clock));
524 
525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
526              clock.m1++) {
527                 for (clock.m2 = limit->m2.min;
528                      clock.m2 <= limit->m2.max; clock.m2++) {
529                         if (clock.m2 >= clock.m1)
530                                 break;
531                         for (clock.n = limit->n.min;
532                              clock.n <= limit->n.max; clock.n++) {
533                                 for (clock.p1 = limit->p1.min;
534                                         clock.p1 <= limit->p1.max; clock.p1++) {
535                                         int this_err;
536 
537                                         i9xx_clock(refclk, &clock);
538                                         if (!intel_PLL_is_valid(dev, limit,
539                                                                 &clock))
540                                                 continue;
541                                         if (match_clock &&
542                                             clock.p != match_clock->p)
543                                                 continue;
544 
545                                         this_err = abs(clock.dot - target);
546                                         if (this_err < err) {
547                                                 *best_clock = clock;
548                                                 err = this_err;
549                                         }
550                                 }
551                         }
552                 }
553         }
554 
555         return (err != target);
556 }
557 
558 static bool
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560                    int target, int refclk, intel_clock_t *match_clock,
561                    intel_clock_t *best_clock)
562 {
563         struct drm_device *dev = crtc->dev;
564         intel_clock_t clock;
565         int err = target;
566 
567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
568                 /*
569                  * For LVDS just rely on its current settings for dual-channel.
570                  * We haven't figured out how to reliably set up different
571                  * single/dual channel state, if we even can.
572                  */
573                 if (intel_is_dual_link_lvds(dev))
574                         clock.p2 = limit->p2.p2_fast;
575                 else
576                         clock.p2 = limit->p2.p2_slow;
577         } else {
578                 if (target < limit->p2.dot_limit)
579                         clock.p2 = limit->p2.p2_slow;
580                 else
581                         clock.p2 = limit->p2.p2_fast;
582         }
583 
584         memset(best_clock, 0, sizeof(*best_clock));
585 
586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
587              clock.m1++) {
588                 for (clock.m2 = limit->m2.min;
589                      clock.m2 <= limit->m2.max; clock.m2++) {
590                         for (clock.n = limit->n.min;
591                              clock.n <= limit->n.max; clock.n++) {
592                                 for (clock.p1 = limit->p1.min;
593                                         clock.p1 <= limit->p1.max; clock.p1++) {
594                                         int this_err;
595 
596                                         pineview_clock(refclk, &clock);
597                                         if (!intel_PLL_is_valid(dev, limit,
598                                                                 &clock))
599                                                 continue;
600                                         if (match_clock &&
601                                             clock.p != match_clock->p)
602                                                 continue;
603 
604                                         this_err = abs(clock.dot - target);
605                                         if (this_err < err) {
606                                                 *best_clock = clock;
607                                                 err = this_err;
608                                         }
609                                 }
610                         }
611                 }
612         }
613 
614         return (err != target);
615 }
616 
617 static bool
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619                    int target, int refclk, intel_clock_t *match_clock,
620                    intel_clock_t *best_clock)
621 {
622         struct drm_device *dev = crtc->dev;
623         intel_clock_t clock;
624         int max_n;
625         bool found;
626         /* approximately equals target * 0.00585 */
627         int err_most = (target >> 8) + (target >> 9);
628         found = false;
629 
630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631                 if (intel_is_dual_link_lvds(dev))
632                         clock.p2 = limit->p2.p2_fast;
633                 else
634                         clock.p2 = limit->p2.p2_slow;
635         } else {
636                 if (target < limit->p2.dot_limit)
637                         clock.p2 = limit->p2.p2_slow;
638                 else
639                         clock.p2 = limit->p2.p2_fast;
640         }
641 
642         memset(best_clock, 0, sizeof(*best_clock));
643         max_n = limit->n.max;
644         /* based on hardware requirement, prefer smaller n to precision */
645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646                 /* based on hardware requirement, prefere larger m1,m2 */
647                 for (clock.m1 = limit->m1.max;
648                      clock.m1 >= limit->m1.min; clock.m1--) {
649                         for (clock.m2 = limit->m2.max;
650                              clock.m2 >= limit->m2.min; clock.m2--) {
651                                 for (clock.p1 = limit->p1.max;
652                                      clock.p1 >= limit->p1.min; clock.p1--) {
653                                         int this_err;
654 
655                                         i9xx_clock(refclk, &clock);
656                                         if (!intel_PLL_is_valid(dev, limit,
657                                                                 &clock))
658                                                 continue;
659 
660                                         this_err = abs(clock.dot - target);
661                                         if (this_err < err_most) {
662                                                 *best_clock = clock;
663                                                 err_most = this_err;
664                                                 max_n = clock.n;
665                                                 found = true;
666                                         }
667                                 }
668                         }
669                 }
670         }
671         return found;
672 }
673 
674 static bool
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676                    int target, int refclk, intel_clock_t *match_clock,
677                    intel_clock_t *best_clock)
678 {
679         struct drm_device *dev = crtc->dev;
680         intel_clock_t clock;
681         unsigned int bestppm = 1000000;
682         /* min update 19.2 MHz */
683         int max_n = min(limit->n.max, refclk / 19200);
684         bool found = false;
685 
686         target *= 5; /* fast clock */
687 
688         memset(best_clock, 0, sizeof(*best_clock));
689 
690         /* based on hardware requirement, prefer smaller n to precision */
691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695                                 clock.p = clock.p1 * clock.p2;
696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698                                         unsigned int ppm, diff;
699 
700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
701                                                                      refclk * clock.m1);
702 
703                                         vlv_clock(refclk, &clock);
704 
705                                         if (!intel_PLL_is_valid(dev, limit,
706                                                                 &clock))
707                                                 continue;
708 
709                                         diff = abs(clock.dot - target);
710                                         ppm = div_u64(1000000ULL * diff, target);
711 
712                                         if (ppm < 100 && clock.p > best_clock->p) {
713                                                 bestppm = 0;
714                                                 *best_clock = clock;
715                                                 found = true;
716                                         }
717 
718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
719                                                 bestppm = ppm;
720                                                 *best_clock = clock;
721                                                 found = true;
722                                         }
723                                 }
724                         }
725                 }
726         }
727 
728         return found;
729 }
730 
731 bool intel_crtc_active(struct drm_crtc *crtc)
732 {
733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734 
735         /* Be paranoid as we can arrive here with only partial
736          * state retrieved from the hardware during setup.
737          *
738          * We can ditch the adjusted_mode.crtc_clock check as soon
739          * as Haswell has gained clock readout/fastboot support.
740          *
741          * We can ditch the crtc->fb check as soon as we can
742          * properly reconstruct framebuffers.
743          */
744         return intel_crtc->active && crtc->fb &&
745                 intel_crtc->config.adjusted_mode.crtc_clock;
746 }
747 
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
749                                              enum pipe pipe)
750 {
751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
753 
754         return intel_crtc->config.cpu_transcoder;
755 }
756 
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
758 {
759         struct drm_i915_private *dev_priv = dev->dev_private;
760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
761 
762         frame = I915_READ(frame_reg);
763 
764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765                 DRM_DEBUG_KMS("vblank wait timed out\n");
766 }
767 
768 /**
769  * intel_wait_for_vblank - wait for vblank on a given pipe
770  * @dev: drm device
771  * @pipe: pipe to wait for
772  *
773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
774  * mode setting code.
775  */
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
777 {
778         struct drm_i915_private *dev_priv = dev->dev_private;
779         int pipestat_reg = PIPESTAT(pipe);
780 
781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782                 g4x_wait_for_vblank(dev, pipe);
783                 return;
784         }
785 
786         /* Clear existing vblank status. Note this will clear any other
787          * sticky status fields as well.
788          *
789          * This races with i915_driver_irq_handler() with the result
790          * that either function could miss a vblank event.  Here it is not
791          * fatal, as we will either wait upon the next vblank interrupt or
792          * timeout.  Generally speaking intel_wait_for_vblank() is only
793          * called during modeset at which time the GPU should be idle and
794          * should *not* be performing page flips and thus not waiting on
795          * vblanks...
796          * Currently, the result of us stealing a vblank from the irq
797          * handler is that a single frame will be skipped during swapbuffers.
798          */
799         I915_WRITE(pipestat_reg,
800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
801 
802         /* Wait for vblank interrupt bit to set */
803         if (wait_for(I915_READ(pipestat_reg) &
804                      PIPE_VBLANK_INTERRUPT_STATUS,
805                      50))
806                 DRM_DEBUG_KMS("vblank wait timed out\n");
807 }
808 
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
810 {
811         struct drm_i915_private *dev_priv = dev->dev_private;
812         u32 reg = PIPEDSL(pipe);
813         u32 line1, line2;
814         u32 line_mask;
815 
816         if (IS_GEN2(dev))
817                 line_mask = DSL_LINEMASK_GEN2;
818         else
819                 line_mask = DSL_LINEMASK_GEN3;
820 
821         line1 = I915_READ(reg) & line_mask;
822         mdelay(5);
823         line2 = I915_READ(reg) & line_mask;
824 
825         return line1 == line2;
826 }
827 
828 /*
829  * intel_wait_for_pipe_off - wait for pipe to turn off
830  * @dev: drm device
831  * @pipe: pipe to wait for
832  *
833  * After disabling a pipe, we can't wait for vblank in the usual way,
834  * spinning on the vblank interrupt status bit, since we won't actually
835  * see an interrupt when the pipe is disabled.
836  *
837  * On Gen4 and above:
838  *   wait for the pipe register state bit to turn off
839  *
840  * Otherwise:
841  *   wait for the display line value to settle (it usually
842  *   ends up stopping at the start of the next frame).
843  *
844  */
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
846 {
847         struct drm_i915_private *dev_priv = dev->dev_private;
848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
849                                                                       pipe);
850 
851         if (INTEL_INFO(dev)->gen >= 4) {
852                 int reg = PIPECONF(cpu_transcoder);
853 
854                 /* Wait for the Pipe State to go off */
855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856                              100))
857                         WARN(1, "pipe_off wait timed out\n");
858         } else {
859                 /* Wait for the display line to settle */
860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861                         WARN(1, "pipe_off wait timed out\n");
862         }
863 }
864 
865 /*
866  * ibx_digital_port_connected - is the specified port connected?
867  * @dev_priv: i915 private structure
868  * @port: the port to test
869  *
870  * Returns true if @port is connected, false otherwise.
871  */
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873                                 struct intel_digital_port *port)
874 {
875         u32 bit;
876 
877         if (HAS_PCH_IBX(dev_priv->dev)) {
878                 switch(port->port) {
879                 case PORT_B:
880                         bit = SDE_PORTB_HOTPLUG;
881                         break;
882                 case PORT_C:
883                         bit = SDE_PORTC_HOTPLUG;
884                         break;
885                 case PORT_D:
886                         bit = SDE_PORTD_HOTPLUG;
887                         break;
888                 default:
889                         return true;
890                 }
891         } else {
892                 switch(port->port) {
893                 case PORT_B:
894                         bit = SDE_PORTB_HOTPLUG_CPT;
895                         break;
896                 case PORT_C:
897                         bit = SDE_PORTC_HOTPLUG_CPT;
898                         break;
899                 case PORT_D:
900                         bit = SDE_PORTD_HOTPLUG_CPT;
901                         break;
902                 default:
903                         return true;
904                 }
905         }
906 
907         return I915_READ(SDEISR) & bit;
908 }
909 
910 static const char *state_string(bool enabled)
911 {
912         return enabled ? "on" : "off";
913 }
914 
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917                 enum pipe pipe, bool state)
918 {
919         int reg;
920         u32 val;
921         bool cur_state;
922 
923         reg = DPLL(pipe);
924         val = I915_READ(reg);
925         cur_state = !!(val & DPLL_VCO_ENABLE);
926         WARN(cur_state != state,
927              "PLL state assertion failure (expected %s, current %s)\n",
928              state_string(state), state_string(cur_state));
929 }
930 
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933 {
934         u32 val;
935         bool cur_state;
936 
937         mutex_lock(&dev_priv->dpio_lock);
938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939         mutex_unlock(&dev_priv->dpio_lock);
940 
941         cur_state = val & DSI_PLL_VCO_EN;
942         WARN(cur_state != state,
943              "DSI PLL state assertion failure (expected %s, current %s)\n",
944              state_string(state), state_string(cur_state));
945 }
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948 
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951 {
952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953 
954         if (crtc->config.shared_dpll < 0)
955                 return NULL;
956 
957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
958 }
959 
960 /* For ILK+ */
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962                         struct intel_shared_dpll *pll,
963                         bool state)
964 {
965         bool cur_state;
966         struct intel_dpll_hw_state hw_state;
967 
968         if (HAS_PCH_LPT(dev_priv->dev)) {
969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970                 return;
971         }
972 
973         if (WARN (!pll,
974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
975                 return;
976 
977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978         WARN(cur_state != state,
979              "%s assertion failure (expected %s, current %s)\n",
980              pll->name, state_string(state), state_string(cur_state));
981 }
982 
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984                           enum pipe pipe, bool state)
985 {
986         int reg;
987         u32 val;
988         bool cur_state;
989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990                                                                       pipe);
991 
992         if (HAS_DDI(dev_priv->dev)) {
993                 /* DDI does not have a specific FDI_TX register */
994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995                 val = I915_READ(reg);
996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
997         } else {
998                 reg = FDI_TX_CTL(pipe);
999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008 
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015 
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025 
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031 
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035 
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039 
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044 
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051 
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059 
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067 
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075 
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080 
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083 
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088 
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094 
1095         if (IS_845G(dev) || IS_I865G(dev))
1096                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1097         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1098                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1099         else
1100                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1101 
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108 
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117 
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121 
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130 
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135 
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142 
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150 
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153 
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161 
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171 
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183 
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190 
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213 
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218 
1219         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1220 
1221         val = I915_READ(PCH_DREF_CONTROL);
1222         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223                             DREF_SUPERSPREAD_SOURCE_MASK));
1224         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225 }
1226 
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228                                            enum pipe pipe)
1229 {
1230         int reg;
1231         u32 val;
1232         bool enabled;
1233 
1234         reg = PCH_TRANSCONF(pipe);
1235         val = I915_READ(reg);
1236         enabled = !!(val & TRANS_ENABLE);
1237         WARN(enabled,
1238              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239              pipe_name(pipe));
1240 }
1241 
1242 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243                             enum pipe pipe, u32 port_sel, u32 val)
1244 {
1245         if ((val & DP_PORT_EN) == 0)
1246                 return false;
1247 
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252                         return false;
1253         } else {
1254                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255                         return false;
1256         }
1257         return true;
1258 }
1259 
1260 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261                               enum pipe pipe, u32 val)
1262 {
1263         if ((val & SDVO_ENABLE) == 0)
1264                 return false;
1265 
1266         if (HAS_PCH_CPT(dev_priv->dev)) {
1267                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1268                         return false;
1269         } else {
1270                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1271                         return false;
1272         }
1273         return true;
1274 }
1275 
1276 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277                               enum pipe pipe, u32 val)
1278 {
1279         if ((val & LVDS_PORT_EN) == 0)
1280                 return false;
1281 
1282         if (HAS_PCH_CPT(dev_priv->dev)) {
1283                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284                         return false;
1285         } else {
1286                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287                         return false;
1288         }
1289         return true;
1290 }
1291 
1292 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293                               enum pipe pipe, u32 val)
1294 {
1295         if ((val & ADPA_DAC_ENABLE) == 0)
1296                 return false;
1297         if (HAS_PCH_CPT(dev_priv->dev)) {
1298                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299                         return false;
1300         } else {
1301                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302                         return false;
1303         }
1304         return true;
1305 }
1306 
1307 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1308                                    enum pipe pipe, int reg, u32 port_sel)
1309 {
1310         u32 val = I915_READ(reg);
1311         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1312              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313              reg, pipe_name(pipe));
1314 
1315         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316              && (val & DP_PIPEB_SELECT),
1317              "IBX PCH dp port still using transcoder B\n");
1318 }
1319 
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321                                      enum pipe pipe, int reg)
1322 {
1323         u32 val = I915_READ(reg);
1324         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1325              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326              reg, pipe_name(pipe));
1327 
1328         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1329              && (val & SDVO_PIPE_B_SELECT),
1330              "IBX PCH hdmi port still using transcoder B\n");
1331 }
1332 
1333 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334                                       enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338 
1339         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1342 
1343         reg = PCH_ADPA;
1344         val = I915_READ(reg);
1345         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1346              "PCH VGA enabled on transcoder %c, should be disabled\n",
1347              pipe_name(pipe));
1348 
1349         reg = PCH_LVDS;
1350         val = I915_READ(reg);
1351         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1352              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1353              pipe_name(pipe));
1354 
1355         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1358 }
1359 
1360 static void intel_init_dpio(struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363 
1364         if (!IS_VALLEYVIEW(dev))
1365                 return;
1366 
1367         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1368 }
1369 
1370 static void intel_reset_dpio(struct drm_device *dev)
1371 {
1372         struct drm_i915_private *dev_priv = dev->dev_private;
1373 
1374         if (!IS_VALLEYVIEW(dev))
1375                 return;
1376 
1377         /*
1378          * Enable the CRI clock source so we can get at the display and the
1379          * reference clock for VGA hotplug / manual detection.
1380          */
1381         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1382                    DPLL_REFA_CLK_ENABLE_VLV |
1383                    DPLL_INTEGRATED_CRI_CLK_VLV);
1384 
1385         /*
1386          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1388          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389          *   b. The other bits such as sfr settings / modesel may all be set
1390          *      to 0.
1391          *
1392          * This should only be done on init and resume from S3 with both
1393          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394          */
1395         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1396 }
1397 
1398 static void vlv_enable_pll(struct intel_crtc *crtc)
1399 {
1400         struct drm_device *dev = crtc->base.dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         int reg = DPLL(crtc->pipe);
1403         u32 dpll = crtc->config.dpll_hw_state.dpll;
1404 
1405         assert_pipe_disabled(dev_priv, crtc->pipe);
1406 
1407         /* No really, not for ILK+ */
1408         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409 
1410         /* PLL is protected by panel, make sure we can write it */
1411         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1412                 assert_panel_unlocked(dev_priv, crtc->pipe);
1413 
1414         I915_WRITE(reg, dpll);
1415         POSTING_READ(reg);
1416         udelay(150);
1417 
1418         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1419                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420 
1421         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1422         POSTING_READ(DPLL_MD(crtc->pipe));
1423 
1424         /* We do this three times for luck */
1425         I915_WRITE(reg, dpll);
1426         POSTING_READ(reg);
1427         udelay(150); /* wait for warmup */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434 }
1435 
1436 static void i9xx_enable_pll(struct intel_crtc *crtc)
1437 {
1438         struct drm_device *dev = crtc->base.dev;
1439         struct drm_i915_private *dev_priv = dev->dev_private;
1440         int reg = DPLL(crtc->pipe);
1441         u32 dpll = crtc->config.dpll_hw_state.dpll;
1442 
1443         assert_pipe_disabled(dev_priv, crtc->pipe);
1444 
1445         /* No really, not for ILK+ */
1446         BUG_ON(dev_priv->info->gen >= 5);
1447 
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev) && !IS_I830(dev))
1450                 assert_panel_unlocked(dev_priv, crtc->pipe);
1451 
1452         I915_WRITE(reg, dpll);
1453 
1454         /* Wait for the clocks to stabilize. */
1455         POSTING_READ(reg);
1456         udelay(150);
1457 
1458         if (INTEL_INFO(dev)->gen >= 4) {
1459                 I915_WRITE(DPLL_MD(crtc->pipe),
1460                            crtc->config.dpll_hw_state.dpll_md);
1461         } else {
1462                 /* The pixel multiplier can only be updated once the
1463                  * DPLL is enabled and the clocks are stable.
1464                  *
1465                  * So write it again.
1466                  */
1467                 I915_WRITE(reg, dpll);
1468         }
1469 
1470         /* We do this three times for luck */
1471         I915_WRITE(reg, dpll);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480 }
1481 
1482 /**
1483  * i9xx_disable_pll - disable a PLL
1484  * @dev_priv: i915 private structure
1485  * @pipe: pipe PLL to disable
1486  *
1487  * Disable the PLL for @pipe, making sure the pipe is off first.
1488  *
1489  * Note!  This is for pre-ILK only.
1490  */
1491 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1492 {
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496 
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499 
1500         I915_WRITE(DPLL(pipe), 0);
1501         POSTING_READ(DPLL(pipe));
1502 }
1503 
1504 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506         u32 val = 0;
1507 
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510 
1511         /*
1512          * Leave integrated clock source and reference clock enabled for pipe B.
1513          * The latter is needed for VGA hotplug / manual detection.
1514          */
1515         if (pipe == PIPE_B)
1516                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1517         I915_WRITE(DPLL(pipe), val);
1518         POSTING_READ(DPLL(pipe));
1519 }
1520 
1521 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1522                 struct intel_digital_port *dport)
1523 {
1524         u32 port_mask;
1525 
1526         switch (dport->port) {
1527         case PORT_B:
1528                 port_mask = DPLL_PORTB_READY_MASK;
1529                 break;
1530         case PORT_C:
1531                 port_mask = DPLL_PORTC_READY_MASK;
1532                 break;
1533         default:
1534                 BUG();
1535         }
1536 
1537         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1538                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539                      port_name(dport->port), I915_READ(DPLL(0)));
1540 }
1541 
1542 /**
1543  * ironlake_enable_shared_dpll - enable PCH PLL
1544  * @dev_priv: i915 private structure
1545  * @pipe: pipe PLL to enable
1546  *
1547  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548  * drives the transcoder clock.
1549  */
1550 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1551 {
1552         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1553         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1554 
1555         /* PCH PLLs only available on ILK, SNB and IVB */
1556         BUG_ON(dev_priv->info->gen < 5);
1557         if (WARN_ON(pll == NULL))
1558                 return;
1559 
1560         if (WARN_ON(pll->refcount == 0))
1561                 return;
1562 
1563         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564                       pll->name, pll->active, pll->on,
1565                       crtc->base.base.id);
1566 
1567         if (pll->active++) {
1568                 WARN_ON(!pll->on);
1569                 assert_shared_dpll_enabled(dev_priv, pll);
1570                 return;
1571         }
1572         WARN_ON(pll->on);
1573 
1574         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1575         pll->enable(dev_priv, pll);
1576         pll->on = true;
1577 }
1578 
1579 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1580 {
1581         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1582         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1583 
1584         /* PCH only available on ILK+ */
1585         BUG_ON(dev_priv->info->gen < 5);
1586         if (WARN_ON(pll == NULL))
1587                return;
1588 
1589         if (WARN_ON(pll->refcount == 0))
1590                 return;
1591 
1592         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593                       pll->name, pll->active, pll->on,
1594                       crtc->base.base.id);
1595 
1596         if (WARN_ON(pll->active == 0)) {
1597                 assert_shared_dpll_disabled(dev_priv, pll);
1598                 return;
1599         }
1600 
1601         assert_shared_dpll_enabled(dev_priv, pll);
1602         WARN_ON(!pll->on);
1603         if (--pll->active)
1604                 return;
1605 
1606         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1607         pll->disable(dev_priv, pll);
1608         pll->on = false;
1609 }
1610 
1611 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1612                                            enum pipe pipe)
1613 {
1614         struct drm_device *dev = dev_priv->dev;
1615         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617         uint32_t reg, val, pipeconf_val;
1618 
1619         /* PCH only available on ILK+ */
1620         BUG_ON(dev_priv->info->gen < 5);
1621 
1622         /* Make sure PCH DPLL is enabled */
1623         assert_shared_dpll_enabled(dev_priv,
1624                                    intel_crtc_to_shared_dpll(intel_crtc));
1625 
1626         /* FDI must be feeding us bits for PCH ports */
1627         assert_fdi_tx_enabled(dev_priv, pipe);
1628         assert_fdi_rx_enabled(dev_priv, pipe);
1629 
1630         if (HAS_PCH_CPT(dev)) {
1631                 /* Workaround: Set the timing override bit before enabling the
1632                  * pch transcoder. */
1633                 reg = TRANS_CHICKEN2(pipe);
1634                 val = I915_READ(reg);
1635                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1636                 I915_WRITE(reg, val);
1637         }
1638 
1639         reg = PCH_TRANSCONF(pipe);
1640         val = I915_READ(reg);
1641         pipeconf_val = I915_READ(PIPECONF(pipe));
1642 
1643         if (HAS_PCH_IBX(dev_priv->dev)) {
1644                 /*
1645                  * make the BPC in transcoder be consistent with
1646                  * that in pipeconf reg.
1647                  */
1648                 val &= ~PIPECONF_BPC_MASK;
1649                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1650         }
1651 
1652         val &= ~TRANS_INTERLACE_MASK;
1653         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1654                 if (HAS_PCH_IBX(dev_priv->dev) &&
1655                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1656                         val |= TRANS_LEGACY_INTERLACED_ILK;
1657                 else
1658                         val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661 
1662         I915_WRITE(reg, val | TRANS_ENABLE);
1663         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1665 }
1666 
1667 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                       enum transcoder cpu_transcoder)
1669 {
1670         u32 val, pipeconf_val;
1671 
1672         /* PCH only available on ILK+ */
1673         BUG_ON(dev_priv->info->gen < 5);
1674 
1675         /* FDI must be feeding us bits for PCH ports */
1676         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1677         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1678 
1679         /* Workaround: set timing override bit. */
1680         val = I915_READ(_TRANSA_CHICKEN2);
1681         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1682         I915_WRITE(_TRANSA_CHICKEN2, val);
1683 
1684         val = TRANS_ENABLE;
1685         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1686 
1687         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1688             PIPECONF_INTERLACED_ILK)
1689                 val |= TRANS_INTERLACED;
1690         else
1691                 val |= TRANS_PROGRESSIVE;
1692 
1693         I915_WRITE(LPT_TRANSCONF, val);
1694         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1695                 DRM_ERROR("Failed to enable PCH transcoder\n");
1696 }
1697 
1698 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1699                                             enum pipe pipe)
1700 {
1701         struct drm_device *dev = dev_priv->dev;
1702         uint32_t reg, val;
1703 
1704         /* FDI relies on the transcoder */
1705         assert_fdi_tx_disabled(dev_priv, pipe);
1706         assert_fdi_rx_disabled(dev_priv, pipe);
1707 
1708         /* Ports must be off as well */
1709         assert_pch_ports_disabled(dev_priv, pipe);
1710 
1711         reg = PCH_TRANSCONF(pipe);
1712         val = I915_READ(reg);
1713         val &= ~TRANS_ENABLE;
1714         I915_WRITE(reg, val);
1715         /* wait for PCH transcoder off, transcoder state */
1716         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1717                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1718 
1719         if (!HAS_PCH_IBX(dev)) {
1720                 /* Workaround: Clear the timing override chicken bit again. */
1721                 reg = TRANS_CHICKEN2(pipe);
1722                 val = I915_READ(reg);
1723                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1724                 I915_WRITE(reg, val);
1725         }
1726 }
1727 
1728 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1729 {
1730         u32 val;
1731 
1732         val = I915_READ(LPT_TRANSCONF);
1733         val &= ~TRANS_ENABLE;
1734         I915_WRITE(LPT_TRANSCONF, val);
1735         /* wait for PCH transcoder off, transcoder state */
1736         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1737                 DRM_ERROR("Failed to disable PCH transcoder\n");
1738 
1739         /* Workaround: clear timing override bit. */
1740         val = I915_READ(_TRANSA_CHICKEN2);
1741         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1742         I915_WRITE(_TRANSA_CHICKEN2, val);
1743 }
1744 
1745 /**
1746  * intel_enable_pipe - enable a pipe, asserting requirements
1747  * @dev_priv: i915 private structure
1748  * @pipe: pipe to enable
1749  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1750  *
1751  * Enable @pipe, making sure that various hardware specific requirements
1752  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1753  *
1754  * @pipe should be %PIPE_A or %PIPE_B.
1755  *
1756  * Will wait until the pipe is actually running (i.e. first vblank) before
1757  * returning.
1758  */
1759 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1760                               bool pch_port, bool dsi)
1761 {
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767 
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771 
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776 
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (dsi)
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (pch_port) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796 
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE)
1800                 return;
1801 
1802         I915_WRITE(reg, val | PIPECONF_ENABLE);
1803         intel_wait_for_vblank(dev_priv->dev, pipe);
1804 }
1805 
1806 /**
1807  * intel_disable_pipe - disable a pipe, asserting requirements
1808  * @dev_priv: i915 private structure
1809  * @pipe: pipe to disable
1810  *
1811  * Disable @pipe, making sure that various hardware specific requirements
1812  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1813  *
1814  * @pipe should be %PIPE_A or %PIPE_B.
1815  *
1816  * Will wait until the pipe has shut down before returning.
1817  */
1818 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1819                                enum pipe pipe)
1820 {
1821         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1822                                                                       pipe);
1823         int reg;
1824         u32 val;
1825 
1826         /*
1827          * Make sure planes won't keep trying to pump pixels to us,
1828          * or we might hang the display.
1829          */
1830         assert_planes_disabled(dev_priv, pipe);
1831         assert_cursor_disabled(dev_priv, pipe);
1832         assert_sprites_disabled(dev_priv, pipe);
1833 
1834         /* Don't disable pipe A or pipe A PLLs if needed */
1835         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1836                 return;
1837 
1838         reg = PIPECONF(cpu_transcoder);
1839         val = I915_READ(reg);
1840         if ((val & PIPECONF_ENABLE) == 0)
1841                 return;
1842 
1843         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1844         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1845 }
1846 
1847 /*
1848  * Plane regs are double buffered, going from enabled->disabled needs a
1849  * trigger in order to latch.  The display address reg provides this.
1850  */
1851 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1852                                enum plane plane)
1853 {
1854         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1855 
1856         I915_WRITE(reg, I915_READ(reg));
1857         POSTING_READ(reg);
1858 }
1859 
1860 /**
1861  * intel_enable_primary_plane - enable the primary plane on a given pipe
1862  * @dev_priv: i915 private structure
1863  * @plane: plane to enable
1864  * @pipe: pipe being fed
1865  *
1866  * Enable @plane on @pipe, making sure that @pipe is running first.
1867  */
1868 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1869                                        enum plane plane, enum pipe pipe)
1870 {
1871         struct intel_crtc *intel_crtc =
1872                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1873         int reg;
1874         u32 val;
1875 
1876         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877         assert_pipe_enabled(dev_priv, pipe);
1878 
1879         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1880 
1881         intel_crtc->primary_enabled = true;
1882 
1883         reg = DSPCNTR(plane);
1884         val = I915_READ(reg);
1885         if (val & DISPLAY_PLANE_ENABLE)
1886                 return;
1887 
1888         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1889         intel_flush_primary_plane(dev_priv, plane);
1890         intel_wait_for_vblank(dev_priv->dev, pipe);
1891 }
1892 
1893 /**
1894  * intel_disable_primary_plane - disable the primary plane
1895  * @dev_priv: i915 private structure
1896  * @plane: plane to disable
1897  * @pipe: pipe consuming the data
1898  *
1899  * Disable @plane; should be an independent operation.
1900  */
1901 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1902                                         enum plane plane, enum pipe pipe)
1903 {
1904         struct intel_crtc *intel_crtc =
1905                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1906         int reg;
1907         u32 val;
1908 
1909         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1910 
1911         intel_crtc->primary_enabled = false;
1912 
1913         reg = DSPCNTR(plane);
1914         val = I915_READ(reg);
1915         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1916                 return;
1917 
1918         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1919         intel_flush_primary_plane(dev_priv, plane);
1920         intel_wait_for_vblank(dev_priv->dev, pipe);
1921 }
1922 
1923 static bool need_vtd_wa(struct drm_device *dev)
1924 {
1925 #ifdef CONFIG_INTEL_IOMMU
1926         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1927                 return true;
1928 #endif
1929         return false;
1930 }
1931 
1932 int
1933 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1934                            struct drm_i915_gem_object *obj,
1935                            struct intel_ring_buffer *pipelined)
1936 {
1937         struct drm_i915_private *dev_priv = dev->dev_private;
1938         u32 alignment;
1939         int ret;
1940 
1941         switch (obj->tiling_mode) {
1942         case I915_TILING_NONE:
1943                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1944                         alignment = 128 * 1024;
1945                 else if (INTEL_INFO(dev)->gen >= 4)
1946                         alignment = 4 * 1024;
1947                 else
1948                         alignment = 64 * 1024;
1949                 break;
1950         case I915_TILING_X:
1951                 /* pin() will align the object as required by fence */
1952                 alignment = 0;
1953                 break;
1954         case I915_TILING_Y:
1955                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1956                 return -EINVAL;
1957         default:
1958                 BUG();
1959         }
1960 
1961         /* Note that the w/a also requires 64 PTE of padding following the
1962          * bo. We currently fill all unused PTE with the shadow page and so
1963          * we should always have valid PTE following the scanout preventing
1964          * the VT-d warning.
1965          */
1966         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1967                 alignment = 256 * 1024;
1968 
1969         dev_priv->mm.interruptible = false;
1970         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1971         if (ret)
1972                 goto err_interruptible;
1973 
1974         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975          * fence, whereas 965+ only requires a fence if using
1976          * framebuffer compression.  For simplicity, we always install
1977          * a fence as the cost is not that onerous.
1978          */
1979         ret = i915_gem_object_get_fence(obj);
1980         if (ret)
1981                 goto err_unpin;
1982 
1983         i915_gem_object_pin_fence(obj);
1984 
1985         dev_priv->mm.interruptible = true;
1986         return 0;
1987 
1988 err_unpin:
1989         i915_gem_object_unpin_from_display_plane(obj);
1990 err_interruptible:
1991         dev_priv->mm.interruptible = true;
1992         return ret;
1993 }
1994 
1995 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1996 {
1997         i915_gem_object_unpin_fence(obj);
1998         i915_gem_object_unpin_from_display_plane(obj);
1999 }
2000 
2001 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002  * is assumed to be a power-of-two. */
2003 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2004                                              unsigned int tiling_mode,
2005                                              unsigned int cpp,
2006                                              unsigned int pitch)
2007 {
2008         if (tiling_mode != I915_TILING_NONE) {
2009                 unsigned int tile_rows, tiles;
2010 
2011                 tile_rows = *y / 8;
2012                 *y %= 8;
2013 
2014                 tiles = *x / (512/cpp);
2015                 *x %= 512/cpp;
2016 
2017                 return tile_rows * pitch * 8 + tiles * 4096;
2018         } else {
2019                 unsigned int offset;
2020 
2021                 offset = *y * pitch + *x * cpp;
2022                 *y = 0;
2023                 *x = (offset & 4095) / cpp;
2024                 return offset & -4096;
2025         }
2026 }
2027 
2028 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2029                              int x, int y)
2030 {
2031         struct drm_device *dev = crtc->dev;
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2034         struct intel_framebuffer *intel_fb;
2035         struct drm_i915_gem_object *obj;
2036         int plane = intel_crtc->plane;
2037         unsigned long linear_offset;
2038         u32 dspcntr;
2039         u32 reg;
2040 
2041         switch (plane) {
2042         case 0:
2043         case 1:
2044                 break;
2045         default:
2046                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2047                 return -EINVAL;
2048         }
2049 
2050         intel_fb = to_intel_framebuffer(fb);
2051         obj = intel_fb->obj;
2052 
2053         reg = DSPCNTR(plane);
2054         dspcntr = I915_READ(reg);
2055         /* Mask out pixel format bits in case we change it */
2056         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2057         switch (fb->pixel_format) {
2058         case DRM_FORMAT_C8:
2059                 dspcntr |= DISPPLANE_8BPP;
2060                 break;
2061         case DRM_FORMAT_XRGB1555:
2062         case DRM_FORMAT_ARGB1555:
2063                 dspcntr |= DISPPLANE_BGRX555;
2064                 break;
2065         case DRM_FORMAT_RGB565:
2066                 dspcntr |= DISPPLANE_BGRX565;
2067                 break;
2068         case DRM_FORMAT_XRGB8888:
2069         case DRM_FORMAT_ARGB8888:
2070                 dspcntr |= DISPPLANE_BGRX888;
2071                 break;
2072         case DRM_FORMAT_XBGR8888:
2073         case DRM_FORMAT_ABGR8888:
2074                 dspcntr |= DISPPLANE_RGBX888;
2075                 break;
2076         case DRM_FORMAT_XRGB2101010:
2077         case DRM_FORMAT_ARGB2101010:
2078                 dspcntr |= DISPPLANE_BGRX101010;
2079                 break;
2080         case DRM_FORMAT_XBGR2101010:
2081         case DRM_FORMAT_ABGR2101010:
2082                 dspcntr |= DISPPLANE_RGBX101010;
2083                 break;
2084         default:
2085                 BUG();
2086         }
2087 
2088         if (INTEL_INFO(dev)->gen >= 4) {
2089                 if (obj->tiling_mode != I915_TILING_NONE)
2090                         dspcntr |= DISPPLANE_TILED;
2091                 else
2092                         dspcntr &= ~DISPPLANE_TILED;
2093         }
2094 
2095         if (IS_G4X(dev))
2096                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097 
2098         I915_WRITE(reg, dspcntr);
2099 
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101 
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2105                                                        fb->bits_per_pixel / 8,
2106                                                        fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111 
2112         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2114                       fb->pitches[0]);
2115         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2116         if (INTEL_INFO(dev)->gen >= 4) {
2117                 I915_WRITE(DSPSURF(plane),
2118                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2119                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2120                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2121         } else
2122                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2123         POSTING_READ(reg);
2124 
2125         return 0;
2126 }
2127 
2128 static int ironlake_update_plane(struct drm_crtc *crtc,
2129                                  struct drm_framebuffer *fb, int x, int y)
2130 {
2131         struct drm_device *dev = crtc->dev;
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134         struct intel_framebuffer *intel_fb;
2135         struct drm_i915_gem_object *obj;
2136         int plane = intel_crtc->plane;
2137         unsigned long linear_offset;
2138         u32 dspcntr;
2139         u32 reg;
2140 
2141         switch (plane) {
2142         case 0:
2143         case 1:
2144         case 2:
2145                 break;
2146         default:
2147                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2148                 return -EINVAL;
2149         }
2150 
2151         intel_fb = to_intel_framebuffer(fb);
2152         obj = intel_fb->obj;
2153 
2154         reg = DSPCNTR(plane);
2155         dspcntr = I915_READ(reg);
2156         /* Mask out pixel format bits in case we change it */
2157         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2158         switch (fb->pixel_format) {
2159         case DRM_FORMAT_C8:
2160                 dspcntr |= DISPPLANE_8BPP;
2161                 break;
2162         case DRM_FORMAT_RGB565:
2163                 dspcntr |= DISPPLANE_BGRX565;
2164                 break;
2165         case DRM_FORMAT_XRGB8888:
2166         case DRM_FORMAT_ARGB8888:
2167                 dspcntr |= DISPPLANE_BGRX888;
2168                 break;
2169         case DRM_FORMAT_XBGR8888:
2170         case DRM_FORMAT_ABGR8888:
2171                 dspcntr |= DISPPLANE_RGBX888;
2172                 break;
2173         case DRM_FORMAT_XRGB2101010:
2174         case DRM_FORMAT_ARGB2101010:
2175                 dspcntr |= DISPPLANE_BGRX101010;
2176                 break;
2177         case DRM_FORMAT_XBGR2101010:
2178         case DRM_FORMAT_ABGR2101010:
2179                 dspcntr |= DISPPLANE_RGBX101010;
2180                 break;
2181         default:
2182                 BUG();
2183         }
2184 
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189 
2190         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2191                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2192         else
2193                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2194 
2195         I915_WRITE(reg, dspcntr);
2196 
2197         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2198         intel_crtc->dspaddr_offset =
2199                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2200                                                fb->bits_per_pixel / 8,
2201                                                fb->pitches[0]);
2202         linear_offset -= intel_crtc->dspaddr_offset;
2203 
2204         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2206                       fb->pitches[0]);
2207         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208         I915_WRITE(DSPSURF(plane),
2209                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2210         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2211                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212         } else {
2213                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215         }
2216         POSTING_READ(reg);
2217 
2218         return 0;
2219 }
2220 
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2222 static int
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224                            int x, int y, enum mode_set_atomic state)
2225 {
2226         struct drm_device *dev = crtc->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228 
2229         if (dev_priv->display.disable_fbc)
2230                 dev_priv->display.disable_fbc(dev);
2231         intel_increase_pllclock(crtc);
2232 
2233         return dev_priv->display.update_plane(crtc, fb, x, y);
2234 }
2235 
2236 void intel_display_handle_reset(struct drm_device *dev)
2237 {
2238         struct drm_i915_private *dev_priv = dev->dev_private;
2239         struct drm_crtc *crtc;
2240 
2241         /*
2242          * Flips in the rings have been nuked by the reset,
2243          * so complete all pending flips so that user space
2244          * will get its events and not get stuck.
2245          *
2246          * Also update the base address of all primary
2247          * planes to the the last fb to make sure we're
2248          * showing the correct fb after a reset.
2249          *
2250          * Need to make two loops over the crtcs so that we
2251          * don't try to grab a crtc mutex before the
2252          * pending_flip_queue really got woken up.
2253          */
2254 
2255         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2256                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257                 enum plane plane = intel_crtc->plane;
2258 
2259                 intel_prepare_page_flip(dev, plane);
2260                 intel_finish_page_flip_plane(dev, plane);
2261         }
2262 
2263         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2264                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265 
2266                 mutex_lock(&crtc->mutex);
2267                 /*
2268                  * FIXME: Once we have proper support for primary planes (and
2269                  * disabling them without disabling the entire crtc) allow again
2270                  * a NULL crtc->fb.
2271                  */
2272                 if (intel_crtc->active && crtc->fb)
2273                         dev_priv->display.update_plane(crtc, crtc->fb,
2274                                                        crtc->x, crtc->y);
2275                 mutex_unlock(&crtc->mutex);
2276         }
2277 }
2278 
2279 static int
2280 intel_finish_fb(struct drm_framebuffer *old_fb)
2281 {
2282         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2283         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284         bool was_interruptible = dev_priv->mm.interruptible;
2285         int ret;
2286 
2287         /* Big Hammer, we also need to ensure that any pending
2288          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289          * current scanout is retired before unpinning the old
2290          * framebuffer.
2291          *
2292          * This should only fail upon a hung GPU, in which case we
2293          * can safely continue.
2294          */
2295         dev_priv->mm.interruptible = false;
2296         ret = i915_gem_object_finish_gpu(obj);
2297         dev_priv->mm.interruptible = was_interruptible;
2298 
2299         return ret;
2300 }
2301 
2302 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2303 {
2304         struct drm_device *dev = crtc->dev;
2305         struct drm_i915_master_private *master_priv;
2306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307 
2308         if (!dev->primary->master)
2309                 return;
2310 
2311         master_priv = dev->primary->master->driver_priv;
2312         if (!master_priv->sarea_priv)
2313                 return;
2314 
2315         switch (intel_crtc->pipe) {
2316         case 0:
2317                 master_priv->sarea_priv->pipeA_x = x;
2318                 master_priv->sarea_priv->pipeA_y = y;
2319                 break;
2320         case 1:
2321                 master_priv->sarea_priv->pipeB_x = x;
2322                 master_priv->sarea_priv->pipeB_y = y;
2323                 break;
2324         default:
2325                 break;
2326         }
2327 }
2328 
2329 static int
2330 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2331                     struct drm_framebuffer *fb)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         struct drm_framebuffer *old_fb;
2337         int ret;
2338 
2339         /* no fb bound */
2340         if (!fb) {
2341                 DRM_ERROR("No FB bound\n");
2342                 return 0;
2343         }
2344 
2345         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2346                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347                           plane_name(intel_crtc->plane),
2348                           INTEL_INFO(dev)->num_pipes);
2349                 return -EINVAL;
2350         }
2351 
2352         mutex_lock(&dev->struct_mutex);
2353         ret = intel_pin_and_fence_fb_obj(dev,
2354                                          to_intel_framebuffer(fb)->obj,
2355                                          NULL);
2356         if (ret != 0) {
2357                 mutex_unlock(&dev->struct_mutex);
2358                 DRM_ERROR("pin & fence failed\n");
2359                 return ret;
2360         }
2361 
2362         /*
2363          * Update pipe size and adjust fitter if needed: the reason for this is
2364          * that in compute_mode_changes we check the native mode (not the pfit
2365          * mode) to see if we can flip rather than do a full mode set. In the
2366          * fastboot case, we'll flip, but if we don't update the pipesrc and
2367          * pfit state, we'll end up with a big fb scanned out into the wrong
2368          * sized surface.
2369          *
2370          * To fix this properly, we need to hoist the checks up into
2371          * compute_mode_changes (or above), check the actual pfit state and
2372          * whether the platform allows pfit disable with pipe active, and only
2373          * then update the pipesrc and pfit state, even on the flip path.
2374          */
2375         if (i915_fastboot) {
2376                 const struct drm_display_mode *adjusted_mode =
2377                         &intel_crtc->config.adjusted_mode;
2378 
2379                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2380                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2381                            (adjusted_mode->crtc_vdisplay - 1));
2382                 if (!intel_crtc->config.pch_pfit.enabled &&
2383                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2384                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2385                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2386                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2387                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2388                 }
2389                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2390                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2391         }
2392 
2393         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2394         if (ret) {
2395                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2396                 mutex_unlock(&dev->struct_mutex);
2397                 DRM_ERROR("failed to update base address\n");
2398                 return ret;
2399         }
2400 
2401         old_fb = crtc->fb;
2402         crtc->fb = fb;
2403         crtc->x = x;
2404         crtc->y = y;
2405 
2406         if (old_fb) {
2407                 if (intel_crtc->active && old_fb != fb)
2408                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2409                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2410         }
2411 
2412         intel_update_fbc(dev);
2413         intel_edp_psr_update(dev);
2414         mutex_unlock(&dev->struct_mutex);
2415 
2416         intel_crtc_update_sarea_pos(crtc, x, y);
2417 
2418         return 0;
2419 }
2420 
2421 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         u32 reg, temp;
2428 
2429         /* enable normal train */
2430         reg = FDI_TX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         if (IS_IVYBRIDGE(dev)) {
2433                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2434                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2435         } else {
2436                 temp &= ~FDI_LINK_TRAIN_NONE;
2437                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2438         }
2439         I915_WRITE(reg, temp);
2440 
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         if (HAS_PCH_CPT(dev)) {
2444                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2446         } else {
2447                 temp &= ~FDI_LINK_TRAIN_NONE;
2448                 temp |= FDI_LINK_TRAIN_NONE;
2449         }
2450         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2451 
2452         /* wait one idle pattern time */
2453         POSTING_READ(reg);
2454         udelay(1000);
2455 
2456         /* IVB wants error correction enabled */
2457         if (IS_IVYBRIDGE(dev))
2458                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2459                            FDI_FE_ERRC_ENABLE);
2460 }
2461 
2462 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2463 {
2464         return crtc->base.enabled && crtc->active &&
2465                 crtc->config.has_pch_encoder;
2466 }
2467 
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *pipe_B_crtc =
2472                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473         struct intel_crtc *pipe_C_crtc =
2474                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475         uint32_t temp;
2476 
2477         /*
2478          * When everything is off disable fdi C so that we could enable fdi B
2479          * with all lanes. Note that we don't care about enabled pipes without
2480          * an enabled pch encoder.
2481          */
2482         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2483             !pipe_has_enabled_pch(pipe_C_crtc)) {
2484                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2485                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2486 
2487                 temp = I915_READ(SOUTH_CHICKEN1);
2488                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2489                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490                 I915_WRITE(SOUTH_CHICKEN1, temp);
2491         }
2492 }
2493 
2494 /* The FDI link training functions for ILK/Ibexpeak. */
2495 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2496 {
2497         struct drm_device *dev = crtc->dev;
2498         struct drm_i915_private *dev_priv = dev->dev_private;
2499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500         int pipe = intel_crtc->pipe;
2501         int plane = intel_crtc->plane;
2502         u32 reg, temp, tries;
2503 
2504         /* FDI needs bits from pipe & plane first */
2505         assert_pipe_enabled(dev_priv, pipe);
2506         assert_plane_enabled(dev_priv, plane);
2507 
2508         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509            for train result */
2510         reg = FDI_RX_IMR(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_RX_SYMBOL_LOCK;
2513         temp &= ~FDI_RX_BIT_LOCK;
2514         I915_WRITE(reg, temp);
2515         I915_READ(reg);
2516         udelay(150);
2517 
2518         /* enable CPU FDI TX and PCH FDI RX */
2519         reg = FDI_TX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2522         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_1;
2525         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2526 
2527         reg = FDI_RX_CTL(pipe);
2528         temp = I915_READ(reg);
2529         temp &= ~FDI_LINK_TRAIN_NONE;
2530         temp |= FDI_LINK_TRAIN_PATTERN_1;
2531         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2532 
2533         POSTING_READ(reg);
2534         udelay(150);
2535 
2536         /* Ironlake workaround, enable clock pointer after FDI enable*/
2537         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2538         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2539                    FDI_RX_PHASE_SYNC_POINTER_EN);
2540 
2541         reg = FDI_RX_IIR(pipe);
2542         for (tries = 0; tries < 5; tries++) {
2543                 temp = I915_READ(reg);
2544                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545 
2546                 if ((temp & FDI_RX_BIT_LOCK)) {
2547                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2548                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549                         break;
2550                 }
2551         }
2552         if (tries == 5)
2553                 DRM_ERROR("FDI train 1 fail!\n");
2554 
2555         /* Train 2 */
2556         reg = FDI_TX_CTL(pipe);
2557         temp = I915_READ(reg);
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_2;
2560         I915_WRITE(reg, temp);
2561 
2562         reg = FDI_RX_CTL(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_LINK_TRAIN_NONE;
2565         temp |= FDI_LINK_TRAIN_PATTERN_2;
2566         I915_WRITE(reg, temp);
2567 
2568         POSTING_READ(reg);
2569         udelay(150);
2570 
2571         reg = FDI_RX_IIR(pipe);
2572         for (tries = 0; tries < 5; tries++) {
2573                 temp = I915_READ(reg);
2574                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575 
2576                 if (temp & FDI_RX_SYMBOL_LOCK) {
2577                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2578                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2579                         break;
2580                 }
2581         }
2582         if (tries == 5)
2583                 DRM_ERROR("FDI train 2 fail!\n");
2584 
2585         DRM_DEBUG_KMS("FDI train done\n");
2586 
2587 }
2588 
2589 static const int snb_b_fdi_train_param[] = {
2590         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2591         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2592         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2593         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2594 };
2595 
2596 /* The FDI link training functions for SNB/Cougarpoint. */
2597 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2598 {
2599         struct drm_device *dev = crtc->dev;
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602         int pipe = intel_crtc->pipe;
2603         u32 reg, temp, i, retry;
2604 
2605         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606            for train result */
2607         reg = FDI_RX_IMR(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_RX_SYMBOL_LOCK;
2610         temp &= ~FDI_RX_BIT_LOCK;
2611         I915_WRITE(reg, temp);
2612 
2613         POSTING_READ(reg);
2614         udelay(150);
2615 
2616         /* enable CPU FDI TX and PCH FDI RX */
2617         reg = FDI_TX_CTL(pipe);
2618         temp = I915_READ(reg);
2619         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2620         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2621         temp &= ~FDI_LINK_TRAIN_NONE;
2622         temp |= FDI_LINK_TRAIN_PATTERN_1;
2623         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624         /* SNB-B */
2625         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2626         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627 
2628         I915_WRITE(FDI_RX_MISC(pipe),
2629                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2630 
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         if (HAS_PCH_CPT(dev)) {
2634                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636         } else {
2637                 temp &= ~FDI_LINK_TRAIN_NONE;
2638                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2639         }
2640         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641 
2642         POSTING_READ(reg);
2643         udelay(150);
2644 
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651 
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654 
2655                 for (retry = 0; retry < 5; retry++) {
2656                         reg = FDI_RX_IIR(pipe);
2657                         temp = I915_READ(reg);
2658                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659                         if (temp & FDI_RX_BIT_LOCK) {
2660                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662                                 break;
2663                         }
2664                         udelay(50);
2665                 }
2666                 if (retry < 5)
2667                         break;
2668         }
2669         if (i == 4)
2670                 DRM_ERROR("FDI train 1 fail!\n");
2671 
2672         /* Train 2 */
2673         reg = FDI_TX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_NONE;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2;
2677         if (IS_GEN6(dev)) {
2678                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679                 /* SNB-B */
2680                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681         }
2682         I915_WRITE(reg, temp);
2683 
2684         reg = FDI_RX_CTL(pipe);
2685         temp = I915_READ(reg);
2686         if (HAS_PCH_CPT(dev)) {
2687                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2689         } else {
2690                 temp &= ~FDI_LINK_TRAIN_NONE;
2691                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2692         }
2693         I915_WRITE(reg, temp);
2694 
2695         POSTING_READ(reg);
2696         udelay(150);
2697 
2698         for (i = 0; i < 4; i++) {
2699                 reg = FDI_TX_CTL(pipe);
2700                 temp = I915_READ(reg);
2701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702                 temp |= snb_b_fdi_train_param[i];
2703                 I915_WRITE(reg, temp);
2704 
2705                 POSTING_READ(reg);
2706                 udelay(500);
2707 
2708                 for (retry = 0; retry < 5; retry++) {
2709                         reg = FDI_RX_IIR(pipe);
2710                         temp = I915_READ(reg);
2711                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2712                         if (temp & FDI_RX_SYMBOL_LOCK) {
2713                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2714                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2715                                 break;
2716                         }
2717                         udelay(50);
2718                 }
2719                 if (retry < 5)
2720                         break;
2721         }
2722         if (i == 4)
2723                 DRM_ERROR("FDI train 2 fail!\n");
2724 
2725         DRM_DEBUG_KMS("FDI train done.\n");
2726 }
2727 
2728 /* Manual link training for Ivy Bridge A0 parts */
2729 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2730 {
2731         struct drm_device *dev = crtc->dev;
2732         struct drm_i915_private *dev_priv = dev->dev_private;
2733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2734         int pipe = intel_crtc->pipe;
2735         u32 reg, temp, i, j;
2736 
2737         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2738            for train result */
2739         reg = FDI_RX_IMR(pipe);
2740         temp = I915_READ(reg);
2741         temp &= ~FDI_RX_SYMBOL_LOCK;
2742         temp &= ~FDI_RX_BIT_LOCK;
2743         I915_WRITE(reg, temp);
2744 
2745         POSTING_READ(reg);
2746         udelay(150);
2747 
2748         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749                       I915_READ(FDI_RX_IIR(pipe)));
2750 
2751         /* Try each vswing and preemphasis setting twice before moving on */
2752         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2753                 /* disable first in case we need to retry */
2754                 reg = FDI_TX_CTL(pipe);
2755                 temp = I915_READ(reg);
2756                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2757                 temp &= ~FDI_TX_ENABLE;
2758                 I915_WRITE(reg, temp);
2759 
2760                 reg = FDI_RX_CTL(pipe);
2761                 temp = I915_READ(reg);
2762                 temp &= ~FDI_LINK_TRAIN_AUTO;
2763                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764                 temp &= ~FDI_RX_ENABLE;
2765                 I915_WRITE(reg, temp);
2766 
2767                 /* enable CPU FDI TX and PCH FDI RX */
2768                 reg = FDI_TX_CTL(pipe);
2769                 temp = I915_READ(reg);
2770                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2771                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2772                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2773                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2774                 temp |= snb_b_fdi_train_param[j/2];
2775                 temp |= FDI_COMPOSITE_SYNC;
2776                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2777 
2778                 I915_WRITE(FDI_RX_MISC(pipe),
2779                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2780 
2781                 reg = FDI_RX_CTL(pipe);
2782                 temp = I915_READ(reg);
2783                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2784                 temp |= FDI_COMPOSITE_SYNC;
2785                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2786 
2787                 POSTING_READ(reg);
2788                 udelay(1); /* should be 0.5us */
2789 
2790                 for (i = 0; i < 4; i++) {
2791                         reg = FDI_RX_IIR(pipe);
2792                         temp = I915_READ(reg);
2793                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794 
2795                         if (temp & FDI_RX_BIT_LOCK ||
2796                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2798                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2799                                               i);
2800                                 break;
2801                         }
2802                         udelay(1); /* should be 0.5us */
2803                 }
2804                 if (i == 4) {
2805                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2806                         continue;
2807                 }
2808 
2809                 /* Train 2 */
2810                 reg = FDI_TX_CTL(pipe);
2811                 temp = I915_READ(reg);
2812                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2813                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2814                 I915_WRITE(reg, temp);
2815 
2816                 reg = FDI_RX_CTL(pipe);
2817                 temp = I915_READ(reg);
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820                 I915_WRITE(reg, temp);
2821 
2822                 POSTING_READ(reg);
2823                 udelay(2); /* should be 1.5us */
2824 
2825                 for (i = 0; i < 4; i++) {
2826                         reg = FDI_RX_IIR(pipe);
2827                         temp = I915_READ(reg);
2828                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829 
2830                         if (temp & FDI_RX_SYMBOL_LOCK ||
2831                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2832                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2833                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2834                                               i);
2835                                 goto train_done;
2836                         }
2837                         udelay(2); /* should be 1.5us */
2838                 }
2839                 if (i == 4)
2840                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2841         }
2842 
2843 train_done:
2844         DRM_DEBUG_KMS("FDI train done.\n");
2845 }
2846 
2847 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2848 {
2849         struct drm_device *dev = intel_crtc->base.dev;
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         int pipe = intel_crtc->pipe;
2852         u32 reg, temp;
2853 
2854 
2855         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2859         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2860         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2862 
2863         POSTING_READ(reg);
2864         udelay(200);
2865 
2866         /* Switch from Rawclk to PCDclk */
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp | FDI_PCDCLK);
2869 
2870         POSTING_READ(reg);
2871         udelay(200);
2872 
2873         /* Enable CPU FDI TX PLL, always on for Ironlake */
2874         reg = FDI_TX_CTL(pipe);
2875         temp = I915_READ(reg);
2876         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2877                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2878 
2879                 POSTING_READ(reg);
2880                 udelay(100);
2881         }
2882 }
2883 
2884 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2885 {
2886         struct drm_device *dev = intel_crtc->base.dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         int pipe = intel_crtc->pipe;
2889         u32 reg, temp;
2890 
2891         /* Switch from PCDclk to Rawclk */
2892         reg = FDI_RX_CTL(pipe);
2893         temp = I915_READ(reg);
2894         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2895 
2896         /* Disable CPU FDI TX PLL */
2897         reg = FDI_TX_CTL(pipe);
2898         temp = I915_READ(reg);
2899         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2900 
2901         POSTING_READ(reg);
2902         udelay(100);
2903 
2904         reg = FDI_RX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2907 
2908         /* Wait for the clocks to turn off. */
2909         POSTING_READ(reg);
2910         udelay(100);
2911 }
2912 
2913 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2914 {
2915         struct drm_device *dev = crtc->dev;
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918         int pipe = intel_crtc->pipe;
2919         u32 reg, temp;
2920 
2921         /* disable CPU FDI tx and PCH FDI rx */
2922         reg = FDI_TX_CTL(pipe);
2923         temp = I915_READ(reg);
2924         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2925         POSTING_READ(reg);
2926 
2927         reg = FDI_RX_CTL(pipe);
2928         temp = I915_READ(reg);
2929         temp &= ~(0x7 << 16);
2930         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2931         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2932 
2933         POSTING_READ(reg);
2934         udelay(100);
2935 
2936         /* Ironlake workaround, disable clock pointer after downing FDI */
2937         if (HAS_PCH_IBX(dev)) {
2938                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2939         }
2940 
2941         /* still set train pattern 1 */
2942         reg = FDI_TX_CTL(pipe);
2943         temp = I915_READ(reg);
2944         temp &= ~FDI_LINK_TRAIN_NONE;
2945         temp |= FDI_LINK_TRAIN_PATTERN_1;
2946         I915_WRITE(reg, temp);
2947 
2948         reg = FDI_RX_CTL(pipe);
2949         temp = I915_READ(reg);
2950         if (HAS_PCH_CPT(dev)) {
2951                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2952                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2953         } else {
2954                 temp &= ~FDI_LINK_TRAIN_NONE;
2955                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2956         }
2957         /* BPC in FDI rx is consistent with that in PIPECONF */
2958         temp &= ~(0x07 << 16);
2959         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2960         I915_WRITE(reg, temp);
2961 
2962         POSTING_READ(reg);
2963         udelay(100);
2964 }
2965 
2966 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971         unsigned long flags;
2972         bool pending;
2973 
2974         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2975             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2976                 return false;
2977 
2978         spin_lock_irqsave(&dev->event_lock, flags);
2979         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2980         spin_unlock_irqrestore(&dev->event_lock, flags);
2981 
2982         return pending;
2983 }
2984 
2985 bool intel_has_pending_fb_unpin(struct drm_device *dev)
2986 {
2987         struct intel_crtc *crtc;
2988 
2989         /* Note that we don't need to be called with mode_config.lock here
2990          * as our list of CRTC objects is static for the lifetime of the
2991          * device and so cannot disappear as we iterate. Similarly, we can
2992          * happily treat the predicates as racy, atomic checks as userspace
2993          * cannot claim and pin a new fb without at least acquring the
2994          * struct_mutex and so serialising with us.
2995          */
2996         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2997                 if (atomic_read(&crtc->unpin_work_count) == 0)
2998                         continue;
2999 
3000                 if (crtc->unpin_work)
3001                         intel_wait_for_vblank(dev, crtc->pipe);
3002 
3003                 return true;
3004         }
3005 
3006         return false;
3007 }
3008 
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3010 {
3011         struct drm_device *dev = crtc->dev;
3012         struct drm_i915_private *dev_priv = dev->dev_private;
3013 
3014         if (crtc->fb == NULL)
3015                 return;
3016 
3017         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3018 
3019         wait_event(dev_priv->pending_flip_queue,
3020                    !intel_crtc_has_pending_flip(crtc));
3021 
3022         mutex_lock(&dev->struct_mutex);
3023         intel_finish_fb(crtc->fb);
3024         mutex_unlock(&dev->struct_mutex);
3025 }
3026 
3027 /* Program iCLKIP clock to the desired frequency */
3028 static void lpt_program_iclkip(struct drm_crtc *crtc)
3029 {
3030         struct drm_device *dev = crtc->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3033         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3034         u32 temp;
3035 
3036         mutex_lock(&dev_priv->dpio_lock);
3037 
3038         /* It is necessary to ungate the pixclk gate prior to programming
3039          * the divisors, and gate it back when it is done.
3040          */
3041         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3042 
3043         /* Disable SSCCTL */
3044         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3045                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3046                                 SBI_SSCCTL_DISABLE,
3047                         SBI_ICLK);
3048 
3049         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3050         if (clock == 20000) {
3051                 auxdiv = 1;
3052                 divsel = 0x41;
3053                 phaseinc = 0x20;
3054         } else {
3055                 /* The iCLK virtual clock root frequency is in MHz,
3056                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3057                  * divisors, it is necessary to divide one by another, so we
3058                  * convert the virtual clock precision to KHz here for higher
3059                  * precision.
3060                  */
3061                 u32 iclk_virtual_root_freq = 172800 * 1000;
3062                 u32 iclk_pi_range = 64;
3063                 u32 desired_divisor, msb_divisor_value, pi_value;
3064 
3065                 desired_divisor = (iclk_virtual_root_freq / clock);
3066                 msb_divisor_value = desired_divisor / iclk_pi_range;
3067                 pi_value = desired_divisor % iclk_pi_range;
3068 
3069                 auxdiv = 0;
3070                 divsel = msb_divisor_value - 2;
3071                 phaseinc = pi_value;
3072         }
3073 
3074         /* This should not happen with any sane values */
3075         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3076                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3077         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3078                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3079 
3080         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3081                         clock,
3082                         auxdiv,
3083                         divsel,
3084                         phasedir,
3085                         phaseinc);
3086 
3087         /* Program SSCDIVINTPHASE6 */
3088         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3089         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3090         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3091         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3092         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3093         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3094         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3095         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3096 
3097         /* Program SSCAUXDIV */
3098         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3099         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3100         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3101         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3102 
3103         /* Enable modulator and associated divider */
3104         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3105         temp &= ~SBI_SSCCTL_DISABLE;
3106         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3107 
3108         /* Wait for initialization time */
3109         udelay(24);
3110 
3111         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3112 
3113         mutex_unlock(&dev_priv->dpio_lock);
3114 }
3115 
3116 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3117                                                 enum pipe pch_transcoder)
3118 {
3119         struct drm_device *dev = crtc->base.dev;
3120         struct drm_i915_private *dev_priv = dev->dev_private;
3121         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3122 
3123         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3124                    I915_READ(HTOTAL(cpu_transcoder)));
3125         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3126                    I915_READ(HBLANK(cpu_transcoder)));
3127         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3128                    I915_READ(HSYNC(cpu_transcoder)));
3129 
3130         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3131                    I915_READ(VTOTAL(cpu_transcoder)));
3132         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3133                    I915_READ(VBLANK(cpu_transcoder)));
3134         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3135                    I915_READ(VSYNC(cpu_transcoder)));
3136         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3137                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3138 }
3139 
3140 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3141 {
3142         struct drm_i915_private *dev_priv = dev->dev_private;
3143         uint32_t temp;
3144 
3145         temp = I915_READ(SOUTH_CHICKEN1);
3146         if (temp & FDI_BC_BIFURCATION_SELECT)
3147                 return;
3148 
3149         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3150         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3151 
3152         temp |= FDI_BC_BIFURCATION_SELECT;
3153         DRM_DEBUG_KMS("enabling fdi C rx\n");
3154         I915_WRITE(SOUTH_CHICKEN1, temp);
3155         POSTING_READ(SOUTH_CHICKEN1);
3156 }
3157 
3158 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3159 {
3160         struct drm_device *dev = intel_crtc->base.dev;
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162 
3163         switch (intel_crtc->pipe) {
3164         case PIPE_A:
3165                 break;
3166         case PIPE_B:
3167                 if (intel_crtc->config.fdi_lanes > 2)
3168                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3169                 else
3170                         cpt_enable_fdi_bc_bifurcation(dev);
3171 
3172                 break;
3173         case PIPE_C:
3174                 cpt_enable_fdi_bc_bifurcation(dev);
3175 
3176                 break;
3177         default:
3178                 BUG();
3179         }
3180 }
3181 
3182 /*
3183  * Enable PCH resources required for PCH ports:
3184  *   - PCH PLLs
3185  *   - FDI training & RX/TX
3186  *   - update transcoder timings
3187  *   - DP transcoding bits
3188  *   - transcoder
3189  */
3190 static void ironlake_pch_enable(struct drm_crtc *crtc)
3191 {
3192         struct drm_device *dev = crtc->dev;
3193         struct drm_i915_private *dev_priv = dev->dev_private;
3194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3195         int pipe = intel_crtc->pipe;
3196         u32 reg, temp;
3197 
3198         assert_pch_transcoder_disabled(dev_priv, pipe);
3199 
3200         if (IS_IVYBRIDGE(dev))
3201                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3202 
3203         /* Write the TU size bits before fdi link training, so that error
3204          * detection works. */
3205         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3206                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3207 
3208         /* For PCH output, training FDI link */
3209         dev_priv->display.fdi_link_train(crtc);
3210 
3211         /* We need to program the right clock selection before writing the pixel
3212          * mutliplier into the DPLL. */
3213         if (HAS_PCH_CPT(dev)) {
3214                 u32 sel;
3215 
3216                 temp = I915_READ(PCH_DPLL_SEL);
3217                 temp |= TRANS_DPLL_ENABLE(pipe);
3218                 sel = TRANS_DPLLB_SEL(pipe);
3219                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3220                         temp |= sel;
3221                 else
3222                         temp &= ~sel;
3223                 I915_WRITE(PCH_DPLL_SEL, temp);
3224         }
3225 
3226         /* XXX: pch pll's can be enabled any time before we enable the PCH
3227          * transcoder, and we actually should do this to not upset any PCH
3228          * transcoder that already use the clock when we share it.
3229          *
3230          * Note that enable_shared_dpll tries to do the right thing, but
3231          * get_shared_dpll unconditionally resets the pll - we need that to have
3232          * the right LVDS enable sequence. */
3233         ironlake_enable_shared_dpll(intel_crtc);
3234 
3235         /* set transcoder timing, panel must allow it */
3236         assert_panel_unlocked(dev_priv, pipe);
3237         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3238 
3239         intel_fdi_normal_train(crtc);
3240 
3241         /* For PCH DP, enable TRANS_DP_CTL */
3242         if (HAS_PCH_CPT(dev) &&
3243             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3244              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3245                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3246                 reg = TRANS_DP_CTL(pipe);
3247                 temp = I915_READ(reg);
3248                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3249                           TRANS_DP_SYNC_MASK |
3250                           TRANS_DP_BPC_MASK);
3251                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3252                          TRANS_DP_ENH_FRAMING);
3253                 temp |= bpc << 9; /* same format but at 11:9 */
3254 
3255                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3256                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3257                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3258                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3259 
3260                 switch (intel_trans_dp_port_sel(crtc)) {
3261                 case PCH_DP_B:
3262                         temp |= TRANS_DP_PORT_SEL_B;
3263                         break;
3264                 case PCH_DP_C:
3265                         temp |= TRANS_DP_PORT_SEL_C;
3266                         break;
3267                 case PCH_DP_D:
3268                         temp |= TRANS_DP_PORT_SEL_D;
3269                         break;
3270                 default:
3271                         BUG();
3272                 }
3273 
3274                 I915_WRITE(reg, temp);
3275         }
3276 
3277         ironlake_enable_pch_transcoder(dev_priv, pipe);
3278 }
3279 
3280 static void lpt_pch_enable(struct drm_crtc *crtc)
3281 {
3282         struct drm_device *dev = crtc->dev;
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3286 
3287         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3288 
3289         lpt_program_iclkip(crtc);
3290 
3291         /* Set transcoder timing. */
3292         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3293 
3294         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3295 }
3296 
3297 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3298 {
3299         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3300 
3301         if (pll == NULL)
3302                 return;
3303 
3304         if (pll->refcount == 0) {
3305                 WARN(1, "bad %s refcount\n", pll->name);
3306                 return;
3307         }
3308 
3309         if (--pll->refcount == 0) {
3310                 WARN_ON(pll->on);
3311                 WARN_ON(pll->active);
3312         }
3313 
3314         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3315 }
3316 
3317 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3318 {
3319         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3320         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3321         enum intel_dpll_id i;
3322 
3323         if (pll) {
3324                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3325                               crtc->base.base.id, pll->name);
3326                 intel_put_shared_dpll(crtc);
3327         }
3328 
3329         if (HAS_PCH_IBX(dev_priv->dev)) {
3330                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3331                 i = (enum intel_dpll_id) crtc->pipe;
3332                 pll = &dev_priv->shared_dplls[i];
3333 
3334                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3335                               crtc->base.base.id, pll->name);
3336 
3337                 goto found;
3338         }
3339 
3340         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3341                 pll = &dev_priv->shared_dplls[i];
3342 
3343                 /* Only want to check enabled timings first */
3344                 if (pll->refcount == 0)
3345                         continue;
3346 
3347                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3348                            sizeof(pll->hw_state)) == 0) {
3349                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3350                                       crtc->base.base.id,
3351                                       pll->name, pll->refcount, pll->active);
3352 
3353                         goto found;
3354                 }
3355         }
3356 
3357         /* Ok no matching timings, maybe there's a free one? */
3358         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3359                 pll = &dev_priv->shared_dplls[i];
3360                 if (pll->refcount == 0) {
3361                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3362                                       crtc->base.base.id, pll->name);
3363                         goto found;
3364                 }
3365         }
3366 
3367         return NULL;
3368 
3369 found:
3370         crtc->config.shared_dpll = i;
3371         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3372                          pipe_name(crtc->pipe));
3373 
3374         if (pll->active == 0) {
3375                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3376                        sizeof(pll->hw_state));
3377 
3378                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3379                 WARN_ON(pll->on);
3380                 assert_shared_dpll_disabled(dev_priv, pll);
3381 
3382                 pll->mode_set(dev_priv, pll);
3383         }
3384         pll->refcount++;
3385 
3386         return pll;
3387 }
3388 
3389 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3390 {
3391         struct drm_i915_private *dev_priv = dev->dev_private;
3392         int dslreg = PIPEDSL(pipe);
3393         u32 temp;
3394 
3395         temp = I915_READ(dslreg);
3396         udelay(500);
3397         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3398                 if (wait_for(I915_READ(dslreg) != temp, 5))
3399                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3400         }
3401 }
3402 
3403 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3404 {
3405         struct drm_device *dev = crtc->base.dev;
3406         struct drm_i915_private *dev_priv = dev->dev_private;
3407         int pipe = crtc->pipe;
3408 
3409         if (crtc->config.pch_pfit.enabled) {
3410                 /* Force use of hard-coded filter coefficients
3411                  * as some pre-programmed values are broken,
3412                  * e.g. x201.
3413                  */
3414                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3415                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3416                                                  PF_PIPE_SEL_IVB(pipe));
3417                 else
3418                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3419                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3420                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3421         }
3422 }
3423 
3424 static void intel_enable_planes(struct drm_crtc *crtc)
3425 {
3426         struct drm_device *dev = crtc->dev;
3427         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3428         struct intel_plane *intel_plane;
3429 
3430         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3431                 if (intel_plane->pipe == pipe)
3432                         intel_plane_restore(&intel_plane->base);
3433 }
3434 
3435 static void intel_disable_planes(struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3439         struct intel_plane *intel_plane;
3440 
3441         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3442                 if (intel_plane->pipe == pipe)
3443                         intel_plane_disable(&intel_plane->base);
3444 }
3445 
3446 void hsw_enable_ips(struct intel_crtc *crtc)
3447 {
3448         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3449 
3450         if (!crtc->config.ips_enabled)
3451                 return;
3452 
3453         /* We can only enable IPS after we enable a plane and wait for a vblank.
3454          * We guarantee that the plane is enabled by calling intel_enable_ips
3455          * only after intel_enable_plane. And intel_enable_plane already waits
3456          * for a vblank, so all we need to do here is to enable the IPS bit. */
3457         assert_plane_enabled(dev_priv, crtc->plane);
3458         if (IS_BROADWELL(crtc->base.dev)) {
3459                 mutex_lock(&dev_priv->rps.hw_lock);
3460                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3461                 mutex_unlock(&dev_priv->rps.hw_lock);
3462                 /* Quoting Art Runyan: "its not safe to expect any particular
3463                  * value in IPS_CTL bit 31 after enabling IPS through the
3464                  * mailbox." Moreover, the mailbox may return a bogus state,
3465                  * so we need to just enable it and continue on.
3466                  */
3467         } else {
3468                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3469                 /* The bit only becomes 1 in the next vblank, so this wait here
3470                  * is essentially intel_wait_for_vblank. If we don't have this
3471                  * and don't wait for vblanks until the end of crtc_enable, then
3472                  * the HW state readout code will complain that the expected
3473                  * IPS_CTL value is not the one we read. */
3474                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3475                         DRM_ERROR("Timed out waiting for IPS enable\n");
3476         }
3477 }
3478 
3479 void hsw_disable_ips(struct intel_crtc *crtc)
3480 {
3481         struct drm_device *dev = crtc->base.dev;
3482         struct drm_i915_private *dev_priv = dev->dev_private;
3483 
3484         if (!crtc->config.ips_enabled)
3485                 return;
3486 
3487         assert_plane_enabled(dev_priv, crtc->plane);
3488         if (IS_BROADWELL(crtc->base.dev)) {
3489                 mutex_lock(&dev_priv->rps.hw_lock);
3490                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3491                 mutex_unlock(&dev_priv->rps.hw_lock);
3492         } else {
3493                 I915_WRITE(IPS_CTL, 0);
3494                 POSTING_READ(IPS_CTL);
3495         }
3496 
3497         /* We need to wait for a vblank before we can disable the plane. */
3498         intel_wait_for_vblank(dev, crtc->pipe);
3499 }
3500 
3501 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3502 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         enum pipe pipe = intel_crtc->pipe;
3508         int palreg = PALETTE(pipe);
3509         int i;
3510         bool reenable_ips = false;
3511 
3512         /* The clocks have to be on to load the palette. */
3513         if (!crtc->enabled || !intel_crtc->active)
3514                 return;
3515 
3516         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3517                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3518                         assert_dsi_pll_enabled(dev_priv);
3519                 else
3520                         assert_pll_enabled(dev_priv, pipe);
3521         }
3522 
3523         /* use legacy palette for Ironlake */
3524         if (HAS_PCH_SPLIT(dev))
3525                 palreg = LGC_PALETTE(pipe);
3526 
3527         /* Workaround : Do not read or write the pipe palette/gamma data while
3528          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3529          */
3530         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3531             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3532              GAMMA_MODE_MODE_SPLIT)) {
3533                 hsw_disable_ips(intel_crtc);
3534                 reenable_ips = true;
3535         }
3536 
3537         for (i = 0; i < 256; i++) {
3538                 I915_WRITE(palreg + 4 * i,
3539                            (intel_crtc->lut_r[i] << 16) |
3540                            (intel_crtc->lut_g[i] << 8) |
3541                            intel_crtc->lut_b[i]);
3542         }
3543 
3544         if (reenable_ips)
3545                 hsw_enable_ips(intel_crtc);
3546 }
3547 
3548 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         struct intel_encoder *encoder;
3554         int pipe = intel_crtc->pipe;
3555         int plane = intel_crtc->plane;
3556 
3557         WARN_ON(!crtc->enabled);
3558 
3559         if (intel_crtc->active)
3560                 return;
3561 
3562         intel_crtc->active = true;
3563 
3564         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3565         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3566 
3567         for_each_encoder_on_crtc(dev, crtc, encoder)
3568                 if (encoder->pre_enable)
3569                         encoder->pre_enable(encoder);
3570 
3571         if (intel_crtc->config.has_pch_encoder) {
3572                 /* Note: FDI PLL enabling _must_ be done before we enable the
3573                  * cpu pipes, hence this is separate from all the other fdi/pch
3574                  * enabling. */
3575                 ironlake_fdi_pll_enable(intel_crtc);
3576         } else {
3577                 assert_fdi_tx_disabled(dev_priv, pipe);
3578                 assert_fdi_rx_disabled(dev_priv, pipe);
3579         }
3580 
3581         ironlake_pfit_enable(intel_crtc);
3582 
3583         /*
3584          * On ILK+ LUT must be loaded before the pipe is running but with
3585          * clocks enabled
3586          */
3587         intel_crtc_load_lut(crtc);
3588 
3589         intel_update_watermarks(crtc);
3590         intel_enable_pipe(dev_priv, pipe,
3591                           intel_crtc->config.has_pch_encoder, false);
3592         intel_enable_primary_plane(dev_priv, plane, pipe);
3593         intel_enable_planes(crtc);
3594         intel_crtc_update_cursor(crtc, true);
3595 
3596         if (intel_crtc->config.has_pch_encoder)
3597                 ironlake_pch_enable(crtc);
3598 
3599         mutex_lock(&dev->struct_mutex);
3600         intel_update_fbc(dev);
3601         mutex_unlock(&dev->struct_mutex);
3602 
3603         for_each_encoder_on_crtc(dev, crtc, encoder)
3604                 encoder->enable(encoder);
3605 
3606         if (HAS_PCH_CPT(dev))
3607                 cpt_verify_modeset(dev, intel_crtc->pipe);
3608 
3609         /*
3610          * There seems to be a race in PCH platform hw (at least on some
3611          * outputs) where an enabled pipe still completes any pageflip right
3612          * away (as if the pipe is off) instead of waiting for vblank. As soon
3613          * as the first vblank happend, everything works as expected. Hence just
3614          * wait for one vblank before returning to avoid strange things
3615          * happening.
3616          */
3617         intel_wait_for_vblank(dev, intel_crtc->pipe);
3618 }
3619 
3620 /* IPS only exists on ULT machines and is tied to pipe A. */
3621 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3622 {
3623         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3624 }
3625 
3626 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3627 {
3628         struct drm_device *dev = crtc->dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         int pipe = intel_crtc->pipe;
3632         int plane = intel_crtc->plane;
3633 
3634         intel_enable_primary_plane(dev_priv, plane, pipe);
3635         intel_enable_planes(crtc);
3636         intel_crtc_update_cursor(crtc, true);
3637 
3638         hsw_enable_ips(intel_crtc);
3639 
3640         mutex_lock(&dev->struct_mutex);
3641         intel_update_fbc(dev);
3642         mutex_unlock(&dev->struct_mutex);
3643 }
3644 
3645 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3646 {
3647         struct drm_device *dev = crtc->dev;
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650         int pipe = intel_crtc->pipe;
3651         int plane = intel_crtc->plane;
3652 
3653         intel_crtc_wait_for_pending_flips(crtc);
3654         drm_vblank_off(dev, pipe);
3655 
3656         /* FBC must be disabled before disabling the plane on HSW. */
3657         if (dev_priv->fbc.plane == plane)
3658                 intel_disable_fbc(dev);
3659 
3660         hsw_disable_ips(intel_crtc);
3661 
3662         intel_crtc_update_cursor(crtc, false);
3663         intel_disable_planes(crtc);
3664         intel_disable_primary_plane(dev_priv, plane, pipe);
3665 }
3666 
3667 /*
3668  * This implements the workaround described in the "notes" section of the mode
3669  * set sequence documentation. When going from no pipes or single pipe to
3670  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3671  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3672  */
3673 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3674 {
3675         struct drm_device *dev = crtc->base.dev;
3676         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3677 
3678         /* We want to get the other_active_crtc only if there's only 1 other
3679          * active crtc. */
3680         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3681                 if (!crtc_it->active || crtc_it == crtc)
3682                         continue;
3683 
3684                 if (other_active_crtc)
3685                         return;
3686 
3687                 other_active_crtc = crtc_it;
3688         }
3689         if (!other_active_crtc)
3690                 return;
3691 
3692         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3693         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3694 }
3695 
3696 static void haswell_crtc_enable(struct drm_crtc *crtc)
3697 {
3698         struct drm_device *dev = crtc->dev;
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701         struct intel_encoder *encoder;
3702         int pipe = intel_crtc->pipe;
3703 
3704         WARN_ON(!crtc->enabled);
3705 
3706         if (intel_crtc->active)
3707                 return;
3708 
3709         intel_crtc->active = true;
3710 
3711         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3712         if (intel_crtc->config.has_pch_encoder)
3713                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3714 
3715         if (intel_crtc->config.has_pch_encoder)
3716                 dev_priv->display.fdi_link_train(crtc);
3717 
3718         for_each_encoder_on_crtc(dev, crtc, encoder)
3719                 if (encoder->pre_enable)
3720                         encoder->pre_enable(encoder);
3721 
3722         intel_ddi_enable_pipe_clock(intel_crtc);
3723 
3724         ironlake_pfit_enable(intel_crtc);
3725 
3726         /*
3727          * On ILK+ LUT must be loaded before the pipe is running but with
3728          * clocks enabled
3729          */
3730         intel_crtc_load_lut(crtc);
3731 
3732         intel_ddi_set_pipe_settings(crtc);
3733         intel_ddi_enable_transcoder_func(crtc);
3734 
3735         intel_update_watermarks(crtc);
3736         intel_enable_pipe(dev_priv, pipe,
3737                           intel_crtc->config.has_pch_encoder, false);
3738 
3739         if (intel_crtc->config.has_pch_encoder)
3740                 lpt_pch_enable(crtc);
3741 
3742         for_each_encoder_on_crtc(dev, crtc, encoder) {
3743                 encoder->enable(encoder);
3744                 intel_opregion_notify_encoder(encoder, true);
3745         }
3746 
3747         /* If we change the relative order between pipe/planes enabling, we need
3748          * to change the workaround. */
3749         haswell_mode_set_planes_workaround(intel_crtc);
3750         haswell_crtc_enable_planes(crtc);
3751 
3752         /*
3753          * There seems to be a race in PCH platform hw (at least on some
3754          * outputs) where an enabled pipe still completes any pageflip right
3755          * away (as if the pipe is off) instead of waiting for vblank. As soon
3756          * as the first vblank happend, everything works as expected. Hence just
3757          * wait for one vblank before returning to avoid strange things
3758          * happening.
3759          */
3760         intel_wait_for_vblank(dev, intel_crtc->pipe);
3761 }
3762 
3763 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3764 {
3765         struct drm_device *dev = crtc->base.dev;
3766         struct drm_i915_private *dev_priv = dev->dev_private;
3767         int pipe = crtc->pipe;
3768 
3769         /* To avoid upsetting the power well on haswell only disable the pfit if
3770          * it's in use. The hw state code will make sure we get this right. */
3771         if (crtc->config.pch_pfit.enabled) {
3772                 I915_WRITE(PF_CTL(pipe), 0);
3773                 I915_WRITE(PF_WIN_POS(pipe), 0);
3774                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3775         }
3776 }
3777 
3778 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3779 {
3780         struct drm_device *dev = crtc->dev;
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783         struct intel_encoder *encoder;
3784         int pipe = intel_crtc->pipe;
3785         int plane = intel_crtc->plane;
3786         u32 reg, temp;
3787 
3788 
3789         if (!intel_crtc->active)
3790                 return;
3791 
3792         for_each_encoder_on_crtc(dev, crtc, encoder)
3793                 encoder->disable(encoder);
3794 
3795         intel_crtc_wait_for_pending_flips(crtc);
3796         drm_vblank_off(dev, pipe);
3797 
3798         if (dev_priv->fbc.plane == plane)
3799                 intel_disable_fbc(dev);
3800 
3801         intel_crtc_update_cursor(crtc, false);
3802         intel_disable_planes(crtc);
3803         intel_disable_primary_plane(dev_priv, plane, pipe);
3804 
3805         if (intel_crtc->config.has_pch_encoder)
3806                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3807 
3808         intel_disable_pipe(dev_priv, pipe);
3809 
3810         ironlake_pfit_disable(intel_crtc);
3811 
3812         for_each_encoder_on_crtc(dev, crtc, encoder)
3813                 if (encoder->post_disable)
3814                         encoder->post_disable(encoder);
3815 
3816         if (intel_crtc->config.has_pch_encoder) {
3817                 ironlake_fdi_disable(crtc);
3818 
3819                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3820                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3821 
3822                 if (HAS_PCH_CPT(dev)) {
3823                         /* disable TRANS_DP_CTL */
3824                         reg = TRANS_DP_CTL(pipe);
3825                         temp = I915_READ(reg);
3826                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3827                                   TRANS_DP_PORT_SEL_MASK);
3828                         temp |= TRANS_DP_PORT_SEL_NONE;
3829                         I915_WRITE(reg, temp);
3830 
3831                         /* disable DPLL_SEL */
3832                         temp = I915_READ(PCH_DPLL_SEL);
3833                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3834                         I915_WRITE(PCH_DPLL_SEL, temp);
3835                 }
3836 
3837                 /* disable PCH DPLL */
3838                 intel_disable_shared_dpll(intel_crtc);
3839 
3840                 ironlake_fdi_pll_disable(intel_crtc);
3841         }
3842 
3843         intel_crtc->active = false;
3844         intel_update_watermarks(crtc);
3845 
3846         mutex_lock(&dev->struct_mutex);
3847         intel_update_fbc(dev);
3848         mutex_unlock(&dev->struct_mutex);
3849 }
3850 
3851 static void haswell_crtc_disable(struct drm_crtc *crtc)
3852 {
3853         struct drm_device *dev = crtc->dev;
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856         struct intel_encoder *encoder;
3857         int pipe = intel_crtc->pipe;
3858         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3859 
3860         if (!intel_crtc->active)
3861                 return;
3862 
3863         haswell_crtc_disable_planes(crtc);
3864 
3865         for_each_encoder_on_crtc(dev, crtc, encoder) {
3866                 intel_opregion_notify_encoder(encoder, false);
3867                 encoder->disable(encoder);
3868         }
3869 
3870         if (intel_crtc->config.has_pch_encoder)
3871                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3872         intel_disable_pipe(dev_priv, pipe);
3873 
3874         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3875 
3876         ironlake_pfit_disable(intel_crtc);
3877 
3878         intel_ddi_disable_pipe_clock(intel_crtc);
3879 
3880         for_each_encoder_on_crtc(dev, crtc, encoder)
3881                 if (encoder->post_disable)
3882                         encoder->post_disable(encoder);
3883 
3884         if (intel_crtc->config.has_pch_encoder) {
3885                 lpt_disable_pch_transcoder(dev_priv);
3886                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3887                 intel_ddi_fdi_disable(crtc);
3888         }
3889 
3890         intel_crtc->active = false;
3891         intel_update_watermarks(crtc);
3892 
3893         mutex_lock(&dev->struct_mutex);
3894         intel_update_fbc(dev);
3895         mutex_unlock(&dev->struct_mutex);
3896 }
3897 
3898 static void ironlake_crtc_off(struct drm_crtc *crtc)
3899 {
3900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3901         intel_put_shared_dpll(intel_crtc);
3902 }
3903 
3904 static void haswell_crtc_off(struct drm_crtc *crtc)
3905 {
3906         intel_ddi_put_crtc_pll(crtc);
3907 }
3908 
3909 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3910 {
3911         if (!enable && intel_crtc->overlay) {
3912                 struct drm_device *dev = intel_crtc->base.dev;
3913                 struct drm_i915_private *dev_priv = dev->dev_private;
3914 
3915                 mutex_lock(&dev->struct_mutex);
3916                 dev_priv->mm.interruptible = false;
3917                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3918                 dev_priv->mm.interruptible = true;
3919                 mutex_unlock(&dev->struct_mutex);
3920         }
3921 
3922         /* Let userspace switch the overlay on again. In most cases userspace
3923          * has to recompute where to put it anyway.
3924          */
3925 }
3926 
3927 /**
3928  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3929  * cursor plane briefly if not already running after enabling the display
3930  * plane.
3931  * This workaround avoids occasional blank screens when self refresh is
3932  * enabled.
3933  */
3934 static void
3935 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3936 {
3937         u32 cntl = I915_READ(CURCNTR(pipe));
3938 
3939         if ((cntl & CURSOR_MODE) == 0) {
3940                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3941 
3942                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3943                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3944                 intel_wait_for_vblank(dev_priv->dev, pipe);
3945                 I915_WRITE(CURCNTR(pipe), cntl);
3946                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3947                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3948         }
3949 }
3950 
3951 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3952 {
3953         struct drm_device *dev = crtc->base.dev;
3954         struct drm_i915_private *dev_priv = dev->dev_private;
3955         struct intel_crtc_config *pipe_config = &crtc->config;
3956 
3957         if (!crtc->config.gmch_pfit.control)
3958                 return;
3959 
3960         /*
3961          * The panel fitter should only be adjusted whilst the pipe is disabled,
3962          * according to register description and PRM.
3963          */
3964         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3965         assert_pipe_disabled(dev_priv, crtc->pipe);
3966 
3967         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3968         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3969 
3970         /* Border color in case we don't scale up to the full screen. Black by
3971          * default, change to something else for debugging. */
3972         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3973 }
3974 
3975 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3976 {
3977         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3978 
3979         /* Obtain SKU information */
3980         mutex_lock(&dev_priv->dpio_lock);
3981         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3982                 CCK_FUSE_HPLL_FREQ_MASK;
3983         mutex_unlock(&dev_priv->dpio_lock);
3984 
3985         return vco_freq[hpll_freq];
3986 }
3987 
3988 /* Adjust CDclk dividers to allow high res or save power if possible */
3989 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3990 {
3991         struct drm_i915_private *dev_priv = dev->dev_private;
3992         u32 val, cmd;
3993 
3994         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3995                 cmd = 2;
3996         else if (cdclk == 266)
3997                 cmd = 1;
3998         else
3999                 cmd = 0;
4000 
4001         mutex_lock(&dev_priv->rps.hw_lock);
4002         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4003         val &= ~DSPFREQGUAR_MASK;
4004         val |= (cmd << DSPFREQGUAR_SHIFT);
4005         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4006         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4007                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4008                      50)) {
4009                 DRM_ERROR("timed out waiting for CDclk change\n");
4010         }
4011         mutex_unlock(&dev_priv->rps.hw_lock);
4012 
4013         if (cdclk == 400) {
4014                 u32 divider, vco;
4015 
4016                 vco = valleyview_get_vco(dev_priv);
4017                 divider = ((vco << 1) / cdclk) - 1;
4018 
4019                 mutex_lock(&dev_priv->dpio_lock);
4020                 /* adjust cdclk divider */
4021                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4022                 val &= ~0xf;
4023                 val |= divider;
4024                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4025                 mutex_unlock(&dev_priv->dpio_lock);
4026         }
4027 
4028         mutex_lock(&dev_priv->dpio_lock);
4029         /* adjust self-refresh exit latency value */
4030         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4031         val &= ~0x7f;
4032 
4033         /*
4034          * For high bandwidth configs, we set a higher latency in the bunit
4035          * so that the core display fetch happens in time to avoid underruns.
4036          */
4037         if (cdclk == 400)
4038                 val |= 4500 / 250; /* 4.5 usec */
4039         else
4040                 val |= 3000 / 250; /* 3.0 usec */
4041         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4042         mutex_unlock(&dev_priv->dpio_lock);
4043 
4044         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4045         intel_i2c_reset(dev);
4046 }
4047 
4048 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4049 {
4050         int cur_cdclk, vco;
4051         int divider;
4052 
4053         vco = valleyview_get_vco(dev_priv);
4054 
4055         mutex_lock(&dev_priv->dpio_lock);
4056         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4057         mutex_unlock(&dev_priv->dpio_lock);
4058 
4059         divider &= 0xf;
4060 
4061         cur_cdclk = (vco << 1) / (divider + 1);
4062 
4063         return cur_cdclk;
4064 }
4065 
4066 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4067                                  int max_pixclk)
4068 {
4069         int cur_cdclk;
4070 
4071         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4072 
4073         /*
4074          * Really only a few cases to deal with, as only 4 CDclks are supported:
4075          *   200MHz
4076          *   267MHz
4077          *   320MHz
4078          *   400MHz
4079          * So we check to see whether we're above 90% of the lower bin and
4080          * adjust if needed.
4081          */
4082         if (max_pixclk > 288000) {
4083                 return 400;
4084         } else if (max_pixclk > 240000) {
4085                 return 320;
4086         } else
4087                 return 266;
4088         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4089 }
4090 
4091 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4092                                  unsigned modeset_pipes,
4093                                  struct intel_crtc_config *pipe_config)
4094 {
4095         struct drm_device *dev = dev_priv->dev;
4096         struct intel_crtc *intel_crtc;
4097         int max_pixclk = 0;
4098 
4099         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4100                             base.head) {
4101                 if (modeset_pipes & (1 << intel_crtc->pipe))
4102                         max_pixclk = max(max_pixclk,
4103                                          pipe_config->adjusted_mode.crtc_clock);
4104                 else if (intel_crtc->base.enabled)
4105                         max_pixclk = max(max_pixclk,
4106                                          intel_crtc->config.adjusted_mode.crtc_clock);
4107         }
4108 
4109         return max_pixclk;
4110 }
4111 
4112 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4113                                             unsigned *prepare_pipes,
4114                                             unsigned modeset_pipes,
4115                                             struct intel_crtc_config *pipe_config)
4116 {
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc;
4119         int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4120                                                pipe_config);
4121         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4122 
4123         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4124                 return;
4125 
4126         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4127                             base.head)
4128                 if (intel_crtc->base.enabled)
4129                         *prepare_pipes |= (1 << intel_crtc->pipe);
4130 }
4131 
4132 static void valleyview_modeset_global_resources(struct drm_device *dev)
4133 {
4134         struct drm_i915_private *dev_priv = dev->dev_private;
4135         int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4136         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4137         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4138 
4139         if (req_cdclk != cur_cdclk)
4140                 valleyview_set_cdclk(dev, req_cdclk);
4141 }
4142 
4143 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148         struct intel_encoder *encoder;
4149         int pipe = intel_crtc->pipe;
4150         int plane = intel_crtc->plane;
4151         bool is_dsi;
4152 
4153         WARN_ON(!crtc->enabled);
4154 
4155         if (intel_crtc->active)
4156                 return;
4157 
4158         intel_crtc->active = true;
4159 
4160         for_each_encoder_on_crtc(dev, crtc, encoder)
4161                 if (encoder->pre_pll_enable)
4162                         encoder->pre_pll_enable(encoder);
4163 
4164         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4165 
4166         if (!is_dsi)
4167                 vlv_enable_pll(intel_crtc);
4168 
4169         for_each_encoder_on_crtc(dev, crtc, encoder)
4170                 if (encoder->pre_enable)
4171                         encoder->pre_enable(encoder);
4172 
4173         i9xx_pfit_enable(intel_crtc);
4174 
4175         intel_crtc_load_lut(crtc);
4176 
4177         intel_update_watermarks(crtc);
4178         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4179         intel_enable_primary_plane(dev_priv, plane, pipe);
4180         intel_enable_planes(crtc);
4181         intel_crtc_update_cursor(crtc, true);
4182 
4183         intel_update_fbc(dev);
4184 
4185         for_each_encoder_on_crtc(dev, crtc, encoder)
4186                 encoder->enable(encoder);
4187 }
4188 
4189 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4190 {
4191         struct drm_device *dev = crtc->dev;
4192         struct drm_i915_private *dev_priv = dev->dev_private;
4193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194         struct intel_encoder *encoder;
4195         int pipe = intel_crtc->pipe;
4196         int plane = intel_crtc->plane;
4197 
4198         WARN_ON(!crtc->enabled);
4199 
4200         if (intel_crtc->active)
4201                 return;
4202 
4203         intel_crtc->active = true;
4204 
4205         for_each_encoder_on_crtc(dev, crtc, encoder)
4206                 if (encoder->pre_enable)
4207                         encoder->pre_enable(encoder);
4208 
4209         i9xx_enable_pll(intel_crtc);
4210 
4211         i9xx_pfit_enable(intel_crtc);
4212 
4213         intel_crtc_load_lut(crtc);
4214 
4215         intel_update_watermarks(crtc);
4216         intel_enable_pipe(dev_priv, pipe, false, false);
4217         intel_enable_primary_plane(dev_priv, plane, pipe);
4218         intel_enable_planes(crtc);
4219         /* The fixup needs to happen before cursor is enabled */
4220         if (IS_G4X(dev))
4221                 g4x_fixup_plane(dev_priv, pipe);
4222         intel_crtc_update_cursor(crtc, true);
4223 
4224         /* Give the overlay scaler a chance to enable if it's on this pipe */
4225         intel_crtc_dpms_overlay(intel_crtc, true);
4226 
4227         intel_update_fbc(dev);
4228 
4229         for_each_encoder_on_crtc(dev, crtc, encoder)
4230                 encoder->enable(encoder);
4231 }
4232 
4233 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4234 {
4235         struct drm_device *dev = crtc->base.dev;
4236         struct drm_i915_private *dev_priv = dev->dev_private;
4237 
4238         if (!crtc->config.gmch_pfit.control)
4239                 return;
4240 
4241         assert_pipe_disabled(dev_priv, crtc->pipe);
4242 
4243         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4244                          I915_READ(PFIT_CONTROL));
4245         I915_WRITE(PFIT_CONTROL, 0);
4246 }
4247 
4248 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4249 {
4250         struct drm_device *dev = crtc->dev;
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253         struct intel_encoder *encoder;
4254         int pipe = intel_crtc->pipe;
4255         int plane = intel_crtc->plane;
4256 
4257         if (!intel_crtc->active)
4258                 return;
4259 
4260         for_each_encoder_on_crtc(dev, crtc, encoder)
4261                 encoder->disable(encoder);
4262 
4263         /* Give the overlay scaler a chance to disable if it's on this pipe */
4264         intel_crtc_wait_for_pending_flips(crtc);
4265         drm_vblank_off(dev, pipe);
4266 
4267         if (dev_priv->fbc.plane == plane)
4268                 intel_disable_fbc(dev);
4269 
4270         intel_crtc_dpms_overlay(intel_crtc, false);
4271         intel_crtc_update_cursor(crtc, false);
4272         intel_disable_planes(crtc);
4273         intel_disable_primary_plane(dev_priv, plane, pipe);
4274 
4275         intel_disable_pipe(dev_priv, pipe);
4276 
4277         i9xx_pfit_disable(intel_crtc);
4278 
4279         for_each_encoder_on_crtc(dev, crtc, encoder)
4280                 if (encoder->post_disable)
4281                         encoder->post_disable(encoder);
4282 
4283         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4284                 vlv_disable_pll(dev_priv, pipe);
4285         else if (!IS_VALLEYVIEW(dev))
4286                 i9xx_disable_pll(dev_priv, pipe);
4287 
4288         intel_crtc->active = false;
4289         intel_update_watermarks(crtc);
4290 
4291         intel_update_fbc(dev);
4292 }
4293 
4294 static void i9xx_crtc_off(struct drm_crtc *crtc)
4295 {
4296 }
4297 
4298 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4299                                     bool enabled)
4300 {
4301         struct drm_device *dev = crtc->dev;
4302         struct drm_i915_master_private *master_priv;
4303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4304         int pipe = intel_crtc->pipe;
4305 
4306         if (!dev->primary->master)
4307                 return;
4308 
4309         master_priv = dev->primary->master->driver_priv;
4310         if (!master_priv->sarea_priv)
4311                 return;
4312 
4313         switch (pipe) {
4314         case 0:
4315                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4316                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4317                 break;
4318         case 1:
4319                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4320                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4321                 break;
4322         default:
4323                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4324                 break;
4325         }
4326 }
4327 
4328 /**
4329  * Sets the power management mode of the pipe and plane.
4330  */
4331 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4332 {
4333         struct drm_device *dev = crtc->dev;
4334         struct drm_i915_private *dev_priv = dev->dev_private;
4335         struct intel_encoder *intel_encoder;
4336         bool enable = false;
4337 
4338         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4339                 enable |= intel_encoder->connectors_active;
4340 
4341         if (enable)
4342                 dev_priv->display.crtc_enable(crtc);
4343         else
4344                 dev_priv->display.crtc_disable(crtc);
4345 
4346         intel_crtc_update_sarea(crtc, enable);
4347 }
4348 
4349 static void intel_crtc_disable(struct drm_crtc *crtc)
4350 {
4351         struct drm_device *dev = crtc->dev;
4352         struct drm_connector *connector;
4353         struct drm_i915_private *dev_priv = dev->dev_private;
4354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4355 
4356         /* crtc should still be enabled when we disable it. */
4357         WARN_ON(!crtc->enabled);
4358 
4359         dev_priv->display.crtc_disable(crtc);
4360         intel_crtc->eld_vld = false;
4361         intel_crtc_update_sarea(crtc, false);
4362         dev_priv->display.off(crtc);
4363 
4364         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4365         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4366         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4367 
4368         if (crtc->fb) {
4369                 mutex_lock(&dev->struct_mutex);
4370                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4371                 mutex_unlock(&dev->struct_mutex);
4372                 crtc->fb = NULL;
4373         }
4374 
4375         /* Update computed state. */
4376         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4377                 if (!connector->encoder || !connector->encoder->crtc)
4378                         continue;
4379 
4380                 if (connector->encoder->crtc != crtc)
4381                         continue;
4382 
4383                 connector->dpms = DRM_MODE_DPMS_OFF;
4384                 to_intel_encoder(connector->encoder)->connectors_active = false;
4385         }
4386 }
4387 
4388 void intel_encoder_destroy(struct drm_encoder *encoder)
4389 {
4390         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4391 
4392         drm_encoder_cleanup(encoder);
4393         kfree(intel_encoder);
4394 }
4395 
4396 /* Simple dpms helper for encoders with just one connector, no cloning and only
4397  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4398  * state of the entire output pipe. */
4399 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4400 {
4401         if (mode == DRM_MODE_DPMS_ON) {
4402                 encoder->connectors_active = true;
4403 
4404                 intel_crtc_update_dpms(encoder->base.crtc);
4405         } else {
4406                 encoder->connectors_active = false;
4407 
4408                 intel_crtc_update_dpms(encoder->base.crtc);
4409         }
4410 }
4411 
4412 /* Cross check the actual hw state with our own modeset state tracking (and it's
4413  * internal consistency). */
4414 static void intel_connector_check_state(struct intel_connector *connector)
4415 {
4416         if (connector->get_hw_state(connector)) {
4417                 struct intel_encoder *encoder = connector->encoder;
4418                 struct drm_crtc *crtc;
4419                 bool encoder_enabled;
4420                 enum pipe pipe;
4421 
4422                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4423                               connector->base.base.id,
4424                               drm_get_connector_name(&connector->base));
4425 
4426                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4427                      "wrong connector dpms state\n");
4428                 WARN(connector->base.encoder != &encoder->base,
4429                      "active connector not linked to encoder\n");
4430                 WARN(!encoder->connectors_active,
4431                      "encoder->connectors_active not set\n");
4432 
4433                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4434                 WARN(!encoder_enabled, "encoder not enabled\n");
4435                 if (WARN_ON(!encoder->base.crtc))
4436                         return;
4437 
4438                 crtc = encoder->base.crtc;
4439 
4440                 WARN(!crtc->enabled, "crtc not enabled\n");
4441                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4442                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4443                      "encoder active on the wrong pipe\n");
4444         }
4445 }
4446 
4447 /* Even simpler default implementation, if there's really no special case to
4448  * consider. */
4449 void intel_connector_dpms(struct drm_connector *connector, int mode)
4450 {
4451         /* All the simple cases only support two dpms states. */
4452         if (mode != DRM_MODE_DPMS_ON)
4453                 mode = DRM_MODE_DPMS_OFF;
4454 
4455         if (mode == connector->dpms)
4456                 return;
4457 
4458         connector->dpms = mode;
4459 
4460         /* Only need to change hw state when actually enabled */
4461         if (connector->encoder)
4462                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4463 
4464         intel_modeset_check_state(connector->dev);
4465 }
4466 
4467 /* Simple connector->get_hw_state implementation for encoders that support only
4468  * one connector and no cloning and hence the encoder state determines the state
4469  * of the connector. */
4470 bool intel_connector_get_hw_state(struct intel_connector *connector)
4471 {
4472         enum pipe pipe = 0;
4473         struct intel_encoder *encoder = connector->encoder;
4474 
4475         return encoder->get_hw_state(encoder, &pipe);
4476 }
4477 
4478 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4479                                      struct intel_crtc_config *pipe_config)
4480 {
4481         struct drm_i915_private *dev_priv = dev->dev_private;
4482         struct intel_crtc *pipe_B_crtc =
4483                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4484 
4485         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4486                       pipe_name(pipe), pipe_config->fdi_lanes);
4487         if (pipe_config->fdi_lanes > 4) {
4488                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4489                               pipe_name(pipe), pipe_config->fdi_lanes);
4490                 return false;
4491         }
4492 
4493         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4494                 if (pipe_config->fdi_lanes > 2) {
4495                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4496                                       pipe_config->fdi_lanes);
4497                         return false;
4498                 } else {
4499                         return true;
4500                 }
4501         }
4502 
4503         if (INTEL_INFO(dev)->num_pipes == 2)
4504                 return true;
4505 
4506         /* Ivybridge 3 pipe is really complicated */
4507         switch (pipe) {
4508         case PIPE_A:
4509                 return true;
4510         case PIPE_B:
4511                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4512                     pipe_config->fdi_lanes > 2) {
4513                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4514                                       pipe_name(pipe), pipe_config->fdi_lanes);
4515                         return false;
4516                 }
4517                 return true;
4518         case PIPE_C:
4519                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4520                     pipe_B_crtc->config.fdi_lanes <= 2) {
4521                         if (pipe_config->fdi_lanes > 2) {
4522                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4523                                               pipe_name(pipe), pipe_config->fdi_lanes);
4524                                 return false;
4525                         }
4526                 } else {
4527                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4528                         return false;
4529                 }
4530                 return true;
4531         default:
4532                 BUG();
4533         }
4534 }
4535 
4536 #define RETRY 1
4537 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4538                                        struct intel_crtc_config *pipe_config)
4539 {
4540         struct drm_device *dev = intel_crtc->base.dev;
4541         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4542         int lane, link_bw, fdi_dotclock;
4543         bool setup_ok, needs_recompute = false;
4544 
4545 retry:
4546         /* FDI is a binary signal running at ~2.7GHz, encoding
4547          * each output octet as 10 bits. The actual frequency
4548          * is stored as a divider into a 100MHz clock, and the
4549          * mode pixel clock is stored in units of 1KHz.
4550          * Hence the bw of each lane in terms of the mode signal
4551          * is:
4552          */
4553         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4554 
4555         fdi_dotclock = adjusted_mode->crtc_clock;
4556 
4557         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4558                                            pipe_config->pipe_bpp);
4559 
4560         pipe_config->fdi_lanes = lane;
4561 
4562         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4563                                link_bw, &pipe_config->fdi_m_n);
4564 
4565         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4566                                             intel_crtc->pipe, pipe_config);
4567         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4568                 pipe_config->pipe_bpp -= 2*3;
4569                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4570                               pipe_config->pipe_bpp);
4571                 needs_recompute = true;
4572                 pipe_config->bw_constrained = true;
4573 
4574                 goto retry;
4575         }
4576 
4577         if (needs_recompute)
4578                 return RETRY;
4579 
4580         return setup_ok ? 0 : -EINVAL;
4581 }
4582 
4583 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4584                                    struct intel_crtc_config *pipe_config)
4585 {
4586         pipe_config->ips_enabled = i915_enable_ips &&
4587                                    hsw_crtc_supports_ips(crtc) &&
4588                                    pipe_config->pipe_bpp <= 24;
4589 }
4590 
4591 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4592                                      struct intel_crtc_config *pipe_config)
4593 {
4594         struct drm_device *dev = crtc->base.dev;
4595         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4596 
4597         /* FIXME should check pixel clock limits on all platforms */
4598         if (INTEL_INFO(dev)->gen < 4) {
4599                 struct drm_i915_private *dev_priv = dev->dev_private;
4600                 int clock_limit =
4601                         dev_priv->display.get_display_clock_speed(dev);
4602 
4603                 /*
4604                  * Enable pixel doubling when the dot clock
4605                  * is > 90% of the (display) core speed.
4606                  *
4607                  * GDG double wide on either pipe,
4608                  * otherwise pipe A only.
4609                  */
4610                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4611                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4612                         clock_limit *= 2;
4613                         pipe_config->double_wide = true;
4614                 }
4615 
4616                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4617                         return -EINVAL;
4618         }
4619 
4620         /*
4621          * Pipe horizontal size must be even in:
4622          * - DVO ganged mode
4623          * - LVDS dual channel mode
4624          * - Double wide pipe
4625          */
4626         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4627              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4628                 pipe_config->pipe_src_w &= ~1;
4629 
4630         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4631          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4632          */
4633         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4634                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4635                 return -EINVAL;
4636 
4637         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4638                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4639         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4640                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4641                  * for lvds. */
4642                 pipe_config->pipe_bpp = 8*3;
4643         }
4644 
4645         if (HAS_IPS(dev))
4646                 hsw_compute_ips_config(crtc, pipe_config);
4647 
4648         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4649          * clock survives for now. */
4650         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4651                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4652 
4653         if (pipe_config->has_pch_encoder)
4654                 return ironlake_fdi_compute_config(crtc, pipe_config);
4655 
4656         return 0;
4657 }
4658 
4659 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4660 {
4661         return 400000; /* FIXME */
4662 }
4663 
4664 static int i945_get_display_clock_speed(struct drm_device *dev)
4665 {
4666         return 400000;
4667 }
4668 
4669 static int i915_get_display_clock_speed(struct drm_device *dev)
4670 {
4671         return 333000;
4672 }
4673 
4674 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4675 {
4676         return 200000;
4677 }
4678 
4679 static int pnv_get_display_clock_speed(struct drm_device *dev)
4680 {
4681         u16 gcfgc = 0;
4682 
4683         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4684 
4685         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4686         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4687                 return 267000;
4688         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4689                 return 333000;
4690         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4691                 return 444000;
4692         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4693                 return 200000;
4694         default:
4695                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4696         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4697                 return 133000;
4698         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4699                 return 167000;
4700         }
4701 }
4702 
4703 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4704 {
4705         u16 gcfgc = 0;
4706 
4707         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4708 
4709         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4710                 return 133000;
4711         else {
4712                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4713                 case GC_DISPLAY_CLOCK_333_MHZ:
4714                         return 333000;
4715                 default:
4716                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4717                         return 190000;
4718                 }
4719         }
4720 }
4721 
4722 static int i865_get_display_clock_speed(struct drm_device *dev)
4723 {
4724         return 266000;
4725 }
4726 
4727 static int i855_get_display_clock_speed(struct drm_device *dev)
4728 {
4729         u16 hpllcc = 0;
4730         /* Assume that the hardware is in the high speed state.  This
4731          * should be the default.
4732          */
4733         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4734         case GC_CLOCK_133_200:
4735         case GC_CLOCK_100_200:
4736                 return 200000;
4737         case GC_CLOCK_166_250:
4738                 return 250000;
4739         case GC_CLOCK_100_133:
4740                 return 133000;
4741         }
4742 
4743         /* Shouldn't happen */
4744         return 0;
4745 }
4746 
4747 static int i830_get_display_clock_speed(struct drm_device *dev)
4748 {
4749         return 133000;
4750 }
4751 
4752 static void
4753 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4754 {
4755         while (*num > DATA_LINK_M_N_MASK ||
4756                *den > DATA_LINK_M_N_MASK) {
4757                 *num >>= 1;
4758                 *den >>= 1;
4759         }
4760 }
4761 
4762 static void compute_m_n(unsigned int m, unsigned int n,
4763                         uint32_t *ret_m, uint32_t *ret_n)
4764 {
4765         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4766         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4767         intel_reduce_m_n_ratio(ret_m, ret_n);
4768 }
4769 
4770 void
4771 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4772                        int pixel_clock, int link_clock,
4773                        struct intel_link_m_n *m_n)
4774 {
4775         m_n->tu = 64;
4776 
4777         compute_m_n(bits_per_pixel * pixel_clock,
4778                     link_clock * nlanes * 8,
4779                     &m_n->gmch_m, &m_n->gmch_n);
4780 
4781         compute_m_n(pixel_clock, link_clock,
4782                     &m_n->link_m, &m_n->link_n);
4783 }
4784 
4785 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4786 {
4787         if (i915_panel_use_ssc >= 0)
4788                 return i915_panel_use_ssc != 0;
4789         return dev_priv->vbt.lvds_use_ssc
4790                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4791 }
4792 
4793 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4794 {
4795         struct drm_device *dev = crtc->dev;
4796         struct drm_i915_private *dev_priv = dev->dev_private;
4797         int refclk;
4798 
4799         if (IS_VALLEYVIEW(dev)) {
4800                 refclk = 100000;
4801         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4802             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4803                 refclk = dev_priv->vbt.lvds_ssc_freq;
4804                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4805         } else if (!IS_GEN2(dev)) {
4806                 refclk = 96000;
4807         } else {
4808                 refclk = 48000;
4809         }
4810 
4811         return refclk;
4812 }
4813 
4814 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4815 {
4816         return (1 << dpll->n) << 16 | dpll->m2;
4817 }
4818 
4819 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4820 {
4821         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4822 }
4823 
4824 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4825                                      intel_clock_t *reduced_clock)
4826 {
4827         struct drm_device *dev = crtc->base.dev;
4828         struct drm_i915_private *dev_priv = dev->dev_private;
4829         int pipe = crtc->pipe;
4830         u32 fp, fp2 = 0;
4831 
4832         if (IS_PINEVIEW(dev)) {
4833                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4834                 if (reduced_clock)
4835                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4836         } else {
4837                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4838                 if (reduced_clock)
4839                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4840         }
4841 
4842         I915_WRITE(FP0(pipe), fp);
4843         crtc->config.dpll_hw_state.fp0 = fp;
4844 
4845         crtc->lowfreq_avail = false;
4846         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4847             reduced_clock && i915_powersave) {
4848                 I915_WRITE(FP1(pipe), fp2);
4849                 crtc->config.dpll_hw_state.fp1 = fp2;
4850                 crtc->lowfreq_avail = true;
4851         } else {
4852                 I915_WRITE(FP1(pipe), fp);
4853                 crtc->config.dpll_hw_state.fp1 = fp;
4854         }
4855 }
4856 
4857 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4858                 pipe)
4859 {
4860         u32 reg_val;
4861 
4862         /*
4863          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4864          * and set it to a reasonable value instead.
4865          */
4866         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4867         reg_val &= 0xffffff00;
4868         reg_val |= 0x00000030;
4869         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4870 
4871         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4872         reg_val &= 0x8cffffff;
4873         reg_val = 0x8c000000;
4874         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4875 
4876         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4877         reg_val &= 0xffffff00;
4878         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4879 
4880         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4881         reg_val &= 0x00ffffff;
4882         reg_val |= 0xb0000000;
4883         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4884 }
4885 
4886 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4887                                          struct intel_link_m_n *m_n)
4888 {
4889         struct drm_device *dev = crtc->base.dev;
4890         struct drm_i915_private *dev_priv = dev->dev_private;
4891         int pipe = crtc->pipe;
4892 
4893         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4894         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4895         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4896         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4897 }
4898 
4899 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4900                                          struct intel_link_m_n *m_n)
4901 {
4902         struct drm_device *dev = crtc->base.dev;
4903         struct drm_i915_private *dev_priv = dev->dev_private;
4904         int pipe = crtc->pipe;
4905         enum transcoder transcoder = crtc->config.cpu_transcoder;
4906 
4907         if (INTEL_INFO(dev)->gen >= 5) {
4908                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4909                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4910                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4911                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4912         } else {
4913                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4914                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4915                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4916                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4917         }
4918 }
4919 
4920 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4921 {
4922         if (crtc->config.has_pch_encoder)
4923                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4924         else
4925                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4926 }
4927 
4928 static void vlv_update_pll(struct intel_crtc *crtc)
4929 {
4930         struct drm_device *dev = crtc->base.dev;
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932         int pipe = crtc->pipe;
4933         u32 dpll, mdiv;
4934         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4935         u32 coreclk, reg_val, dpll_md;
4936 
4937         mutex_lock(&dev_priv->dpio_lock);
4938 
4939         bestn = crtc->config.dpll.n;
4940         bestm1 = crtc->config.dpll.m1;
4941         bestm2 = crtc->config.dpll.m2;
4942         bestp1 = crtc->config.dpll.p1;
4943         bestp2 = crtc->config.dpll.p2;
4944 
4945         /* See eDP HDMI DPIO driver vbios notes doc */
4946 
4947         /* PLL B needs special handling */
4948         if (pipe)
4949                 vlv_pllb_recal_opamp(dev_priv, pipe);
4950 
4951         /* Set up Tx target for periodic Rcomp update */
4952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4953 
4954         /* Disable target IRef on PLL */
4955         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4956         reg_val &= 0x00ffffff;
4957         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4958 
4959         /* Disable fast lock */
4960         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4961 
4962         /* Set idtafcrecal before PLL is enabled */
4963         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4964         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4965         mdiv |= ((bestn << DPIO_N_SHIFT));
4966         mdiv |= (1 << DPIO_K_SHIFT);
4967 
4968         /*
4969          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4970          * but we don't support that).
4971          * Note: don't use the DAC post divider as it seems unstable.
4972          */
4973         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4974         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4975 
4976         mdiv |= DPIO_ENABLE_CALIBRATION;
4977         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4978 
4979         /* Set HBR and RBR LPF coefficients */
4980         if (crtc->config.port_clock == 162000 ||
4981             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4982             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4983                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4984                                  0x009f0003);
4985         else
4986                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4987                                  0x00d0000f);
4988 
4989         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4990             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4991                 /* Use SSC source */
4992                 if (!pipe)
4993                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4994                                          0x0df40000);
4995                 else
4996                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4997                                          0x0df70000);
4998         } else { /* HDMI or VGA */
4999                 /* Use bend source */
5000                 if (!pipe)
5001                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5002                                          0x0df70000);
5003                 else
5004                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5005                                          0x0df40000);
5006         }
5007 
5008         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5009         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5010         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5011             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5012                 coreclk |= 0x01000000;
5013         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5014 
5015         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5016 
5017         /*
5018          * Enable DPIO clock input. We should never disable the reference
5019          * clock for pipe B, since VGA hotplug / manual detection depends
5020          * on it.
5021          */
5022         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5023                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5024         /* We should never disable this, set it here for state tracking */
5025         if (pipe == PIPE_B)
5026                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5027         dpll |= DPLL_VCO_ENABLE;
5028         crtc->config.dpll_hw_state.dpll = dpll;
5029 
5030         dpll_md = (crtc->config.pixel_multiplier - 1)
5031                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5032         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5033 
5034         if (crtc->config.has_dp_encoder)
5035                 intel_dp_set_m_n(crtc);
5036 
5037         mutex_unlock(&dev_priv->dpio_lock);
5038 }
5039 
5040 static void i9xx_update_pll(struct intel_crtc *crtc,
5041                             intel_clock_t *reduced_clock,
5042                             int num_connectors)
5043 {
5044         struct drm_device *dev = crtc->base.dev;
5045         struct drm_i915_private *dev_priv = dev->dev_private;
5046         u32 dpll;
5047         bool is_sdvo;
5048         struct dpll *clock = &crtc->config.dpll;
5049 
5050         i9xx_update_pll_dividers(crtc, reduced_clock);
5051 
5052         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5053                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5054 
5055         dpll = DPLL_VGA_MODE_DIS;
5056 
5057         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5058                 dpll |= DPLLB_MODE_LVDS;
5059         else
5060                 dpll |= DPLLB_MODE_DAC_SERIAL;
5061 
5062         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5063                 dpll |= (crtc->config.pixel_multiplier - 1)
5064                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5065         }
5066 
5067         if (is_sdvo)
5068                 dpll |= DPLL_SDVO_HIGH_SPEED;
5069 
5070         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5071                 dpll |= DPLL_SDVO_HIGH_SPEED;
5072 
5073         /* compute bitmask from p1 value */
5074         if (IS_PINEVIEW(dev))
5075                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5076         else {
5077                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5078                 if (IS_G4X(dev) && reduced_clock)
5079                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5080         }
5081         switch (clock->p2) {
5082         case 5:
5083                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5084                 break;
5085         case 7:
5086                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5087                 break;
5088         case 10:
5089                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5090                 break;
5091         case 14:
5092                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5093                 break;
5094         }
5095         if (INTEL_INFO(dev)->gen >= 4)
5096                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5097 
5098         if (crtc->config.sdvo_tv_clock)
5099                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5100         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5101                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5102                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5103         else
5104                 dpll |= PLL_REF_INPUT_DREFCLK;
5105 
5106         dpll |= DPLL_VCO_ENABLE;
5107         crtc->config.dpll_hw_state.dpll = dpll;
5108 
5109         if (INTEL_INFO(dev)->gen >= 4) {
5110                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5111                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5112                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5113         }
5114 
5115         if (crtc->config.has_dp_encoder)
5116                 intel_dp_set_m_n(crtc);
5117 }
5118 
5119 static void i8xx_update_pll(struct intel_crtc *crtc,
5120                             intel_clock_t *reduced_clock,
5121                             int num_connectors)
5122 {
5123         struct drm_device *dev = crtc->base.dev;
5124         struct drm_i915_private *dev_priv = dev->dev_private;
5125         u32 dpll;
5126         struct dpll *clock = &crtc->config.dpll;
5127 
5128         i9xx_update_pll_dividers(crtc, reduced_clock);
5129 
5130         dpll = DPLL_VGA_MODE_DIS;
5131 
5132         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5133                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5134         } else {
5135                 if (clock->p1 == 2)
5136                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5137                 else
5138                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5139                 if (clock->p2 == 4)
5140                         dpll |= PLL_P2_DIVIDE_BY_4;
5141         }
5142 
5143         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5144                 dpll |= DPLL_DVO_2X_MODE;
5145 
5146         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5147                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5148                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5149         else
5150                 dpll |= PLL_REF_INPUT_DREFCLK;
5151 
5152         dpll |= DPLL_VCO_ENABLE;
5153         crtc->config.dpll_hw_state.dpll = dpll;
5154 }
5155 
5156 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5157 {
5158         struct drm_device *dev = intel_crtc->base.dev;
5159         struct drm_i915_private *dev_priv = dev->dev_private;
5160         enum pipe pipe = intel_crtc->pipe;
5161         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5162         struct drm_display_mode *adjusted_mode =
5163                 &intel_crtc->config.adjusted_mode;
5164         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5165 
5166         /* We need to be careful not to changed the adjusted mode, for otherwise
5167          * the hw state checker will get angry at the mismatch. */
5168         crtc_vtotal = adjusted_mode->crtc_vtotal;
5169         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5170 
5171         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5172                 /* the chip adds 2 halflines automatically */
5173                 crtc_vtotal -= 1;
5174                 crtc_vblank_end -= 1;
5175                 vsyncshift = adjusted_mode->crtc_hsync_start
5176                              - adjusted_mode->crtc_htotal / 2;
5177         } else {
5178                 vsyncshift = 0;
5179         }
5180 
5181         if (INTEL_INFO(dev)->gen > 3)
5182                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5183 
5184         I915_WRITE(HTOTAL(cpu_transcoder),
5185                    (adjusted_mode->crtc_hdisplay - 1) |
5186                    ((adjusted_mode->crtc_htotal - 1) << 16));
5187         I915_WRITE(HBLANK(cpu_transcoder),
5188                    (adjusted_mode->crtc_hblank_start - 1) |
5189                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5190         I915_WRITE(HSYNC(cpu_transcoder),
5191                    (adjusted_mode->crtc_hsync_start - 1) |
5192                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5193 
5194         I915_WRITE(VTOTAL(cpu_transcoder),
5195                    (adjusted_mode->crtc_vdisplay - 1) |
5196                    ((crtc_vtotal - 1) << 16));
5197         I915_WRITE(VBLANK(cpu_transcoder),
5198                    (adjusted_mode->crtc_vblank_start - 1) |
5199                    ((crtc_vblank_end - 1) << 16));
5200         I915_WRITE(VSYNC(cpu_transcoder),
5201                    (adjusted_mode->crtc_vsync_start - 1) |
5202                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5203 
5204         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5205          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5206          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5207          * bits. */
5208         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5209             (pipe == PIPE_B || pipe == PIPE_C))
5210                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5211 
5212         /* pipesrc controls the size that is scaled from, which should
5213          * always be the user's requested size.
5214          */
5215         I915_WRITE(PIPESRC(pipe),
5216                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5217                    (intel_crtc->config.pipe_src_h - 1));
5218 }
5219 
5220 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5221                                    struct intel_crtc_config *pipe_config)
5222 {
5223         struct drm_device *dev = crtc->base.dev;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5226         uint32_t tmp;
5227 
5228         tmp = I915_READ(HTOTAL(cpu_transcoder));
5229         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5230         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5231         tmp = I915_READ(HBLANK(cpu_transcoder));
5232         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5233         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5234         tmp = I915_READ(HSYNC(cpu_transcoder));
5235         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5236         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5237 
5238         tmp = I915_READ(VTOTAL(cpu_transcoder));
5239         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5240         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5241         tmp = I915_READ(VBLANK(cpu_transcoder));
5242         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5243         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5244         tmp = I915_READ(VSYNC(cpu_transcoder));
5245         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5246         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5247 
5248         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5249                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5250                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5251                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5252         }
5253 
5254         tmp = I915_READ(PIPESRC(crtc->pipe));
5255         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5256         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5257 
5258         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5259         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5260 }
5261 
5262 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5263                                              struct intel_crtc_config *pipe_config)
5264 {
5265         struct drm_crtc *crtc = &intel_crtc->base;
5266 
5267         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5268         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5269         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5270         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5271 
5272         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5273         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5274         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5275         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5276 
5277         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5278 
5279         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5280         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5281 }
5282 
5283 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5284 {
5285         struct drm_device *dev = intel_crtc->base.dev;
5286         struct drm_i915_private *dev_priv = dev->dev_private;
5287         uint32_t pipeconf;
5288 
5289         pipeconf = 0;
5290 
5291         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5292             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5293                 pipeconf |= PIPECONF_ENABLE;
5294 
5295         if (intel_crtc->config.double_wide)
5296                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5297 
5298         /* only g4x and later have fancy bpc/dither controls */
5299         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5300                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5301                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5302                         pipeconf |= PIPECONF_DITHER_EN |
5303                                     PIPECONF_DITHER_TYPE_SP;
5304 
5305                 switch (intel_crtc->config.pipe_bpp) {
5306                 case 18:
5307                         pipeconf |= PIPECONF_6BPC;
5308                         break;
5309                 case 24:
5310                         pipeconf |= PIPECONF_8BPC;
5311                         break;
5312                 case 30:
5313                         pipeconf |= PIPECONF_10BPC;
5314                         break;
5315                 default:
5316                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5317                         BUG();
5318                 }
5319         }
5320 
5321         if (HAS_PIPE_CXSR(dev)) {
5322                 if (intel_crtc->lowfreq_avail) {
5323                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5324                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5325                 } else {
5326                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5327                 }
5328         }
5329 
5330         if (!IS_GEN2(dev) &&
5331             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5332                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5333         else
5334                 pipeconf |= PIPECONF_PROGRESSIVE;
5335 
5336         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5337                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5338 
5339         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5340         POSTING_READ(PIPECONF(intel_crtc->pipe));
5341 }
5342 
5343 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5344                               int x, int y,
5345                               struct drm_framebuffer *fb)
5346 {
5347         struct drm_device *dev = crtc->dev;
5348         struct drm_i915_private *dev_priv = dev->dev_private;
5349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350         int pipe = intel_crtc->pipe;
5351         int plane = intel_crtc->plane;
5352         int refclk, num_connectors = 0;
5353         intel_clock_t clock, reduced_clock;
5354         u32 dspcntr;
5355         bool ok, has_reduced_clock = false;
5356         bool is_lvds = false, is_dsi = false;
5357         struct intel_encoder *encoder;
5358         const intel_limit_t *limit;
5359         int ret;
5360 
5361         for_each_encoder_on_crtc(dev, crtc, encoder) {
5362                 switch (encoder->type) {
5363                 case INTEL_OUTPUT_LVDS:
5364                         is_lvds = true;
5365                         break;
5366                 case INTEL_OUTPUT_DSI:
5367                         is_dsi = true;
5368                         break;
5369                 }
5370 
5371                 num_connectors++;
5372         }
5373 
5374         if (is_dsi)
5375                 goto skip_dpll;
5376 
5377         if (!intel_crtc->config.clock_set) {
5378                 refclk = i9xx_get_refclk(crtc, num_connectors);
5379 
5380                 /*
5381                  * Returns a set of divisors for the desired target clock with
5382                  * the given refclk, or FALSE.  The returned values represent
5383                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5384                  * 2) / p1 / p2.
5385                  */
5386                 limit = intel_limit(crtc, refclk);
5387                 ok = dev_priv->display.find_dpll(limit, crtc,
5388                                                  intel_crtc->config.port_clock,
5389                                                  refclk, NULL, &clock);
5390                 if (!ok) {
5391                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5392                         return -EINVAL;
5393                 }
5394 
5395                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5396                         /*
5397                          * Ensure we match the reduced clock's P to the target
5398                          * clock.  If the clocks don't match, we can't switch
5399                          * the display clock by using the FP0/FP1. In such case
5400                          * we will disable the LVDS downclock feature.
5401                          */
5402                         has_reduced_clock =
5403                                 dev_priv->display.find_dpll(limit, crtc,
5404                                                             dev_priv->lvds_downclock,
5405                                                             refclk, &clock,
5406                                                             &reduced_clock);
5407                 }
5408                 /* Compat-code for transition, will disappear. */
5409                 intel_crtc->config.dpll.n = clock.n;
5410                 intel_crtc->config.dpll.m1 = clock.m1;
5411                 intel_crtc->config.dpll.m2 = clock.m2;
5412                 intel_crtc->config.dpll.p1 = clock.p1;
5413                 intel_crtc->config.dpll.p2 = clock.p2;
5414         }
5415 
5416         if (IS_GEN2(dev)) {
5417                 i8xx_update_pll(intel_crtc,
5418                                 has_reduced_clock ? &reduced_clock : NULL,
5419                                 num_connectors);
5420         } else if (IS_VALLEYVIEW(dev)) {
5421                 vlv_update_pll(intel_crtc);
5422         } else {
5423                 i9xx_update_pll(intel_crtc,
5424                                 has_reduced_clock ? &reduced_clock : NULL,
5425                                 num_connectors);
5426         }
5427 
5428 skip_dpll:
5429         /* Set up the display plane register */
5430         dspcntr = DISPPLANE_GAMMA_ENABLE;
5431 
5432         if (!IS_VALLEYVIEW(dev)) {
5433                 if (pipe == 0)
5434                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5435                 else
5436                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5437         }
5438 
5439         intel_set_pipe_timings(intel_crtc);
5440 
5441         /* pipesrc and dspsize control the size that is scaled from,
5442          * which should always be the user's requested size.
5443          */
5444         I915_WRITE(DSPSIZE(plane),
5445                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5446                    (intel_crtc->config.pipe_src_w - 1));
5447         I915_WRITE(DSPPOS(plane), 0);
5448 
5449         i9xx_set_pipeconf(intel_crtc);
5450 
5451         I915_WRITE(DSPCNTR(plane), dspcntr);
5452         POSTING_READ(DSPCNTR(plane));
5453 
5454         ret = intel_pipe_set_base(crtc, x, y, fb);
5455 
5456         return ret;
5457 }
5458 
5459 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5460                                  struct intel_crtc_config *pipe_config)
5461 {
5462         struct drm_device *dev = crtc->base.dev;
5463         struct drm_i915_private *dev_priv = dev->dev_private;
5464         uint32_t tmp;
5465 
5466         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5467                 return;
5468 
5469         tmp = I915_READ(PFIT_CONTROL);
5470         if (!(tmp & PFIT_ENABLE))
5471                 return;
5472 
5473         /* Check whether the pfit is attached to our pipe. */
5474         if (INTEL_INFO(dev)->gen < 4) {
5475                 if (crtc->pipe != PIPE_B)
5476                         return;
5477         } else {
5478                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5479                         return;
5480         }
5481 
5482         pipe_config->gmch_pfit.control = tmp;
5483         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5484         if (INTEL_INFO(dev)->gen < 5)
5485                 pipe_config->gmch_pfit.lvds_border_bits =
5486                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5487 }
5488 
5489 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5490                                struct intel_crtc_config *pipe_config)
5491 {
5492         struct drm_device *dev = crtc->base.dev;
5493         struct drm_i915_private *dev_priv = dev->dev_private;
5494         int pipe = pipe_config->cpu_transcoder;
5495         intel_clock_t clock;
5496         u32 mdiv;
5497         int refclk = 100000;
5498 
5499         mutex_lock(&dev_priv->dpio_lock);
5500         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5501         mutex_unlock(&dev_priv->dpio_lock);
5502 
5503         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5504         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5505         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5506         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5507         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5508 
5509         vlv_clock(refclk, &clock);
5510 
5511         /* clock.dot is the fast clock */
5512         pipe_config->port_clock = clock.dot / 5;
5513 }
5514 
5515 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5516                                  struct intel_crtc_config *pipe_config)
5517 {
5518         struct drm_device *dev = crtc->base.dev;
5519         struct drm_i915_private *dev_priv = dev->dev_private;
5520         uint32_t tmp;
5521 
5522         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5523         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5524 
5525         tmp = I915_READ(PIPECONF(crtc->pipe));
5526         if (!(tmp & PIPECONF_ENABLE))
5527                 return false;
5528 
5529         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5530                 switch (tmp & PIPECONF_BPC_MASK) {
5531                 case PIPECONF_6BPC:
5532                         pipe_config->pipe_bpp = 18;
5533                         break;
5534                 case PIPECONF_8BPC:
5535                         pipe_config->pipe_bpp = 24;
5536                         break;
5537                 case PIPECONF_10BPC:
5538                         pipe_config->pipe_bpp = 30;
5539                         break;
5540                 default:
5541                         break;
5542                 }
5543         }
5544 
5545         if (INTEL_INFO(dev)->gen < 4)
5546                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5547 
5548         intel_get_pipe_timings(crtc, pipe_config);
5549 
5550         i9xx_get_pfit_config(crtc, pipe_config);
5551 
5552         if (INTEL_INFO(dev)->gen >= 4) {
5553                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5554                 pipe_config->pixel_multiplier =
5555                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5556                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5557                 pipe_config->dpll_hw_state.dpll_md = tmp;
5558         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5559                 tmp = I915_READ(DPLL(crtc->pipe));
5560                 pipe_config->pixel_multiplier =
5561                         ((tmp & SDVO_MULTIPLIER_MASK)
5562                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5563         } else {
5564                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5565                  * port and will be fixed up in the encoder->get_config
5566                  * function. */
5567                 pipe_config->pixel_multiplier = 1;
5568         }
5569         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5570         if (!IS_VALLEYVIEW(dev)) {
5571                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5572                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5573         } else {
5574                 /* Mask out read-only status bits. */
5575                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5576                                                      DPLL_PORTC_READY_MASK |
5577                                                      DPLL_PORTB_READY_MASK);
5578         }
5579 
5580         if (IS_VALLEYVIEW(dev))
5581                 vlv_crtc_clock_get(crtc, pipe_config);
5582         else
5583                 i9xx_crtc_clock_get(crtc, pipe_config);
5584 
5585         return true;
5586 }
5587 
5588 static void ironlake_init_pch_refclk(struct drm_device *dev)
5589 {
5590         struct drm_i915_private *dev_priv = dev->dev_private;
5591         struct drm_mode_config *mode_config = &dev->mode_config;
5592         struct intel_encoder *encoder;
5593         u32 val, final;
5594         bool has_lvds = false;
5595         bool has_cpu_edp = false;
5596         bool has_panel = false;
5597         bool has_ck505 = false;
5598         bool can_ssc = false;
5599 
5600         /* We need to take the global config into account */
5601         list_for_each_entry(encoder, &mode_config->encoder_list,
5602                             base.head) {
5603                 switch (encoder->type) {
5604                 case INTEL_OUTPUT_LVDS:
5605                         has_panel = true;
5606                         has_lvds = true;
5607                         break;
5608                 case INTEL_OUTPUT_EDP:
5609                         has_panel = true;
5610                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5611                                 has_cpu_edp = true;
5612                         break;
5613                 }
5614         }
5615 
5616         if (HAS_PCH_IBX(dev)) {
5617                 has_ck505 = dev_priv->vbt.display_clock_mode;
5618                 can_ssc = has_ck505;
5619         } else {
5620                 has_ck505 = false;
5621                 can_ssc = true;
5622         }
5623 
5624         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5625                       has_panel, has_lvds, has_ck505);
5626 
5627         /* Ironlake: try to setup display ref clock before DPLL
5628          * enabling. This is only under driver's control after
5629          * PCH B stepping, previous chipset stepping should be
5630          * ignoring this setting.
5631          */
5632         val = I915_READ(PCH_DREF_CONTROL);
5633 
5634         /* As we must carefully and slowly disable/enable each source in turn,
5635          * compute the final state we want first and check if we need to
5636          * make any changes at all.
5637          */
5638         final = val;
5639         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5640         if (has_ck505)
5641                 final |= DREF_NONSPREAD_CK505_ENABLE;
5642         else
5643                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5644 
5645         final &= ~DREF_SSC_SOURCE_MASK;
5646         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5647         final &= ~DREF_SSC1_ENABLE;
5648 
5649         if (has_panel) {
5650                 final |= DREF_SSC_SOURCE_ENABLE;
5651 
5652                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5653                         final |= DREF_SSC1_ENABLE;
5654 
5655                 if (has_cpu_edp) {
5656                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5657                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5658                         else
5659                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5660                 } else
5661                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5662         } else {
5663                 final |= DREF_SSC_SOURCE_DISABLE;
5664                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5665         }
5666 
5667         if (final == val)
5668                 return;
5669 
5670         /* Always enable nonspread source */
5671         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5672 
5673         if (has_ck505)
5674                 val |= DREF_NONSPREAD_CK505_ENABLE;
5675         else
5676                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5677 
5678         if (has_panel) {
5679                 val &= ~DREF_SSC_SOURCE_MASK;
5680                 val |= DREF_SSC_SOURCE_ENABLE;
5681 
5682                 /* SSC must be turned on before enabling the CPU output  */
5683                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5684                         DRM_DEBUG_KMS("Using SSC on panel\n");
5685                         val |= DREF_SSC1_ENABLE;
5686                 } else
5687                         val &= ~DREF_SSC1_ENABLE;
5688 
5689                 /* Get SSC going before enabling the outputs */
5690                 I915_WRITE(PCH_DREF_CONTROL, val);
5691                 POSTING_READ(PCH_DREF_CONTROL);
5692                 udelay(200);
5693 
5694                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5695 
5696                 /* Enable CPU source on CPU attached eDP */
5697                 if (has_cpu_edp) {
5698                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5699                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5700                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5701                         }
5702                         else
5703                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5704                 } else
5705                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5706 
5707                 I915_WRITE(PCH_DREF_CONTROL, val);
5708                 POSTING_READ(PCH_DREF_CONTROL);
5709                 udelay(200);
5710         } else {
5711                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5712 
5713                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5714 
5715                 /* Turn off CPU output */
5716                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5717 
5718                 I915_WRITE(PCH_DREF_CONTROL, val);
5719                 POSTING_READ(PCH_DREF_CONTROL);
5720                 udelay(200);
5721 
5722                 /* Turn off the SSC source */
5723                 val &= ~DREF_SSC_SOURCE_MASK;
5724                 val |= DREF_SSC_SOURCE_DISABLE;
5725 
5726                 /* Turn off SSC1 */
5727                 val &= ~DREF_SSC1_ENABLE;
5728 
5729                 I915_WRITE(PCH_DREF_CONTROL, val);
5730                 POSTING_READ(PCH_DREF_CONTROL);
5731                 udelay(200);
5732         }
5733 
5734         BUG_ON(val != final);
5735 }
5736 
5737 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5738 {
5739         uint32_t tmp;
5740 
5741         tmp = I915_READ(SOUTH_CHICKEN2);
5742         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5743         I915_WRITE(SOUTH_CHICKEN2, tmp);
5744 
5745         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5746                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5747                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5748 
5749         tmp = I915_READ(SOUTH_CHICKEN2);
5750         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5751         I915_WRITE(SOUTH_CHICKEN2, tmp);
5752 
5753         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5754                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5755                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5756 }
5757 
5758 /* WaMPhyProgramming:hsw */
5759 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5760 {
5761         uint32_t tmp;
5762 
5763         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5764         tmp &= ~(0xFF << 24);
5765         tmp |= (0x12 << 24);
5766         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5767 
5768         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5769         tmp |= (1 << 11);
5770         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5771 
5772         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5773         tmp |= (1 << 11);
5774         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5775 
5776         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5777         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5778         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5779 
5780         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5781         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5782         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5783 
5784         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5785         tmp &= ~(7 << 13);
5786         tmp |= (5 << 13);
5787         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5788 
5789         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5790         tmp &= ~(7 << 13);
5791         tmp |= (5 << 13);
5792         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5793 
5794         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5795         tmp &= ~0xFF;
5796         tmp |= 0x1C;
5797         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5798 
5799         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5800         tmp &= ~0xFF;
5801         tmp |= 0x1C;
5802         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5803 
5804         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5805         tmp &= ~(0xFF << 16);
5806         tmp |= (0x1C << 16);
5807         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5808 
5809         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5810         tmp &= ~(0xFF << 16);
5811         tmp |= (0x1C << 16);
5812         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5813 
5814         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5815         tmp |= (1 << 27);
5816         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5817 
5818         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5819         tmp |= (1 << 27);
5820         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5821 
5822         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5823         tmp &= ~(0xF << 28);
5824         tmp |= (4 << 28);
5825         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5826 
5827         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5828         tmp &= ~(0xF << 28);
5829         tmp |= (4 << 28);
5830         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5831 }
5832 
5833 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5834  * Programming" based on the parameters passed:
5835  * - Sequence to enable CLKOUT_DP
5836  * - Sequence to enable CLKOUT_DP without spread
5837  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5838  */
5839 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5840                                  bool with_fdi)
5841 {
5842         struct drm_i915_private *dev_priv = dev->dev_private;
5843         uint32_t reg, tmp;
5844 
5845         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5846                 with_spread = true;
5847         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5848                  with_fdi, "LP PCH doesn't have FDI\n"))
5849                 with_fdi = false;
5850 
5851         mutex_lock(&dev_priv->dpio_lock);
5852 
5853         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5854         tmp &= ~SBI_SSCCTL_DISABLE;
5855         tmp |= SBI_SSCCTL_PATHALT;
5856         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5857 
5858         udelay(24);
5859 
5860         if (with_spread) {
5861                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5862                 tmp &= ~SBI_SSCCTL_PATHALT;
5863                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5864 
5865                 if (with_fdi) {
5866                         lpt_reset_fdi_mphy(dev_priv);
5867                         lpt_program_fdi_mphy(dev_priv);
5868                 }
5869         }
5870 
5871         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5872                SBI_GEN0 : SBI_DBUFF0;
5873         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5874         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5875         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5876 
5877         mutex_unlock(&dev_priv->dpio_lock);
5878 }
5879 
5880 /* Sequence to disable CLKOUT_DP */
5881 static void lpt_disable_clkout_dp(struct drm_device *dev)
5882 {
5883         struct drm_i915_private *dev_priv = dev->dev_private;
5884         uint32_t reg, tmp;
5885 
5886         mutex_lock(&dev_priv->dpio_lock);
5887 
5888         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5889                SBI_GEN0 : SBI_DBUFF0;
5890         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5891         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5892         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5893 
5894         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5895         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5896                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5897                         tmp |= SBI_SSCCTL_PATHALT;
5898                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5899                         udelay(32);
5900                 }
5901                 tmp |= SBI_SSCCTL_DISABLE;
5902                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5903         }
5904 
5905         mutex_unlock(&dev_priv->dpio_lock);
5906 }
5907 
5908 static void lpt_init_pch_refclk(struct drm_device *dev)
5909 {
5910         struct drm_mode_config *mode_config = &dev->mode_config;
5911         struct intel_encoder *encoder;
5912         bool has_vga = false;
5913 
5914         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5915                 switch (encoder->type) {
5916                 case INTEL_OUTPUT_ANALOG:
5917                         has_vga = true;
5918                         break;
5919                 }
5920         }
5921 
5922         if (has_vga)
5923                 lpt_enable_clkout_dp(dev, true, true);
5924         else
5925                 lpt_disable_clkout_dp(dev);
5926 }
5927 
5928 /*
5929  * Initialize reference clocks when the driver loads
5930  */
5931 void intel_init_pch_refclk(struct drm_device *dev)
5932 {
5933         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5934                 ironlake_init_pch_refclk(dev);
5935         else if (HAS_PCH_LPT(dev))
5936                 lpt_init_pch_refclk(dev);
5937 }
5938 
5939 static int ironlake_get_refclk(struct drm_crtc *crtc)
5940 {
5941         struct drm_device *dev = crtc->dev;
5942         struct drm_i915_private *dev_priv = dev->dev_private;
5943         struct intel_encoder *encoder;
5944         int num_connectors = 0;
5945         bool is_lvds = false;
5946 
5947         for_each_encoder_on_crtc(dev, crtc, encoder) {
5948                 switch (encoder->type) {
5949                 case INTEL_OUTPUT_LVDS:
5950                         is_lvds = true;
5951                         break;
5952                 }
5953                 num_connectors++;
5954         }
5955 
5956         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5957                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5958                               dev_priv->vbt.lvds_ssc_freq);
5959                 return dev_priv->vbt.lvds_ssc_freq;
5960         }
5961 
5962         return 120000;
5963 }
5964 
5965 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5966 {
5967         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5969         int pipe = intel_crtc->pipe;
5970         uint32_t val;
5971 
5972         val = 0;
5973 
5974         switch (intel_crtc->config.pipe_bpp) {
5975         case 18:
5976                 val |= PIPECONF_6BPC;
5977                 break;
5978         case 24:
5979                 val |= PIPECONF_8BPC;
5980                 break;
5981         case 30:
5982                 val |= PIPECONF_10BPC;
5983                 break;
5984         case 36:
5985                 val |= PIPECONF_12BPC;
5986                 break;
5987         default:
5988                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5989                 BUG();
5990         }
5991 
5992         if (intel_crtc->config.dither)
5993                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5994 
5995         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5996                 val |= PIPECONF_INTERLACED_ILK;
5997         else
5998                 val |= PIPECONF_PROGRESSIVE;
5999 
6000         if (intel_crtc->config.limited_color_range)
6001                 val |= PIPECONF_COLOR_RANGE_SELECT;
6002 
6003         I915_WRITE(PIPECONF(pipe), val);
6004         POSTING_READ(PIPECONF(pipe));
6005 }
6006 
6007 /*
6008  * Set up the pipe CSC unit.
6009  *
6010  * Currently only full range RGB to limited range RGB conversion
6011  * is supported, but eventually this should handle various
6012  * RGB<->YCbCr scenarios as well.
6013  */
6014 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6015 {
6016         struct drm_device *dev = crtc->dev;
6017         struct drm_i915_private *dev_priv = dev->dev_private;
6018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6019         int pipe = intel_crtc->pipe;
6020         uint16_t coeff = 0x7800; /* 1.0 */
6021 
6022         /*
6023          * TODO: Check what kind of values actually come out of the pipe
6024          * with these coeff/postoff values and adjust to get the best
6025          * accuracy. Perhaps we even need to take the bpc value into
6026          * consideration.
6027          */
6028 
6029         if (intel_crtc->config.limited_color_range)
6030                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6031 
6032         /*
6033          * GY/GU and RY/RU should be the other way around according
6034          * to BSpec, but reality doesn't agree. Just set them up in
6035          * a way that results in the correct picture.
6036          */
6037         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6038         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6039 
6040         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6041         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6042 
6043         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6044         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6045 
6046         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6047         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6048         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6049 
6050         if (INTEL_INFO(dev)->gen > 6) {
6051                 uint16_t postoff = 0;
6052 
6053                 if (intel_crtc->config.limited_color_range)
6054                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6055 
6056                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6057                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6058                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6059 
6060                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6061         } else {
6062                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6063 
6064                 if (intel_crtc->config.limited_color_range)
6065                         mode |= CSC_BLACK_SCREEN_OFFSET;
6066 
6067                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6068         }
6069 }
6070 
6071 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6072 {
6073         struct drm_device *dev = crtc->dev;
6074         struct drm_i915_private *dev_priv = dev->dev_private;
6075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076         enum pipe pipe = intel_crtc->pipe;
6077         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6078         uint32_t val;
6079 
6080         val = 0;
6081 
6082         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6083                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6084 
6085         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6086                 val |= PIPECONF_INTERLACED_ILK;
6087         else
6088                 val |= PIPECONF_PROGRESSIVE;
6089 
6090         I915_WRITE(PIPECONF(cpu_transcoder), val);
6091         POSTING_READ(PIPECONF(cpu_transcoder));
6092 
6093         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6094         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6095 
6096         if (IS_BROADWELL(dev)) {
6097                 val = 0;
6098 
6099                 switch (intel_crtc->config.pipe_bpp) {
6100                 case 18:
6101                         val |= PIPEMISC_DITHER_6_BPC;
6102                         break;
6103                 case 24:
6104                         val |= PIPEMISC_DITHER_8_BPC;
6105                         break;
6106                 case 30:
6107                         val |= PIPEMISC_DITHER_10_BPC;
6108                         break;
6109                 case 36:
6110                         val |= PIPEMISC_DITHER_12_BPC;
6111                         break;
6112                 default:
6113                         /* Case prevented by pipe_config_set_bpp. */
6114                         BUG();
6115                 }
6116 
6117                 if (intel_crtc->config.dither)
6118                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6119 
6120                 I915_WRITE(PIPEMISC(pipe), val);
6121         }
6122 }
6123 
6124 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6125                                     intel_clock_t *clock,
6126                                     bool *has_reduced_clock,
6127                                     intel_clock_t *reduced_clock)
6128 {
6129         struct drm_device *dev = crtc->dev;
6130         struct drm_i915_private *dev_priv = dev->dev_private;
6131         struct intel_encoder *intel_encoder;
6132         int refclk;
6133         const intel_limit_t *limit;
6134         bool ret, is_lvds = false;
6135 
6136         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6137                 switch (intel_encoder->type) {
6138                 case INTEL_OUTPUT_LVDS:
6139                         is_lvds = true;
6140                         break;
6141                 }
6142         }
6143 
6144         refclk = ironlake_get_refclk(crtc);
6145 
6146         /*
6147          * Returns a set of divisors for the desired target clock with the given
6148          * refclk, or FALSE.  The returned values represent the clock equation:
6149          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6150          */
6151         limit = intel_limit(crtc, refclk);
6152         ret = dev_priv->display.find_dpll(limit, crtc,
6153                                           to_intel_crtc(crtc)->config.port_clock,
6154                                           refclk, NULL, clock);
6155         if (!ret)
6156                 return false;
6157 
6158         if (is_lvds && dev_priv->lvds_downclock_avail) {
6159                 /*
6160                  * Ensure we match the reduced clock's P to the target clock.
6161                  * If the clocks don't match, we can't switch the display clock
6162                  * by using the FP0/FP1. In such case we will disable the LVDS
6163                  * downclock feature.
6164                 */
6165                 *has_reduced_clock =
6166                         dev_priv->display.find_dpll(limit, crtc,
6167                                                     dev_priv->lvds_downclock,
6168                                                     refclk, clock,
6169                                                     reduced_clock);
6170         }
6171 
6172         return true;
6173 }
6174 
6175 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6176 {
6177         /*
6178          * Account for spread spectrum to avoid
6179          * oversubscribing the link. Max center spread
6180          * is 2.5%; use 5% for safety's sake.
6181          */
6182         u32 bps = target_clock * bpp * 21 / 20;
6183         return bps / (link_bw * 8) + 1;
6184 }
6185 
6186 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6187 {
6188         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6189 }
6190 
6191 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6192                                       u32 *fp,
6193                                       intel_clock_t *reduced_clock, u32 *fp2)
6194 {
6195         struct drm_crtc *crtc = &intel_crtc->base;
6196         struct drm_device *dev = crtc->dev;
6197         struct drm_i915_private *dev_priv = dev->dev_private;
6198         struct intel_encoder *intel_encoder;
6199         uint32_t dpll;
6200         int factor, num_connectors = 0;
6201         bool is_lvds = false, is_sdvo = false;
6202 
6203         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6204                 switch (intel_encoder->type) {
6205                 case INTEL_OUTPUT_LVDS:
6206                         is_lvds = true;
6207                         break;
6208                 case INTEL_OUTPUT_SDVO:
6209                 case INTEL_OUTPUT_HDMI:
6210                         is_sdvo = true;
6211                         break;
6212                 }
6213 
6214                 num_connectors++;
6215         }
6216 
6217         /* Enable autotuning of the PLL clock (if permissible) */
6218         factor = 21;
6219         if (is_lvds) {
6220                 if ((intel_panel_use_ssc(dev_priv) &&
6221                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6222                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6223                         factor = 25;
6224         } else if (intel_crtc->config.sdvo_tv_clock)
6225                 factor = 20;
6226 
6227         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6228                 *fp |= FP_CB_TUNE;
6229 
6230         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6231                 *fp2 |= FP_CB_TUNE;
6232 
6233         dpll = 0;
6234 
6235         if (is_lvds)
6236                 dpll |= DPLLB_MODE_LVDS;
6237         else
6238                 dpll |= DPLLB_MODE_DAC_SERIAL;
6239 
6240         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6241                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6242 
6243         if (is_sdvo)
6244                 dpll |= DPLL_SDVO_HIGH_SPEED;
6245         if (intel_crtc->config.has_dp_encoder)
6246                 dpll |= DPLL_SDVO_HIGH_SPEED;
6247 
6248         /* compute bitmask from p1 value */
6249         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6250         /* also FPA1 */
6251         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6252 
6253         switch (intel_crtc->config.dpll.p2) {
6254         case 5:
6255                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6256                 break;
6257         case 7:
6258                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6259                 break;
6260         case 10:
6261                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6262                 break;
6263         case 14:
6264                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6265                 break;
6266         }
6267 
6268         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6269                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6270         else
6271                 dpll |= PLL_REF_INPUT_DREFCLK;
6272 
6273         return dpll | DPLL_VCO_ENABLE;
6274 }
6275 
6276 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6277                                   int x, int y,
6278                                   struct drm_framebuffer *fb)
6279 {
6280         struct drm_device *dev = crtc->dev;
6281         struct drm_i915_private *dev_priv = dev->dev_private;
6282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6283         int pipe = intel_crtc->pipe;
6284         int plane = intel_crtc->plane;
6285         int num_connectors = 0;
6286         intel_clock_t clock, reduced_clock;
6287         u32 dpll = 0, fp = 0, fp2 = 0;
6288         bool ok, has_reduced_clock = false;
6289         bool is_lvds = false;
6290         struct intel_encoder *encoder;
6291         struct intel_shared_dpll *pll;
6292         int ret;
6293 
6294         for_each_encoder_on_crtc(dev, crtc, encoder) {
6295                 switch (encoder->type) {
6296                 case INTEL_OUTPUT_LVDS:
6297                         is_lvds = true;
6298                         break;
6299                 }
6300 
6301                 num_connectors++;
6302         }
6303 
6304         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6305              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6306 
6307         ok = ironlake_compute_clocks(crtc, &clock,
6308                                      &has_reduced_clock, &reduced_clock);
6309         if (!ok && !intel_crtc->config.clock_set) {
6310                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6311                 return -EINVAL;
6312         }
6313         /* Compat-code for transition, will disappear. */
6314         if (!intel_crtc->config.clock_set) {
6315                 intel_crtc->config.dpll.n = clock.n;
6316                 intel_crtc->config.dpll.m1 = clock.m1;
6317                 intel_crtc->config.dpll.m2 = clock.m2;
6318                 intel_crtc->config.dpll.p1 = clock.p1;
6319                 intel_crtc->config.dpll.p2 = clock.p2;
6320         }
6321 
6322         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6323         if (intel_crtc->config.has_pch_encoder) {
6324                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6325                 if (has_reduced_clock)
6326                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6327 
6328                 dpll = ironlake_compute_dpll(intel_crtc,
6329                                              &fp, &reduced_clock,
6330                                              has_reduced_clock ? &fp2 : NULL);
6331 
6332                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6333                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6334                 if (has_reduced_clock)
6335                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6336                 else
6337                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6338 
6339                 pll = intel_get_shared_dpll(intel_crtc);
6340                 if (pll == NULL) {
6341                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6342                                          pipe_name(pipe));
6343                         return -EINVAL;
6344                 }
6345         } else
6346                 intel_put_shared_dpll(intel_crtc);
6347 
6348         if (intel_crtc->config.has_dp_encoder)
6349                 intel_dp_set_m_n(intel_crtc);
6350 
6351         if (is_lvds && has_reduced_clock && i915_powersave)
6352                 intel_crtc->lowfreq_avail = true;
6353         else
6354                 intel_crtc->lowfreq_avail = false;
6355 
6356         intel_set_pipe_timings(intel_crtc);
6357 
6358         if (intel_crtc->config.has_pch_encoder) {
6359                 intel_cpu_transcoder_set_m_n(intel_crtc,
6360                                              &intel_crtc->config.fdi_m_n);
6361         }
6362 
6363         ironlake_set_pipeconf(crtc);
6364 
6365         /* Set up the display plane register */
6366         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6367         POSTING_READ(DSPCNTR(plane));
6368 
6369         ret = intel_pipe_set_base(crtc, x, y, fb);
6370 
6371         return ret;
6372 }
6373 
6374 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6375                                          struct intel_link_m_n *m_n)
6376 {
6377         struct drm_device *dev = crtc->base.dev;
6378         struct drm_i915_private *dev_priv = dev->dev_private;
6379         enum pipe pipe = crtc->pipe;
6380 
6381         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6382         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6383         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6384                 & ~TU_SIZE_MASK;
6385         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6386         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6387                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6388 }
6389 
6390 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6391                                          enum transcoder transcoder,
6392                                          struct intel_link_m_n *m_n)
6393 {
6394         struct drm_device *dev = crtc->base.dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         enum pipe pipe = crtc->pipe;
6397 
6398         if (INTEL_INFO(dev)->gen >= 5) {
6399                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6400                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6401                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6402                         & ~TU_SIZE_MASK;
6403                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6404                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6405                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6406         } else {
6407                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6408                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6409                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6410                         & ~TU_SIZE_MASK;
6411                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6412                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6413                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6414         }
6415 }
6416 
6417 void intel_dp_get_m_n(struct intel_crtc *crtc,
6418                       struct intel_crtc_config *pipe_config)
6419 {
6420         if (crtc->config.has_pch_encoder)
6421                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6422         else
6423                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6424                                              &pipe_config->dp_m_n);
6425 }
6426 
6427 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6428                                         struct intel_crtc_config *pipe_config)
6429 {
6430         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6431                                      &pipe_config->fdi_m_n);
6432 }
6433 
6434 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6435                                      struct intel_crtc_config *pipe_config)
6436 {
6437         struct drm_device *dev = crtc->base.dev;
6438         struct drm_i915_private *dev_priv = dev