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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_gem_dmabuf.h"
 40 #include "intel_dsi.h"
 41 #include "i915_trace.h"
 42 #include <drm/drm_atomic.h>
 43 #include <drm/drm_atomic_helper.h>
 44 #include <drm/drm_dp_helper.h>
 45 #include <drm/drm_crtc_helper.h>
 46 #include <drm/drm_plane_helper.h>
 47 #include <drm/drm_rect.h>
 48 #include <linux/dma_remapping.h>
 49 #include <linux/reservation.h>
 50 
 51 static bool is_mmio_work(struct intel_flip_work *work)
 52 {
 53         return work->mmio_work.func;
 54 }
 55 
 56 /* Primary plane formats for gen <= 3 */
 57 static const uint32_t i8xx_primary_formats[] = {
 58         DRM_FORMAT_C8,
 59         DRM_FORMAT_RGB565,
 60         DRM_FORMAT_XRGB1555,
 61         DRM_FORMAT_XRGB8888,
 62 };
 63 
 64 /* Primary plane formats for gen >= 4 */
 65 static const uint32_t i965_primary_formats[] = {
 66         DRM_FORMAT_C8,
 67         DRM_FORMAT_RGB565,
 68         DRM_FORMAT_XRGB8888,
 69         DRM_FORMAT_XBGR8888,
 70         DRM_FORMAT_XRGB2101010,
 71         DRM_FORMAT_XBGR2101010,
 72 };
 73 
 74 static const uint32_t skl_primary_formats[] = {
 75         DRM_FORMAT_C8,
 76         DRM_FORMAT_RGB565,
 77         DRM_FORMAT_XRGB8888,
 78         DRM_FORMAT_XBGR8888,
 79         DRM_FORMAT_ARGB8888,
 80         DRM_FORMAT_ABGR8888,
 81         DRM_FORMAT_XRGB2101010,
 82         DRM_FORMAT_XBGR2101010,
 83         DRM_FORMAT_YUYV,
 84         DRM_FORMAT_YVYU,
 85         DRM_FORMAT_UYVY,
 86         DRM_FORMAT_VYUY,
 87 };
 88 
 89 /* Cursor formats */
 90 static const uint32_t intel_cursor_formats[] = {
 91         DRM_FORMAT_ARGB8888,
 92 };
 93 
 94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 95                                 struct intel_crtc_state *pipe_config);
 96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 97                                    struct intel_crtc_state *pipe_config);
 98 
 99 static int intel_framebuffer_init(struct drm_device *dev,
100                                   struct intel_framebuffer *ifb,
101                                   struct drm_mode_fb_cmd2 *mode_cmd,
102                                   struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107                                          struct intel_link_m_n *m_n,
108                                          struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113                             const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115                             const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119         struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int bxt_calc_cdclk(int max_pixclk);
127 
128 struct intel_limit {
129         struct {
130                 int min, max;
131         } dot, vco, n, m, m1, m2, p, p1;
132 
133         struct {
134                 int dot_limit;
135                 int p2_slow, p2_fast;
136         } p2;
137 };
138 
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143 
144         /* Obtain SKU information */
145         mutex_lock(&dev_priv->sb_lock);
146         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147                 CCK_FUSE_HPLL_FREQ_MASK;
148         mutex_unlock(&dev_priv->sb_lock);
149 
150         return vco_freq[hpll_freq] * 1000;
151 }
152 
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154                       const char *name, u32 reg, int ref_freq)
155 {
156         u32 val;
157         int divider;
158 
159         mutex_lock(&dev_priv->sb_lock);
160         val = vlv_cck_read(dev_priv, reg);
161         mutex_unlock(&dev_priv->sb_lock);
162 
163         divider = val & CCK_FREQUENCY_VALUES;
164 
165         WARN((val & CCK_FREQUENCY_STATUS) !=
166              (divider << CCK_FREQUENCY_STATUS_SHIFT),
167              "%s change in progress\n", name);
168 
169         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171 
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173                                   const char *name, u32 reg)
174 {
175         if (dev_priv->hpll_freq == 0)
176                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177 
178         return vlv_get_cck_clock(dev_priv, name, reg,
179                                  dev_priv->hpll_freq);
180 }
181 
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187 
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191         /* RAWCLK_FREQ_VLV register updated from power well code */
192         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195 
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199         uint32_t clkcfg;
200 
201         /* hrawclock is 1/4 the FSB frequency */
202         clkcfg = I915_READ(CLKCFG);
203         switch (clkcfg & CLKCFG_FSB_MASK) {
204         case CLKCFG_FSB_400:
205                 return 100000;
206         case CLKCFG_FSB_533:
207                 return 133333;
208         case CLKCFG_FSB_667:
209                 return 166667;
210         case CLKCFG_FSB_800:
211                 return 200000;
212         case CLKCFG_FSB_1067:
213                 return 266667;
214         case CLKCFG_FSB_1333:
215                 return 333333;
216         /* these two are just a guess; one of them might be right */
217         case CLKCFG_FSB_1600:
218         case CLKCFG_FSB_1600_ALT:
219                 return 400000;
220         default:
221                 return 133333;
222         }
223 }
224 
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227         if (HAS_PCH_SPLIT(dev_priv))
228                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233         else
234                 return; /* no rawclk on other platforms, or no need to know it */
235 
236         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238 
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242                 return;
243 
244         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245                                                       CCK_CZ_CLOCK_CONTROL);
246 
247         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249 
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252                     const struct intel_crtc_state *pipe_config)
253 {
254         if (HAS_DDI(dev_priv))
255                 return pipe_config->port_clock; /* SPLL */
256         else if (IS_GEN5(dev_priv))
257                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258         else
259                 return 270000;
260 }
261 
262 static const struct intel_limit intel_limits_i8xx_dac = {
263         .dot = { .min = 25000, .max = 350000 },
264         .vco = { .min = 908000, .max = 1512000 },
265         .n = { .min = 2, .max = 16 },
266         .m = { .min = 96, .max = 140 },
267         .m1 = { .min = 18, .max = 26 },
268         .m2 = { .min = 6, .max = 16 },
269         .p = { .min = 4, .max = 128 },
270         .p1 = { .min = 2, .max = 33 },
271         .p2 = { .dot_limit = 165000,
272                 .p2_slow = 4, .p2_fast = 2 },
273 };
274 
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276         .dot = { .min = 25000, .max = 350000 },
277         .vco = { .min = 908000, .max = 1512000 },
278         .n = { .min = 2, .max = 16 },
279         .m = { .min = 96, .max = 140 },
280         .m1 = { .min = 18, .max = 26 },
281         .m2 = { .min = 6, .max = 16 },
282         .p = { .min = 4, .max = 128 },
283         .p1 = { .min = 2, .max = 33 },
284         .p2 = { .dot_limit = 165000,
285                 .p2_slow = 4, .p2_fast = 4 },
286 };
287 
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289         .dot = { .min = 25000, .max = 350000 },
290         .vco = { .min = 908000, .max = 1512000 },
291         .n = { .min = 2, .max = 16 },
292         .m = { .min = 96, .max = 140 },
293         .m1 = { .min = 18, .max = 26 },
294         .m2 = { .min = 6, .max = 16 },
295         .p = { .min = 4, .max = 128 },
296         .p1 = { .min = 1, .max = 6 },
297         .p2 = { .dot_limit = 165000,
298                 .p2_slow = 14, .p2_fast = 7 },
299 };
300 
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302         .dot = { .min = 20000, .max = 400000 },
303         .vco = { .min = 1400000, .max = 2800000 },
304         .n = { .min = 1, .max = 6 },
305         .m = { .min = 70, .max = 120 },
306         .m1 = { .min = 8, .max = 18 },
307         .m2 = { .min = 3, .max = 7 },
308         .p = { .min = 5, .max = 80 },
309         .p1 = { .min = 1, .max = 8 },
310         .p2 = { .dot_limit = 200000,
311                 .p2_slow = 10, .p2_fast = 5 },
312 };
313 
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315         .dot = { .min = 20000, .max = 400000 },
316         .vco = { .min = 1400000, .max = 2800000 },
317         .n = { .min = 1, .max = 6 },
318         .m = { .min = 70, .max = 120 },
319         .m1 = { .min = 8, .max = 18 },
320         .m2 = { .min = 3, .max = 7 },
321         .p = { .min = 7, .max = 98 },
322         .p1 = { .min = 1, .max = 8 },
323         .p2 = { .dot_limit = 112000,
324                 .p2_slow = 14, .p2_fast = 7 },
325 };
326 
327 
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329         .dot = { .min = 25000, .max = 270000 },
330         .vco = { .min = 1750000, .max = 3500000},
331         .n = { .min = 1, .max = 4 },
332         .m = { .min = 104, .max = 138 },
333         .m1 = { .min = 17, .max = 23 },
334         .m2 = { .min = 5, .max = 11 },
335         .p = { .min = 10, .max = 30 },
336         .p1 = { .min = 1, .max = 3},
337         .p2 = { .dot_limit = 270000,
338                 .p2_slow = 10,
339                 .p2_fast = 10
340         },
341 };
342 
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344         .dot = { .min = 22000, .max = 400000 },
345         .vco = { .min = 1750000, .max = 3500000},
346         .n = { .min = 1, .max = 4 },
347         .m = { .min = 104, .max = 138 },
348         .m1 = { .min = 16, .max = 23 },
349         .m2 = { .min = 5, .max = 11 },
350         .p = { .min = 5, .max = 80 },
351         .p1 = { .min = 1, .max = 8},
352         .p2 = { .dot_limit = 165000,
353                 .p2_slow = 10, .p2_fast = 5 },
354 };
355 
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357         .dot = { .min = 20000, .max = 115000 },
358         .vco = { .min = 1750000, .max = 3500000 },
359         .n = { .min = 1, .max = 3 },
360         .m = { .min = 104, .max = 138 },
361         .m1 = { .min = 17, .max = 23 },
362         .m2 = { .min = 5, .max = 11 },
363         .p = { .min = 28, .max = 112 },
364         .p1 = { .min = 2, .max = 8 },
365         .p2 = { .dot_limit = 0,
366                 .p2_slow = 14, .p2_fast = 14
367         },
368 };
369 
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371         .dot = { .min = 80000, .max = 224000 },
372         .vco = { .min = 1750000, .max = 3500000 },
373         .n = { .min = 1, .max = 3 },
374         .m = { .min = 104, .max = 138 },
375         .m1 = { .min = 17, .max = 23 },
376         .m2 = { .min = 5, .max = 11 },
377         .p = { .min = 14, .max = 42 },
378         .p1 = { .min = 2, .max = 6 },
379         .p2 = { .dot_limit = 0,
380                 .p2_slow = 7, .p2_fast = 7
381         },
382 };
383 
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385         .dot = { .min = 20000, .max = 400000},
386         .vco = { .min = 1700000, .max = 3500000 },
387         /* Pineview's Ncounter is a ring counter */
388         .n = { .min = 3, .max = 6 },
389         .m = { .min = 2, .max = 256 },
390         /* Pineview only has one combined m divider, which we treat as m2. */
391         .m1 = { .min = 0, .max = 0 },
392         .m2 = { .min = 0, .max = 254 },
393         .p = { .min = 5, .max = 80 },
394         .p1 = { .min = 1, .max = 8 },
395         .p2 = { .dot_limit = 200000,
396                 .p2_slow = 10, .p2_fast = 5 },
397 };
398 
399 static const struct intel_limit intel_limits_pineview_lvds = {
400         .dot = { .min = 20000, .max = 400000 },
401         .vco = { .min = 1700000, .max = 3500000 },
402         .n = { .min = 3, .max = 6 },
403         .m = { .min = 2, .max = 256 },
404         .m1 = { .min = 0, .max = 0 },
405         .m2 = { .min = 0, .max = 254 },
406         .p = { .min = 7, .max = 112 },
407         .p1 = { .min = 1, .max = 8 },
408         .p2 = { .dot_limit = 112000,
409                 .p2_slow = 14, .p2_fast = 14 },
410 };
411 
412 /* Ironlake / Sandybridge
413  *
414  * We calculate clock using (register_value + 2) for N/M1/M2, so here
415  * the range value for them is (actual_value - 2).
416  */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418         .dot = { .min = 25000, .max = 350000 },
419         .vco = { .min = 1760000, .max = 3510000 },
420         .n = { .min = 1, .max = 5 },
421         .m = { .min = 79, .max = 127 },
422         .m1 = { .min = 12, .max = 22 },
423         .m2 = { .min = 5, .max = 9 },
424         .p = { .min = 5, .max = 80 },
425         .p1 = { .min = 1, .max = 8 },
426         .p2 = { .dot_limit = 225000,
427                 .p2_slow = 10, .p2_fast = 5 },
428 };
429 
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431         .dot = { .min = 25000, .max = 350000 },
432         .vco = { .min = 1760000, .max = 3510000 },
433         .n = { .min = 1, .max = 3 },
434         .m = { .min = 79, .max = 118 },
435         .m1 = { .min = 12, .max = 22 },
436         .m2 = { .min = 5, .max = 9 },
437         .p = { .min = 28, .max = 112 },
438         .p1 = { .min = 2, .max = 8 },
439         .p2 = { .dot_limit = 225000,
440                 .p2_slow = 14, .p2_fast = 14 },
441 };
442 
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444         .dot = { .min = 25000, .max = 350000 },
445         .vco = { .min = 1760000, .max = 3510000 },
446         .n = { .min = 1, .max = 3 },
447         .m = { .min = 79, .max = 127 },
448         .m1 = { .min = 12, .max = 22 },
449         .m2 = { .min = 5, .max = 9 },
450         .p = { .min = 14, .max = 56 },
451         .p1 = { .min = 2, .max = 8 },
452         .p2 = { .dot_limit = 225000,
453                 .p2_slow = 7, .p2_fast = 7 },
454 };
455 
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458         .dot = { .min = 25000, .max = 350000 },
459         .vco = { .min = 1760000, .max = 3510000 },
460         .n = { .min = 1, .max = 2 },
461         .m = { .min = 79, .max = 126 },
462         .m1 = { .min = 12, .max = 22 },
463         .m2 = { .min = 5, .max = 9 },
464         .p = { .min = 28, .max = 112 },
465         .p1 = { .min = 2, .max = 8 },
466         .p2 = { .dot_limit = 225000,
467                 .p2_slow = 14, .p2_fast = 14 },
468 };
469 
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471         .dot = { .min = 25000, .max = 350000 },
472         .vco = { .min = 1760000, .max = 3510000 },
473         .n = { .min = 1, .max = 3 },
474         .m = { .min = 79, .max = 126 },
475         .m1 = { .min = 12, .max = 22 },
476         .m2 = { .min = 5, .max = 9 },
477         .p = { .min = 14, .max = 42 },
478         .p1 = { .min = 2, .max = 6 },
479         .p2 = { .dot_limit = 225000,
480                 .p2_slow = 7, .p2_fast = 7 },
481 };
482 
483 static const struct intel_limit intel_limits_vlv = {
484          /*
485           * These are the data rate limits (measured in fast clocks)
486           * since those are the strictest limits we have. The fast
487           * clock and actual rate limits are more relaxed, so checking
488           * them would make no difference.
489           */
490         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491         .vco = { .min = 4000000, .max = 6000000 },
492         .n = { .min = 1, .max = 7 },
493         .m1 = { .min = 2, .max = 3 },
494         .m2 = { .min = 11, .max = 156 },
495         .p1 = { .min = 2, .max = 3 },
496         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498 
499 static const struct intel_limit intel_limits_chv = {
500         /*
501          * These are the data rate limits (measured in fast clocks)
502          * since those are the strictest limits we have.  The fast
503          * clock and actual rate limits are more relaxed, so checking
504          * them would make no difference.
505          */
506         .dot = { .min = 25000 * 5, .max = 540000 * 5},
507         .vco = { .min = 4800000, .max = 6480000 },
508         .n = { .min = 1, .max = 1 },
509         .m1 = { .min = 2, .max = 2 },
510         .m2 = { .min = 24 << 22, .max = 175 << 22 },
511         .p1 = { .min = 2, .max = 4 },
512         .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514 
515 static const struct intel_limit intel_limits_bxt = {
516         /* FIXME: find real dot limits */
517         .dot = { .min = 0, .max = INT_MAX },
518         .vco = { .min = 4800000, .max = 6700000 },
519         .n = { .min = 1, .max = 1 },
520         .m1 = { .min = 2, .max = 2 },
521         /* FIXME: find real m2 limits */
522         .m2 = { .min = 2 << 22, .max = 255 << 22 },
523         .p1 = { .min = 2, .max = 4 },
524         .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526 
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530         return drm_atomic_crtc_needs_modeset(state);
531 }
532 
533 /*
534  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
535  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
536  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
537  * The helpers' return value is the rate of the clock that is fed to the
538  * display engine's pipe which can be the above fast dot clock rate or a
539  * divided-down version of it.
540  */
541 /* m1 is reserved as 0 in Pineview, n is a ring counter */
542 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
543 {
544         clock->m = clock->m2 + 2;
545         clock->p = clock->p1 * clock->p2;
546         if (WARN_ON(clock->n == 0 || clock->p == 0))
547                 return 0;
548         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
549         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
550 
551         return clock->dot;
552 }
553 
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555 {
556         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557 }
558 
559 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
560 {
561         clock->m = i9xx_dpll_compute_m(clock);
562         clock->p = clock->p1 * clock->p2;
563         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564                 return 0;
565         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
567 
568         return clock->dot;
569 }
570 
571 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
572 {
573         clock->m = clock->m1 * clock->m2;
574         clock->p = clock->p1 * clock->p2;
575         if (WARN_ON(clock->n == 0 || clock->p == 0))
576                 return 0;
577         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
578         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
579 
580         return clock->dot / 5;
581 }
582 
583 int chv_calc_dpll_params(int refclk, struct dpll *clock)
584 {
585         clock->m = clock->m1 * clock->m2;
586         clock->p = clock->p1 * clock->p2;
587         if (WARN_ON(clock->n == 0 || clock->p == 0))
588                 return 0;
589         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
590                         clock->n << 22);
591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592 
593         return clock->dot / 5;
594 }
595 
596 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598  * Returns whether the given set of divisors are valid for a given refclk with
599  * the given connectors.
600  */
601 
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603                                const struct intel_limit *limit,
604                                const struct dpll *clock)
605 {
606         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
607                 INTELPllInvalid("n out of range\n");
608         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
609                 INTELPllInvalid("p1 out of range\n");
610         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
611                 INTELPllInvalid("m2 out of range\n");
612         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
613                 INTELPllInvalid("m1 out of range\n");
614 
615         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
616             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
617                 if (clock->m1 <= clock->m2)
618                         INTELPllInvalid("m1 <= m2\n");
619 
620         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
621                 if (clock->p < limit->p.min || limit->p.max < clock->p)
622                         INTELPllInvalid("p out of range\n");
623                 if (clock->m < limit->m.min || limit->m.max < clock->m)
624                         INTELPllInvalid("m out of range\n");
625         }
626 
627         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628                 INTELPllInvalid("vco out of range\n");
629         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630          * connector, etc., rather than just a single range.
631          */
632         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633                 INTELPllInvalid("dot out of range\n");
634 
635         return true;
636 }
637 
638 static int
639 i9xx_select_p2_div(const struct intel_limit *limit,
640                    const struct intel_crtc_state *crtc_state,
641                    int target)
642 {
643         struct drm_device *dev = crtc_state->base.crtc->dev;
644 
645         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
646                 /*
647                  * For LVDS just rely on its current settings for dual-channel.
648                  * We haven't figured out how to reliably set up different
649                  * single/dual channel state, if we even can.
650                  */
651                 if (intel_is_dual_link_lvds(dev))
652                         return limit->p2.p2_fast;
653                 else
654                         return limit->p2.p2_slow;
655         } else {
656                 if (target < limit->p2.dot_limit)
657                         return limit->p2.p2_slow;
658                 else
659                         return limit->p2.p2_fast;
660         }
661 }
662 
663 /*
664  * Returns a set of divisors for the desired target clock with the given
665  * refclk, or FALSE.  The returned values represent the clock equation:
666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667  *
668  * Target and reference clocks are specified in kHz.
669  *
670  * If match_clock is provided, then best_clock P divider must match the P
671  * divider from @match_clock used for LVDS downclocking.
672  */
673 static bool
674 i9xx_find_best_dpll(const struct intel_limit *limit,
675                     struct intel_crtc_state *crtc_state,
676                     int target, int refclk, struct dpll *match_clock,
677                     struct dpll *best_clock)
678 {
679         struct drm_device *dev = crtc_state->base.crtc->dev;
680         struct dpll clock;
681         int err = target;
682 
683         memset(best_clock, 0, sizeof(*best_clock));
684 
685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686 
687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688              clock.m1++) {
689                 for (clock.m2 = limit->m2.min;
690                      clock.m2 <= limit->m2.max; clock.m2++) {
691                         if (clock.m2 >= clock.m1)
692                                 break;
693                         for (clock.n = limit->n.min;
694                              clock.n <= limit->n.max; clock.n++) {
695                                 for (clock.p1 = limit->p1.min;
696                                         clock.p1 <= limit->p1.max; clock.p1++) {
697                                         int this_err;
698 
699                                         i9xx_calc_dpll_params(refclk, &clock);
700                                         if (!intel_PLL_is_valid(dev, limit,
701                                                                 &clock))
702                                                 continue;
703                                         if (match_clock &&
704                                             clock.p != match_clock->p)
705                                                 continue;
706 
707                                         this_err = abs(clock.dot - target);
708                                         if (this_err < err) {
709                                                 *best_clock = clock;
710                                                 err = this_err;
711                                         }
712                                 }
713                         }
714                 }
715         }
716 
717         return (err != target);
718 }
719 
720 /*
721  * Returns a set of divisors for the desired target clock with the given
722  * refclk, or FALSE.  The returned values represent the clock equation:
723  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724  *
725  * Target and reference clocks are specified in kHz.
726  *
727  * If match_clock is provided, then best_clock P divider must match the P
728  * divider from @match_clock used for LVDS downclocking.
729  */
730 static bool
731 pnv_find_best_dpll(const struct intel_limit *limit,
732                    struct intel_crtc_state *crtc_state,
733                    int target, int refclk, struct dpll *match_clock,
734                    struct dpll *best_clock)
735 {
736         struct drm_device *dev = crtc_state->base.crtc->dev;
737         struct dpll clock;
738         int err = target;
739 
740         memset(best_clock, 0, sizeof(*best_clock));
741 
742         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
743 
744         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
745              clock.m1++) {
746                 for (clock.m2 = limit->m2.min;
747                      clock.m2 <= limit->m2.max; clock.m2++) {
748                         for (clock.n = limit->n.min;
749                              clock.n <= limit->n.max; clock.n++) {
750                                 for (clock.p1 = limit->p1.min;
751                                         clock.p1 <= limit->p1.max; clock.p1++) {
752                                         int this_err;
753 
754                                         pnv_calc_dpll_params(refclk, &clock);
755                                         if (!intel_PLL_is_valid(dev, limit,
756                                                                 &clock))
757                                                 continue;
758                                         if (match_clock &&
759                                             clock.p != match_clock->p)
760                                                 continue;
761 
762                                         this_err = abs(clock.dot - target);
763                                         if (this_err < err) {
764                                                 *best_clock = clock;
765                                                 err = this_err;
766                                         }
767                                 }
768                         }
769                 }
770         }
771 
772         return (err != target);
773 }
774 
775 /*
776  * Returns a set of divisors for the desired target clock with the given
777  * refclk, or FALSE.  The returned values represent the clock equation:
778  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
779  *
780  * Target and reference clocks are specified in kHz.
781  *
782  * If match_clock is provided, then best_clock P divider must match the P
783  * divider from @match_clock used for LVDS downclocking.
784  */
785 static bool
786 g4x_find_best_dpll(const struct intel_limit *limit,
787                    struct intel_crtc_state *crtc_state,
788                    int target, int refclk, struct dpll *match_clock,
789                    struct dpll *best_clock)
790 {
791         struct drm_device *dev = crtc_state->base.crtc->dev;
792         struct dpll clock;
793         int max_n;
794         bool found = false;
795         /* approximately equals target * 0.00585 */
796         int err_most = (target >> 8) + (target >> 9);
797 
798         memset(best_clock, 0, sizeof(*best_clock));
799 
800         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
801 
802         max_n = limit->n.max;
803         /* based on hardware requirement, prefer smaller n to precision */
804         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
805                 /* based on hardware requirement, prefere larger m1,m2 */
806                 for (clock.m1 = limit->m1.max;
807                      clock.m1 >= limit->m1.min; clock.m1--) {
808                         for (clock.m2 = limit->m2.max;
809                              clock.m2 >= limit->m2.min; clock.m2--) {
810                                 for (clock.p1 = limit->p1.max;
811                                      clock.p1 >= limit->p1.min; clock.p1--) {
812                                         int this_err;
813 
814                                         i9xx_calc_dpll_params(refclk, &clock);
815                                         if (!intel_PLL_is_valid(dev, limit,
816                                                                 &clock))
817                                                 continue;
818 
819                                         this_err = abs(clock.dot - target);
820                                         if (this_err < err_most) {
821                                                 *best_clock = clock;
822                                                 err_most = this_err;
823                                                 max_n = clock.n;
824                                                 found = true;
825                                         }
826                                 }
827                         }
828                 }
829         }
830         return found;
831 }
832 
833 /*
834  * Check if the calculated PLL configuration is more optimal compared to the
835  * best configuration and error found so far. Return the calculated error.
836  */
837 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
838                                const struct dpll *calculated_clock,
839                                const struct dpll *best_clock,
840                                unsigned int best_error_ppm,
841                                unsigned int *error_ppm)
842 {
843         /*
844          * For CHV ignore the error and consider only the P value.
845          * Prefer a bigger P value based on HW requirements.
846          */
847         if (IS_CHERRYVIEW(dev)) {
848                 *error_ppm = 0;
849 
850                 return calculated_clock->p > best_clock->p;
851         }
852 
853         if (WARN_ON_ONCE(!target_freq))
854                 return false;
855 
856         *error_ppm = div_u64(1000000ULL *
857                                 abs(target_freq - calculated_clock->dot),
858                              target_freq);
859         /*
860          * Prefer a better P value over a better (smaller) error if the error
861          * is small. Ensure this preference for future configurations too by
862          * setting the error to 0.
863          */
864         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
865                 *error_ppm = 0;
866 
867                 return true;
868         }
869 
870         return *error_ppm + 10 < best_error_ppm;
871 }
872 
873 /*
874  * Returns a set of divisors for the desired target clock with the given
875  * refclk, or FALSE.  The returned values represent the clock equation:
876  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
877  */
878 static bool
879 vlv_find_best_dpll(const struct intel_limit *limit,
880                    struct intel_crtc_state *crtc_state,
881                    int target, int refclk, struct dpll *match_clock,
882                    struct dpll *best_clock)
883 {
884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
885         struct drm_device *dev = crtc->base.dev;
886         struct dpll clock;
887         unsigned int bestppm = 1000000;
888         /* min update 19.2 MHz */
889         int max_n = min(limit->n.max, refclk / 19200);
890         bool found = false;
891 
892         target *= 5; /* fast clock */
893 
894         memset(best_clock, 0, sizeof(*best_clock));
895 
896         /* based on hardware requirement, prefer smaller n to precision */
897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
898                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
899                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
900                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
901                                 clock.p = clock.p1 * clock.p2;
902                                 /* based on hardware requirement, prefer bigger m1,m2 values */
903                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
904                                         unsigned int ppm;
905 
906                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
907                                                                      refclk * clock.m1);
908 
909                                         vlv_calc_dpll_params(refclk, &clock);
910 
911                                         if (!intel_PLL_is_valid(dev, limit,
912                                                                 &clock))
913                                                 continue;
914 
915                                         if (!vlv_PLL_is_optimal(dev, target,
916                                                                 &clock,
917                                                                 best_clock,
918                                                                 bestppm, &ppm))
919                                                 continue;
920 
921                                         *best_clock = clock;
922                                         bestppm = ppm;
923                                         found = true;
924                                 }
925                         }
926                 }
927         }
928 
929         return found;
930 }
931 
932 /*
933  * Returns a set of divisors for the desired target clock with the given
934  * refclk, or FALSE.  The returned values represent the clock equation:
935  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
936  */
937 static bool
938 chv_find_best_dpll(const struct intel_limit *limit,
939                    struct intel_crtc_state *crtc_state,
940                    int target, int refclk, struct dpll *match_clock,
941                    struct dpll *best_clock)
942 {
943         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
944         struct drm_device *dev = crtc->base.dev;
945         unsigned int best_error_ppm;
946         struct dpll clock;
947         uint64_t m2;
948         int found = false;
949 
950         memset(best_clock, 0, sizeof(*best_clock));
951         best_error_ppm = 1000000;
952 
953         /*
954          * Based on hardware doc, the n always set to 1, and m1 always
955          * set to 2.  If requires to support 200Mhz refclk, we need to
956          * revisit this because n may not 1 anymore.
957          */
958         clock.n = 1, clock.m1 = 2;
959         target *= 5;    /* fast clock */
960 
961         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
962                 for (clock.p2 = limit->p2.p2_fast;
963                                 clock.p2 >= limit->p2.p2_slow;
964                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
965                         unsigned int error_ppm;
966 
967                         clock.p = clock.p1 * clock.p2;
968 
969                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
970                                         clock.n) << 22, refclk * clock.m1);
971 
972                         if (m2 > INT_MAX/clock.m1)
973                                 continue;
974 
975                         clock.m2 = m2;
976 
977                         chv_calc_dpll_params(refclk, &clock);
978 
979                         if (!intel_PLL_is_valid(dev, limit, &clock))
980                                 continue;
981 
982                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
983                                                 best_error_ppm, &error_ppm))
984                                 continue;
985 
986                         *best_clock = clock;
987                         best_error_ppm = error_ppm;
988                         found = true;
989                 }
990         }
991 
992         return found;
993 }
994 
995 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
996                         struct dpll *best_clock)
997 {
998         int refclk = 100000;
999         const struct intel_limit *limit = &intel_limits_bxt;
1000 
1001         return chv_find_best_dpll(limit, crtc_state,
1002                                   target_clock, refclk, NULL, best_clock);
1003 }
1004 
1005 bool intel_crtc_active(struct drm_crtc *crtc)
1006 {
1007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008 
1009         /* Be paranoid as we can arrive here with only partial
1010          * state retrieved from the hardware during setup.
1011          *
1012          * We can ditch the adjusted_mode.crtc_clock check as soon
1013          * as Haswell has gained clock readout/fastboot support.
1014          *
1015          * We can ditch the crtc->primary->fb check as soon as we can
1016          * properly reconstruct framebuffers.
1017          *
1018          * FIXME: The intel_crtc->active here should be switched to
1019          * crtc->state->active once we have proper CRTC states wired up
1020          * for atomic.
1021          */
1022         return intel_crtc->active && crtc->primary->state->fb &&
1023                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1024 }
1025 
1026 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1027                                              enum pipe pipe)
1028 {
1029         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1031 
1032         return intel_crtc->config->cpu_transcoder;
1033 }
1034 
1035 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(dev);
1038         i915_reg_t reg = PIPEDSL(pipe);
1039         u32 line1, line2;
1040         u32 line_mask;
1041 
1042         if (IS_GEN2(dev))
1043                 line_mask = DSL_LINEMASK_GEN2;
1044         else
1045                 line_mask = DSL_LINEMASK_GEN3;
1046 
1047         line1 = I915_READ(reg) & line_mask;
1048         msleep(5);
1049         line2 = I915_READ(reg) & line_mask;
1050 
1051         return line1 == line2;
1052 }
1053 
1054 /*
1055  * intel_wait_for_pipe_off - wait for pipe to turn off
1056  * @crtc: crtc whose pipe to wait for
1057  *
1058  * After disabling a pipe, we can't wait for vblank in the usual way,
1059  * spinning on the vblank interrupt status bit, since we won't actually
1060  * see an interrupt when the pipe is disabled.
1061  *
1062  * On Gen4 and above:
1063  *   wait for the pipe register state bit to turn off
1064  *
1065  * Otherwise:
1066  *   wait for the display line value to settle (it usually
1067  *   ends up stopping at the start of the next frame).
1068  *
1069  */
1070 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1071 {
1072         struct drm_device *dev = crtc->base.dev;
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1075         enum pipe pipe = crtc->pipe;
1076 
1077         if (INTEL_INFO(dev)->gen >= 4) {
1078                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1079 
1080                 /* Wait for the Pipe State to go off */
1081                 if (intel_wait_for_register(dev_priv,
1082                                             reg, I965_PIPECONF_ACTIVE, 0,
1083                                             100))
1084                         WARN(1, "pipe_off wait timed out\n");
1085         } else {
1086                 /* Wait for the display line to settle */
1087                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1088                         WARN(1, "pipe_off wait timed out\n");
1089         }
1090 }
1091 
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094                 enum pipe pipe, bool state)
1095 {
1096         u32 val;
1097         bool cur_state;
1098 
1099         val = I915_READ(DPLL(pipe));
1100         cur_state = !!(val & DPLL_VCO_ENABLE);
1101         I915_STATE_WARN(cur_state != state,
1102              "PLL state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105 
1106 /* XXX: the dsi pll is shared between MIPI DSI ports */
1107 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111 
1112         mutex_lock(&dev_priv->sb_lock);
1113         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1114         mutex_unlock(&dev_priv->sb_lock);
1115 
1116         cur_state = val & DSI_PLL_VCO_EN;
1117         I915_STATE_WARN(cur_state != state,
1118              "DSI PLL state assertion failure (expected %s, current %s)\n",
1119                         onoff(state), onoff(cur_state));
1120 }
1121 
1122 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1123                           enum pipe pipe, bool state)
1124 {
1125         bool cur_state;
1126         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1127                                                                       pipe);
1128 
1129         if (HAS_DDI(dev_priv)) {
1130                 /* DDI does not have a specific FDI_TX register */
1131                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1135                 cur_state = !!(val & FDI_TX_ENABLE);
1136         }
1137         I915_STATE_WARN(cur_state != state,
1138              "FDI TX state assertion failure (expected %s, current %s)\n",
1139                         onoff(state), onoff(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143 
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         u32 val;
1148         bool cur_state;
1149 
1150         val = I915_READ(FDI_RX_CTL(pipe));
1151         cur_state = !!(val & FDI_RX_ENABLE);
1152         I915_STATE_WARN(cur_state != state,
1153              "FDI RX state assertion failure (expected %s, current %s)\n",
1154                         onoff(state), onoff(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160                                       enum pipe pipe)
1161 {
1162         u32 val;
1163 
1164         /* ILK FDI PLL is always enabled */
1165         if (IS_GEN5(dev_priv))
1166                 return;
1167 
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv))
1170                 return;
1171 
1172         val = I915_READ(FDI_TX_CTL(pipe));
1173         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1174 }
1175 
1176 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1177                        enum pipe pipe, bool state)
1178 {
1179         u32 val;
1180         bool cur_state;
1181 
1182         val = I915_READ(FDI_RX_CTL(pipe));
1183         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184         I915_STATE_WARN(cur_state != state,
1185              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186                         onoff(state), onoff(cur_state));
1187 }
1188 
1189 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190                            enum pipe pipe)
1191 {
1192         struct drm_device *dev = &dev_priv->drm;
1193         i915_reg_t pp_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197 
1198         if (WARN_ON(HAS_DDI(dev)))
1199                 return;
1200 
1201         if (HAS_PCH_SPLIT(dev)) {
1202                 u32 port_sel;
1203 
1204                 pp_reg = PCH_PP_CONTROL;
1205                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1206 
1207                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1208                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1209                         panel_pipe = PIPE_B;
1210                 /* XXX: else fix for eDP */
1211         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1212                 /* presumably write lock depends on pipe, not port select */
1213                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1214                 panel_pipe = pipe;
1215         } else {
1216                 pp_reg = PP_CONTROL;
1217                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1218                         panel_pipe = PIPE_B;
1219         }
1220 
1221         val = I915_READ(pp_reg);
1222         if (!(val & PANEL_POWER_ON) ||
1223             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1224                 locked = false;
1225 
1226         I915_STATE_WARN(panel_pipe == pipe && locked,
1227              "panel assertion failure, pipe %c regs locked\n",
1228              pipe_name(pipe));
1229 }
1230 
1231 static void assert_cursor(struct drm_i915_private *dev_priv,
1232                           enum pipe pipe, bool state)
1233 {
1234         struct drm_device *dev = &dev_priv->drm;
1235         bool cur_state;
1236 
1237         if (IS_845G(dev) || IS_I865G(dev))
1238                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1239         else
1240                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1241 
1242         I915_STATE_WARN(cur_state != state,
1243              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244                         pipe_name(pipe), onoff(state), onoff(cur_state));
1245 }
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1248 
1249 void assert_pipe(struct drm_i915_private *dev_priv,
1250                  enum pipe pipe, bool state)
1251 {
1252         bool cur_state;
1253         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1254                                                                       pipe);
1255         enum intel_display_power_domain power_domain;
1256 
1257         /* if we need the pipe quirk it must be always on */
1258         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1259             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1260                 state = true;
1261 
1262         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1263         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1264                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1265                 cur_state = !!(val & PIPECONF_ENABLE);
1266 
1267                 intel_display_power_put(dev_priv, power_domain);
1268         } else {
1269                 cur_state = false;
1270         }
1271 
1272         I915_STATE_WARN(cur_state != state,
1273              "pipe %c assertion failure (expected %s, current %s)\n",
1274                         pipe_name(pipe), onoff(state), onoff(cur_state));
1275 }
1276 
1277 static void assert_plane(struct drm_i915_private *dev_priv,
1278                          enum plane plane, bool state)
1279 {
1280         u32 val;
1281         bool cur_state;
1282 
1283         val = I915_READ(DSPCNTR(plane));
1284         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1285         I915_STATE_WARN(cur_state != state,
1286              "plane %c assertion failure (expected %s, current %s)\n",
1287                         plane_name(plane), onoff(state), onoff(cur_state));
1288 }
1289 
1290 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1291 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1292 
1293 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1294                                    enum pipe pipe)
1295 {
1296         struct drm_device *dev = &dev_priv->drm;
1297         int i;
1298 
1299         /* Primary planes are fixed to pipes on gen4+ */
1300         if (INTEL_INFO(dev)->gen >= 4) {
1301                 u32 val = I915_READ(DSPCNTR(pipe));
1302                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1303                      "plane %c assertion failure, should be disabled but not\n",
1304                      plane_name(pipe));
1305                 return;
1306         }
1307 
1308         /* Need to check both planes against the pipe */
1309         for_each_pipe(dev_priv, i) {
1310                 u32 val = I915_READ(DSPCNTR(i));
1311                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1312                         DISPPLANE_SEL_PIPE_SHIFT;
1313                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1314                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1315                      plane_name(i), pipe_name(pipe));
1316         }
1317 }
1318 
1319 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1320                                     enum pipe pipe)
1321 {
1322         struct drm_device *dev = &dev_priv->drm;
1323         int sprite;
1324 
1325         if (INTEL_INFO(dev)->gen >= 9) {
1326                 for_each_sprite(dev_priv, pipe, sprite) {
1327                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1328                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1329                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1330                              sprite, pipe_name(pipe));
1331                 }
1332         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1333                 for_each_sprite(dev_priv, pipe, sprite) {
1334                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1335                         I915_STATE_WARN(val & SP_ENABLE,
1336                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337                              sprite_name(pipe, sprite), pipe_name(pipe));
1338                 }
1339         } else if (INTEL_INFO(dev)->gen >= 7) {
1340                 u32 val = I915_READ(SPRCTL(pipe));
1341                 I915_STATE_WARN(val & SPRITE_ENABLE,
1342                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343                      plane_name(pipe), pipe_name(pipe));
1344         } else if (INTEL_INFO(dev)->gen >= 5) {
1345                 u32 val = I915_READ(DVSCNTR(pipe));
1346                 I915_STATE_WARN(val & DVS_ENABLE,
1347                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348                      plane_name(pipe), pipe_name(pipe));
1349         }
1350 }
1351 
1352 static void assert_vblank_disabled(struct drm_crtc *crtc)
1353 {
1354         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1355                 drm_crtc_vblank_put(crtc);
1356 }
1357 
1358 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359                                     enum pipe pipe)
1360 {
1361         u32 val;
1362         bool enabled;
1363 
1364         val = I915_READ(PCH_TRANSCONF(pipe));
1365         enabled = !!(val & TRANS_ENABLE);
1366         I915_STATE_WARN(enabled,
1367              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1368              pipe_name(pipe));
1369 }
1370 
1371 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1372                             enum pipe pipe, u32 port_sel, u32 val)
1373 {
1374         if ((val & DP_PORT_EN) == 0)
1375                 return false;
1376 
1377         if (HAS_PCH_CPT(dev_priv)) {
1378                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1379                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380                         return false;
1381         } else if (IS_CHERRYVIEW(dev_priv)) {
1382                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386                         return false;
1387         }
1388         return true;
1389 }
1390 
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & SDVO_ENABLE) == 0)
1395                 return false;
1396 
1397         if (HAS_PCH_CPT(dev_priv)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399                         return false;
1400         } else if (IS_CHERRYVIEW(dev_priv)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402                         return false;
1403         } else {
1404                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405                         return false;
1406         }
1407         return true;
1408 }
1409 
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411                               enum pipe pipe, u32 val)
1412 {
1413         if ((val & LVDS_PORT_EN) == 0)
1414                 return false;
1415 
1416         if (HAS_PCH_CPT(dev_priv)) {
1417                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418                         return false;
1419         } else {
1420                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421                         return false;
1422         }
1423         return true;
1424 }
1425 
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427                               enum pipe pipe, u32 val)
1428 {
1429         if ((val & ADPA_DAC_ENABLE) == 0)
1430                 return false;
1431         if (HAS_PCH_CPT(dev_priv)) {
1432                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433                         return false;
1434         } else {
1435                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436                         return false;
1437         }
1438         return true;
1439 }
1440 
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442                                    enum pipe pipe, i915_reg_t reg,
1443                                    u32 port_sel)
1444 {
1445         u32 val = I915_READ(reg);
1446         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1447              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448              i915_mmio_reg_offset(reg), pipe_name(pipe));
1449 
1450         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1451              && (val & DP_PIPEB_SELECT),
1452              "IBX PCH dp port still using transcoder B\n");
1453 }
1454 
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1456                                      enum pipe pipe, i915_reg_t reg)
1457 {
1458         u32 val = I915_READ(reg);
1459         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1460              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461              i915_mmio_reg_offset(reg), pipe_name(pipe));
1462 
1463         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1464              && (val & SDVO_PIPE_B_SELECT),
1465              "IBX PCH hdmi port still using transcoder B\n");
1466 }
1467 
1468 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469                                       enum pipe pipe)
1470 {
1471         u32 val;
1472 
1473         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476 
1477         val = I915_READ(PCH_ADPA);
1478         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479              "PCH VGA enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481 
1482         val = I915_READ(PCH_LVDS);
1483         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1484              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485              pipe_name(pipe));
1486 
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 }
1491 
1492 static void _vlv_enable_pll(struct intel_crtc *crtc,
1493                             const struct intel_crtc_state *pipe_config)
1494 {
1495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1496         enum pipe pipe = crtc->pipe;
1497 
1498         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1499         POSTING_READ(DPLL(pipe));
1500         udelay(150);
1501 
1502         if (intel_wait_for_register(dev_priv,
1503                                     DPLL(pipe),
1504                                     DPLL_LOCK_VLV,
1505                                     DPLL_LOCK_VLV,
1506                                     1))
1507                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1508 }
1509 
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1514         enum pipe pipe = crtc->pipe;
1515 
1516         assert_pipe_disabled(dev_priv, pipe);
1517 
1518         /* PLL is protected by panel, make sure we can write it */
1519         assert_panel_unlocked(dev_priv, pipe);
1520 
1521         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1522                 _vlv_enable_pll(crtc, pipe_config);
1523 
1524         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1525         POSTING_READ(DPLL_MD(pipe));
1526 }
1527 
1528 
1529 static void _chv_enable_pll(struct intel_crtc *crtc,
1530                             const struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533         enum pipe pipe = crtc->pipe;
1534         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1535         u32 tmp;
1536 
1537         mutex_lock(&dev_priv->sb_lock);
1538 
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543 
1544         mutex_unlock(&dev_priv->sb_lock);
1545 
1546         /*
1547          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1548          */
1549         udelay(1);
1550 
1551         /* Enable PLL */
1552         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1553 
1554         /* Check PLL is locked */
1555         if (intel_wait_for_register(dev_priv,
1556                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1557                                     1))
1558                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1559 }
1560 
1561 static void chv_enable_pll(struct intel_crtc *crtc,
1562                            const struct intel_crtc_state *pipe_config)
1563 {
1564         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1565         enum pipe pipe = crtc->pipe;
1566 
1567         assert_pipe_disabled(dev_priv, pipe);
1568 
1569         /* PLL is protected by panel, make sure we can write it */
1570         assert_panel_unlocked(dev_priv, pipe);
1571 
1572         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1573                 _chv_enable_pll(crtc, pipe_config);
1574 
1575         if (pipe != PIPE_A) {
1576                 /*
1577                  * WaPixelRepeatModeFixForC0:chv
1578                  *
1579                  * DPLLCMD is AWOL. Use chicken bits to propagate
1580                  * the value from DPLLBMD to either pipe B or C.
1581                  */
1582                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1583                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1584                 I915_WRITE(CBR4_VLV, 0);
1585                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1586 
1587                 /*
1588                  * DPLLB VGA mode also seems to cause problems.
1589                  * We should always have it disabled.
1590                  */
1591                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1592         } else {
1593                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1594                 POSTING_READ(DPLL_MD(pipe));
1595         }
1596 }
1597 
1598 static int intel_num_dvo_pipes(struct drm_device *dev)
1599 {
1600         struct intel_crtc *crtc;
1601         int count = 0;
1602 
1603         for_each_intel_crtc(dev, crtc) {
1604                 count += crtc->base.state->active &&
1605                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1606         }
1607 
1608         return count;
1609 }
1610 
1611 static void i9xx_enable_pll(struct intel_crtc *crtc)
1612 {
1613         struct drm_device *dev = crtc->base.dev;
1614         struct drm_i915_private *dev_priv = to_i915(dev);
1615         i915_reg_t reg = DPLL(crtc->pipe);
1616         u32 dpll = crtc->config->dpll_hw_state.dpll;
1617 
1618         assert_pipe_disabled(dev_priv, crtc->pipe);
1619 
1620         /* PLL is protected by panel, make sure we can write it */
1621         if (IS_MOBILE(dev) && !IS_I830(dev))
1622                 assert_panel_unlocked(dev_priv, crtc->pipe);
1623 
1624         /* Enable DVO 2x clock on both PLLs if necessary */
1625         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1626                 /*
1627                  * It appears to be important that we don't enable this
1628                  * for the current pipe before otherwise configuring the
1629                  * PLL. No idea how this should be handled if multiple
1630                  * DVO outputs are enabled simultaneosly.
1631                  */
1632                 dpll |= DPLL_DVO_2X_MODE;
1633                 I915_WRITE(DPLL(!crtc->pipe),
1634                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1635         }
1636 
1637         /*
1638          * Apparently we need to have VGA mode enabled prior to changing
1639          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1640          * dividers, even though the register value does change.
1641          */
1642         I915_WRITE(reg, 0);
1643 
1644         I915_WRITE(reg, dpll);
1645 
1646         /* Wait for the clocks to stabilize. */
1647         POSTING_READ(reg);
1648         udelay(150);
1649 
1650         if (INTEL_INFO(dev)->gen >= 4) {
1651                 I915_WRITE(DPLL_MD(crtc->pipe),
1652                            crtc->config->dpll_hw_state.dpll_md);
1653         } else {
1654                 /* The pixel multiplier can only be updated once the
1655                  * DPLL is enabled and the clocks are stable.
1656                  *
1657                  * So write it again.
1658                  */
1659                 I915_WRITE(reg, dpll);
1660         }
1661 
1662         /* We do this three times for luck */
1663         I915_WRITE(reg, dpll);
1664         POSTING_READ(reg);
1665         udelay(150); /* wait for warmup */
1666         I915_WRITE(reg, dpll);
1667         POSTING_READ(reg);
1668         udelay(150); /* wait for warmup */
1669         I915_WRITE(reg, dpll);
1670         POSTING_READ(reg);
1671         udelay(150); /* wait for warmup */
1672 }
1673 
1674 /**
1675  * i9xx_disable_pll - disable a PLL
1676  * @dev_priv: i915 private structure
1677  * @pipe: pipe PLL to disable
1678  *
1679  * Disable the PLL for @pipe, making sure the pipe is off first.
1680  *
1681  * Note!  This is for pre-ILK only.
1682  */
1683 static void i9xx_disable_pll(struct intel_crtc *crtc)
1684 {
1685         struct drm_device *dev = crtc->base.dev;
1686         struct drm_i915_private *dev_priv = to_i915(dev);
1687         enum pipe pipe = crtc->pipe;
1688 
1689         /* Disable DVO 2x clock on both PLLs if necessary */
1690         if (IS_I830(dev) &&
1691             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1692             !intel_num_dvo_pipes(dev)) {
1693                 I915_WRITE(DPLL(PIPE_B),
1694                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1695                 I915_WRITE(DPLL(PIPE_A),
1696                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1697         }
1698 
1699         /* Don't disable pipe or pipe PLLs if needed */
1700         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1701             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1702                 return;
1703 
1704         /* Make sure the pipe isn't still relying on us */
1705         assert_pipe_disabled(dev_priv, pipe);
1706 
1707         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1708         POSTING_READ(DPLL(pipe));
1709 }
1710 
1711 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713         u32 val;
1714 
1715         /* Make sure the pipe isn't still relying on us */
1716         assert_pipe_disabled(dev_priv, pipe);
1717 
1718         val = DPLL_INTEGRATED_REF_CLK_VLV |
1719                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1720         if (pipe != PIPE_A)
1721                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1722 
1723         I915_WRITE(DPLL(pipe), val);
1724         POSTING_READ(DPLL(pipe));
1725 }
1726 
1727 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1728 {
1729         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1730         u32 val;
1731 
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734 
1735         val = DPLL_SSC_REF_CLK_CHV |
1736                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737         if (pipe != PIPE_A)
1738                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739 
1740         I915_WRITE(DPLL(pipe), val);
1741         POSTING_READ(DPLL(pipe));
1742 
1743         mutex_lock(&dev_priv->sb_lock);
1744 
1745         /* Disable 10bit clock to display controller */
1746         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1747         val &= ~DPIO_DCLKP_EN;
1748         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1749 
1750         mutex_unlock(&dev_priv->sb_lock);
1751 }
1752 
1753 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1754                          struct intel_digital_port *dport,
1755                          unsigned int expected_mask)
1756 {
1757         u32 port_mask;
1758         i915_reg_t dpll_reg;
1759 
1760         switch (dport->port) {
1761         case PORT_B:
1762                 port_mask = DPLL_PORTB_READY_MASK;
1763                 dpll_reg = DPLL(0);
1764                 break;
1765         case PORT_C:
1766                 port_mask = DPLL_PORTC_READY_MASK;
1767                 dpll_reg = DPLL(0);
1768                 expected_mask <<= 4;
1769                 break;
1770         case PORT_D:
1771                 port_mask = DPLL_PORTD_READY_MASK;
1772                 dpll_reg = DPIO_PHY_STATUS;
1773                 break;
1774         default:
1775                 BUG();
1776         }
1777 
1778         if (intel_wait_for_register(dev_priv,
1779                                     dpll_reg, port_mask, expected_mask,
1780                                     1000))
1781                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1782                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1783 }
1784 
1785 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1786                                            enum pipe pipe)
1787 {
1788         struct drm_device *dev = &dev_priv->drm;
1789         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791         i915_reg_t reg;
1792         uint32_t val, pipeconf_val;
1793 
1794         /* Make sure PCH DPLL is enabled */
1795         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1796 
1797         /* FDI must be feeding us bits for PCH ports */
1798         assert_fdi_tx_enabled(dev_priv, pipe);
1799         assert_fdi_rx_enabled(dev_priv, pipe);
1800 
1801         if (HAS_PCH_CPT(dev)) {
1802                 /* Workaround: Set the timing override bit before enabling the
1803                  * pch transcoder. */
1804                 reg = TRANS_CHICKEN2(pipe);
1805                 val = I915_READ(reg);
1806                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1807                 I915_WRITE(reg, val);
1808         }
1809 
1810         reg = PCH_TRANSCONF(pipe);
1811         val = I915_READ(reg);
1812         pipeconf_val = I915_READ(PIPECONF(pipe));
1813 
1814         if (HAS_PCH_IBX(dev_priv)) {
1815                 /*
1816                  * Make the BPC in transcoder be consistent with
1817                  * that in pipeconf reg. For HDMI we must use 8bpc
1818                  * here for both 8bpc and 12bpc.
1819                  */
1820                 val &= ~PIPECONF_BPC_MASK;
1821                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1822                         val |= PIPECONF_8BPC;
1823                 else
1824                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1825         }
1826 
1827         val &= ~TRANS_INTERLACE_MASK;
1828         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1829                 if (HAS_PCH_IBX(dev_priv) &&
1830                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1831                         val |= TRANS_LEGACY_INTERLACED_ILK;
1832                 else
1833                         val |= TRANS_INTERLACED;
1834         else
1835                 val |= TRANS_PROGRESSIVE;
1836 
1837         I915_WRITE(reg, val | TRANS_ENABLE);
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1840                                     100))
1841                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1842 }
1843 
1844 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1845                                       enum transcoder cpu_transcoder)
1846 {
1847         u32 val, pipeconf_val;
1848 
1849         /* FDI must be feeding us bits for PCH ports */
1850         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1851         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1852 
1853         /* Workaround: set timing override bit. */
1854         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1855         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1857 
1858         val = TRANS_ENABLE;
1859         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1860 
1861         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1862             PIPECONF_INTERLACED_ILK)
1863                 val |= TRANS_INTERLACED;
1864         else
1865                 val |= TRANS_PROGRESSIVE;
1866 
1867         I915_WRITE(LPT_TRANSCONF, val);
1868         if (intel_wait_for_register(dev_priv,
1869                                     LPT_TRANSCONF,
1870                                     TRANS_STATE_ENABLE,
1871                                     TRANS_STATE_ENABLE,
1872                                     100))
1873                 DRM_ERROR("Failed to enable PCH transcoder\n");
1874 }
1875 
1876 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1877                                             enum pipe pipe)
1878 {
1879         struct drm_device *dev = &dev_priv->drm;
1880         i915_reg_t reg;
1881         uint32_t val;
1882 
1883         /* FDI relies on the transcoder */
1884         assert_fdi_tx_disabled(dev_priv, pipe);
1885         assert_fdi_rx_disabled(dev_priv, pipe);
1886 
1887         /* Ports must be off as well */
1888         assert_pch_ports_disabled(dev_priv, pipe);
1889 
1890         reg = PCH_TRANSCONF(pipe);
1891         val = I915_READ(reg);
1892         val &= ~TRANS_ENABLE;
1893         I915_WRITE(reg, val);
1894         /* wait for PCH transcoder off, transcoder state */
1895         if (intel_wait_for_register(dev_priv,
1896                                     reg, TRANS_STATE_ENABLE, 0,
1897                                     50))
1898                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1899 
1900         if (HAS_PCH_CPT(dev)) {
1901                 /* Workaround: Clear the timing override chicken bit again. */
1902                 reg = TRANS_CHICKEN2(pipe);
1903                 val = I915_READ(reg);
1904                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1905                 I915_WRITE(reg, val);
1906         }
1907 }
1908 
1909 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1910 {
1911         u32 val;
1912 
1913         val = I915_READ(LPT_TRANSCONF);
1914         val &= ~TRANS_ENABLE;
1915         I915_WRITE(LPT_TRANSCONF, val);
1916         /* wait for PCH transcoder off, transcoder state */
1917         if (intel_wait_for_register(dev_priv,
1918                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1919                                     50))
1920                 DRM_ERROR("Failed to disable PCH transcoder\n");
1921 
1922         /* Workaround: clear timing override bit. */
1923         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1924         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1925         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1926 }
1927 
1928 /**
1929  * intel_enable_pipe - enable a pipe, asserting requirements
1930  * @crtc: crtc responsible for the pipe
1931  *
1932  * Enable @crtc's pipe, making sure that various hardware specific requirements
1933  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1934  */
1935 static void intel_enable_pipe(struct intel_crtc *crtc)
1936 {
1937         struct drm_device *dev = crtc->base.dev;
1938         struct drm_i915_private *dev_priv = to_i915(dev);
1939         enum pipe pipe = crtc->pipe;
1940         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1941         enum pipe pch_transcoder;
1942         i915_reg_t reg;
1943         u32 val;
1944 
1945         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1946 
1947         assert_planes_disabled(dev_priv, pipe);
1948         assert_cursor_disabled(dev_priv, pipe);
1949         assert_sprites_disabled(dev_priv, pipe);
1950 
1951         if (HAS_PCH_LPT(dev_priv))
1952                 pch_transcoder = TRANSCODER_A;
1953         else
1954                 pch_transcoder = pipe;
1955 
1956         /*
1957          * A pipe without a PLL won't actually be able to drive bits from
1958          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1959          * need the check.
1960          */
1961         if (HAS_GMCH_DISPLAY(dev_priv))
1962                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1963                         assert_dsi_pll_enabled(dev_priv);
1964                 else
1965                         assert_pll_enabled(dev_priv, pipe);
1966         else {
1967                 if (crtc->config->has_pch_encoder) {
1968                         /* if driving the PCH, we need FDI enabled */
1969                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1970                         assert_fdi_tx_pll_enabled(dev_priv,
1971                                                   (enum pipe) cpu_transcoder);
1972                 }
1973                 /* FIXME: assert CPU port conditions for SNB+ */
1974         }
1975 
1976         reg = PIPECONF(cpu_transcoder);
1977         val = I915_READ(reg);
1978         if (val & PIPECONF_ENABLE) {
1979                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1980                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1981                 return;
1982         }
1983 
1984         I915_WRITE(reg, val | PIPECONF_ENABLE);
1985         POSTING_READ(reg);
1986 
1987         /*
1988          * Until the pipe starts DSL will read as 0, which would cause
1989          * an apparent vblank timestamp jump, which messes up also the
1990          * frame count when it's derived from the timestamps. So let's
1991          * wait for the pipe to start properly before we call
1992          * drm_crtc_vblank_on()
1993          */
1994         if (dev->max_vblank_count == 0 &&
1995             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1996                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1997 }
1998 
1999 /**
2000  * intel_disable_pipe - disable a pipe, asserting requirements
2001  * @crtc: crtc whose pipes is to be disabled
2002  *
2003  * Disable the pipe of @crtc, making sure that various hardware
2004  * specific requirements are met, if applicable, e.g. plane
2005  * disabled, panel fitter off, etc.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2012         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2013         enum pipe pipe = crtc->pipe;
2014         i915_reg_t reg;
2015         u32 val;
2016 
2017         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2018 
2019         /*
2020          * Make sure planes won't keep trying to pump pixels to us,
2021          * or we might hang the display.
2022          */
2023         assert_planes_disabled(dev_priv, pipe);
2024         assert_cursor_disabled(dev_priv, pipe);
2025         assert_sprites_disabled(dev_priv, pipe);
2026 
2027         reg = PIPECONF(cpu_transcoder);
2028         val = I915_READ(reg);
2029         if ((val & PIPECONF_ENABLE) == 0)
2030                 return;
2031 
2032         /*
2033          * Double wide has implications for planes
2034          * so best keep it disabled when not needed.
2035          */
2036         if (crtc->config->double_wide)
2037                 val &= ~PIPECONF_DOUBLE_WIDE;
2038 
2039         /* Don't disable pipe or pipe PLLs if needed */
2040         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2041             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2042                 val &= ~PIPECONF_ENABLE;
2043 
2044         I915_WRITE(reg, val);
2045         if ((val & PIPECONF_ENABLE) == 0)
2046                 intel_wait_for_pipe_off(crtc);
2047 }
2048 
2049 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2050 {
2051         return IS_GEN2(dev_priv) ? 2048 : 4096;
2052 }
2053 
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2055                                            uint64_t fb_modifier, unsigned int cpp)
2056 {
2057         switch (fb_modifier) {
2058         case DRM_FORMAT_MOD_NONE:
2059                 return cpp;
2060         case I915_FORMAT_MOD_X_TILED:
2061                 if (IS_GEN2(dev_priv))
2062                         return 128;
2063                 else
2064                         return 512;
2065         case I915_FORMAT_MOD_Y_TILED:
2066                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2067                         return 128;
2068                 else
2069                         return 512;
2070         case I915_FORMAT_MOD_Yf_TILED:
2071                 switch (cpp) {
2072                 case 1:
2073                         return 64;
2074                 case 2:
2075                 case 4:
2076                         return 128;
2077                 case 8:
2078                 case 16:
2079                         return 256;
2080                 default:
2081                         MISSING_CASE(cpp);
2082                         return cpp;
2083                 }
2084                 break;
2085         default:
2086                 MISSING_CASE(fb_modifier);
2087                 return cpp;
2088         }
2089 }
2090 
2091 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2092                                uint64_t fb_modifier, unsigned int cpp)
2093 {
2094         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2095                 return 1;
2096         else
2097                 return intel_tile_size(dev_priv) /
2098                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2099 }
2100 
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2103                             unsigned int *tile_width,
2104                             unsigned int *tile_height,
2105                             uint64_t fb_modifier,
2106                             unsigned int cpp)
2107 {
2108         unsigned int tile_width_bytes =
2109                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2110 
2111         *tile_width = tile_width_bytes / cpp;
2112         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2113 }
2114 
2115 unsigned int
2116 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2117                       uint32_t pixel_format, uint64_t fb_modifier)
2118 {
2119         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2120         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2121 
2122         return ALIGN(height, tile_height);
2123 }
2124 
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2126 {
2127         unsigned int size = 0;
2128         int i;
2129 
2130         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2131                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2132 
2133         return size;
2134 }
2135 
2136 static void
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2138                         const struct drm_framebuffer *fb,
2139                         unsigned int rotation)
2140 {
2141         if (intel_rotation_90_or_270(rotation)) {
2142                 *view = i915_ggtt_view_rotated;
2143                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2144         } else {
2145                 *view = i915_ggtt_view_normal;
2146         }
2147 }
2148 
2149 static void
2150 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2151                    struct drm_framebuffer *fb)
2152 {
2153         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2154         unsigned int tile_size, tile_width, tile_height, cpp;
2155 
2156         tile_size = intel_tile_size(dev_priv);
2157 
2158         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2159         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2160                         fb->modifier[0], cpp);
2161 
2162         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2163         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2164 
2165         if (info->pixel_format == DRM_FORMAT_NV12) {
2166                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2167                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2168                                 fb->modifier[1], cpp);
2169 
2170                 info->uv_offset = fb->offsets[1];
2171                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2172                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2173         }
2174 }
2175 
2176 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2177 {
2178         if (INTEL_INFO(dev_priv)->gen >= 9)
2179                 return 256 * 1024;
2180         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2181                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2182                 return 128 * 1024;
2183         else if (INTEL_INFO(dev_priv)->gen >= 4)
2184                 return 4 * 1024;
2185         else
2186                 return 0;
2187 }
2188 
2189 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2190                                          uint64_t fb_modifier)
2191 {
2192         switch (fb_modifier) {
2193         case DRM_FORMAT_MOD_NONE:
2194                 return intel_linear_alignment(dev_priv);
2195         case I915_FORMAT_MOD_X_TILED:
2196                 if (INTEL_INFO(dev_priv)->gen >= 9)
2197                         return 256 * 1024;
2198                 return 0;
2199         case I915_FORMAT_MOD_Y_TILED:
2200         case I915_FORMAT_MOD_Yf_TILED:
2201                 return 1 * 1024 * 1024;
2202         default:
2203                 MISSING_CASE(fb_modifier);
2204                 return 0;
2205         }
2206 }
2207 
2208 int
2209 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2210                            unsigned int rotation)
2211 {
2212         struct drm_device *dev = fb->dev;
2213         struct drm_i915_private *dev_priv = to_i915(dev);
2214         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2215         struct i915_ggtt_view view;
2216         u32 alignment;
2217         int ret;
2218 
2219         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2220 
2221         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2222 
2223         intel_fill_fb_ggtt_view(&view, fb, rotation);
2224 
2225         /* Note that the w/a also requires 64 PTE of padding following the
2226          * bo. We currently fill all unused PTE with the shadow page and so
2227          * we should always have valid PTE following the scanout preventing
2228          * the VT-d warning.
2229          */
2230         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2231                 alignment = 256 * 1024;
2232 
2233         /*
2234          * Global gtt pte registers are special registers which actually forward
2235          * writes to a chunk of system memory. Which means that there is no risk
2236          * that the register values disappear as soon as we call
2237          * intel_runtime_pm_put(), so it is correct to wrap only the
2238          * pin/unpin/fence and not more.
2239          */
2240         intel_runtime_pm_get(dev_priv);
2241 
2242         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2243                                                    &view);
2244         if (ret)
2245                 goto err_pm;
2246 
2247         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2248          * fence, whereas 965+ only requires a fence if using
2249          * framebuffer compression.  For simplicity, we always install
2250          * a fence as the cost is not that onerous.
2251          */
2252         if (view.type == I915_GGTT_VIEW_NORMAL) {
2253                 ret = i915_gem_object_get_fence(obj);
2254                 if (ret == -EDEADLK) {
2255                         /*
2256                          * -EDEADLK means there are no free fences
2257                          * no pending flips.
2258                          *
2259                          * This is propagated to atomic, but it uses
2260                          * -EDEADLK to force a locking recovery, so
2261                          * change the returned error to -EBUSY.
2262                          */
2263                         ret = -EBUSY;
2264                         goto err_unpin;
2265                 } else if (ret)
2266                         goto err_unpin;
2267 
2268                 i915_gem_object_pin_fence(obj);
2269         }
2270 
2271         intel_runtime_pm_put(dev_priv);
2272         return 0;
2273 
2274 err_unpin:
2275         i915_gem_object_unpin_from_display_plane(obj, &view);
2276 err_pm:
2277         intel_runtime_pm_put(dev_priv);
2278         return ret;
2279 }
2280 
2281 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2282 {
2283         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2284         struct i915_ggtt_view view;
2285 
2286         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2287 
2288         intel_fill_fb_ggtt_view(&view, fb, rotation);
2289 
2290         if (view.type == I915_GGTT_VIEW_NORMAL)
2291                 i915_gem_object_unpin_fence(obj);
2292 
2293         i915_gem_object_unpin_from_display_plane(obj, &view);
2294 }
2295 
2296 /*
2297  * Adjust the tile offset by moving the difference into
2298  * the x/y offsets.
2299  *
2300  * Input tile dimensions and pitch must already be
2301  * rotated to match x and y, and in pixel units.
2302  */
2303 static u32 intel_adjust_tile_offset(int *x, int *y,
2304                                     unsigned int tile_width,
2305                                     unsigned int tile_height,
2306                                     unsigned int tile_size,
2307                                     unsigned int pitch_tiles,
2308                                     u32 old_offset,
2309                                     u32 new_offset)
2310 {
2311         unsigned int tiles;
2312 
2313         WARN_ON(old_offset & (tile_size - 1));
2314         WARN_ON(new_offset & (tile_size - 1));
2315         WARN_ON(new_offset > old_offset);
2316 
2317         tiles = (old_offset - new_offset) / tile_size;
2318 
2319         *y += tiles / pitch_tiles * tile_height;
2320         *x += tiles % pitch_tiles * tile_width;
2321 
2322         return new_offset;
2323 }
2324 
2325 /*
2326  * Computes the linear offset to the base tile and adjusts
2327  * x, y. bytes per pixel is assumed to be a power-of-two.
2328  *
2329  * In the 90/270 rotated case, x and y are assumed
2330  * to be already rotated to match the rotated GTT view, and
2331  * pitch is the tile_height aligned framebuffer height.
2332  */
2333 u32 intel_compute_tile_offset(int *x, int *y,
2334                               const struct drm_framebuffer *fb, int plane,
2335                               unsigned int pitch,
2336                               unsigned int rotation)
2337 {
2338         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2339         uint64_t fb_modifier = fb->modifier[plane];
2340         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2341         u32 offset, offset_aligned, alignment;
2342 
2343         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2344         if (alignment)
2345                 alignment--;
2346 
2347         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2348                 unsigned int tile_size, tile_width, tile_height;
2349                 unsigned int tile_rows, tiles, pitch_tiles;
2350 
2351                 tile_size = intel_tile_size(dev_priv);
2352                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2353                                 fb_modifier, cpp);
2354 
2355                 if (intel_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361 
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364 
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367 
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370 
2371                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                          tile_size, pitch_tiles,
2373                                          offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377 
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381 
2382         return offset_aligned;
2383 }
2384 
2385 static int i9xx_format_to_fourcc(int format)
2386 {
2387         switch (format) {
2388         case DISPPLANE_8BPP:
2389                 return DRM_FORMAT_C8;
2390         case DISPPLANE_BGRX555:
2391                 return DRM_FORMAT_XRGB1555;
2392         case DISPPLANE_BGRX565:
2393                 return DRM_FORMAT_RGB565;
2394         default:
2395         case DISPPLANE_BGRX888:
2396                 return DRM_FORMAT_XRGB8888;
2397         case DISPPLANE_RGBX888:
2398                 return DRM_FORMAT_XBGR8888;
2399         case DISPPLANE_BGRX101010:
2400                 return DRM_FORMAT_XRGB2101010;
2401         case DISPPLANE_RGBX101010:
2402                 return DRM_FORMAT_XBGR2101010;
2403         }
2404 }
2405 
2406 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2407 {
2408         switch (format) {
2409         case PLANE_CTL_FORMAT_RGB_565:
2410                 return DRM_FORMAT_RGB565;
2411         default:
2412         case PLANE_CTL_FORMAT_XRGB_8888:
2413                 if (rgb_order) {
2414                         if (alpha)
2415                                 return DRM_FORMAT_ABGR8888;
2416                         else
2417                                 return DRM_FORMAT_XBGR8888;
2418                 } else {
2419                         if (alpha)
2420                                 return DRM_FORMAT_ARGB8888;
2421                         else
2422                                 return DRM_FORMAT_XRGB8888;
2423                 }
2424         case PLANE_CTL_FORMAT_XRGB_2101010:
2425                 if (rgb_order)
2426                         return DRM_FORMAT_XBGR2101010;
2427                 else
2428                         return DRM_FORMAT_XRGB2101010;
2429         }
2430 }
2431 
2432 static bool
2433 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2434                               struct intel_initial_plane_config *plane_config)
2435 {
2436         struct drm_device *dev = crtc->base.dev;
2437         struct drm_i915_private *dev_priv = to_i915(dev);
2438         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2439         struct drm_i915_gem_object *obj = NULL;
2440         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2441         struct drm_framebuffer *fb = &plane_config->fb->base;
2442         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2443         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2444                                     PAGE_SIZE);
2445 
2446         size_aligned -= base_aligned;
2447 
2448         if (plane_config->size == 0)
2449                 return false;
2450 
2451         /* If the FB is too big, just don't use it since fbdev is not very
2452          * important and we should probably use that space with FBC or other
2453          * features. */
2454         if (size_aligned * 2 > ggtt->stolen_usable_size)
2455                 return false;
2456 
2457         mutex_lock(&dev->struct_mutex);
2458 
2459         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2460                                                              base_aligned,
2461                                                              base_aligned,
2462                                                              size_aligned);
2463         if (!obj) {
2464                 mutex_unlock(&dev->struct_mutex);
2465                 return false;
2466         }
2467 
2468         obj->tiling_mode = plane_config->tiling;
2469         if (obj->tiling_mode == I915_TILING_X)
2470                 obj->stride = fb->pitches[0];
2471 
2472         mode_cmd.pixel_format = fb->pixel_format;
2473         mode_cmd.width = fb->width;
2474         mode_cmd.height = fb->height;
2475         mode_cmd.pitches[0] = fb->pitches[0];
2476         mode_cmd.modifier[0] = fb->modifier[0];
2477         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2478 
2479         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2480                                    &mode_cmd, obj)) {
2481                 DRM_DEBUG_KMS("intel fb init failed\n");
2482                 goto out_unref_obj;
2483         }
2484 
2485         mutex_unlock(&dev->struct_mutex);
2486 
2487         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2488         return true;
2489 
2490 out_unref_obj:
2491         drm_gem_object_unreference(&obj->base);
2492         mutex_unlock(&dev->struct_mutex);
2493         return false;
2494 }
2495 
2496 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2497 static void
2498 update_state_fb(struct drm_plane *plane)
2499 {
2500         if (plane->fb == plane->state->fb)
2501                 return;
2502 
2503         if (plane->state->fb)
2504                 drm_framebuffer_unreference(plane->state->fb);
2505         plane->state->fb = plane->fb;
2506         if (plane->state->fb)
2507                 drm_framebuffer_reference(plane->state->fb);
2508 }
2509 
2510 static void
2511 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2512                              struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = intel_crtc->base.dev;
2515         struct drm_i915_private *dev_priv = to_i915(dev);
2516         struct drm_crtc *c;
2517         struct intel_crtc *i;
2518         struct drm_i915_gem_object *obj;
2519         struct drm_plane *primary = intel_crtc->base.primary;
2520         struct drm_plane_state *plane_state = primary->state;
2521         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2522         struct intel_plane *intel_plane = to_intel_plane(primary);
2523         struct intel_plane_state *intel_state =
2524                 to_intel_plane_state(plane_state);
2525         struct drm_framebuffer *fb;
2526 
2527         if (!plane_config->fb)
2528                 return;
2529 
2530         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2531                 fb = &plane_config->fb->base;
2532                 goto valid_fb;
2533         }
2534 
2535         kfree(plane_config->fb);
2536 
2537         /*
2538          * Failed to alloc the obj, check to see if we should share
2539          * an fb with another CRTC instead
2540          */
2541         for_each_crtc(dev, c) {
2542                 i = to_intel_crtc(c);
2543 
2544                 if (c == &intel_crtc->base)
2545                         continue;
2546 
2547                 if (!i->active)
2548                         continue;
2549 
2550                 fb = c->primary->fb;
2551                 if (!fb)
2552                         continue;
2553 
2554                 obj = intel_fb_obj(fb);
2555                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2556                         drm_framebuffer_reference(fb);
2557                         goto valid_fb;
2558                 }
2559         }
2560 
2561         /*
2562          * We've failed to reconstruct the BIOS FB.  Current display state
2563          * indicates that the primary plane is visible, but has a NULL FB,
2564          * which will lead to problems later if we don't fix it up.  The
2565          * simplest solution is to just disable the primary plane now and
2566          * pretend the BIOS never had it enabled.
2567          */
2568         to_intel_plane_state(plane_state)->visible = false;
2569         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2570         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2571         intel_plane->disable_plane(primary, &intel_crtc->base);
2572 
2573         return;
2574 
2575 valid_fb:
2576         plane_state->src_x = 0;
2577         plane_state->src_y = 0;
2578         plane_state->src_w = fb->width << 16;
2579         plane_state->src_h = fb->height << 16;
2580 
2581         plane_state->crtc_x = 0;
2582         plane_state->crtc_y = 0;
2583         plane_state->crtc_w = fb->width;
2584         plane_state->crtc_h = fb->height;
2585 
2586         intel_state->src.x1 = plane_state->src_x;
2587         intel_state->src.y1 = plane_state->src_y;
2588         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2589         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2590         intel_state->dst.x1 = plane_state->crtc_x;
2591         intel_state->dst.y1 = plane_state->crtc_y;
2592         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2593         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2594 
2595         obj = intel_fb_obj(fb);
2596         if (obj->tiling_mode != I915_TILING_NONE)
2597                 dev_priv->preserve_bios_swizzle = true;
2598 
2599         drm_framebuffer_reference(fb);
2600         primary->fb = primary->state->fb = fb;
2601         primary->crtc = primary->state->crtc = &intel_crtc->base;
2602         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2603         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2604 }
2605 
2606 static void i9xx_update_primary_plane(struct drm_plane *primary,
2607                                       const struct intel_crtc_state *crtc_state,
2608                                       const struct intel_plane_state *plane_state)
2609 {
2610         struct drm_device *dev = primary->dev;
2611         struct drm_i915_private *dev_priv = to_i915(dev);
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2613         struct drm_framebuffer *fb = plane_state->base.fb;
2614         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2615         int plane = intel_crtc->plane;
2616         u32 linear_offset;
2617         u32 dspcntr;
2618         i915_reg_t reg = DSPCNTR(plane);
2619         unsigned int rotation = plane_state->base.rotation;
2620         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2621         int x = plane_state->src.x1 >> 16;
2622         int y = plane_state->src.y1 >> 16;
2623 
2624         dspcntr = DISPPLANE_GAMMA_ENABLE;
2625 
2626         dspcntr |= DISPLAY_PLANE_ENABLE;
2627 
2628         if (INTEL_INFO(dev)->gen < 4) {
2629                 if (intel_crtc->pipe == PIPE_B)
2630                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2631 
2632                 /* pipesrc and dspsize control the size that is scaled from,
2633                  * which should always be the user's requested size.
2634                  */
2635                 I915_WRITE(DSPSIZE(plane),
2636                            ((crtc_state->pipe_src_h - 1) << 16) |
2637                            (crtc_state->pipe_src_w - 1));
2638                 I915_WRITE(DSPPOS(plane), 0);
2639         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2640                 I915_WRITE(PRIMSIZE(plane),
2641                            ((crtc_state->pipe_src_h - 1) << 16) |
2642                            (crtc_state->pipe_src_w - 1));
2643                 I915_WRITE(PRIMPOS(plane), 0);
2644                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2645         }
2646 
2647         switch (fb->pixel_format) {
2648         case DRM_FORMAT_C8:
2649                 dspcntr |= DISPPLANE_8BPP;
2650                 break;
2651         case DRM_FORMAT_XRGB1555:
2652                 dspcntr |= DISPPLANE_BGRX555;
2653                 break;
2654         case DRM_FORMAT_RGB565:
2655                 dspcntr |= DISPPLANE_BGRX565;
2656                 break;
2657         case DRM_FORMAT_XRGB8888:
2658                 dspcntr |= DISPPLANE_BGRX888;
2659                 break;
2660         case DRM_FORMAT_XBGR8888:
2661                 dspcntr |= DISPPLANE_RGBX888;
2662                 break;
2663         case DRM_FORMAT_XRGB2101010:
2664                 dspcntr |= DISPPLANE_BGRX101010;
2665                 break;
2666         case DRM_FORMAT_XBGR2101010:
2667                 dspcntr |= DISPPLANE_RGBX101010;
2668                 break;
2669         default:
2670                 BUG();
2671         }
2672 
2673         if (INTEL_INFO(dev)->gen >= 4 &&
2674             obj->tiling_mode != I915_TILING_NONE)
2675                 dspcntr |= DISPPLANE_TILED;
2676 
2677         if (IS_G4X(dev))
2678                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2679 
2680         linear_offset = y * fb->pitches[0] + x * cpp;
2681 
2682         if (INTEL_INFO(dev)->gen >= 4) {
2683                 intel_crtc->dspaddr_offset =
2684                         intel_compute_tile_offset(&x, &y, fb, 0,
2685                                                   fb->pitches[0], rotation);
2686                 linear_offset -= intel_crtc->dspaddr_offset;
2687         } else {
2688                 intel_crtc->dspaddr_offset = linear_offset;
2689         }
2690 
2691         if (rotation == BIT(DRM_ROTATE_180)) {
2692                 dspcntr |= DISPPLANE_ROTATE_180;
2693 
2694                 x += (crtc_state->pipe_src_w - 1);
2695                 y += (crtc_state->pipe_src_h - 1);
2696 
2697                 /* Finding the last pixel of the last line of the display
2698                 data and adding to linear_offset*/
2699                 linear_offset +=
2700                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2701                         (crtc_state->pipe_src_w - 1) * cpp;
2702         }
2703 
2704         intel_crtc->adjusted_x = x;
2705         intel_crtc->adjusted_y = y;
2706 
2707         I915_WRITE(reg, dspcntr);
2708 
2709         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2710         if (INTEL_INFO(dev)->gen >= 4) {
2711                 I915_WRITE(DSPSURF(plane),
2712                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2713                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2714                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2715         } else
2716                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2717         POSTING_READ(reg);
2718 }
2719 
2720 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2721                                        struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int plane = intel_crtc->plane;
2727 
2728         I915_WRITE(DSPCNTR(plane), 0);
2729         if (INTEL_INFO(dev_priv)->gen >= 4)
2730                 I915_WRITE(DSPSURF(plane), 0);
2731         else
2732                 I915_WRITE(DSPADDR(plane), 0);
2733         POSTING_READ(DSPCNTR(plane));
2734 }
2735 
2736 static void ironlake_update_primary_plane(struct drm_plane *primary,
2737                                           const struct intel_crtc_state *crtc_state,
2738                                           const struct intel_plane_state *plane_state)
2739 {
2740         struct drm_device *dev = primary->dev;
2741         struct drm_i915_private *dev_priv = to_i915(dev);
2742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2743         struct drm_framebuffer *fb = plane_state->base.fb;
2744         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2745         int plane = intel_crtc->plane;
2746         u32 linear_offset;
2747         u32 dspcntr;
2748         i915_reg_t reg = DSPCNTR(plane);
2749         unsigned int rotation = plane_state->base.rotation;
2750         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2751         int x = plane_state->src.x1 >> 16;
2752         int y = plane_state->src.y1 >> 16;
2753 
2754         dspcntr = DISPPLANE_GAMMA_ENABLE;
2755         dspcntr |= DISPLAY_PLANE_ENABLE;
2756 
2757         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2758                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2759 
2760         switch (fb->pixel_format) {
2761         case DRM_FORMAT_C8:
2762                 dspcntr |= DISPPLANE_8BPP;
2763                 break;
2764         case DRM_FORMAT_RGB565:
2765                 dspcntr |= DISPPLANE_BGRX565;
2766                 break;
2767         case DRM_FORMAT_XRGB8888:
2768                 dspcntr |= DISPPLANE_BGRX888;
2769                 break;
2770         case DRM_FORMAT_XBGR8888:
2771                 dspcntr |= DISPPLANE_RGBX888;
2772                 break;
2773         case DRM_FORMAT_XRGB2101010:
2774                 dspcntr |= DISPPLANE_BGRX101010;
2775                 break;
2776         case DRM_FORMAT_XBGR2101010:
2777                 dspcntr |= DISPPLANE_RGBX101010;
2778                 break;
2779         default:
2780                 BUG();
2781         }
2782 
2783         if (obj->tiling_mode != I915_TILING_NONE)
2784                 dspcntr |= DISPPLANE_TILED;
2785 
2786         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2787                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2788 
2789         linear_offset = y * fb->pitches[0] + x * cpp;
2790         intel_crtc->dspaddr_offset =
2791                 intel_compute_tile_offset(&x, &y, fb, 0,
2792                                           fb->pitches[0], rotation);
2793         linear_offset -= intel_crtc->dspaddr_offset;
2794         if (rotation == BIT(DRM_ROTATE_180)) {
2795                 dspcntr |= DISPPLANE_ROTATE_180;
2796 
2797                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2798                         x += (crtc_state->pipe_src_w - 1);
2799                         y += (crtc_state->pipe_src_h - 1);
2800 
2801                         /* Finding the last pixel of the last line of the display
2802                         data and adding to linear_offset*/
2803                         linear_offset +=
2804                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2805                                 (crtc_state->pipe_src_w - 1) * cpp;
2806                 }
2807         }
2808 
2809         intel_crtc->adjusted_x = x;
2810         intel_crtc->adjusted_y = y;
2811 
2812         I915_WRITE(reg, dspcntr);
2813 
2814         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2815         I915_WRITE(DSPSURF(plane),
2816                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2817         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2818                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2819         } else {
2820                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2821                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2822         }
2823         POSTING_READ(reg);
2824 }
2825 
2826 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2827                               uint64_t fb_modifier, uint32_t pixel_format)
2828 {
2829         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2830                 return 64;
2831         } else {
2832                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2833 
2834                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2835         }
2836 }
2837 
2838 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2839                            struct drm_i915_gem_object *obj,
2840                            unsigned int plane)
2841 {
2842         struct i915_ggtt_view view;
2843         struct i915_vma *vma;
2844         u64 offset;
2845 
2846         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2847                                 intel_plane->base.state->rotation);
2848 
2849         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2850         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2851                 view.type))
2852                 return -1;
2853 
2854         offset = vma->node.start;
2855 
2856         if (plane == 1) {
2857                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2858                           PAGE_SIZE;
2859         }
2860 
2861         WARN_ON(upper_32_bits(offset));
2862 
2863         return lower_32_bits(offset);
2864 }
2865 
2866 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2867 {
2868         struct drm_device *dev = intel_crtc->base.dev;
2869         struct drm_i915_private *dev_priv = to_i915(dev);
2870 
2871         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2872         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2873         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2874 }
2875 
2876 /*
2877  * This function detaches (aka. unbinds) unused scalers in hardware
2878  */
2879 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2880 {
2881         struct intel_crtc_scaler_state *scaler_state;
2882         int i;
2883 
2884         scaler_state = &intel_crtc->config->scaler_state;
2885 
2886         /* loop through and disable scalers that aren't in use */
2887         for (i = 0; i < intel_crtc->num_scalers; i++) {
2888                 if (!scaler_state->scalers[i].in_use)
2889                         skl_detach_scaler(intel_crtc, i);
2890         }
2891 }
2892 
2893 u32 skl_plane_ctl_format(uint32_t pixel_format)
2894 {
2895         switch (pixel_format) {
2896         case DRM_FORMAT_C8:
2897                 return PLANE_CTL_FORMAT_INDEXED;
2898         case DRM_FORMAT_RGB565:
2899                 return PLANE_CTL_FORMAT_RGB_565;
2900         case DRM_FORMAT_XBGR8888:
2901                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2902         case DRM_FORMAT_XRGB8888:
2903                 return PLANE_CTL_FORMAT_XRGB_8888;
2904         /*
2905          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2906          * to be already pre-multiplied. We need to add a knob (or a different
2907          * DRM_FORMAT) for user-space to configure that.
2908          */
2909         case DRM_FORMAT_ABGR8888:
2910                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2911                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2912         case DRM_FORMAT_ARGB8888:
2913                 return PLANE_CTL_FORMAT_XRGB_8888 |
2914                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2915         case DRM_FORMAT_XRGB2101010:
2916                 return PLANE_CTL_FORMAT_XRGB_2101010;
2917         case DRM_FORMAT_XBGR2101010:
2918                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2919         case DRM_FORMAT_YUYV:
2920                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2921         case DRM_FORMAT_YVYU:
2922                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2923         case DRM_FORMAT_UYVY:
2924                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2925         case DRM_FORMAT_VYUY:
2926                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2927         default:
2928                 MISSING_CASE(pixel_format);
2929         }
2930 
2931         return 0;
2932 }
2933 
2934 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2935 {
2936         switch (fb_modifier) {
2937         case DRM_FORMAT_MOD_NONE:
2938                 break;
2939         case I915_FORMAT_MOD_X_TILED:
2940                 return PLANE_CTL_TILED_X;
2941         case I915_FORMAT_MOD_Y_TILED:
2942                 return PLANE_CTL_TILED_Y;
2943         case I915_FORMAT_MOD_Yf_TILED:
2944                 return PLANE_CTL_TILED_YF;
2945         default:
2946                 MISSING_CASE(fb_modifier);
2947         }
2948 
2949         return 0;
2950 }
2951 
2952 u32 skl_plane_ctl_rotation(unsigned int rotation)
2953 {
2954         switch (rotation) {
2955         case BIT(DRM_ROTATE_0):
2956                 break;
2957         /*
2958          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2959          * while i915 HW rotation is clockwise, thats why this swapping.
2960          */
2961         case BIT(DRM_ROTATE_90):
2962                 return PLANE_CTL_ROTATE_270;
2963         case BIT(DRM_ROTATE_180):
2964                 return PLANE_CTL_ROTATE_180;
2965         case BIT(DRM_ROTATE_270):
2966                 return PLANE_CTL_ROTATE_90;
2967         default:
2968                 MISSING_CASE(rotation);
2969         }
2970 
2971         return 0;
2972 }
2973 
2974 static void skylake_update_primary_plane(struct drm_plane *plane,
2975                                          const struct intel_crtc_state *crtc_state,
2976                                          const struct intel_plane_state *plane_state)
2977 {
2978         struct drm_device *dev = plane->dev;
2979         struct drm_i915_private *dev_priv = to_i915(dev);
2980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2981         struct drm_framebuffer *fb = plane_state->base.fb;
2982         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2983         int pipe = intel_crtc->pipe;
2984         u32 plane_ctl, stride_div, stride;
2985         u32 tile_height, plane_offset, plane_size;
2986         unsigned int rotation = plane_state->base.rotation;
2987         int x_offset, y_offset;
2988         u32 surf_addr;
2989         int scaler_id = plane_state->scaler_id;
2990         int src_x = plane_state->src.x1 >> 16;
2991         int src_y = plane_state->src.y1 >> 16;
2992         int src_w = drm_rect_width(&plane_state->src) >> 16;
2993         int src_h = drm_rect_height(&plane_state->src) >> 16;
2994         int dst_x = plane_state->dst.x1;
2995         int dst_y = plane_state->dst.y1;
2996         int dst_w = drm_rect_width(&plane_state->dst);
2997         int dst_h = drm_rect_height(&plane_state->dst);
2998 
2999         plane_ctl = PLANE_CTL_ENABLE |
3000                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3001                     PLANE_CTL_PIPE_CSC_ENABLE;
3002 
3003         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3004         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3005         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3006         plane_ctl |= skl_plane_ctl_rotation(rotation);
3007 
3008         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3009                                                fb->pixel_format);
3010         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3011 
3012         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3013 
3014         if (intel_rotation_90_or_270(rotation)) {
3015                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3016 
3017                 /* stride = Surface height in tiles */
3018                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3019                 stride = DIV_ROUND_UP(fb->height, tile_height);
3020                 x_offset = stride * tile_height - src_y - src_h;
3021                 y_offset = src_x;
3022                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3023         } else {
3024                 stride = fb->pitches[0] / stride_div;
3025                 x_offset = src_x;
3026                 y_offset = src_y;
3027                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3028         }
3029         plane_offset = y_offset << 16 | x_offset;
3030 
3031         intel_crtc->adjusted_x = x_offset;
3032         intel_crtc->adjusted_y = y_offset;
3033 
3034         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3035         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3036         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3037         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3038 
3039         if (scaler_id >= 0) {
3040                 uint32_t ps_ctrl = 0;
3041 
3042                 WARN_ON(!dst_w || !dst_h);
3043                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3044                         crtc_state->scaler_state.scalers[scaler_id].mode;
3045                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3046                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3047                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3048                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3049                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3050         } else {
3051                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3052         }
3053 
3054         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3055 
3056         POSTING_READ(PLANE_SURF(pipe, 0));
3057 }
3058 
3059 static void skylake_disable_primary_plane(struct drm_plane *primary,
3060                                           struct drm_crtc *crtc)
3061 {
3062         struct drm_device *dev = crtc->dev;
3063         struct drm_i915_private *dev_priv = to_i915(dev);
3064         int pipe = to_intel_crtc(crtc)->pipe;
3065 
3066         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3067         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3068         POSTING_READ(PLANE_SURF(pipe, 0));
3069 }
3070 
3071 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3072 static int
3073 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3074                            int x, int y, enum mode_set_atomic state)
3075 {
3076         /* Support for kgdboc is disabled, this needs a major rework. */
3077         DRM_ERROR("legacy panic handler not supported any more.\n");
3078 
3079         return -ENODEV;
3080 }
3081 
3082 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3083 {
3084         struct intel_crtc *crtc;
3085 
3086         for_each_intel_crtc(&dev_priv->drm, crtc)
3087                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3088 }
3089 
3090 static void intel_update_primary_planes(struct drm_device *dev)
3091 {
3092         struct drm_crtc *crtc;
3093 
3094         for_each_crtc(dev, crtc) {
3095                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3096                 struct intel_plane_state *plane_state =
3097                         to_intel_plane_state(plane->base.state);
3098 
3099                 if (plane_state->visible)
3100                         plane->update_plane(&plane->base,
3101                                             to_intel_crtc_state(crtc->state),
3102                                             plane_state);
3103         }
3104 }
3105 
3106 static int
3107 __intel_display_resume(struct drm_device *dev,
3108                        struct drm_atomic_state *state)
3109 {
3110         struct drm_crtc_state *crtc_state;
3111         struct drm_crtc *crtc;
3112         int i, ret;
3113 
3114         intel_modeset_setup_hw_state(dev);
3115         i915_redisable_vga(dev);
3116 
3117         if (!state)
3118                 return 0;
3119 
3120         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3121                 /*
3122                  * Force recalculation even if we restore
3123                  * current state. With fast modeset this may not result
3124                  * in a modeset when the state is compatible.
3125                  */
3126                 crtc_state->mode_changed = true;
3127         }
3128 
3129         /* ignore any reset values/BIOS leftovers in the WM registers */
3130         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3131 
3132         ret = drm_atomic_commit(state);
3133 
3134         WARN_ON(ret == -EDEADLK);
3135         return ret;
3136 }
3137 
3138 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3139 {
3140         struct drm_device *dev = &dev_priv->drm;
3141         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3142         struct drm_atomic_state *state;
3143         int ret;
3144 
3145         /* no reset support for gen2 */
3146         if (IS_GEN2(dev_priv))
3147                 return;
3148 
3149         /*
3150          * Need mode_config.mutex so that we don't
3151          * trample ongoing ->detect() and whatnot.
3152          */
3153         mutex_lock(&dev->mode_config.mutex);
3154         drm_modeset_acquire_init(ctx, 0);
3155         while (1) {
3156                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3157                 if (ret != -EDEADLK)
3158                         break;
3159 
3160                 drm_modeset_backoff(ctx);
3161         }
3162 
3163         /* reset doesn't touch the display, but flips might get nuked anyway, */
3164         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3165                 return;
3166 
3167         /*
3168          * Disabling the crtcs gracefully seems nicer. Also the
3169          * g33 docs say we should at least disable all the planes.
3170          */
3171         state = drm_atomic_helper_duplicate_state(dev, ctx);
3172         if (IS_ERR(state)) {
3173                 ret = PTR_ERR(state);
3174                 state = NULL;
3175                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3176                 goto err;
3177         }
3178 
3179         ret = drm_atomic_helper_disable_all(dev, ctx);
3180         if (ret) {
3181                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3182                 goto err;
3183         }
3184 
3185         dev_priv->modeset_restore_state = state;
3186         state->acquire_ctx = ctx;
3187         return;
3188 
3189 err:
3190         drm_atomic_state_free(state);
3191 }
3192 
3193 void intel_finish_reset(struct drm_i915_private *dev_priv)
3194 {
3195         struct drm_device *dev = &dev_priv->drm;
3196         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3197         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3198         int ret;
3199 
3200         /*
3201          * Flips in the rings will be nuked by the reset,
3202          * so complete all pending flips so that user space
3203          * will get its events and not get stuck.
3204          */
3205         intel_complete_page_flips(dev_priv);
3206 
3207         /* no reset support for gen2 */
3208         if (IS_GEN2(dev_priv))
3209                 return;
3210 
3211         dev_priv->modeset_restore_state = NULL;
3212 
3213         /* reset doesn't touch the display */
3214         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3215                 /*
3216                  * Flips in the rings have been nuked by the reset,
3217                  * so update the base address of all primary
3218                  * planes to the the last fb to make sure we're
3219                  * showing the correct fb after a reset.
3220                  *
3221                  * FIXME: Atomic will make this obsolete since we won't schedule
3222                  * CS-based flips (which might get lost in gpu resets) any more.
3223                  */
3224                 intel_update_primary_planes(dev);
3225         } else {
3226                 /*
3227                  * The display has been reset as well,
3228                  * so need a full re-initialization.
3229                  */
3230                 intel_runtime_pm_disable_interrupts(dev_priv);
3231                 intel_runtime_pm_enable_interrupts(dev_priv);
3232 
3233                 intel_modeset_init_hw(dev);
3234 
3235                 spin_lock_irq(&dev_priv->irq_lock);
3236                 if (dev_priv->display.hpd_irq_setup)
3237                         dev_priv->display.hpd_irq_setup(dev_priv);
3238                 spin_unlock_irq(&dev_priv->irq_lock);
3239 
3240                 ret = __intel_display_resume(dev, state);
3241                 if (ret)
3242                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3243 
3244                 intel_hpd_init(dev_priv);
3245         }
3246 
3247         drm_modeset_drop_locks(ctx);
3248         drm_modeset_acquire_fini(ctx);
3249         mutex_unlock(&dev->mode_config.mutex);
3250 }
3251 
3252 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3253 {
3254         struct drm_device *dev = crtc->dev;
3255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256         unsigned reset_counter;
3257         bool pending;
3258 
3259         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3260         if (intel_crtc->reset_counter != reset_counter)
3261                 return false;
3262 
3263         spin_lock_irq(&dev->event_lock);
3264         pending = to_intel_crtc(crtc)->flip_work != NULL;
3265         spin_unlock_irq(&dev->event_lock);
3266 
3267         return pending;
3268 }
3269 
3270 static void intel_update_pipe_config(struct intel_crtc *crtc,
3271                                      struct intel_crtc_state *old_crtc_state)
3272 {
3273         struct drm_device *dev = crtc->base.dev;
3274         struct drm_i915_private *dev_priv = to_i915(dev);
3275         struct intel_crtc_state *pipe_config =
3276                 to_intel_crtc_state(crtc->base.state);
3277 
3278         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3279         crtc->base.mode = crtc->base.state->mode;
3280 
3281         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3282                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3283                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3284 
3285         /*
3286          * Update pipe size and adjust fitter if needed: the reason for this is
3287          * that in compute_mode_changes we check the native mode (not the pfit
3288          * mode) to see if we can flip rather than do a full mode set. In the
3289          * fastboot case, we'll flip, but if we don't update the pipesrc and
3290          * pfit state, we'll end up with a big fb scanned out into the wrong
3291          * sized surface.
3292          */
3293 
3294         I915_WRITE(PIPESRC(crtc->pipe),
3295                    ((pipe_config->pipe_src_w - 1) << 16) |
3296                    (pipe_config->pipe_src_h - 1));
3297 
3298         /* on skylake this is done by detaching scalers */
3299         if (INTEL_INFO(dev)->gen >= 9) {
3300                 skl_detach_scalers(crtc);
3301 
3302                 if (pipe_config->pch_pfit.enabled)
3303                         skylake_pfit_enable(crtc);
3304         } else if (HAS_PCH_SPLIT(dev)) {
3305                 if (pipe_config->pch_pfit.enabled)
3306                         ironlake_pfit_enable(crtc);
3307                 else if (old_crtc_state->pch_pfit.enabled)
3308                         ironlake_pfit_disable(crtc, true);
3309         }
3310 }
3311 
3312 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3313 {
3314         struct drm_device *dev = crtc->dev;
3315         struct drm_i915_private *dev_priv = to_i915(dev);
3316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3317         int pipe = intel_crtc->pipe;
3318         i915_reg_t reg;
3319         u32 temp;
3320 
3321         /* enable normal train */
3322         reg = FDI_TX_CTL(pipe);
3323         temp = I915_READ(reg);
3324         if (IS_IVYBRIDGE(dev)) {
3325                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3326                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3327         } else {
3328                 temp &= ~FDI_LINK_TRAIN_NONE;
3329                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3330         }
3331         I915_WRITE(reg, temp);
3332 
3333         reg = FDI_RX_CTL(pipe);
3334         temp = I915_READ(reg);
3335         if (HAS_PCH_CPT(dev)) {
3336                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3337                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3338         } else {
3339                 temp &= ~FDI_LINK_TRAIN_NONE;
3340                 temp |= FDI_LINK_TRAIN_NONE;
3341         }
3342         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3343 
3344         /* wait one idle pattern time */
3345         POSTING_READ(reg);
3346         udelay(1000);
3347 
3348         /* IVB wants error correction enabled */
3349         if (IS_IVYBRIDGE(dev))
3350                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3351                            FDI_FE_ERRC_ENABLE);
3352 }
3353 
3354 /* The FDI link training functions for ILK/Ibexpeak. */
3355 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3356 {
3357         struct drm_device *dev = crtc->dev;
3358         struct drm_i915_private *dev_priv = to_i915(dev);
3359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3360         int pipe = intel_crtc->pipe;
3361         i915_reg_t reg;
3362         u32 temp, tries;
3363 
3364         /* FDI needs bits from pipe first */
3365         assert_pipe_enabled(dev_priv, pipe);
3366 
3367         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3368            for train result */
3369         reg = FDI_RX_IMR(pipe);
3370         temp = I915_READ(reg);
3371         temp &= ~FDI_RX_SYMBOL_LOCK;
3372         temp &= ~FDI_RX_BIT_LOCK;
3373         I915_WRITE(reg, temp);
3374         I915_READ(reg);
3375         udelay(150);
3376 
3377         /* enable CPU FDI TX and PCH FDI RX */
3378         reg = FDI_TX_CTL(pipe);
3379         temp = I915_READ(reg);
3380         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3381         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3382         temp &= ~FDI_LINK_TRAIN_NONE;
3383         temp |= FDI_LINK_TRAIN_PATTERN_1;
3384         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3385 
3386         reg = FDI_RX_CTL(pipe);
3387         temp = I915_READ(reg);
3388         temp &= ~FDI_LINK_TRAIN_NONE;
3389         temp |= FDI_LINK_TRAIN_PATTERN_1;
3390         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3391 
3392         POSTING_READ(reg);
3393         udelay(150);
3394 
3395         /* Ironlake workaround, enable clock pointer after FDI enable*/
3396         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3397         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3398                    FDI_RX_PHASE_SYNC_POINTER_EN);
3399 
3400         reg = FDI_RX_IIR(pipe);
3401         for (tries = 0; tries < 5; tries++) {
3402                 temp = I915_READ(reg);
3403                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3404 
3405                 if ((temp & FDI_RX_BIT_LOCK)) {
3406                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3407                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3408                         break;
3409                 }
3410         }
3411         if (tries == 5)
3412                 DRM_ERROR("FDI train 1 fail!\n");
3413 
3414         /* Train 2 */
3415         reg = FDI_TX_CTL(pipe);
3416         temp = I915_READ(reg);
3417         temp &= ~FDI_LINK_TRAIN_NONE;
3418         temp |= FDI_LINK_TRAIN_PATTERN_2;
3419         I915_WRITE(reg, temp);
3420 
3421         reg = FDI_RX_CTL(pipe);
3422         temp = I915_READ(reg);
3423         temp &= ~FDI_LINK_TRAIN_NONE;
3424         temp |= FDI_LINK_TRAIN_PATTERN_2;
3425         I915_WRITE(reg, temp);
3426 
3427         POSTING_READ(reg);
3428         udelay(150);
3429 
3430         reg = FDI_RX_IIR(pipe);
3431         for (tries = 0; tries < 5; tries++) {
3432                 temp = I915_READ(reg);
3433                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3434 
3435                 if (temp & FDI_RX_SYMBOL_LOCK) {
3436                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3437                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3438                         break;
3439                 }
3440         }
3441         if (tries == 5)
3442                 DRM_ERROR("FDI train 2 fail!\n");
3443 
3444         DRM_DEBUG_KMS("FDI train done\n");
3445 
3446 }
3447 
3448 static const int snb_b_fdi_train_param[] = {
3449         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3450         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3451         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3452         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3453 };
3454 
3455 /* The FDI link training functions for SNB/Cougarpoint. */
3456 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3457 {
3458         struct drm_device *dev = crtc->dev;
3459         struct drm_i915_private *dev_priv = to_i915(dev);
3460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461         int pipe = intel_crtc->pipe;
3462         i915_reg_t reg;
3463         u32 temp, i, retry;
3464 
3465         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3466            for train result */
3467         reg = FDI_RX_IMR(pipe);
3468         temp = I915_READ(reg);
3469         temp &= ~FDI_RX_SYMBOL_LOCK;
3470         temp &= ~FDI_RX_BIT_LOCK;
3471         I915_WRITE(reg, temp);
3472 
3473         POSTING_READ(reg);
3474         udelay(150);
3475 
3476         /* enable CPU FDI TX and PCH FDI RX */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3480         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3481         temp &= ~FDI_LINK_TRAIN_NONE;
3482         temp |= FDI_LINK_TRAIN_PATTERN_1;
3483         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3484         /* SNB-B */
3485         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3486         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3487 
3488         I915_WRITE(FDI_RX_MISC(pipe),
3489                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3490 
3491         reg = FDI_RX_CTL(pipe);
3492         temp = I915_READ(reg);
3493         if (HAS_PCH_CPT(dev)) {
3494                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3495                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3496         } else {
3497                 temp &= ~FDI_LINK_TRAIN_NONE;
3498                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3499         }
3500         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3501 
3502         POSTING_READ(reg);
3503         udelay(150);
3504 
3505         for (i = 0; i < 4; i++) {
3506                 reg = FDI_TX_CTL(pipe);
3507                 temp = I915_READ(reg);
3508                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3509                 temp |= snb_b_fdi_train_param[i];
3510                 I915_WRITE(reg, temp);
3511 
3512                 POSTING_READ(reg);
3513                 udelay(500);
3514 
3515                 for (retry = 0; retry < 5; retry++) {
3516                         reg = FDI_RX_IIR(pipe);
3517                         temp = I915_READ(reg);
3518                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3519                         if (temp & FDI_RX_BIT_LOCK) {
3520                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3521                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3522                                 break;
3523                         }
3524                         udelay(50);
3525                 }
3526                 if (retry < 5)
3527                         break;
3528         }
3529         if (i == 4)
3530                 DRM_ERROR("FDI train 1 fail!\n");
3531 
3532         /* Train 2 */
3533         reg = FDI_TX_CTL(pipe);
3534         temp = I915_READ(reg);
3535         temp &= ~FDI_LINK_TRAIN_NONE;
3536         temp |= FDI_LINK_TRAIN_PATTERN_2;
3537         if (IS_GEN6(dev)) {
3538                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3539                 /* SNB-B */
3540                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3541         }
3542         I915_WRITE(reg, temp);
3543 
3544         reg = FDI_RX_CTL(pipe);
3545         temp = I915_READ(reg);
3546         if (HAS_PCH_CPT(dev)) {
3547                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3548                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3549         } else {
3550                 temp &= ~FDI_LINK_TRAIN_NONE;
3551                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3552         }
3553         I915_WRITE(reg, temp);
3554 
3555         POSTING_READ(reg);
3556         udelay(150);
3557 
3558         for (i = 0; i < 4; i++) {
3559                 reg = FDI_TX_CTL(pipe);
3560                 temp = I915_READ(reg);
3561                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3562                 temp |= snb_b_fdi_train_param[i];
3563                 I915_WRITE(reg, temp);
3564 
3565                 POSTING_READ(reg);
3566                 udelay(500);
3567 
3568                 for (retry = 0; retry < 5; retry++) {
3569                         reg = FDI_RX_IIR(pipe);
3570                         temp = I915_READ(reg);
3571                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3572                         if (temp & FDI_RX_SYMBOL_LOCK) {
3573                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3574                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3575                                 break;
3576                         }
3577                         udelay(50);
3578                 }
3579                 if (retry < 5)
3580                         break;
3581         }
3582         if (i == 4)
3583                 DRM_ERROR("FDI train 2 fail!\n");
3584 
3585         DRM_DEBUG_KMS("FDI train done.\n");
3586 }
3587 
3588 /* Manual link training for Ivy Bridge A0 parts */
3589 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3590 {
3591         struct drm_device *dev = crtc->dev;
3592         struct drm_i915_private *dev_priv = to_i915(dev);
3593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594         int pipe = intel_crtc->pipe;
3595         i915_reg_t reg;
3596         u32 temp, i, j;
3597 
3598         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3599            for train result */
3600         reg = FDI_RX_IMR(pipe);
3601         temp = I915_READ(reg);
3602         temp &= ~FDI_RX_SYMBOL_LOCK;
3603         temp &= ~FDI_RX_BIT_LOCK;
3604         I915_WRITE(reg, temp);
3605 
3606         POSTING_READ(reg);
3607         udelay(150);
3608 
3609         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3610                       I915_READ(FDI_RX_IIR(pipe)));
3611 
3612         /* Try each vswing and preemphasis setting twice before moving on */
3613         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3614                 /* disable first in case we need to retry */
3615                 reg = FDI_TX_CTL(pipe);
3616                 temp = I915_READ(reg);
3617                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3618                 temp &= ~FDI_TX_ENABLE;
3619                 I915_WRITE(reg, temp);
3620 
3621                 reg = FDI_RX_CTL(pipe);
3622                 temp = I915_READ(reg);
3623                 temp &= ~FDI_LINK_TRAIN_AUTO;
3624                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3625                 temp &= ~FDI_RX_ENABLE;
3626                 I915_WRITE(reg, temp);
3627 
3628                 /* enable CPU FDI TX and PCH FDI RX */
3629                 reg = FDI_TX_CTL(pipe);
3630                 temp = I915_READ(reg);
3631                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3632                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3633                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3634                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3635                 temp |= snb_b_fdi_train_param[j/2];
3636                 temp |= FDI_COMPOSITE_SYNC;
3637                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3638 
3639                 I915_WRITE(FDI_RX_MISC(pipe),
3640                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3641 
3642                 reg = FDI_RX_CTL(pipe);
3643                 temp = I915_READ(reg);
3644                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3645                 temp |= FDI_COMPOSITE_SYNC;
3646                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3647 
3648                 POSTING_READ(reg);
3649                 udelay(1); /* should be 0.5us */
3650 
3651                 for (i = 0; i < 4; i++) {
3652                         reg = FDI_RX_IIR(pipe);
3653                         temp = I915_READ(reg);
3654                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3655 
3656                         if (temp & FDI_RX_BIT_LOCK ||
3657                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3658                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3659                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3660                                               i);
3661                                 break;
3662                         }
3663                         udelay(1); /* should be 0.5us */
3664                 }
3665                 if (i == 4) {
3666                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3667                         continue;
3668                 }
3669 
3670                 /* Train 2 */
3671                 reg = FDI_TX_CTL(pipe);
3672                 temp = I915_READ(reg);
3673                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3674                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3675                 I915_WRITE(reg, temp);
3676 
3677                 reg = FDI_RX_CTL(pipe);
3678                 temp = I915_READ(reg);
3679                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3680                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3681                 I915_WRITE(reg, temp);
3682 
3683                 POSTING_READ(reg);
3684                 udelay(2); /* should be 1.5us */
3685 
3686                 for (i = 0; i < 4; i++) {
3687                         reg = FDI_RX_IIR(pipe);
3688                         temp = I915_READ(reg);
3689                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3690 
3691                         if (temp & FDI_RX_SYMBOL_LOCK ||
3692                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3693                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3694                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3695                                               i);
3696                                 goto train_done;
3697                         }
3698                         udelay(2); /* should be 1.5us */
3699                 }
3700                 if (i == 4)
3701                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3702         }
3703 
3704 train_done:
3705         DRM_DEBUG_KMS("FDI train done.\n");
3706 }
3707 
3708 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3709 {
3710         struct drm_device *dev = intel_crtc->base.dev;
3711         struct drm_i915_private *dev_priv = to_i915(dev);
3712         int pipe = intel_crtc->pipe;
3713         i915_reg_t reg;
3714         u32 temp;
3715 
3716         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3717         reg = FDI_RX_CTL(pipe);
3718         temp = I915_READ(reg);
3719         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3720         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3721         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3722         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3723 
3724         POSTING_READ(reg);
3725         udelay(200);
3726 
3727         /* Switch from Rawclk to PCDclk */
3728         temp = I915_READ(reg);
3729         I915_WRITE(reg, temp | FDI_PCDCLK);
3730 
3731         POSTING_READ(reg);
3732         udelay(200);
3733 
3734         /* Enable CPU FDI TX PLL, always on for Ironlake */
3735         reg = FDI_TX_CTL(pipe);
3736         temp = I915_READ(reg);
3737         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3738                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3739 
3740                 POSTING_READ(reg);
3741                 udelay(100);
3742         }
3743 }
3744 
3745 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3746 {
3747         struct drm_device *dev = intel_crtc->base.dev;
3748         struct drm_i915_private *dev_priv = to_i915(dev);
3749         int pipe = intel_crtc->pipe;
3750         i915_reg_t reg;
3751         u32 temp;
3752 
3753         /* Switch from PCDclk to Rawclk */
3754         reg = FDI_RX_CTL(pipe);
3755         temp = I915_READ(reg);
3756         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3757 
3758         /* Disable CPU FDI TX PLL */
3759         reg = FDI_TX_CTL(pipe);
3760         temp = I915_READ(reg);
3761         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3762 
3763         POSTING_READ(reg);
3764         udelay(100);
3765 
3766         reg = FDI_RX_CTL(pipe);
3767         temp = I915_READ(reg);
3768         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3769 
3770         /* Wait for the clocks to turn off. */
3771         POSTING_READ(reg);
3772         udelay(100);
3773 }
3774 
3775 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3776 {
3777         struct drm_device *dev = crtc->dev;
3778         struct drm_i915_private *dev_priv = to_i915(dev);
3779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3780         int pipe = intel_crtc->pipe;
3781         i915_reg_t reg;
3782         u32 temp;
3783 
3784         /* disable CPU FDI tx and PCH FDI rx */
3785         reg = FDI_TX_CTL(pipe);
3786         temp = I915_READ(reg);
3787         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3788         POSTING_READ(reg);
3789 
3790         reg = FDI_RX_CTL(pipe);
3791         temp = I915_READ(reg);
3792         temp &= ~(0x7 << 16);
3793         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3794         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3795 
3796         POSTING_READ(reg);
3797         udelay(100);
3798 
3799         /* Ironlake workaround, disable clock pointer after downing FDI */
3800         if (HAS_PCH_IBX(dev))
3801                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3802 
3803         /* still set train pattern 1 */
3804         reg = FDI_TX_CTL(pipe);
3805         temp = I915_READ(reg);
3806         temp &= ~FDI_LINK_TRAIN_NONE;
3807         temp |= FDI_LINK_TRAIN_PATTERN_1;
3808         I915_WRITE(reg, temp);
3809 
3810         reg = FDI_RX_CTL(pipe);
3811         temp = I915_READ(reg);
3812         if (HAS_PCH_CPT(dev)) {
3813                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3814                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3815         } else {
3816                 temp &= ~FDI_LINK_TRAIN_NONE;
3817                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3818         }
3819         /* BPC in FDI rx is consistent with that in PIPECONF */
3820         temp &= ~(0x07 << 16);
3821         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3822         I915_WRITE(reg, temp);
3823 
3824         POSTING_READ(reg);
3825         udelay(100);
3826 }
3827 
3828 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3829 {
3830         struct intel_crtc *crtc;
3831 
3832         /* Note that we don't need to be called with mode_config.lock here
3833          * as our list of CRTC objects is static for the lifetime of the
3834          * device and so cannot disappear as we iterate. Similarly, we can
3835          * happily treat the predicates as racy, atomic checks as userspace
3836          * cannot claim and pin a new fb without at least acquring the
3837          * struct_mutex and so serialising with us.
3838          */
3839         for_each_intel_crtc(dev, crtc) {
3840                 if (atomic_read(&crtc->unpin_work_count) == 0)
3841                         continue;
3842 
3843                 if (crtc->flip_work)
3844                         intel_wait_for_vblank(dev, crtc->pipe);
3845 
3846                 return true;
3847         }
3848 
3849         return false;
3850 }
3851 
3852 static void page_flip_completed(struct intel_crtc *intel_crtc)
3853 {
3854         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3855         struct intel_flip_work *work = intel_crtc->flip_work;
3856 
3857         intel_crtc->flip_work = NULL;
3858 
3859         if (work->event)
3860                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3861 
3862         drm_crtc_vblank_put(&intel_crtc->base);
3863 
3864         wake_up_all(&dev_priv->pending_flip_queue);
3865         queue_work(dev_priv->wq, &work->unpin_work);
3866 
3867         trace_i915_flip_complete(intel_crtc->plane,
3868                                  work->pending_flip_obj);
3869 }
3870 
3871 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3872 {
3873         struct drm_device *dev = crtc->dev;
3874         struct drm_i915_private *dev_priv = to_i915(dev);
3875         long ret;
3876 
3877         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3878 
3879         ret = wait_event_interruptible_timeout(
3880                                         dev_priv->pending_flip_queue,
3881                                         !intel_crtc_has_pending_flip(crtc),
3882                                         60*HZ);
3883 
3884         if (ret < 0)
3885                 return ret;
3886 
3887         if (ret == 0) {
3888                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3889                 struct intel_flip_work *work;
3890 
3891                 spin_lock_irq(&dev->event_lock);
3892                 work = intel_crtc->flip_work;
3893                 if (work && !is_mmio_work(work)) {
3894                         WARN_ONCE(1, "Removing stuck page flip\n");
3895                         page_flip_completed(intel_crtc);
3896                 }
3897                 spin_unlock_irq(&dev->event_lock);
3898         }
3899 
3900         return 0;
3901 }
3902 
3903 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3904 {
3905         u32 temp;
3906 
3907         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3908 
3909         mutex_lock(&dev_priv->sb_lock);
3910 
3911         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3912         temp |= SBI_SSCCTL_DISABLE;
3913         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3914 
3915         mutex_unlock(&dev_priv->sb_lock);
3916 }
3917 
3918 /* Program iCLKIP clock to the desired frequency */
3919 static void lpt_program_iclkip(struct drm_crtc *crtc)
3920 {
3921         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3922         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3923         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3924         u32 temp;
3925 
3926         lpt_disable_iclkip(dev_priv);
3927 
3928         /* The iCLK virtual clock root frequency is in MHz,
3929          * but the adjusted_mode->crtc_clock in in KHz. To get the
3930          * divisors, it is necessary to divide one by another, so we
3931          * convert the virtual clock precision to KHz here for higher
3932          * precision.
3933          */
3934         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3935                 u32 iclk_virtual_root_freq = 172800 * 1000;
3936                 u32 iclk_pi_range = 64;
3937                 u32 desired_divisor;
3938 
3939                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3940                                                     clock << auxdiv);
3941                 divsel = (desired_divisor / iclk_pi_range) - 2;
3942                 phaseinc = desired_divisor % iclk_pi_range;
3943 
3944                 /*
3945                  * Near 20MHz is a corner case which is
3946                  * out of range for the 7-bit divisor
3947                  */
3948                 if (divsel <= 0x7f)
3949                         break;
3950         }
3951 
3952         /* This should not happen with any sane values */
3953         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3954                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3955         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3956                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3957 
3958         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3959                         clock,
3960                         auxdiv,
3961                         divsel,
3962                         phasedir,
3963                         phaseinc);
3964 
3965         mutex_lock(&dev_priv->sb_lock);
3966 
3967         /* Program SSCDIVINTPHASE6 */
3968         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3969         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3970         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3971         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3972         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3973         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3974         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3975         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3976 
3977         /* Program SSCAUXDIV */
3978         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3979         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3980         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3981         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3982 
3983         /* Enable modulator and associated divider */
3984         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3985         temp &= ~SBI_SSCCTL_DISABLE;
3986         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3987 
3988         mutex_unlock(&dev_priv->sb_lock);
3989 
3990         /* Wait for initialization time */
3991         udelay(24);
3992 
3993         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3994 }
3995 
3996 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3997 {
3998         u32 divsel, phaseinc, auxdiv;
3999         u32 iclk_virtual_root_freq = 172800 * 1000;
4000         u32 iclk_pi_range = 64;
4001         u32 desired_divisor;
4002         u32 temp;
4003 
4004         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4005                 return 0;
4006 
4007         mutex_lock(&dev_priv->sb_lock);
4008 
4009         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4010         if (temp & SBI_SSCCTL_DISABLE) {
4011                 mutex_unlock(&dev_priv->sb_lock);
4012                 return 0;
4013         }
4014 
4015         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4016         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4017                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4018         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4019                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4020 
4021         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4022         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4023                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4024 
4025         mutex_unlock(&dev_priv->sb_lock);
4026 
4027         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4028 
4029         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4030                                  desired_divisor << auxdiv);
4031 }
4032 
4033 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4034                                                 enum pipe pch_transcoder)
4035 {
4036         struct drm_device *dev = crtc->base.dev;
4037         struct drm_i915_private *dev_priv = to_i915(dev);
4038         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4039 
4040         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4041                    I915_READ(HTOTAL(cpu_transcoder)));
4042         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4043                    I915_READ(HBLANK(cpu_transcoder)));
4044         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4045                    I915_READ(HSYNC(cpu_transcoder)));
4046 
4047         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4048                    I915_READ(VTOTAL(cpu_transcoder)));
4049         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4050                    I915_READ(VBLANK(cpu_transcoder)));
4051         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4052                    I915_READ(VSYNC(cpu_transcoder)));
4053         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4054                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4055 }
4056 
4057 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4058 {
4059         struct drm_i915_private *dev_priv = to_i915(dev);
4060         uint32_t temp;
4061 
4062         temp = I915_READ(SOUTH_CHICKEN1);
4063         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4064                 return;
4065 
4066         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4067         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4068 
4069         temp &= ~FDI_BC_BIFURCATION_SELECT;
4070         if (enable)
4071                 temp |= FDI_BC_BIFURCATION_SELECT;
4072 
4073         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4074         I915_WRITE(SOUTH_CHICKEN1, temp);
4075         POSTING_READ(SOUTH_CHICKEN1);
4076 }
4077 
4078 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4079 {
4080         struct drm_device *dev = intel_crtc->base.dev;
4081 
4082         switch (intel_crtc->pipe) {
4083         case PIPE_A:
4084                 break;
4085         case PIPE_B:
4086                 if (intel_crtc->config->fdi_lanes > 2)
4087                         cpt_set_fdi_bc_bifurcation(dev, false);
4088                 else
4089                         cpt_set_fdi_bc_bifurcation(dev, true);
4090 
4091                 break;
4092         case PIPE_C:
4093                 cpt_set_fdi_bc_bifurcation(dev, true);
4094 
4095                 break;
4096         default:
4097                 BUG();
4098         }
4099 }
4100 
4101 /* Return which DP Port should be selected for Transcoder DP control */
4102 static enum port
4103 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4104 {
4105         struct drm_device *dev = crtc->dev;
4106         struct intel_encoder *encoder;
4107 
4108         for_each_encoder_on_crtc(dev, crtc, encoder) {
4109                 if (encoder->type == INTEL_OUTPUT_DP ||
4110                     encoder->type == INTEL_OUTPUT_EDP)
4111                         return enc_to_dig_port(&encoder->base)->port;
4112         }
4113 
4114         return -1;
4115 }
4116 
4117 /*
4118  * Enable PCH resources required for PCH ports:
4119  *   - PCH PLLs
4120  *   - FDI training & RX/TX
4121  *   - update transcoder timings
4122  *   - DP transcoding bits
4123  *   - transcoder
4124  */
4125 static void ironlake_pch_enable(struct drm_crtc *crtc)
4126 {
4127         struct drm_device *dev = crtc->dev;
4128         struct drm_i915_private *dev_priv = to_i915(dev);
4129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130         int pipe = intel_crtc->pipe;
4131         u32 temp;
4132 
4133         assert_pch_transcoder_disabled(dev_priv, pipe);
4134 
4135         if (IS_IVYBRIDGE(dev))
4136                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4137 
4138         /* Write the TU size bits before fdi link training, so that error
4139          * detection works. */
4140         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4141                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4142 
4143         /* For PCH output, training FDI link */
4144         dev_priv->display.fdi_link_train(crtc);
4145 
4146         /* We need to program the right clock selection before writing the pixel
4147          * mutliplier into the DPLL. */
4148         if (HAS_PCH_CPT(dev)) {
4149                 u32 sel;
4150 
4151                 temp = I915_READ(PCH_DPLL_SEL);
4152                 temp |= TRANS_DPLL_ENABLE(pipe);
4153                 sel = TRANS_DPLLB_SEL(pipe);
4154                 if (intel_crtc->config->shared_dpll ==
4155                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4156                         temp |= sel;
4157                 else
4158                         temp &= ~sel;
4159                 I915_WRITE(PCH_DPLL_SEL, temp);
4160         }
4161 
4162         /* XXX: pch pll's can be enabled any time before we enable the PCH
4163          * transcoder, and we actually should do this to not upset any PCH
4164          * transcoder that already use the clock when we share it.
4165          *
4166          * Note that enable_shared_dpll tries to do the right thing, but
4167          * get_shared_dpll unconditionally resets the pll - we need that to have
4168          * the right LVDS enable sequence. */
4169         intel_enable_shared_dpll(intel_crtc);
4170 
4171         /* set transcoder timing, panel must allow it */
4172         assert_panel_unlocked(dev_priv, pipe);
4173         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4174 
4175         intel_fdi_normal_train(crtc);
4176 
4177         /* For PCH DP, enable TRANS_DP_CTL */
4178         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4179                 const struct drm_display_mode *adjusted_mode =
4180                         &intel_crtc->config->base.adjusted_mode;
4181                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4182                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4183                 temp = I915_READ(reg);
4184                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4185                           TRANS_DP_SYNC_MASK |
4186                           TRANS_DP_BPC_MASK);
4187                 temp |= TRANS_DP_OUTPUT_ENABLE;
4188                 temp |= bpc << 9; /* same format but at 11:9 */
4189 
4190                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4191                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4192                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4193                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4194 
4195                 switch (intel_trans_dp_port_sel(crtc)) {
4196                 case PORT_B:
4197                         temp |= TRANS_DP_PORT_SEL_B;
4198                         break;
4199                 case PORT_C:
4200                         temp |= TRANS_DP_PORT_SEL_C;
4201                         break;
4202                 case PORT_D:
4203                         temp |= TRANS_DP_PORT_SEL_D;
4204                         break;
4205                 default:
4206                         BUG();
4207                 }
4208 
4209                 I915_WRITE(reg, temp);
4210         }
4211 
4212         ironlake_enable_pch_transcoder(dev_priv, pipe);
4213 }
4214 
4215 static void lpt_pch_enable(struct drm_crtc *crtc)
4216 {
4217         struct drm_device *dev = crtc->dev;
4218         struct drm_i915_private *dev_priv = to_i915(dev);
4219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4221 
4222         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4223 
4224         lpt_program_iclkip(crtc);
4225 
4226         /* Set transcoder timing. */
4227         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4228 
4229         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4230 }
4231 
4232 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4233 {
4234         struct drm_i915_private *dev_priv = to_i915(dev);
4235         i915_reg_t dslreg = PIPEDSL(pipe);
4236         u32 temp;
4237 
4238         temp = I915_READ(dslreg);
4239         udelay(500);
4240         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4241                 if (wait_for(I915_READ(dslreg) != temp, 5))
4242                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4243         }
4244 }
4245 
4246 static int
4247 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4248                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4249                   int src_w, int src_h, int dst_w, int dst_h)
4250 {
4251         struct intel_crtc_scaler_state *scaler_state =
4252                 &crtc_state->scaler_state;
4253         struct intel_crtc *intel_crtc =
4254                 to_intel_crtc(crtc_state->base.crtc);
4255         int need_scaling;
4256 
4257         need_scaling = intel_rotation_90_or_270(rotation) ?
4258                 (src_h != dst_w || src_w != dst_h):
4259                 (src_w != dst_w || src_h != dst_h);
4260 
4261         /*
4262          * if plane is being disabled or scaler is no more required or force detach
4263          *  - free scaler binded to this plane/crtc
4264          *  - in order to do this, update crtc->scaler_usage
4265          *
4266          * Here scaler state in crtc_state is set free so that
4267          * scaler can be assigned to other user. Actual register
4268          * update to free the scaler is done in plane/panel-fit programming.
4269          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4270          */
4271         if (force_detach || !need_scaling) {
4272                 if (*scaler_id >= 0) {
4273                         scaler_state->scaler_users &= ~(1 << scaler_user);
4274                         scaler_state->scalers[*scaler_id].in_use = 0;
4275 
4276                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4277                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4278                                 intel_crtc->pipe, scaler_user, *scaler_id,
4279                                 scaler_state->scaler_users);
4280                         *scaler_id = -1;
4281                 }
4282                 return 0;
4283         }
4284 
4285         /* range checks */
4286         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4287                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4288 
4289                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4290                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4291                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4292                         "size is out of scaler range\n",
4293                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4294                 return -EINVAL;
4295         }
4296 
4297         /* mark this plane as a scaler user in crtc_state */
4298         scaler_state->scaler_users |= (1 << scaler_user);
4299         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4300                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4301                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4302                 scaler_state->scaler_users);
4303 
4304         return 0;
4305 }
4306 
4307 /**
4308  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4309  *
4310  * @state: crtc's scaler state
4311  *
4312  * Return
4313  *     0 - scaler_usage updated successfully
4314  *    error - requested scaling cannot be supported or other error condition
4315  */
4316 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4317 {
4318         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4319         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4320 
4321         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4322                       intel_crtc->base.base.id, intel_crtc->base.name,
4323                       intel_crtc->pipe, SKL_CRTC_INDEX);
4324 
4325         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4326                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4327                 state->pipe_src_w, state->pipe_src_h,
4328                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4329 }
4330 
4331 /**
4332  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4333  *
4334  * @state: crtc's scaler state
4335  * @plane_state: atomic plane state to update
4336  *
4337  * Return
4338  *     0 - scaler_usage updated successfully
4339  *    error - requested scaling cannot be supported or other error condition
4340  */
4341 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4342                                    struct intel_plane_state *plane_state)
4343 {
4344 
4345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4346         struct intel_plane *intel_plane =
4347                 to_intel_plane(plane_state->base.plane);
4348         struct drm_framebuffer *fb = plane_state->base.fb;
4349         int ret;
4350 
4351         bool force_detach = !fb || !plane_state->visible;
4352 
4353         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4354                       intel_plane->base.base.id, intel_plane->base.name,
4355                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4356 
4357         ret = skl_update_scaler(crtc_state, force_detach,
4358                                 drm_plane_index(&intel_plane->base),
4359                                 &plane_state->scaler_id,
4360                                 plane_state->base.rotation,
4361                                 drm_rect_width(&plane_state->src) >> 16,
4362                                 drm_rect_height(&plane_state->src) >> 16,
4363                                 drm_rect_width(&plane_state->dst),
4364                                 drm_rect_height(&plane_state->dst));
4365 
4366         if (ret || plane_state->scaler_id < 0)
4367                 return ret;
4368 
4369         /* check colorkey */
4370         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4371                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4372                               intel_plane->base.base.id,
4373                               intel_plane->base.name);
4374                 return -EINVAL;
4375         }
4376 
4377         /* Check src format */
4378         switch (fb->pixel_format) {
4379         case DRM_FORMAT_RGB565:
4380         case DRM_FORMAT_XBGR8888:
4381         case DRM_FORMAT_XRGB8888:
4382         case DRM_FORMAT_ABGR8888:
4383         case DRM_FORMAT_ARGB8888:
4384         case DRM_FORMAT_XRGB2101010:
4385         case DRM_FORMAT_XBGR2101010:
4386         case DRM_FORMAT_YUYV:
4387         case DRM_FORMAT_YVYU:
4388         case DRM_FORMAT_UYVY:
4389         case DRM_FORMAT_VYUY:
4390                 break;
4391         default:
4392                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4393                               intel_plane->base.base.id, intel_plane->base.name,
4394                               fb->base.id, fb->pixel_format);
4395                 return -EINVAL;
4396         }
4397 
4398         return 0;
4399 }
4400 
4401 static void skylake_scaler_disable(struct intel_crtc *crtc)
4402 {
4403         int i;
4404 
4405         for (i = 0; i < crtc->num_scalers; i++)
4406                 skl_detach_scaler(crtc, i);
4407 }
4408 
4409 static void skylake_pfit_enable(struct intel_crtc *crtc)
4410 {
4411         struct drm_device *dev = crtc->base.dev;
4412         struct drm_i915_private *dev_priv = to_i915(dev);
4413         int pipe = crtc->pipe;
4414         struct intel_crtc_scaler_state *scaler_state =
4415                 &crtc->config->scaler_state;
4416 
4417         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4418 
4419         if (crtc->config->pch_pfit.enabled) {
4420                 int id;
4421 
4422                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4423                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4424                         return;
4425                 }
4426 
4427                 id = scaler_state->scaler_id;
4428                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4429                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4430                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4431                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4432 
4433                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4434         }
4435 }
4436 
4437 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = to_i915(dev);
4441         int pipe = crtc->pipe;
4442 
4443         if (crtc->config->pch_pfit.enabled) {
4444                 /* Force use of hard-coded filter coefficients
4445                  * as some pre-programmed values are broken,
4446                  * e.g. x201.
4447                  */
4448                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4449                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4450                                                  PF_PIPE_SEL_IVB(pipe));
4451                 else
4452                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4453                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4454                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4455         }
4456 }
4457 
4458 void hsw_enable_ips(struct intel_crtc *crtc)
4459 {
4460         struct drm_device *dev = crtc->base.dev;
4461         struct drm_i915_private *dev_priv = to_i915(dev);
4462 
4463         if (!crtc->config->ips_enabled)
4464                 return;
4465 
4466         /*
4467          * We can only enable IPS after we enable a plane and wait for a vblank
4468          * This function is called from post_plane_update, which is run after
4469          * a vblank wait.
4470          */
4471 
4472         assert_plane_enabled(dev_priv, crtc->plane);
4473         if (IS_BROADWELL(dev)) {
4474                 mutex_lock(&dev_priv->rps.hw_lock);
4475                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4476                 mutex_unlock(&dev_priv->rps.hw_lock);
4477                 /* Quoting Art Runyan: "its not safe to expect any particular
4478                  * value in IPS_CTL bit 31 after enabling IPS through the
4479                  * mailbox." Moreover, the mailbox may return a bogus state,
4480                  * so we need to just enable it and continue on.
4481                  */
4482         } else {
4483                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4484                 /* The bit only becomes 1 in the next vblank, so this wait here
4485                  * is essentially intel_wait_for_vblank. If we don't have this
4486                  * and don't wait for vblanks until the end of crtc_enable, then
4487                  * the HW state readout code will complain that the expected
4488                  * IPS_CTL value is not the one we read. */
4489                 if (intel_wait_for_register(dev_priv,
4490                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4491                                             50))
4492                         DRM_ERROR("Timed out waiting for IPS enable\n");
4493         }
4494 }
4495 
4496 void hsw_disable_ips(struct intel_crtc *crtc)
4497 {
4498         struct drm_device *dev = crtc->base.dev;
4499         struct drm_i915_private *dev_priv = to_i915(dev);
4500 
4501         if (!crtc->config->ips_enabled)
4502                 return;
4503 
4504         assert_plane_enabled(dev_priv, crtc->plane);
4505         if (IS_BROADWELL(dev)) {
4506                 mutex_lock(&dev_priv->rps.hw_lock);
4507                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4508                 mutex_unlock(&dev_priv->rps.hw_lock);
4509                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4510                 if (intel_wait_for_register(dev_priv,
4511                                             IPS_CTL, IPS_ENABLE, 0,
4512                                             42))
4513                         DRM_ERROR("Timed out waiting for IPS disable\n");
4514         } else {
4515                 I915_WRITE(IPS_CTL, 0);
4516                 POSTING_READ(IPS_CTL);
4517         }
4518 
4519         /* We need to wait for a vblank before we can disable the plane. */
4520         intel_wait_for_vblank(dev, crtc->pipe);
4521 }
4522 
4523 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4524 {
4525         if (intel_crtc->overlay) {
4526                 struct drm_device *dev = intel_crtc->base.dev;
4527                 struct drm_i915_private *dev_priv = to_i915(dev);
4528 
4529                 mutex_lock(&dev->struct_mutex);
4530                 dev_priv->mm.interruptible = false;
4531                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4532                 dev_priv->mm.interruptible = true;
4533                 mutex_unlock(&dev->struct_mutex);
4534         }
4535 
4536         /* Let userspace switch the overlay on again. In most cases userspace
4537          * has to recompute where to put it anyway.
4538          */
4539 }
4540 
4541 /**
4542  * intel_post_enable_primary - Perform operations after enabling primary plane
4543  * @crtc: the CRTC whose primary plane was just enabled
4544  *
4545  * Performs potentially sleeping operations that must be done after the primary
4546  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4547  * called due to an explicit primary plane update, or due to an implicit
4548  * re-enable that is caused when a sprite plane is updated to no longer
4549  * completely hide the primary plane.
4550  */
4551 static void
4552 intel_post_enable_primary(struct drm_crtc *crtc)
4553 {
4554         struct drm_device *dev = crtc->dev;
4555         struct drm_i915_private *dev_priv = to_i915(dev);
4556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4557         int pipe = intel_crtc->pipe;
4558 
4559         /*
4560          * FIXME IPS should be fine as long as one plane is
4561          * enabled, but in practice it seems to have problems
4562          * when going from primary only to sprite only and vice
4563          * versa.
4564          */
4565         hsw_enable_ips(intel_crtc);
4566 
4567         /*
4568          * Gen2 reports pipe underruns whenever all planes are disabled.
4569          * So don't enable underrun reporting before at least some planes
4570          * are enabled.
4571          * FIXME: Need to fix the logic to work when we turn off all planes
4572          * but leave the pipe running.
4573          */
4574         if (IS_GEN2(dev))
4575                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4576 
4577         /* Underruns don't always raise interrupts, so check manually. */
4578         intel_check_cpu_fifo_underruns(dev_priv);
4579         intel_check_pch_fifo_underruns(dev_priv);
4580 }
4581 
4582 /* FIXME move all this to pre_plane_update() with proper state tracking */
4583 static void
4584 intel_pre_disable_primary(struct drm_crtc *crtc)
4585 {
4586         struct drm_device *dev = crtc->dev;
4587         struct drm_i915_private *dev_priv = to_i915(dev);
4588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4589         int pipe = intel_crtc->pipe;
4590 
4591         /*
4592          * Gen2 reports pipe underruns whenever all planes are disabled.
4593          * So diasble underrun reporting before all the planes get disabled.
4594          * FIXME: Need to fix the logic to work when we turn off all planes
4595          * but leave the pipe running.
4596          */
4597         if (IS_GEN2(dev))
4598                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4599 
4600         /*
4601          * FIXME IPS should be fine as long as one plane is
4602          * enabled, but in practice it seems to have problems
4603          * when going from primary only to sprite only and vice
4604          * versa.
4605          */
4606         hsw_disable_ips(intel_crtc);
4607 }
4608 
4609 /* FIXME get rid of this and use pre_plane_update */
4610 static void
4611 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4612 {
4613         struct drm_device *dev = crtc->dev;
4614         struct drm_i915_private *dev_priv = to_i915(dev);
4615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4616         int pipe = intel_crtc->pipe;
4617 
4618         intel_pre_disable_primary(crtc);
4619 
4620         /*
4621          * Vblank time updates from the shadow to live plane control register
4622          * are blocked if the memory self-refresh mode is active at that
4623          * moment. So to make sure the plane gets truly disabled, disable
4624          * first the self-refresh mode. The self-refresh enable bit in turn
4625          * will be checked/applied by the HW only at the next frame start
4626          * event which is after the vblank start event, so we need to have a
4627          * wait-for-vblank between disabling the plane and the pipe.
4628          */
4629         if (HAS_GMCH_DISPLAY(dev)) {
4630                 intel_set_memory_cxsr(dev_priv, false);
4631                 dev_priv->wm.vlv.cxsr = false;
4632                 intel_wait_for_vblank(dev, pipe);
4633         }
4634 }
4635 
4636 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4637 {
4638         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4639         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4640         struct intel_crtc_state *pipe_config =
4641                 to_intel_crtc_state(crtc->base.state);
4642         struct drm_device *dev = crtc->base.dev;
4643         struct drm_plane *primary = crtc->base.primary;
4644         struct drm_plane_state *old_pri_state =
4645                 drm_atomic_get_existing_plane_state(old_state, primary);
4646 
4647         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4648 
4649         crtc->wm.cxsr_allowed = true;
4650 
4651         if (pipe_config->update_wm_post && pipe_config->base.active)
4652                 intel_update_watermarks(&crtc->base);
4653 
4654         if (old_pri_state) {
4655                 struct intel_plane_state *primary_state =
4656                         to_intel_plane_state(primary->state);
4657                 struct intel_plane_state *old_primary_state =
4658                         to_intel_plane_state(old_pri_state);
4659 
4660                 intel_fbc_post_update(crtc);
4661 
4662                 if (primary_state->visible &&
4663                     (needs_modeset(&pipe_config->base) ||
4664                      !old_primary_state->visible))
4665                         intel_post_enable_primary(&crtc->base);
4666         }
4667 }
4668 
4669 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4670 {
4671         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4672         struct drm_device *dev = crtc->base.dev;
4673         struct drm_i915_private *dev_priv = to_i915(dev);
4674         struct intel_crtc_state *pipe_config =
4675                 to_intel_crtc_state(crtc->base.state);
4676         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4677         struct drm_plane *primary = crtc->base.primary;
4678         struct drm_plane_state *old_pri_state =
4679                 drm_atomic_get_existing_plane_state(old_state, primary);
4680         bool modeset = needs_modeset(&pipe_config->base);
4681 
4682         if (old_pri_state) {
4683                 struct intel_plane_state *primary_state =
4684                         to_intel_plane_state(primary->state);
4685                 struct intel_plane_state *old_primary_state =
4686                         to_intel_plane_state(old_pri_state);
4687 
4688                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4689 
4690                 if (old_primary_state->visible &&
4691                     (modeset || !primary_state->visible))
4692                         intel_pre_disable_primary(&crtc->base);
4693         }
4694 
4695         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4696                 crtc->wm.cxsr_allowed = false;
4697 
4698                 /*
4699                  * Vblank time updates from the shadow to live plane control register
4700                  * are blocked if the memory self-refresh mode is active at that
4701                  * moment. So to make sure the plane gets truly disabled, disable
4702                  * first the self-refresh mode. The self-refresh enable bit in turn
4703                  * will be checked/applied by the HW only at the next frame start
4704                  * event which is after the vblank start event, so we need to have a
4705                  * wait-for-vblank between disabling the plane and the pipe.
4706                  */
4707                 if (old_crtc_state->base.active) {
4708                         intel_set_memory_cxsr(dev_priv, false);
4709                         dev_priv->wm.vlv.cxsr = false;
4710                         intel_wait_for_vblank(dev, crtc->pipe);
4711                 }
4712         }
4713 
4714         /*
4715          * IVB workaround: must disable low power watermarks for at least
4716          * one frame before enabling scaling.  LP watermarks can be re-enabled
4717          * when scaling is disabled.
4718          *
4719          * WaCxSRDisabledForSpriteScaling:ivb
4720          */
4721         if (pipe_config->disable_lp_wm) {
4722                 ilk_disable_lp_wm(dev);
4723                 intel_wait_for_vblank(dev, crtc->pipe);
4724         }
4725 
4726         /*
4727          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4728          * watermark programming here.
4729          */
4730         if (needs_modeset(&pipe_config->base))
4731                 return;
4732 
4733         /*
4734          * For platforms that support atomic watermarks, program the
4735          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4736          * will be the intermediate values that are safe for both pre- and
4737          * post- vblank; when vblank happens, the 'active' values will be set
4738          * to the final 'target' values and we'll do this again to get the
4739          * optimal watermarks.  For gen9+ platforms, the values we program here
4740          * will be the final target values which will get automatically latched
4741          * at vblank time; no further programming will be necessary.
4742          *
4743          * If a platform hasn't been transitioned to atomic watermarks yet,
4744          * we'll continue to update watermarks the old way, if flags tell
4745          * us to.
4746          */
4747         if (dev_priv->display.initial_watermarks != NULL)
4748                 dev_priv->display.initial_watermarks(pipe_config);
4749         else if (pipe_config->update_wm_pre)
4750                 intel_update_watermarks(&crtc->base);
4751 }
4752 
4753 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4754 {
4755         struct drm_device *dev = crtc->dev;
4756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4757         struct drm_plane *p;
4758         int pipe = intel_crtc->pipe;
4759 
4760         intel_crtc_dpms_overlay_disable(intel_crtc);
4761 
4762         drm_for_each_plane_mask(p, dev, plane_mask)
4763                 to_intel_plane(p)->disable_plane(p, crtc);
4764 
4765         /*
4766          * FIXME: Once we grow proper nuclear flip support out of this we need
4767          * to compute the mask of flip planes precisely. For the time being
4768          * consider this a flip to a NULL plane.
4769          */
4770         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4771 }
4772 
4773 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4774 {
4775         struct drm_device *dev = crtc->dev;
4776         struct drm_i915_private *dev_priv = to_i915(dev);
4777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778         struct intel_encoder *encoder;
4779         int pipe = intel_crtc->pipe;
4780         struct intel_crtc_state *pipe_config =
4781                 to_intel_crtc_state(crtc->state);
4782 
4783         if (WARN_ON(intel_crtc->active))
4784                 return;
4785 
4786         /*
4787          * Sometimes spurious CPU pipe underruns happen during FDI
4788          * training, at least with VGA+HDMI cloning. Suppress them.
4789          *
4790          * On ILK we get an occasional spurious CPU pipe underruns
4791          * between eDP port A enable and vdd enable. Also PCH port
4792          * enable seems to result in the occasional CPU pipe underrun.
4793          *
4794          * Spurious PCH underruns also occur during PCH enabling.
4795          */
4796         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4797                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4798         if (intel_crtc->config->has_pch_encoder)
4799                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4800 
4801         if (intel_crtc->config->has_pch_encoder)
4802                 intel_prepare_shared_dpll(intel_crtc);
4803 
4804         if (intel_crtc_has_dp_encoder(intel_crtc->config))
4805                 intel_dp_set_m_n(intel_crtc, M1_N1);
4806 
4807         intel_set_pipe_timings(intel_crtc);
4808         intel_set_pipe_src_size(intel_crtc);
4809 
4810         if (intel_crtc->config->has_pch_encoder) {
4811                 intel_cpu_transcoder_set_m_n(intel_crtc,
4812                                      &intel_crtc->config->fdi_m_n, NULL);
4813         }
4814 
4815         ironlake_set_pipeconf(crtc);
4816 
4817         intel_crtc->active = true;
4818 
4819         for_each_encoder_on_crtc(dev, crtc, encoder)
4820                 if (encoder->pre_enable)
4821                         encoder->pre_enable(encoder);
4822 
4823         if (intel_crtc->config->has_pch_encoder) {
4824                 /* Note: FDI PLL enabling _must_ be done before we enable the
4825                  * cpu pipes, hence this is separate from all the other fdi/pch
4826                  * enabling. */
4827                 ironlake_fdi_pll_enable(intel_crtc);
4828         } else {
4829                 assert_fdi_tx_disabled(dev_priv, pipe);
4830                 assert_fdi_rx_disabled(dev_priv, pipe);
4831         }
4832 
4833         ironlake_pfit_enable(intel_crtc);
4834 
4835         /*
4836          * On ILK+ LUT must be loaded before the pipe is running but with
4837          * clocks enabled
4838          */
4839         intel_color_load_luts(&pipe_config->base);
4840 
4841         if (dev_priv->display.initial_watermarks != NULL)
4842                 dev_priv->display.initial_watermarks(intel_crtc->config);
4843         intel_enable_pipe(intel_crtc);
4844 
4845         if (intel_crtc->config->has_pch_encoder)
4846                 ironlake_pch_enable(crtc);
4847 
4848         assert_vblank_disabled(crtc);
4849         drm_crtc_vblank_on(crtc);
4850 
4851         for_each_encoder_on_crtc(dev, crtc, encoder)
4852                 encoder->enable(encoder);
4853 
4854         if (HAS_PCH_CPT(dev))
4855                 cpt_verify_modeset(dev, intel_crtc->pipe);
4856 
4857         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4858         if (intel_crtc->config->has_pch_encoder)
4859                 intel_wait_for_vblank(dev, pipe);
4860         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4861         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4862 }
4863 
4864 /* IPS only exists on ULT machines and is tied to pipe A. */
4865 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4866 {
4867         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4868 }
4869 
4870 static void haswell_crtc_enable(struct drm_crtc *crtc)
4871 {
4872         struct drm_device *dev = crtc->dev;
4873         struct drm_i915_private *dev_priv = to_i915(dev);
4874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875         struct intel_encoder *encoder;
4876         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4877         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4878         struct intel_crtc_state *pipe_config =
4879                 to_intel_crtc_state(crtc->state);
4880 
4881         if (WARN_ON(intel_crtc->active))
4882                 return;
4883 
4884         if (intel_crtc->config->has_pch_encoder)
4885                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4886                                                       false);
4887 
4888         for_each_encoder_on_crtc(dev, crtc, encoder)
4889                 if (encoder->pre_pll_enable)
4890                         encoder->pre_pll_enable(encoder);
4891 
4892         if (intel_crtc->config->shared_dpll)
4893                 intel_enable_shared_dpll(intel_crtc);
4894 
4895         if (intel_crtc_has_dp_encoder(intel_crtc->config))
4896                 intel_dp_set_m_n(intel_crtc, M1_N1);
4897 
4898         if (!transcoder_is_dsi(cpu_transcoder))
4899                 intel_set_pipe_timings(intel_crtc);
4900 
4901         intel_set_pipe_src_size(intel_crtc);
4902 
4903         if (cpu_transcoder != TRANSCODER_EDP &&
4904             !transcoder_is_dsi(cpu_transcoder)) {
4905                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4906                            intel_crtc->config->pixel_multiplier - 1);
4907         }
4908 
4909         if (intel_crtc->config->has_pch_encoder) {
4910                 intel_cpu_transcoder_set_m_n(intel_crtc,
4911                                      &intel_crtc->config->fdi_m_n, NULL);
4912         }
4913 
4914         if (!transcoder_is_dsi(cpu_transcoder))
4915                 haswell_set_pipeconf(crtc);
4916 
4917         haswell_set_pipemisc(crtc);
4918 
4919         intel_color_set_csc(&pipe_config->base);
4920 
4921         intel_crtc->active = true;
4922 
4923         if (intel_crtc->config->has_pch_encoder)
4924                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4925         else
4926                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4927 
4928         for_each_encoder_on_crtc(dev, crtc, encoder) {
4929                 if (encoder->pre_enable)
4930                         encoder->pre_enable(encoder);
4931         }
4932 
4933         if (intel_crtc->config->has_pch_encoder)
4934                 dev_priv->display.fdi_link_train(crtc);
4935 
4936         if (!transcoder_is_dsi(cpu_transcoder))
4937                 intel_ddi_enable_pipe_clock(intel_crtc);
4938 
4939         if (INTEL_INFO(dev)->gen >= 9)
4940                 skylake_pfit_enable(intel_crtc);
4941         else
4942                 ironlake_pfit_enable(intel_crtc);
4943 
4944         /*
4945          * On ILK+ LUT must be loaded before the pipe is running but with
4946          * clocks enabled
4947          */
4948         intel_color_load_luts(&pipe_config->base);
4949 
4950         intel_ddi_set_pipe_settings(crtc);
4951         if (!transcoder_is_dsi(cpu_transcoder))
4952                 intel_ddi_enable_transcoder_func(crtc);
4953 
4954         if (dev_priv->display.initial_watermarks != NULL)
4955                 dev_priv->display.initial_watermarks(pipe_config);
4956         else
4957                 intel_update_watermarks(crtc);
4958 
4959         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4960         if (!transcoder_is_dsi(cpu_transcoder))
4961                 intel_enable_pipe(intel_crtc);
4962 
4963         if (intel_crtc->config->has_pch_encoder)
4964                 lpt_pch_enable(crtc);
4965 
4966         if (intel_crtc->config->dp_encoder_is_mst)
4967                 intel_ddi_set_vc_payload_alloc(crtc, true);
4968 
4969         assert_vblank_disabled(crtc);
4970         drm_crtc_vblank_on(crtc);
4971 
4972         for_each_encoder_on_crtc(dev, crtc, encoder) {
4973                 encoder->enable(encoder);
4974                 intel_opregion_notify_encoder(encoder, true);
4975         }
4976 
4977         if (intel_crtc->config->has_pch_encoder) {
4978                 intel_wait_for_vblank(dev, pipe);
4979                 intel_wait_for_vblank(dev, pipe);
4980                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4981                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4982                                                       true);
4983         }
4984 
4985         /* If we change the relative order between pipe/planes enabling, we need
4986          * to change the workaround. */
4987         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4988         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4989                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4991         }
4992 }
4993 
4994 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4995 {
4996         struct drm_device *dev = crtc->base.dev;
4997         struct drm_i915_private *dev_priv = to_i915(dev);
4998         int pipe = crtc->pipe;
4999 
5000         /* To avoid upsetting the power well on haswell only disable the pfit if
5001          * it's in use. The hw state code will make sure we get this right. */
5002         if (force || crtc->config->pch_pfit.enabled) {
5003                 I915_WRITE(PF_CTL(pipe), 0);
5004                 I915_WRITE(PF_WIN_POS(pipe), 0);
5005                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5006         }
5007 }
5008 
5009 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5010 {
5011         struct drm_device *dev = crtc->dev;
5012         struct drm_i915_private *dev_priv = to_i915(dev);
5013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014         struct intel_encoder *encoder;
5015         int pipe = intel_crtc->pipe;
5016 
5017         /*
5018          * Sometimes spurious CPU pipe underruns happen when the
5019          * pipe is already disabled, but FDI RX/TX is still enabled.
5020          * Happens at least with VGA+HDMI cloning. Suppress them.
5021          */
5022         if (intel_crtc->config->has_pch_encoder) {
5023                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5024                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5025         }
5026 
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 encoder->disable(encoder);
5029 
5030         drm_crtc_vblank_off(crtc);
5031         assert_vblank_disabled(crtc);
5032 
5033         intel_disable_pipe(intel_crtc);
5034 
5035         ironlake_pfit_disable(intel_crtc, false);
5036 
5037         if (intel_crtc->config->has_pch_encoder)
5038                 ironlake_fdi_disable(crtc);
5039 
5040         for_each_encoder_on_crtc(dev, crtc, encoder)
5041                 if (encoder->post_disable)
5042                         encoder->post_disable(encoder);
5043 
5044         if (intel_crtc->config->has_pch_encoder) {
5045                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5046 
5047                 if (HAS_PCH_CPT(dev)) {
5048                         i915_reg_t reg;
5049                         u32 temp;
5050 
5051                         /* disable TRANS_DP_CTL */
5052                         reg = TRANS_DP_CTL(pipe);
5053                         temp = I915_READ(reg);
5054                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5055                                   TRANS_DP_PORT_SEL_MASK);
5056                         temp |= TRANS_DP_PORT_SEL_NONE;
5057                         I915_WRITE(reg, temp);
5058 
5059                         /* disable DPLL_SEL */
5060                         temp = I915_READ(PCH_DPLL_SEL);
5061                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5062                         I915_WRITE(PCH_DPLL_SEL, temp);
5063                 }
5064 
5065                 ironlake_fdi_pll_disable(intel_crtc);
5066         }
5067 
5068         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5069         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5070 }
5071 
5072 static void haswell_crtc_disable(struct drm_crtc *crtc)
5073 {
5074         struct drm_device *dev = crtc->dev;
5075         struct drm_i915_private *dev_priv = to_i915(dev);
5076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5077         struct intel_encoder *encoder;
5078         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5079 
5080         if (intel_crtc->config->has_pch_encoder)
5081                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5082                                                       false);
5083 
5084         for_each_encoder_on_crtc(dev, crtc, encoder) {
5085                 intel_opregion_notify_encoder(encoder, false);
5086                 encoder->disable(encoder);
5087         }
5088 
5089         drm_crtc_vblank_off(crtc);
5090         assert_vblank_disabled(crtc);
5091 
5092         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5093         if (!transcoder_is_dsi(cpu_transcoder))
5094                 intel_disable_pipe(intel_crtc);
5095 
5096         if (intel_crtc->config->dp_encoder_is_mst)
5097                 intel_ddi_set_vc_payload_alloc(crtc, false);
5098 
5099         if (!transcoder_is_dsi(cpu_transcoder))
5100                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5101 
5102         if (INTEL_INFO(dev)->gen >= 9)
5103                 skylake_scaler_disable(intel_crtc);
5104         else
5105                 ironlake_pfit_disable(intel_crtc, false);
5106 
5107         if (!transcoder_is_dsi(cpu_transcoder))
5108                 intel_ddi_disable_pipe_clock(intel_crtc);
5109 
5110         for_each_encoder_on_crtc(dev, crtc, encoder)
5111                 if (encoder->post_disable)
5112                         encoder->post_disable(encoder);
5113 
5114         if (intel_crtc->config->has_pch_encoder) {
5115                 lpt_disable_pch_transcoder(dev_priv);
5116                 lpt_disable_iclkip(dev_priv);
5117                 intel_ddi_fdi_disable(crtc);
5118 
5119                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5120                                                       true);
5121         }
5122 }
5123 
5124 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5125 {
5126         struct drm_device *dev = crtc->base.dev;
5127         struct drm_i915_private *dev_priv = to_i915(dev);
5128         struct intel_crtc_state *pipe_config = crtc->config;
5129 
5130         if (!pipe_config->gmch_pfit.control)
5131                 return;
5132 
5133         /*
5134          * The panel fitter should only be adjusted whilst the pipe is disabled,
5135          * according to register description and PRM.
5136          */
5137         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5138         assert_pipe_disabled(dev_priv, crtc->pipe);
5139 
5140         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5141         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5142 
5143         /* Border color in case we don't scale up to the full screen. Black by
5144          * default, change to something else for debugging. */
5145         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5146 }
5147 
5148 static enum intel_display_power_domain port_to_power_domain(enum port port)
5149 {
5150         switch (port) {
5151         case PORT_A:
5152                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5153         case PORT_B:
5154                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5155         case PORT_C:
5156                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5157         case PORT_D:
5158                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5159         case PORT_E:
5160                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5161         default:
5162                 MISSING_CASE(port);
5163                 return POWER_DOMAIN_PORT_OTHER;
5164         }
5165 }
5166 
5167 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5168 {
5169         switch (port) {
5170         case PORT_A:
5171                 return POWER_DOMAIN_AUX_A;
5172         case PORT_B:
5173                 return POWER_DOMAIN_AUX_B;
5174         case PORT_C:
5175                 return POWER_DOMAIN_AUX_C;
5176         case PORT_D:
5177                 return POWER_DOMAIN_AUX_D;
5178         case PORT_E:
5179                 /* FIXME: Check VBT for actual wiring of PORT E */
5180                 return POWER_DOMAIN_AUX_D;
5181         default:
5182                 MISSING_CASE(port);
5183                 return POWER_DOMAIN_AUX_A;
5184         }
5185 }
5186 
5187 enum intel_display_power_domain
5188 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5189 {
5190         struct drm_device *dev = intel_encoder->base.dev;
5191         struct intel_digital_port *intel_dig_port;
5192 
5193         switch (intel_encoder->type) {
5194         case INTEL_OUTPUT_UNKNOWN:
5195                 /* Only DDI platforms should ever use this output type */
5196                 WARN_ON_ONCE(!HAS_DDI(dev));
5197         case INTEL_OUTPUT_DP:
5198         case INTEL_OUTPUT_HDMI:
5199         case INTEL_OUTPUT_EDP:
5200                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5201                 return port_to_power_domain(intel_dig_port->port);
5202         case INTEL_OUTPUT_DP_MST:
5203                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5204                 return port_to_power_domain(intel_dig_port->port);
5205         case INTEL_OUTPUT_ANALOG:
5206                 return POWER_DOMAIN_PORT_CRT;
5207         case INTEL_OUTPUT_DSI:
5208                 return POWER_DOMAIN_PORT_DSI;
5209         default:
5210                 return POWER_DOMAIN_PORT_OTHER;
5211         }
5212 }
5213 
5214 enum intel_display_power_domain
5215 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5216 {
5217         struct drm_device *dev = intel_encoder->base.dev;
5218         struct intel_digital_port *intel_dig_port;
5219 
5220         switch (intel_encoder->type) {
5221         case INTEL_OUTPUT_UNKNOWN:
5222         case INTEL_OUTPUT_HDMI:
5223                 /*
5224                  * Only DDI platforms should ever use these output types.
5225                  * We can get here after the HDMI detect code has already set
5226                  * the type of the shared encoder. Since we can't be sure
5227                  * what's the status of the given connectors, play safe and
5228                  * run the DP detection too.
5229                  */
5230                 WARN_ON_ONCE(!HAS_DDI(dev));
5231         case INTEL_OUTPUT_DP:
5232         case INTEL_OUTPUT_EDP:
5233                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5234                 return port_to_aux_power_domain(intel_dig_port->port);
5235         case INTEL_OUTPUT_DP_MST:
5236                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5237                 return port_to_aux_power_domain(intel_dig_port->port);
5238         default:
5239                 MISSING_CASE(intel_encoder->type);
5240                 return POWER_DOMAIN_AUX_A;
5241         }
5242 }
5243 
5244 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5245                                             struct intel_crtc_state *crtc_state)
5246 {
5247         struct drm_device *dev = crtc->dev;
5248         struct drm_encoder *encoder;
5249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5250         enum pipe pipe = intel_crtc->pipe;
5251         unsigned long mask;
5252         enum transcoder transcoder = crtc_state->cpu_transcoder;
5253 
5254         if (!crtc_state->base.active)
5255                 return 0;
5256 
5257         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5258         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5259         if (crtc_state->pch_pfit.enabled ||
5260             crtc_state->pch_pfit.force_thru)
5261                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5262 
5263         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5264                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5265 
5266                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5267         }
5268 
5269         if (crtc_state->shared_dpll)
5270                 mask |= BIT(POWER_DOMAIN_PLLS);
5271 
5272         return mask;
5273 }
5274 
5275 static unsigned long
5276 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5277                                struct intel_crtc_state *crtc_state)
5278 {
5279         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5281         enum intel_display_power_domain domain;
5282         unsigned long domains, new_domains, old_domains;
5283 
5284         old_domains = intel_crtc->enabled_power_domains;
5285         intel_crtc->enabled_power_domains = new_domains =
5286                 get_crtc_power_domains(crtc, crtc_state);
5287 
5288         domains = new_domains & ~old_domains;
5289 
5290         for_each_power_domain(domain, domains)
5291                 intel_display_power_get(dev_priv, domain);
5292 
5293         return old_domains & ~new_domains;
5294 }
5295 
5296 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5297                                       unsigned long domains)
5298 {
5299         enum intel_display_power_domain domain;
5300 
5301         for_each_power_domain(domain, domains)
5302                 intel_display_power_put(dev_priv, domain);
5303 }
5304 
5305 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5306 {
5307         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5308 
5309         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5310             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5311                 return max_cdclk_freq;
5312         else if (IS_CHERRYVIEW(dev_priv))
5313                 return max_cdclk_freq*95/100;
5314         else if (INTEL_INFO(dev_priv)->gen < 4)
5315                 return 2*max_cdclk_freq*90/100;
5316         else
5317                 return max_cdclk_freq*90/100;
5318 }
5319 
5320 static int skl_calc_cdclk(int max_pixclk, int vco);
5321 
5322 static void intel_update_max_cdclk(struct drm_device *dev)
5323 {
5324         struct drm_i915_private *dev_priv = to_i915(dev);
5325 
5326         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5327                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5328                 int max_cdclk, vco;
5329 
5330                 vco = dev_priv->skl_preferred_vco_freq;
5331                 WARN_ON(vco != 8100000 && vco != 8640000);
5332 
5333                 /*
5334                  * Use the lower (vco 8640) cdclk values as a
5335                  * first guess. skl_calc_cdclk() will correct it
5336                  * if the preferred vco is 8100 instead.
5337                  */
5338                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5339                         max_cdclk = 617143;
5340                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5341                         max_cdclk = 540000;
5342                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5343                         max_cdclk = 432000;
5344                 else
5345                         max_cdclk = 308571;
5346 
5347                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5348         } else if (IS_BROXTON(dev)) {
5349                 dev_priv->max_cdclk_freq = 624000;
5350         } else if (IS_BROADWELL(dev))  {
5351                 /*
5352                  * FIXME with extra cooling we can allow
5353                  * 540 MHz for ULX and 675 Mhz for ULT.
5354                  * How can we know if extra cooling is
5355                  * available? PCI ID, VTB, something else?
5356                  */
5357                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5358                         dev_priv->max_cdclk_freq = 450000;
5359                 else if (IS_BDW_ULX(dev))
5360                         dev_priv->max_cdclk_freq = 450000;
5361                 else if (IS_BDW_ULT(dev))
5362                         dev_priv->max_cdclk_freq = 540000;
5363                 else
5364                         dev_priv->max_cdclk_freq = 675000;
5365         } else if (IS_CHERRYVIEW(dev)) {
5366                 dev_priv->max_cdclk_freq = 320000;
5367         } else if (IS_VALLEYVIEW(dev)) {
5368                 dev_priv->max_cdclk_freq = 400000;
5369         } else {
5370                 /* otherwise assume cdclk is fixed */
5371                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5372         }
5373 
5374         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5375 
5376         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5377                          dev_priv->max_cdclk_freq);
5378 
5379         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5380                          dev_priv->max_dotclk_freq);
5381 }
5382 
5383 static void intel_update_cdclk(struct drm_device *dev)
5384 {
5385         struct drm_i915_private *dev_priv = to_i915(dev);
5386 
5387         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5388 
5389         if (INTEL_GEN(dev_priv) >= 9)
5390                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5391                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5392                                  dev_priv->cdclk_pll.ref);
5393         else
5394                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5395                                  dev_priv->cdclk_freq);
5396 
5397         /*
5398          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5399          * Programmng [sic] note: bit[9:2] should be programmed to the number
5400          * of cdclk that generates 4MHz reference clock freq which is used to
5401          * generate GMBus clock. This will vary with the cdclk freq.
5402          */
5403         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5404                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5405 }
5406 
5407 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5408 static int skl_cdclk_decimal(int cdclk)
5409 {
5410         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5411 }
5412 
5413 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5414 {
5415         int ratio;
5416 
5417         if (cdclk == dev_priv->cdclk_pll.ref)
5418                 return 0;
5419 
5420         switch (cdclk) {
5421         default:
5422                 MISSING_CASE(cdclk);
5423         case 144000:
5424         case 288000:
5425         case 384000:
5426         case 576000:
5427                 ratio = 60;
5428                 break;
5429         case 624000:
5430                 ratio = 65;
5431                 break;
5432         }
5433 
5434         return dev_priv->cdclk_pll.ref * ratio;
5435 }
5436 
5437 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5438 {
5439         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5440 
5441         /* Timeout 200us */
5442         if (intel_wait_for_register(dev_priv,
5443                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5444                                     1))
5445                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5446 
5447         dev_priv->cdclk_pll.vco = 0;
5448 }
5449 
5450 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5451 {
5452         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5453         u32 val;
5454 
5455         val = I915_READ(BXT_DE_PLL_CTL);
5456         val &= ~BXT_DE_PLL_RATIO_MASK;
5457         val |= BXT_DE_PLL_RATIO(ratio);
5458         I915_WRITE(BXT_DE_PLL_CTL, val);
5459 
5460         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5461 
5462         /* Timeout 200us */
5463         if (intel_wait_for_register(dev_priv,
5464                                     BXT_DE_PLL_ENABLE,
5465                                     BXT_DE_PLL_LOCK,
5466                                     BXT_DE_PLL_LOCK,
5467                                     1))
5468                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5469 
5470         dev_priv->cdclk_pll.vco = vco;
5471 }
5472 
5473 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5474 {
5475         u32 val, divider;
5476         int vco, ret;
5477 
5478         vco = bxt_de_pll_vco(dev_priv, cdclk);
5479 
5480         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5481 
5482         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5483         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5484         case 8:
5485                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5486                 break;
5487         case 4:
5488                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5489                 break;
5490         case 3:
5491                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5492                 break;
5493         case 2:
5494                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5495                 break;
5496         default:
5497                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5498                 WARN_ON(vco != 0);
5499 
5500                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5501                 break;
5502         }
5503 
5504         /* Inform power controller of upcoming frequency change */
5505         mutex_lock(&dev_priv->rps.hw_lock);
5506         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5507                                       0x80000000);
5508         mutex_unlock(&dev_priv->rps.hw_lock);
5509 
5510         if (ret) {
5511                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5512                           ret, cdclk);
5513                 return;
5514         }
5515 
5516         if (dev_priv->cdclk_pll.vco != 0 &&
5517             dev_priv->cdclk_pll.vco != vco)
5518                 bxt_de_pll_disable(dev_priv);
5519 
5520         if (dev_priv->cdclk_pll.vco != vco)
5521                 bxt_de_pll_enable(dev_priv, vco);
5522 
5523         val = divider | skl_cdclk_decimal(cdclk);
5524         /*
5525          * FIXME if only the cd2x divider needs changing, it could be done
5526          * without shutting off the pipe (if only one pipe is active).
5527          */
5528         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5529         /*
5530          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5531          * enable otherwise.
5532          */
5533         if (cdclk >= 500000)
5534                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5535         I915_WRITE(CDCLK_CTL, val);
5536 
5537         mutex_lock(&dev_priv->rps.hw_lock);
5538         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5539                                       DIV_ROUND_UP(cdclk, 25000));
5540         mutex_unlock(&dev_priv->rps.hw_lock);
5541 
5542         if (ret) {
5543                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5544                           ret, cdclk);
5545                 return;
5546         }
5547 
5548         intel_update_cdclk(&dev_priv->drm);
5549 }
5550 
5551 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5552 {
5553         u32 cdctl, expected;
5554 
5555         intel_update_cdclk(&dev_priv->drm);
5556 
5557         if (dev_priv->cdclk_pll.vco == 0 ||
5558             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5559                 goto sanitize;
5560 
5561         /* DPLL okay; verify the cdclock
5562          *
5563          * Some BIOS versions leave an incorrect decimal frequency value and
5564          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5565          * so sanitize this register.
5566          */
5567         cdctl = I915_READ(CDCLK_CTL);
5568         /*
5569          * Let's ignore the pipe field, since BIOS could have configured the
5570          * dividers both synching to an active pipe, or asynchronously
5571          * (PIPE_NONE).
5572          */
5573         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5574 
5575         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5576                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5577         /*
5578          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5579          * enable otherwise.
5580          */
5581         if (dev_priv->cdclk_freq >= 500000)
5582                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5583 
5584         if (cdctl == expected)
5585                 /* All well; nothing to sanitize */
5586                 return;
5587 
5588 sanitize:
5589         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5590 
5591         /* force cdclk programming */
5592         dev_priv->cdclk_freq = 0;
5593 
5594         /* force full PLL disable + enable */
5595         dev_priv->cdclk_pll.vco = -1;
5596 }
5597 
5598 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5599 {
5600         bxt_sanitize_cdclk(dev_priv);
5601 
5602         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5603                 return;
5604 
5605         /*
5606          * FIXME:
5607          * - The initial CDCLK needs to be read from VBT.
5608          *   Need to make this change after VBT has changes for BXT.
5609          */
5610         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5611 }
5612 
5613 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5614 {
5615         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5616 }
5617 
5618 static int skl_calc_cdclk(int max_pixclk, int vco)
5619 {
5620         if (vco == 8640000) {
5621                 if (max_pixclk > 540000)
5622                         return 617143;
5623                 else if (max_pixclk > 432000)
5624                         return 540000;
5625                 else if (max_pixclk > 308571)
5626                         return 432000;
5627                 else
5628                         return 308571;
5629         } else {
5630                 if (max_pixclk > 540000)
5631                         return 675000;
5632                 else if (max_pixclk > 450000)
5633                         return 540000;
5634                 else if (max_pixclk > 337500)
5635                         return 450000;
5636                 else
5637                         return 337500;
5638         }
5639 }
5640 
5641 static void
5642 skl_dpll0_update(struct drm_i915_private *dev_priv)
5643 {
5644         u32 val;
5645 
5646         dev_priv->cdclk_pll.ref = 24000;
5647         dev_priv->cdclk_pll.vco = 0;
5648 
5649         val = I915_READ(LCPLL1_CTL);
5650         if ((val & LCPLL_PLL_ENABLE) == 0)
5651                 return;
5652 
5653         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5654                 return;
5655 
5656         val = I915_READ(DPLL_CTRL1);
5657 
5658         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5659                             DPLL_CTRL1_SSC(SKL_DPLL0) |
5660                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5661                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5662                 return;
5663 
5664         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5665         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5666         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5667         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5668         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5669                 dev_priv->cdclk_pll.vco = 8100000;
5670                 break;
5671         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5672         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5673                 dev_priv->cdclk_pll.vco = 8640000;
5674                 break;
5675         default:
5676                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5677                 break;
5678         }
5679 }
5680 
5681 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5682 {
5683         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5684 
5685         dev_priv->skl_preferred_vco_freq = vco;
5686 
5687         if (changed)
5688                 intel_update_max_cdclk(&dev_priv->drm);
5689 }
5690 
5691 static void
5692 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5693 {
5694         int min_cdclk = skl_calc_cdclk(0, vco);
5695         u32 val;
5696 
5697         WARN_ON(vco != 8100000 && vco != 8640000);
5698 
5699         /* select the minimum CDCLK before enabling DPLL 0 */
5700         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5701         I915_WRITE(CDCLK_CTL, val);
5702         POSTING_READ(CDCLK_CTL);
5703 
5704         /*
5705          * We always enable DPLL0 with the lowest link rate possible, but still
5706          * taking into account the VCO required to operate the eDP panel at the
5707          * desired frequency. The usual DP link rates operate with a VCO of
5708          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5709          * The modeset code is responsible for the selection of the exact link
5710          * rate later on, with the constraint of choosing a frequency that
5711          * works with vco.
5712          */
5713         val = I915_READ(DPLL_CTRL1);
5714 
5715         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5716                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5717         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5718         if (vco == 8640000)
5719                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5720                                             SKL_DPLL0);
5721         else
5722                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5723                                             SKL_DPLL0);
5724 
5725         I915_WRITE(DPLL_CTRL1, val);
5726         POSTING_READ(DPLL_CTRL1);
5727 
5728         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5729 
5730         if (intel_wait_for_register(dev_priv,
5731                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5732                                     5))
5733                 DRM_ERROR("DPLL0 not locked\n");
5734 
5735         dev_priv->cdclk_pll.vco = vco;
5736 
5737         /* We'll want to keep using the current vco from now on. */
5738         skl_set_preferred_cdclk_vco(dev_priv, vco);
5739 }
5740 
5741 static void
5742 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5743 {
5744         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5745         if (intel_wait_for_register(dev_priv,
5746                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
5747                                    1))
5748                 DRM_ERROR("Couldn't disable DPLL0\n");
5749 
5750         dev_priv->cdclk_pll.vco = 0;
5751 }
5752 
5753 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5754 {
5755         int ret;
5756         u32 val;
5757 
5758         /* inform PCU we want to change CDCLK */
5759         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5760         mutex_lock(&dev_priv->rps.hw_lock);
5761         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5762         mutex_unlock(&dev_priv->rps.hw_lock);
5763 
5764         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5765 }
5766 
5767 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5768 {
5769         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
5770 }
5771 
5772 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5773 {
5774         struct drm_device *dev = &dev_priv->drm;
5775         u32 freq_select, pcu_ack;
5776 
5777         WARN_ON((cdclk == 24000) != (vco == 0));
5778 
5779         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5780 
5781         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5782                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5783                 return;
5784         }
5785 
5786         /* set CDCLK_CTL */
5787         switch (cdclk) {
5788         case 450000:
5789         case 432000:
5790                 freq_select = CDCLK_FREQ_450_432;
5791                 pcu_ack = 1;
5792                 break;
5793         case 540000:
5794                 freq_select = CDCLK_FREQ_540;
5795                 pcu_ack = 2;
5796                 break;
5797         case 308571:
5798         case 337500:
5799         default:
5800                 freq_select = CDCLK_FREQ_337_308;
5801                 pcu_ack = 0;
5802                 break;
5803         case 617143:
5804         case 675000:
5805                 freq_select = CDCLK_FREQ_675_617;
5806                 pcu_ack = 3;
5807                 break;
5808         }
5809 
5810         if (dev_priv->cdclk_pll.vco != 0 &&
5811             dev_priv->cdclk_pll.vco != vco)
5812                 skl_dpll0_disable(dev_priv);
5813 
5814         if (dev_priv->cdclk_pll.vco != vco)
5815                 skl_dpll0_enable(dev_priv, vco);
5816 
5817         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5818         POSTING_READ(CDCLK_CTL);
5819 
5820         /* inform PCU of the change */
5821         mutex_lock(&dev_priv->rps.hw_lock);
5822         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5823         mutex_unlock(&dev_priv->rps.hw_lock);
5824 
5825         intel_update_cdclk(dev);
5826 }
5827 
5828 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5829 
5830 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5831 {
5832         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5833 }
5834 
5835 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5836 {
5837         int cdclk, vco;
5838 
5839         skl_sanitize_cdclk(dev_priv);
5840 
5841         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5842                 /*
5843                  * Use the current vco as our initial
5844                  * guess as to what the preferred vco is.
5845                  */
5846                 if (dev_priv->skl_preferred_vco_freq == 0)
5847                         skl_set_preferred_cdclk_vco(dev_priv,
5848                                                     dev_priv->cdclk_pll.vco);
5849                 return;
5850         }
5851 
5852         vco = dev_priv->skl_preferred_vco_freq;
5853         if (vco == 0)
5854                 vco = 8100000;
5855         cdclk = skl_calc_cdclk(0, vco);
5856 
5857         skl_set_cdclk(dev_priv, cdclk, vco);
5858 }
5859 
5860 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5861 {
5862         uint32_t cdctl, expected;
5863 
5864         /*
5865          * check if the pre-os intialized the display
5866          * There is SWF18 scratchpad register defined which is set by the
5867          * pre-os which can be used by the OS drivers to check the status
5868          */
5869         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5870                 goto sanitize;
5871 
5872         intel_update_cdclk(&dev_priv->drm);
5873         /* Is PLL enabled and locked ? */
5874         if (dev_priv->cdclk_pll.vco == 0 ||
5875             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5876                 goto sanitize;
5877 
5878         /* DPLL okay; verify the cdclock
5879          *
5880          * Noticed in some instances that the freq selection is correct but
5881          * decimal part is programmed wrong from BIOS where pre-os does not
5882          * enable display. Verify the same as well.
5883          */
5884         cdctl = I915_READ(CDCLK_CTL);
5885         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5886                 skl_cdclk_decimal(dev_priv->cdclk_freq);
5887         if (cdctl == expected)
5888                 /* All well; nothing to sanitize */
5889                 return;
5890 
5891 sanitize:
5892         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5893 
5894         /* force cdclk programming */
5895         dev_priv->cdclk_freq = 0;
5896         /* force full PLL disable + enable */
5897         dev_priv->cdclk_pll.vco = -1;
5898 }
5899 
5900 /* Adjust CDclk dividers to allow high res or save power if possible */
5901 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5902 {
5903         struct drm_i915_private *dev_priv = to_i915(dev);
5904         u32 val, cmd;
5905 
5906         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5907                                         != dev_priv->cdclk_freq);
5908 
5909         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5910                 cmd = 2;
5911         else if (cdclk == 266667)
5912                 cmd = 1;
5913         else
5914                 cmd = 0;
5915 
5916         mutex_lock(&dev_priv->rps.hw_lock);
5917         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5918         val &= ~DSPFREQGUAR_MASK;
5919         val |= (cmd << DSPFREQGUAR_SHIFT);
5920         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5921         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5922                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5923                      50)) {
5924                 DRM_ERROR("timed out waiting for CDclk change\n");
5925         }
5926         mutex_unlock(&dev_priv->rps.hw_lock);
5927 
5928         mutex_lock(&dev_priv->sb_lock);
5929 
5930         if (cdclk == 400000) {
5931                 u32 divider;
5932 
5933                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5934 
5935                 /* adjust cdclk divider */
5936                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5937                 val &= ~CCK_FREQUENCY_VALUES;
5938                 val |= divider;
5939                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5940 
5941                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5942                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5943                              50))
5944                         DRM_ERROR("timed out waiting for CDclk change\n");
5945         }
5946 
5947         /* adjust self-refresh exit latency value */
5948         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5949         val &= ~0x7f;
5950 
5951         /*
5952          * For high bandwidth configs, we set a higher latency in the bunit
5953          * so that the core display fetch happens in time to avoid underruns.
5954          */
5955         if (cdclk == 400000)
5956                 val |= 4500 / 250; /* 4.5 usec */
5957         else
5958                 val |= 3000 / 250; /* 3.0 usec */
5959         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5960 
5961         mutex_unlock(&dev_priv->sb_lock);
5962 
5963         intel_update_cdclk(dev);
5964 }
5965 
5966 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5967 {
5968         struct drm_i915_private *dev_priv = to_i915(dev);
5969         u32 val, cmd;
5970 
5971         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5972                                                 != dev_priv->cdclk_freq);
5973 
5974         switch (cdclk) {
5975         case 333333:
5976         case 320000:
5977         case 266667:
5978         case 200000:
5979                 break;
5980         default:
5981                 MISSING_CASE(cdclk);
5982                 return;
5983         }
5984 
5985         /*
5986          * Specs are full of misinformation, but testing on actual
5987          * hardware has shown that we just need to write the desired
5988          * CCK divider into the Punit register.
5989          */
5990         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5991 
5992         mutex_lock(&dev_priv->rps.hw_lock);
5993         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5994         val &= ~DSPFREQGUAR_MASK_CHV;
5995         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5996         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5997         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5998                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5999                      50)) {
6000                 DRM_ERROR("timed out waiting for CDclk change\n");
6001         }
6002         mutex_unlock(&dev_priv->rps.hw_lock);
6003 
6004         intel_update_cdclk(dev);
6005 }
6006 
6007 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6008                                  int max_pixclk)
6009 {
6010         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6011         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6012 
6013         /*
6014          * Really only a few cases to deal with, as only 4 CDclks are supported:
6015          *   200MHz
6016          *   267MHz
6017          *   320/333MHz (depends on HPLL freq)
6018          *   400MHz (VLV only)
6019          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6020          * of the lower bin and adjust if needed.
6021          *
6022          * We seem to get an unstable or solid color picture at 200MHz.
6023          * Not sure what's wrong. For now use 200MHz only when all pipes
6024          * are off.
6025          */
6026         if (!IS_CHERRYVIEW(dev_priv) &&
6027             max_pixclk > freq_320*limit/100)
6028                 return 400000;
6029         else if (max_pixclk > 266667*limit/100)
6030                 return freq_320;
6031         else if (max_pixclk > 0)
6032                 return 266667;
6033         else
6034                 return 200000;
6035 }
6036 
6037 static int bxt_calc_cdclk(int max_pixclk)
6038 {
6039         if (max_pixclk > 576000)
6040                 return 624000;
6041         else if (max_pixclk > 384000)
6042                 return 576000;
6043         else if (max_pixclk > 288000)
6044                 return 384000;
6045         else if (max_pixclk > 144000)
6046                 return 288000;
6047         else
6048                 return 144000;
6049 }
6050 
6051 /* Compute the max pixel clock for new configuration. */
6052 static int intel_mode_max_pixclk(struct drm_device *dev,
6053                                  struct drm_atomic_state *state)
6054 {
6055         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6056         struct drm_i915_private *dev_priv = to_i915(dev);
6057         struct drm_crtc *crtc;
6058         struct drm_crtc_state *crtc_state;
6059         unsigned max_pixclk = 0, i;
6060         enum pipe pipe;
6061 
6062         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6063                sizeof(intel_state->min_pixclk));
6064 
6065         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6066                 int pixclk = 0;
6067 
6068                 if (crtc_state->enable)
6069                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6070 
6071                 intel_state->min_pixclk[i] = pixclk;
6072         }
6073 
6074         for_each_pipe(dev_priv, pipe)
6075                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6076 
6077         return max_pixclk;
6078 }
6079 
6080 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6081 {
6082         struct drm_device *dev = state->dev;
6083         struct drm_i915_private *dev_priv = to_i915(dev);
6084         int max_pixclk = intel_mode_max_pixclk(dev, state);
6085         struct intel_atomic_state *intel_state =
6086                 to_intel_atomic_state(state);
6087 
6088         intel_state->cdclk = intel_state->dev_cdclk =
6089                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6090 
6091         if (!intel_state->active_crtcs)
6092                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6093 
6094         return 0;
6095 }
6096 
6097 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6098 {
6099         int max_pixclk = ilk_max_pixel_rate(state);
6100         struct intel_atomic_state *intel_state =
6101                 to_intel_atomic_state(state);
6102 
6103         intel_state->cdclk = intel_state->dev_cdclk =
6104                 bxt_calc_cdclk(max_pixclk);
6105 
6106         if (!intel_state->active_crtcs)
6107                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6108 
6109         return 0;
6110 }
6111 
6112 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6113 {
6114         unsigned int credits, default_credits;
6115 
6116         if (IS_CHERRYVIEW(dev_priv))
6117                 default_credits = PFI_CREDIT(12);
6118         else
6119                 default_credits = PFI_CREDIT(8);
6120 
6121         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6122                 /* CHV suggested value is 31 or 63 */
6123                 if (IS_CHERRYVIEW(dev_priv))
6124                         credits = PFI_CREDIT_63;
6125                 else
6126                         credits = PFI_CREDIT(15);
6127         } else {
6128                 credits = default_credits;
6129         }
6130 
6131         /*
6132          * WA - write default credits before re-programming
6133          * FIXME: should we also set the resend bit here?
6134          */
6135         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6136                    default_credits);
6137 
6138         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6139                    credits | PFI_CREDIT_RESEND);
6140 
6141         /*
6142          * FIXME is this guaranteed to clear
6143          * immediately or should we poll for it?
6144          */
6145         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6146 }
6147 
6148 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6149 {
6150         struct drm_device *dev = old_state->dev;
6151         struct drm_i915_private *dev_priv = to_i915(dev);
6152         struct intel_atomic_state *old_intel_state =
6153                 to_intel_atomic_state(old_state);
6154         unsigned req_cdclk = old_intel_state->dev_cdclk;
6155 
6156         /*
6157          * FIXME: We can end up here with all power domains off, yet
6158          * with a CDCLK frequency other than the minimum. To account
6159          * for this take the PIPE-A power domain, which covers the HW
6160          * blocks needed for the following programming. This can be
6161          * removed once it's guaranteed that we get here either with
6162          * the minimum CDCLK set, or the required power domains
6163          * enabled.
6164          */
6165         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6166 
6167         if (IS_CHERRYVIEW(dev))
6168                 cherryview_set_cdclk(dev, req_cdclk);
6169         else
6170                 valleyview_set_cdclk(dev, req_cdclk);
6171 
6172         vlv_program_pfi_credits(dev_priv);
6173 
6174         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6175 }
6176 
6177 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6178 {
6179         struct drm_device *dev = crtc->dev;
6180         struct drm_i915_private *dev_priv = to_i915(dev);
6181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6182         struct intel_encoder *encoder;
6183         struct intel_crtc_state *pipe_config =
6184                 to_intel_crtc_state(crtc->state);
6185         int pipe = intel_crtc->pipe;
6186 
6187         if (WARN_ON(intel_crtc->active))
6188                 return;
6189 
6190         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6191                 intel_dp_set_m_n(intel_crtc, M1_N1);
6192 
6193         intel_set_pipe_timings(intel_crtc);
6194         intel_set_pipe_src_size(intel_crtc);
6195 
6196         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6197                 struct drm_i915_private *dev_priv = to_i915(dev);
6198 
6199                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6200                 I915_WRITE(CHV_CANVAS(pipe), 0);
6201         }
6202 
6203         i9xx_set_pipeconf(intel_crtc);
6204 
6205         intel_crtc->active = true;
6206 
6207         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6208 
6209         for_each_encoder_on_crtc(dev, crtc, encoder)
6210                 if (encoder->pre_pll_enable)
6211                         encoder->pre_pll_enable(encoder);
6212 
6213         if (IS_CHERRYVIEW(dev)) {
6214                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6215                 chv_enable_pll(intel_crtc, intel_crtc->config);
6216         } else {
6217                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6218                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6219         }
6220 
6221         for_each_encoder_on_crtc(dev, crtc, encoder)
6222                 if (encoder->pre_enable)
6223                         encoder->pre_enable(encoder);
6224 
6225         i9xx_pfit_enable(intel_crtc);
6226 
6227         intel_color_load_luts(&pipe_config->base);
6228 
6229         intel_update_watermarks(crtc);
6230         intel_enable_pipe(intel_crtc);
6231 
6232         assert_vblank_disabled(crtc);
6233         drm_crtc_vblank_on(crtc);
6234 
6235         for_each_encoder_on_crtc(dev, crtc, encoder)
6236                 encoder->enable(encoder);
6237 }
6238 
6239 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6240 {
6241         struct drm_device *dev = crtc->base.dev;
6242         struct drm_i915_private *dev_priv = to_i915(dev);
6243 
6244         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6245         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6246 }
6247 
6248 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6249 {
6250         struct drm_device *dev = crtc->dev;
6251         struct drm_i915_private *dev_priv = to_i915(dev);
6252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6253         struct intel_encoder *encoder;
6254         struct intel_crtc_state *pipe_config =
6255                 to_intel_crtc_state(crtc->state);
6256         enum pipe pipe = intel_crtc->pipe;
6257 
6258         if (WARN_ON(intel_crtc->active))
6259                 return;
6260 
6261         i9xx_set_pll_dividers(intel_crtc);
6262 
6263         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6264                 intel_dp_set_m_n(intel_crtc, M1_N1);
6265 
6266         intel_set_pipe_timings(intel_crtc);
6267         intel_set_pipe_src_size(intel_crtc);
6268 
6269         i9xx_set_pipeconf(intel_crtc);
6270 
6271         intel_crtc->active = true;
6272 
6273         if (!IS_GEN2(dev))
6274                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6275 
6276         for_each_encoder_on_crtc(dev, crtc, encoder)
6277                 if (encoder->pre_enable)
6278                         encoder->pre_enable(encoder);
6279 
6280         i9xx_enable_pll(intel_crtc);
6281 
6282         i9xx_pfit_enable(intel_crtc);
6283 
6284         intel_color_load_luts(&pipe_config->base);
6285 
6286         intel_update_watermarks(crtc);
6287         intel_enable_pipe(intel_crtc);
6288 
6289         assert_vblank_disabled(crtc);
6290         drm_crtc_vblank_on(crtc);
6291 
6292         for_each_encoder_on_crtc(dev, crtc, encoder)
6293                 encoder->enable(encoder);
6294 }
6295 
6296 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6297 {
6298         struct drm_device *dev = crtc->base.dev;
6299         struct drm_i915_private *dev_priv = to_i915(dev);
6300 
6301         if (!crtc->config->gmch_pfit.control)
6302                 return;
6303 
6304         assert_pipe_disabled(dev_priv, crtc->pipe);
6305 
6306         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6307                          I915_READ(PFIT_CONTROL));
6308         I915_WRITE(PFIT_CONTROL, 0);
6309 }
6310 
6311 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6312 {
6313         struct drm_device *dev = crtc->dev;
6314         struct drm_i915_private *dev_priv = to_i915(dev);
6315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6316         struct intel_encoder *encoder;
6317         int pipe = intel_crtc->pipe;
6318 
6319         /*
6320          * On gen2 planes are double buffered but the pipe isn't, so we must
6321          * wait for planes to fully turn off before disabling the pipe.
6322          */
6323         if (IS_GEN2(dev))
6324                 intel_wait_for_vblank(dev, pipe);
6325 
6326         for_each_encoder_on_crtc(dev, crtc, encoder)
6327                 encoder->disable(encoder);
6328 
6329         drm_crtc_vblank_off(crtc);
6330         assert_vblank_disabled(crtc);
6331 
6332         intel_disable_pipe(intel_crtc);
6333 
6334         i9xx_pfit_disable(intel_crtc);
6335 
6336         for_each_encoder_on_crtc(dev, crtc, encoder)
6337                 if (encoder->post_disable)
6338                         encoder->post_disable(encoder);
6339 
6340         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6341                 if (IS_CHERRYVIEW(dev))
6342                         chv_disable_pll(dev_priv, pipe);
6343                 else if (IS_VALLEYVIEW(dev))
6344                         vlv_disable_pll(dev_priv, pipe);
6345                 else
6346                         i9xx_disable_pll(intel_crtc);
6347         }
6348 
6349         for_each_encoder_on_crtc(dev, crtc, encoder)
6350                 if (encoder->post_pll_disable)
6351                         encoder->post_pll_disable(encoder);
6352 
6353         if (!IS_GEN2(dev))
6354                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6355 }
6356 
6357 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6358 {
6359         struct intel_encoder *encoder;
6360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6362         enum intel_display_power_domain domain;
6363         unsigned long domains;
6364 
6365         if (!intel_crtc->active)
6366                 return;
6367 
6368         if (to_intel_plane_state(crtc->primary->state)->visible) {
6369                 WARN_ON(intel_crtc->flip_work);
6370 
6371                 intel_pre_disable_primary_noatomic(crtc);
6372 
6373                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6374                 to_intel_plane_state(crtc->primary->state)->visible = false;
6375         }
6376 
6377         dev_priv->display.crtc_disable(crtc);
6378 
6379         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6380                       crtc->base.id, crtc->name);
6381 
6382         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6383         crtc->state->active = false;
6384         intel_crtc->active = false;
6385         crtc->enabled = false;
6386         crtc->state->connector_mask = 0;
6387         crtc->state->encoder_mask = 0;
6388 
6389         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6390                 encoder->base.crtc = NULL;
6391 
6392         intel_fbc_disable(intel_crtc);
6393         intel_update_watermarks(crtc);
6394         intel_disable_shared_dpll(intel_crtc);
6395 
6396         domains = intel_crtc->enabled_power_domains;
6397         for_each_power_domain(domain, domains)
6398                 intel_display_power_put(dev_priv, domain);
6399         intel_crtc->enabled_power_domains = 0;
6400 
6401         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6402         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6403 }
6404 
6405 /*
6406  * turn all crtc's off, but do not adjust state
6407  * This has to be paired with a call to intel_modeset_setup_hw_state.
6408  */
6409 int intel_display_suspend(struct drm_device *dev)
6410 {
6411         struct drm_i915_private *dev_priv = to_i915(dev);
6412         struct drm_atomic_state *state;
6413         int ret;
6414 
6415         state = drm_atomic_helper_suspend(dev);
6416         ret = PTR_ERR_OR_ZERO(state);
6417         if (ret)
6418                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6419         else
6420                 dev_priv->modeset_restore_state = state;
6421         return ret;
6422 }
6423 
6424 void intel_encoder_destroy(struct drm_encoder *encoder)
6425 {
6426         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6427 
6428         drm_encoder_cleanup(encoder);
6429         kfree(intel_encoder);
6430 }
6431 
6432 /* Cross check the actual hw state with our own modeset state tracking (and it's
6433  * internal consistency). */
6434 static void intel_connector_verify_state(struct intel_connector *connector)
6435 {
6436         struct drm_crtc *crtc = connector->base.state->crtc;
6437 
6438         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6439                       connector->base.base.id,
6440                       connector->base.name);
6441 
6442         if (connector->get_hw_state(connector)) {
6443                 struct intel_encoder *encoder = connector->encoder;
6444                 struct drm_connector_state *conn_state = connector->base.state;
6445 
6446                 I915_STATE_WARN(!crtc,
6447                          "connector enabled without attached crtc\n");
6448 
6449                 if (!crtc)
6450                         return;
6451 
6452                 I915_STATE_WARN(!crtc->state->active,
6453                       "connector is active, but attached crtc isn't\n");
6454 
6455                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6456                         return;
6457 
6458                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6459                         "atomic encoder doesn't match attached encoder\n");
6460 
6461                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6462                         "attached encoder crtc differs from connector crtc\n");
6463         } else {
6464                 I915_STATE_WARN(crtc && crtc->state->active,
6465                         "attached crtc is active, but connector isn't\n");
6466                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6467                         "best encoder set without crtc!\n");
6468         }
6469 }
6470 
6471 int intel_connector_init(struct intel_connector *connector)
6472 {
6473         drm_atomic_helper_connector_reset(&connector->base);
6474 
6475         if (!connector->base.state)
6476                 return -ENOMEM;
6477 
6478         return 0;
6479 }
6480 
6481 struct intel_connector *intel_connector_alloc(void)
6482 {
6483         struct intel_connector *connector;
6484 
6485         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6486         if (!connector)
6487                 return NULL;
6488 
6489         if (intel_connector_init(connector) < 0) {
6490