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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include "intel_frontbuffer.h"
 38 #include <drm/i915_drm.h>
 39 #include "i915_drv.h"
 40 #include "i915_gem_dmabuf.h"
 41 #include "intel_dsi.h"
 42 #include "i915_trace.h"
 43 #include <drm/drm_atomic.h>
 44 #include <drm/drm_atomic_helper.h>
 45 #include <drm/drm_dp_helper.h>
 46 #include <drm/drm_crtc_helper.h>
 47 #include <drm/drm_plane_helper.h>
 48 #include <drm/drm_rect.h>
 49 #include <linux/dma_remapping.h>
 50 #include <linux/reservation.h>
 51 
 52 static bool is_mmio_work(struct intel_flip_work *work)
 53 {
 54         return work->mmio_work.func;
 55 }
 56 
 57 /* Primary plane formats for gen <= 3 */
 58 static const uint32_t i8xx_primary_formats[] = {
 59         DRM_FORMAT_C8,
 60         DRM_FORMAT_RGB565,
 61         DRM_FORMAT_XRGB1555,
 62         DRM_FORMAT_XRGB8888,
 63 };
 64 
 65 /* Primary plane formats for gen >= 4 */
 66 static const uint32_t i965_primary_formats[] = {
 67         DRM_FORMAT_C8,
 68         DRM_FORMAT_RGB565,
 69         DRM_FORMAT_XRGB8888,
 70         DRM_FORMAT_XBGR8888,
 71         DRM_FORMAT_XRGB2101010,
 72         DRM_FORMAT_XBGR2101010,
 73 };
 74 
 75 static const uint32_t skl_primary_formats[] = {
 76         DRM_FORMAT_C8,
 77         DRM_FORMAT_RGB565,
 78         DRM_FORMAT_XRGB8888,
 79         DRM_FORMAT_XBGR8888,
 80         DRM_FORMAT_ARGB8888,
 81         DRM_FORMAT_ABGR8888,
 82         DRM_FORMAT_XRGB2101010,
 83         DRM_FORMAT_XBGR2101010,
 84         DRM_FORMAT_YUYV,
 85         DRM_FORMAT_YVYU,
 86         DRM_FORMAT_UYVY,
 87         DRM_FORMAT_VYUY,
 88 };
 89 
 90 /* Cursor formats */
 91 static const uint32_t intel_cursor_formats[] = {
 92         DRM_FORMAT_ARGB8888,
 93 };
 94 
 95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 96                                 struct intel_crtc_state *pipe_config);
 97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 98                                    struct intel_crtc_state *pipe_config);
 99 
100 static int intel_framebuffer_init(struct drm_device *dev,
101                                   struct intel_framebuffer *ifb,
102                                   struct drm_mode_fb_cmd2 *mode_cmd,
103                                   struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108                                          struct intel_link_m_n *m_n,
109                                          struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114                             const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116                             const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120         struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128 
129 struct intel_limit {
130         struct {
131                 int min, max;
132         } dot, vco, n, m, m1, m2, p, p1;
133 
134         struct {
135                 int dot_limit;
136                 int p2_slow, p2_fast;
137         } p2;
138 };
139 
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144 
145         /* Obtain SKU information */
146         mutex_lock(&dev_priv->sb_lock);
147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148                 CCK_FUSE_HPLL_FREQ_MASK;
149         mutex_unlock(&dev_priv->sb_lock);
150 
151         return vco_freq[hpll_freq] * 1000;
152 }
153 
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155                       const char *name, u32 reg, int ref_freq)
156 {
157         u32 val;
158         int divider;
159 
160         mutex_lock(&dev_priv->sb_lock);
161         val = vlv_cck_read(dev_priv, reg);
162         mutex_unlock(&dev_priv->sb_lock);
163 
164         divider = val & CCK_FREQUENCY_VALUES;
165 
166         WARN((val & CCK_FREQUENCY_STATUS) !=
167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
168              "%s change in progress\n", name);
169 
170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172 
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174                                   const char *name, u32 reg)
175 {
176         if (dev_priv->hpll_freq == 0)
177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178 
179         return vlv_get_cck_clock(dev_priv, name, reg,
180                                  dev_priv->hpll_freq);
181 }
182 
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188 
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192         /* RAWCLK_FREQ_VLV register updated from power well code */
193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196 
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200         uint32_t clkcfg;
201 
202         /* hrawclock is 1/4 the FSB frequency */
203         clkcfg = I915_READ(CLKCFG);
204         switch (clkcfg & CLKCFG_FSB_MASK) {
205         case CLKCFG_FSB_400:
206                 return 100000;
207         case CLKCFG_FSB_533:
208                 return 133333;
209         case CLKCFG_FSB_667:
210                 return 166667;
211         case CLKCFG_FSB_800:
212                 return 200000;
213         case CLKCFG_FSB_1067:
214                 return 266667;
215         case CLKCFG_FSB_1333:
216                 return 333333;
217         /* these two are just a guess; one of them might be right */
218         case CLKCFG_FSB_1600:
219         case CLKCFG_FSB_1600_ALT:
220                 return 400000;
221         default:
222                 return 133333;
223         }
224 }
225 
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228         if (HAS_PCH_SPLIT(dev_priv))
229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234         else
235                 return; /* no rawclk on other platforms, or no need to know it */
236 
237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239 
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243                 return;
244 
245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246                                                       CCK_CZ_CLOCK_CONTROL);
247 
248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250 
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253                     const struct intel_crtc_state *pipe_config)
254 {
255         if (HAS_DDI(dev_priv))
256                 return pipe_config->port_clock; /* SPLL */
257         else if (IS_GEN5(dev_priv))
258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259         else
260                 return 270000;
261 }
262 
263 static const struct intel_limit intel_limits_i8xx_dac = {
264         .dot = { .min = 25000, .max = 350000 },
265         .vco = { .min = 908000, .max = 1512000 },
266         .n = { .min = 2, .max = 16 },
267         .m = { .min = 96, .max = 140 },
268         .m1 = { .min = 18, .max = 26 },
269         .m2 = { .min = 6, .max = 16 },
270         .p = { .min = 4, .max = 128 },
271         .p1 = { .min = 2, .max = 33 },
272         .p2 = { .dot_limit = 165000,
273                 .p2_slow = 4, .p2_fast = 2 },
274 };
275 
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277         .dot = { .min = 25000, .max = 350000 },
278         .vco = { .min = 908000, .max = 1512000 },
279         .n = { .min = 2, .max = 16 },
280         .m = { .min = 96, .max = 140 },
281         .m1 = { .min = 18, .max = 26 },
282         .m2 = { .min = 6, .max = 16 },
283         .p = { .min = 4, .max = 128 },
284         .p1 = { .min = 2, .max = 33 },
285         .p2 = { .dot_limit = 165000,
286                 .p2_slow = 4, .p2_fast = 4 },
287 };
288 
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290         .dot = { .min = 25000, .max = 350000 },
291         .vco = { .min = 908000, .max = 1512000 },
292         .n = { .min = 2, .max = 16 },
293         .m = { .min = 96, .max = 140 },
294         .m1 = { .min = 18, .max = 26 },
295         .m2 = { .min = 6, .max = 16 },
296         .p = { .min = 4, .max = 128 },
297         .p1 = { .min = 1, .max = 6 },
298         .p2 = { .dot_limit = 165000,
299                 .p2_slow = 14, .p2_fast = 7 },
300 };
301 
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303         .dot = { .min = 20000, .max = 400000 },
304         .vco = { .min = 1400000, .max = 2800000 },
305         .n = { .min = 1, .max = 6 },
306         .m = { .min = 70, .max = 120 },
307         .m1 = { .min = 8, .max = 18 },
308         .m2 = { .min = 3, .max = 7 },
309         .p = { .min = 5, .max = 80 },
310         .p1 = { .min = 1, .max = 8 },
311         .p2 = { .dot_limit = 200000,
312                 .p2_slow = 10, .p2_fast = 5 },
313 };
314 
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316         .dot = { .min = 20000, .max = 400000 },
317         .vco = { .min = 1400000, .max = 2800000 },
318         .n = { .min = 1, .max = 6 },
319         .m = { .min = 70, .max = 120 },
320         .m1 = { .min = 8, .max = 18 },
321         .m2 = { .min = 3, .max = 7 },
322         .p = { .min = 7, .max = 98 },
323         .p1 = { .min = 1, .max = 8 },
324         .p2 = { .dot_limit = 112000,
325                 .p2_slow = 14, .p2_fast = 7 },
326 };
327 
328 
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330         .dot = { .min = 25000, .max = 270000 },
331         .vco = { .min = 1750000, .max = 3500000},
332         .n = { .min = 1, .max = 4 },
333         .m = { .min = 104, .max = 138 },
334         .m1 = { .min = 17, .max = 23 },
335         .m2 = { .min = 5, .max = 11 },
336         .p = { .min = 10, .max = 30 },
337         .p1 = { .min = 1, .max = 3},
338         .p2 = { .dot_limit = 270000,
339                 .p2_slow = 10,
340                 .p2_fast = 10
341         },
342 };
343 
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345         .dot = { .min = 22000, .max = 400000 },
346         .vco = { .min = 1750000, .max = 3500000},
347         .n = { .min = 1, .max = 4 },
348         .m = { .min = 104, .max = 138 },
349         .m1 = { .min = 16, .max = 23 },
350         .m2 = { .min = 5, .max = 11 },
351         .p = { .min = 5, .max = 80 },
352         .p1 = { .min = 1, .max = 8},
353         .p2 = { .dot_limit = 165000,
354                 .p2_slow = 10, .p2_fast = 5 },
355 };
356 
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358         .dot = { .min = 20000, .max = 115000 },
359         .vco = { .min = 1750000, .max = 3500000 },
360         .n = { .min = 1, .max = 3 },
361         .m = { .min = 104, .max = 138 },
362         .m1 = { .min = 17, .max = 23 },
363         .m2 = { .min = 5, .max = 11 },
364         .p = { .min = 28, .max = 112 },
365         .p1 = { .min = 2, .max = 8 },
366         .p2 = { .dot_limit = 0,
367                 .p2_slow = 14, .p2_fast = 14
368         },
369 };
370 
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372         .dot = { .min = 80000, .max = 224000 },
373         .vco = { .min = 1750000, .max = 3500000 },
374         .n = { .min = 1, .max = 3 },
375         .m = { .min = 104, .max = 138 },
376         .m1 = { .min = 17, .max = 23 },
377         .m2 = { .min = 5, .max = 11 },
378         .p = { .min = 14, .max = 42 },
379         .p1 = { .min = 2, .max = 6 },
380         .p2 = { .dot_limit = 0,
381                 .p2_slow = 7, .p2_fast = 7
382         },
383 };
384 
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386         .dot = { .min = 20000, .max = 400000},
387         .vco = { .min = 1700000, .max = 3500000 },
388         /* Pineview's Ncounter is a ring counter */
389         .n = { .min = 3, .max = 6 },
390         .m = { .min = 2, .max = 256 },
391         /* Pineview only has one combined m divider, which we treat as m2. */
392         .m1 = { .min = 0, .max = 0 },
393         .m2 = { .min = 0, .max = 254 },
394         .p = { .min = 5, .max = 80 },
395         .p1 = { .min = 1, .max = 8 },
396         .p2 = { .dot_limit = 200000,
397                 .p2_slow = 10, .p2_fast = 5 },
398 };
399 
400 static const struct intel_limit intel_limits_pineview_lvds = {
401         .dot = { .min = 20000, .max = 400000 },
402         .vco = { .min = 1700000, .max = 3500000 },
403         .n = { .min = 3, .max = 6 },
404         .m = { .min = 2, .max = 256 },
405         .m1 = { .min = 0, .max = 0 },
406         .m2 = { .min = 0, .max = 254 },
407         .p = { .min = 7, .max = 112 },
408         .p1 = { .min = 1, .max = 8 },
409         .p2 = { .dot_limit = 112000,
410                 .p2_slow = 14, .p2_fast = 14 },
411 };
412 
413 /* Ironlake / Sandybridge
414  *
415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
416  * the range value for them is (actual_value - 2).
417  */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419         .dot = { .min = 25000, .max = 350000 },
420         .vco = { .min = 1760000, .max = 3510000 },
421         .n = { .min = 1, .max = 5 },
422         .m = { .min = 79, .max = 127 },
423         .m1 = { .min = 12, .max = 22 },
424         .m2 = { .min = 5, .max = 9 },
425         .p = { .min = 5, .max = 80 },
426         .p1 = { .min = 1, .max = 8 },
427         .p2 = { .dot_limit = 225000,
428                 .p2_slow = 10, .p2_fast = 5 },
429 };
430 
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432         .dot = { .min = 25000, .max = 350000 },
433         .vco = { .min = 1760000, .max = 3510000 },
434         .n = { .min = 1, .max = 3 },
435         .m = { .min = 79, .max = 118 },
436         .m1 = { .min = 12, .max = 22 },
437         .m2 = { .min = 5, .max = 9 },
438         .p = { .min = 28, .max = 112 },
439         .p1 = { .min = 2, .max = 8 },
440         .p2 = { .dot_limit = 225000,
441                 .p2_slow = 14, .p2_fast = 14 },
442 };
443 
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445         .dot = { .min = 25000, .max = 350000 },
446         .vco = { .min = 1760000, .max = 3510000 },
447         .n = { .min = 1, .max = 3 },
448         .m = { .min = 79, .max = 127 },
449         .m1 = { .min = 12, .max = 22 },
450         .m2 = { .min = 5, .max = 9 },
451         .p = { .min = 14, .max = 56 },
452         .p1 = { .min = 2, .max = 8 },
453         .p2 = { .dot_limit = 225000,
454                 .p2_slow = 7, .p2_fast = 7 },
455 };
456 
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459         .dot = { .min = 25000, .max = 350000 },
460         .vco = { .min = 1760000, .max = 3510000 },
461         .n = { .min = 1, .max = 2 },
462         .m = { .min = 79, .max = 126 },
463         .m1 = { .min = 12, .max = 22 },
464         .m2 = { .min = 5, .max = 9 },
465         .p = { .min = 28, .max = 112 },
466         .p1 = { .min = 2, .max = 8 },
467         .p2 = { .dot_limit = 225000,
468                 .p2_slow = 14, .p2_fast = 14 },
469 };
470 
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472         .dot = { .min = 25000, .max = 350000 },
473         .vco = { .min = 1760000, .max = 3510000 },
474         .n = { .min = 1, .max = 3 },
475         .m = { .min = 79, .max = 126 },
476         .m1 = { .min = 12, .max = 22 },
477         .m2 = { .min = 5, .max = 9 },
478         .p = { .min = 14, .max = 42 },
479         .p1 = { .min = 2, .max = 6 },
480         .p2 = { .dot_limit = 225000,
481                 .p2_slow = 7, .p2_fast = 7 },
482 };
483 
484 static const struct intel_limit intel_limits_vlv = {
485          /*
486           * These are the data rate limits (measured in fast clocks)
487           * since those are the strictest limits we have. The fast
488           * clock and actual rate limits are more relaxed, so checking
489           * them would make no difference.
490           */
491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492         .vco = { .min = 4000000, .max = 6000000 },
493         .n = { .min = 1, .max = 7 },
494         .m1 = { .min = 2, .max = 3 },
495         .m2 = { .min = 11, .max = 156 },
496         .p1 = { .min = 2, .max = 3 },
497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499 
500 static const struct intel_limit intel_limits_chv = {
501         /*
502          * These are the data rate limits (measured in fast clocks)
503          * since those are the strictest limits we have.  The fast
504          * clock and actual rate limits are more relaxed, so checking
505          * them would make no difference.
506          */
507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
508         .vco = { .min = 4800000, .max = 6480000 },
509         .n = { .min = 1, .max = 1 },
510         .m1 = { .min = 2, .max = 2 },
511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
512         .p1 = { .min = 2, .max = 4 },
513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515 
516 static const struct intel_limit intel_limits_bxt = {
517         /* FIXME: find real dot limits */
518         .dot = { .min = 0, .max = INT_MAX },
519         .vco = { .min = 4800000, .max = 6700000 },
520         .n = { .min = 1, .max = 1 },
521         .m1 = { .min = 2, .max = 2 },
522         /* FIXME: find real m2 limits */
523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
524         .p1 = { .min = 2, .max = 4 },
525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527 
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531         return drm_atomic_crtc_needs_modeset(state);
532 }
533 
534 /*
535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538  * The helpers' return value is the rate of the clock that is fed to the
539  * display engine's pipe which can be the above fast dot clock rate or a
540  * divided-down version of it.
541  */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545         clock->m = clock->m2 + 2;
546         clock->p = clock->p1 * clock->p2;
547         if (WARN_ON(clock->n == 0 || clock->p == 0))
548                 return 0;
549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551 
552         return clock->dot;
553 }
554 
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559 
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562         clock->m = i9xx_dpll_compute_m(clock);
563         clock->p = clock->p1 * clock->p2;
564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565                 return 0;
566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 
569         return clock->dot;
570 }
571 
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574         clock->m = clock->m1 * clock->m2;
575         clock->p = clock->p1 * clock->p2;
576         if (WARN_ON(clock->n == 0 || clock->p == 0))
577                 return 0;
578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580 
581         return clock->dot / 5;
582 }
583 
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586         clock->m = clock->m1 * clock->m2;
587         clock->p = clock->p1 * clock->p2;
588         if (WARN_ON(clock->n == 0 || clock->p == 0))
589                 return 0;
590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591                         clock->n << 22);
592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593 
594         return clock->dot / 5;
595 }
596 
597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599  * Returns whether the given set of divisors are valid for a given refclk with
600  * the given connectors.
601  */
602 
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604                                const struct intel_limit *limit,
605                                const struct dpll *clock)
606 {
607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
608                 INTELPllInvalid("n out of range\n");
609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
610                 INTELPllInvalid("p1 out of range\n");
611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
612                 INTELPllInvalid("m2 out of range\n");
613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
614                 INTELPllInvalid("m1 out of range\n");
615 
616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618                 if (clock->m1 <= clock->m2)
619                         INTELPllInvalid("m1 <= m2\n");
620 
621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
623                         INTELPllInvalid("p out of range\n");
624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
625                         INTELPllInvalid("m out of range\n");
626         }
627 
628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629                 INTELPllInvalid("vco out of range\n");
630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631          * connector, etc., rather than just a single range.
632          */
633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634                 INTELPllInvalid("dot out of range\n");
635 
636         return true;
637 }
638 
639 static int
640 i9xx_select_p2_div(const struct intel_limit *limit,
641                    const struct intel_crtc_state *crtc_state,
642                    int target)
643 {
644         struct drm_device *dev = crtc_state->base.crtc->dev;
645 
646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
647                 /*
648                  * For LVDS just rely on its current settings for dual-channel.
649                  * We haven't figured out how to reliably set up different
650                  * single/dual channel state, if we even can.
651                  */
652                 if (intel_is_dual_link_lvds(dev))
653                         return limit->p2.p2_fast;
654                 else
655                         return limit->p2.p2_slow;
656         } else {
657                 if (target < limit->p2.dot_limit)
658                         return limit->p2.p2_slow;
659                 else
660                         return limit->p2.p2_fast;
661         }
662 }
663 
664 /*
665  * Returns a set of divisors for the desired target clock with the given
666  * refclk, or FALSE.  The returned values represent the clock equation:
667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668  *
669  * Target and reference clocks are specified in kHz.
670  *
671  * If match_clock is provided, then best_clock P divider must match the P
672  * divider from @match_clock used for LVDS downclocking.
673  */
674 static bool
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676                     struct intel_crtc_state *crtc_state,
677                     int target, int refclk, struct dpll *match_clock,
678                     struct dpll *best_clock)
679 {
680         struct drm_device *dev = crtc_state->base.crtc->dev;
681         struct dpll clock;
682         int err = target;
683 
684         memset(best_clock, 0, sizeof(*best_clock));
685 
686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687 
688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689              clock.m1++) {
690                 for (clock.m2 = limit->m2.min;
691                      clock.m2 <= limit->m2.max; clock.m2++) {
692                         if (clock.m2 >= clock.m1)
693                                 break;
694                         for (clock.n = limit->n.min;
695                              clock.n <= limit->n.max; clock.n++) {
696                                 for (clock.p1 = limit->p1.min;
697                                         clock.p1 <= limit->p1.max; clock.p1++) {
698                                         int this_err;
699 
700                                         i9xx_calc_dpll_params(refclk, &clock);
701                                         if (!intel_PLL_is_valid(dev, limit,
702                                                                 &clock))
703                                                 continue;
704                                         if (match_clock &&
705                                             clock.p != match_clock->p)
706                                                 continue;
707 
708                                         this_err = abs(clock.dot - target);
709                                         if (this_err < err) {
710                                                 *best_clock = clock;
711                                                 err = this_err;
712                                         }
713                                 }
714                         }
715                 }
716         }
717 
718         return (err != target);
719 }
720 
721 /*
722  * Returns a set of divisors for the desired target clock with the given
723  * refclk, or FALSE.  The returned values represent the clock equation:
724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725  *
726  * Target and reference clocks are specified in kHz.
727  *
728  * If match_clock is provided, then best_clock P divider must match the P
729  * divider from @match_clock used for LVDS downclocking.
730  */
731 static bool
732 pnv_find_best_dpll(const struct intel_limit *limit,
733                    struct intel_crtc_state *crtc_state,
734                    int target, int refclk, struct dpll *match_clock,
735                    struct dpll *best_clock)
736 {
737         struct drm_device *dev = crtc_state->base.crtc->dev;
738         struct dpll clock;
739         int err = target;
740 
741         memset(best_clock, 0, sizeof(*best_clock));
742 
743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744 
745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
746              clock.m1++) {
747                 for (clock.m2 = limit->m2.min;
748                      clock.m2 <= limit->m2.max; clock.m2++) {
749                         for (clock.n = limit->n.min;
750                              clock.n <= limit->n.max; clock.n++) {
751                                 for (clock.p1 = limit->p1.min;
752                                         clock.p1 <= limit->p1.max; clock.p1++) {
753                                         int this_err;
754 
755                                         pnv_calc_dpll_params(refclk, &clock);
756                                         if (!intel_PLL_is_valid(dev, limit,
757                                                                 &clock))
758                                                 continue;
759                                         if (match_clock &&
760                                             clock.p != match_clock->p)
761                                                 continue;
762 
763                                         this_err = abs(clock.dot - target);
764                                         if (this_err < err) {
765                                                 *best_clock = clock;
766                                                 err = this_err;
767                                         }
768                                 }
769                         }
770                 }
771         }
772 
773         return (err != target);
774 }
775 
776 /*
777  * Returns a set of divisors for the desired target clock with the given
778  * refclk, or FALSE.  The returned values represent the clock equation:
779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780  *
781  * Target and reference clocks are specified in kHz.
782  *
783  * If match_clock is provided, then best_clock P divider must match the P
784  * divider from @match_clock used for LVDS downclocking.
785  */
786 static bool
787 g4x_find_best_dpll(const struct intel_limit *limit,
788                    struct intel_crtc_state *crtc_state,
789                    int target, int refclk, struct dpll *match_clock,
790                    struct dpll *best_clock)
791 {
792         struct drm_device *dev = crtc_state->base.crtc->dev;
793         struct dpll clock;
794         int max_n;
795         bool found = false;
796         /* approximately equals target * 0.00585 */
797         int err_most = (target >> 8) + (target >> 9);
798 
799         memset(best_clock, 0, sizeof(*best_clock));
800 
801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
802 
803         max_n = limit->n.max;
804         /* based on hardware requirement, prefer smaller n to precision */
805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806                 /* based on hardware requirement, prefere larger m1,m2 */
807                 for (clock.m1 = limit->m1.max;
808                      clock.m1 >= limit->m1.min; clock.m1--) {
809                         for (clock.m2 = limit->m2.max;
810                              clock.m2 >= limit->m2.min; clock.m2--) {
811                                 for (clock.p1 = limit->p1.max;
812                                      clock.p1 >= limit->p1.min; clock.p1--) {
813                                         int this_err;
814 
815                                         i9xx_calc_dpll_params(refclk, &clock);
816                                         if (!intel_PLL_is_valid(dev, limit,
817                                                                 &clock))
818                                                 continue;
819 
820                                         this_err = abs(clock.dot - target);
821                                         if (this_err < err_most) {
822                                                 *best_clock = clock;
823                                                 err_most = this_err;
824                                                 max_n = clock.n;
825                                                 found = true;
826                                         }
827                                 }
828                         }
829                 }
830         }
831         return found;
832 }
833 
834 /*
835  * Check if the calculated PLL configuration is more optimal compared to the
836  * best configuration and error found so far. Return the calculated error.
837  */
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839                                const struct dpll *calculated_clock,
840                                const struct dpll *best_clock,
841                                unsigned int best_error_ppm,
842                                unsigned int *error_ppm)
843 {
844         /*
845          * For CHV ignore the error and consider only the P value.
846          * Prefer a bigger P value based on HW requirements.
847          */
848         if (IS_CHERRYVIEW(dev)) {
849                 *error_ppm = 0;
850 
851                 return calculated_clock->p > best_clock->p;
852         }
853 
854         if (WARN_ON_ONCE(!target_freq))
855                 return false;
856 
857         *error_ppm = div_u64(1000000ULL *
858                                 abs(target_freq - calculated_clock->dot),
859                              target_freq);
860         /*
861          * Prefer a better P value over a better (smaller) error if the error
862          * is small. Ensure this preference for future configurations too by
863          * setting the error to 0.
864          */
865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866                 *error_ppm = 0;
867 
868                 return true;
869         }
870 
871         return *error_ppm + 10 < best_error_ppm;
872 }
873 
874 /*
875  * Returns a set of divisors for the desired target clock with the given
876  * refclk, or FALSE.  The returned values represent the clock equation:
877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878  */
879 static bool
880 vlv_find_best_dpll(const struct intel_limit *limit,
881                    struct intel_crtc_state *crtc_state,
882                    int target, int refclk, struct dpll *match_clock,
883                    struct dpll *best_clock)
884 {
885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886         struct drm_device *dev = crtc->base.dev;
887         struct dpll clock;
888         unsigned int bestppm = 1000000;
889         /* min update 19.2 MHz */
890         int max_n = min(limit->n.max, refclk / 19200);
891         bool found = false;
892 
893         target *= 5; /* fast clock */
894 
895         memset(best_clock, 0, sizeof(*best_clock));
896 
897         /* based on hardware requirement, prefer smaller n to precision */
898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902                                 clock.p = clock.p1 * clock.p2;
903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
905                                         unsigned int ppm;
906 
907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
908                                                                      refclk * clock.m1);
909 
910                                         vlv_calc_dpll_params(refclk, &clock);
911 
912                                         if (!intel_PLL_is_valid(dev, limit,
913                                                                 &clock))
914                                                 continue;
915 
916                                         if (!vlv_PLL_is_optimal(dev, target,
917                                                                 &clock,
918                                                                 best_clock,
919                                                                 bestppm, &ppm))
920                                                 continue;
921 
922                                         *best_clock = clock;
923                                         bestppm = ppm;
924                                         found = true;
925                                 }
926                         }
927                 }
928         }
929 
930         return found;
931 }
932 
933 /*
934  * Returns a set of divisors for the desired target clock with the given
935  * refclk, or FALSE.  The returned values represent the clock equation:
936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
937  */
938 static bool
939 chv_find_best_dpll(const struct intel_limit *limit,
940                    struct intel_crtc_state *crtc_state,
941                    int target, int refclk, struct dpll *match_clock,
942                    struct dpll *best_clock)
943 {
944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945         struct drm_device *dev = crtc->base.dev;
946         unsigned int best_error_ppm;
947         struct dpll clock;
948         uint64_t m2;
949         int found = false;
950 
951         memset(best_clock, 0, sizeof(*best_clock));
952         best_error_ppm = 1000000;
953 
954         /*
955          * Based on hardware doc, the n always set to 1, and m1 always
956          * set to 2.  If requires to support 200Mhz refclk, we need to
957          * revisit this because n may not 1 anymore.
958          */
959         clock.n = 1, clock.m1 = 2;
960         target *= 5;    /* fast clock */
961 
962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963                 for (clock.p2 = limit->p2.p2_fast;
964                                 clock.p2 >= limit->p2.p2_slow;
965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966                         unsigned int error_ppm;
967 
968                         clock.p = clock.p1 * clock.p2;
969 
970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971                                         clock.n) << 22, refclk * clock.m1);
972 
973                         if (m2 > INT_MAX/clock.m1)
974                                 continue;
975 
976                         clock.m2 = m2;
977 
978                         chv_calc_dpll_params(refclk, &clock);
979 
980                         if (!intel_PLL_is_valid(dev, limit, &clock))
981                                 continue;
982 
983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984                                                 best_error_ppm, &error_ppm))
985                                 continue;
986 
987                         *best_clock = clock;
988                         best_error_ppm = error_ppm;
989                         found = true;
990                 }
991         }
992 
993         return found;
994 }
995 
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997                         struct dpll *best_clock)
998 {
999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001 
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005 
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009 
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026 
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032 
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035 
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042 
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047 
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051 
1052         return line1 == line2;
1053 }
1054 
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077 
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080 
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092 
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099 
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106 
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112 
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116 
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122 
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129 
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150 
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159 
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164 
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168 
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172 
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176 
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182 
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189 
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198 
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201 
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204 
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207 
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221 
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226 
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231 
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237 
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242 
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249 
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257 
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262 
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267 
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272 
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277 
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283 
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290 
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293 
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299 
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308 
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319 
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325 
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352 
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358 
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364 
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371 
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377 
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391 
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397 
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410 
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416 
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426 
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441 
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450 
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455 
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463 
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468 
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473 
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477 
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482 
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487 
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492 
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498 
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502 
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510 
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516 
1517         assert_pipe_disabled(dev_priv, pipe);
1518 
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521 
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524 
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528 
1529 
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537 
1538         mutex_lock(&dev_priv->sb_lock);
1539 
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544 
1545         mutex_unlock(&dev_priv->sb_lock);
1546 
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551 
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554 
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561 
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567 
1568         assert_pipe_disabled(dev_priv, pipe);
1569 
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572 
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575 
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587 
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598 
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603 
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608 
1609         return count;
1610 }
1611 
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618 
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620 
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624 
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637 
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644 
1645         I915_WRITE(reg, dpll);
1646 
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650 
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662 
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674 
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689 
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699 
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704 
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707 
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711 
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715 
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718 
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723 
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727 
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732 
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735 
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740 
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743 
1744         mutex_lock(&dev_priv->sb_lock);
1745 
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750 
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753 
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760 
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778 
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785 
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794 
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797 
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801 
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810 
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814 
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827 
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837 
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844 
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849 
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853 
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861 
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867 
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876 
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883 
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887 
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890 
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900 
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909 
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913 
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922 
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928 
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945 
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947 
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951 
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956 
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976 
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984 
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987 
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999 
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017 
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019 
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027 
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032 
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039 
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044 
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049 
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054 
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091 
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101 
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111 
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115 
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122 
2123         return ALIGN(height, tile_height);
2124 }
2125 
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130 
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133 
2134         return size;
2135 }
2136 
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (intel_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149 
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162 
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181 
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185         struct drm_device *dev = fb->dev;
2186         struct drm_i915_private *dev_priv = to_i915(dev);
2187         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188         struct i915_ggtt_view view;
2189         struct i915_vma *vma;
2190         u32 alignment;
2191 
2192         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193 
2194         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195 
2196         intel_fill_fb_ggtt_view(&view, fb, rotation);
2197 
2198         /* Note that the w/a also requires 64 PTE of padding following the
2199          * bo. We currently fill all unused PTE with the shadow page and so
2200          * we should always have valid PTE following the scanout preventing
2201          * the VT-d warning.
2202          */
2203         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204                 alignment = 256 * 1024;
2205 
2206         /*
2207          * Global gtt pte registers are special registers which actually forward
2208          * writes to a chunk of system memory. Which means that there is no risk
2209          * that the register values disappear as soon as we call
2210          * intel_runtime_pm_put(), so it is correct to wrap only the
2211          * pin/unpin/fence and not more.
2212          */
2213         intel_runtime_pm_get(dev_priv);
2214 
2215         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216         if (IS_ERR(vma))
2217                 goto err;
2218 
2219         if (i915_vma_is_map_and_fenceable(vma)) {
2220                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221                  * fence, whereas 965+ only requires a fence if using
2222                  * framebuffer compression.  For simplicity, we always, when
2223                  * possible, install a fence as the cost is not that onerous.
2224                  *
2225                  * If we fail to fence the tiled scanout, then either the
2226                  * modeset will reject the change (which is highly unlikely as
2227                  * the affected systems, all but one, do not have unmappable
2228                  * space) or we will not be able to enable full powersaving
2229                  * techniques (also likely not to apply due to various limits
2230                  * FBC and the like impose on the size of the buffer, which
2231                  * presumably we violated anyway with this unmappable buffer).
2232                  * Anyway, it is presumably better to stumble onwards with
2233                  * something and try to run the system in a "less than optimal"
2234                  * mode that matches the user configuration.
2235                  */
2236                 if (i915_vma_get_fence(vma) == 0)
2237                         i915_vma_pin_fence(vma);
2238         }
2239 
2240 err:
2241         intel_runtime_pm_put(dev_priv);
2242         return vma;
2243 }
2244 
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         struct i915_ggtt_view view;
2249         struct i915_vma *vma;
2250 
2251         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252 
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254         vma = i915_gem_object_to_ggtt(obj, &view);
2255 
2256         i915_vma_unpin_fence(vma);
2257         i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259 
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261                           unsigned int rotation)
2262 {
2263         if (intel_rotation_90_or_270(rotation))
2264                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265         else
2266                 return fb->pitches[plane];
2267 }
2268 
2269 /*
2270  * Convert the x/y offsets into a linear offset.
2271  * Only valid with 0/180 degree rotation, which is fine since linear
2272  * offset is only used with linear buffers on pre-hsw and tiled buffers
2273  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274  */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276                           const struct intel_plane_state *state,
2277                           int plane)
2278 {
2279         const struct drm_framebuffer *fb = state->base.fb;
2280         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281         unsigned int pitch = fb->pitches[plane];
2282 
2283         return y * pitch + x * cpp;
2284 }
2285 
2286 /*
2287  * Add the x/y offsets derived from fb->offsets[] to the user
2288  * specified plane src x/y offsets. The resulting x/y offsets
2289  * specify the start of scanout from the beginning of the gtt mapping.
2290  */
2291 void intel_add_fb_offsets(int *x, int *y,
2292                           const struct intel_plane_state *state,
2293                           int plane)
2294 
2295 {
2296         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297         unsigned int rotation = state->base.rotation;
2298 
2299         if (intel_rotation_90_or_270(rotation)) {
2300                 *x += intel_fb->rotated[plane].x;
2301                 *y += intel_fb->rotated[plane].y;
2302         } else {
2303                 *x += intel_fb->normal[plane].x;
2304                 *y += intel_fb->normal[plane].y;
2305         }
2306 }
2307 
2308 /*
2309  * Input tile dimensions and pitch must already be
2310  * rotated to match x and y, and in pixel units.
2311  */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313                                      unsigned int tile_width,
2314                                      unsigned int tile_height,
2315                                      unsigned int tile_size,
2316                                      unsigned int pitch_tiles,
2317                                      u32 old_offset,
2318                                      u32 new_offset)
2319 {
2320         unsigned int pitch_pixels = pitch_tiles * tile_width;
2321         unsigned int tiles;
2322 
2323         WARN_ON(old_offset & (tile_size - 1));
2324         WARN_ON(new_offset & (tile_size - 1));
2325         WARN_ON(new_offset > old_offset);
2326 
2327         tiles = (old_offset - new_offset) / tile_size;
2328 
2329         *y += tiles / pitch_tiles * tile_height;
2330         *x += tiles % pitch_tiles * tile_width;
2331 
2332         /* minimize x in case it got needlessly big */
2333         *y += *x / pitch_pixels * tile_height;
2334         *x %= pitch_pixels;
2335 
2336         return new_offset;
2337 }
2338 
2339 /*
2340  * Adjust the tile offset by moving the difference into
2341  * the x/y offsets.
2342  */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344                                     const struct intel_plane_state *state, int plane,
2345                                     u32 old_offset, u32 new_offset)
2346 {
2347         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348         const struct drm_framebuffer *fb = state->base.fb;
2349         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350         unsigned int rotation = state->base.rotation;
2351         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352 
2353         WARN_ON(new_offset > old_offset);
2354 
2355         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356                 unsigned int tile_size, tile_width, tile_height;
2357                 unsigned int pitch_tiles;
2358 
2359                 tile_size = intel_tile_size(dev_priv);
2360                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361                                 fb->modifier[plane], cpp);
2362 
2363                 if (intel_rotation_90_or_270(rotation)) {
2364                         pitch_tiles = pitch / tile_height;
2365                         swap(tile_width, tile_height);
2366                 } else {
2367                         pitch_tiles = pitch / (tile_width * cpp);
2368                 }
2369 
2370                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371                                           tile_size, pitch_tiles,
2372                                           old_offset, new_offset);
2373         } else {
2374                 old_offset += *y * pitch + *x * cpp;
2375 
2376                 *y = (old_offset - new_offset) / pitch;
2377                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378         }
2379 
2380         return new_offset;
2381 }
2382 
2383 /*
2384  * Computes the linear offset to the base tile and adjusts
2385  * x, y. bytes per pixel is assumed to be a power-of-two.
2386  *
2387  * In the 90/270 rotated case, x and y are assumed
2388  * to be already rotated to match the rotated GTT view, and
2389  * pitch is the tile_height aligned framebuffer height.
2390  *
2391  * This function is used when computing the derived information
2392  * under intel_framebuffer, so using any of that information
2393  * here is not allowed. Anything under drm_framebuffer can be
2394  * used. This is why the user has to pass in the pitch since it
2395  * is specified in the rotated orientation.
2396  */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398                                       int *x, int *y,
2399                                       const struct drm_framebuffer *fb, int plane,
2400                                       unsigned int pitch,
2401                                       unsigned int rotation,
2402                                       u32 alignment)
2403 {
2404         uint64_t fb_modifier = fb->modifier[plane];
2405         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406         u32 offset, offset_aligned;
2407 
2408         if (alignment)
2409                 alignment--;
2410 
2411         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412                 unsigned int tile_size, tile_width, tile_height;
2413                 unsigned int tile_rows, tiles, pitch_tiles;
2414 
2415                 tile_size = intel_tile_size(dev_priv);
2416                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417                                 fb_modifier, cpp);
2418 
2419                 if (intel_rotation_90_or_270(rotation)) {
2420                         pitch_tiles = pitch / tile_height;
2421                         swap(tile_width, tile_height);
2422                 } else {
2423                         pitch_tiles = pitch / (tile_width * cpp);
2424                 }
2425 
2426                 tile_rows = *y / tile_height;
2427                 *y %= tile_height;
2428 
2429                 tiles = *x / tile_width;
2430                 *x %= tile_width;
2431 
2432                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433                 offset_aligned = offset & ~alignment;
2434 
2435                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436                                           tile_size, pitch_tiles,
2437                                           offset, offset_aligned);
2438         } else {
2439                 offset = *y * pitch + *x * cpp;
2440                 offset_aligned = offset & ~alignment;
2441 
2442                 *y = (offset & alignment) / pitch;
2443                 *x = ((offset & alignment) - *y * pitch) / cpp;
2444         }
2445 
2446         return offset_aligned;
2447 }
2448 
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450                               const struct intel_plane_state *state,
2451                               int plane)
2452 {
2453         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454         const struct drm_framebuffer *fb = state->base.fb;
2455         unsigned int rotation = state->base.rotation;
2456         int pitch = intel_fb_pitch(fb, plane, rotation);
2457         u32 alignment;
2458 
2459         /* AUX_DIST needs only 4K alignment */
2460         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461                 alignment = 4096;
2462         else
2463                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464 
2465         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466                                           rotation, alignment);
2467 }
2468 
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471                                   const struct drm_framebuffer *fb, int plane)
2472 {
2473         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474         unsigned int pitch = fb->pitches[plane];
2475         u32 linear_offset = fb->offsets[plane];
2476 
2477         *y = linear_offset / pitch;
2478         *x = linear_offset % pitch / cpp;
2479 }
2480 
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483         switch (fb_modifier) {
2484         case I915_FORMAT_MOD_X_TILED:
2485                 return I915_TILING_X;
2486         case I915_FORMAT_MOD_Y_TILED:
2487                 return I915_TILING_Y;
2488         default:
2489                 return I915_TILING_NONE;
2490         }
2491 }
2492 
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495                    struct drm_framebuffer *fb)
2496 {
2497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499         u32 gtt_offset_rotated = 0;
2500         unsigned int max_size = 0;
2501         uint32_t format = fb->pixel_format;
2502         int i, num_planes = drm_format_num_planes(format);
2503         unsigned int tile_size = intel_tile_size(dev_priv);
2504 
2505         for (i = 0; i < num_planes; i++) {
2506                 unsigned int width, height;
2507                 unsigned int cpp, size;
2508                 u32 offset;
2509                 int x, y;
2510 
2511                 cpp = drm_format_plane_cpp(format, i);
2512                 width = drm_format_plane_width(fb->width, format, i);
2513                 height = drm_format_plane_height(fb->height, format, i);
2514 
2515                 intel_fb_offset_to_xy(&x, &y, fb, i);
2516 
2517                 /*
2518                  * The fence (if used) is aligned to the start of the object
2519                  * so having the framebuffer wrap around across the edge of the
2520                  * fenced region doesn't really work. We have no API to configure
2521                  * the fence start offset within the object (nor could we probably
2522                  * on gen2/3). So it's just easier if we just require that the
2523                  * fb layout agrees with the fence layout. We already check that the
2524                  * fb stride matches the fence stride elsewhere.
2525                  */
2526                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527                     (x + width) * cpp > fb->pitches[i]) {
2528                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529                                   i, fb->offsets[i]);
2530                         return -EINVAL;
2531                 }
2532 
2533                 /*
2534                  * First pixel of the framebuffer from
2535                  * the start of the normal gtt mapping.
2536                  */
2537                 intel_fb->normal[i].x = x;
2538                 intel_fb->normal[i].y = y;
2539 
2540                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541                                                     fb, 0, fb->pitches[i],
2542                                                     DRM_ROTATE_0, tile_size);
2543                 offset /= tile_size;
2544 
2545                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546                         unsigned int tile_width, tile_height;
2547                         unsigned int pitch_tiles;
2548                         struct drm_rect r;
2549 
2550                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551                                         fb->modifier[i], cpp);
2552 
2553                         rot_info->plane[i].offset = offset;
2554                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557 
2558                         intel_fb->rotated[i].pitch =
2559                                 rot_info->plane[i].height * tile_height;
2560 
2561                         /* how many tiles does this plane need */
2562                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563                         /*
2564                          * If the plane isn't horizontally tile aligned,
2565                          * we need one more tile.
2566                          */
2567                         if (x != 0)
2568                                 size++;
2569 
2570                         /* rotate the x/y offsets to match the GTT view */
2571                         r.x1 = x;
2572                         r.y1 = y;
2573                         r.x2 = x + width;
2574                         r.y2 = y + height;
2575                         drm_rect_rotate(&r,
2576                                         rot_info->plane[i].width * tile_width,
2577                                         rot_info->plane[i].height * tile_height,
2578                                         DRM_ROTATE_270);
2579                         x = r.x1;
2580                         y = r.y1;
2581 
2582                         /* rotate the tile dimensions to match the GTT view */
2583                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584                         swap(tile_width, tile_height);
2585 
2586                         /*
2587                          * We only keep the x/y offsets, so push all of the
2588                          * gtt offset into the x/y offsets.
2589                          */
2590                         _intel_adjust_tile_offset(&x, &y, tile_size,
2591                                                   tile_width, tile_height, pitch_tiles,
2592                                                   gtt_offset_rotated * tile_size, 0);
2593 
2594                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595 
2596                         /*
2597                          * First pixel of the framebuffer from
2598                          * the start of the rotated gtt mapping.
2599                          */
2600                         intel_fb->rotated[i].x = x;
2601                         intel_fb->rotated[i].y = y;
2602                 } else {
2603                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604                                             x * cpp, tile_size);
2605                 }
2606 
2607                 /* how many tiles in total needed in the bo */
2608                 max_size = max(max_size, offset + size);
2609         }
2610 
2611         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614                 return -EINVAL;
2615         }
2616 
2617         return 0;
2618 }
2619 
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622         switch (format) {
2623         case DISPPLANE_8BPP:
2624                 return DRM_FORMAT_C8;
2625         case DISPPLANE_BGRX555:
2626                 return DRM_FORMAT_XRGB1555;
2627         case DISPPLANE_BGRX565:
2628                 return DRM_FORMAT_RGB565;
2629         default:
2630         case DISPPLANE_BGRX888:
2631                 return DRM_FORMAT_XRGB8888;
2632         case DISPPLANE_RGBX888:
2633                 return DRM_FORMAT_XBGR8888;
2634         case DISPPLANE_BGRX101010:
2635                 return DRM_FORMAT_XRGB2101010;
2636         case DISPPLANE_RGBX101010:
2637                 return DRM_FORMAT_XBGR2101010;
2638         }
2639 }
2640 
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643         switch (format) {
2644         case PLANE_CTL_FORMAT_RGB_565:
2645                 return DRM_FORMAT_RGB565;
2646         default:
2647         case PLANE_CTL_FORMAT_XRGB_8888:
2648                 if (rgb_order) {
2649                         if (alpha)
2650                                 return DRM_FORMAT_ABGR8888;
2651                         else
2652                                 return DRM_FORMAT_XBGR8888;
2653                 } else {
2654                         if (alpha)
2655                                 return DRM_FORMAT_ARGB8888;
2656                         else
2657                                 return DRM_FORMAT_XRGB8888;
2658                 }
2659         case PLANE_CTL_FORMAT_XRGB_2101010:
2660                 if (rgb_order)
2661                         return DRM_FORMAT_XBGR2101010;
2662                 else
2663                         return DRM_FORMAT_XRGB2101010;
2664         }
2665 }
2666 
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669                               struct intel_initial_plane_config *plane_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674         struct drm_i915_gem_object *obj = NULL;
2675         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676         struct drm_framebuffer *fb = &plane_config->fb->base;
2677         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679                                     PAGE_SIZE);
2680 
2681         size_aligned -= base_aligned;
2682 
2683         if (plane_config->size == 0)
2684                 return false;
2685 
2686         /* If the FB is too big, just don't use it since fbdev is not very
2687          * important and we should probably use that space with FBC or other
2688          * features. */
2689         if (size_aligned * 2 > ggtt->stolen_usable_size)
2690                 return false;
2691 
2692         mutex_lock(&dev->struct_mutex);
2693 
2694         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695                                                              base_aligned,
2696                                                              base_aligned,
2697                                                              size_aligned);
2698         if (!obj) {
2699                 mutex_unlock(&dev->struct_mutex);
2700                 return false;
2701         }
2702 
2703         if (plane_config->tiling == I915_TILING_X)
2704                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705 
2706         mode_cmd.pixel_format = fb->pixel_format;
2707         mode_cmd.width = fb->width;
2708         mode_cmd.height = fb->height;
2709         mode_cmd.pitches[0] = fb->pitches[0];
2710         mode_cmd.modifier[0] = fb->modifier[0];
2711         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712 
2713         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714                                    &mode_cmd, obj)) {
2715                 DRM_DEBUG_KMS("intel fb init failed\n");
2716                 goto out_unref_obj;
2717         }
2718 
2719         mutex_unlock(&dev->struct_mutex);
2720 
2721         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722         return true;
2723 
2724 out_unref_obj:
2725         i915_gem_object_put(obj);
2726         mutex_unlock(&dev->struct_mutex);
2727         return false;
2728 }
2729 
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734         if (plane->fb == plane->state->fb)
2735                 return;
2736 
2737         if (plane->state->fb)
2738                 drm_framebuffer_unreference(plane->state->fb);
2739         plane->state->fb = plane->fb;
2740         if (plane->state->fb)
2741                 drm_framebuffer_reference(plane->state->fb);
2742 }
2743 
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746                              struct intel_initial_plane_config *plane_config)
2747 {
2748         struct drm_device *dev = intel_crtc->base.dev;
2749         struct drm_i915_private *dev_priv = to_i915(dev);
2750         struct drm_crtc *c;
2751         struct intel_crtc *i;
2752         struct drm_i915_gem_object *obj;
2753         struct drm_plane *primary = intel_crtc->base.primary;
2754         struct drm_plane_state *plane_state = primary->state;
2755         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756         struct intel_plane *intel_plane = to_intel_plane(primary);
2757         struct intel_plane_state *intel_state =
2758                 to_intel_plane_state(plane_state);
2759         struct drm_framebuffer *fb;
2760 
2761         if (!plane_config->fb)
2762                 return;
2763 
2764         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765                 fb = &plane_config->fb->base;
2766                 goto valid_fb;
2767         }
2768 
2769         kfree(plane_config->fb);
2770 
2771         /*
2772          * Failed to alloc the obj, check to see if we should share
2773          * an fb with another CRTC instead
2774          */
2775         for_each_crtc(dev, c) {
2776                 i = to_intel_crtc(c);
2777 
2778                 if (c == &intel_crtc->base)
2779                         continue;
2780 
2781                 if (!i->active)
2782                         continue;
2783 
2784                 fb = c->primary->fb;
2785                 if (!fb)
2786                         continue;
2787 
2788                 obj = intel_fb_obj(fb);
2789                 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790                         drm_framebuffer_reference(fb);
2791                         goto valid_fb;
2792                 }
2793         }
2794 
2795         /*
2796          * We've failed to reconstruct the BIOS FB.  Current display state
2797          * indicates that the primary plane is visible, but has a NULL FB,
2798          * which will lead to problems later if we don't fix it up.  The
2799          * simplest solution is to just disable the primary plane now and
2800          * pretend the BIOS never had it enabled.
2801          */
2802         to_intel_plane_state(plane_state)->base.visible = false;
2803         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805         intel_plane->disable_plane(primary, &intel_crtc->base);
2806 
2807         return;
2808 
2809 valid_fb:
2810         plane_state->src_x = 0;
2811         plane_state->src_y = 0;
2812         plane_state->src_w = fb->width << 16;
2813         plane_state->src_h = fb->height << 16;
2814 
2815         plane_state->crtc_x = 0;
2816         plane_state->crtc_y = 0;
2817         plane_state->crtc_w = fb->width;
2818         plane_state->crtc_h = fb->height;
2819 
2820         intel_state->base.src.x1 = plane_state->src_x;
2821         intel_state->base.src.y1 = plane_state->src_y;
2822         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824         intel_state->base.dst.x1 = plane_state->crtc_x;
2825         intel_state->base.dst.y1 = plane_state->crtc_y;
2826         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828 
2829         obj = intel_fb_obj(fb);
2830         if (i915_gem_object_is_tiled(obj))
2831                 dev_priv->preserve_bios_swizzle = true;
2832 
2833         drm_framebuffer_reference(fb);
2834         primary->fb = primary->state->fb = fb;
2835         primary->crtc = primary->state->crtc = &intel_crtc->base;
2836         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838                   &obj->frontbuffer_bits);
2839 }
2840 
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842                                unsigned int rotation)
2843 {
2844         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845 
2846         switch (fb->modifier[plane]) {
2847         case DRM_FORMAT_MOD_NONE:
2848         case I915_FORMAT_MOD_X_TILED:
2849                 switch (cpp) {
2850                 case 8:
2851                         return 4096;
2852                 case 4:
2853                 case 2:
2854                 case 1:
2855                         return 8192;
2856                 default:
2857                         MISSING_CASE(cpp);
2858                         break;
2859                 }
2860                 break;
2861         case I915_FORMAT_MOD_Y_TILED:
2862         case I915_FORMAT_MOD_Yf_TILED:
2863                 switch (cpp) {
2864                 case 8:
2865                         return 2048;
2866                 case 4:
2867                         return 4096;
2868                 case 2:
2869                 case 1:
2870                         return 8192;
2871                 default:
2872                         MISSING_CASE(cpp);
2873                         break;
2874                 }
2875                 break;
2876         default:
2877                 MISSING_CASE(fb->modifier[plane]);
2878         }
2879 
2880         return 2048;
2881 }
2882 
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886         const struct drm_framebuffer *fb = plane_state->base.fb;
2887         unsigned int rotation = plane_state->base.rotation;
2888         int x = plane_state->base.src.x1 >> 16;
2889         int y = plane_state->base.src.y1 >> 16;
2890         int w = drm_rect_width(&plane_state->base.src) >> 16;
2891         int h = drm_rect_height(&plane_state->base.src) >> 16;
2892         int max_width = skl_max_plane_width(fb, 0, rotation);
2893         int max_height = 4096;
2894         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895 
2896         if (w > max_width || h > max_height) {
2897                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898                               w, h, max_width, max_height);
2899                 return -EINVAL;
2900         }
2901 
2902         intel_add_fb_offsets(&x, &y, plane_state, 0);
2903         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904 
2905         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906 
2907         /*
2908          * AUX surface offset is specified as the distance from the
2909          * main surface offset, and it must be non-negative. Make
2910          * sure that is what we will get.
2911          */
2912         if (offset > aux_offset)
2913                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914                                                   offset, aux_offset & ~(alignment - 1));
2915 
2916         /*
2917          * When using an X-tiled surface, the plane blows up
2918          * if the x offset + width exceed the stride.
2919          *
2920          * TODO: linear and Y-tiled seem fine, Yf untested,
2921          */
2922         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924 
2925                 while ((x + w) * cpp > fb->pitches[0]) {
2926                         if (offset == 0) {
2927                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928                                 return -EINVAL;
2929                         }
2930 
2931                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932                                                           offset, offset - alignment);
2933                 }
2934         }
2935 
2936         plane_state->main.offset = offset;
2937         plane_state->main.x = x;
2938         plane_state->main.y = y;
2939 
2940         return 0;
2941 }
2942 
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945         const struct drm_framebuffer *fb = plane_state->base.fb;
2946         unsigned int rotation = plane_state->base.rotation;
2947         int max_width = skl_max_plane_width(fb, 1, rotation);
2948         int max_height = 4096;
2949         int x = plane_state->base.src.x1 >> 17;
2950         int y = plane_state->base.src.y1 >> 17;
2951         int w = drm_rect_width(&plane_state->base.src) >> 17;
2952         int h = drm_rect_height(&plane_state->base.src) >> 17;
2953         u32 offset;
2954 
2955         intel_add_fb_offsets(&x, &y, plane_state, 1);
2956         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957 
2958         /* FIXME not quite sure how/if these apply to the chroma plane */
2959         if (w > max_width || h > max_height) {
2960                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961                               w, h, max_width, max_height);
2962                 return -EINVAL;
2963         }
2964 
2965         plane_state->aux.offset = offset;
2966         plane_state->aux.x = x;
2967         plane_state->aux.y = y;
2968 
2969         return 0;
2970 }
2971 
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974         const struct drm_framebuffer *fb = plane_state->base.fb;
2975         unsigned int rotation = plane_state->base.rotation;
2976         int ret;
2977 
2978         /* Rotate src coordinates to match rotated GTT view */
2979         if (intel_rotation_90_or_270(rotation))
2980                 drm_rect_rotate(&plane_state->base.src,
2981                                 fb->width << 16, fb->height << 16,
2982                                 DRM_ROTATE_270);
2983 
2984         /*
2985          * Handle the AUX surface first since
2986          * the main surface setup depends on it.
2987          */
2988         if (fb->pixel_format == DRM_FORMAT_NV12) {
2989                 ret = skl_check_nv12_aux_surface(plane_state);
2990                 if (ret)
2991                         return ret;
2992         } else {
2993                 plane_state->aux.offset = ~0xfff;
2994                 plane_state->aux.x = 0;
2995                 plane_state->aux.y = 0;
2996         }
2997 
2998         ret = skl_check_main_surface(plane_state);
2999         if (ret)
3000                 return ret;
3001 
3002         return 0;
3003 }
3004 
3005 static void i9xx_update_primary_plane(struct drm_plane *primary,
3006                                       const struct intel_crtc_state *crtc_state,
3007                                       const struct intel_plane_state *plane_state)
3008 {
3009         struct drm_device *dev = primary->dev;
3010         struct drm_i915_private *dev_priv = to_i915(dev);
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3012         struct drm_framebuffer *fb = plane_state->base.fb;
3013         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3014         int plane = intel_crtc->plane;
3015         u32 linear_offset;
3016         u32 dspcntr;
3017         i915_reg_t reg = DSPCNTR(plane);
3018         unsigned int rotation = plane_state->base.rotation;
3019         int x = plane_state->base.src.x1 >> 16;
3020         int y = plane_state->base.src.y1 >> 16;
3021 
3022         dspcntr = DISPPLANE_GAMMA_ENABLE;
3023 
3024         dspcntr |= DISPLAY_PLANE_ENABLE;
3025 
3026         if (INTEL_INFO(dev)->gen < 4) {
3027                 if (intel_crtc->pipe == PIPE_B)
3028                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3029 
3030                 /* pipesrc and dspsize control the size that is scaled from,
3031                  * which should always be the user's requested size.
3032                  */
3033                 I915_WRITE(DSPSIZE(plane),
3034                            ((crtc_state->pipe_src_h - 1) << 16) |
3035                            (crtc_state->pipe_src_w - 1));
3036                 I915_WRITE(DSPPOS(plane), 0);
3037         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3038                 I915_WRITE(PRIMSIZE(plane),
3039                            ((crtc_state->pipe_src_h - 1) << 16) |
3040                            (crtc_state->pipe_src_w - 1));
3041                 I915_WRITE(PRIMPOS(plane), 0);
3042                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3043         }
3044 
3045         switch (fb->pixel_format) {
3046         case DRM_FORMAT_C8:
3047                 dspcntr |= DISPPLANE_8BPP;
3048                 break;
3049         case DRM_FORMAT_XRGB1555:
3050                 dspcntr |= DISPPLANE_BGRX555;
3051                 break;
3052         case DRM_FORMAT_RGB565:
3053                 dspcntr |= DISPPLANE_BGRX565;
3054                 break;
3055         case DRM_FORMAT_XRGB8888:
3056                 dspcntr |= DISPPLANE_BGRX888;
3057                 break;
3058         case DRM_FORMAT_XBGR8888:
3059                 dspcntr |= DISPPLANE_RGBX888;
3060                 break;
3061         case DRM_FORMAT_XRGB2101010:
3062                 dspcntr |= DISPPLANE_BGRX101010;
3063                 break;
3064         case DRM_FORMAT_XBGR2101010:
3065                 dspcntr |= DISPPLANE_RGBX101010;
3066                 break;
3067         default:
3068                 BUG();
3069         }
3070 
3071         if (INTEL_GEN(dev_priv) >= 4 &&
3072             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3073                 dspcntr |= DISPPLANE_TILED;
3074 
3075         if (IS_G4X(dev))
3076                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3077 
3078         intel_add_fb_offsets(&x, &y, plane_state, 0);
3079 
3080         if (INTEL_INFO(dev)->gen >= 4)
3081                 intel_crtc->dspaddr_offset =
3082                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3083 
3084         if (rotation == DRM_ROTATE_180) {
3085                 dspcntr |= DISPPLANE_ROTATE_180;
3086 
3087                 x += (crtc_state->pipe_src_w - 1);
3088                 y += (crtc_state->pipe_src_h - 1);
3089         }
3090 
3091         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3092 
3093         if (INTEL_INFO(dev)->gen < 4)
3094                 intel_crtc->dspaddr_offset = linear_offset;
3095 
3096         intel_crtc->adjusted_x = x;
3097         intel_crtc->adjusted_y = y;
3098 
3099         I915_WRITE(reg, dspcntr);
3100 
3101         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3102         if (INTEL_INFO(dev)->gen >= 4) {
3103                 I915_WRITE(DSPSURF(plane),
3104                            intel_fb_gtt_offset(fb, rotation) +
3105                            intel_crtc->dspaddr_offset);
3106                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3107                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3108         } else
3109                 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3110         POSTING_READ(reg);
3111 }
3112 
3113 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3114                                        struct drm_crtc *crtc)
3115 {
3116         struct drm_device *dev = crtc->dev;
3117         struct drm_i915_private *dev_priv = to_i915(dev);
3118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119         int plane = intel_crtc->plane;
3120 
3121         I915_WRITE(DSPCNTR(plane), 0);
3122         if (INTEL_INFO(dev_priv)->gen >= 4)
3123                 I915_WRITE(DSPSURF(plane), 0);
3124         else
3125                 I915_WRITE(DSPADDR(plane), 0);
3126         POSTING_READ(DSPCNTR(plane));
3127 }
3128 
3129 static void ironlake_update_primary_plane(struct drm_plane *primary,
3130                                           const struct intel_crtc_state *crtc_state,
3131                                           const struct intel_plane_state *plane_state)
3132 {
3133         struct drm_device *dev = primary->dev;
3134         struct drm_i915_private *dev_priv = to_i915(dev);
3135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3136         struct drm_framebuffer *fb = plane_state->base.fb;
3137         int plane = intel_crtc->plane;
3138         u32 linear_offset;
3139         u32 dspcntr;
3140         i915_reg_t reg = DSPCNTR(plane);
3141         unsigned int rotation = plane_state->base.rotation;
3142         int x = plane_state->base.src.x1 >> 16;
3143         int y = plane_state->base.src.y1 >> 16;
3144 
3145         dspcntr = DISPPLANE_GAMMA_ENABLE;
3146         dspcntr |= DISPLAY_PLANE_ENABLE;
3147 
3148         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3149                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3150 
3151         switch (fb->pixel_format) {
3152         case DRM_FORMAT_C8:
3153                 dspcntr |= DISPPLANE_8BPP;
3154                 break;
3155         case DRM_FORMAT_RGB565:
3156                 dspcntr |= DISPPLANE_BGRX565;
3157                 break;
3158         case DRM_FORMAT_XRGB8888:
3159                 dspcntr |= DISPPLANE_BGRX888;
3160                 break;
3161         case DRM_FORMAT_XBGR8888:
3162                 dspcntr |= DISPPLANE_RGBX888;
3163                 break;
3164         case DRM_FORMAT_XRGB2101010:
3165                 dspcntr |= DISPPLANE_BGRX101010;
3166                 break;
3167         case DRM_FORMAT_XBGR2101010:
3168                 dspcntr |= DISPPLANE_RGBX101010;
3169                 break;
3170         default:
3171                 BUG();
3172         }
3173 
3174         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3175                 dspcntr |= DISPPLANE_TILED;
3176 
3177         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3178                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3179 
3180         intel_add_fb_offsets(&x, &y, plane_state, 0);
3181 
3182         intel_crtc->dspaddr_offset =
3183                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3184 
3185         if (rotation == DRM_ROTATE_180) {
3186                 dspcntr |= DISPPLANE_ROTATE_180;
3187 
3188                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3189                         x += (crtc_state->pipe_src_w - 1);
3190                         y += (crtc_state->pipe_src_h - 1);
3191                 }
3192         }
3193 
3194         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3195 
3196         intel_crtc->adjusted_x = x;
3197         intel_crtc->adjusted_y = y;
3198 
3199         I915_WRITE(reg, dspcntr);
3200 
3201         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3202         I915_WRITE(DSPSURF(plane),
3203                    intel_fb_gtt_offset(fb, rotation) +
3204                    intel_crtc->dspaddr_offset);
3205         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3206                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3207         } else {
3208                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3209                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3210         }
3211         POSTING_READ(reg);
3212 }
3213 
3214 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3215                               uint64_t fb_modifier, uint32_t pixel_format)
3216 {
3217         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3218                 return 64;
3219         } else {
3220                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3221 
3222                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3223         }
3224 }
3225 
3226 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3227                         unsigned int rotation)
3228 {
3229         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3230         struct i915_ggtt_view view;
3231         struct i915_vma *vma;
3232 
3233         intel_fill_fb_ggtt_view(&view, fb, rotation);
3234 
3235         vma = i915_gem_object_to_ggtt(obj, &view);
3236         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3237                  view.type))
3238                 return -1;
3239 
3240         return i915_ggtt_offset(vma);
3241 }
3242 
3243 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3244 {
3245         struct drm_device *dev = intel_crtc->base.dev;
3246         struct drm_i915_private *dev_priv = to_i915(dev);
3247 
3248         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3249         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3250         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3251 }
3252 
3253 /*
3254  * This function detaches (aka. unbinds) unused scalers in hardware
3255  */
3256 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3257 {
3258         struct intel_crtc_scaler_state *scaler_state;
3259         int i;
3260 
3261         scaler_state = &intel_crtc->config->scaler_state;
3262 
3263         /* loop through and disable scalers that aren't in use */
3264         for (i = 0; i < intel_crtc->num_scalers; i++) {
3265                 if (!scaler_state->scalers[i].in_use)
3266                         skl_detach_scaler(intel_crtc, i);
3267         }
3268 }
3269 
3270 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3271                      unsigned int rotation)
3272 {
3273         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3274         u32 stride = intel_fb_pitch(fb, plane, rotation);
3275 
3276         /*
3277          * The stride is either expressed as a multiple of 64 bytes chunks for
3278          * linear buffers or in number of tiles for tiled buffers.
3279          */
3280         if (intel_rotation_90_or_270(rotation)) {
3281                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3282 
3283                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3284         } else {
3285                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3286                                                     fb->pixel_format);
3287         }
3288 
3289         return stride;
3290 }
3291 
3292 u32 skl_plane_ctl_format(uint32_t pixel_format)
3293 {
3294         switch (pixel_format) {
3295         case DRM_FORMAT_C8:
3296                 return PLANE_CTL_FORMAT_INDEXED;
3297         case DRM_FORMAT_RGB565:
3298                 return PLANE_CTL_FORMAT_RGB_565;
3299         case DRM_FORMAT_XBGR8888:
3300                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3301         case DRM_FORMAT_XRGB8888:
3302                 return PLANE_CTL_FORMAT_XRGB_8888;
3303         /*
3304          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3305          * to be already pre-multiplied. We need to add a knob (or a different
3306          * DRM_FORMAT) for user-space to configure that.
3307          */
3308         case DRM_FORMAT_ABGR8888:
3309                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3310                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311         case DRM_FORMAT_ARGB8888:
3312                 return PLANE_CTL_FORMAT_XRGB_8888 |
3313                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3314         case DRM_FORMAT_XRGB2101010:
3315                 return PLANE_CTL_FORMAT_XRGB_2101010;
3316         case DRM_FORMAT_XBGR2101010:
3317                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3318         case DRM_FORMAT_YUYV:
3319                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3320         case DRM_FORMAT_YVYU:
3321                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3322         case DRM_FORMAT_UYVY:
3323                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3324         case DRM_FORMAT_VYUY:
3325                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3326         default:
3327                 MISSING_CASE(pixel_format);
3328         }
3329 
3330         return 0;
3331 }
3332 
3333 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3334 {
3335         switch (fb_modifier) {
3336         case DRM_FORMAT_MOD_NONE:
3337                 break;
3338         case I915_FORMAT_MOD_X_TILED:
3339                 return PLANE_CTL_TILED_X;
3340         case I915_FORMAT_MOD_Y_TILED:
3341                 return PLANE_CTL_TILED_Y;
3342         case I915_FORMAT_MOD_Yf_TILED:
3343                 return PLANE_CTL_TILED_YF;
3344         default:
3345                 MISSING_CASE(fb_modifier);
3346         }
3347 
3348         return 0;
3349 }
3350 
3351 u32 skl_plane_ctl_rotation(unsigned int rotation)
3352 {
3353         switch (rotation) {
3354         case DRM_ROTATE_0:
3355                 break;
3356         /*
3357          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3358          * while i915 HW rotation is clockwise, thats why this swapping.
3359          */
3360         case DRM_ROTATE_90:
3361                 return PLANE_CTL_ROTATE_270;
3362         case DRM_ROTATE_180:
3363                 return PLANE_CTL_ROTATE_180;
3364         case DRM_ROTATE_270:
3365                 return PLANE_CTL_ROTATE_90;
3366         default:
3367                 MISSING_CASE(rotation);
3368         }
3369 
3370         return 0;
3371 }
3372 
3373 static void skylake_update_primary_plane(struct drm_plane *plane,
3374                                          const struct intel_crtc_state *crtc_state,
3375                                          const struct intel_plane_state *plane_state)
3376 {
3377         struct drm_device *dev = plane->dev;
3378         struct drm_i915_private *dev_priv = to_i915(dev);
3379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3380         struct drm_framebuffer *fb = plane_state->base.fb;
3381         const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3382         int pipe = intel_crtc->pipe;
3383         u32 plane_ctl;
3384         unsigned int rotation = plane_state->base.rotation;
3385         u32 stride = skl_plane_stride(fb, 0, rotation);
3386         u32 surf_addr = plane_state->main.offset;
3387         int scaler_id = plane_state->scaler_id;
3388         int src_x = plane_state->main.x;
3389         int src_y = plane_state->main.y;
3390         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3391         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3392         int dst_x = plane_state->base.dst.x1;
3393         int dst_y = plane_state->base.dst.y1;
3394         int dst_w = drm_rect_width(&plane_state->base.dst);
3395         int dst_h = drm_rect_height(&plane_state->base.dst);
3396 
3397         plane_ctl = PLANE_CTL_ENABLE |
3398                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3399                     PLANE_CTL_PIPE_CSC_ENABLE;
3400 
3401         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3402         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3403         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3404         plane_ctl |= skl_plane_ctl_rotation(rotation);
3405 
3406         /* Sizes are 0 based */
3407         src_w--;
3408         src_h--;
3409         dst_w--;
3410         dst_h--;
3411 
3412         intel_crtc->dspaddr_offset = surf_addr;
3413 
3414         intel_crtc->adjusted_x = src_x;
3415         intel_crtc->adjusted_y = src_y;
3416 
3417         if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3418                 skl_write_plane_wm(intel_crtc, wm, 0);
3419 
3420         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3421         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3422         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3423         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3424 
3425         if (scaler_id >= 0) {
3426                 uint32_t ps_ctrl = 0;
3427 
3428                 WARN_ON(!dst_w || !dst_h);
3429                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3430                         crtc_state->scaler_state.scalers[scaler_id].mode;
3431                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3432                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3433                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3434                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3435                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3436         } else {
3437                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3438         }
3439 
3440         I915_WRITE(PLANE_SURF(pipe, 0),
3441                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3442 
3443         POSTING_READ(PLANE_SURF(pipe, 0));
3444 }
3445 
3446 static void skylake_disable_primary_plane(struct drm_plane *primary,
3447                                           struct drm_crtc *crtc)
3448 {
3449         struct drm_device *dev = crtc->dev;
3450         struct drm_i915_private *dev_priv = to_i915(dev);
3451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452         int pipe = intel_crtc->pipe;
3453 
3454         /*
3455          * We only populate skl_results on watermark updates, and if the
3456          * plane's visiblity isn't actually changing neither is its watermarks.
3457          */
3458         if (!crtc->primary->state->visible)
3459                 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3460 
3461         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3462         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3463         POSTING_READ(PLANE_SURF(pipe, 0));
3464 }
3465 
3466 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3467 static int
3468 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3469                            int x, int y, enum mode_set_atomic state)
3470 {
3471         /* Support for kgdboc is disabled, this needs a major rework. */
3472         DRM_ERROR("legacy panic handler not supported any more.\n");
3473 
3474         return -ENODEV;
3475 }
3476 
3477 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3478 {
3479         struct intel_crtc *crtc;
3480 
3481         for_each_intel_crtc(&dev_priv->drm, crtc)
3482                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3483 }
3484 
3485 static void intel_update_primary_planes(struct drm_device *dev)
3486 {
3487         struct drm_crtc *crtc;
3488 
3489         for_each_crtc(dev, crtc) {
3490                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3491                 struct intel_plane_state *plane_state =
3492                         to_intel_plane_state(plane->base.state);
3493 
3494                 if (plane_state->base.visible)
3495                         plane->update_plane(&plane->base,
3496                                             to_intel_crtc_state(crtc->state),
3497                                             plane_state);
3498         }
3499 }
3500 
3501 static int
3502 __intel_display_resume(struct drm_device *dev,
3503                        struct drm_atomic_state *state)
3504 {
3505         struct drm_crtc_state *crtc_state;
3506         struct drm_crtc *crtc;
3507         int i, ret;
3508 
3509         intel_modeset_setup_hw_state(dev);
3510         i915_redisable_vga(dev);
3511 
3512         if (!state)
3513                 return 0;
3514 
3515         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3516                 /*
3517                  * Force recalculation even if we restore
3518                  * current state. With fast modeset this may not result
3519                  * in a modeset when the state is compatible.
3520                  */
3521                 crtc_state->mode_changed = true;
3522         }
3523 
3524         /* ignore any reset values/BIOS leftovers in the WM registers */
3525         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3526 
3527         ret = drm_atomic_commit(state);
3528 
3529         WARN_ON(ret == -EDEADLK);
3530         return ret;
3531 }
3532 
3533 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3534 {
3535         return intel_has_gpu_reset(dev_priv) &&
3536                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3537 }
3538 
3539 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3540 {
3541         struct drm_device *dev = &dev_priv->drm;
3542         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3543         struct drm_atomic_state *state;
3544         int ret;
3545 
3546         /*
3547          * Need mode_config.mutex so that we don't
3548          * trample ongoing ->detect() and whatnot.
3549          */
3550         mutex_lock(&dev->mode_config.mutex);
3551         drm_modeset_acquire_init(ctx, 0);
3552         while (1) {
3553                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3554                 if (ret != -EDEADLK)
3555                         break;
3556 
3557                 drm_modeset_backoff(ctx);
3558         }
3559 
3560         /* reset doesn't touch the display, but flips might get nuked anyway, */
3561         if (!i915.force_reset_modeset_test &&
3562             !gpu_reset_clobbers_display(dev_priv))
3563                 return;
3564 
3565         /*
3566          * Disabling the crtcs gracefully seems nicer. Also the
3567          * g33 docs say we should at least disable all the planes.
3568          */
3569         state = drm_atomic_helper_duplicate_state(dev, ctx);
3570         if (IS_ERR(state)) {
3571                 ret = PTR_ERR(state);
3572                 state = NULL;
3573                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3574                 goto err;
3575         }
3576 
3577         ret = drm_atomic_helper_disable_all(dev, ctx);
3578         if (ret) {
3579                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3580                 goto err;
3581         }
3582 
3583         dev_priv->modeset_restore_state = state;
3584         state->acquire_ctx = ctx;
3585         return;
3586 
3587 err:
3588         drm_atomic_state_free(state);
3589 }
3590 
3591 void intel_finish_reset(struct drm_i915_private *dev_priv)
3592 {
3593         struct drm_device *dev = &dev_priv->drm;
3594         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3595         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3596         int ret;
3597 
3598         /*
3599          * Flips in the rings will be nuked by the reset,
3600          * so complete all pending flips so that user space
3601          * will get its events and not get stuck.
3602          */
3603         intel_complete_page_flips(dev_priv);
3604 
3605         dev_priv->modeset_restore_state = NULL;
3606 
3607         dev_priv->modeset_restore_state = NULL;
3608 
3609         /* reset doesn't touch the display */
3610         if (!gpu_reset_clobbers_display(dev_priv)) {
3611                 if (!state) {
3612                         /*
3613                          * Flips in the rings have been nuked by the reset,
3614                          * so update the base address of all primary
3615                          * planes to the the last fb to make sure we're
3616                          * showing the correct fb after a reset.
3617                          *
3618                          * FIXME: Atomic will make this obsolete since we won't schedule
3619                          * CS-based flips (which might get lost in gpu resets) any more.
3620                          */
3621                         intel_update_primary_planes(dev);
3622                 } else {
3623                         ret = __intel_display_resume(dev, state);
3624                         if (ret)
3625                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3626                 }
3627         } else {
3628                 /*
3629                  * The display has been reset as well,
3630                  * so need a full re-initialization.
3631                  */
3632                 intel_runtime_pm_disable_interrupts(dev_priv);
3633                 intel_runtime_pm_enable_interrupts(dev_priv);
3634 
3635                 intel_pps_unlock_regs_wa(dev_priv);
3636                 intel_modeset_init_hw(dev);
3637 
3638                 spin_lock_irq(&dev_priv->irq_lock);
3639                 if (dev_priv->display.hpd_irq_setup)
3640                         dev_priv->display.hpd_irq_setup(dev_priv);
3641                 spin_unlock_irq(&dev_priv->irq_lock);
3642 
3643                 ret = __intel_display_resume(dev, state);
3644                 if (ret)
3645                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3646 
3647                 intel_hpd_init(dev_priv);
3648         }
3649 
3650         drm_modeset_drop_locks(ctx);
3651         drm_modeset_acquire_fini(ctx);
3652         mutex_unlock(&dev->mode_config.mutex);
3653 }
3654 
3655 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3656 {
3657         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3658 
3659         if (i915_reset_in_progress(error))
3660                 return true;
3661 
3662         if (crtc->reset_count != i915_reset_count(error))
3663                 return true;
3664 
3665         return false;
3666 }
3667 
3668 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3669 {
3670         struct drm_device *dev = crtc->dev;
3671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3672         bool pending;
3673 
3674         if (abort_flip_on_reset(intel_crtc))
3675                 return false;
3676 
3677         spin_lock_irq(&dev->event_lock);
3678         pending = to_intel_crtc(crtc)->flip_work != NULL;
3679         spin_unlock_irq(&dev->event_lock);
3680 
3681         return pending;
3682 }
3683 
3684 static void intel_update_pipe_config(struct intel_crtc *crtc,
3685                                      struct intel_crtc_state *old_crtc_state)
3686 {
3687         struct drm_device *dev = crtc->base.dev;
3688         struct drm_i915_private *dev_priv = to_i915(dev);
3689         struct intel_crtc_state *pipe_config =
3690                 to_intel_crtc_state(crtc->base.state);
3691 
3692         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3693         crtc->base.mode = crtc->base.state->mode;
3694 
3695         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3696                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3697                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3698 
3699         /*
3700          * Update pipe size and adjust fitter if needed: the reason for this is
3701          * that in compute_mode_changes we check the native mode (not the pfit
3702          * mode) to see if we can flip rather than do a full mode set. In the
3703          * fastboot case, we'll flip, but if we don't update the pipesrc and
3704          * pfit state, we'll end up with a big fb scanned out into the wrong
3705          * sized surface.
3706          */
3707 
3708         I915_WRITE(PIPESRC(crtc->pipe),
3709                    ((pipe_config->pipe_src_w - 1) << 16) |
3710                    (pipe_config->pipe_src_h - 1));
3711 
3712         /* on skylake this is done by detaching scalers */
3713         if (INTEL_INFO(dev)->gen >= 9) {
3714                 skl_detach_scalers(crtc);
3715 
3716                 if (pipe_config->pch_pfit.enabled)
3717                         skylake_pfit_enable(crtc);
3718         } else if (HAS_PCH_SPLIT(dev)) {
3719                 if (pipe_config->pch_pfit.enabled)
3720                         ironlake_pfit_enable(crtc);
3721                 else if (old_crtc_state->pch_pfit.enabled)
3722                         ironlake_pfit_disable(crtc, true);
3723         }
3724 }
3725 
3726 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3727 {
3728         struct drm_device *dev = crtc->dev;
3729         struct drm_i915_private *dev_priv = to_i915(dev);
3730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3731         int pipe = intel_crtc->pipe;
3732         i915_reg_t reg;
3733         u32 temp;
3734 
3735         /* enable normal train */
3736         reg = FDI_TX_CTL(pipe);
3737         temp = I915_READ(reg);
3738         if (IS_IVYBRIDGE(dev)) {
3739                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3740                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3741         } else {
3742                 temp &= ~FDI_LINK_TRAIN_NONE;
3743                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3744         }
3745         I915_WRITE(reg, temp);
3746 
3747         reg = FDI_RX_CTL(pipe);
3748         temp = I915_READ(reg);
3749         if (HAS_PCH_CPT(dev)) {
3750                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3751                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3752         } else {
3753                 temp &= ~FDI_LINK_TRAIN_NONE;
3754                 temp |= FDI_LINK_TRAIN_NONE;
3755         }
3756         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3757 
3758         /* wait one idle pattern time */
3759         POSTING_READ(reg);
3760         udelay(1000);
3761 
3762         /* IVB wants error correction enabled */
3763         if (IS_IVYBRIDGE(dev))
3764                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3765                            FDI_FE_ERRC_ENABLE);
3766 }
3767 
3768 /* The FDI link training functions for ILK/Ibexpeak. */
3769 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3770 {
3771         struct drm_device *dev = crtc->dev;
3772         struct drm_i915_private *dev_priv = to_i915(dev);
3773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3774         int pipe = intel_crtc->pipe;
3775         i915_reg_t reg;
3776         u32 temp, tries;
3777 
3778         /* FDI needs bits from pipe first */
3779         assert_pipe_enabled(dev_priv, pipe);
3780 
3781         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3782            for train result */
3783         reg = FDI_RX_IMR(pipe);
3784         temp = I915_READ(reg);
3785         temp &= ~FDI_RX_SYMBOL_LOCK;
3786         temp &= ~FDI_RX_BIT_LOCK;
3787         I915_WRITE(reg, temp);
3788         I915_READ(reg);
3789         udelay(150);
3790 
3791         /* enable CPU FDI TX and PCH FDI RX */
3792         reg = FDI_TX_CTL(pipe);
3793         temp = I915_READ(reg);
3794         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3795         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3796         temp &= ~FDI_LINK_TRAIN_NONE;
3797         temp |= FDI_LINK_TRAIN_PATTERN_1;
3798         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3799 
3800         reg = FDI_RX_CTL(pipe);
3801         temp = I915_READ(reg);
3802         temp &= ~FDI_LINK_TRAIN_NONE;
3803         temp |= FDI_LINK_TRAIN_PATTERN_1;
3804         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3805 
3806         POSTING_READ(reg);
3807         udelay(150);
3808 
3809         /* Ironlake workaround, enable clock pointer after FDI enable*/
3810         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3811         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3812                    FDI_RX_PHASE_SYNC_POINTER_EN);
3813 
3814         reg = FDI_RX_IIR(pipe);
3815         for (tries = 0; tries < 5; tries++) {
3816                 temp = I915_READ(reg);
3817                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3818 
3819                 if ((temp & FDI_RX_BIT_LOCK)) {
3820                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3821                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3822                         break;
3823                 }
3824         }
3825         if (tries == 5)
3826                 DRM_ERROR("FDI train 1 fail!\n");
3827 
3828         /* Train 2 */
3829         reg = FDI_TX_CTL(pipe);
3830         temp = I915_READ(reg);
3831         temp &= ~FDI_LINK_TRAIN_NONE;
3832         temp |= FDI_LINK_TRAIN_PATTERN_2;
3833         I915_WRITE(reg, temp);
3834 
3835         reg = FDI_RX_CTL(pipe);
3836         temp = I915_READ(reg);
3837         temp &= ~FDI_LINK_TRAIN_NONE;
3838         temp |= FDI_LINK_TRAIN_PATTERN_2;
3839         I915_WRITE(reg, temp);
3840 
3841         POSTING_READ(reg);
3842         udelay(150);
3843 
3844         reg = FDI_RX_IIR(pipe);
3845         for (tries = 0; tries < 5; tries++) {
3846                 temp = I915_READ(reg);
3847                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3848 
3849                 if (temp & FDI_RX_SYMBOL_LOCK) {
3850                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3851                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3852                         break;
3853                 }
3854         }
3855         if (tries == 5)
3856                 DRM_ERROR("FDI train 2 fail!\n");
3857 
3858         DRM_DEBUG_KMS("FDI train done\n");
3859 
3860 }
3861 
3862 static const int snb_b_fdi_train_param[] = {
3863         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3864         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3865         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3866         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3867 };
3868 
3869 /* The FDI link training functions for SNB/Cougarpoint. */
3870 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3871 {
3872         struct drm_device *dev = crtc->dev;
3873         struct drm_i915_private *dev_priv = to_i915(dev);
3874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875         int pipe = intel_crtc->pipe;
3876         i915_reg_t reg;
3877         u32 temp, i, retry;
3878 
3879         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3880            for train result */
3881         reg = FDI_RX_IMR(pipe);
3882         temp = I915_READ(reg);
3883         temp &= ~FDI_RX_SYMBOL_LOCK;
3884         temp &= ~FDI_RX_BIT_LOCK;
3885         I915_WRITE(reg, temp);
3886 
3887         POSTING_READ(reg);
3888         udelay(150);
3889 
3890         /* enable CPU FDI TX and PCH FDI RX */
3891         reg = FDI_TX_CTL(pipe);
3892         temp = I915_READ(reg);
3893         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3894         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3895         temp &= ~FDI_LINK_TRAIN_NONE;
3896         temp |= FDI_LINK_TRAIN_PATTERN_1;
3897         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3898         /* SNB-B */
3899         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3900         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3901 
3902         I915_WRITE(FDI_RX_MISC(pipe),
3903                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3904 
3905         reg = FDI_RX_CTL(pipe);
3906         temp = I915_READ(reg);
3907         if (HAS_PCH_CPT(dev)) {
3908                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3909                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3910         } else {
3911                 temp &= ~FDI_LINK_TRAIN_NONE;
3912                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3913         }
3914         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3915 
3916         POSTING_READ(reg);
3917         udelay(150);
3918 
3919         for (i = 0; i < 4; i++) {
3920                 reg = FDI_TX_CTL(pipe);
3921                 temp = I915_READ(reg);
3922                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3923                 temp |= snb_b_fdi_train_param[i];
3924                 I915_WRITE(reg, temp);
3925 
3926                 POSTING_READ(reg);
3927                 udelay(500);
3928 
3929                 for (retry = 0; retry < 5; retry++) {
3930                         reg = FDI_RX_IIR(pipe);
3931                         temp = I915_READ(reg);
3932                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3933                         if (temp & FDI_RX_BIT_LOCK) {
3934                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3935                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3936                                 break;
3937                         }
3938                         udelay(50);
3939                 }
3940                 if (retry < 5)
3941                         break;
3942         }
3943         if (i == 4)
3944                 DRM_ERROR("FDI train 1 fail!\n");
3945 
3946         /* Train 2 */
3947         reg = FDI_TX_CTL(pipe);
3948         temp = I915_READ(reg);
3949         temp &= ~FDI_LINK_TRAIN_NONE;
3950         temp |= FDI_LINK_TRAIN_PATTERN_2;
3951         if (IS_GEN6(dev)) {
3952                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3953                 /* SNB-B */
3954                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3955         }
3956         I915_WRITE(reg, temp);
3957 
3958         reg = FDI_RX_CTL(pipe);
3959         temp = I915_READ(reg);
3960         if (HAS_PCH_CPT(dev)) {
3961                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3962                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3963         } else {
3964                 temp &= ~FDI_LINK_TRAIN_NONE;
3965                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3966         }
3967         I915_WRITE(reg, temp);
3968 
3969         POSTING_READ(reg);
3970         udelay(150);
3971 
3972         for (i = 0; i < 4; i++) {
3973                 reg = FDI_TX_CTL(pipe);
3974                 temp = I915_READ(reg);
3975                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3976                 temp |= snb_b_fdi_train_param[i];
3977                 I915_WRITE(reg, temp);
3978 
3979                 POSTING_READ(reg);
3980                 udelay(500);
3981 
3982                 for (retry = 0; retry < 5; retry++) {
3983                         reg = FDI_RX_IIR(pipe);
3984                         temp = I915_READ(reg);
3985                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3986                         if (temp & FDI_RX_SYMBOL_LOCK) {
3987                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3988                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3989                                 break;
3990                         }
3991                         udelay(50);
3992                 }
3993                 if (retry < 5)
3994                         break;
3995         }
3996         if (i == 4)
3997                 DRM_ERROR("FDI train 2 fail!\n");
3998 
3999         DRM_DEBUG_KMS("FDI train done.\n");
4000 }
4001 
4002 /* Manual link training for Ivy Bridge A0 parts */
4003 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4004 {
4005         struct drm_device *dev = crtc->dev;
4006         struct drm_i915_private *dev_priv = to_i915(dev);
4007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4008         int pipe = intel_crtc->pipe;
4009         i915_reg_t reg;
4010         u32 temp, i, j;
4011 
4012         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4013            for train result */
4014         reg = FDI_RX_IMR(pipe);
4015         temp = I915_READ(reg);
4016         temp &= ~FDI_RX_SYMBOL_LOCK;
4017         temp &= ~FDI_RX_BIT_LOCK;
4018         I915_WRITE(reg, temp);
4019 
4020         POSTING_READ(reg);
4021         udelay(150);
4022 
4023         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4024                       I915_READ(FDI_RX_IIR(pipe)));
4025 
4026         /* Try each vswing and preemphasis setting twice before moving on */
4027         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4028                 /* disable first in case we need to retry */
4029                 reg = FDI_TX_CTL(pipe);
4030                 temp = I915_READ(reg);
4031                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4032                 temp &= ~FDI_TX_ENABLE;
4033                 I915_WRITE(reg, temp);
4034 
4035                 reg = FDI_RX_CTL(pipe);
4036                 temp = I915_READ(reg);
4037                 temp &= ~FDI_LINK_TRAIN_AUTO;
4038                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4039                 temp &= ~FDI_RX_ENABLE;
4040                 I915_WRITE(reg, temp);
4041 
4042                 /* enable CPU FDI TX and PCH FDI RX */
4043                 reg = FDI_TX_CTL(pipe);
4044                 temp = I915_READ(reg);
4045                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4046                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4047                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4048                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4049                 temp |= snb_b_fdi_train_param[j/2];
4050                 temp |= FDI_COMPOSITE_SYNC;
4051                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4052 
4053                 I915_WRITE(FDI_RX_MISC(pipe),
4054                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4055 
4056                 reg = FDI_RX_CTL(pipe);
4057                 temp = I915_READ(reg);
4058                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4059                 temp |= FDI_COMPOSITE_SYNC;
4060                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4061 
4062                 POSTING_READ(reg);
4063                 udelay(1); /* should be 0.5us */
4064 
4065                 for (i = 0; i < 4; i++) {
4066                         reg = FDI_RX_IIR(pipe);
4067                         temp = I915_READ(reg);
4068                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4069 
4070                         if (temp & FDI_RX_BIT_LOCK ||
4071                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4072                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4073                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4074                                               i);
4075                                 break;
4076                         }
4077                         udelay(1); /* should be 0.5us */
4078                 }
4079                 if (i == 4) {
4080                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4081                         continue;
4082                 }
4083 
4084                 /* Train 2 */
4085                 reg = FDI_TX_CTL(pipe);
4086                 temp = I915_READ(reg);
4087                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4088                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4089                 I915_WRITE(reg, temp);
4090 
4091                 reg = FDI_RX_CTL(pipe);
4092                 temp = I915_READ(reg);
4093                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4094                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4095                 I915_WRITE(reg, temp);
4096 
4097                 POSTING_READ(reg);
4098                 udelay(2); /* should be 1.5us */
4099 
4100                 for (i = 0; i < 4; i++) {
4101                         reg = FDI_RX_IIR(pipe);
4102                         temp = I915_READ(reg);
4103                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4104 
4105                         if (temp & FDI_RX_SYMBOL_LOCK ||
4106                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4107                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4108                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4109                                               i);
4110                                 goto train_done;
4111                         }
4112                         udelay(2); /* should be 1.5us */
4113                 }
4114                 if (i == 4)
4115                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4116         }
4117 
4118 train_done:
4119         DRM_DEBUG_KMS("FDI train done.\n");
4120 }
4121 
4122 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4123 {
4124         struct drm_device *dev = intel_crtc->base.dev;
4125         struct drm_i915_private *dev_priv = to_i915(dev);
4126         int pipe = intel_crtc->pipe;
4127         i915_reg_t reg;
4128         u32 temp;
4129 
4130         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4131         reg = FDI_RX_CTL(pipe);
4132         temp = I915_READ(reg);
4133         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4134         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4135         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4136         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4137 
4138         POSTING_READ(reg);
4139         udelay(200);
4140 
4141         /* Switch from Rawclk to PCDclk */
4142         temp = I915_READ(reg);
4143         I915_WRITE(reg, temp | FDI_PCDCLK);
4144 
4145         POSTING_READ(reg);
4146         udelay(200);
4147 
4148         /* Enable CPU FDI TX PLL, always on for Ironlake */
4149         reg = FDI_TX_CTL(pipe);
4150         temp = I915_READ(reg);
4151         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4152                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4153 
4154                 POSTING_READ(reg);
4155                 udelay(100);
4156         }
4157 }
4158 
4159 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4160 {
4161         struct drm_device *dev = intel_crtc->base.dev;
4162         struct drm_i915_private *dev_priv = to_i915(dev);
4163         int pipe = intel_crtc->pipe;
4164         i915_reg_t reg;
4165         u32 temp;
4166 
4167         /* Switch from PCDclk to Rawclk */
4168         reg = FDI_RX_CTL(pipe);
4169         temp = I915_READ(reg);
4170         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4171 
4172         /* Disable CPU FDI TX PLL */
4173         reg = FDI_TX_CTL(pipe);
4174         temp = I915_READ(reg);
4175         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4176 
4177         POSTING_READ(reg);
4178         udelay(100);
4179 
4180         reg = FDI_RX_CTL(pipe);
4181         temp = I915_READ(reg);
4182         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4183 
4184         /* Wait for the clocks to turn off. */
4185         POSTING_READ(reg);
4186         udelay(100);
4187 }
4188 
4189 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4190 {
4191         struct drm_device *dev = crtc->dev;
4192         struct drm_i915_private *dev_priv = to_i915(dev);
4193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4194         int pipe = intel_crtc->pipe;
4195         i915_reg_t reg;
4196         u32 temp;
4197 
4198         /* disable CPU FDI tx and PCH FDI rx */
4199         reg = FDI_TX_CTL(pipe);
4200         temp = I915_READ(reg);
4201         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4202         POSTING_READ(reg);
4203 
4204         reg = FDI_RX_CTL(pipe);
4205         temp = I915_READ(reg);
4206         temp &= ~(0x7 << 16);
4207         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4208         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4209 
4210         POSTING_READ(reg);
4211         udelay(100);
4212 
4213         /* Ironlake workaround, disable clock pointer after downing FDI */
4214         if (HAS_PCH_IBX(dev))
4215                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4216 
4217         /* still set train pattern 1 */
4218         reg = FDI_TX_CTL(pipe);
4219         temp = I915_READ(reg);
4220         temp &= ~FDI_LINK_TRAIN_NONE;
4221         temp |= FDI_LINK_TRAIN_PATTERN_1;
4222         I915_WRITE(reg, temp);
4223 
4224         reg = FDI_RX_CTL(pipe);
4225         temp = I915_READ(reg);
4226         if (HAS_PCH_CPT(dev)) {
4227                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4228                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4229         } else {
4230                 temp &= ~FDI_LINK_TRAIN_NONE;
4231                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4232         }
4233         /* BPC in FDI rx is consistent with that in PIPECONF */
4234         temp &= ~(0x07 << 16);
4235         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4236         I915_WRITE(reg, temp);
4237 
4238         POSTING_READ(reg);
4239         udelay(100);
4240 }
4241 
4242 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4243 {
4244         struct intel_crtc *crtc;
4245 
4246         /* Note that we don't need to be called with mode_config.lock here
4247          * as our list of CRTC objects is static for the lifetime of the
4248          * device and so cannot disappear as we iterate. Similarly, we can
4249          * happily treat the predicates as racy, atomic checks as userspace
4250          * cannot claim and pin a new fb without at least acquring the
4251          * struct_mutex and so serialising with us.
4252          */
4253         for_each_intel_crtc(dev, crtc) {
4254                 if (atomic_read(&crtc->unpin_work_count) == 0)
4255                         continue;
4256 
4257                 if (crtc->flip_work)
4258                         intel_wait_for_vblank(dev, crtc->pipe);
4259 
4260                 return true;
4261         }
4262 
4263         return false;
4264 }
4265 
4266 static void page_flip_completed(struct intel_crtc *intel_crtc)
4267 {
4268         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4269         struct intel_flip_work *work = intel_crtc->flip_work;
4270 
4271         intel_crtc->flip_work = NULL;
4272 
4273         if (work->event)
4274                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4275 
4276         drm_crtc_vblank_put(&intel_crtc->base);
4277 
4278         wake_up_all(&dev_priv->pending_flip_queue);
4279         queue_work(dev_priv->wq, &work->unpin_work);
4280 
4281         trace_i915_flip_complete(intel_crtc->plane,
4282                                  work->pending_flip_obj);
4283 }
4284 
4285 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4286 {
4287         struct drm_device *dev = crtc->dev;
4288         struct drm_i915_private *dev_priv = to_i915(dev);
4289         long ret;
4290 
4291         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4292 
4293         ret = wait_event_interruptible_timeout(
4294                                         dev_priv->pending_flip_queue,
4295                                         !intel_crtc_has_pending_flip(crtc),
4296                                         60*HZ);
4297 
4298         if (ret < 0)
4299                 return ret;
4300 
4301         if (ret == 0) {
4302                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303                 struct intel_flip_work *work;
4304 
4305                 spin_lock_irq(&dev->event_lock);
4306                 work = intel_crtc->flip_work;
4307                 if (work && !is_mmio_work(work)) {
4308                         WARN_ONCE(1, "Removing stuck page flip\n");
4309                         page_flip_completed(intel_crtc);
4310                 }
4311                 spin_unlock_irq(&dev->event_lock);
4312         }
4313 
4314         return 0;
4315 }
4316 
4317 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4318 {
4319         u32 temp;
4320 
4321         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4322 
4323         mutex_lock(&dev_priv->sb_lock);
4324 
4325         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4326         temp |= SBI_SSCCTL_DISABLE;
4327         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4328 
4329         mutex_unlock(&dev_priv->sb_lock);
4330 }
4331 
4332 /* Program iCLKIP clock to the desired frequency */
4333 static void lpt_program_iclkip(struct drm_crtc *crtc)
4334 {
4335         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4336         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4337         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4338         u32 temp;
4339 
4340         lpt_disable_iclkip(dev_priv);
4341 
4342         /* The iCLK virtual clock root frequency is in MHz,
4343          * but the adjusted_mode->crtc_clock in in KHz. To get the
4344          * divisors, it is necessary to divide one by another, so we
4345          * convert the virtual clock precision to KHz here for higher
4346          * precision.
4347          */
4348         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4349                 u32 iclk_virtual_root_freq = 172800 * 1000;
4350                 u32 iclk_pi_range = 64;
4351                 u32 desired_divisor;
4352 
4353                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4354                                                     clock << auxdiv);
4355                 divsel = (desired_divisor / iclk_pi_range) - 2;
4356                 phaseinc = desired_divisor % iclk_pi_range;
4357 
4358                 /*
4359                  * Near 20MHz is a corner case which is
4360                  * out of range for the 7-bit divisor
4361                  */
4362                 if (divsel <= 0x7f)
4363                         break;
4364         }
4365 
4366         /* This should not happen with any sane values */
4367         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4368                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4369         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4370                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4371 
4372         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4373                         clock,
4374                         auxdiv,
4375                         divsel,
4376                         phasedir,
4377                         phaseinc);
4378 
4379         mutex_lock(&dev_priv->sb_lock);
4380 
4381         /* Program SSCDIVINTPHASE6 */
4382         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4383         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4384         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4385         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4386         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4387         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4388         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4389         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4390 
4391         /* Program SSCAUXDIV */
4392         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4393         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4394         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4395         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4396 
4397         /* Enable modulator and associated divider */
4398         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4399         temp &= ~SBI_SSCCTL_DISABLE;
4400         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4401 
4402         mutex_unlock(&dev_priv->sb_lock);
4403 
4404         /* Wait for initialization time */
4405         udelay(24);
4406 
4407         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4408 }
4409 
4410 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4411 {
4412         u32 divsel, phaseinc, auxdiv;
4413         u32 iclk_virtual_root_freq = 172800 * 1000;
4414         u32 iclk_pi_range = 64;
4415         u32 desired_divisor;
4416         u32 temp;
4417 
4418         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4419                 return 0;
4420 
4421         mutex_lock(&dev_priv->sb_lock);
4422 
4423         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4424         if (temp & SBI_SSCCTL_DISABLE) {
4425                 mutex_unlock(&dev_priv->sb_lock);
4426                 return 0;
4427         }
4428 
4429         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4430         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4431                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4432         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4433                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4434 
4435         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4436         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4437                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4438 
4439         mutex_unlock(&dev_priv->sb_lock);
4440 
4441         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4442 
4443         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4444                                  desired_divisor << auxdiv);
4445 }
4446 
4447 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4448                                                 enum pipe pch_transcoder)
4449 {
4450         struct drm_device *dev = crtc->base.dev;
4451         struct drm_i915_private *dev_priv = to_i915(dev);
4452         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4453 
4454         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4455                    I915_READ(HTOTAL(cpu_transcoder)));
4456         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4457                    I915_READ(HBLANK(cpu_transcoder)));
4458         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4459                    I915_READ(HSYNC(cpu_transcoder)));
4460 
4461         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4462                    I915_READ(VTOTAL(cpu_transcoder)));
4463         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4464                    I915_READ(VBLANK(cpu_transcoder)));
4465         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4466                    I915_READ(VSYNC(cpu_transcoder)));
4467         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4468                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4469 }
4470 
4471 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4472 {
4473         struct drm_i915_private *dev_priv = to_i915(dev);
4474         uint32_t temp;
4475 
4476         temp = I915_READ(SOUTH_CHICKEN1);
4477         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4478                 return;
4479 
4480         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4481         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4482 
4483         temp &= ~FDI_BC_BIFURCATION_SELECT;
4484         if (enable)
4485                 temp |= FDI_BC_BIFURCATION_SELECT;
4486 
4487         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4488         I915_WRITE(SOUTH_CHICKEN1, temp);
4489         POSTING_READ(SOUTH_CHICKEN1);
4490 }
4491 
4492 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4493 {
4494         struct drm_device *dev = intel_crtc->base.dev;
4495 
4496         switch (intel_crtc->pipe) {
4497         case PIPE_A:
4498                 break;
4499         case PIPE_B:
4500                 if (intel_crtc->config->fdi_lanes > 2)
4501                         cpt_set_fdi_bc_bifurcation(dev, false);
4502                 else
4503                         cpt_set_fdi_bc_bifurcation(dev, true);
4504 
4505                 break;
4506         case PIPE_C:
4507                 cpt_set_fdi_bc_bifurcation(dev, true);
4508 
4509                 break;
4510         default:
4511                 BUG();
4512         }
4513 }
4514 
4515 /* Return which DP Port should be selected for Transcoder DP control */
4516 static enum port
4517 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4518 {
4519         struct drm_device *dev = crtc->dev;
4520         struct intel_encoder *encoder;
4521 
4522         for_each_encoder_on_crtc(dev, crtc, encoder) {
4523                 if (encoder->type == INTEL_OUTPUT_DP ||
4524                     encoder->type == INTEL_OUTPUT_EDP)
4525                         return enc_to_dig_port(&encoder->base)->port;
4526         }
4527 
4528         return -1;
4529 }
4530 
4531 /*
4532  * Enable PCH resources required for PCH ports:
4533  *   - PCH PLLs
4534  *   - FDI training & RX/TX
4535  *   - update transcoder timings
4536  *   - DP transcoding bits
4537  *   - transcoder
4538  */
4539 static void ironlake_pch_enable(struct drm_crtc *crtc)
4540 {
4541         struct drm_device *dev = crtc->dev;
4542         struct drm_i915_private *dev_priv = to_i915(dev);
4543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4544         int pipe = intel_crtc->pipe;
4545         u32 temp;
4546 
4547         assert_pch_transcoder_disabled(dev_priv, pipe);
4548 
4549         if (IS_IVYBRIDGE(dev))
4550                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4551 
4552         /* Write the TU size bits before fdi link training, so that error
4553          * detection works. */
4554         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4555                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4556 
4557         /* For PCH output, training FDI link */
4558         dev_priv->display.fdi_link_train(crtc);
4559 
4560         /* We need to program the right clock selection before writing the pixel
4561          * mutliplier into the DPLL. */
4562         if (HAS_PCH_CPT(dev)) {
4563                 u32 sel;
4564 
4565                 temp = I915_READ(PCH_DPLL_SEL);
4566                 temp |= TRANS_DPLL_ENABLE(pipe);
4567                 sel = TRANS_DPLLB_SEL(pipe);
4568                 if (intel_crtc->config->shared_dpll ==
4569                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4570                         temp |= sel;
4571                 else
4572                         temp &= ~sel;
4573                 I915_WRITE(PCH_DPLL_SEL, temp);
4574         }
4575 
4576         /* XXX: pch pll's can be enabled any time before we enable the PCH
4577          * transcoder, and we actually should do this to not upset any PCH
4578          * transcoder that already use the clock when we share it.
4579          *
4580          * Note that enable_shared_dpll tries to do the right thing, but
4581          * get_shared_dpll unconditionally resets the pll - we need that to have
4582          * the right LVDS enable sequence. */
4583         intel_enable_shared_dpll(intel_crtc);
4584 
4585         /* set transcoder timing, panel must allow it */
4586         assert_panel_unlocked(dev_priv, pipe);
4587         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4588 
4589         intel_fdi_normal_train(crtc);
4590 
4591         /* For PCH DP, enable TRANS_DP_CTL */
4592         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4593                 const struct drm_display_mode *adjusted_mode =
4594                         &intel_crtc->config->base.adjusted_mode;
4595                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4596                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4597                 temp = I915_READ(reg);
4598                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4599                           TRANS_DP_SYNC_MASK |
4600                           TRANS_DP_BPC_MASK);
4601                 temp |= TRANS_DP_OUTPUT_ENABLE;
4602                 temp |= bpc << 9; /* same format but at 11:9 */
4603 
4604                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4605                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4606                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4607                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4608 
4609                 switch (intel_trans_dp_port_sel(crtc)) {
4610                 case PORT_B:
4611                         temp |= TRANS_DP_PORT_SEL_B;
4612                         break;
4613                 case PORT_C:
4614                         temp |= TRANS_DP_PORT_SEL_C;
4615                         break;
4616                 case PORT_D:
4617                         temp |= TRANS_DP_PORT_SEL_D;
4618                         break;
4619                 default:
4620                         BUG();
4621                 }
4622 
4623                 I915_WRITE(reg, temp);
4624         }
4625 
4626         ironlake_enable_pch_transcoder(dev_priv, pipe);
4627 }
4628 
4629 static void lpt_pch_enable(struct drm_crtc *crtc)
4630 {
4631         struct drm_device *dev = crtc->dev;
4632         struct drm_i915_private *dev_priv = to_i915(dev);
4633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4635 
4636         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4637 
4638         lpt_program_iclkip(crtc);
4639 
4640         /* Set transcoder timing. */
4641         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4642 
4643         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4644 }
4645 
4646 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4647 {
4648         struct drm_i915_private *dev_priv = to_i915(dev);
4649         i915_reg_t dslreg = PIPEDSL(pipe);
4650         u32 temp;
4651 
4652         temp = I915_READ(dslreg);
4653         udelay(500);
4654         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4655                 if (wait_for(I915_READ(dslreg) != temp, 5))
4656                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4657         }
4658 }
4659 
4660 static int
4661 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4662                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4663                   int src_w, int src_h, int dst_w, int dst_h)
4664 {
4665         struct intel_crtc_scaler_state *scaler_state =
4666                 &crtc_state->scaler_state;
4667         struct intel_crtc *intel_crtc =
4668                 to_intel_crtc(crtc_state->base.crtc);
4669         int need_scaling;
4670 
4671         need_scaling = intel_rotation_90_or_270(rotation) ?
4672                 (src_h != dst_w || src_w != dst_h):
4673                 (src_w != dst_w || src_h != dst_h);
4674 
4675         /*
4676          * if plane is being disabled or scaler is no more required or force detach
4677          *  - free scaler binded to this plane/crtc
4678          *  - in order to do this, update crtc->scaler_usage
4679          *
4680          * Here scaler state in crtc_state is set free so that
4681          * scaler can be assigned to other user. Actual register
4682          * update to free the scaler is done in plane/panel-fit programming.
4683          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4684          */
4685         if (force_detach || !need_scaling) {
4686                 if (*scaler_id >= 0) {
4687                         scaler_state->scaler_users &= ~(1 << scaler_user);
4688                         scaler_state->scalers[*scaler_id].in_use = 0;
4689 
4690                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4691                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4692                                 intel_crtc->pipe, scaler_user, *scaler_id,
4693                                 scaler_state->scaler_users);
4694                         *scaler_id = -1;
4695                 }
4696                 return 0;
4697         }
4698 
4699         /* range checks */
4700         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4701                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4702 
4703                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4704                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4705                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4706                         "size is out of scaler range\n",
4707                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4708                 return -EINVAL;
4709         }
4710 
4711         /* mark this plane as a scaler user in crtc_state */
4712         scaler_state->scaler_users |= (1 << scaler_user);
4713         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4714                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4715                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4716                 scaler_state->scaler_users);
4717 
4718         return 0;
4719 }
4720 
4721 /**
4722  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4723  *
4724  * @state: crtc's scaler state
4725  *
4726  * Return
4727  *     0 - scaler_usage updated successfully
4728  *    error - requested scaling cannot be supported or other error condition
4729  */
4730 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4731 {
4732         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4733         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4734 
4735         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4736                       intel_crtc->base.base.id, intel_crtc->base.name,
4737                       intel_crtc->pipe, SKL_CRTC_INDEX);
4738 
4739         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4740                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4741                 state->pipe_src_w, state->pipe_src_h,
4742                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4743 }
4744 
4745 /**
4746  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4747  *
4748  * @state: crtc's scaler state
4749  * @plane_state: atomic plane state to update
4750  *
4751  * Return
4752  *     0 - scaler_usage updated successfully
4753  *    error - requested scaling cannot be supported or other error condition
4754  */
4755 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4756                                    struct intel_plane_state *plane_state)
4757 {
4758 
4759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4760         struct intel_plane *intel_plane =
4761                 to_intel_plane(plane_state->base.plane);
4762         struct drm_framebuffer *fb = plane_state->base.fb;
4763         int ret;
4764 
4765         bool force_detach = !fb || !plane_state->base.visible;
4766 
4767         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4768                       intel_plane->base.base.id, intel_plane->base.name,
4769                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4770 
4771         ret = skl_update_scaler(crtc_state, force_detach,
4772                                 drm_plane_index(&intel_plane->base),
4773                                 &plane_state->scaler_id,
4774                                 plane_state->base.rotation,
4775                                 drm_rect_width(&plane_state->base.src) >> 16,
4776                                 drm_rect_height(&plane_state->base.src) >> 16,
4777                                 drm_rect_width(&plane_state->base.dst),
4778                                 drm_rect_height(&plane_state->base.dst));
4779 
4780         if (ret || plane_state->scaler_id < 0)
4781                 return ret;
4782 
4783         /* check colorkey */
4784         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4785                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4786                               intel_plane->base.base.id,
4787                               intel_plane->base.name);
4788                 return -EINVAL;
4789         }
4790 
4791         /* Check src format */
4792         switch (fb->pixel_format) {
4793         case DRM_FORMAT_RGB565:
4794         case DRM_FORMAT_XBGR8888:
4795         case DRM_FORMAT_XRGB8888:
4796         case DRM_FORMAT_ABGR8888:
4797         case DRM_FORMAT_ARGB8888:
4798         case DRM_FORMAT_XRGB2101010:
4799         case DRM_FORMAT_XBGR2101010:
4800         case DRM_FORMAT_YUYV:
4801         case DRM_FORMAT_YVYU:
4802         case DRM_FORMAT_UYVY:
4803         case DRM_FORMAT_VYUY:
4804                 break;
4805         default:
4806                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4807                               intel_plane->base.base.id, intel_plane->base.name,
4808                               fb->base.id, fb->pixel_format);
4809                 return -EINVAL;
4810         }
4811 
4812         return 0;
4813 }
4814 
4815 static void skylake_scaler_disable(struct intel_crtc *crtc)
4816 {
4817         int i;
4818 
4819         for (i = 0; i < crtc->num_scalers; i++)
4820                 skl_detach_scaler(crtc, i);
4821 }
4822 
4823 static void skylake_pfit_enable(struct intel_crtc *crtc)
4824 {
4825         struct drm_device *dev = crtc->base.dev;
4826         struct drm_i915_private *dev_priv = to_i915(dev);
4827         int pipe = crtc->pipe;
4828         struct intel_crtc_scaler_state *scaler_state =
4829                 &crtc->config->scaler_state;
4830 
4831         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4832 
4833         if (crtc->config->pch_pfit.enabled) {
4834                 int id;
4835 
4836                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4837                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4838                         return;
4839                 }
4840 
4841                 id = scaler_state->scaler_id;
4842                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4843                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4844                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4845                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4846 
4847                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4848         }
4849 }
4850 
4851 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4852 {
4853         struct drm_device *dev = crtc->base.dev;
4854         struct drm_i915_private *dev_priv = to_i915(dev);
4855         int pipe = crtc->pipe;
4856 
4857         if (crtc->config->pch_pfit.enabled) {
4858                 /* Force use of hard-coded filter coefficients
4859                  * as some pre-programmed values are broken,
4860                  * e.g. x201.
4861                  */
4862                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4863                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4864                                                  PF_PIPE_SEL_IVB(pipe));
4865                 else
4866                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4867                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4868                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4869         }
4870 }
4871 
4872 void hsw_enable_ips(struct intel_crtc *crtc)
4873 {
4874         struct drm_device *dev = crtc->base.dev;
4875         struct drm_i915_private *dev_priv = to_i915(dev);
4876 
4877         if (!crtc->config->ips_enabled)
4878                 return;
4879 
4880         /*
4881          * We can only enable IPS after we enable a plane and wait for a vblank
4882          * This function is called from post_plane_update, which is run after
4883          * a vblank wait.
4884          */
4885 
4886         assert_plane_enabled(dev_priv, crtc->plane);
4887         if (IS_BROADWELL(dev)) {
4888                 mutex_lock(&dev_priv->rps.hw_lock);
4889                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4890                 mutex_unlock(&dev_priv->rps.hw_lock);
4891                 /* Quoting Art Runyan: "its not safe to expect any particular
4892                  * value in IPS_CTL bit 31 after enabling IPS through the
4893                  * mailbox." Moreover, the mailbox may return a bogus state,
4894                  * so we need to just enable it and continue on.
4895                  */
4896         } else {
4897                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4898                 /* The bit only becomes 1 in the next vblank, so this wait here
4899                  * is essentially intel_wait_for_vblank. If we don't have this
4900                  * and don't wait for vblanks until the end of crtc_enable, then
4901                  * the HW state readout code will complain that the expected
4902                  * IPS_CTL value is not the one we read. */
4903                 if (intel_wait_for_register(dev_priv,
4904                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4905                                             50))
4906                         DRM_ERROR("Timed out waiting for IPS enable\n");
4907         }
4908 }
4909 
4910 void hsw_disable_ips(struct intel_crtc *crtc)
4911 {
4912         struct drm_device *dev = crtc->base.dev;
4913         struct drm_i915_private *dev_priv = to_i915(dev);
4914 
4915         if (!crtc->config->ips_enabled)
4916                 return;
4917 
4918         assert_plane_enabled(dev_priv, crtc->plane);
4919         if (IS_BROADWELL(dev)) {
4920                 mutex_lock(&dev_priv->rps.hw_lock);
4921                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4922                 mutex_unlock(&dev_priv->rps.hw_lock);
4923                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4924                 if (intel_wait_for_register(dev_priv,
4925                                             IPS_CTL, IPS_ENABLE, 0,
4926                                             42))
4927                         DRM_ERROR("Timed out waiting for IPS disable\n");
4928         } else {
4929                 I915_WRITE(IPS_CTL, 0);
4930                 POSTING_READ(IPS_CTL);
4931         }
4932 
4933         /* We need to wait for a vblank before we can disable the plane. */
4934         intel_wait_for_vblank(dev, crtc->pipe);
4935 }
4936 
4937 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4938 {
4939         if (intel_crtc->overlay) {
4940                 struct drm_device *dev = intel_crtc->base.dev;
4941                 struct drm_i915_private *dev_priv = to_i915(dev);
4942 
4943                 mutex_lock(&dev->struct_mutex);
4944                 dev_priv->mm.interruptible = false;
4945                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4946                 dev_priv->mm.interruptible = true;
4947                 mutex_unlock(&dev->struct_mutex);
4948         }
4949 
4950         /* Let userspace switch the overlay on again. In most cases userspace
4951          * has to recompute where to put it anyway.
4952          */
4953 }
4954 
4955 /**
4956  * intel_post_enable_primary - Perform operations after enabling primary plane
4957  * @crtc: the CRTC whose primary plane was just enabled
4958  *
4959  * Performs potentially sleeping operations that must be done after the primary
4960  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4961  * called due to an explicit primary plane update, or due to an implicit
4962  * re-enable that is caused when a sprite plane is updated to no longer
4963  * completely hide the primary plane.
4964  */
4965 static void
4966 intel_post_enable_primary(struct drm_crtc *crtc)
4967 {
4968         struct drm_device *dev = crtc->dev;
4969         struct drm_i915_private *dev_priv = to_i915(dev);
4970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4971         int pipe = intel_crtc->pipe;
4972 
4973         /*
4974          * FIXME IPS should be fine as long as one plane is
4975          * enabled, but in practice it seems to have problems
4976          * when going from primary only to sprite only and vice
4977          * versa.
4978          */
4979         hsw_enable_ips(intel_crtc);
4980 
4981         /*
4982          * Gen2 reports pipe underruns whenever all planes are disabled.
4983          * So don't enable underrun reporting before at least some planes
4984          * are enabled.
4985          * FIXME: Need to fix the logic to work when we turn off all planes
4986          * but leave the pipe running.
4987          */
4988         if (IS_GEN2(dev))
4989                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4990 
4991         /* Underruns don't always raise interrupts, so check manually. */
4992         intel_check_cpu_fifo_underruns(dev_priv);
4993         intel_check_pch_fifo_underruns(dev_priv);
4994 }
4995 
4996 /* FIXME move all this to pre_plane_update() with proper state tracking */
4997 static void
4998 intel_pre_disable_primary(struct drm_crtc *crtc)
4999 {
5000         struct drm_device *dev = crtc->dev;
5001         struct drm_i915_private *dev_priv = to_i915(dev);
5002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5003         int pipe = intel_crtc->pipe;
5004 
5005         /*
5006          * Gen2 reports pipe underruns whenever all planes are disabled.
5007          * So diasble underrun reporting before all the planes get disabled.
5008          * FIXME: Need to fix the logic to work when we turn off all planes
5009          * but leave the pipe running.
5010          */
5011         if (IS_GEN2(dev))
5012                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5013 
5014         /*
5015          * FIXME IPS should be fine as long as one plane is
5016          * enabled, but in practice it seems to have problems
5017          * when going from primary only to sprite only and vice
5018          * versa.
5019          */
5020         hsw_disable_ips(intel_crtc);
5021 }
5022 
5023 /* FIXME get rid of this and use pre_plane_update */
5024 static void
5025 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5026 {
5027         struct drm_device *dev = crtc->dev;
5028         struct drm_i915_private *dev_priv = to_i915(dev);
5029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030         int pipe = intel_crtc->pipe;
5031 
5032         intel_pre_disable_primary(crtc);
5033 
5034         /*
5035          * Vblank time updates from the shadow to live plane control register
5036          * are blocked if the memory self-refresh mode is active at that
5037          * moment. So to make sure the plane gets truly disabled, disable
5038          * first the self-refresh mode. The self-refresh enable bit in turn
5039          * will be checked/applied by the HW only at the next frame start
5040          * event which is after the vblank start event, so we need to have a
5041          * wait-for-vblank between disabling the plane and the pipe.
5042          */
5043         if (HAS_GMCH_DISPLAY(dev)) {
5044                 intel_set_memory_cxsr(dev_priv, false);
5045                 dev_priv->wm.vlv.cxsr = false;
5046                 intel_wait_for_vblank(dev, pipe);
5047         }
5048 }
5049 
5050 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5051 {
5052         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5053         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5054         struct intel_crtc_state *pipe_config =
5055                 to_intel_crtc_state(crtc->base.state);
5056         struct drm_plane *primary = crtc->base.primary;
5057         struct drm_plane_state *old_pri_state =
5058                 drm_atomic_get_existing_plane_state(old_state, primary);
5059 
5060         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5061 
5062         crtc->wm.cxsr_allowed = true;
5063 
5064         if (pipe_config->update_wm_post && pipe_config->base.active)
5065                 intel_update_watermarks(&crtc->base);
5066 
5067         if (old_pri_state) {
5068                 struct intel_plane_state *primary_state =
5069                         to_intel_plane_state(primary->state);
5070                 struct intel_plane_state *old_primary_state =
5071                         to_intel_plane_state(old_pri_state);
5072 
5073                 intel_fbc_post_update(crtc);
5074 
5075                 if (primary_state->base.visible &&
5076                     (needs_modeset(&pipe_config->base) ||
5077                      !old_primary_state->base.visible))
5078                         intel_post_enable_primary(&crtc->base);
5079         }
5080 }
5081 
5082 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5083 {
5084         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5085         struct drm_device *dev = crtc->base.dev;
5086         struct drm_i915_private *dev_priv = to_i915(dev);
5087         struct intel_crtc_state *pipe_config =
5088                 to_intel_crtc_state(crtc->base.state);
5089         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5090         struct drm_plane *primary = crtc->base.primary;
5091         struct drm_plane_state *old_pri_state =
5092                 drm_atomic_get_existing_plane_state(old_state, primary);
5093         bool modeset = needs_modeset(&pipe_config->base);
5094 
5095         if (old_pri_state) {
5096                 struct intel_plane_state *primary_state =
5097                         to_intel_plane_state(primary->state);
5098                 struct intel_plane_state *old_primary_state =
5099                         to_intel_plane_state(old_pri_state);
5100 
5101                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5102 
5103                 if (old_primary_state->base.visible &&
5104                     (modeset || !primary_state->base.visible))
5105                         intel_pre_disable_primary(&crtc->base);
5106         }
5107 
5108         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5109                 crtc->wm.cxsr_allowed = false;
5110 
5111                 /*
5112                  * Vblank time updates from the shadow to live plane control register
5113                  * are blocked if the memory self-refresh mode is active at that
5114                  * moment. So to make sure the plane gets truly disabled, disable
5115                  * first the self-refresh mode. The self-refresh enable bit in turn
5116                  * will be checked/applied by the HW only at the next frame start
5117                  * event which is after the vblank start event, so we need to have a
5118                  * wait-for-vblank between disabling the plane and the pipe.
5119                  */
5120                 if (old_crtc_state->base.active) {
5121                         intel_set_memory_cxsr(dev_priv, false);
5122                         dev_priv->wm.vlv.cxsr = false;
5123                         intel_wait_for_vblank(dev, crtc->pipe);
5124                 }
5125         }
5126 
5127         /*
5128          * IVB workaround: must disable low power watermarks for at least
5129          * one frame before enabling scaling.  LP watermarks can be re-enabled
5130          * when scaling is disabled.
5131          *
5132          * WaCxSRDisabledForSpriteScaling:ivb
5133          */
5134         if (pipe_config->disable_lp_wm) {
5135                 ilk_disable_lp_wm(dev);
5136                 intel_wait_for_vblank(dev, crtc->pipe);
5137         }
5138 
5139         /*
5140          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5141          * watermark programming here.
5142          */
5143         if (needs_modeset(&pipe_config->base))
5144                 return;
5145 
5146         /*
5147          * For platforms that support atomic watermarks, program the
5148          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5149          * will be the intermediate values that are safe for both pre- and
5150          * post- vblank; when vblank happens, the 'active' values will be set
5151          * to the final 'target' values and we'll do this again to get the
5152          * optimal watermarks.  For gen9+ platforms, the values we program here
5153          * will be the final target values which will get automatically latched
5154          * at vblank time; no further programming will be necessary.
5155          *
5156          * If a platform hasn't been transitioned to atomic watermarks yet,
5157          * we'll continue to update watermarks the old way, if flags tell
5158          * us to.
5159          */
5160         if (dev_priv->display.initial_watermarks != NULL)
5161                 dev_priv->display.initial_watermarks(pipe_config);
5162         else if (pipe_config->update_wm_pre)
5163                 intel_update_watermarks(&crtc->base);
5164 }
5165 
5166 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5167 {
5168         struct drm_device *dev = crtc->dev;
5169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5170         struct drm_plane *p;
5171         int pipe = intel_crtc->pipe;
5172 
5173         intel_crtc_dpms_overlay_disable(intel_crtc);
5174 
5175         drm_for_each_plane_mask(p, dev, plane_mask)
5176                 to_intel_plane(p)->disable_plane(p, crtc);
5177 
5178         /*
5179          * FIXME: Once we grow proper nuclear flip support out of this we need
5180          * to compute the mask of flip planes precisely. For the time being
5181          * consider this a flip to a NULL plane.
5182          */
5183         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5184 }
5185 
5186 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5187                                           struct intel_crtc_state *crtc_state,
5188                                           struct drm_atomic_state *old_state)
5189 {
5190         struct drm_connector_state *old_conn_state;
5191         struct drm_connector *conn;
5192         int i;
5193 
5194         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5195                 struct drm_connector_state *conn_state = conn->state;
5196                 struct intel_encoder *encoder =
5197                         to_intel_encoder(conn_state->best_encoder);
5198 
5199                 if (conn_state->crtc != crtc)
5200                         continue;
5201 
5202                 if (encoder->pre_pll_enable)
5203                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5204         }
5205 }
5206 
5207 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5208                                       struct intel_crtc_state *crtc_state,
5209                                       struct drm_atomic_state *old_state)
5210 {
5211         struct drm_connector_state *old_conn_state;
5212         struct drm_connector *conn;
5213         int i;
5214 
5215         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5216                 struct drm_connector_state *conn_state = conn->state;
5217                 struct intel_encoder *encoder =
5218                         to_intel_encoder(conn_state->best_encoder);
5219 
5220                 if (conn_state->crtc != crtc)
5221                         continue;
5222 
5223                 if (encoder->pre_enable)
5224                         encoder->pre_enable(encoder, crtc_state, conn_state);
5225         }
5226 }
5227 
5228 static void intel_encoders_enable(struct drm_crtc *crtc,
5229                                   struct intel_crtc_state *crtc_state,
5230                                   struct drm_atomic_state *old_state)
5231 {
5232         struct drm_connector_state *old_conn_state;
5233         struct drm_connector *conn;
5234         int i;
5235 
5236         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5237                 struct drm_connector_state *conn_state = conn->state;
5238                 struct intel_encoder *encoder =
5239                         to_intel_encoder(conn_state->best_encoder);
5240 
5241                 if (conn_state->crtc != crtc)
5242                         continue;
5243 
5244                 encoder->enable(encoder, crtc_state, conn_state);
5245                 intel_opregion_notify_encoder(encoder, true);
5246         }
5247 }
5248 
5249 static void intel_encoders_disable(struct drm_crtc *crtc,
5250                                    struct intel_crtc_state *old_crtc_state,
5251                                    struct drm_atomic_state *old_state)
5252 {
5253         struct drm_connector_state *old_conn_state;
5254         struct drm_connector *conn;
5255         int i;
5256 
5257         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5258                 struct intel_encoder *encoder =
5259                         to_intel_encoder(old_conn_state->best_encoder);
5260 
5261                 if (old_conn_state->crtc != crtc)
5262                         continue;
5263 
5264                 intel_opregion_notify_encoder(encoder, false);
5265                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5266         }
5267 }
5268 
5269 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5270                                         struct intel_crtc_state *old_crtc_state,
5271                                         struct drm_atomic_state *old_state)
5272 {
5273         struct drm_connector_state *old_conn_state;
5274         struct drm_connector *conn;
5275         int i;
5276 
5277         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5278                 struct intel_encoder *encoder =
5279                         to_intel_encoder(old_conn_state->best_encoder);
5280 
5281                 if (old_conn_state->crtc != crtc)
5282                         continue;
5283 
5284                 if (encoder->post_disable)
5285                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5286         }
5287 }
5288 
5289 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5290                                             struct intel_crtc_state *old_crtc_state,
5291                                             struct drm_atomic_state *old_state)
5292 {
5293         struct drm_connector_state *old_conn_state;
5294         struct drm_connector *conn;
5295         int i;
5296 
5297         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5298                 struct intel_encoder *encoder =
5299                         to_intel_encoder(old_conn_state->best_encoder);
5300 
5301                 if (old_conn_state->crtc != crtc)
5302                         continue;
5303 
5304                 if (encoder->post_pll_disable)
5305                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5306         }
5307 }
5308 
5309 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5310                                  struct drm_atomic_state *old_state)
5311 {
5312         struct drm_crtc *crtc = pipe_config->base.crtc;
5313         struct drm_device *dev = crtc->dev;
5314         struct drm_i915_private *dev_priv = to_i915(dev);
5315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5316         int pipe = intel_crtc->pipe;
5317 
5318         if (WARN_ON(intel_crtc->active))
5319                 return;
5320 
5321         /*
5322          * Sometimes spurious CPU pipe underruns happen during FDI
5323          * training, at least with VGA+HDMI cloning. Suppress them.
5324          *
5325          * On ILK we get an occasional spurious CPU pipe underruns
5326          * between eDP port A enable and vdd enable. Also PCH port
5327          * enable seems to result in the occasional CPU pipe underrun.
5328          *
5329          * Spurious PCH underruns also occur during PCH enabling.
5330          */
5331         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5332                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5333         if (intel_crtc->config->has_pch_encoder)
5334                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5335 
5336         if (intel_crtc->config->has_pch_encoder)
5337                 intel_prepare_shared_dpll(intel_crtc);
5338 
5339         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5340                 intel_dp_set_m_n(intel_crtc, M1_N1);
5341 
5342         intel_set_pipe_timings(intel_crtc);
5343         intel_set_pipe_src_size(intel_crtc);
5344 
5345         if (intel_crtc->config->has_pch_encoder) {
5346                 intel_cpu_transcoder_set_m_n(intel_crtc,
5347                                      &intel_crtc->config->fdi_m_n, NULL);
5348         }
5349 
5350         ironlake_set_pipeconf(crtc);
5351 
5352         intel_crtc->active = true;
5353 
5354         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5355 
5356         if (intel_crtc->config->has_pch_encoder) {
5357                 /* Note: FDI PLL enabling _must_ be done before we enable the
5358                  * cpu pipes, hence this is separate from all the other fdi/pch
5359                  * enabling. */
5360                 ironlake_fdi_pll_enable(intel_crtc);
5361         } else {
5362                 assert_fdi_tx_disabled(dev_priv, pipe);
5363                 assert_fdi_rx_disabled(dev_priv, pipe);
5364         }
5365 
5366         ironlake_pfit_enable(intel_crtc);
5367 
5368         /*
5369          * On ILK+ LUT must be loaded before the pipe is running but with
5370          * clocks enabled
5371          */
5372         intel_color_load_luts(&pipe_config->base);
5373 
5374         if (dev_priv->display.initial_watermarks != NULL)
5375                 dev_priv->display.initial_watermarks(intel_crtc->config);
5376         intel_enable_pipe(intel_crtc);
5377 
5378         if (intel_crtc->config->has_pch_encoder)
5379                 ironlake_pch_enable(crtc);
5380 
5381         assert_vblank_disabled(crtc);
5382         drm_crtc_vblank_on(crtc);
5383 
5384         intel_encoders_enable(crtc, pipe_config, old_state);
5385 
5386         if (HAS_PCH_CPT(dev))
5387                 cpt_verify_modeset(dev, intel_crtc->pipe);
5388 
5389         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5390         if (intel_crtc->config->has_pch_encoder)
5391                 intel_wait_for_vblank(dev, pipe);
5392         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5393         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5394 }
5395 
5396 /* IPS only exists on ULT machines and is tied to pipe A. */
5397 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5398 {
5399         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5400 }
5401 
5402 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5403                                 struct drm_atomic_state *old_state)
5404 {
5405         struct drm_crtc *crtc = pipe_config->base.crtc;
5406         struct drm_device *dev = crtc->dev;
5407         struct drm_i915_private *dev_priv = to_i915(dev);
5408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5409         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5410         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5411 
5412         if (WARN_ON(intel_crtc->active))
5413                 return;
5414 
5415         if (intel_crtc->config->has_pch_encoder)
5416                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5417                                                       false);
5418 
5419         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5420 
5421         if (intel_crtc->config->shared_dpll)
5422                 intel_enable_shared_dpll(intel_crtc);
5423 
5424         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5425                 intel_dp_set_m_n(intel_crtc, M1_N1);
5426 
5427         if (!transcoder_is_dsi(cpu_transcoder))
5428                 intel_set_pipe_timings(intel_crtc);
5429 
5430         intel_set_pipe_src_size(intel_crtc);
5431 
5432         if (cpu_transcoder != TRANSCODER_EDP &&
5433             !transcoder_is_dsi(cpu_transcoder)) {
5434                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5435                            intel_crtc->config->pixel_multiplier - 1);
5436         }
5437 
5438         if (intel_crtc->config->has_pch_encoder) {
5439                 intel_cpu_transcoder_set_m_n(intel_crtc,
5440                                      &intel_crtc->config->fdi_m_n, NULL);
5441         }
5442 
5443         if (!transcoder_is_dsi(cpu_transcoder))
5444                 haswell_set_pipeconf(crtc);
5445 
5446         haswell_set_pipemisc(crtc);
5447 
5448         intel_color_set_csc(&pipe_config->base);
5449 
5450         intel_crtc->active = true;
5451 
5452         if (intel_crtc->config->has_pch_encoder)
5453                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5454         else
5455                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5456 
5457         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5458 
5459         if (intel_crtc->config->has_pch_encoder)
5460                 dev_priv->display.fdi_link_train(crtc);
5461 
5462         if (!transcoder_is_dsi(cpu_transcoder))
5463                 intel_ddi_enable_pipe_clock(intel_crtc);
5464 
5465         if (INTEL_INFO(dev)->gen >= 9)
5466                 skylake_pfit_enable(intel_crtc);
5467         else
5468                 ironlake_pfit_enable(intel_crtc);
5469 
5470         /*
5471          * On ILK+ LUT must be loaded before the pipe is running but with
5472          * clocks enabled
5473          */
5474         intel_color_load_luts(&pipe_config->base);
5475 
5476         intel_ddi_set_pipe_settings(crtc);
5477         if (!transcoder_is_dsi(cpu_transcoder))
5478                 intel_ddi_enable_transcoder_func(crtc);
5479 
5480         if (dev_priv->display.initial_watermarks != NULL)
5481                 dev_priv->display.initial_watermarks(pipe_config);
5482         else
5483                 intel_update_watermarks(crtc);
5484 
5485         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5486         if (!transcoder_is_dsi(cpu_transcoder))
5487                 intel_enable_pipe(intel_crtc);
5488 
5489         if (intel_crtc->config->has_pch_encoder)
5490                 lpt_pch_enable(crtc);
5491 
5492         if (intel_crtc->config->dp_encoder_is_mst)
5493                 intel_ddi_set_vc_payload_alloc(crtc, true);
5494 
5495         assert_vblank_disabled(crtc);
5496         drm_crtc_vblank_on(crtc);
5497 
5498         intel_encoders_enable(crtc, pipe_config, old_state);
5499 
5500         if (intel_crtc->config->has_pch_encoder) {
5501                 intel_wait_for_vblank(dev, pipe);
5502                 intel_wait_for_vblank(dev, pipe);
5503                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5504                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5505                                                       true);
5506         }
5507 
5508         /* If we change the relative order between pipe/planes enabling, we need
5509          * to change the workaround. */
5510         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5511         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5512                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5513                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5514         }
5515 }
5516 
5517 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5518 {
5519         struct drm_device *dev = crtc->base.dev;
5520         struct drm_i915_private *dev_priv = to_i915(dev);
5521         int pipe = crtc->pipe;
5522 
5523         /* To avoid upsetting the power well on haswell only disable the pfit if
5524          * it's in use. The hw state code will make sure we get this right. */
5525         if (force || crtc->config->pch_pfit.enabled) {
5526                 I915_WRITE(PF_CTL(pipe), 0);
5527                 I915_WRITE(PF_WIN_POS(pipe), 0);
5528                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5529         }
5530 }
5531 
5532 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5533                                   struct drm_atomic_state *old_state)
5534 {
5535         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5536         struct drm_device *dev = crtc->dev;
5537         struct drm_i915_private *dev_priv = to_i915(dev);
5538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5539         int pipe = intel_crtc->pipe;
5540 
5541         /*
5542          * Sometimes spurious CPU pipe underruns happen when the
5543          * pipe is already disabled, but FDI RX/TX is still enabled.
5544          * Happens at least with VGA+HDMI cloning. Suppress them.
5545          */
5546         if (intel_crtc->config->has_pch_encoder) {
5547                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5548                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5549         }
5550 
5551         intel_encoders_disable(crtc, old_crtc_state, old_state);
5552 
5553         drm_crtc_vblank_off(crtc);
5554         assert_vblank_disabled(crtc);
5555 
5556         intel_disable_pipe(intel_crtc);
5557 
5558         ironlake_pfit_disable(intel_crtc, false);
5559 
5560         if (intel_crtc->config->has_pch_encoder)
5561                 ironlake_fdi_disable(crtc);
5562 
5563         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5564 
5565         if (intel_crtc->config->has_pch_encoder) {
5566                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5567 
5568                 if (HAS_PCH_CPT(dev)) {
5569                         i915_reg_t reg;
5570                         u32 temp;
5571 
5572                         /* disable TRANS_DP_CTL */
5573                         reg = TRANS_DP_CTL(pipe);
5574                         temp = I915_READ(reg);
5575                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5576                                   TRANS_DP_PORT_SEL_MASK);
5577                         temp |= TRANS_DP_PORT_SEL_NONE;
5578                         I915_WRITE(reg, temp);
5579 
5580                         /* disable DPLL_SEL */
5581                         temp = I915_READ(PCH_DPLL_SEL);
5582                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5583                         I915_WRITE(PCH_DPLL_SEL, temp);
5584                 }
5585 
5586                 ironlake_fdi_pll_disable(intel_crtc);
5587         }
5588 
5589         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5590         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5591 }
5592 
5593 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5594                                  struct drm_atomic_state *old_state)
5595 {
5596         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5597         struct drm_device *dev = crtc->dev;
5598         struct drm_i915_private *dev_priv = to_i915(dev);
5599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5601 
5602         if (intel_crtc->config->has_pch_encoder)
5603                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5604                                                       false);
5605 
5606         intel_encoders_disable(crtc, old_crtc_state, old_state);
5607 
5608         drm_crtc_vblank_off(crtc);
5609         assert_vblank_disabled(crtc);
5610 
5611         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5612         if (!transcoder_is_dsi(cpu_transcoder))
5613                 intel_disable_pipe(intel_crtc);
5614 
5615         if (intel_crtc->config->dp_encoder_is_mst)
5616                 intel_ddi_set_vc_payload_alloc(crtc, false);
5617 
5618         if (!transcoder_is_dsi(cpu_transcoder))
5619                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5620 
5621         if (INTEL_INFO(dev)->gen >= 9)
5622                 skylake_scaler_disable(intel_crtc);
5623         else
5624                 ironlake_pfit_disable(intel_crtc, false);
5625 
5626         if (!transcoder_is_dsi(cpu_transcoder))
5627                 intel_ddi_disable_pipe_clock(intel_crtc);
5628 
5629         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5630 
5631         if (old_crtc_state->has_pch_encoder)
5632                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5633                                                       true);
5634 }
5635 
5636 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5637 {
5638         struct drm_device *dev = crtc->base.dev;
5639         struct drm_i915_private *dev_priv = to_i915(dev);
5640         struct intel_crtc_state *pipe_config = crtc->config;
5641 
5642         if (!pipe_config->gmch_pfit.control)
5643                 return;
5644 
5645         /*
5646          * The panel fitter should only be adjusted whilst the pipe is disabled,
5647          * according to register description and PRM.
5648          */
5649         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5650         assert_pipe_disabled(dev_priv, crtc->pipe);
5651 
5652         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5653         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5654 
5655         /* Border color in case we don't scale up to the full screen. Black by
5656          * default, change to something else for debugging. */
5657         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5658 }
5659 
5660 static enum intel_display_power_domain port_to_power_domain(enum port port)
5661 {
5662         switch (port) {
5663         case PORT_A:
5664                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5665         case PORT_B:
5666                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5667         case PORT_C:
5668                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5669         case PORT_D:
5670                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5671         case PORT_E:
5672                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5673         default:
5674                 MISSING_CASE(port);
5675                 return POWER_DOMAIN_PORT_OTHER;
5676         }
5677 }
5678 
5679 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5680 {
5681         switch (port) {
5682         case PORT_A:
5683                 return POWER_DOMAIN_AUX_A;
5684         case PORT_B:
5685                 return POWER_DOMAIN_AUX_B;
5686         case PORT_C:
5687                 return POWER_DOMAIN_AUX_C;
5688         case PORT_D:
5689                 return POWER_DOMAIN_AUX_D;
5690         case PORT_E:
5691                 /* FIXME: Check VBT for actual wiring of PORT E */
5692                 return POWER_DOMAIN_AUX_D;
5693         default:
5694                 MISSING_CASE(port);
5695                 return POWER_DOMAIN_AUX_A;
5696         }
5697 }
5698 
5699 enum intel_display_power_domain
5700 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5701 {
5702         struct drm_device *dev = intel_encoder->base.dev;
5703         struct intel_digital_port *intel_dig_port;
5704 
5705         switch (intel_encoder->type) {
5706         case INTEL_OUTPUT_UNKNOWN:
5707                 /* Only DDI platforms should ever use this output type */
5708                 WARN_ON_ONCE(!HAS_DDI(dev));
5709         case INTEL_OUTPUT_DP:
5710         case INTEL_OUTPUT_HDMI:
5711         case INTEL_OUTPUT_EDP:
5712                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5713                 return port_to_power_domain(intel_dig_port->port);
5714         case INTEL_OUTPUT_DP_MST:
5715                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5716                 return port_to_power_domain(intel_dig_port->port);
5717         case INTEL_OUTPUT_ANALOG:
5718                 return POWER_DOMAIN_PORT_CRT;
5719         case INTEL_OUTPUT_DSI:
5720                 return POWER_DOMAIN_PORT_DSI;
5721         default:
5722                 return POWER_DOMAIN_PORT_OTHER;
5723         }
5724 }
5725 
5726 enum intel_display_power_domain
5727 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5728 {
5729         struct drm_device *dev = intel_encoder->base.dev;
5730         struct intel_digital_port *intel_dig_port;
5731 
5732         switch (intel_encoder->type) {
5733         case INTEL_OUTPUT_UNKNOWN:
5734         case INTEL_OUTPUT_HDMI:
5735                 /*
5736                  * Only DDI platforms should ever use these output types.
5737                  * We can get here after the HDMI detect code has already set
5738                  * the type of the shared encoder. Since we can't be sure
5739                  * what's the status of the given connectors, play safe and
5740                  * run the DP detection too.
5741                  */
5742                 WARN_ON_ONCE(!HAS_DDI(dev));
5743         case INTEL_OUTPUT_DP:
5744         case INTEL_OUTPUT_EDP:
5745                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5746                 return port_to_aux_power_domain(intel_dig_port->port);
5747         case INTEL_OUTPUT_DP_MST:
5748                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5749                 return port_to_aux_power_domain(intel_dig_port->port);
5750         default:
5751                 MISSING_CASE(intel_encoder->type);
5752                 return POWER_DOMAIN_AUX_A;
5753         }
5754 }
5755 
5756 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5757                                             struct intel_crtc_state *crtc_state)
5758 {
5759         struct drm_device *dev = crtc->dev;
5760         struct drm_encoder *encoder;
5761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5762         enum pipe pipe = intel_crtc->pipe;
5763         unsigned long mask;
5764         enum transcoder transcoder = crtc_state->cpu_transcoder;
5765 
5766         if (!crtc_state->base.active)
5767                 return 0;
5768 
5769         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5770         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5771         if (crtc_state->pch_pfit.enabled ||
5772             crtc_state->pch_pfit.force_thru)
5773                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5774 
5775         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5776                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5777 
5778                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5779         }
5780 
5781         if (crtc_state->shared_dpll)
5782                 mask |= BIT(POWER_DOMAIN_PLLS);
5783 
5784         return mask;
5785 }
5786 
5787 static unsigned long
5788 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5789                                struct intel_crtc_state *crtc_state)
5790 {
5791         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5793         enum intel_display_power_domain domain;
5794         unsigned long domains, new_domains, old_domains;
5795 
5796         old_domains = intel_crtc->enabled_power_domains;
5797         intel_crtc->enabled_power_domains = new_domains =
5798                 get_crtc_power_domains(crtc, crtc_state);
5799 
5800         domains = new_domains & ~old_domains;
5801 
5802         for_each_power_domain(domain, domains)
5803                 intel_display_power_get(dev_priv, domain);
5804 
5805         return old_domains & ~new_domains;
5806 }
5807 
5808 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5809                                       unsigned long domains)
5810 {
5811         enum intel_display_power_domain domain;
5812 
5813         for_each_power_domain(domain, domains)
5814                 intel_display_power_put(dev_priv, domain);
5815 }
5816 
5817 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5818 {
5819         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5820 
5821         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5822             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5823                 return max_cdclk_freq;
5824         else if (IS_CHERRYVIEW(dev_priv))
5825                 return max_cdclk_freq*95/100;
5826         else if (INTEL_INFO(dev_priv)->gen < 4)
5827                 return 2*max_cdclk_freq*90/100;
5828         else
5829                 return max_cdclk_freq*90/100;
5830 }
5831 
5832 static int skl_calc_cdclk(int max_pixclk, int vco);
5833 
5834 static void intel_update_max_cdclk(struct drm_device *dev)
5835 {
5836         struct drm_i915_private *dev_priv = to_i915(dev);
5837 
5838         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5839                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5840                 int max_cdclk, vco;
5841 
5842                 vco = dev_priv->skl_preferred_vco_freq;
5843                 WARN_ON(vco != 8100000 && vco != 8640000);
5844 
5845                 /*
5846                  * Use the lower (vco 8640) cdclk values as a
5847                  * first guess. skl_calc_cdclk() will correct it
5848                  * if the preferred vco is 8100 instead.
5849                  */
5850                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5851                         max_cdclk = 617143;
5852                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5853                         max_cdclk = 540000;
5854                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5855                         max_cdclk = 432000;
5856                 else
5857                         max_cdclk = 308571;
5858 
5859                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5860         } else if (IS_BROXTON(dev)) {
5861                 dev_priv->max_cdclk_freq = 624000;
5862         } else if (IS_BROADWELL(dev))  {
5863                 /*
5864                  * FIXME with extra cooling we can allow
5865                  * 540 MHz for ULX and 675 Mhz for ULT.
5866                  * How can we know if extra cooling is
5867                  * available? PCI ID, VTB, something else?
5868                  */
5869                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5870                         dev_priv->max_cdclk_freq = 450000;
5871                 else if (IS_BDW_ULX(dev))
5872                         dev_priv->max_cdclk_freq = 450000;
5873                 else if (IS_BDW_ULT(dev))
5874                         dev_priv->max_cdclk_freq = 540000;
5875                 else
5876                         dev_priv->max_cdclk_freq = 675000;
5877         } else if (IS_CHERRYVIEW(dev)) {
5878                 dev_priv->max_cdclk_freq = 320000;
5879         } else if (IS_VALLEYVIEW(dev)) {
5880                 dev_priv->max_cdclk_freq = 400000;
5881         } else {
5882                 /* otherwise assume cdclk is fixed */
5883                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5884         }
5885 
5886         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5887 
5888         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5889                          dev_priv->max_cdclk_freq);
5890 
5891         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5892                          dev_priv->max_dotclk_freq);
5893 }
5894 
5895 static void intel_update_cdclk(struct drm_device *dev)
5896 {
5897         struct drm_i915_private *dev_priv = to_i915(dev);
5898 
5899         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5900 
5901         if (INTEL_GEN(dev_priv) >= 9)
5902                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5903                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5904                                  dev_priv->cdclk_pll.ref);
5905         else
5906                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5907                                  dev_priv->cdclk_freq);
5908 
5909         /*
5910          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5911          * Programmng [sic] note: bit[9:2] should be programmed to the number
5912          * of cdclk that generates 4MHz reference clock freq which is used to
5913          * generate GMBus clock. This will vary with the cdclk freq.
5914          */
5915         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5916                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5917 }
5918 
5919 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5920 static int skl_cdclk_decimal(int cdclk)
5921 {
5922         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5923 }
5924 
5925 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5926 {
5927         int ratio;
5928 
5929         if (cdclk == dev_priv->cdclk_pll.ref)
5930                 return 0;
5931 
5932         switch (cdclk) {
5933         default:
5934                 MISSING_CASE(cdclk);
5935         case 144000:
5936         case 288000:
5937         case 384000:
5938         case 576000:
5939                 ratio = 60;
5940                 break;
5941         case 624000:
5942                 ratio = 65;
5943                 break;
5944         }
5945 
5946         return dev_priv->cdclk_pll.ref * ratio;
5947 }
5948 
5949 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5950 {
5951         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5952 
5953         /* Timeout 200us */
5954         if (intel_wait_for_register(dev_priv,
5955                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5956                                     1))
5957                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5958 
5959         dev_priv->cdclk_pll.vco = 0;
5960 }
5961 
5962 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5963 {
5964         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5965         u32 val;
5966 
5967         val = I915_READ(BXT_DE_PLL_CTL);
5968         val &= ~BXT_DE_PLL_RATIO_MASK;
5969         val |= BXT_DE_PLL_RATIO(ratio);
5970         I915_WRITE(BXT_DE_PLL_CTL, val);
5971 
5972         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5973 
5974         /* Timeout 200us */
5975         if (intel_wait_for_register(dev_priv,
5976                                     BXT_DE_PLL_ENABLE,
5977                                     BXT_DE_PLL_LOCK,
5978                                     BXT_DE_PLL_LOCK,
5979                                     1))
5980                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5981 
5982         dev_priv->cdclk_pll.vco = vco;
5983 }
5984 
5985 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5986 {
5987         u32 val, divider;
5988         int vco, ret;
5989 
5990         vco = bxt_de_pll_vco(dev_priv, cdclk);
5991 
5992         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5993 
5994         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5995         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5996         case 8:
5997                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5998                 break;
5999         case 4:
6000                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6001                 break;
6002         case 3:
6003                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6004                 break;
6005         case 2:
6006                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6007                 break;
6008         default:
6009                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6010                 WARN_ON(vco != 0);
6011 
6012                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6013                 break;
6014         }
6015 
6016         /* Inform power controller of upcoming frequency change */
6017         mutex_lock(&dev_priv->rps.hw_lock);
6018         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6019                                       0x80000000);
6020         mutex_unlock(&dev_priv->rps.hw_lock);
6021 
6022         if (ret) {
6023                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6024                           ret, cdclk);
6025                 return;
6026         }
6027 
6028         if (dev_priv->cdclk_pll.vco != 0 &&
6029             dev_priv->cdclk_pll.vco != vco)
6030                 bxt_de_pll_disable(dev_priv);
6031 
6032         if (dev_priv->cdclk_pll.vco != vco)
6033                 bxt_de_pll_enable(dev_priv, vco);
6034 
6035         val = divider | skl_cdclk_decimal(cdclk);
6036         /*
6037          * FIXME if only the cd2x divider needs changing, it could be done
6038          * without shutting off the pipe (if only one pipe is active).
6039          */
6040         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6041         /*
6042          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6043          * enable otherwise.
6044          */
6045         if (cdclk >= 500000)
6046                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6047         I915_WRITE(CDCLK_CTL, val);
6048 
6049         mutex_lock(&dev_priv->rps.hw_lock);
6050         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6051                                       DIV_ROUND_UP(cdclk, 25000));
6052         mutex_unlock(&dev_priv->rps.hw_lock);
6053 
6054         if (ret) {
6055                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6056                           ret, cdclk);
6057                 return;
6058         }
6059 
6060         intel_update_cdclk(&dev_priv->drm);
6061 }
6062 
6063 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6064 {
6065         u32 cdctl, expected;
6066 
6067         intel_update_cdclk(&dev_priv->drm);
6068 
6069         if (dev_priv->cdclk_pll.vco == 0 ||
6070             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6071                 goto sanitize;
6072 
6073         /* DPLL okay; verify the cdclock
6074          *
6075          * Some BIOS versions leave an incorrect decimal frequency value and
6076          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6077          * so sanitize this register.
6078          */
6079         cdctl = I915_READ(CDCLK_CTL);
6080         /*
6081          * Let's ignore the pipe field, since BIOS could have configured the
6082          * dividers both synching to an active pipe, or asynchronously
6083          * (PIPE_NONE).
6084          */
6085         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6086 
6087         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6088                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6089         /*
6090          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6091          * enable otherwise.
6092          */
6093         if (dev_priv->cdclk_freq >= 500000)
6094                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6095 
6096         if (cdctl == expected)
6097                 /* All well; nothing to sanitize */
6098                 return;
6099 
6100 sanitize:
6101         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6102 
6103         /* force cdclk programming */
6104         dev_priv->cdclk_freq = 0;
6105 
6106         /* force full PLL disable + enable */
6107         dev_priv->cdclk_pll.vco = -1;
6108 }
6109 
6110 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6111 {
6112         bxt_sanitize_cdclk(dev_priv);
6113 
6114         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6115                 return;
6116 
6117         /*
6118          * FIXME:
6119          * - The initial CDCLK needs to be read from VBT.
6120          *   Need to make this change after VBT has changes for BXT.
6121          */
6122         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6123 }
6124 
6125 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6126 {
6127         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6128 }
6129 
6130 static int skl_calc_cdclk(int max_pixclk, int vco)
6131 {
6132         if (vco == 8640000) {
6133                 if (max_pixclk > 540000)
6134                         return 617143;
6135                 else if (max_pixclk > 432000)
6136                         return 540000;
6137                 else if (max_pixclk > 308571)
6138                         return 432000;
6139                 else
6140                         return 308571;
6141         } else {
6142                 if (max_pixclk > 540000)
6143                         return 675000;
6144                 else if (max_pixclk > 450000)
6145                         return 540000;
6146                 else if (max_pixclk > 337500)
6147                         return 450000;
6148                 else
6149                         return 337500;
6150         }
6151 }
6152 
6153 static void
6154 skl_dpll0_update(struct drm_i915_private *dev_priv)
6155 {
6156         u32 val;
6157 
6158         dev_priv->cdclk_pll.ref = 24000;
6159         dev_priv->cdclk_pll.vco = 0;
6160 
6161         val = I915_READ(LCPLL1_CTL);
6162         if ((val & LCPLL_PLL_ENABLE) == 0)
6163                 return;
6164 
6165         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6166                 return;
6167 
6168         val = I915_READ(DPLL_CTRL1);
6169 
6170         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6171                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6172                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6173                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6174                 return;
6175 
6176         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6177         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6178         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6179         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6180         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6181                 dev_priv->cdclk_pll.vco = 8100000;
6182                 break;
6183         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6184         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6185                 dev_priv->cdclk_pll.vco = 8640000;
6186                 break;
6187         default:
6188                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6189                 break;
6190         }
6191 }
6192 
6193 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6194 {
6195         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6196 
6197         dev_priv->skl_preferred_vco_freq = vco;
6198 
6199         if (changed)
6200                 intel_update_max_cdclk(&dev_priv->drm);
6201 }
6202 
6203 static void
6204 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6205 {
6206         int min_cdclk = skl_calc_cdclk(0, vco);
6207         u32 val;
6208 
6209         WARN_ON(vco != 8100000 && vco != 8640000);
6210 
6211         /* select the minimum CDCLK before enabling DPLL 0 */
6212         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6213         I915_WRITE(CDCLK_CTL, val);
6214         POSTING_READ(CDCLK_CTL);
6215 
6216         /*
6217          * We always enable DPLL0 with the lowest link rate possible, but still
6218          * taking into account the VCO required to operate the eDP panel at the
6219          * desired frequency. The usual DP link rates operate with a VCO of
6220          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6221          * The modeset code is responsible for the selection of the exact link
6222          * rate later on, with the constraint of choosing a frequency that
6223          * works with vco.
6224          */
6225         val = I915_READ(DPLL_CTRL1);
6226 
6227         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6228                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6229         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6230         if (vco == 8640000)
6231                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6232                                             SKL_DPLL0);
6233         else
6234                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6235                                             SKL_DPLL0);
6236 
6237         I915_WRITE(DPLL_CTRL1, val);
6238         POSTING_READ(DPLL_CTRL1);
6239 
6240         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6241 
6242         if (intel_wait_for_register(dev_priv,
6243                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6244                                     5))
6245                 DRM_ERROR("DPLL0 not locked\n");
6246 
6247         dev_priv->cdclk_pll.vco = vco;
6248 
6249         /* We'll want to keep using the current vco from now on. */
6250         skl_set_preferred_cdclk_vco(dev_priv, vco);
6251 }
6252 
6253 static void
6254 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6255 {
6256         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6257         if (intel_wait_for_register(dev_priv,
6258                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6259                                    1))
6260                 DRM_ERROR("Couldn't disable DPLL0\n");
6261 
6262         dev_priv->cdclk_pll.vco = 0;
6263 }
6264 
6265 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6266 {
6267         int ret;
6268         u32 val;
6269 
6270         /* inform PCU we want to change CDCLK */
6271         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6272         mutex_lock(&dev_priv->rps.hw_lock);
6273         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6274         mutex_unlock(&dev_priv->rps.hw_lock);
6275 
6276         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6277 }
6278 
6279 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6280 {
6281         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6282 }
6283 
6284 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6285 {
6286         struct drm_device *dev = &dev_priv->drm;
6287         u32 freq_select, pcu_ack;
6288 
6289         WARN_ON((cdclk == 24000) != (vco == 0));
6290 
6291         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6292 
6293         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6294                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6295                 return;
6296         }
6297 
6298         /* set CDCLK_CTL */
6299         switch (cdclk) {
6300         case 450000:
6301         case 432000:
6302                 freq_select = CDCLK_FREQ_450_432;
6303                 pcu_ack = 1;
6304                 break;
6305         case 540000:
6306                 freq_select = CDCLK_FREQ_540;
6307                 pcu_ack = 2;
6308                 break;
6309         case 308571:
6310         case 337500:
6311         default:
6312                 freq_select = CDCLK_FREQ_337_308;
6313                 pcu_ack = 0;
6314                 break;
6315         case 617143:
6316         case 675000:
6317                 freq_select = CDCLK_FREQ_675_617;
6318                 pcu_ack = 3;
6319                 break;
6320         }
6321 
6322         if (dev_priv->cdclk_pll.vco != 0 &&
6323             dev_priv->cdclk_pll.vco != vco)
6324                 skl_dpll0_disable(dev_priv);
6325 
6326         if (dev_priv->cdclk_pll.vco != vco)
6327                 skl_dpll0_enable(dev_priv, vco);
6328 
6329         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6330         POSTING_READ(CDCLK_CTL);
6331 
6332         /* inform PCU of the change */
6333         mutex_lock(&dev_priv->rps.hw_lock);
6334         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6335         mutex_unlock(&dev_priv->rps.hw_lock);
6336 
6337         intel_update_cdclk(dev);
6338 }
6339 
6340 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6341 
6342 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6343 {
6344         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6345 }
6346 
6347 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6348 {
6349         int cdclk, vco;
6350 
6351         skl_sanitize_cdclk(dev_priv);
6352 
6353         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6354                 /*
6355                  * Use the current vco as our initial
6356                  * guess as to what the preferred vco is.
6357                  */
6358                 if (dev_priv->skl_preferred_vco_freq == 0)
6359                         skl_set_preferred_cdclk_vco(dev_priv,
6360                                                     dev_priv->cdclk_pll.vco);
6361                 return;
6362         }
6363 
6364         vco = dev_priv->skl_preferred_vco_freq;
6365         if (vco == 0)
6366                 vco = 8100000;
6367         cdclk = skl_calc_cdclk(0, vco);
6368 
6369         skl_set_cdclk(dev_priv, cdclk, vco);
6370 }
6371 
6372 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6373 {
6374         uint32_t cdctl, expected;
6375 
6376         /*
6377          * check if the pre-os intialized the display
6378          * There is SWF18 scratchpad register defined which is set by the
6379          * pre-os which can be used by the OS drivers to check the status
6380          */
6381         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6382                 goto sanitize;
6383 
6384         intel_update_cdclk(&dev_priv->drm);
6385         /* Is PLL enabled and locked ? */
6386         if (dev_priv->cdclk_pll.vco == 0 ||
6387             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6388                 goto sanitize;
6389 
6390         /* DPLL okay; verify the cdclock
6391          *
6392          * Noticed in some instances that the freq selection is correct but
6393          * decimal part is programmed wrong from BIOS where pre-os does not
6394          * enable display. Verify the same as well.
6395          */
6396         cdctl = I915_READ(CDCLK_CTL);
6397         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6398                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6399         if (cdctl == expected)
6400                 /* All well; nothing to sanitize */
6401                 return;
6402 
6403 sanitize:
6404         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6405 
6406         /* force cdclk programming */
6407         dev_priv->cdclk_freq = 0;
6408         /* force full PLL disable + enable */
6409         dev_priv->cdclk_pll.vco = -1;
6410 }
6411 
6412 /* Adjust CDclk dividers to allow high res or save power if possible */
6413 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6414 {
6415         struct drm_i915_private *dev_priv = to_i915(dev);
6416         u32 val, cmd;
6417 
6418         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6419                                         != dev_priv->cdclk_freq);
6420 
6421         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6422                 cmd = 2;
6423         else if (cdclk == 266667)
6424                 cmd = 1;
6425         else
6426                 cmd = 0;
6427 
6428         mutex_lock(&dev_priv->rps.hw_lock);
6429         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6430         val &= ~DSPFREQGUAR_MASK;
6431         val |= (cmd << DSPFREQGUAR_SHIFT);
6432         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6433         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6434                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6435                      50)) {
6436                 DRM_ERROR("timed out waiting for CDclk change\n");
6437         }
6438         mutex_unlock(&dev_priv->rps.hw_lock);
6439 
6440         mutex_lock(&dev_priv->sb_lock);
6441 
6442         if (cdclk == 400000) {
6443                 u32 divider;
6444 
6445                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6446 
6447                 /* adjust cdclk divider */
6448                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6449                 val &= ~CCK_FREQUENCY_VALUES;
6450                 val |= divider;
6451                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6452 
6453                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6454                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6455                              50))
6456                         DRM_ERROR("timed out waiting for CDclk change\n");
6457         }
6458 
6459         /* adjust self-refresh exit latency value */
6460         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6461         val &= ~0x7f;
6462 
6463         /*
6464          * For high bandwidth configs, we set a higher latency in the bunit
6465          * so that the core display fetch happens in time to avoid underruns.
6466          */
6467         if (cdclk == 400000)
6468                 val |= 4500 / 250; /* 4.5 usec */
6469         else
6470                 val |= 3000 / 250; /* 3.0 usec */