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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "intel_dsi.h"
 40 #include "i915_trace.h"
 41 #include <drm/drm_atomic.h>
 42 #include <drm/drm_atomic_helper.h>
 43 #include <drm/drm_dp_helper.h>
 44 #include <drm/drm_crtc_helper.h>
 45 #include <drm/drm_plane_helper.h>
 46 #include <drm/drm_rect.h>
 47 #include <linux/dma_remapping.h>
 48 #include <linux/reservation.h>
 49 #include <linux/dma-buf.h>
 50 
 51 /* Primary plane formats for gen <= 3 */
 52 static const uint32_t i8xx_primary_formats[] = {
 53         DRM_FORMAT_C8,
 54         DRM_FORMAT_RGB565,
 55         DRM_FORMAT_XRGB1555,
 56         DRM_FORMAT_XRGB8888,
 57 };
 58 
 59 /* Primary plane formats for gen >= 4 */
 60 static const uint32_t i965_primary_formats[] = {
 61         DRM_FORMAT_C8,
 62         DRM_FORMAT_RGB565,
 63         DRM_FORMAT_XRGB8888,
 64         DRM_FORMAT_XBGR8888,
 65         DRM_FORMAT_XRGB2101010,
 66         DRM_FORMAT_XBGR2101010,
 67 };
 68 
 69 static const uint32_t skl_primary_formats[] = {
 70         DRM_FORMAT_C8,
 71         DRM_FORMAT_RGB565,
 72         DRM_FORMAT_XRGB8888,
 73         DRM_FORMAT_XBGR8888,
 74         DRM_FORMAT_ARGB8888,
 75         DRM_FORMAT_ABGR8888,
 76         DRM_FORMAT_XRGB2101010,
 77         DRM_FORMAT_XBGR2101010,
 78         DRM_FORMAT_YUYV,
 79         DRM_FORMAT_YVYU,
 80         DRM_FORMAT_UYVY,
 81         DRM_FORMAT_VYUY,
 82 };
 83 
 84 /* Cursor formats */
 85 static const uint32_t intel_cursor_formats[] = {
 86         DRM_FORMAT_ARGB8888,
 87 };
 88 
 89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 90                                 struct intel_crtc_state *pipe_config);
 91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 92                                    struct intel_crtc_state *pipe_config);
 93 
 94 static int intel_framebuffer_init(struct drm_device *dev,
 95                                   struct intel_framebuffer *ifb,
 96                                   struct drm_mode_fb_cmd2 *mode_cmd,
 97                                   struct drm_i915_gem_object *obj);
 98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102                                          struct intel_link_m_n *m_n,
103                                          struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108                             const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110                             const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114         struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120 
121 typedef struct {
122         int     min, max;
123 } intel_range_t;
124 
125 typedef struct {
126         int     dot_limit;
127         int     p2_slow, p2_fast;
128 } intel_p2_t;
129 
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
133         intel_p2_t          p2;
134 };
135 
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140 
141         /* Obtain SKU information */
142         mutex_lock(&dev_priv->sb_lock);
143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144                 CCK_FUSE_HPLL_FREQ_MASK;
145         mutex_unlock(&dev_priv->sb_lock);
146 
147         return vco_freq[hpll_freq] * 1000;
148 }
149 
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151                       const char *name, u32 reg, int ref_freq)
152 {
153         u32 val;
154         int divider;
155 
156         mutex_lock(&dev_priv->sb_lock);
157         val = vlv_cck_read(dev_priv, reg);
158         mutex_unlock(&dev_priv->sb_lock);
159 
160         divider = val & CCK_FREQUENCY_VALUES;
161 
162         WARN((val & CCK_FREQUENCY_STATUS) !=
163              (divider << CCK_FREQUENCY_STATUS_SHIFT),
164              "%s change in progress\n", name);
165 
166         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168 
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170                                   const char *name, u32 reg)
171 {
172         if (dev_priv->hpll_freq == 0)
173                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
174 
175         return vlv_get_cck_clock(dev_priv, name, reg,
176                                  dev_priv->hpll_freq);
177 }
178 
179 static int
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
181 {
182         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
183 }
184 
185 static int
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
187 {
188         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
189                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
190 }
191 
192 static int
193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
194 {
195         uint32_t clkcfg;
196 
197         /* hrawclock is 1/4 the FSB frequency */
198         clkcfg = I915_READ(CLKCFG);
199         switch (clkcfg & CLKCFG_FSB_MASK) {
200         case CLKCFG_FSB_400:
201                 return 100000;
202         case CLKCFG_FSB_533:
203                 return 133333;
204         case CLKCFG_FSB_667:
205                 return 166667;
206         case CLKCFG_FSB_800:
207                 return 200000;
208         case CLKCFG_FSB_1067:
209                 return 266667;
210         case CLKCFG_FSB_1333:
211                 return 333333;
212         /* these two are just a guess; one of them might be right */
213         case CLKCFG_FSB_1600:
214         case CLKCFG_FSB_1600_ALT:
215                 return 400000;
216         default:
217                 return 133333;
218         }
219 }
220 
221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
222 {
223         if (HAS_PCH_SPLIT(dev_priv))
224                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
225         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
226                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
227         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
228                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
229         else
230                 return; /* no rawclk on other platforms, or no need to know it */
231 
232         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
233 }
234 
235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
236 {
237         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
238                 return;
239 
240         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
241                                                       CCK_CZ_CLOCK_CONTROL);
242 
243         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
244 }
245 
246 static inline u32 /* units of 100MHz */
247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
248                     const struct intel_crtc_state *pipe_config)
249 {
250         if (HAS_DDI(dev_priv))
251                 return pipe_config->port_clock; /* SPLL */
252         else if (IS_GEN5(dev_priv))
253                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
254         else
255                 return 270000;
256 }
257 
258 static const intel_limit_t intel_limits_i8xx_dac = {
259         .dot = { .min = 25000, .max = 350000 },
260         .vco = { .min = 908000, .max = 1512000 },
261         .n = { .min = 2, .max = 16 },
262         .m = { .min = 96, .max = 140 },
263         .m1 = { .min = 18, .max = 26 },
264         .m2 = { .min = 6, .max = 16 },
265         .p = { .min = 4, .max = 128 },
266         .p1 = { .min = 2, .max = 33 },
267         .p2 = { .dot_limit = 165000,
268                 .p2_slow = 4, .p2_fast = 2 },
269 };
270 
271 static const intel_limit_t intel_limits_i8xx_dvo = {
272         .dot = { .min = 25000, .max = 350000 },
273         .vco = { .min = 908000, .max = 1512000 },
274         .n = { .min = 2, .max = 16 },
275         .m = { .min = 96, .max = 140 },
276         .m1 = { .min = 18, .max = 26 },
277         .m2 = { .min = 6, .max = 16 },
278         .p = { .min = 4, .max = 128 },
279         .p1 = { .min = 2, .max = 33 },
280         .p2 = { .dot_limit = 165000,
281                 .p2_slow = 4, .p2_fast = 4 },
282 };
283 
284 static const intel_limit_t intel_limits_i8xx_lvds = {
285         .dot = { .min = 25000, .max = 350000 },
286         .vco = { .min = 908000, .max = 1512000 },
287         .n = { .min = 2, .max = 16 },
288         .m = { .min = 96, .max = 140 },
289         .m1 = { .min = 18, .max = 26 },
290         .m2 = { .min = 6, .max = 16 },
291         .p = { .min = 4, .max = 128 },
292         .p1 = { .min = 1, .max = 6 },
293         .p2 = { .dot_limit = 165000,
294                 .p2_slow = 14, .p2_fast = 7 },
295 };
296 
297 static const intel_limit_t intel_limits_i9xx_sdvo = {
298         .dot = { .min = 20000, .max = 400000 },
299         .vco = { .min = 1400000, .max = 2800000 },
300         .n = { .min = 1, .max = 6 },
301         .m = { .min = 70, .max = 120 },
302         .m1 = { .min = 8, .max = 18 },
303         .m2 = { .min = 3, .max = 7 },
304         .p = { .min = 5, .max = 80 },
305         .p1 = { .min = 1, .max = 8 },
306         .p2 = { .dot_limit = 200000,
307                 .p2_slow = 10, .p2_fast = 5 },
308 };
309 
310 static const intel_limit_t intel_limits_i9xx_lvds = {
311         .dot = { .min = 20000, .max = 400000 },
312         .vco = { .min = 1400000, .max = 2800000 },
313         .n = { .min = 1, .max = 6 },
314         .m = { .min = 70, .max = 120 },
315         .m1 = { .min = 8, .max = 18 },
316         .m2 = { .min = 3, .max = 7 },
317         .p = { .min = 7, .max = 98 },
318         .p1 = { .min = 1, .max = 8 },
319         .p2 = { .dot_limit = 112000,
320                 .p2_slow = 14, .p2_fast = 7 },
321 };
322 
323 
324 static const intel_limit_t intel_limits_g4x_sdvo = {
325         .dot = { .min = 25000, .max = 270000 },
326         .vco = { .min = 1750000, .max = 3500000},
327         .n = { .min = 1, .max = 4 },
328         .m = { .min = 104, .max = 138 },
329         .m1 = { .min = 17, .max = 23 },
330         .m2 = { .min = 5, .max = 11 },
331         .p = { .min = 10, .max = 30 },
332         .p1 = { .min = 1, .max = 3},
333         .p2 = { .dot_limit = 270000,
334                 .p2_slow = 10,
335                 .p2_fast = 10
336         },
337 };
338 
339 static const intel_limit_t intel_limits_g4x_hdmi = {
340         .dot = { .min = 22000, .max = 400000 },
341         .vco = { .min = 1750000, .max = 3500000},
342         .n = { .min = 1, .max = 4 },
343         .m = { .min = 104, .max = 138 },
344         .m1 = { .min = 16, .max = 23 },
345         .m2 = { .min = 5, .max = 11 },
346         .p = { .min = 5, .max = 80 },
347         .p1 = { .min = 1, .max = 8},
348         .p2 = { .dot_limit = 165000,
349                 .p2_slow = 10, .p2_fast = 5 },
350 };
351 
352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
353         .dot = { .min = 20000, .max = 115000 },
354         .vco = { .min = 1750000, .max = 3500000 },
355         .n = { .min = 1, .max = 3 },
356         .m = { .min = 104, .max = 138 },
357         .m1 = { .min = 17, .max = 23 },
358         .m2 = { .min = 5, .max = 11 },
359         .p = { .min = 28, .max = 112 },
360         .p1 = { .min = 2, .max = 8 },
361         .p2 = { .dot_limit = 0,
362                 .p2_slow = 14, .p2_fast = 14
363         },
364 };
365 
366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
367         .dot = { .min = 80000, .max = 224000 },
368         .vco = { .min = 1750000, .max = 3500000 },
369         .n = { .min = 1, .max = 3 },
370         .m = { .min = 104, .max = 138 },
371         .m1 = { .min = 17, .max = 23 },
372         .m2 = { .min = 5, .max = 11 },
373         .p = { .min = 14, .max = 42 },
374         .p1 = { .min = 2, .max = 6 },
375         .p2 = { .dot_limit = 0,
376                 .p2_slow = 7, .p2_fast = 7
377         },
378 };
379 
380 static const intel_limit_t intel_limits_pineview_sdvo = {
381         .dot = { .min = 20000, .max = 400000},
382         .vco = { .min = 1700000, .max = 3500000 },
383         /* Pineview's Ncounter is a ring counter */
384         .n = { .min = 3, .max = 6 },
385         .m = { .min = 2, .max = 256 },
386         /* Pineview only has one combined m divider, which we treat as m2. */
387         .m1 = { .min = 0, .max = 0 },
388         .m2 = { .min = 0, .max = 254 },
389         .p = { .min = 5, .max = 80 },
390         .p1 = { .min = 1, .max = 8 },
391         .p2 = { .dot_limit = 200000,
392                 .p2_slow = 10, .p2_fast = 5 },
393 };
394 
395 static const intel_limit_t intel_limits_pineview_lvds = {
396         .dot = { .min = 20000, .max = 400000 },
397         .vco = { .min = 1700000, .max = 3500000 },
398         .n = { .min = 3, .max = 6 },
399         .m = { .min = 2, .max = 256 },
400         .m1 = { .min = 0, .max = 0 },
401         .m2 = { .min = 0, .max = 254 },
402         .p = { .min = 7, .max = 112 },
403         .p1 = { .min = 1, .max = 8 },
404         .p2 = { .dot_limit = 112000,
405                 .p2_slow = 14, .p2_fast = 14 },
406 };
407 
408 /* Ironlake / Sandybridge
409  *
410  * We calculate clock using (register_value + 2) for N/M1/M2, so here
411  * the range value for them is (actual_value - 2).
412  */
413 static const intel_limit_t intel_limits_ironlake_dac = {
414         .dot = { .min = 25000, .max = 350000 },
415         .vco = { .min = 1760000, .max = 3510000 },
416         .n = { .min = 1, .max = 5 },
417         .m = { .min = 79, .max = 127 },
418         .m1 = { .min = 12, .max = 22 },
419         .m2 = { .min = 5, .max = 9 },
420         .p = { .min = 5, .max = 80 },
421         .p1 = { .min = 1, .max = 8 },
422         .p2 = { .dot_limit = 225000,
423                 .p2_slow = 10, .p2_fast = 5 },
424 };
425 
426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
427         .dot = { .min = 25000, .max = 350000 },
428         .vco = { .min = 1760000, .max = 3510000 },
429         .n = { .min = 1, .max = 3 },
430         .m = { .min = 79, .max = 118 },
431         .m1 = { .min = 12, .max = 22 },
432         .m2 = { .min = 5, .max = 9 },
433         .p = { .min = 28, .max = 112 },
434         .p1 = { .min = 2, .max = 8 },
435         .p2 = { .dot_limit = 225000,
436                 .p2_slow = 14, .p2_fast = 14 },
437 };
438 
439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
440         .dot = { .min = 25000, .max = 350000 },
441         .vco = { .min = 1760000, .max = 3510000 },
442         .n = { .min = 1, .max = 3 },
443         .m = { .min = 79, .max = 127 },
444         .m1 = { .min = 12, .max = 22 },
445         .m2 = { .min = 5, .max = 9 },
446         .p = { .min = 14, .max = 56 },
447         .p1 = { .min = 2, .max = 8 },
448         .p2 = { .dot_limit = 225000,
449                 .p2_slow = 7, .p2_fast = 7 },
450 };
451 
452 /* LVDS 100mhz refclk limits. */
453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
454         .dot = { .min = 25000, .max = 350000 },
455         .vco = { .min = 1760000, .max = 3510000 },
456         .n = { .min = 1, .max = 2 },
457         .m = { .min = 79, .max = 126 },
458         .m1 = { .min = 12, .max = 22 },
459         .m2 = { .min = 5, .max = 9 },
460         .p = { .min = 28, .max = 112 },
461         .p1 = { .min = 2, .max = 8 },
462         .p2 = { .dot_limit = 225000,
463                 .p2_slow = 14, .p2_fast = 14 },
464 };
465 
466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
467         .dot = { .min = 25000, .max = 350000 },
468         .vco = { .min = 1760000, .max = 3510000 },
469         .n = { .min = 1, .max = 3 },
470         .m = { .min = 79, .max = 126 },
471         .m1 = { .min = 12, .max = 22 },
472         .m2 = { .min = 5, .max = 9 },
473         .p = { .min = 14, .max = 42 },
474         .p1 = { .min = 2, .max = 6 },
475         .p2 = { .dot_limit = 225000,
476                 .p2_slow = 7, .p2_fast = 7 },
477 };
478 
479 static const intel_limit_t intel_limits_vlv = {
480          /*
481           * These are the data rate limits (measured in fast clocks)
482           * since those are the strictest limits we have. The fast
483           * clock and actual rate limits are more relaxed, so checking
484           * them would make no difference.
485           */
486         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
487         .vco = { .min = 4000000, .max = 6000000 },
488         .n = { .min = 1, .max = 7 },
489         .m1 = { .min = 2, .max = 3 },
490         .m2 = { .min = 11, .max = 156 },
491         .p1 = { .min = 2, .max = 3 },
492         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
493 };
494 
495 static const intel_limit_t intel_limits_chv = {
496         /*
497          * These are the data rate limits (measured in fast clocks)
498          * since those are the strictest limits we have.  The fast
499          * clock and actual rate limits are more relaxed, so checking
500          * them would make no difference.
501          */
502         .dot = { .min = 25000 * 5, .max = 540000 * 5},
503         .vco = { .min = 4800000, .max = 6480000 },
504         .n = { .min = 1, .max = 1 },
505         .m1 = { .min = 2, .max = 2 },
506         .m2 = { .min = 24 << 22, .max = 175 << 22 },
507         .p1 = { .min = 2, .max = 4 },
508         .p2 = { .p2_slow = 1, .p2_fast = 14 },
509 };
510 
511 static const intel_limit_t intel_limits_bxt = {
512         /* FIXME: find real dot limits */
513         .dot = { .min = 0, .max = INT_MAX },
514         .vco = { .min = 4800000, .max = 6700000 },
515         .n = { .min = 1, .max = 1 },
516         .m1 = { .min = 2, .max = 2 },
517         /* FIXME: find real m2 limits */
518         .m2 = { .min = 2 << 22, .max = 255 << 22 },
519         .p1 = { .min = 2, .max = 4 },
520         .p2 = { .p2_slow = 1, .p2_fast = 20 },
521 };
522 
523 static bool
524 needs_modeset(struct drm_crtc_state *state)
525 {
526         return drm_atomic_crtc_needs_modeset(state);
527 }
528 
529 /**
530  * Returns whether any output on the specified pipe is of the specified type
531  */
532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
533 {
534         struct drm_device *dev = crtc->base.dev;
535         struct intel_encoder *encoder;
536 
537         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
538                 if (encoder->type == type)
539                         return true;
540 
541         return false;
542 }
543 
544 /**
545  * Returns whether any output on the specified pipe will have the specified
546  * type after a staged modeset is complete, i.e., the same as
547  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
548  * encoder->crtc.
549  */
550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
551                                       int type)
552 {
553         struct drm_atomic_state *state = crtc_state->base.state;
554         struct drm_connector *connector;
555         struct drm_connector_state *connector_state;
556         struct intel_encoder *encoder;
557         int i, num_connectors = 0;
558 
559         for_each_connector_in_state(state, connector, connector_state, i) {
560                 if (connector_state->crtc != crtc_state->base.crtc)
561                         continue;
562 
563                 num_connectors++;
564 
565                 encoder = to_intel_encoder(connector_state->best_encoder);
566                 if (encoder->type == type)
567                         return true;
568         }
569 
570         WARN_ON(num_connectors == 0);
571 
572         return false;
573 }
574 
575 /*
576  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
577  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
578  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
579  * The helpers' return value is the rate of the clock that is fed to the
580  * display engine's pipe which can be the above fast dot clock rate or a
581  * divided-down version of it.
582  */
583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
585 {
586         clock->m = clock->m2 + 2;
587         clock->p = clock->p1 * clock->p2;
588         if (WARN_ON(clock->n == 0 || clock->p == 0))
589                 return 0;
590         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592 
593         return clock->dot;
594 }
595 
596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
597 {
598         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
599 }
600 
601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
602 {
603         clock->m = i9xx_dpll_compute_m(clock);
604         clock->p = clock->p1 * clock->p2;
605         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
606                 return 0;
607         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
608         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
609 
610         return clock->dot;
611 }
612 
613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
614 {
615         clock->m = clock->m1 * clock->m2;
616         clock->p = clock->p1 * clock->p2;
617         if (WARN_ON(clock->n == 0 || clock->p == 0))
618                 return 0;
619         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
620         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
621 
622         return clock->dot / 5;
623 }
624 
625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
626 {
627         clock->m = clock->m1 * clock->m2;
628         clock->p = clock->p1 * clock->p2;
629         if (WARN_ON(clock->n == 0 || clock->p == 0))
630                 return 0;
631         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
632                         clock->n << 22);
633         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
634 
635         return clock->dot / 5;
636 }
637 
638 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
639 /**
640  * Returns whether the given set of divisors are valid for a given refclk with
641  * the given connectors.
642  */
643 
644 static bool intel_PLL_is_valid(struct drm_device *dev,
645                                const intel_limit_t *limit,
646                                const intel_clock_t *clock)
647 {
648         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
649                 INTELPllInvalid("n out of range\n");
650         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
651                 INTELPllInvalid("p1 out of range\n");
652         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
653                 INTELPllInvalid("m2 out of range\n");
654         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
655                 INTELPllInvalid("m1 out of range\n");
656 
657         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
658             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
659                 if (clock->m1 <= clock->m2)
660                         INTELPllInvalid("m1 <= m2\n");
661 
662         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
663                 if (clock->p < limit->p.min || limit->p.max < clock->p)
664                         INTELPllInvalid("p out of range\n");
665                 if (clock->m < limit->m.min || limit->m.max < clock->m)
666                         INTELPllInvalid("m out of range\n");
667         }
668 
669         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
670                 INTELPllInvalid("vco out of range\n");
671         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
672          * connector, etc., rather than just a single range.
673          */
674         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
675                 INTELPllInvalid("dot out of range\n");
676 
677         return true;
678 }
679 
680 static int
681 i9xx_select_p2_div(const intel_limit_t *limit,
682                    const struct intel_crtc_state *crtc_state,
683                    int target)
684 {
685         struct drm_device *dev = crtc_state->base.crtc->dev;
686 
687         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
688                 /*
689                  * For LVDS just rely on its current settings for dual-channel.
690                  * We haven't figured out how to reliably set up different
691                  * single/dual channel state, if we even can.
692                  */
693                 if (intel_is_dual_link_lvds(dev))
694                         return limit->p2.p2_fast;
695                 else
696                         return limit->p2.p2_slow;
697         } else {
698                 if (target < limit->p2.dot_limit)
699                         return limit->p2.p2_slow;
700                 else
701                         return limit->p2.p2_fast;
702         }
703 }
704 
705 /*
706  * Returns a set of divisors for the desired target clock with the given
707  * refclk, or FALSE.  The returned values represent the clock equation:
708  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
709  *
710  * Target and reference clocks are specified in kHz.
711  *
712  * If match_clock is provided, then best_clock P divider must match the P
713  * divider from @match_clock used for LVDS downclocking.
714  */
715 static bool
716 i9xx_find_best_dpll(const intel_limit_t *limit,
717                     struct intel_crtc_state *crtc_state,
718                     int target, int refclk, intel_clock_t *match_clock,
719                     intel_clock_t *best_clock)
720 {
721         struct drm_device *dev = crtc_state->base.crtc->dev;
722         intel_clock_t clock;
723         int err = target;
724 
725         memset(best_clock, 0, sizeof(*best_clock));
726 
727         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
728 
729         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
730              clock.m1++) {
731                 for (clock.m2 = limit->m2.min;
732                      clock.m2 <= limit->m2.max; clock.m2++) {
733                         if (clock.m2 >= clock.m1)
734                                 break;
735                         for (clock.n = limit->n.min;
736                              clock.n <= limit->n.max; clock.n++) {
737                                 for (clock.p1 = limit->p1.min;
738                                         clock.p1 <= limit->p1.max; clock.p1++) {
739                                         int this_err;
740 
741                                         i9xx_calc_dpll_params(refclk, &clock);
742                                         if (!intel_PLL_is_valid(dev, limit,
743                                                                 &clock))
744                                                 continue;
745                                         if (match_clock &&
746                                             clock.p != match_clock->p)
747                                                 continue;
748 
749                                         this_err = abs(clock.dot - target);
750                                         if (this_err < err) {
751                                                 *best_clock = clock;
752                                                 err = this_err;
753                                         }
754                                 }
755                         }
756                 }
757         }
758 
759         return (err != target);
760 }
761 
762 /*
763  * Returns a set of divisors for the desired target clock with the given
764  * refclk, or FALSE.  The returned values represent the clock equation:
765  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
766  *
767  * Target and reference clocks are specified in kHz.
768  *
769  * If match_clock is provided, then best_clock P divider must match the P
770  * divider from @match_clock used for LVDS downclocking.
771  */
772 static bool
773 pnv_find_best_dpll(const intel_limit_t *limit,
774                    struct intel_crtc_state *crtc_state,
775                    int target, int refclk, intel_clock_t *match_clock,
776                    intel_clock_t *best_clock)
777 {
778         struct drm_device *dev = crtc_state->base.crtc->dev;
779         intel_clock_t clock;
780         int err = target;
781 
782         memset(best_clock, 0, sizeof(*best_clock));
783 
784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785 
786         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
787              clock.m1++) {
788                 for (clock.m2 = limit->m2.min;
789                      clock.m2 <= limit->m2.max; clock.m2++) {
790                         for (clock.n = limit->n.min;
791                              clock.n <= limit->n.max; clock.n++) {
792                                 for (clock.p1 = limit->p1.min;
793                                         clock.p1 <= limit->p1.max; clock.p1++) {
794                                         int this_err;
795 
796                                         pnv_calc_dpll_params(refclk, &clock);
797                                         if (!intel_PLL_is_valid(dev, limit,
798                                                                 &clock))
799                                                 continue;
800                                         if (match_clock &&
801                                             clock.p != match_clock->p)
802                                                 continue;
803 
804                                         this_err = abs(clock.dot - target);
805                                         if (this_err < err) {
806                                                 *best_clock = clock;
807                                                 err = this_err;
808                                         }
809                                 }
810                         }
811                 }
812         }
813 
814         return (err != target);
815 }
816 
817 /*
818  * Returns a set of divisors for the desired target clock with the given
819  * refclk, or FALSE.  The returned values represent the clock equation:
820  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
821  *
822  * Target and reference clocks are specified in kHz.
823  *
824  * If match_clock is provided, then best_clock P divider must match the P
825  * divider from @match_clock used for LVDS downclocking.
826  */
827 static bool
828 g4x_find_best_dpll(const intel_limit_t *limit,
829                    struct intel_crtc_state *crtc_state,
830                    int target, int refclk, intel_clock_t *match_clock,
831                    intel_clock_t *best_clock)
832 {
833         struct drm_device *dev = crtc_state->base.crtc->dev;
834         intel_clock_t clock;
835         int max_n;
836         bool found = false;
837         /* approximately equals target * 0.00585 */
838         int err_most = (target >> 8) + (target >> 9);
839 
840         memset(best_clock, 0, sizeof(*best_clock));
841 
842         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
843 
844         max_n = limit->n.max;
845         /* based on hardware requirement, prefer smaller n to precision */
846         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
847                 /* based on hardware requirement, prefere larger m1,m2 */
848                 for (clock.m1 = limit->m1.max;
849                      clock.m1 >= limit->m1.min; clock.m1--) {
850                         for (clock.m2 = limit->m2.max;
851                              clock.m2 >= limit->m2.min; clock.m2--) {
852                                 for (clock.p1 = limit->p1.max;
853                                      clock.p1 >= limit->p1.min; clock.p1--) {
854                                         int this_err;
855 
856                                         i9xx_calc_dpll_params(refclk, &clock);
857                                         if (!intel_PLL_is_valid(dev, limit,
858                                                                 &clock))
859                                                 continue;
860 
861                                         this_err = abs(clock.dot - target);
862                                         if (this_err < err_most) {
863                                                 *best_clock = clock;
864                                                 err_most = this_err;
865                                                 max_n = clock.n;
866                                                 found = true;
867                                         }
868                                 }
869                         }
870                 }
871         }
872         return found;
873 }
874 
875 /*
876  * Check if the calculated PLL configuration is more optimal compared to the
877  * best configuration and error found so far. Return the calculated error.
878  */
879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
880                                const intel_clock_t *calculated_clock,
881                                const intel_clock_t *best_clock,
882                                unsigned int best_error_ppm,
883                                unsigned int *error_ppm)
884 {
885         /*
886          * For CHV ignore the error and consider only the P value.
887          * Prefer a bigger P value based on HW requirements.
888          */
889         if (IS_CHERRYVIEW(dev)) {
890                 *error_ppm = 0;
891 
892                 return calculated_clock->p > best_clock->p;
893         }
894 
895         if (WARN_ON_ONCE(!target_freq))
896                 return false;
897 
898         *error_ppm = div_u64(1000000ULL *
899                                 abs(target_freq - calculated_clock->dot),
900                              target_freq);
901         /*
902          * Prefer a better P value over a better (smaller) error if the error
903          * is small. Ensure this preference for future configurations too by
904          * setting the error to 0.
905          */
906         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
907                 *error_ppm = 0;
908 
909                 return true;
910         }
911 
912         return *error_ppm + 10 < best_error_ppm;
913 }
914 
915 /*
916  * Returns a set of divisors for the desired target clock with the given
917  * refclk, or FALSE.  The returned values represent the clock equation:
918  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
919  */
920 static bool
921 vlv_find_best_dpll(const intel_limit_t *limit,
922                    struct intel_crtc_state *crtc_state,
923                    int target, int refclk, intel_clock_t *match_clock,
924                    intel_clock_t *best_clock)
925 {
926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
927         struct drm_device *dev = crtc->base.dev;
928         intel_clock_t clock;
929         unsigned int bestppm = 1000000;
930         /* min update 19.2 MHz */
931         int max_n = min(limit->n.max, refclk / 19200);
932         bool found = false;
933 
934         target *= 5; /* fast clock */
935 
936         memset(best_clock, 0, sizeof(*best_clock));
937 
938         /* based on hardware requirement, prefer smaller n to precision */
939         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
940                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
942                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
943                                 clock.p = clock.p1 * clock.p2;
944                                 /* based on hardware requirement, prefer bigger m1,m2 values */
945                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
946                                         unsigned int ppm;
947 
948                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
949                                                                      refclk * clock.m1);
950 
951                                         vlv_calc_dpll_params(refclk, &clock);
952 
953                                         if (!intel_PLL_is_valid(dev, limit,
954                                                                 &clock))
955                                                 continue;
956 
957                                         if (!vlv_PLL_is_optimal(dev, target,
958                                                                 &clock,
959                                                                 best_clock,
960                                                                 bestppm, &ppm))
961                                                 continue;
962 
963                                         *best_clock = clock;
964                                         bestppm = ppm;
965                                         found = true;
966                                 }
967                         }
968                 }
969         }
970 
971         return found;
972 }
973 
974 /*
975  * Returns a set of divisors for the desired target clock with the given
976  * refclk, or FALSE.  The returned values represent the clock equation:
977  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
978  */
979 static bool
980 chv_find_best_dpll(const intel_limit_t *limit,
981                    struct intel_crtc_state *crtc_state,
982                    int target, int refclk, intel_clock_t *match_clock,
983                    intel_clock_t *best_clock)
984 {
985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
986         struct drm_device *dev = crtc->base.dev;
987         unsigned int best_error_ppm;
988         intel_clock_t clock;
989         uint64_t m2;
990         int found = false;
991 
992         memset(best_clock, 0, sizeof(*best_clock));
993         best_error_ppm = 1000000;
994 
995         /*
996          * Based on hardware doc, the n always set to 1, and m1 always
997          * set to 2.  If requires to support 200Mhz refclk, we need to
998          * revisit this because n may not 1 anymore.
999          */
1000         clock.n = 1, clock.m1 = 2;
1001         target *= 5;    /* fast clock */
1002 
1003         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004                 for (clock.p2 = limit->p2.p2_fast;
1005                                 clock.p2 >= limit->p2.p2_slow;
1006                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007                         unsigned int error_ppm;
1008 
1009                         clock.p = clock.p1 * clock.p2;
1010 
1011                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012                                         clock.n) << 22, refclk * clock.m1);
1013 
1014                         if (m2 > INT_MAX/clock.m1)
1015                                 continue;
1016 
1017                         clock.m2 = m2;
1018 
1019                         chv_calc_dpll_params(refclk, &clock);
1020 
1021                         if (!intel_PLL_is_valid(dev, limit, &clock))
1022                                 continue;
1023 
1024                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025                                                 best_error_ppm, &error_ppm))
1026                                 continue;
1027 
1028                         *best_clock = clock;
1029                         best_error_ppm = error_ppm;
1030                         found = true;
1031                 }
1032         }
1033 
1034         return found;
1035 }
1036 
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038                         intel_clock_t *best_clock)
1039 {
1040         int refclk = 100000;
1041         const intel_limit_t *limit = &intel_limits_bxt;
1042 
1043         return chv_find_best_dpll(limit, crtc_state,
1044                                   target_clock, refclk, NULL, best_clock);
1045 }
1046 
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050 
1051         /* Be paranoid as we can arrive here with only partial
1052          * state retrieved from the hardware during setup.
1053          *
1054          * We can ditch the adjusted_mode.crtc_clock check as soon
1055          * as Haswell has gained clock readout/fastboot support.
1056          *
1057          * We can ditch the crtc->primary->fb check as soon as we can
1058          * properly reconstruct framebuffers.
1059          *
1060          * FIXME: The intel_crtc->active here should be switched to
1061          * crtc->state->active once we have proper CRTC states wired up
1062          * for atomic.
1063          */
1064         return intel_crtc->active && crtc->primary->state->fb &&
1065                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067 
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069                                              enum pipe pipe)
1070 {
1071         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073 
1074         return intel_crtc->config->cpu_transcoder;
1075 }
1076 
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         i915_reg_t reg = PIPEDSL(pipe);
1081         u32 line1, line2;
1082         u32 line_mask;
1083 
1084         if (IS_GEN2(dev))
1085                 line_mask = DSL_LINEMASK_GEN2;
1086         else
1087                 line_mask = DSL_LINEMASK_GEN3;
1088 
1089         line1 = I915_READ(reg) & line_mask;
1090         msleep(5);
1091         line2 = I915_READ(reg) & line_mask;
1092 
1093         return line1 == line2;
1094 }
1095 
1096 /*
1097  * intel_wait_for_pipe_off - wait for pipe to turn off
1098  * @crtc: crtc whose pipe to wait for
1099  *
1100  * After disabling a pipe, we can't wait for vblank in the usual way,
1101  * spinning on the vblank interrupt status bit, since we won't actually
1102  * see an interrupt when the pipe is disabled.
1103  *
1104  * On Gen4 and above:
1105  *   wait for the pipe register state bit to turn off
1106  *
1107  * Otherwise:
1108  *   wait for the display line value to settle (it usually
1109  *   ends up stopping at the start of the next frame).
1110  *
1111  */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114         struct drm_device *dev = crtc->base.dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117         enum pipe pipe = crtc->pipe;
1118 
1119         if (INTEL_INFO(dev)->gen >= 4) {
1120                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121 
1122                 /* Wait for the Pipe State to go off */
1123                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124                              100))
1125                         WARN(1, "pipe_off wait timed out\n");
1126         } else {
1127                 /* Wait for the display line to settle */
1128                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129                         WARN(1, "pipe_off wait timed out\n");
1130         }
1131 }
1132 
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135                 enum pipe pipe, bool state)
1136 {
1137         u32 val;
1138         bool cur_state;
1139 
1140         val = I915_READ(DPLL(pipe));
1141         cur_state = !!(val & DPLL_VCO_ENABLE);
1142         I915_STATE_WARN(cur_state != state,
1143              "PLL state assertion failure (expected %s, current %s)\n",
1144                         onoff(state), onoff(cur_state));
1145 }
1146 
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150         u32 val;
1151         bool cur_state;
1152 
1153         mutex_lock(&dev_priv->sb_lock);
1154         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155         mutex_unlock(&dev_priv->sb_lock);
1156 
1157         cur_state = val & DSI_PLL_VCO_EN;
1158         I915_STATE_WARN(cur_state != state,
1159              "DSI PLL state assertion failure (expected %s, current %s)\n",
1160                         onoff(state), onoff(cur_state));
1161 }
1162 
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164                           enum pipe pipe, bool state)
1165 {
1166         bool cur_state;
1167         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168                                                                       pipe);
1169 
1170         if (HAS_DDI(dev_priv)) {
1171                 /* DDI does not have a specific FDI_TX register */
1172                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174         } else {
1175                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176                 cur_state = !!(val & FDI_TX_ENABLE);
1177         }
1178         I915_STATE_WARN(cur_state != state,
1179              "FDI TX state assertion failure (expected %s, current %s)\n",
1180                         onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184 
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         u32 val;
1189         bool cur_state;
1190 
1191         val = I915_READ(FDI_RX_CTL(pipe));
1192         cur_state = !!(val & FDI_RX_ENABLE);
1193         I915_STATE_WARN(cur_state != state,
1194              "FDI RX state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199 
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201                                       enum pipe pipe)
1202 {
1203         u32 val;
1204 
1205         /* ILK FDI PLL is always enabled */
1206         if (INTEL_INFO(dev_priv)->gen == 5)
1207                 return;
1208 
1209         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210         if (HAS_DDI(dev_priv))
1211                 return;
1212 
1213         val = I915_READ(FDI_TX_CTL(pipe));
1214         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216 
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218                        enum pipe pipe, bool state)
1219 {
1220         u32 val;
1221         bool cur_state;
1222 
1223         val = I915_READ(FDI_RX_CTL(pipe));
1224         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225         I915_STATE_WARN(cur_state != state,
1226              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227                         onoff(state), onoff(cur_state));
1228 }
1229 
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231                            enum pipe pipe)
1232 {
1233         struct drm_device *dev = dev_priv->dev;
1234         i915_reg_t pp_reg;
1235         u32 val;
1236         enum pipe panel_pipe = PIPE_A;
1237         bool locked = true;
1238 
1239         if (WARN_ON(HAS_DDI(dev)))
1240                 return;
1241 
1242         if (HAS_PCH_SPLIT(dev)) {
1243                 u32 port_sel;
1244 
1245                 pp_reg = PCH_PP_CONTROL;
1246                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247 
1248                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250                         panel_pipe = PIPE_B;
1251                 /* XXX: else fix for eDP */
1252         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253                 /* presumably write lock depends on pipe, not port select */
1254                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255                 panel_pipe = pipe;
1256         } else {
1257                 pp_reg = PP_CONTROL;
1258                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259                         panel_pipe = PIPE_B;
1260         }
1261 
1262         val = I915_READ(pp_reg);
1263         if (!(val & PANEL_POWER_ON) ||
1264             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265                 locked = false;
1266 
1267         I915_STATE_WARN(panel_pipe == pipe && locked,
1268              "panel assertion failure, pipe %c regs locked\n",
1269              pipe_name(pipe));
1270 }
1271 
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273                           enum pipe pipe, bool state)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         bool cur_state;
1277 
1278         if (IS_845G(dev) || IS_I865G(dev))
1279                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280         else
1281                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282 
1283         I915_STATE_WARN(cur_state != state,
1284              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285                         pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289 
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291                  enum pipe pipe, bool state)
1292 {
1293         bool cur_state;
1294         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295                                                                       pipe);
1296         enum intel_display_power_domain power_domain;
1297 
1298         /* if we need the pipe quirk it must be always on */
1299         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301                 state = true;
1302 
1303         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306                 cur_state = !!(val & PIPECONF_ENABLE);
1307 
1308                 intel_display_power_put(dev_priv, power_domain);
1309         } else {
1310                 cur_state = false;
1311         }
1312 
1313         I915_STATE_WARN(cur_state != state,
1314              "pipe %c assertion failure (expected %s, current %s)\n",
1315                         pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317 
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319                          enum plane plane, bool state)
1320 {
1321         u32 val;
1322         bool cur_state;
1323 
1324         val = I915_READ(DSPCNTR(plane));
1325         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326         I915_STATE_WARN(cur_state != state,
1327              "plane %c assertion failure (expected %s, current %s)\n",
1328                         plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330 
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333 
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335                                    enum pipe pipe)
1336 {
1337         struct drm_device *dev = dev_priv->dev;
1338         int i;
1339 
1340         /* Primary planes are fixed to pipes on gen4+ */
1341         if (INTEL_INFO(dev)->gen >= 4) {
1342                 u32 val = I915_READ(DSPCNTR(pipe));
1343                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344                      "plane %c assertion failure, should be disabled but not\n",
1345                      plane_name(pipe));
1346                 return;
1347         }
1348 
1349         /* Need to check both planes against the pipe */
1350         for_each_pipe(dev_priv, i) {
1351                 u32 val = I915_READ(DSPCNTR(i));
1352                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353                         DISPPLANE_SEL_PIPE_SHIFT;
1354                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356                      plane_name(i), pipe_name(pipe));
1357         }
1358 }
1359 
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361                                     enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int sprite;
1365 
1366         if (INTEL_INFO(dev)->gen >= 9) {
1367                 for_each_sprite(dev_priv, pipe, sprite) {
1368                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371                              sprite, pipe_name(pipe));
1372                 }
1373         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374                 for_each_sprite(dev_priv, pipe, sprite) {
1375                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1376                         I915_STATE_WARN(val & SP_ENABLE,
1377                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378                              sprite_name(pipe, sprite), pipe_name(pipe));
1379                 }
1380         } else if (INTEL_INFO(dev)->gen >= 7) {
1381                 u32 val = I915_READ(SPRCTL(pipe));
1382                 I915_STATE_WARN(val & SPRITE_ENABLE,
1383                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384                      plane_name(pipe), pipe_name(pipe));
1385         } else if (INTEL_INFO(dev)->gen >= 5) {
1386                 u32 val = I915_READ(DVSCNTR(pipe));
1387                 I915_STATE_WARN(val & DVS_ENABLE,
1388                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(pipe), pipe_name(pipe));
1390         }
1391 }
1392 
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396                 drm_crtc_vblank_put(crtc);
1397 }
1398 
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400                                     enum pipe pipe)
1401 {
1402         u32 val;
1403         bool enabled;
1404 
1405         val = I915_READ(PCH_TRANSCONF(pipe));
1406         enabled = !!(val & TRANS_ENABLE);
1407         I915_STATE_WARN(enabled,
1408              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409              pipe_name(pipe));
1410 }
1411 
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413                             enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415         if ((val & DP_PORT_EN) == 0)
1416                 return false;
1417 
1418         if (HAS_PCH_CPT(dev_priv)) {
1419                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421                         return false;
1422         } else if (IS_CHERRYVIEW(dev_priv)) {
1423                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424                         return false;
1425         } else {
1426                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427                         return false;
1428         }
1429         return true;
1430 }
1431 
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433                               enum pipe pipe, u32 val)
1434 {
1435         if ((val & SDVO_ENABLE) == 0)
1436                 return false;
1437 
1438         if (HAS_PCH_CPT(dev_priv)) {
1439                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440                         return false;
1441         } else if (IS_CHERRYVIEW(dev_priv)) {
1442                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443                         return false;
1444         } else {
1445                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446                         return false;
1447         }
1448         return true;
1449 }
1450 
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452                               enum pipe pipe, u32 val)
1453 {
1454         if ((val & LVDS_PORT_EN) == 0)
1455                 return false;
1456 
1457         if (HAS_PCH_CPT(dev_priv)) {
1458                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459                         return false;
1460         } else {
1461                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462                         return false;
1463         }
1464         return true;
1465 }
1466 
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468                               enum pipe pipe, u32 val)
1469 {
1470         if ((val & ADPA_DAC_ENABLE) == 0)
1471                 return false;
1472         if (HAS_PCH_CPT(dev_priv)) {
1473                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477                         return false;
1478         }
1479         return true;
1480 }
1481 
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483                                    enum pipe pipe, i915_reg_t reg,
1484                                    u32 port_sel)
1485 {
1486         u32 val = I915_READ(reg);
1487         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489              i915_mmio_reg_offset(reg), pipe_name(pipe));
1490 
1491         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1492              && (val & DP_PIPEB_SELECT),
1493              "IBX PCH dp port still using transcoder B\n");
1494 }
1495 
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497                                      enum pipe pipe, i915_reg_t reg)
1498 {
1499         u32 val = I915_READ(reg);
1500         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502              i915_mmio_reg_offset(reg), pipe_name(pipe));
1503 
1504         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1505              && (val & SDVO_PIPE_B_SELECT),
1506              "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508 
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510                                       enum pipe pipe)
1511 {
1512         u32 val;
1513 
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517 
1518         val = I915_READ(PCH_ADPA);
1519         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520              "PCH VGA enabled on transcoder %c, should be disabled\n",
1521              pipe_name(pipe));
1522 
1523         val = I915_READ(PCH_LVDS);
1524         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526              pipe_name(pipe));
1527 
1528         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532 
1533 static void _vlv_enable_pll(struct intel_crtc *crtc,
1534                             const struct intel_crtc_state *pipe_config)
1535 {
1536         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1537         enum pipe pipe = crtc->pipe;
1538 
1539         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1540         POSTING_READ(DPLL(pipe));
1541         udelay(150);
1542 
1543         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1544                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1545 }
1546 
1547 static void vlv_enable_pll(struct intel_crtc *crtc,
1548                            const struct intel_crtc_state *pipe_config)
1549 {
1550         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1551         enum pipe pipe = crtc->pipe;
1552 
1553         assert_pipe_disabled(dev_priv, pipe);
1554 
1555         /* PLL is protected by panel, make sure we can write it */
1556         assert_panel_unlocked(dev_priv, pipe);
1557 
1558         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1559                 _vlv_enable_pll(crtc, pipe_config);
1560 
1561         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1562         POSTING_READ(DPLL_MD(pipe));
1563 }
1564 
1565 
1566 static void _chv_enable_pll(struct intel_crtc *crtc,
1567                             const struct intel_crtc_state *pipe_config)
1568 {
1569         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570         enum pipe pipe = crtc->pipe;
1571         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1572         u32 tmp;
1573 
1574         mutex_lock(&dev_priv->sb_lock);
1575 
1576         /* Enable back the 10bit clock to display controller */
1577         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1578         tmp |= DPIO_DCLKP_EN;
1579         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1580 
1581         mutex_unlock(&dev_priv->sb_lock);
1582 
1583         /*
1584          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1585          */
1586         udelay(1);
1587 
1588         /* Enable PLL */
1589         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1590 
1591         /* Check PLL is locked */
1592         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1593                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1594 }
1595 
1596 static void chv_enable_pll(struct intel_crtc *crtc,
1597                            const struct intel_crtc_state *pipe_config)
1598 {
1599         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1600         enum pipe pipe = crtc->pipe;
1601 
1602         assert_pipe_disabled(dev_priv, pipe);
1603 
1604         /* PLL is protected by panel, make sure we can write it */
1605         assert_panel_unlocked(dev_priv, pipe);
1606 
1607         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1608                 _chv_enable_pll(crtc, pipe_config);
1609 
1610         if (pipe != PIPE_A) {
1611                 /*
1612                  * WaPixelRepeatModeFixForC0:chv
1613                  *
1614                  * DPLLCMD is AWOL. Use chicken bits to propagate
1615                  * the value from DPLLBMD to either pipe B or C.
1616                  */
1617                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1618                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1619                 I915_WRITE(CBR4_VLV, 0);
1620                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1621 
1622                 /*
1623                  * DPLLB VGA mode also seems to cause problems.
1624                  * We should always have it disabled.
1625                  */
1626                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1627         } else {
1628                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1629                 POSTING_READ(DPLL_MD(pipe));
1630         }
1631 }
1632 
1633 static int intel_num_dvo_pipes(struct drm_device *dev)
1634 {
1635         struct intel_crtc *crtc;
1636         int count = 0;
1637 
1638         for_each_intel_crtc(dev, crtc)
1639                 count += crtc->base.state->active &&
1640                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1641 
1642         return count;
1643 }
1644 
1645 static void i9xx_enable_pll(struct intel_crtc *crtc)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         i915_reg_t reg = DPLL(crtc->pipe);
1650         u32 dpll = crtc->config->dpll_hw_state.dpll;
1651 
1652         assert_pipe_disabled(dev_priv, crtc->pipe);
1653 
1654         /* PLL is protected by panel, make sure we can write it */
1655         if (IS_MOBILE(dev) && !IS_I830(dev))
1656                 assert_panel_unlocked(dev_priv, crtc->pipe);
1657 
1658         /* Enable DVO 2x clock on both PLLs if necessary */
1659         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1660                 /*
1661                  * It appears to be important that we don't enable this
1662                  * for the current pipe before otherwise configuring the
1663                  * PLL. No idea how this should be handled if multiple
1664                  * DVO outputs are enabled simultaneosly.
1665                  */
1666                 dpll |= DPLL_DVO_2X_MODE;
1667                 I915_WRITE(DPLL(!crtc->pipe),
1668                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1669         }
1670 
1671         /*
1672          * Apparently we need to have VGA mode enabled prior to changing
1673          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1674          * dividers, even though the register value does change.
1675          */
1676         I915_WRITE(reg, 0);
1677 
1678         I915_WRITE(reg, dpll);
1679 
1680         /* Wait for the clocks to stabilize. */
1681         POSTING_READ(reg);
1682         udelay(150);
1683 
1684         if (INTEL_INFO(dev)->gen >= 4) {
1685                 I915_WRITE(DPLL_MD(crtc->pipe),
1686                            crtc->config->dpll_hw_state.dpll_md);
1687         } else {
1688                 /* The pixel multiplier can only be updated once the
1689                  * DPLL is enabled and the clocks are stable.
1690                  *
1691                  * So write it again.
1692                  */
1693                 I915_WRITE(reg, dpll);
1694         }
1695 
1696         /* We do this three times for luck */
1697         I915_WRITE(reg, dpll);
1698         POSTING_READ(reg);
1699         udelay(150); /* wait for warmup */
1700         I915_WRITE(reg, dpll);
1701         POSTING_READ(reg);
1702         udelay(150); /* wait for warmup */
1703         I915_WRITE(reg, dpll);
1704         POSTING_READ(reg);
1705         udelay(150); /* wait for warmup */
1706 }
1707 
1708 /**
1709  * i9xx_disable_pll - disable a PLL
1710  * @dev_priv: i915 private structure
1711  * @pipe: pipe PLL to disable
1712  *
1713  * Disable the PLL for @pipe, making sure the pipe is off first.
1714  *
1715  * Note!  This is for pre-ILK only.
1716  */
1717 static void i9xx_disable_pll(struct intel_crtc *crtc)
1718 {
1719         struct drm_device *dev = crtc->base.dev;
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721         enum pipe pipe = crtc->pipe;
1722 
1723         /* Disable DVO 2x clock on both PLLs if necessary */
1724         if (IS_I830(dev) &&
1725             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1726             !intel_num_dvo_pipes(dev)) {
1727                 I915_WRITE(DPLL(PIPE_B),
1728                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1729                 I915_WRITE(DPLL(PIPE_A),
1730                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1731         }
1732 
1733         /* Don't disable pipe or pipe PLLs if needed */
1734         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1735             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1736                 return;
1737 
1738         /* Make sure the pipe isn't still relying on us */
1739         assert_pipe_disabled(dev_priv, pipe);
1740 
1741         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1742         POSTING_READ(DPLL(pipe));
1743 }
1744 
1745 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1746 {
1747         u32 val;
1748 
1749         /* Make sure the pipe isn't still relying on us */
1750         assert_pipe_disabled(dev_priv, pipe);
1751 
1752         val = DPLL_INTEGRATED_REF_CLK_VLV |
1753                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754         if (pipe != PIPE_A)
1755                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756 
1757         I915_WRITE(DPLL(pipe), val);
1758         POSTING_READ(DPLL(pipe));
1759 }
1760 
1761 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1762 {
1763         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1764         u32 val;
1765 
1766         /* Make sure the pipe isn't still relying on us */
1767         assert_pipe_disabled(dev_priv, pipe);
1768 
1769         val = DPLL_SSC_REF_CLK_CHV |
1770                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1771         if (pipe != PIPE_A)
1772                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1773 
1774         I915_WRITE(DPLL(pipe), val);
1775         POSTING_READ(DPLL(pipe));
1776 
1777         mutex_lock(&dev_priv->sb_lock);
1778 
1779         /* Disable 10bit clock to display controller */
1780         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1781         val &= ~DPIO_DCLKP_EN;
1782         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1783 
1784         mutex_unlock(&dev_priv->sb_lock);
1785 }
1786 
1787 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1788                          struct intel_digital_port *dport,
1789                          unsigned int expected_mask)
1790 {
1791         u32 port_mask;
1792         i915_reg_t dpll_reg;
1793 
1794         switch (dport->port) {
1795         case PORT_B:
1796                 port_mask = DPLL_PORTB_READY_MASK;
1797                 dpll_reg = DPLL(0);
1798                 break;
1799         case PORT_C:
1800                 port_mask = DPLL_PORTC_READY_MASK;
1801                 dpll_reg = DPLL(0);
1802                 expected_mask <<= 4;
1803                 break;
1804         case PORT_D:
1805                 port_mask = DPLL_PORTD_READY_MASK;
1806                 dpll_reg = DPIO_PHY_STATUS;
1807                 break;
1808         default:
1809                 BUG();
1810         }
1811 
1812         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1813                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1814                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1815 }
1816 
1817 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1818                                            enum pipe pipe)
1819 {
1820         struct drm_device *dev = dev_priv->dev;
1821         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823         i915_reg_t reg;
1824         uint32_t val, pipeconf_val;
1825 
1826         /* Make sure PCH DPLL is enabled */
1827         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1828 
1829         /* FDI must be feeding us bits for PCH ports */
1830         assert_fdi_tx_enabled(dev_priv, pipe);
1831         assert_fdi_rx_enabled(dev_priv, pipe);
1832 
1833         if (HAS_PCH_CPT(dev)) {
1834                 /* Workaround: Set the timing override bit before enabling the
1835                  * pch transcoder. */
1836                 reg = TRANS_CHICKEN2(pipe);
1837                 val = I915_READ(reg);
1838                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1839                 I915_WRITE(reg, val);
1840         }
1841 
1842         reg = PCH_TRANSCONF(pipe);
1843         val = I915_READ(reg);
1844         pipeconf_val = I915_READ(PIPECONF(pipe));
1845 
1846         if (HAS_PCH_IBX(dev_priv)) {
1847                 /*
1848                  * Make the BPC in transcoder be consistent with
1849                  * that in pipeconf reg. For HDMI we must use 8bpc
1850                  * here for both 8bpc and 12bpc.
1851                  */
1852                 val &= ~PIPECONF_BPC_MASK;
1853                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1854                         val |= PIPECONF_8BPC;
1855                 else
1856                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1857         }
1858 
1859         val &= ~TRANS_INTERLACE_MASK;
1860         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1861                 if (HAS_PCH_IBX(dev_priv) &&
1862                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1863                         val |= TRANS_LEGACY_INTERLACED_ILK;
1864                 else
1865                         val |= TRANS_INTERLACED;
1866         else
1867                 val |= TRANS_PROGRESSIVE;
1868 
1869         I915_WRITE(reg, val | TRANS_ENABLE);
1870         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1871                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1872 }
1873 
1874 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1875                                       enum transcoder cpu_transcoder)
1876 {
1877         u32 val, pipeconf_val;
1878 
1879         /* FDI must be feeding us bits for PCH ports */
1880         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1881         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1882 
1883         /* Workaround: set timing override bit. */
1884         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1885         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1886         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1887 
1888         val = TRANS_ENABLE;
1889         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1890 
1891         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1892             PIPECONF_INTERLACED_ILK)
1893                 val |= TRANS_INTERLACED;
1894         else
1895                 val |= TRANS_PROGRESSIVE;
1896 
1897         I915_WRITE(LPT_TRANSCONF, val);
1898         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1899                 DRM_ERROR("Failed to enable PCH transcoder\n");
1900 }
1901 
1902 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1903                                             enum pipe pipe)
1904 {
1905         struct drm_device *dev = dev_priv->dev;
1906         i915_reg_t reg;
1907         uint32_t val;
1908 
1909         /* FDI relies on the transcoder */
1910         assert_fdi_tx_disabled(dev_priv, pipe);
1911         assert_fdi_rx_disabled(dev_priv, pipe);
1912 
1913         /* Ports must be off as well */
1914         assert_pch_ports_disabled(dev_priv, pipe);
1915 
1916         reg = PCH_TRANSCONF(pipe);
1917         val = I915_READ(reg);
1918         val &= ~TRANS_ENABLE;
1919         I915_WRITE(reg, val);
1920         /* wait for PCH transcoder off, transcoder state */
1921         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1922                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1923 
1924         if (HAS_PCH_CPT(dev)) {
1925                 /* Workaround: Clear the timing override chicken bit again. */
1926                 reg = TRANS_CHICKEN2(pipe);
1927                 val = I915_READ(reg);
1928                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1929                 I915_WRITE(reg, val);
1930         }
1931 }
1932 
1933 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1934 {
1935         u32 val;
1936 
1937         val = I915_READ(LPT_TRANSCONF);
1938         val &= ~TRANS_ENABLE;
1939         I915_WRITE(LPT_TRANSCONF, val);
1940         /* wait for PCH transcoder off, transcoder state */
1941         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1942                 DRM_ERROR("Failed to disable PCH transcoder\n");
1943 
1944         /* Workaround: clear timing override bit. */
1945         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1946         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1947         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1948 }
1949 
1950 /**
1951  * intel_enable_pipe - enable a pipe, asserting requirements
1952  * @crtc: crtc responsible for the pipe
1953  *
1954  * Enable @crtc's pipe, making sure that various hardware specific requirements
1955  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1956  */
1957 static void intel_enable_pipe(struct intel_crtc *crtc)
1958 {
1959         struct drm_device *dev = crtc->base.dev;
1960         struct drm_i915_private *dev_priv = dev->dev_private;
1961         enum pipe pipe = crtc->pipe;
1962         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1963         enum pipe pch_transcoder;
1964         i915_reg_t reg;
1965         u32 val;
1966 
1967         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1968 
1969         assert_planes_disabled(dev_priv, pipe);
1970         assert_cursor_disabled(dev_priv, pipe);
1971         assert_sprites_disabled(dev_priv, pipe);
1972 
1973         if (HAS_PCH_LPT(dev_priv))
1974                 pch_transcoder = TRANSCODER_A;
1975         else
1976                 pch_transcoder = pipe;
1977 
1978         /*
1979          * A pipe without a PLL won't actually be able to drive bits from
1980          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1981          * need the check.
1982          */
1983         if (HAS_GMCH_DISPLAY(dev_priv))
1984                 if (crtc->config->has_dsi_encoder)
1985                         assert_dsi_pll_enabled(dev_priv);
1986                 else
1987                         assert_pll_enabled(dev_priv, pipe);
1988         else {
1989                 if (crtc->config->has_pch_encoder) {
1990                         /* if driving the PCH, we need FDI enabled */
1991                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1992                         assert_fdi_tx_pll_enabled(dev_priv,
1993                                                   (enum pipe) cpu_transcoder);
1994                 }
1995                 /* FIXME: assert CPU port conditions for SNB+ */
1996         }
1997 
1998         reg = PIPECONF(cpu_transcoder);
1999         val = I915_READ(reg);
2000         if (val & PIPECONF_ENABLE) {
2001                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2002                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2003                 return;
2004         }
2005 
2006         I915_WRITE(reg, val | PIPECONF_ENABLE);
2007         POSTING_READ(reg);
2008 
2009         /*
2010          * Until the pipe starts DSL will read as 0, which would cause
2011          * an apparent vblank timestamp jump, which messes up also the
2012          * frame count when it's derived from the timestamps. So let's
2013          * wait for the pipe to start properly before we call
2014          * drm_crtc_vblank_on()
2015          */
2016         if (dev->max_vblank_count == 0 &&
2017             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2018                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2019 }
2020 
2021 /**
2022  * intel_disable_pipe - disable a pipe, asserting requirements
2023  * @crtc: crtc whose pipes is to be disabled
2024  *
2025  * Disable the pipe of @crtc, making sure that various hardware
2026  * specific requirements are met, if applicable, e.g. plane
2027  * disabled, panel fitter off, etc.
2028  *
2029  * Will wait until the pipe has shut down before returning.
2030  */
2031 static void intel_disable_pipe(struct intel_crtc *crtc)
2032 {
2033         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2034         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2035         enum pipe pipe = crtc->pipe;
2036         i915_reg_t reg;
2037         u32 val;
2038 
2039         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2040 
2041         /*
2042          * Make sure planes won't keep trying to pump pixels to us,
2043          * or we might hang the display.
2044          */
2045         assert_planes_disabled(dev_priv, pipe);
2046         assert_cursor_disabled(dev_priv, pipe);
2047         assert_sprites_disabled(dev_priv, pipe);
2048 
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if ((val & PIPECONF_ENABLE) == 0)
2052                 return;
2053 
2054         /*
2055          * Double wide has implications for planes
2056          * so best keep it disabled when not needed.
2057          */
2058         if (crtc->config->double_wide)
2059                 val &= ~PIPECONF_DOUBLE_WIDE;
2060 
2061         /* Don't disable pipe or pipe PLLs if needed */
2062         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2063             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2064                 val &= ~PIPECONF_ENABLE;
2065 
2066         I915_WRITE(reg, val);
2067         if ((val & PIPECONF_ENABLE) == 0)
2068                 intel_wait_for_pipe_off(crtc);
2069 }
2070 
2071 static bool need_vtd_wa(struct drm_device *dev)
2072 {
2073 #ifdef CONFIG_INTEL_IOMMU
2074         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2075                 return true;
2076 #endif
2077         return false;
2078 }
2079 
2080 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2081 {
2082         return IS_GEN2(dev_priv) ? 2048 : 4096;
2083 }
2084 
2085 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2086                                            uint64_t fb_modifier, unsigned int cpp)
2087 {
2088         switch (fb_modifier) {
2089         case DRM_FORMAT_MOD_NONE:
2090                 return cpp;
2091         case I915_FORMAT_MOD_X_TILED:
2092                 if (IS_GEN2(dev_priv))
2093                         return 128;
2094                 else
2095                         return 512;
2096         case I915_FORMAT_MOD_Y_TILED:
2097                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2098                         return 128;
2099                 else
2100                         return 512;
2101         case I915_FORMAT_MOD_Yf_TILED:
2102                 switch (cpp) {
2103                 case 1:
2104                         return 64;
2105                 case 2:
2106                 case 4:
2107                         return 128;
2108                 case 8:
2109                 case 16:
2110                         return 256;
2111                 default:
2112                         MISSING_CASE(cpp);
2113                         return cpp;
2114                 }
2115                 break;
2116         default:
2117                 MISSING_CASE(fb_modifier);
2118                 return cpp;
2119         }
2120 }
2121 
2122 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2123                                uint64_t fb_modifier, unsigned int cpp)
2124 {
2125         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2126                 return 1;
2127         else
2128                 return intel_tile_size(dev_priv) /
2129                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2130 }
2131 
2132 /* Return the tile dimensions in pixel units */
2133 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2134                             unsigned int *tile_width,
2135                             unsigned int *tile_height,
2136                             uint64_t fb_modifier,
2137                             unsigned int cpp)
2138 {
2139         unsigned int tile_width_bytes =
2140                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2141 
2142         *tile_width = tile_width_bytes / cpp;
2143         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2144 }
2145 
2146 unsigned int
2147 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2148                       uint32_t pixel_format, uint64_t fb_modifier)
2149 {
2150         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2151         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2152 
2153         return ALIGN(height, tile_height);
2154 }
2155 
2156 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2157 {
2158         unsigned int size = 0;
2159         int i;
2160 
2161         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2162                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2163 
2164         return size;
2165 }
2166 
2167 static void
2168 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2169                         const struct drm_framebuffer *fb,
2170                         unsigned int rotation)
2171 {
2172         if (intel_rotation_90_or_270(rotation)) {
2173                 *view = i915_ggtt_view_rotated;
2174                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2175         } else {
2176                 *view = i915_ggtt_view_normal;
2177         }
2178 }
2179 
2180 static void
2181 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2182                    struct drm_framebuffer *fb)
2183 {
2184         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2185         unsigned int tile_size, tile_width, tile_height, cpp;
2186 
2187         tile_size = intel_tile_size(dev_priv);
2188 
2189         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2190         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2191                         fb->modifier[0], cpp);
2192 
2193         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2194         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2195 
2196         if (info->pixel_format == DRM_FORMAT_NV12) {
2197                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2198                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2199                                 fb->modifier[1], cpp);
2200 
2201                 info->uv_offset = fb->offsets[1];
2202                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2203                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2204         }
2205 }
2206 
2207 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2208 {
2209         if (INTEL_INFO(dev_priv)->gen >= 9)
2210                 return 256 * 1024;
2211         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2212                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2213                 return 128 * 1024;
2214         else if (INTEL_INFO(dev_priv)->gen >= 4)
2215                 return 4 * 1024;
2216         else
2217                 return 0;
2218 }
2219 
2220 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2221                                          uint64_t fb_modifier)
2222 {
2223         switch (fb_modifier) {
2224         case DRM_FORMAT_MOD_NONE:
2225                 return intel_linear_alignment(dev_priv);
2226         case I915_FORMAT_MOD_X_TILED:
2227                 if (INTEL_INFO(dev_priv)->gen >= 9)
2228                         return 256 * 1024;
2229                 return 0;
2230         case I915_FORMAT_MOD_Y_TILED:
2231         case I915_FORMAT_MOD_Yf_TILED:
2232                 return 1 * 1024 * 1024;
2233         default:
2234                 MISSING_CASE(fb_modifier);
2235                 return 0;
2236         }
2237 }
2238 
2239 int
2240 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2241                            unsigned int rotation)
2242 {
2243         struct drm_device *dev = fb->dev;
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2246         struct i915_ggtt_view view;
2247         u32 alignment;
2248         int ret;
2249 
2250         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2251 
2252         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2253 
2254         intel_fill_fb_ggtt_view(&view, fb, rotation);
2255 
2256         /* Note that the w/a also requires 64 PTE of padding following the
2257          * bo. We currently fill all unused PTE with the shadow page and so
2258          * we should always have valid PTE following the scanout preventing
2259          * the VT-d warning.
2260          */
2261         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2262                 alignment = 256 * 1024;
2263 
2264         /*
2265          * Global gtt pte registers are special registers which actually forward
2266          * writes to a chunk of system memory. Which means that there is no risk
2267          * that the register values disappear as soon as we call
2268          * intel_runtime_pm_put(), so it is correct to wrap only the
2269          * pin/unpin/fence and not more.
2270          */
2271         intel_runtime_pm_get(dev_priv);
2272 
2273         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2274                                                    &view);
2275         if (ret)
2276                 goto err_pm;
2277 
2278         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2279          * fence, whereas 965+ only requires a fence if using
2280          * framebuffer compression.  For simplicity, we always install
2281          * a fence as the cost is not that onerous.
2282          */
2283         if (view.type == I915_GGTT_VIEW_NORMAL) {
2284                 ret = i915_gem_object_get_fence(obj);
2285                 if (ret == -EDEADLK) {
2286                         /*
2287                          * -EDEADLK means there are no free fences
2288                          * no pending flips.
2289                          *
2290                          * This is propagated to atomic, but it uses
2291                          * -EDEADLK to force a locking recovery, so
2292                          * change the returned error to -EBUSY.
2293                          */
2294                         ret = -EBUSY;
2295                         goto err_unpin;
2296                 } else if (ret)
2297                         goto err_unpin;
2298 
2299                 i915_gem_object_pin_fence(obj);
2300         }
2301 
2302         intel_runtime_pm_put(dev_priv);
2303         return 0;
2304 
2305 err_unpin:
2306         i915_gem_object_unpin_from_display_plane(obj, &view);
2307 err_pm:
2308         intel_runtime_pm_put(dev_priv);
2309         return ret;
2310 }
2311 
2312 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2313 {
2314         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2315         struct i915_ggtt_view view;
2316 
2317         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2318 
2319         intel_fill_fb_ggtt_view(&view, fb, rotation);
2320 
2321         if (view.type == I915_GGTT_VIEW_NORMAL)
2322                 i915_gem_object_unpin_fence(obj);
2323 
2324         i915_gem_object_unpin_from_display_plane(obj, &view);
2325 }
2326 
2327 /*
2328  * Adjust the tile offset by moving the difference into
2329  * the x/y offsets.
2330  *
2331  * Input tile dimensions and pitch must already be
2332  * rotated to match x and y, and in pixel units.
2333  */
2334 static u32 intel_adjust_tile_offset(int *x, int *y,
2335                                     unsigned int tile_width,
2336                                     unsigned int tile_height,
2337                                     unsigned int tile_size,
2338                                     unsigned int pitch_tiles,
2339                                     u32 old_offset,
2340                                     u32 new_offset)
2341 {
2342         unsigned int tiles;
2343 
2344         WARN_ON(old_offset & (tile_size - 1));
2345         WARN_ON(new_offset & (tile_size - 1));
2346         WARN_ON(new_offset > old_offset);
2347 
2348         tiles = (old_offset - new_offset) / tile_size;
2349 
2350         *y += tiles / pitch_tiles * tile_height;
2351         *x += tiles % pitch_tiles * tile_width;
2352 
2353         return new_offset;
2354 }
2355 
2356 /*
2357  * Computes the linear offset to the base tile and adjusts
2358  * x, y. bytes per pixel is assumed to be a power-of-two.
2359  *
2360  * In the 90/270 rotated case, x and y are assumed
2361  * to be already rotated to match the rotated GTT view, and
2362  * pitch is the tile_height aligned framebuffer height.
2363  */
2364 u32 intel_compute_tile_offset(int *x, int *y,
2365                               const struct drm_framebuffer *fb, int plane,
2366                               unsigned int pitch,
2367                               unsigned int rotation)
2368 {
2369         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2370         uint64_t fb_modifier = fb->modifier[plane];
2371         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2372         u32 offset, offset_aligned, alignment;
2373 
2374         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2375         if (alignment)
2376                 alignment--;
2377 
2378         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2379                 unsigned int tile_size, tile_width, tile_height;
2380                 unsigned int tile_rows, tiles, pitch_tiles;
2381 
2382                 tile_size = intel_tile_size(dev_priv);
2383                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2384                                 fb_modifier, cpp);
2385 
2386                 if (intel_rotation_90_or_270(rotation)) {
2387                         pitch_tiles = pitch / tile_height;
2388                         swap(tile_width, tile_height);
2389                 } else {
2390                         pitch_tiles = pitch / (tile_width * cpp);
2391                 }
2392 
2393                 tile_rows = *y / tile_height;
2394                 *y %= tile_height;
2395 
2396                 tiles = *x / tile_width;
2397                 *x %= tile_width;
2398 
2399                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2400                 offset_aligned = offset & ~alignment;
2401 
2402                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2403                                          tile_size, pitch_tiles,
2404                                          offset, offset_aligned);
2405         } else {
2406                 offset = *y * pitch + *x * cpp;
2407                 offset_aligned = offset & ~alignment;
2408 
2409                 *y = (offset & alignment) / pitch;
2410                 *x = ((offset & alignment) - *y * pitch) / cpp;
2411         }
2412 
2413         return offset_aligned;
2414 }
2415 
2416 static int i9xx_format_to_fourcc(int format)
2417 {
2418         switch (format) {
2419         case DISPPLANE_8BPP:
2420                 return DRM_FORMAT_C8;
2421         case DISPPLANE_BGRX555:
2422                 return DRM_FORMAT_XRGB1555;
2423         case DISPPLANE_BGRX565:
2424                 return DRM_FORMAT_RGB565;
2425         default:
2426         case DISPPLANE_BGRX888:
2427                 return DRM_FORMAT_XRGB8888;
2428         case DISPPLANE_RGBX888:
2429                 return DRM_FORMAT_XBGR8888;
2430         case DISPPLANE_BGRX101010:
2431                 return DRM_FORMAT_XRGB2101010;
2432         case DISPPLANE_RGBX101010:
2433                 return DRM_FORMAT_XBGR2101010;
2434         }
2435 }
2436 
2437 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2438 {
2439         switch (format) {
2440         case PLANE_CTL_FORMAT_RGB_565:
2441                 return DRM_FORMAT_RGB565;
2442         default:
2443         case PLANE_CTL_FORMAT_XRGB_8888:
2444                 if (rgb_order) {
2445                         if (alpha)
2446                                 return DRM_FORMAT_ABGR8888;
2447                         else
2448                                 return DRM_FORMAT_XBGR8888;
2449                 } else {
2450                         if (alpha)
2451                                 return DRM_FORMAT_ARGB8888;
2452                         else
2453                                 return DRM_FORMAT_XRGB8888;
2454                 }
2455         case PLANE_CTL_FORMAT_XRGB_2101010:
2456                 if (rgb_order)
2457                         return DRM_FORMAT_XBGR2101010;
2458                 else
2459                         return DRM_FORMAT_XRGB2101010;
2460         }
2461 }
2462 
2463 static bool
2464 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2465                               struct intel_initial_plane_config *plane_config)
2466 {
2467         struct drm_device *dev = crtc->base.dev;
2468         struct drm_i915_private *dev_priv = to_i915(dev);
2469         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2470         struct drm_i915_gem_object *obj = NULL;
2471         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2472         struct drm_framebuffer *fb = &plane_config->fb->base;
2473         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2474         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2475                                     PAGE_SIZE);
2476 
2477         size_aligned -= base_aligned;
2478 
2479         if (plane_config->size == 0)
2480                 return false;
2481 
2482         /* If the FB is too big, just don't use it since fbdev is not very
2483          * important and we should probably use that space with FBC or other
2484          * features. */
2485         if (size_aligned * 2 > ggtt->stolen_usable_size)
2486                 return false;
2487 
2488         mutex_lock(&dev->struct_mutex);
2489 
2490         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2491                                                              base_aligned,
2492                                                              base_aligned,
2493                                                              size_aligned);
2494         if (!obj) {
2495                 mutex_unlock(&dev->struct_mutex);
2496                 return false;
2497         }
2498 
2499         obj->tiling_mode = plane_config->tiling;
2500         if (obj->tiling_mode == I915_TILING_X)
2501                 obj->stride = fb->pitches[0];
2502 
2503         mode_cmd.pixel_format = fb->pixel_format;
2504         mode_cmd.width = fb->width;
2505         mode_cmd.height = fb->height;
2506         mode_cmd.pitches[0] = fb->pitches[0];
2507         mode_cmd.modifier[0] = fb->modifier[0];
2508         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2509 
2510         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2511                                    &mode_cmd, obj)) {
2512                 DRM_DEBUG_KMS("intel fb init failed\n");
2513                 goto out_unref_obj;
2514         }
2515 
2516         mutex_unlock(&dev->struct_mutex);
2517 
2518         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2519         return true;
2520 
2521 out_unref_obj:
2522         drm_gem_object_unreference(&obj->base);
2523         mutex_unlock(&dev->struct_mutex);
2524         return false;
2525 }
2526 
2527 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2528 static void
2529 update_state_fb(struct drm_plane *plane)
2530 {
2531         if (plane->fb == plane->state->fb)
2532                 return;
2533 
2534         if (plane->state->fb)
2535                 drm_framebuffer_unreference(plane->state->fb);
2536         plane->state->fb = plane->fb;
2537         if (plane->state->fb)
2538                 drm_framebuffer_reference(plane->state->fb);
2539 }
2540 
2541 static void
2542 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2543                              struct intel_initial_plane_config *plane_config)
2544 {
2545         struct drm_device *dev = intel_crtc->base.dev;
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct drm_crtc *c;
2548         struct intel_crtc *i;
2549         struct drm_i915_gem_object *obj;
2550         struct drm_plane *primary = intel_crtc->base.primary;
2551         struct drm_plane_state *plane_state = primary->state;
2552         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2553         struct intel_plane *intel_plane = to_intel_plane(primary);
2554         struct intel_plane_state *intel_state =
2555                 to_intel_plane_state(plane_state);
2556         struct drm_framebuffer *fb;
2557 
2558         if (!plane_config->fb)
2559                 return;
2560 
2561         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2562                 fb = &plane_config->fb->base;
2563                 goto valid_fb;
2564         }
2565 
2566         kfree(plane_config->fb);
2567 
2568         /*
2569          * Failed to alloc the obj, check to see if we should share
2570          * an fb with another CRTC instead
2571          */
2572         for_each_crtc(dev, c) {
2573                 i = to_intel_crtc(c);
2574 
2575                 if (c == &intel_crtc->base)
2576                         continue;
2577 
2578                 if (!i->active)
2579                         continue;
2580 
2581                 fb = c->primary->fb;
2582                 if (!fb)
2583                         continue;
2584 
2585                 obj = intel_fb_obj(fb);
2586                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2587                         drm_framebuffer_reference(fb);
2588                         goto valid_fb;
2589                 }
2590         }
2591 
2592         /*
2593          * We've failed to reconstruct the BIOS FB.  Current display state
2594          * indicates that the primary plane is visible, but has a NULL FB,
2595          * which will lead to problems later if we don't fix it up.  The
2596          * simplest solution is to just disable the primary plane now and
2597          * pretend the BIOS never had it enabled.
2598          */
2599         to_intel_plane_state(plane_state)->visible = false;
2600         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2601         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2602         intel_plane->disable_plane(primary, &intel_crtc->base);
2603 
2604         return;
2605 
2606 valid_fb:
2607         plane_state->src_x = 0;
2608         plane_state->src_y = 0;
2609         plane_state->src_w = fb->width << 16;
2610         plane_state->src_h = fb->height << 16;
2611 
2612         plane_state->crtc_x = 0;
2613         plane_state->crtc_y = 0;
2614         plane_state->crtc_w = fb->width;
2615         plane_state->crtc_h = fb->height;
2616 
2617         intel_state->src.x1 = plane_state->src_x;
2618         intel_state->src.y1 = plane_state->src_y;
2619         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2620         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2621         intel_state->dst.x1 = plane_state->crtc_x;
2622         intel_state->dst.y1 = plane_state->crtc_y;
2623         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2624         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2625 
2626         obj = intel_fb_obj(fb);
2627         if (obj->tiling_mode != I915_TILING_NONE)
2628                 dev_priv->preserve_bios_swizzle = true;
2629 
2630         drm_framebuffer_reference(fb);
2631         primary->fb = primary->state->fb = fb;
2632         primary->crtc = primary->state->crtc = &intel_crtc->base;
2633         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2634         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2635 }
2636 
2637 static void i9xx_update_primary_plane(struct drm_plane *primary,
2638                                       const struct intel_crtc_state *crtc_state,
2639                                       const struct intel_plane_state *plane_state)
2640 {
2641         struct drm_device *dev = primary->dev;
2642         struct drm_i915_private *dev_priv = dev->dev_private;
2643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2644         struct drm_framebuffer *fb = plane_state->base.fb;
2645         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2646         int plane = intel_crtc->plane;
2647         u32 linear_offset;
2648         u32 dspcntr;
2649         i915_reg_t reg = DSPCNTR(plane);
2650         unsigned int rotation = plane_state->base.rotation;
2651         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2652         int x = plane_state->src.x1 >> 16;
2653         int y = plane_state->src.y1 >> 16;
2654 
2655         dspcntr = DISPPLANE_GAMMA_ENABLE;
2656 
2657         dspcntr |= DISPLAY_PLANE_ENABLE;
2658 
2659         if (INTEL_INFO(dev)->gen < 4) {
2660                 if (intel_crtc->pipe == PIPE_B)
2661                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2662 
2663                 /* pipesrc and dspsize control the size that is scaled from,
2664                  * which should always be the user's requested size.
2665                  */
2666                 I915_WRITE(DSPSIZE(plane),
2667                            ((crtc_state->pipe_src_h - 1) << 16) |
2668                            (crtc_state->pipe_src_w - 1));
2669                 I915_WRITE(DSPPOS(plane), 0);
2670         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2671                 I915_WRITE(PRIMSIZE(plane),
2672                            ((crtc_state->pipe_src_h - 1) << 16) |
2673                            (crtc_state->pipe_src_w - 1));
2674                 I915_WRITE(PRIMPOS(plane), 0);
2675                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2676         }
2677 
2678         switch (fb->pixel_format) {
2679         case DRM_FORMAT_C8:
2680                 dspcntr |= DISPPLANE_8BPP;
2681                 break;
2682         case DRM_FORMAT_XRGB1555:
2683                 dspcntr |= DISPPLANE_BGRX555;
2684                 break;
2685         case DRM_FORMAT_RGB565:
2686                 dspcntr |= DISPPLANE_BGRX565;
2687                 break;
2688         case DRM_FORMAT_XRGB8888:
2689                 dspcntr |= DISPPLANE_BGRX888;
2690                 break;
2691         case DRM_FORMAT_XBGR8888:
2692                 dspcntr |= DISPPLANE_RGBX888;
2693                 break;
2694         case DRM_FORMAT_XRGB2101010:
2695                 dspcntr |= DISPPLANE_BGRX101010;
2696                 break;
2697         case DRM_FORMAT_XBGR2101010:
2698                 dspcntr |= DISPPLANE_RGBX101010;
2699                 break;
2700         default:
2701                 BUG();
2702         }
2703 
2704         if (INTEL_INFO(dev)->gen >= 4 &&
2705             obj->tiling_mode != I915_TILING_NONE)
2706                 dspcntr |= DISPPLANE_TILED;
2707 
2708         if (IS_G4X(dev))
2709                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2710 
2711         linear_offset = y * fb->pitches[0] + x * cpp;
2712 
2713         if (INTEL_INFO(dev)->gen >= 4) {
2714                 intel_crtc->dspaddr_offset =
2715                         intel_compute_tile_offset(&x, &y, fb, 0,
2716                                                   fb->pitches[0], rotation);
2717                 linear_offset -= intel_crtc->dspaddr_offset;
2718         } else {
2719                 intel_crtc->dspaddr_offset = linear_offset;
2720         }
2721 
2722         if (rotation == BIT(DRM_ROTATE_180)) {
2723                 dspcntr |= DISPPLANE_ROTATE_180;
2724 
2725                 x += (crtc_state->pipe_src_w - 1);
2726                 y += (crtc_state->pipe_src_h - 1);
2727 
2728                 /* Finding the last pixel of the last line of the display
2729                 data and adding to linear_offset*/
2730                 linear_offset +=
2731                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2732                         (crtc_state->pipe_src_w - 1) * cpp;
2733         }
2734 
2735         intel_crtc->adjusted_x = x;
2736         intel_crtc->adjusted_y = y;
2737 
2738         I915_WRITE(reg, dspcntr);
2739 
2740         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2741         if (INTEL_INFO(dev)->gen >= 4) {
2742                 I915_WRITE(DSPSURF(plane),
2743                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2744                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2745                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2746         } else
2747                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2748         POSTING_READ(reg);
2749 }
2750 
2751 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2752                                        struct drm_crtc *crtc)
2753 {
2754         struct drm_device *dev = crtc->dev;
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2757         int plane = intel_crtc->plane;
2758 
2759         I915_WRITE(DSPCNTR(plane), 0);
2760         if (INTEL_INFO(dev_priv)->gen >= 4)
2761                 I915_WRITE(DSPSURF(plane), 0);
2762         else
2763                 I915_WRITE(DSPADDR(plane), 0);
2764         POSTING_READ(DSPCNTR(plane));
2765 }
2766 
2767 static void ironlake_update_primary_plane(struct drm_plane *primary,
2768                                           const struct intel_crtc_state *crtc_state,
2769                                           const struct intel_plane_state *plane_state)
2770 {
2771         struct drm_device *dev = primary->dev;
2772         struct drm_i915_private *dev_priv = dev->dev_private;
2773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2774         struct drm_framebuffer *fb = plane_state->base.fb;
2775         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2776         int plane = intel_crtc->plane;
2777         u32 linear_offset;
2778         u32 dspcntr;
2779         i915_reg_t reg = DSPCNTR(plane);
2780         unsigned int rotation = plane_state->base.rotation;
2781         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2782         int x = plane_state->src.x1 >> 16;
2783         int y = plane_state->src.y1 >> 16;
2784 
2785         dspcntr = DISPPLANE_GAMMA_ENABLE;
2786         dspcntr |= DISPLAY_PLANE_ENABLE;
2787 
2788         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2789                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2790 
2791         switch (fb->pixel_format) {
2792         case DRM_FORMAT_C8:
2793                 dspcntr |= DISPPLANE_8BPP;
2794                 break;
2795         case DRM_FORMAT_RGB565:
2796                 dspcntr |= DISPPLANE_BGRX565;
2797                 break;
2798         case DRM_FORMAT_XRGB8888:
2799                 dspcntr |= DISPPLANE_BGRX888;
2800                 break;
2801         case DRM_FORMAT_XBGR8888:
2802                 dspcntr |= DISPPLANE_RGBX888;
2803                 break;
2804         case DRM_FORMAT_XRGB2101010:
2805                 dspcntr |= DISPPLANE_BGRX101010;
2806                 break;
2807         case DRM_FORMAT_XBGR2101010:
2808                 dspcntr |= DISPPLANE_RGBX101010;
2809                 break;
2810         default:
2811                 BUG();
2812         }
2813 
2814         if (obj->tiling_mode != I915_TILING_NONE)
2815                 dspcntr |= DISPPLANE_TILED;
2816 
2817         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2818                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2819 
2820         linear_offset = y * fb->pitches[0] + x * cpp;
2821         intel_crtc->dspaddr_offset =
2822                 intel_compute_tile_offset(&x, &y, fb, 0,
2823                                           fb->pitches[0], rotation);
2824         linear_offset -= intel_crtc->dspaddr_offset;
2825         if (rotation == BIT(DRM_ROTATE_180)) {
2826                 dspcntr |= DISPPLANE_ROTATE_180;
2827 
2828                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2829                         x += (crtc_state->pipe_src_w - 1);
2830                         y += (crtc_state->pipe_src_h - 1);
2831 
2832                         /* Finding the last pixel of the last line of the display
2833                         data and adding to linear_offset*/
2834                         linear_offset +=
2835                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2836                                 (crtc_state->pipe_src_w - 1) * cpp;
2837                 }
2838         }
2839 
2840         intel_crtc->adjusted_x = x;
2841         intel_crtc->adjusted_y = y;
2842 
2843         I915_WRITE(reg, dspcntr);
2844 
2845         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2846         I915_WRITE(DSPSURF(plane),
2847                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2848         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2849                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2850         } else {
2851                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2852                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2853         }
2854         POSTING_READ(reg);
2855 }
2856 
2857 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2858                               uint64_t fb_modifier, uint32_t pixel_format)
2859 {
2860         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2861                 return 64;
2862         } else {
2863                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2864 
2865                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2866         }
2867 }
2868 
2869 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2870                            struct drm_i915_gem_object *obj,
2871                            unsigned int plane)
2872 {
2873         struct i915_ggtt_view view;
2874         struct i915_vma *vma;
2875         u64 offset;
2876 
2877         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2878                                 intel_plane->base.state->rotation);
2879 
2880         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2881         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2882                 view.type))
2883                 return -1;
2884 
2885         offset = vma->node.start;
2886 
2887         if (plane == 1) {
2888                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2889                           PAGE_SIZE;
2890         }
2891 
2892         WARN_ON(upper_32_bits(offset));
2893 
2894         return lower_32_bits(offset);
2895 }
2896 
2897 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2898 {
2899         struct drm_device *dev = intel_crtc->base.dev;
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901 
2902         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2903         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2904         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2905 }
2906 
2907 /*
2908  * This function detaches (aka. unbinds) unused scalers in hardware
2909  */
2910 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2911 {
2912         struct intel_crtc_scaler_state *scaler_state;
2913         int i;
2914 
2915         scaler_state = &intel_crtc->config->scaler_state;
2916 
2917         /* loop through and disable scalers that aren't in use */
2918         for (i = 0; i < intel_crtc->num_scalers; i++) {
2919                 if (!scaler_state->scalers[i].in_use)
2920                         skl_detach_scaler(intel_crtc, i);
2921         }
2922 }
2923 
2924 u32 skl_plane_ctl_format(uint32_t pixel_format)
2925 {
2926         switch (pixel_format) {
2927         case DRM_FORMAT_C8:
2928                 return PLANE_CTL_FORMAT_INDEXED;
2929         case DRM_FORMAT_RGB565:
2930                 return PLANE_CTL_FORMAT_RGB_565;
2931         case DRM_FORMAT_XBGR8888:
2932                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2933         case DRM_FORMAT_XRGB8888:
2934                 return PLANE_CTL_FORMAT_XRGB_8888;
2935         /*
2936          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2937          * to be already pre-multiplied. We need to add a knob (or a different
2938          * DRM_FORMAT) for user-space to configure that.
2939          */
2940         case DRM_FORMAT_ABGR8888:
2941                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2942                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2943         case DRM_FORMAT_ARGB8888:
2944                 return PLANE_CTL_FORMAT_XRGB_8888 |
2945                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946         case DRM_FORMAT_XRGB2101010:
2947                 return PLANE_CTL_FORMAT_XRGB_2101010;
2948         case DRM_FORMAT_XBGR2101010:
2949                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2950         case DRM_FORMAT_YUYV:
2951                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2952         case DRM_FORMAT_YVYU:
2953                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2954         case DRM_FORMAT_UYVY:
2955                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2956         case DRM_FORMAT_VYUY:
2957                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2958         default:
2959                 MISSING_CASE(pixel_format);
2960         }
2961 
2962         return 0;
2963 }
2964 
2965 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2966 {
2967         switch (fb_modifier) {
2968         case DRM_FORMAT_MOD_NONE:
2969                 break;
2970         case I915_FORMAT_MOD_X_TILED:
2971                 return PLANE_CTL_TILED_X;
2972         case I915_FORMAT_MOD_Y_TILED:
2973                 return PLANE_CTL_TILED_Y;
2974         case I915_FORMAT_MOD_Yf_TILED:
2975                 return PLANE_CTL_TILED_YF;
2976         default:
2977                 MISSING_CASE(fb_modifier);
2978         }
2979 
2980         return 0;
2981 }
2982 
2983 u32 skl_plane_ctl_rotation(unsigned int rotation)
2984 {
2985         switch (rotation) {
2986         case BIT(DRM_ROTATE_0):
2987                 break;
2988         /*
2989          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2990          * while i915 HW rotation is clockwise, thats why this swapping.
2991          */
2992         case BIT(DRM_ROTATE_90):
2993                 return PLANE_CTL_ROTATE_270;
2994         case BIT(DRM_ROTATE_180):
2995                 return PLANE_CTL_ROTATE_180;
2996         case BIT(DRM_ROTATE_270):
2997                 return PLANE_CTL_ROTATE_90;
2998         default:
2999                 MISSING_CASE(rotation);
3000         }
3001 
3002         return 0;
3003 }
3004 
3005 static void skylake_update_primary_plane(struct drm_plane *plane,
3006                                          const struct intel_crtc_state *crtc_state,
3007                                          const struct intel_plane_state *plane_state)
3008 {
3009         struct drm_device *dev = plane->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3012         struct drm_framebuffer *fb = plane_state->base.fb;
3013         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3014         int pipe = intel_crtc->pipe;
3015         u32 plane_ctl, stride_div, stride;
3016         u32 tile_height, plane_offset, plane_size;
3017         unsigned int rotation = plane_state->base.rotation;
3018         int x_offset, y_offset;
3019         u32 surf_addr;
3020         int scaler_id = plane_state->scaler_id;
3021         int src_x = plane_state->src.x1 >> 16;
3022         int src_y = plane_state->src.y1 >> 16;
3023         int src_w = drm_rect_width(&plane_state->src) >> 16;
3024         int src_h = drm_rect_height(&plane_state->src) >> 16;
3025         int dst_x = plane_state->dst.x1;
3026         int dst_y = plane_state->dst.y1;
3027         int dst_w = drm_rect_width(&plane_state->dst);
3028         int dst_h = drm_rect_height(&plane_state->dst);
3029 
3030         plane_ctl = PLANE_CTL_ENABLE |
3031                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3032                     PLANE_CTL_PIPE_CSC_ENABLE;
3033 
3034         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3035         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3036         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3037         plane_ctl |= skl_plane_ctl_rotation(rotation);
3038 
3039         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3040                                                fb->pixel_format);
3041         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3042 
3043         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3044 
3045         if (intel_rotation_90_or_270(rotation)) {
3046                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3047 
3048                 /* stride = Surface height in tiles */
3049                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3050                 stride = DIV_ROUND_UP(fb->height, tile_height);
3051                 x_offset = stride * tile_height - src_y - src_h;
3052                 y_offset = src_x;
3053                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3054         } else {
3055                 stride = fb->pitches[0] / stride_div;
3056                 x_offset = src_x;
3057                 y_offset = src_y;
3058                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3059         }
3060         plane_offset = y_offset << 16 | x_offset;
3061 
3062         intel_crtc->adjusted_x = x_offset;
3063         intel_crtc->adjusted_y = y_offset;
3064 
3065         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3066         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3067         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3068         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3069 
3070         if (scaler_id >= 0) {
3071                 uint32_t ps_ctrl = 0;
3072 
3073                 WARN_ON(!dst_w || !dst_h);
3074                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3075                         crtc_state->scaler_state.scalers[scaler_id].mode;
3076                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3077                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3078                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3079                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3080                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3081         } else {
3082                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3083         }
3084 
3085         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3086 
3087         POSTING_READ(PLANE_SURF(pipe, 0));
3088 }
3089 
3090 static void skylake_disable_primary_plane(struct drm_plane *primary,
3091                                           struct drm_crtc *crtc)
3092 {
3093         struct drm_device *dev = crtc->dev;
3094         struct drm_i915_private *dev_priv = dev->dev_private;
3095         int pipe = to_intel_crtc(crtc)->pipe;
3096 
3097         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3098         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3099         POSTING_READ(PLANE_SURF(pipe, 0));
3100 }
3101 
3102 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3103 static int
3104 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3105                            int x, int y, enum mode_set_atomic state)
3106 {
3107         /* Support for kgdboc is disabled, this needs a major rework. */
3108         DRM_ERROR("legacy panic handler not supported any more.\n");
3109 
3110         return -ENODEV;
3111 }
3112 
3113 static void intel_complete_page_flips(struct drm_device *dev)
3114 {
3115         struct drm_crtc *crtc;
3116 
3117         for_each_crtc(dev, crtc) {
3118                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119                 enum plane plane = intel_crtc->plane;
3120 
3121                 intel_prepare_page_flip(dev, plane);
3122                 intel_finish_page_flip_plane(dev, plane);
3123         }
3124 }
3125 
3126 static void intel_update_primary_planes(struct drm_device *dev)
3127 {
3128         struct drm_crtc *crtc;
3129 
3130         for_each_crtc(dev, crtc) {
3131                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3132                 struct intel_plane_state *plane_state;
3133 
3134                 drm_modeset_lock_crtc(crtc, &plane->base);
3135                 plane_state = to_intel_plane_state(plane->base.state);
3136 
3137                 if (plane_state->visible)
3138                         plane->update_plane(&plane->base,
3139                                             to_intel_crtc_state(crtc->state),
3140                                             plane_state);
3141 
3142                 drm_modeset_unlock_crtc(crtc);
3143         }
3144 }
3145 
3146 void intel_prepare_reset(struct drm_device *dev)
3147 {
3148         /* no reset support for gen2 */
3149         if (IS_GEN2(dev))
3150                 return;
3151 
3152         /* reset doesn't touch the display */
3153         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3154                 return;
3155 
3156         drm_modeset_lock_all(dev);
3157         /*
3158          * Disabling the crtcs gracefully seems nicer. Also the
3159          * g33 docs say we should at least disable all the planes.
3160          */
3161         intel_display_suspend(dev);
3162 }
3163 
3164 void intel_finish_reset(struct drm_device *dev)
3165 {
3166         struct drm_i915_private *dev_priv = to_i915(dev);
3167 
3168         /*
3169          * Flips in the rings will be nuked by the reset,
3170          * so complete all pending flips so that user space
3171          * will get its events and not get stuck.
3172          */
3173         intel_complete_page_flips(dev);
3174 
3175         /* no reset support for gen2 */
3176         if (IS_GEN2(dev))
3177                 return;
3178 
3179         /* reset doesn't touch the display */
3180         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3181                 /*
3182                  * Flips in the rings have been nuked by the reset,
3183                  * so update the base address of all primary
3184                  * planes to the the last fb to make sure we're
3185                  * showing the correct fb after a reset.
3186                  *
3187                  * FIXME: Atomic will make this obsolete since we won't schedule
3188                  * CS-based flips (which might get lost in gpu resets) any more.
3189                  */
3190                 intel_update_primary_planes(dev);
3191                 return;
3192         }
3193 
3194         /*
3195          * The display has been reset as well,
3196          * so need a full re-initialization.
3197          */
3198         intel_runtime_pm_disable_interrupts(dev_priv);
3199         intel_runtime_pm_enable_interrupts(dev_priv);
3200 
3201         intel_modeset_init_hw(dev);
3202 
3203         spin_lock_irq(&dev_priv->irq_lock);
3204         if (dev_priv->display.hpd_irq_setup)
3205                 dev_priv->display.hpd_irq_setup(dev);
3206         spin_unlock_irq(&dev_priv->irq_lock);
3207 
3208         intel_display_resume(dev);
3209 
3210         intel_hpd_init(dev_priv);
3211 
3212         drm_modeset_unlock_all(dev);
3213 }
3214 
3215 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3216 {
3217         struct drm_device *dev = crtc->dev;
3218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3219         unsigned reset_counter;
3220         bool pending;
3221 
3222         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3223         if (intel_crtc->reset_counter != reset_counter)
3224                 return false;
3225 
3226         spin_lock_irq(&dev->event_lock);
3227         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3228         spin_unlock_irq(&dev->event_lock);
3229 
3230         return pending;
3231 }
3232 
3233 static void intel_update_pipe_config(struct intel_crtc *crtc,
3234                                      struct intel_crtc_state *old_crtc_state)
3235 {
3236         struct drm_device *dev = crtc->base.dev;
3237         struct drm_i915_private *dev_priv = dev->dev_private;
3238         struct intel_crtc_state *pipe_config =
3239                 to_intel_crtc_state(crtc->base.state);
3240 
3241         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3242         crtc->base.mode = crtc->base.state->mode;
3243 
3244         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3245                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3246                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3247 
3248         /*
3249          * Update pipe size and adjust fitter if needed: the reason for this is
3250          * that in compute_mode_changes we check the native mode (not the pfit
3251          * mode) to see if we can flip rather than do a full mode set. In the
3252          * fastboot case, we'll flip, but if we don't update the pipesrc and
3253          * pfit state, we'll end up with a big fb scanned out into the wrong
3254          * sized surface.
3255          */
3256 
3257         I915_WRITE(PIPESRC(crtc->pipe),
3258                    ((pipe_config->pipe_src_w - 1) << 16) |
3259                    (pipe_config->pipe_src_h - 1));
3260 
3261         /* on skylake this is done by detaching scalers */
3262         if (INTEL_INFO(dev)->gen >= 9) {
3263                 skl_detach_scalers(crtc);
3264 
3265                 if (pipe_config->pch_pfit.enabled)
3266                         skylake_pfit_enable(crtc);
3267         } else if (HAS_PCH_SPLIT(dev)) {
3268                 if (pipe_config->pch_pfit.enabled)
3269                         ironlake_pfit_enable(crtc);
3270                 else if (old_crtc_state->pch_pfit.enabled)
3271                         ironlake_pfit_disable(crtc, true);
3272         }
3273 }
3274 
3275 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280         int pipe = intel_crtc->pipe;
3281         i915_reg_t reg;
3282         u32 temp;
3283 
3284         /* enable normal train */
3285         reg = FDI_TX_CTL(pipe);
3286         temp = I915_READ(reg);
3287         if (IS_IVYBRIDGE(dev)) {
3288                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3289                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3290         } else {
3291                 temp &= ~FDI_LINK_TRAIN_NONE;
3292                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3293         }
3294         I915_WRITE(reg, temp);
3295 
3296         reg = FDI_RX_CTL(pipe);
3297         temp = I915_READ(reg);
3298         if (HAS_PCH_CPT(dev)) {
3299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3301         } else {
3302                 temp &= ~FDI_LINK_TRAIN_NONE;
3303                 temp |= FDI_LINK_TRAIN_NONE;
3304         }
3305         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3306 
3307         /* wait one idle pattern time */
3308         POSTING_READ(reg);
3309         udelay(1000);
3310 
3311         /* IVB wants error correction enabled */
3312         if (IS_IVYBRIDGE(dev))
3313                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3314                            FDI_FE_ERRC_ENABLE);
3315 }
3316 
3317 /* The FDI link training functions for ILK/Ibexpeak. */
3318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3319 {
3320         struct drm_device *dev = crtc->dev;
3321         struct drm_i915_private *dev_priv = dev->dev_private;
3322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323         int pipe = intel_crtc->pipe;
3324         i915_reg_t reg;
3325         u32 temp, tries;
3326 
3327         /* FDI needs bits from pipe first */
3328         assert_pipe_enabled(dev_priv, pipe);
3329 
3330         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3331            for train result */
3332         reg = FDI_RX_IMR(pipe);
3333         temp = I915_READ(reg);
3334         temp &= ~FDI_RX_SYMBOL_LOCK;
3335         temp &= ~FDI_RX_BIT_LOCK;
3336         I915_WRITE(reg, temp);
3337         I915_READ(reg);
3338         udelay(150);
3339 
3340         /* enable CPU FDI TX and PCH FDI RX */
3341         reg = FDI_TX_CTL(pipe);
3342         temp = I915_READ(reg);
3343         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3344         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3345         temp &= ~FDI_LINK_TRAIN_NONE;
3346         temp |= FDI_LINK_TRAIN_PATTERN_1;
3347         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3348 
3349         reg = FDI_RX_CTL(pipe);
3350         temp = I915_READ(reg);
3351         temp &= ~FDI_LINK_TRAIN_NONE;
3352         temp |= FDI_LINK_TRAIN_PATTERN_1;
3353         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3354 
3355         POSTING_READ(reg);
3356         udelay(150);
3357 
3358         /* Ironlake workaround, enable clock pointer after FDI enable*/
3359         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3360         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3361                    FDI_RX_PHASE_SYNC_POINTER_EN);
3362 
3363         reg = FDI_RX_IIR(pipe);
3364         for (tries = 0; tries < 5; tries++) {
3365                 temp = I915_READ(reg);
3366                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3367 
3368                 if ((temp & FDI_RX_BIT_LOCK)) {
3369                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3370                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3371                         break;
3372                 }
3373         }
3374         if (tries == 5)
3375                 DRM_ERROR("FDI train 1 fail!\n");
3376 
3377         /* Train 2 */
3378         reg = FDI_TX_CTL(pipe);
3379         temp = I915_READ(reg);
3380         temp &= ~FDI_LINK_TRAIN_NONE;
3381         temp |= FDI_LINK_TRAIN_PATTERN_2;
3382         I915_WRITE(reg, temp);
3383 
3384         reg = FDI_RX_CTL(pipe);
3385         temp = I915_READ(reg);
3386         temp &= ~FDI_LINK_TRAIN_NONE;
3387         temp |= FDI_LINK_TRAIN_PATTERN_2;
3388         I915_WRITE(reg, temp);
3389 
3390         POSTING_READ(reg);
3391         udelay(150);
3392 
3393         reg = FDI_RX_IIR(pipe);
3394         for (tries = 0; tries < 5; tries++) {
3395                 temp = I915_READ(reg);
3396                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3397 
3398                 if (temp & FDI_RX_SYMBOL_LOCK) {
3399                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3400                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3401                         break;
3402                 }
3403         }
3404         if (tries == 5)
3405                 DRM_ERROR("FDI train 2 fail!\n");
3406 
3407         DRM_DEBUG_KMS("FDI train done\n");
3408 
3409 }
3410 
3411 static const int snb_b_fdi_train_param[] = {
3412         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3413         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3414         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3415         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3416 };
3417 
3418 /* The FDI link training functions for SNB/Cougarpoint. */
3419 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3420 {
3421         struct drm_device *dev = crtc->dev;
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424         int pipe = intel_crtc->pipe;
3425         i915_reg_t reg;
3426         u32 temp, i, retry;
3427 
3428         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3429            for train result */
3430         reg = FDI_RX_IMR(pipe);
3431         temp = I915_READ(reg);
3432         temp &= ~FDI_RX_SYMBOL_LOCK;
3433         temp &= ~FDI_RX_BIT_LOCK;
3434         I915_WRITE(reg, temp);
3435 
3436         POSTING_READ(reg);
3437         udelay(150);
3438 
3439         /* enable CPU FDI TX and PCH FDI RX */
3440         reg = FDI_TX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3443         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3444         temp &= ~FDI_LINK_TRAIN_NONE;
3445         temp |= FDI_LINK_TRAIN_PATTERN_1;
3446         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3447         /* SNB-B */
3448         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3449         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3450 
3451         I915_WRITE(FDI_RX_MISC(pipe),
3452                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3453 
3454         reg = FDI_RX_CTL(pipe);
3455         temp = I915_READ(reg);
3456         if (HAS_PCH_CPT(dev)) {
3457                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3458                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3459         } else {
3460                 temp &= ~FDI_LINK_TRAIN_NONE;
3461                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3462         }
3463         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3464 
3465         POSTING_READ(reg);
3466         udelay(150);
3467 
3468         for (i = 0; i < 4; i++) {
3469                 reg = FDI_TX_CTL(pipe);
3470                 temp = I915_READ(reg);
3471                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3472                 temp |= snb_b_fdi_train_param[i];
3473                 I915_WRITE(reg, temp);
3474 
3475                 POSTING_READ(reg);
3476                 udelay(500);
3477 
3478                 for (retry = 0; retry < 5; retry++) {
3479                         reg = FDI_RX_IIR(pipe);
3480                         temp = I915_READ(reg);
3481                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3482                         if (temp & FDI_RX_BIT_LOCK) {
3483                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3484                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3485                                 break;
3486                         }
3487                         udelay(50);
3488                 }
3489                 if (retry < 5)
3490                         break;
3491         }
3492         if (i == 4)
3493                 DRM_ERROR("FDI train 1 fail!\n");
3494 
3495         /* Train 2 */
3496         reg = FDI_TX_CTL(pipe);
3497         temp = I915_READ(reg);
3498         temp &= ~FDI_LINK_TRAIN_NONE;
3499         temp |= FDI_LINK_TRAIN_PATTERN_2;
3500         if (IS_GEN6(dev)) {
3501                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3502                 /* SNB-B */
3503                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3504         }
3505         I915_WRITE(reg, temp);
3506 
3507         reg = FDI_RX_CTL(pipe);
3508         temp = I915_READ(reg);
3509         if (HAS_PCH_CPT(dev)) {
3510                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3511                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3512         } else {
3513                 temp &= ~FDI_LINK_TRAIN_NONE;
3514                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3515         }
3516         I915_WRITE(reg, temp);
3517 
3518         POSTING_READ(reg);
3519         udelay(150);
3520 
3521         for (i = 0; i < 4; i++) {
3522                 reg = FDI_TX_CTL(pipe);
3523                 temp = I915_READ(reg);
3524                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3525                 temp |= snb_b_fdi_train_param[i];
3526                 I915_WRITE(reg, temp);
3527 
3528                 POSTING_READ(reg);
3529                 udelay(500);
3530 
3531                 for (retry = 0; retry < 5; retry++) {
3532                         reg = FDI_RX_IIR(pipe);
3533                         temp = I915_READ(reg);
3534                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3535                         if (temp & FDI_RX_SYMBOL_LOCK) {
3536                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3537                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3538                                 break;
3539                         }
3540                         udelay(50);
3541                 }
3542                 if (retry < 5)
3543                         break;
3544         }
3545         if (i == 4)
3546                 DRM_ERROR("FDI train 2 fail!\n");
3547 
3548         DRM_DEBUG_KMS("FDI train done.\n");
3549 }
3550 
3551 /* Manual link training for Ivy Bridge A0 parts */
3552 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3553 {
3554         struct drm_device *dev = crtc->dev;
3555         struct drm_i915_private *dev_priv = dev->dev_private;
3556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557         int pipe = intel_crtc->pipe;
3558         i915_reg_t reg;
3559         u32 temp, i, j;
3560 
3561         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3562            for train result */
3563         reg = FDI_RX_IMR(pipe);
3564         temp = I915_READ(reg);
3565         temp &= ~FDI_RX_SYMBOL_LOCK;
3566         temp &= ~FDI_RX_BIT_LOCK;
3567         I915_WRITE(reg, temp);
3568 
3569         POSTING_READ(reg);
3570         udelay(150);
3571 
3572         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3573                       I915_READ(FDI_RX_IIR(pipe)));
3574 
3575         /* Try each vswing and preemphasis setting twice before moving on */
3576         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3577                 /* disable first in case we need to retry */
3578                 reg = FDI_TX_CTL(pipe);
3579                 temp = I915_READ(reg);
3580                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3581                 temp &= ~FDI_TX_ENABLE;
3582                 I915_WRITE(reg, temp);
3583 
3584                 reg = FDI_RX_CTL(pipe);
3585                 temp = I915_READ(reg);
3586                 temp &= ~FDI_LINK_TRAIN_AUTO;
3587                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3588                 temp &= ~FDI_RX_ENABLE;
3589                 I915_WRITE(reg, temp);
3590 
3591                 /* enable CPU FDI TX and PCH FDI RX */
3592                 reg = FDI_TX_CTL(pipe);
3593                 temp = I915_READ(reg);
3594                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3595                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3596                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3597                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598                 temp |= snb_b_fdi_train_param[j/2];
3599                 temp |= FDI_COMPOSITE_SYNC;
3600                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3601 
3602                 I915_WRITE(FDI_RX_MISC(pipe),
3603                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3604 
3605                 reg = FDI_RX_CTL(pipe);
3606                 temp = I915_READ(reg);
3607                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3608                 temp |= FDI_COMPOSITE_SYNC;
3609                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3610 
3611                 POSTING_READ(reg);
3612                 udelay(1); /* should be 0.5us */
3613 
3614                 for (i = 0; i < 4; i++) {
3615                         reg = FDI_RX_IIR(pipe);
3616                         temp = I915_READ(reg);
3617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3618 
3619                         if (temp & FDI_RX_BIT_LOCK ||
3620                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3621                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3622                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3623                                               i);
3624                                 break;
3625                         }
3626                         udelay(1); /* should be 0.5us */
3627                 }
3628                 if (i == 4) {
3629                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3630                         continue;
3631                 }
3632 
3633                 /* Train 2 */
3634                 reg = FDI_TX_CTL(pipe);
3635                 temp = I915_READ(reg);
3636                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3637                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3638                 I915_WRITE(reg, temp);
3639 
3640                 reg = FDI_RX_CTL(pipe);
3641                 temp = I915_READ(reg);
3642                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3643                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3644                 I915_WRITE(reg, temp);
3645 
3646                 POSTING_READ(reg);
3647                 udelay(2); /* should be 1.5us */
3648 
3649                 for (i = 0; i < 4; i++) {
3650                         reg = FDI_RX_IIR(pipe);
3651                         temp = I915_READ(reg);
3652                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3653 
3654                         if (temp & FDI_RX_SYMBOL_LOCK ||
3655                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3656                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3657                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3658                                               i);
3659                                 goto train_done;
3660                         }
3661                         udelay(2); /* should be 1.5us */
3662                 }
3663                 if (i == 4)
3664                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3665         }
3666 
3667 train_done:
3668         DRM_DEBUG_KMS("FDI train done.\n");
3669 }
3670 
3671 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3672 {
3673         struct drm_device *dev = intel_crtc->base.dev;
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675         int pipe = intel_crtc->pipe;
3676         i915_reg_t reg;
3677         u32 temp;
3678 
3679         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3680         reg = FDI_RX_CTL(pipe);
3681         temp = I915_READ(reg);
3682         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3683         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3684         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3685         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3686 
3687         POSTING_READ(reg);
3688         udelay(200);
3689 
3690         /* Switch from Rawclk to PCDclk */
3691         temp = I915_READ(reg);
3692         I915_WRITE(reg, temp | FDI_PCDCLK);
3693 
3694         POSTING_READ(reg);
3695         udelay(200);
3696 
3697         /* Enable CPU FDI TX PLL, always on for Ironlake */
3698         reg = FDI_TX_CTL(pipe);
3699         temp = I915_READ(reg);
3700         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3701                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3702 
3703                 POSTING_READ(reg);
3704                 udelay(100);
3705         }
3706 }
3707 
3708 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3709 {
3710         struct drm_device *dev = intel_crtc->base.dev;
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712         int pipe = intel_crtc->pipe;
3713         i915_reg_t reg;
3714         u32 temp;
3715 
3716         /* Switch from PCDclk to Rawclk */
3717         reg = FDI_RX_CTL(pipe);
3718         temp = I915_READ(reg);
3719         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3720 
3721         /* Disable CPU FDI TX PLL */
3722         reg = FDI_TX_CTL(pipe);
3723         temp = I915_READ(reg);
3724         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3725 
3726         POSTING_READ(reg);
3727         udelay(100);
3728 
3729         reg = FDI_RX_CTL(pipe);
3730         temp = I915_READ(reg);
3731         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3732 
3733         /* Wait for the clocks to turn off. */
3734         POSTING_READ(reg);
3735         udelay(100);
3736 }
3737 
3738 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3739 {
3740         struct drm_device *dev = crtc->dev;
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743         int pipe = intel_crtc->pipe;
3744         i915_reg_t reg;
3745         u32 temp;
3746 
3747         /* disable CPU FDI tx and PCH FDI rx */
3748         reg = FDI_TX_CTL(pipe);
3749         temp = I915_READ(reg);
3750         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3751         POSTING_READ(reg);
3752 
3753         reg = FDI_RX_CTL(pipe);
3754         temp = I915_READ(reg);
3755         temp &= ~(0x7 << 16);
3756         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3758 
3759         POSTING_READ(reg);
3760         udelay(100);
3761 
3762         /* Ironlake workaround, disable clock pointer after downing FDI */
3763         if (HAS_PCH_IBX(dev))
3764                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3765 
3766         /* still set train pattern 1 */
3767         reg = FDI_TX_CTL(pipe);
3768         temp = I915_READ(reg);
3769         temp &= ~FDI_LINK_TRAIN_NONE;
3770         temp |= FDI_LINK_TRAIN_PATTERN_1;
3771         I915_WRITE(reg, temp);
3772 
3773         reg = FDI_RX_CTL(pipe);
3774         temp = I915_READ(reg);
3775         if (HAS_PCH_CPT(dev)) {
3776                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3777                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3778         } else {
3779                 temp &= ~FDI_LINK_TRAIN_NONE;
3780                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3781         }
3782         /* BPC in FDI rx is consistent with that in PIPECONF */
3783         temp &= ~(0x07 << 16);
3784         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3785         I915_WRITE(reg, temp);
3786 
3787         POSTING_READ(reg);
3788         udelay(100);
3789 }
3790 
3791 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3792 {
3793         struct intel_crtc *crtc;
3794 
3795         /* Note that we don't need to be called with mode_config.lock here
3796          * as our list of CRTC objects is static for the lifetime of the
3797          * device and so cannot disappear as we iterate. Similarly, we can
3798          * happily treat the predicates as racy, atomic checks as userspace
3799          * cannot claim and pin a new fb without at least acquring the
3800          * struct_mutex and so serialising with us.
3801          */
3802         for_each_intel_crtc(dev, crtc) {
3803                 if (atomic_read(&crtc->unpin_work_count) == 0)
3804                         continue;
3805 
3806                 if (crtc->unpin_work)
3807                         intel_wait_for_vblank(dev, crtc->pipe);
3808 
3809                 return true;
3810         }
3811 
3812         return false;
3813 }
3814 
3815 static void page_flip_completed(struct intel_crtc *intel_crtc)
3816 {
3817         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3818         struct intel_unpin_work *work = intel_crtc->unpin_work;
3819 
3820         /* ensure that the unpin work is consistent wrt ->pending. */
3821         smp_rmb();
3822         intel_crtc->unpin_work = NULL;
3823 
3824         if (work->event)
3825                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3826 
3827         drm_crtc_vblank_put(&intel_crtc->base);
3828 
3829         wake_up_all(&dev_priv->pending_flip_queue);
3830         queue_work(dev_priv->wq, &work->work);
3831 
3832         trace_i915_flip_complete(intel_crtc->plane,
3833                                  work->pending_flip_obj);
3834 }
3835 
3836 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3837 {
3838         struct drm_device *dev = crtc->dev;
3839         struct drm_i915_private *dev_priv = dev->dev_private;
3840         long ret;
3841 
3842         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3843 
3844         ret = wait_event_interruptible_timeout(
3845                                         dev_priv->pending_flip_queue,
3846                                         !intel_crtc_has_pending_flip(crtc),
3847                                         60*HZ);
3848 
3849         if (ret < 0)
3850                 return ret;
3851 
3852         if (ret == 0) {
3853                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3854 
3855                 spin_lock_irq(&dev->event_lock);
3856                 if (intel_crtc->unpin_work) {
3857                         WARN_ONCE(1, "Removing stuck page flip\n");
3858                         page_flip_completed(intel_crtc);
3859                 }
3860                 spin_unlock_irq(&dev->event_lock);
3861         }
3862 
3863         return 0;
3864 }
3865 
3866 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3867 {
3868         u32 temp;
3869 
3870         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3871 
3872         mutex_lock(&dev_priv->sb_lock);
3873 
3874         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3875         temp |= SBI_SSCCTL_DISABLE;
3876         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3877 
3878         mutex_unlock(&dev_priv->sb_lock);
3879 }
3880 
3881 /* Program iCLKIP clock to the desired frequency */
3882 static void lpt_program_iclkip(struct drm_crtc *crtc)
3883 {
3884         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3885         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3886         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3887         u32 temp;
3888 
3889         lpt_disable_iclkip(dev_priv);
3890 
3891         /* The iCLK virtual clock root frequency is in MHz,
3892          * but the adjusted_mode->crtc_clock in in KHz. To get the
3893          * divisors, it is necessary to divide one by another, so we
3894          * convert the virtual clock precision to KHz here for higher
3895          * precision.
3896          */
3897         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3898                 u32 iclk_virtual_root_freq = 172800 * 1000;
3899                 u32 iclk_pi_range = 64;
3900                 u32 desired_divisor;
3901 
3902                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3903                                                     clock << auxdiv);
3904                 divsel = (desired_divisor / iclk_pi_range) - 2;
3905                 phaseinc = desired_divisor % iclk_pi_range;
3906 
3907                 /*
3908                  * Near 20MHz is a corner case which is
3909                  * out of range for the 7-bit divisor
3910                  */
3911                 if (divsel <= 0x7f)
3912                         break;
3913         }
3914 
3915         /* This should not happen with any sane values */
3916         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3917                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3918         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3919                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3920 
3921         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3922                         clock,
3923                         auxdiv,
3924                         divsel,
3925                         phasedir,
3926                         phaseinc);
3927 
3928         mutex_lock(&dev_priv->sb_lock);
3929 
3930         /* Program SSCDIVINTPHASE6 */
3931         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3932         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3933         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3934         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3935         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3936         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3937         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3938         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3939 
3940         /* Program SSCAUXDIV */
3941         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3942         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3943         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3944         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3945 
3946         /* Enable modulator and associated divider */
3947         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3948         temp &= ~SBI_SSCCTL_DISABLE;
3949         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3950 
3951         mutex_unlock(&dev_priv->sb_lock);
3952 
3953         /* Wait for initialization time */
3954         udelay(24);
3955 
3956         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3957 }
3958 
3959 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3960 {
3961         u32 divsel, phaseinc, auxdiv;
3962         u32 iclk_virtual_root_freq = 172800 * 1000;
3963         u32 iclk_pi_range = 64;
3964         u32 desired_divisor;
3965         u32 temp;
3966 
3967         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3968                 return 0;
3969 
3970         mutex_lock(&dev_priv->sb_lock);
3971 
3972         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3973         if (temp & SBI_SSCCTL_DISABLE) {
3974                 mutex_unlock(&dev_priv->sb_lock);
3975                 return 0;
3976         }
3977 
3978         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3979         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3980                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3981         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3982                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3983 
3984         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3985         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3986                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3987 
3988         mutex_unlock(&dev_priv->sb_lock);
3989 
3990         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3991 
3992         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3993                                  desired_divisor << auxdiv);
3994 }
3995 
3996 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3997                                                 enum pipe pch_transcoder)
3998 {
3999         struct drm_device *dev = crtc->base.dev;
4000         struct drm_i915_private *dev_priv = dev->dev_private;
4001         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4002 
4003         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4004                    I915_READ(HTOTAL(cpu_transcoder)));
4005         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4006                    I915_READ(HBLANK(cpu_transcoder)));
4007         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4008                    I915_READ(HSYNC(cpu_transcoder)));
4009 
4010         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4011                    I915_READ(VTOTAL(cpu_transcoder)));
4012         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4013                    I915_READ(VBLANK(cpu_transcoder)));
4014         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4015                    I915_READ(VSYNC(cpu_transcoder)));
4016         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4017                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4018 }
4019 
4020 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4021 {
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         uint32_t temp;
4024 
4025         temp = I915_READ(SOUTH_CHICKEN1);
4026         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4027                 return;
4028 
4029         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4030         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4031 
4032         temp &= ~FDI_BC_BIFURCATION_SELECT;
4033         if (enable)
4034                 temp |= FDI_BC_BIFURCATION_SELECT;
4035 
4036         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4037         I915_WRITE(SOUTH_CHICKEN1, temp);
4038         POSTING_READ(SOUTH_CHICKEN1);
4039 }
4040 
4041 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4042 {
4043         struct drm_device *dev = intel_crtc->base.dev;
4044 
4045         switch (intel_crtc->pipe) {
4046         case PIPE_A:
4047                 break;
4048         case PIPE_B:
4049                 if (intel_crtc->config->fdi_lanes > 2)
4050                         cpt_set_fdi_bc_bifurcation(dev, false);
4051                 else
4052                         cpt_set_fdi_bc_bifurcation(dev, true);
4053 
4054                 break;
4055         case PIPE_C:
4056                 cpt_set_fdi_bc_bifurcation(dev, true);
4057 
4058                 break;
4059         default:
4060                 BUG();
4061         }
4062 }
4063 
4064 /* Return which DP Port should be selected for Transcoder DP control */
4065 static enum port
4066 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4067 {
4068         struct drm_device *dev = crtc->dev;
4069         struct intel_encoder *encoder;
4070 
4071         for_each_encoder_on_crtc(dev, crtc, encoder) {
4072                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4073                     encoder->type == INTEL_OUTPUT_EDP)
4074                         return enc_to_dig_port(&encoder->base)->port;
4075         }
4076 
4077         return -1;
4078 }
4079 
4080 /*
4081  * Enable PCH resources required for PCH ports:
4082  *   - PCH PLLs
4083  *   - FDI training & RX/TX
4084  *   - update transcoder timings
4085  *   - DP transcoding bits
4086  *   - transcoder
4087  */
4088 static void ironlake_pch_enable(struct drm_crtc *crtc)
4089 {
4090         struct drm_device *dev = crtc->dev;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093         int pipe = intel_crtc->pipe;
4094         u32 temp;
4095 
4096         assert_pch_transcoder_disabled(dev_priv, pipe);
4097 
4098         if (IS_IVYBRIDGE(dev))
4099                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4100 
4101         /* Write the TU size bits before fdi link training, so that error
4102          * detection works. */
4103         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4104                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4105 
4106         /* For PCH output, training FDI link */
4107         dev_priv->display.fdi_link_train(crtc);
4108 
4109         /* We need to program the right clock selection before writing the pixel
4110          * mutliplier into the DPLL. */
4111         if (HAS_PCH_CPT(dev)) {
4112                 u32 sel;
4113 
4114                 temp = I915_READ(PCH_DPLL_SEL);
4115                 temp |= TRANS_DPLL_ENABLE(pipe);
4116                 sel = TRANS_DPLLB_SEL(pipe);
4117                 if (intel_crtc->config->shared_dpll ==
4118                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4119                         temp |= sel;
4120                 else
4121                         temp &= ~sel;
4122                 I915_WRITE(PCH_DPLL_SEL, temp);
4123         }
4124 
4125         /* XXX: pch pll's can be enabled any time before we enable the PCH
4126          * transcoder, and we actually should do this to not upset any PCH
4127          * transcoder that already use the clock when we share it.
4128          *
4129          * Note that enable_shared_dpll tries to do the right thing, but
4130          * get_shared_dpll unconditionally resets the pll - we need that to have
4131          * the right LVDS enable sequence. */
4132         intel_enable_shared_dpll(intel_crtc);
4133 
4134         /* set transcoder timing, panel must allow it */
4135         assert_panel_unlocked(dev_priv, pipe);
4136         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4137 
4138         intel_fdi_normal_train(crtc);
4139 
4140         /* For PCH DP, enable TRANS_DP_CTL */
4141         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4142                 const struct drm_display_mode *adjusted_mode =
4143                         &intel_crtc->config->base.adjusted_mode;
4144                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4145                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4146                 temp = I915_READ(reg);
4147                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4148                           TRANS_DP_SYNC_MASK |
4149                           TRANS_DP_BPC_MASK);
4150                 temp |= TRANS_DP_OUTPUT_ENABLE;
4151                 temp |= bpc << 9; /* same format but at 11:9 */
4152 
4153                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4154                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4155                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4156                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4157 
4158                 switch (intel_trans_dp_port_sel(crtc)) {
4159                 case PORT_B:
4160                         temp |= TRANS_DP_PORT_SEL_B;
4161                         break;
4162                 case PORT_C:
4163                         temp |= TRANS_DP_PORT_SEL_C;
4164                         break;
4165                 case PORT_D:
4166                         temp |= TRANS_DP_PORT_SEL_D;
4167                         break;
4168                 default:
4169                         BUG();
4170                 }
4171 
4172                 I915_WRITE(reg, temp);
4173         }
4174 
4175         ironlake_enable_pch_transcoder(dev_priv, pipe);
4176 }
4177 
4178 static void lpt_pch_enable(struct drm_crtc *crtc)
4179 {
4180         struct drm_device *dev = crtc->dev;
4181         struct drm_i915_private *dev_priv = dev->dev_private;
4182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4184 
4185         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4186 
4187         lpt_program_iclkip(crtc);
4188 
4189         /* Set transcoder timing. */
4190         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4191 
4192         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4193 }
4194 
4195 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4196 {
4197         struct drm_i915_private *dev_priv = dev->dev_private;
4198         i915_reg_t dslreg = PIPEDSL(pipe);
4199         u32 temp;
4200 
4201         temp = I915_READ(dslreg);
4202         udelay(500);
4203         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4204                 if (wait_for(I915_READ(dslreg) != temp, 5))
4205                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4206         }
4207 }
4208 
4209 static int
4210 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4211                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4212                   int src_w, int src_h, int dst_w, int dst_h)
4213 {
4214         struct intel_crtc_scaler_state *scaler_state =
4215                 &crtc_state->scaler_state;
4216         struct intel_crtc *intel_crtc =
4217                 to_intel_crtc(crtc_state->base.crtc);
4218         int need_scaling;
4219 
4220         need_scaling = intel_rotation_90_or_270(rotation) ?
4221                 (src_h != dst_w || src_w != dst_h):
4222                 (src_w != dst_w || src_h != dst_h);
4223 
4224         /*
4225          * if plane is being disabled or scaler is no more required or force detach
4226          *  - free scaler binded to this plane/crtc
4227          *  - in order to do this, update crtc->scaler_usage
4228          *
4229          * Here scaler state in crtc_state is set free so that
4230          * scaler can be assigned to other user. Actual register
4231          * update to free the scaler is done in plane/panel-fit programming.
4232          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4233          */
4234         if (force_detach || !need_scaling) {
4235                 if (*scaler_id >= 0) {
4236                         scaler_state->scaler_users &= ~(1 << scaler_user);
4237                         scaler_state->scalers[*scaler_id].in_use = 0;
4238 
4239                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4240                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4241                                 intel_crtc->pipe, scaler_user, *scaler_id,
4242                                 scaler_state->scaler_users);
4243                         *scaler_id = -1;
4244                 }
4245                 return 0;
4246         }
4247 
4248         /* range checks */
4249         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4250                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4251 
4252                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4253                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4254                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4255                         "size is out of scaler range\n",
4256                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4257                 return -EINVAL;
4258         }
4259 
4260         /* mark this plane as a scaler user in crtc_state */
4261         scaler_state->scaler_users |= (1 << scaler_user);
4262         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4263                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4264                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4265                 scaler_state->scaler_users);
4266 
4267         return 0;
4268 }
4269 
4270 /**
4271  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4272  *
4273  * @state: crtc's scaler state
4274  *
4275  * Return
4276  *     0 - scaler_usage updated successfully
4277  *    error - requested scaling cannot be supported or other error condition
4278  */
4279 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4280 {
4281         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4282         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4283 
4284         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4285                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4286 
4287         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4288                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4289                 state->pipe_src_w, state->pipe_src_h,
4290                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4291 }
4292 
4293 /**
4294  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4295  *
4296  * @state: crtc's scaler state
4297  * @plane_state: atomic plane state to update
4298  *
4299  * Return
4300  *     0 - scaler_usage updated successfully
4301  *    error - requested scaling cannot be supported or other error condition
4302  */
4303 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4304                                    struct intel_plane_state *plane_state)
4305 {
4306 
4307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4308         struct intel_plane *intel_plane =
4309                 to_intel_plane(plane_state->base.plane);
4310         struct drm_framebuffer *fb = plane_state->base.fb;
4311         int ret;
4312 
4313         bool force_detach = !fb || !plane_state->visible;
4314 
4315         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4316                       intel_plane->base.base.id, intel_crtc->pipe,
4317                       drm_plane_index(&intel_plane->base));
4318 
4319         ret = skl_update_scaler(crtc_state, force_detach,
4320                                 drm_plane_index(&intel_plane->base),
4321                                 &plane_state->scaler_id,
4322                                 plane_state->base.rotation,
4323                                 drm_rect_width(&plane_state->src) >> 16,
4324                                 drm_rect_height(&plane_state->src) >> 16,
4325                                 drm_rect_width(&plane_state->dst),
4326                                 drm_rect_height(&plane_state->dst));
4327 
4328         if (ret || plane_state->scaler_id < 0)
4329                 return ret;
4330 
4331         /* check colorkey */
4332         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4333                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4334                               intel_plane->base.base.id);
4335                 return -EINVAL;
4336         }
4337 
4338         /* Check src format */
4339         switch (fb->pixel_format) {
4340         case DRM_FORMAT_RGB565:
4341         case DRM_FORMAT_XBGR8888:
4342         case DRM_FORMAT_XRGB8888:
4343         case DRM_FORMAT_ABGR8888:
4344         case DRM_FORMAT_ARGB8888:
4345         case DRM_FORMAT_XRGB2101010:
4346         case DRM_FORMAT_XBGR2101010:
4347         case DRM_FORMAT_YUYV:
4348         case DRM_FORMAT_YVYU:
4349         case DRM_FORMAT_UYVY:
4350         case DRM_FORMAT_VYUY:
4351                 break;
4352         default:
4353                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4354                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4355                 return -EINVAL;
4356         }
4357 
4358         return 0;
4359 }
4360 
4361 static void skylake_scaler_disable(struct intel_crtc *crtc)
4362 {
4363         int i;
4364 
4365         for (i = 0; i < crtc->num_scalers; i++)
4366                 skl_detach_scaler(crtc, i);
4367 }
4368 
4369 static void skylake_pfit_enable(struct intel_crtc *crtc)
4370 {
4371         struct drm_device *dev = crtc->base.dev;
4372         struct drm_i915_private *dev_priv = dev->dev_private;
4373         int pipe = crtc->pipe;
4374         struct intel_crtc_scaler_state *scaler_state =
4375                 &crtc->config->scaler_state;
4376 
4377         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4378 
4379         if (crtc->config->pch_pfit.enabled) {
4380                 int id;
4381 
4382                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4383                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4384                         return;
4385                 }
4386 
4387                 id = scaler_state->scaler_id;
4388                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4389                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4390                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4391                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4392 
4393                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4394         }
4395 }
4396 
4397 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4398 {
4399         struct drm_device *dev = crtc->base.dev;
4400         struct drm_i915_private *dev_priv = dev->dev_private;
4401         int pipe = crtc->pipe;
4402 
4403         if (crtc->config->pch_pfit.enabled) {
4404                 /* Force use of hard-coded filter coefficients
4405                  * as some pre-programmed values are broken,
4406                  * e.g. x201.
4407                  */
4408                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4409                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4410                                                  PF_PIPE_SEL_IVB(pipe));
4411                 else
4412                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4413                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4414                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4415         }
4416 }
4417 
4418 void hsw_enable_ips(struct intel_crtc *crtc)
4419 {
4420         struct drm_device *dev = crtc->base.dev;
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422 
4423         if (!crtc->config->ips_enabled)
4424                 return;
4425 
4426         /*
4427          * We can only enable IPS after we enable a plane and wait for a vblank
4428          * This function is called from post_plane_update, which is run after
4429          * a vblank wait.
4430          */
4431 
4432         assert_plane_enabled(dev_priv, crtc->plane);
4433         if (IS_BROADWELL(dev)) {
4434                 mutex_lock(&dev_priv->rps.hw_lock);
4435                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4436                 mutex_unlock(&dev_priv->rps.hw_lock);
4437                 /* Quoting Art Runyan: "its not safe to expect any particular
4438                  * value in IPS_CTL bit 31 after enabling IPS through the
4439                  * mailbox." Moreover, the mailbox may return a bogus state,
4440                  * so we need to just enable it and continue on.
4441                  */
4442         } else {
4443                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4444                 /* The bit only becomes 1 in the next vblank, so this wait here
4445                  * is essentially intel_wait_for_vblank. If we don't have this
4446                  * and don't wait for vblanks until the end of crtc_enable, then
4447                  * the HW state readout code will complain that the expected
4448                  * IPS_CTL value is not the one we read. */
4449                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4450                         DRM_ERROR("Timed out waiting for IPS enable\n");
4451         }
4452 }
4453 
4454 void hsw_disable_ips(struct intel_crtc *crtc)
4455 {
4456         struct drm_device *dev = crtc->base.dev;
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458 
4459         if (!crtc->config->ips_enabled)
4460                 return;
4461 
4462         assert_plane_enabled(dev_priv, crtc->plane);
4463         if (IS_BROADWELL(dev)) {
4464                 mutex_lock(&dev_priv->rps.hw_lock);
4465                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4466                 mutex_unlock(&dev_priv->rps.hw_lock);
4467                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4469                         DRM_ERROR("Timed out waiting for IPS disable\n");
4470         } else {
4471                 I915_WRITE(IPS_CTL, 0);
4472                 POSTING_READ(IPS_CTL);
4473         }
4474 
4475         /* We need to wait for a vblank before we can disable the plane. */
4476         intel_wait_for_vblank(dev, crtc->pipe);
4477 }
4478 
4479 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4480 {
4481         if (intel_crtc->overlay) {
4482                 struct drm_device *dev = intel_crtc->base.dev;
4483                 struct drm_i915_private *dev_priv = dev->dev_private;
4484 
4485                 mutex_lock(&dev->struct_mutex);
4486                 dev_priv->mm.interruptible = false;
4487                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4488                 dev_priv->mm.interruptible = true;
4489                 mutex_unlock(&dev->struct_mutex);
4490         }
4491 
4492         /* Let userspace switch the overlay on again. In most cases userspace
4493          * has to recompute where to put it anyway.
4494          */
4495 }
4496 
4497 /**
4498  * intel_post_enable_primary - Perform operations after enabling primary plane
4499  * @crtc: the CRTC whose primary plane was just enabled
4500  *
4501  * Performs potentially sleeping operations that must be done after the primary
4502  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4503  * called due to an explicit primary plane update, or due to an implicit
4504  * re-enable that is caused when a sprite plane is updated to no longer
4505  * completely hide the primary plane.
4506  */
4507 static void
4508 intel_post_enable_primary(struct drm_crtc *crtc)
4509 {
4510         struct drm_device *dev = crtc->dev;
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4513         int pipe = intel_crtc->pipe;
4514 
4515         /*
4516          * FIXME IPS should be fine as long as one plane is
4517          * enabled, but in practice it seems to have problems
4518          * when going from primary only to sprite only and vice
4519          * versa.
4520          */
4521         hsw_enable_ips(intel_crtc);
4522 
4523         /*
4524          * Gen2 reports pipe underruns whenever all planes are disabled.
4525          * So don't enable underrun reporting before at least some planes
4526          * are enabled.
4527          * FIXME: Need to fix the logic to work when we turn off all planes
4528          * but leave the pipe running.
4529          */
4530         if (IS_GEN2(dev))
4531                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4532 
4533         /* Underruns don't always raise interrupts, so check manually. */
4534         intel_check_cpu_fifo_underruns(dev_priv);
4535         intel_check_pch_fifo_underruns(dev_priv);
4536 }
4537 
4538 /* FIXME move all this to pre_plane_update() with proper state tracking */
4539 static void
4540 intel_pre_disable_primary(struct drm_crtc *crtc)
4541 {
4542         struct drm_device *dev = crtc->dev;
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545         int pipe = intel_crtc->pipe;
4546 
4547         /*
4548          * Gen2 reports pipe underruns whenever all planes are disabled.
4549          * So diasble underrun reporting before all the planes get disabled.
4550          * FIXME: Need to fix the logic to work when we turn off all planes
4551          * but leave the pipe running.
4552          */
4553         if (IS_GEN2(dev))
4554                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4555 
4556         /*
4557          * FIXME IPS should be fine as long as one plane is
4558          * enabled, but in practice it seems to have problems
4559          * when going from primary only to sprite only and vice
4560          * versa.
4561          */
4562         hsw_disable_ips(intel_crtc);
4563 }
4564 
4565 /* FIXME get rid of this and use pre_plane_update */
4566 static void
4567 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4568 {
4569         struct drm_device *dev = crtc->dev;
4570         struct drm_i915_private *dev_priv = dev->dev_private;
4571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572         int pipe = intel_crtc->pipe;
4573 
4574         intel_pre_disable_primary(crtc);
4575 
4576         /*
4577          * Vblank time updates from the shadow to live plane control register
4578          * are blocked if the memory self-refresh mode is active at that
4579          * moment. So to make sure the plane gets truly disabled, disable
4580          * first the self-refresh mode. The self-refresh enable bit in turn
4581          * will be checked/applied by the HW only at the next frame start
4582          * event which is after the vblank start event, so we need to have a
4583          * wait-for-vblank between disabling the plane and the pipe.
4584          */
4585         if (HAS_GMCH_DISPLAY(dev)) {
4586                 intel_set_memory_cxsr(dev_priv, false);
4587                 dev_priv->wm.vlv.cxsr = false;
4588                 intel_wait_for_vblank(dev, pipe);
4589         }
4590 }
4591 
4592 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4593 {
4594         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4595         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4596         struct intel_crtc_state *pipe_config =
4597                 to_intel_crtc_state(crtc->base.state);
4598         struct drm_device *dev = crtc->base.dev;
4599         struct drm_plane *primary = crtc->base.primary;
4600         struct drm_plane_state *old_pri_state =
4601                 drm_atomic_get_existing_plane_state(old_state, primary);
4602 
4603         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4604 
4605         crtc->wm.cxsr_allowed = true;
4606 
4607         if (pipe_config->update_wm_post && pipe_config->base.active)
4608                 intel_update_watermarks(&crtc->base);
4609 
4610         if (old_pri_state) {
4611                 struct intel_plane_state *primary_state =
4612                         to_intel_plane_state(primary->state);
4613                 struct intel_plane_state *old_primary_state =
4614                         to_intel_plane_state(old_pri_state);
4615 
4616                 intel_fbc_post_update(crtc);
4617 
4618                 if (primary_state->visible &&
4619                     (needs_modeset(&pipe_config->base) ||
4620                      !old_primary_state->visible))
4621                         intel_post_enable_primary(&crtc->base);
4622         }
4623 }
4624 
4625 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4626 {
4627         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4628         struct drm_device *dev = crtc->base.dev;
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630         struct intel_crtc_state *pipe_config =
4631                 to_intel_crtc_state(crtc->base.state);
4632         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4633         struct drm_plane *primary = crtc->base.primary;
4634         struct drm_plane_state *old_pri_state =
4635                 drm_atomic_get_existing_plane_state(old_state, primary);
4636         bool modeset = needs_modeset(&pipe_config->base);
4637 
4638         if (old_pri_state) {
4639                 struct intel_plane_state *primary_state =
4640                         to_intel_plane_state(primary->state);
4641                 struct intel_plane_state *old_primary_state =
4642                         to_intel_plane_state(old_pri_state);
4643 
4644                 intel_fbc_pre_update(crtc);
4645 
4646                 if (old_primary_state->visible &&
4647                     (modeset || !primary_state->visible))
4648                         intel_pre_disable_primary(&crtc->base);
4649         }
4650 
4651         if (pipe_config->disable_cxsr) {
4652                 crtc->wm.cxsr_allowed = false;
4653 
4654                 /*
4655                  * Vblank time updates from the shadow to live plane control register
4656                  * are blocked if the memory self-refresh mode is active at that
4657                  * moment. So to make sure the plane gets truly disabled, disable
4658                  * first the self-refresh mode. The self-refresh enable bit in turn
4659                  * will be checked/applied by the HW only at the next frame start
4660                  * event which is after the vblank start event, so we need to have a
4661                  * wait-for-vblank between disabling the plane and the pipe.
4662                  */
4663                 if (old_crtc_state->base.active) {
4664                         intel_set_memory_cxsr(dev_priv, false);
4665                         dev_priv->wm.vlv.cxsr = false;
4666                         intel_wait_for_vblank(dev, crtc->pipe);
4667                 }
4668         }
4669 
4670         /*
4671          * IVB workaround: must disable low power watermarks for at least
4672          * one frame before enabling scaling.  LP watermarks can be re-enabled
4673          * when scaling is disabled.
4674          *
4675          * WaCxSRDisabledForSpriteScaling:ivb
4676          */
4677         if (pipe_config->disable_lp_wm) {
4678                 ilk_disable_lp_wm(dev);
4679                 intel_wait_for_vblank(dev, crtc->pipe);
4680         }
4681 
4682         /*
4683          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4684          * watermark programming here.
4685          */
4686         if (needs_modeset(&pipe_config->base))
4687                 return;
4688 
4689         /*
4690          * For platforms that support atomic watermarks, program the
4691          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4692          * will be the intermediate values that are safe for both pre- and
4693          * post- vblank; when vblank happens, the 'active' values will be set
4694          * to the final 'target' values and we'll do this again to get the
4695          * optimal watermarks.  For gen9+ platforms, the values we program here
4696          * will be the final target values which will get automatically latched
4697          * at vblank time; no further programming will be necessary.
4698          *
4699          * If a platform hasn't been transitioned to atomic watermarks yet,
4700          * we'll continue to update watermarks the old way, if flags tell
4701          * us to.
4702          */
4703         if (dev_priv->display.initial_watermarks != NULL)
4704                 dev_priv->display.initial_watermarks(pipe_config);
4705         else if (pipe_config->update_wm_pre)
4706                 intel_update_watermarks(&crtc->base);
4707 }
4708 
4709 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4710 {
4711         struct drm_device *dev = crtc->dev;
4712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713         struct drm_plane *p;
4714         int pipe = intel_crtc->pipe;
4715 
4716         intel_crtc_dpms_overlay_disable(intel_crtc);
4717 
4718         drm_for_each_plane_mask(p, dev, plane_mask)
4719                 to_intel_plane(p)->disable_plane(p, crtc);
4720 
4721         /*
4722          * FIXME: Once we grow proper nuclear flip support out of this we need
4723          * to compute the mask of flip planes precisely. For the time being
4724          * consider this a flip to a NULL plane.
4725          */
4726         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4727 }
4728 
4729 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4730 {
4731         struct drm_device *dev = crtc->dev;
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734         struct intel_encoder *encoder;
4735         int pipe = intel_crtc->pipe;
4736         struct intel_crtc_state *pipe_config =
4737                 to_intel_crtc_state(crtc->state);
4738 
4739         if (WARN_ON(intel_crtc->active))
4740                 return;
4741 
4742         /*
4743          * Sometimes spurious CPU pipe underruns happen during FDI
4744          * training, at least with VGA+HDMI cloning. Suppress them.
4745          *
4746          * On ILK we get an occasional spurious CPU pipe underruns
4747          * between eDP port A enable and vdd enable. Also PCH port
4748          * enable seems to result in the occasional CPU pipe underrun.
4749          *
4750          * Spurious PCH underruns also occur during PCH enabling.
4751          */
4752         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4753                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4754         if (intel_crtc->config->has_pch_encoder)
4755                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756 
4757         if (intel_crtc->config->has_pch_encoder)
4758                 intel_prepare_shared_dpll(intel_crtc);
4759 
4760         if (intel_crtc->config->has_dp_encoder)
4761                 intel_dp_set_m_n(intel_crtc, M1_N1);
4762 
4763         intel_set_pipe_timings(intel_crtc);
4764         intel_set_pipe_src_size(intel_crtc);
4765 
4766         if (intel_crtc->config->has_pch_encoder) {
4767                 intel_cpu_transcoder_set_m_n(intel_crtc,
4768                                      &intel_crtc->config->fdi_m_n, NULL);
4769         }
4770 
4771         ironlake_set_pipeconf(crtc);
4772 
4773         intel_crtc->active = true;
4774 
4775         for_each_encoder_on_crtc(dev, crtc, encoder)
4776                 if (encoder->pre_enable)
4777                         encoder->pre_enable(encoder);
4778 
4779         if (intel_crtc->config->has_pch_encoder) {
4780                 /* Note: FDI PLL enabling _must_ be done before we enable the
4781                  * cpu pipes, hence this is separate from all the other fdi/pch
4782                  * enabling. */
4783                 ironlake_fdi_pll_enable(intel_crtc);
4784         } else {
4785                 assert_fdi_tx_disabled(dev_priv, pipe);
4786                 assert_fdi_rx_disabled(dev_priv, pipe);
4787         }
4788 
4789         ironlake_pfit_enable(intel_crtc);
4790 
4791         /*
4792          * On ILK+ LUT must be loaded before the pipe is running but with
4793          * clocks enabled
4794          */
4795         intel_color_load_luts(&pipe_config->base);
4796 
4797         if (dev_priv->display.initial_watermarks != NULL)
4798                 dev_priv->display.initial_watermarks(intel_crtc->config);
4799         intel_enable_pipe(intel_crtc);
4800 
4801         if (intel_crtc->config->has_pch_encoder)
4802                 ironlake_pch_enable(crtc);
4803 
4804         assert_vblank_disabled(crtc);
4805         drm_crtc_vblank_on(crtc);
4806 
4807         for_each_encoder_on_crtc(dev, crtc, encoder)
4808                 encoder->enable(encoder);
4809 
4810         if (HAS_PCH_CPT(dev))
4811                 cpt_verify_modeset(dev, intel_crtc->pipe);
4812 
4813         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4814         if (intel_crtc->config->has_pch_encoder)
4815                 intel_wait_for_vblank(dev, pipe);
4816         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4817         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4818 }
4819 
4820 /* IPS only exists on ULT machines and is tied to pipe A. */
4821 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4822 {
4823         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4824 }
4825 
4826 static void haswell_crtc_enable(struct drm_crtc *crtc)
4827 {
4828         struct drm_device *dev = crtc->dev;
4829         struct drm_i915_private *dev_priv = dev->dev_private;
4830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831         struct intel_encoder *encoder;
4832         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4833         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4834         struct intel_crtc_state *pipe_config =
4835                 to_intel_crtc_state(crtc->state);
4836 
4837         if (WARN_ON(intel_crtc->active))
4838                 return;
4839 
4840         if (intel_crtc->config->has_pch_encoder)
4841                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4842                                                       false);
4843 
4844         if (intel_crtc->config->shared_dpll)
4845                 intel_enable_shared_dpll(intel_crtc);
4846 
4847         if (intel_crtc->config->has_dp_encoder)
4848                 intel_dp_set_m_n(intel_crtc, M1_N1);
4849 
4850         if (!intel_crtc->config->has_dsi_encoder)
4851                 intel_set_pipe_timings(intel_crtc);
4852 
4853         intel_set_pipe_src_size(intel_crtc);
4854 
4855         if (cpu_transcoder != TRANSCODER_EDP &&
4856             !transcoder_is_dsi(cpu_transcoder)) {
4857                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4858                            intel_crtc->config->pixel_multiplier - 1);
4859         }
4860 
4861         if (intel_crtc->config->has_pch_encoder) {
4862                 intel_cpu_transcoder_set_m_n(intel_crtc,
4863                                      &intel_crtc->config->fdi_m_n, NULL);
4864         }
4865 
4866         if (!intel_crtc->config->has_dsi_encoder)
4867                 haswell_set_pipeconf(crtc);
4868 
4869         haswell_set_pipemisc(crtc);
4870 
4871         intel_color_set_csc(&pipe_config->base);
4872 
4873         intel_crtc->active = true;
4874 
4875         if (intel_crtc->config->has_pch_encoder)
4876                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4877         else
4878                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4879 
4880         for_each_encoder_on_crtc(dev, crtc, encoder) {
4881                 if (encoder->pre_enable)
4882                         encoder->pre_enable(encoder);
4883         }
4884 
4885         if (intel_crtc->config->has_pch_encoder)
4886                 dev_priv->display.fdi_link_train(crtc);
4887 
4888         if (!intel_crtc->config->has_dsi_encoder)
4889                 intel_ddi_enable_pipe_clock(intel_crtc);
4890 
4891         if (INTEL_INFO(dev)->gen >= 9)
4892                 skylake_pfit_enable(intel_crtc);
4893         else
4894                 ironlake_pfit_enable(intel_crtc);
4895 
4896         /*
4897          * On ILK+ LUT must be loaded before the pipe is running but with
4898          * clocks enabled
4899          */
4900         intel_color_load_luts(&pipe_config->base);
4901 
4902         intel_ddi_set_pipe_settings(crtc);
4903         if (!intel_crtc->config->has_dsi_encoder)
4904                 intel_ddi_enable_transcoder_func(crtc);
4905 
4906         if (dev_priv->display.initial_watermarks != NULL)
4907                 dev_priv->display.initial_watermarks(pipe_config);
4908         else
4909                 intel_update_watermarks(crtc);
4910 
4911         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4912         if (!intel_crtc->config->has_dsi_encoder)
4913                 intel_enable_pipe(intel_crtc);
4914 
4915         if (intel_crtc->config->has_pch_encoder)
4916                 lpt_pch_enable(crtc);
4917 
4918         if (intel_crtc->config->dp_encoder_is_mst)
4919                 intel_ddi_set_vc_payload_alloc(crtc, true);
4920 
4921         assert_vblank_disabled(crtc);
4922         drm_crtc_vblank_on(crtc);
4923 
4924         for_each_encoder_on_crtc(dev, crtc, encoder) {
4925                 encoder->enable(encoder);
4926                 intel_opregion_notify_encoder(encoder, true);
4927         }
4928 
4929         if (intel_crtc->config->has_pch_encoder) {
4930                 intel_wait_for_vblank(dev, pipe);
4931                 intel_wait_for_vblank(dev, pipe);
4932                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4933                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4934                                                       true);
4935         }
4936 
4937         /* If we change the relative order between pipe/planes enabling, we need
4938          * to change the workaround. */
4939         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4940         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4941                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4942                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4943         }
4944 }
4945 
4946 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4947 {
4948         struct drm_device *dev = crtc->base.dev;
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         int pipe = crtc->pipe;
4951 
4952         /* To avoid upsetting the power well on haswell only disable the pfit if
4953          * it's in use. The hw state code will make sure we get this right. */
4954         if (force || crtc->config->pch_pfit.enabled) {
4955                 I915_WRITE(PF_CTL(pipe), 0);
4956                 I915_WRITE(PF_WIN_POS(pipe), 0);
4957                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4958         }
4959 }
4960 
4961 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4962 {
4963         struct drm_device *dev = crtc->dev;
4964         struct drm_i915_private *dev_priv = dev->dev_private;
4965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966         struct intel_encoder *encoder;
4967         int pipe = intel_crtc->pipe;
4968 
4969         /*
4970          * Sometimes spurious CPU pipe underruns happen when the
4971          * pipe is already disabled, but FDI RX/TX is still enabled.
4972          * Happens at least with VGA+HDMI cloning. Suppress them.
4973          */
4974         if (intel_crtc->config->has_pch_encoder) {
4975                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4976                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4977         }
4978 
4979         for_each_encoder_on_crtc(dev, crtc, encoder)
4980                 encoder->disable(encoder);
4981 
4982         drm_crtc_vblank_off(crtc);
4983         assert_vblank_disabled(crtc);
4984 
4985         intel_disable_pipe(intel_crtc);
4986 
4987         ironlake_pfit_disable(intel_crtc, false);
4988 
4989         if (intel_crtc->config->has_pch_encoder)
4990                 ironlake_fdi_disable(crtc);
4991 
4992         for_each_encoder_on_crtc(dev, crtc, encoder)
4993                 if (encoder->post_disable)
4994                         encoder->post_disable(encoder);
4995 
4996         if (intel_crtc->config->has_pch_encoder) {
4997                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4998 
4999                 if (HAS_PCH_CPT(dev)) {
5000                         i915_reg_t reg;
5001                         u32 temp;
5002 
5003                         /* disable TRANS_DP_CTL */
5004                         reg = TRANS_DP_CTL(pipe);
5005                         temp = I915_READ(reg);
5006                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5007                                   TRANS_DP_PORT_SEL_MASK);
5008                         temp |= TRANS_DP_PORT_SEL_NONE;
5009                         I915_WRITE(reg, temp);
5010 
5011                         /* disable DPLL_SEL */
5012                         temp = I915_READ(PCH_DPLL_SEL);
5013                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5014                         I915_WRITE(PCH_DPLL_SEL, temp);
5015                 }
5016 
5017                 ironlake_fdi_pll_disable(intel_crtc);
5018         }
5019 
5020         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5021         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5022 }
5023 
5024 static void haswell_crtc_disable(struct drm_crtc *crtc)
5025 {
5026         struct drm_device *dev = crtc->dev;
5027         struct drm_i915_private *dev_priv = dev->dev_private;
5028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5029         struct intel_encoder *encoder;
5030         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5031 
5032         if (intel_crtc->config->has_pch_encoder)
5033                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034                                                       false);
5035 
5036         for_each_encoder_on_crtc(dev, crtc, encoder) {
5037                 intel_opregion_notify_encoder(encoder, false);
5038                 encoder->disable(encoder);
5039         }
5040 
5041         drm_crtc_vblank_off(crtc);
5042         assert_vblank_disabled(crtc);
5043 
5044         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5045         if (!intel_crtc->config->has_dsi_encoder)
5046                 intel_disable_pipe(intel_crtc);
5047 
5048         if (intel_crtc->config->dp_encoder_is_mst)
5049                 intel_ddi_set_vc_payload_alloc(crtc, false);
5050 
5051         if (!intel_crtc->config->has_dsi_encoder)
5052                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5053 
5054         if (INTEL_INFO(dev)->gen >= 9)
5055                 skylake_scaler_disable(intel_crtc);
5056         else
5057                 ironlake_pfit_disable(intel_crtc, false);
5058 
5059         if (!intel_crtc->config->has_dsi_encoder)
5060                 intel_ddi_disable_pipe_clock(intel_crtc);
5061 
5062         for_each_encoder_on_crtc(dev, crtc, encoder)
5063                 if (encoder->post_disable)
5064                         encoder->post_disable(encoder);
5065 
5066         if (intel_crtc->config->has_pch_encoder) {
5067                 lpt_disable_pch_transcoder(dev_priv);
5068                 lpt_disable_iclkip(dev_priv);
5069                 intel_ddi_fdi_disable(crtc);
5070 
5071                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5072                                                       true);
5073         }
5074 }
5075 
5076 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->base.dev;
5079         struct drm_i915_private *dev_priv = dev->dev_private;
5080         struct intel_crtc_state *pipe_config = crtc->config;
5081 
5082         if (!pipe_config->gmch_pfit.control)
5083                 return;
5084 
5085         /*
5086          * The panel fitter should only be adjusted whilst the pipe is disabled,
5087          * according to register description and PRM.
5088          */
5089         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5090         assert_pipe_disabled(dev_priv, crtc->pipe);
5091 
5092         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5093         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5094 
5095         /* Border color in case we don't scale up to the full screen. Black by
5096          * default, change to something else for debugging. */
5097         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5098 }
5099 
5100 static enum intel_display_power_domain port_to_power_domain(enum port port)
5101 {
5102         switch (port) {
5103         case PORT_A:
5104                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5105         case PORT_B:
5106                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5107         case PORT_C:
5108                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5109         case PORT_D:
5110                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5111         case PORT_E:
5112                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5113         default:
5114                 MISSING_CASE(port);
5115                 return POWER_DOMAIN_PORT_OTHER;
5116         }
5117 }
5118 
5119 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5120 {
5121         switch (port) {
5122         case PORT_A:
5123                 return POWER_DOMAIN_AUX_A;
5124         case PORT_B:
5125                 return POWER_DOMAIN_AUX_B;
5126         case PORT_C:
5127                 return POWER_DOMAIN_AUX_C;
5128         case PORT_D:
5129                 return POWER_DOMAIN_AUX_D;
5130         case PORT_E:
5131                 /* FIXME: Check VBT for actual wiring of PORT E */
5132                 return POWER_DOMAIN_AUX_D;
5133         default:
5134                 MISSING_CASE(port);
5135                 return POWER_DOMAIN_AUX_A;
5136         }
5137 }
5138 
5139 enum intel_display_power_domain
5140 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5141 {
5142         struct drm_device *dev = intel_encoder->base.dev;
5143         struct intel_digital_port *intel_dig_port;
5144 
5145         switch (intel_encoder->type) {
5146         case INTEL_OUTPUT_UNKNOWN:
5147                 /* Only DDI platforms should ever use this output type */
5148                 WARN_ON_ONCE(!HAS_DDI(dev));
5149         case INTEL_OUTPUT_DISPLAYPORT:
5150         case INTEL_OUTPUT_HDMI:
5151         case INTEL_OUTPUT_EDP:
5152                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5153                 return port_to_power_domain(intel_dig_port->port);
5154         case INTEL_OUTPUT_DP_MST:
5155                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5156                 return port_to_power_domain(intel_dig_port->port);
5157         case INTEL_OUTPUT_ANALOG:
5158                 return POWER_DOMAIN_PORT_CRT;
5159         case INTEL_OUTPUT_DSI:
5160                 return POWER_DOMAIN_PORT_DSI;
5161         default:
5162                 return POWER_DOMAIN_PORT_OTHER;
5163         }
5164 }
5165 
5166 enum intel_display_power_domain
5167 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5168 {
5169         struct drm_device *dev = intel_encoder->base.dev;
5170         struct intel_digital_port *intel_dig_port;
5171 
5172         switch (intel_encoder->type) {
5173         case INTEL_OUTPUT_UNKNOWN:
5174         case INTEL_OUTPUT_HDMI:
5175                 /*
5176                  * Only DDI platforms should ever use these output types.
5177                  * We can get here after the HDMI detect code has already set
5178                  * the type of the shared encoder. Since we can't be sure
5179                  * what's the status of the given connectors, play safe and
5180                  * run the DP detection too.
5181                  */
5182                 WARN_ON_ONCE(!HAS_DDI(dev));
5183         case INTEL_OUTPUT_DISPLAYPORT:
5184         case INTEL_OUTPUT_EDP:
5185                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5186                 return port_to_aux_power_domain(intel_dig_port->port);
5187         case INTEL_OUTPUT_DP_MST:
5188                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5189                 return port_to_aux_power_domain(intel_dig_port->port);
5190         default:
5191                 MISSING_CASE(intel_encoder->type);
5192                 return POWER_DOMAIN_AUX_A;
5193         }
5194 }
5195 
5196 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5197                                             struct intel_crtc_state *crtc_state)
5198 {
5199         struct drm_device *dev = crtc->dev;
5200         struct drm_encoder *encoder;
5201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202         enum pipe pipe = intel_crtc->pipe;
5203         unsigned long mask;
5204         enum transcoder transcoder = crtc_state->cpu_transcoder;
5205 
5206         if (!crtc_state->base.active)
5207                 return 0;
5208 
5209         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5210         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5211         if (crtc_state->pch_pfit.enabled ||
5212             crtc_state->pch_pfit.force_thru)
5213                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5214 
5215         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5216                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5217 
5218                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5219         }
5220 
5221         if (crtc_state->shared_dpll)
5222                 mask |= BIT(POWER_DOMAIN_PLLS);
5223 
5224         return mask;
5225 }
5226 
5227 static unsigned long
5228 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5229                                struct intel_crtc_state *crtc_state)
5230 {
5231         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233         enum intel_display_power_domain domain;
5234         unsigned long domains, new_domains, old_domains;
5235 
5236         old_domains = intel_crtc->enabled_power_domains;
5237         intel_crtc->enabled_power_domains = new_domains =
5238                 get_crtc_power_domains(crtc, crtc_state);
5239 
5240         domains = new_domains & ~old_domains;
5241 
5242         for_each_power_domain(domain, domains)
5243                 intel_display_power_get(dev_priv, domain);
5244 
5245         return old_domains & ~new_domains;
5246 }
5247 
5248 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5249                                       unsigned long domains)
5250 {
5251         enum intel_display_power_domain domain;
5252 
5253         for_each_power_domain(domain, domains)
5254                 intel_display_power_put(dev_priv, domain);
5255 }
5256 
5257 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5258 {
5259         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5260 
5261         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5262             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5263                 return max_cdclk_freq;
5264         else if (IS_CHERRYVIEW(dev_priv))
5265                 return max_cdclk_freq*95/100;
5266         else if (INTEL_INFO(dev_priv)->gen < 4)
5267                 return 2*max_cdclk_freq*90/100;
5268         else
5269                 return max_cdclk_freq*90/100;
5270 }
5271 
5272 static void intel_update_max_cdclk(struct drm_device *dev)
5273 {
5274         struct drm_i915_private *dev_priv = dev->dev_private;
5275 
5276         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5277                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5278 
5279                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5280                         dev_priv->max_cdclk_freq = 675000;
5281                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5282                         dev_priv->max_cdclk_freq = 540000;
5283                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5284                         dev_priv->max_cdclk_freq = 450000;
5285                 else
5286                         dev_priv->max_cdclk_freq = 337500;
5287         } else if (IS_BROXTON(dev)) {
5288                 dev_priv->max_cdclk_freq = 624000;
5289         } else if (IS_BROADWELL(dev))  {
5290                 /*
5291                  * FIXME with extra cooling we can allow
5292                  * 540 MHz for ULX and 675 Mhz for ULT.
5293                  * How can we know if extra cooling is
5294                  * available? PCI ID, VTB, something else?
5295                  */
5296                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5297                         dev_priv->max_cdclk_freq = 450000;
5298                 else if (IS_BDW_ULX(dev))
5299                         dev_priv->max_cdclk_freq = 450000;
5300                 else if (IS_BDW_ULT(dev))
5301                         dev_priv->max_cdclk_freq = 540000;
5302                 else
5303                         dev_priv->max_cdclk_freq = 675000;
5304         } else if (IS_CHERRYVIEW(dev)) {
5305                 dev_priv->max_cdclk_freq = 320000;
5306         } else if (IS_VALLEYVIEW(dev)) {
5307                 dev_priv->max_cdclk_freq = 400000;
5308         } else {
5309                 /* otherwise assume cdclk is fixed */
5310                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5311         }
5312 
5313         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5314 
5315         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5316                          dev_priv->max_cdclk_freq);
5317 
5318         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5319                          dev_priv->max_dotclk_freq);
5320 }
5321 
5322 static void intel_update_cdclk(struct drm_device *dev)
5323 {
5324         struct drm_i915_private *dev_priv = dev->dev_private;
5325 
5326         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5327         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5328                          dev_priv->cdclk_freq);
5329 
5330         /*
5331          * Program the gmbus_freq based on the cdclk frequency.
5332          * BSpec erroneously claims we should aim for 4MHz, but
5333          * in fact 1MHz is the correct frequency.
5334          */
5335         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5336                 /*
5337                  * Program the gmbus_freq based on the cdclk frequency.
5338                  * BSpec erroneously claims we should aim for 4MHz, but
5339                  * in fact 1MHz is the correct frequency.
5340                  */
5341                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5342         }
5343 
5344         if (dev_priv->max_cdclk_freq == 0)
5345                 intel_update_max_cdclk(dev);
5346 }
5347 
5348 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5349 {
5350         uint32_t divider;
5351         uint32_t ratio;
5352         uint32_t current_freq;
5353         int ret;
5354 
5355         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5356         switch (frequency) {
5357         case 144000:
5358                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5359                 ratio = BXT_DE_PLL_RATIO(60);
5360                 break;
5361         case 288000:
5362                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5363                 ratio = BXT_DE_PLL_RATIO(60);
5364                 break;
5365         case 384000:
5366                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5367                 ratio = BXT_DE_PLL_RATIO(60);
5368                 break;
5369         case 576000:
5370                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371                 ratio = BXT_DE_PLL_RATIO(60);
5372                 break;
5373         case 624000:
5374                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375                 ratio = BXT_DE_PLL_RATIO(65);
5376                 break;
5377         case 19200:
5378                 /*
5379                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5380                  * to suppress GCC warning.
5381                  */
5382                 ratio = 0;
5383                 divider = 0;
5384                 break;
5385         default:
5386                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5387 
5388                 return;
5389         }
5390 
5391         mutex_lock(&dev_priv->rps.hw_lock);
5392         /* Inform power controller of upcoming frequency change */
5393         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5394                                       0x80000000);
5395         mutex_unlock(&dev_priv->rps.hw_lock);
5396 
5397         if (ret) {
5398                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5399                           ret, frequency);
5400                 return;
5401         }
5402 
5403         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5404         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5405         current_freq = current_freq * 500 + 1000;
5406 
5407         /*
5408          * DE PLL has to be disabled when
5409          * - setting to 19.2MHz (bypass, PLL isn't used)
5410          * - before setting to 624MHz (PLL needs toggling)
5411          * - before setting to any frequency from 624MHz (PLL needs toggling)
5412          */
5413         if (frequency == 19200 || frequency == 624000 ||
5414             current_freq == 624000) {
5415                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5416                 /* Timeout 200us */
5417                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5418                              1))
5419                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5420         }
5421 
5422         if (frequency != 19200) {
5423                 uint32_t val;
5424 
5425                 val = I915_READ(BXT_DE_PLL_CTL);
5426                 val &= ~BXT_DE_PLL_RATIO_MASK;
5427                 val |= ratio;
5428                 I915_WRITE(BXT_DE_PLL_CTL, val);
5429 
5430                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5431                 /* Timeout 200us */
5432                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5433                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5434 
5435                 val = I915_READ(CDCLK_CTL);
5436                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5437                 val |= divider;
5438                 /*
5439                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5440                  * enable otherwise.
5441                  */
5442                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5443                 if (frequency >= 500000)
5444                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 
5446                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5447                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5448                 val |= (frequency - 1000) / 500;
5449                 I915_WRITE(CDCLK_CTL, val);
5450         }
5451 
5452         mutex_lock(&dev_priv->rps.hw_lock);
5453         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5454                                       DIV_ROUND_UP(frequency, 25000));
5455         mutex_unlock(&dev_priv->rps.hw_lock);
5456 
5457         if (ret) {
5458                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5459                           ret, frequency);
5460                 return;
5461         }
5462 
5463         intel_update_cdclk(dev_priv->dev);
5464 }
5465 
5466 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5467 {
5468         if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5469                 return false;
5470 
5471         /* TODO: Check for a valid CDCLK rate */
5472 
5473         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5474                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5475 
5476                 return false;
5477         }
5478 
5479         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5480                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5481 
5482                 return false;
5483         }
5484 
5485         return true;
5486 }
5487 
5488 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5489 {
5490         return broxton_cdclk_is_enabled(dev_priv);
5491 }
5492 
5493 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5494 {
5495         /* check if cd clock is enabled */
5496         if (broxton_cdclk_is_enabled(dev_priv)) {
5497                 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5498                 return;
5499         }
5500 
5501         DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5502 
5503         /*
5504          * FIXME:
5505          * - The initial CDCLK needs to be read from VBT.
5506          *   Need to make this change after VBT has changes for BXT.
5507          * - check if setting the max (or any) cdclk freq is really necessary
5508          *   here, it belongs to modeset time
5509          */
5510         broxton_set_cdclk(dev_priv, 624000);
5511 
5512         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5513         POSTING_READ(DBUF_CTL);
5514 
5515         udelay(10);
5516 
5517         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5518                 DRM_ERROR("DBuf power enable timeout!\n");
5519 }
5520 
5521 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5522 {
5523         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5524         POSTING_READ(DBUF_CTL);
5525 
5526         udelay(10);
5527 
5528         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5529                 DRM_ERROR("DBuf power disable timeout!\n");
5530 
5531         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5532         broxton_set_cdclk(dev_priv, 19200);
5533 }
5534 
5535 static const struct skl_cdclk_entry {
5536         unsigned int freq;
5537         unsigned int vco;
5538 } skl_cdclk_frequencies[] = {
5539         { .freq = 308570, .vco = 8640 },
5540         { .freq = 337500, .vco = 8100 },
5541         { .freq = 432000, .vco = 8640 },
5542         { .freq = 450000, .vco = 8100 },
5543         { .freq = 540000, .vco = 8100 },
5544         { .freq = 617140, .vco = 8640 },
5545         { .freq = 675000, .vco = 8100 },
5546 };
5547 
5548 static unsigned int skl_cdclk_decimal(unsigned int freq)
5549 {
5550         return (freq - 1000) / 500;
5551 }
5552 
5553 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5554 {
5555         unsigned int i;
5556 
5557         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5558                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5559 
5560                 if (e->freq == freq)
5561                         return e->vco;
5562         }
5563 
5564         return 8100;
5565 }
5566 
5567 static void
5568 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5569 {
5570         unsigned int min_freq;
5571         u32 val;
5572 
5573         /* select the minimum CDCLK before enabling DPLL 0 */
5574         val = I915_READ(CDCLK_CTL);
5575         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5576         val |= CDCLK_FREQ_337_308;
5577 
5578         if (required_vco == 8640)
5579                 min_freq = 308570;
5580         else
5581                 min_freq = 337500;
5582 
5583         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5584 
5585         I915_WRITE(CDCLK_CTL, val);
5586         POSTING_READ(CDCLK_CTL);
5587 
5588         /*
5589          * We always enable DPLL0 with the lowest link rate possible, but still
5590          * taking into account the VCO required to operate the eDP panel at the
5591          * desired frequency. The usual DP link rates operate with a VCO of
5592          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5593          * The modeset code is responsible for the selection of the exact link
5594          * rate later on, with the constraint of choosing a frequency that
5595          * works with required_vco.
5596          */
5597         val = I915_READ(DPLL_CTRL1);
5598 
5599         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5600                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5601         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5602         if (required_vco == 8640)
5603                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5604                                             SKL_DPLL0);
5605         else
5606                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5607                                             SKL_DPLL0);
5608 
5609         I915_WRITE(DPLL_CTRL1, val);
5610         POSTING_READ(DPLL_CTRL1);
5611 
5612         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5613 
5614         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5615                 DRM_ERROR("DPLL0 not locked\n");
5616 }
5617 
5618 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5619 {
5620         int ret;
5621         u32 val;
5622 
5623         /* inform PCU we want to change CDCLK */
5624         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5625         mutex_lock(&dev_priv->rps.hw_lock);
5626         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5627         mutex_unlock(&dev_priv->rps.hw_lock);
5628 
5629         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5630 }
5631 
5632 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5633 {
5634         unsigned int i;
5635 
5636         for (i = 0; i < 15; i++) {
5637                 if (skl_cdclk_pcu_ready(dev_priv))
5638                         return true;
5639                 udelay(10);
5640         }
5641 
5642         return false;
5643 }
5644 
5645 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5646 {
5647         struct drm_device *dev = dev_priv->dev;
5648         u32 freq_select, pcu_ack;
5649 
5650         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5651 
5652         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5653                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5654                 return;
5655         }
5656 
5657         /* set CDCLK_CTL */
5658         switch(freq) {
5659         case 450000:
5660         case 432000:
5661                 freq_select = CDCLK_FREQ_450_432;
5662                 pcu_ack = 1;
5663                 break;
5664         case 540000:
5665                 freq_select = CDCLK_FREQ_540;
5666                 pcu_ack = 2;
5667                 break;
5668         case 308570:
5669         case 337500:
5670         default:
5671                 freq_select = CDCLK_FREQ_337_308;
5672                 pcu_ack = 0;
5673                 break;
5674         case 617140:
5675         case 675000:
5676                 freq_select = CDCLK_FREQ_675_617;
5677                 pcu_ack = 3;
5678                 break;
5679         }
5680 
5681         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5682         POSTING_READ(CDCLK_CTL);
5683 
5684         /* inform PCU of the change */
5685         mutex_lock(&dev_priv->rps.hw_lock);
5686         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5687         mutex_unlock(&dev_priv->rps.hw_lock);
5688 
5689         intel_update_cdclk(dev);
5690 }
5691 
5692 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5693 {
5694         /* disable DBUF power */
5695         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5696         POSTING_READ(DBUF_CTL);
5697 
5698         udelay(10);
5699 
5700         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5701                 DRM_ERROR("DBuf power disable timeout\n");
5702 
5703         /* disable DPLL0 */
5704         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5705         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5706                 DRM_ERROR("Couldn't disable DPLL0\n");
5707 }
5708 
5709 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5710 {
5711         unsigned int required_vco;
5712 
5713         /* DPLL0 not enabled (happens on early BIOS versions) */
5714         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5715                 /* enable DPLL0 */
5716                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5717                 skl_dpll0_enable(dev_priv, required_vco);
5718         }
5719 
5720         /* set CDCLK to the frequency the BIOS chose */
5721         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5722 
5723         /* enable DBUF power */
5724         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5725         POSTING_READ(DBUF_CTL);
5726 
5727         udelay(10);
5728 
5729         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5730                 DRM_ERROR("DBuf power enable timeout\n");
5731 }
5732 
5733 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5734 {
5735         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5736         uint32_t cdctl = I915_READ(CDCLK_CTL);
5737         int freq = dev_priv->skl_boot_cdclk;
5738 
5739         /*
5740          * check if the pre-os intialized the display
5741          * There is SWF18 scratchpad register defined which is set by the
5742          * pre-os which can be used by the OS drivers to check the status
5743          */
5744         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5745                 goto sanitize;
5746 
5747         /* Is PLL enabled and locked ? */
5748         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5749                 goto sanitize;
5750 
5751         /* DPLL okay; verify the cdclock
5752          *
5753          * Noticed in some instances that the freq selection is correct but
5754          * decimal part is programmed wrong from BIOS where pre-os does not
5755          * enable display. Verify the same as well.
5756          */
5757         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5758                 /* All well; nothing to sanitize */
5759                 return false;
5760 sanitize:
5761         /*
5762          * As of now initialize with max cdclk till
5763          * we get dynamic cdclk support
5764          * */
5765         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5766         skl_init_cdclk(dev_priv);
5767 
5768         /* we did have to sanitize */
5769         return true;
5770 }
5771 
5772 /* Adjust CDclk dividers to allow high res or save power if possible */
5773 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5774 {
5775         struct drm_i915_private *dev_priv = dev->dev_private;
5776         u32 val, cmd;
5777 
5778         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5779                                         != dev_priv->cdclk_freq);
5780 
5781         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5782                 cmd = 2;
5783         else if (cdclk == 266667)
5784                 cmd = 1;
5785         else
5786                 cmd = 0;
5787 
5788         mutex_lock(&dev_priv->rps.hw_lock);
5789         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5790         val &= ~DSPFREQGUAR_MASK;
5791         val |= (cmd << DSPFREQGUAR_SHIFT);
5792         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5793         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5794                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5795                      50)) {
5796                 DRM_ERROR("timed out waiting for CDclk change\n");
5797         }
5798         mutex_unlock(&dev_priv->rps.hw_lock);
5799 
5800         mutex_lock(&dev_priv->sb_lock);
5801 
5802         if (cdclk == 400000) {
5803                 u32 divider;
5804 
5805                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5806 
5807                 /* adjust cdclk divider */
5808                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5809                 val &= ~CCK_FREQUENCY_VALUES;
5810                 val |= divider;
5811                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5812 
5813                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5814                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5815                              50))
5816                         DRM_ERROR("timed out waiting for CDclk change\n");
5817         }
5818 
5819         /* adjust self-refresh exit latency value */
5820         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5821         val &= ~0x7f;
5822 
5823         /*
5824          * For high bandwidth configs, we set a higher latency in the bunit
5825          * so that the core display fetch happens in time to avoid underruns.
5826          */
5827         if (cdclk == 400000)
5828                 val |= 4500 / 250; /* 4.5 usec */
5829         else
5830                 val |= 3000 / 250; /* 3.0 usec */
5831         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5832 
5833         mutex_unlock(&dev_priv->sb_lock);
5834 
5835         intel_update_cdclk(dev);
5836 }
5837 
5838 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5839 {
5840         struct drm_i915_private *dev_priv = dev->dev_private;
5841         u32 val, cmd;
5842 
5843         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5844                                                 != dev_priv->cdclk_freq);
5845 
5846         switch (cdclk) {
5847         case 333333:
5848         case 320000:
5849         case 266667:
5850         case 200000:
5851                 break;
5852         default:
5853                 MISSING_CASE(cdclk);
5854                 return;
5855         }
5856 
5857         /*
5858          * Specs are full of misinformation, but testing on actual
5859          * hardware has shown that we just need to write the desired
5860          * CCK divider into the Punit register.
5861          */
5862         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5863 
5864         mutex_lock(&dev_priv->rps.hw_lock);
5865         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5866         val &= ~DSPFREQGUAR_MASK_CHV;
5867         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5868         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5869         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5870                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5871                      50)) {
5872                 DRM_ERROR("timed out waiting for CDclk change\n");
5873         }
5874         mutex_unlock(&dev_priv->rps.hw_lock);
5875 
5876         intel_update_cdclk(dev);
5877 }
5878 
5879 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5880                                  int max_pixclk)
5881 {
5882         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5883         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5884 
5885         /*
5886          * Really only a few cases to deal with, as only 4 CDclks are supported:
5887          *   200MHz
5888          *   267MHz
5889          *   320/333MHz (depends on HPLL freq)
5890          *   400MHz (VLV only)
5891          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5892          * of the lower bin and adjust if needed.
5893          *
5894          * We seem to get an unstable or solid color picture at 200MHz.
5895          * Not sure what's wrong. For now use 200MHz only when all pipes
5896          * are off.
5897          */
5898         if (!IS_CHERRYVIEW(dev_priv) &&
5899             max_pixclk > freq_320*limit/100)
5900                 return 400000;
5901         else if (max_pixclk > 266667*limit/100)
5902                 return freq_320;
5903         else if (max_pixclk > 0)
5904                 return 266667;
5905         else
5906                 return 200000;
5907 }
5908 
5909 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5910                               int max_pixclk)
5911 {
5912         /*
5913          * FIXME:
5914          * - remove the guardband, it's not needed on BXT
5915          * - set 19.2MHz bypass frequency if there are no active pipes
5916          */
5917         if (max_pixclk > 576000*9/10)
5918                 return 624000;
5919         else if (max_pixclk > 384000*9/10)
5920                 return 576000;
5921         else if (max_pixclk > 288000*9/10)
5922                 return 384000;
5923         else if (max_pixclk > 144000*9/10)
5924                 return 288000;
5925         else
5926                 return 144000;
5927 }
5928 
5929 /* Compute the max pixel clock for new configuration. */
5930 static int intel_mode_max_pixclk(struct drm_device *dev,
5931                                  struct drm_atomic_state *state)
5932 {
5933         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5934         struct drm_i915_private *dev_priv = dev->dev_private;
5935         struct drm_crtc *crtc;
5936         struct drm_crtc_state *crtc_state;
5937         unsigned max_pixclk = 0, i;
5938         enum pipe pipe;
5939 
5940         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5941                sizeof(intel_state->min_pixclk));
5942 
5943         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5944                 int pixclk = 0;
5945 
5946                 if (crtc_state->enable)
5947                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5948 
5949                 intel_state->min_pixclk[i] = pixclk;
5950         }
5951 
5952         for_each_pipe(dev_priv, pipe)
5953                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5954 
5955         return max_pixclk;
5956 }
5957 
5958 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5959 {
5960         struct drm_device *dev = state->dev;
5961         struct drm_i915_private *dev_priv = dev->dev_private;
5962         int max_pixclk = intel_mode_max_pixclk(dev, state);
5963         struct intel_atomic_state *intel_state =
5964                 to_intel_atomic_state(state);
5965 
5966         if (max_pixclk < 0)
5967                 return max_pixclk;
5968 
5969         intel_state->cdclk = intel_state->dev_cdclk =
5970                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5971 
5972         if (!intel_state->active_crtcs)
5973                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5974 
5975         return 0;
5976 }
5977 
5978 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5979 {
5980         struct drm_device *dev = state->dev;
5981         struct drm_i915_private *dev_priv = dev->dev_private;
5982         int max_pixclk = intel_mode_max_pixclk(dev, state);
5983         struct intel_atomic_state *intel_state =
5984                 to_intel_atomic_state(state);
5985 
5986         if (max_pixclk < 0)
5987                 return max_pixclk;
5988 
5989         intel_state->cdclk = intel_state->dev_cdclk =
5990                 broxton_calc_cdclk(dev_priv, max_pixclk);
5991 
5992         if (!intel_state->active_crtcs)
5993                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5994 
5995         return 0;
5996 }
5997 
5998 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5999 {
6000         unsigned int credits, default_credits;
6001 
6002         if (IS_CHERRYVIEW(dev_priv))
6003                 default_credits = PFI_CREDIT(12);
6004         else
6005                 default_credits = PFI_CREDIT(8);
6006 
6007         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6008                 /* CHV suggested value is 31 or 63 */
6009                 if (IS_CHERRYVIEW(dev_priv))
6010                         credits = PFI_CREDIT_63;
6011                 else
6012                         credits = PFI_CREDIT(15);
6013         } else {
6014                 credits = default_credits;
6015         }
6016 
6017         /*
6018          * WA - write default credits before re-programming
6019          * FIXME: should we also set the resend bit here?
6020          */
6021         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6022                    default_credits);
6023 
6024         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6025                    credits | PFI_CREDIT_RESEND);
6026 
6027         /*
6028          * FIXME is this guaranteed to clear
6029          * immediately or should we poll for it?
6030          */
6031         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6032 }
6033 
6034 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6035 {
6036         struct drm_device *dev = old_state->dev;
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         struct intel_atomic_state *old_intel_state =
6039                 to_intel_atomic_state(old_state);
6040         unsigned req_cdclk = old_intel_state->dev_cdclk;
6041 
6042         /*
6043          * FIXME: We can end up here with all power domains off, yet
6044          * with a CDCLK frequency other than the minimum. To account
6045          * for this take the PIPE-A power domain, which covers the HW
6046          * blocks needed for the following programming. This can be
6047          * removed once it's guaranteed that we get here either with
6048          * the minimum CDCLK set, or the required power domains
6049          * enabled.
6050          */
6051         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6052 
6053         if (IS_CHERRYVIEW(dev))
6054                 cherryview_set_cdclk(dev, req_cdclk);
6055         else
6056                 valleyview_set_cdclk(dev, req_cdclk);
6057 
6058         vlv_program_pfi_credits(dev_priv);
6059 
6060         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6061 }
6062 
6063 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6064 {
6065         struct drm_device *dev = crtc->dev;
6066         struct drm_i915_private *dev_priv = to_i915(dev);
6067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6068         struct intel_encoder *encoder;
6069         struct intel_crtc_state *pipe_config =
6070                 to_intel_crtc_state(crtc->state);
6071         int pipe = intel_crtc->pipe;
6072 
6073         if (WARN_ON(intel_crtc->active))
6074                 return;
6075 
6076         if (intel_crtc->config->has_dp_encoder)
6077                 intel_dp_set_m_n(intel_crtc, M1_N1);
6078 
6079         intel_set_pipe_timings(intel_crtc);
6080         intel_set_pipe_src_size(intel_crtc);
6081 
6082         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6083                 struct drm_i915_private *dev_priv = dev->dev_private;
6084 
6085                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6086                 I915_WRITE(CHV_CANVAS(pipe), 0);
6087         }
6088 
6089         i9xx_set_pipeconf(intel_crtc);
6090 
6091         intel_crtc->active = true;
6092 
6093         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6094 
6095         for_each_encoder_on_crtc(dev, crtc, encoder)
6096                 if (encoder->pre_pll_enable)
6097                         encoder->pre_pll_enable(encoder);
6098 
6099         if (IS_CHERRYVIEW(dev)) {
6100                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6101                 chv_enable_pll(intel_crtc, intel_crtc->config);
6102         } else {
6103                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6104                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6105         }
6106 
6107         for_each_encoder_on_crtc(dev, crtc, encoder)
6108                 if (encoder->pre_enable)
6109                         encoder->pre_enable(encoder);
6110 
6111         i9xx_pfit_enable(intel_crtc);
6112 
6113         intel_color_load_luts(&pipe_config->base);
6114 
6115         intel_update_watermarks(crtc);
6116         intel_enable_pipe(intel_crtc);
6117 
6118         assert_vblank_disabled(crtc);
6119         drm_crtc_vblank_on(crtc);
6120 
6121         for_each_encoder_on_crtc(dev, crtc, encoder)
6122                 encoder->enable(encoder);
6123 }
6124 
6125 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6126 {
6127         struct drm_device *dev = crtc->base.dev;
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129 
6130         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6131         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6132 }
6133 
6134 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6135 {
6136         struct drm_device *dev = crtc->dev;
6137         struct drm_i915_private *dev_priv = to_i915(dev);
6138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139         struct intel_encoder *encoder;
6140         struct intel_crtc_state *pipe_config =
6141                 to_intel_crtc_state(crtc->state);
6142         enum pipe pipe = intel_crtc->pipe;
6143 
6144         if (WARN_ON(intel_crtc->active))
6145                 return;
6146 
6147         i9xx_set_pll_dividers(intel_crtc);
6148 
6149         if (intel_crtc->config->has_dp_encoder)
6150                 intel_dp_set_m_n(intel_crtc, M1_N1);
6151 
6152         intel_set_pipe_timings(intel_crtc);
6153         intel_set_pipe_src_size(intel_crtc);
6154 
6155         i9xx_set_pipeconf(intel_crtc);
6156 
6157         intel_crtc->active = true;
6158 
6159         if (!IS_GEN2(dev))
6160                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6161 
6162         for_each_encoder_on_crtc(dev, crtc, encoder)
6163                 if (encoder->pre_enable)
6164                         encoder->pre_enable(encoder);
6165 
6166         i9xx_enable_pll(intel_crtc);
6167 
6168         i9xx_pfit_enable(intel_crtc);
6169 
6170         intel_color_load_luts(&pipe_config->base);
6171 
6172         intel_update_watermarks(crtc);
6173         intel_enable_pipe(intel_crtc);
6174 
6175         assert_vblank_disabled(crtc);
6176         drm_crtc_vblank_on(crtc);
6177 
6178         for_each_encoder_on_crtc(dev, crtc, encoder)
6179                 encoder->enable(encoder);
6180 }
6181 
6182 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6183 {
6184         struct drm_device *dev = crtc->base.dev;
6185         struct drm_i915_private *dev_priv = dev->dev_private;
6186 
6187         if (!crtc->config->gmch_pfit.control)
6188                 return;
6189 
6190         assert_pipe_disabled(dev_priv, crtc->pipe);
6191 
6192         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6193                          I915_READ(PFIT_CONTROL));
6194         I915_WRITE(PFIT_CONTROL, 0);
6195 }
6196 
6197 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6198 {
6199         struct drm_device *dev = crtc->dev;
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6202         struct intel_encoder *encoder;
6203         int pipe = intel_crtc->pipe;
6204 
6205         /*
6206          * On gen2 planes are double buffered but the pipe isn't, so we must
6207          * wait for planes to fully turn off before disabling the pipe.
6208          */
6209         if (IS_GEN2(dev))
6210                 intel_wait_for_vblank(dev, pipe);
6211 
6212         for_each_encoder_on_crtc(dev, crtc, encoder)
6213                 encoder->disable(encoder);
6214 
6215         drm_crtc_vblank_off(crtc);
6216         assert_vblank_disabled(crtc);
6217 
6218         intel_disable_pipe(intel_crtc);
6219 
6220         i9xx_pfit_disable(intel_crtc);
6221 
6222         for_each_encoder_on_crtc(dev, crtc, encoder)
6223                 if (encoder->post_disable)
6224                         encoder->post_disable(encoder);
6225 
6226         if (!intel_crtc->config->has_dsi_encoder) {
6227                 if (IS_CHERRYVIEW(dev))
6228                         chv_disable_pll(dev_priv, pipe);
6229                 else if (IS_VALLEYVIEW(dev))
6230                         vlv_disable_pll(dev_priv, pipe);
6231                 else
6232                         i9xx_disable_pll(intel_crtc);
6233         }
6234 
6235         for_each_encoder_on_crtc(dev, crtc, encoder)
6236                 if (encoder->post_pll_disable)
6237                         encoder->post_pll_disable(encoder);
6238 
6239         if (!IS_GEN2(dev))
6240                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6241 }
6242 
6243 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6244 {
6245         struct intel_encoder *encoder;
6246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6247         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6248         enum intel_display_power_domain domain;
6249         unsigned long domains;
6250 
6251         if (!intel_crtc->active)
6252                 return;
6253 
6254         if (to_intel_plane_state(crtc->primary->state)->visible) {
6255                 WARN_ON(intel_crtc->unpin_work);
6256 
6257                 intel_pre_disable_primary_noatomic(crtc);
6258 
6259                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6260                 to_intel_plane_state(crtc->primary->state)->visible = false;
6261         }
6262 
6263         dev_priv->display.crtc_disable(crtc);
6264 
6265         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6266                       crtc->base.id);
6267 
6268         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6269         crtc->state->active = false;
6270         intel_crtc->active = false;
6271         crtc->enabled = false;
6272         crtc->state->connector_mask = 0;
6273         crtc->state->encoder_mask = 0;
6274 
6275         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6276                 encoder->base.crtc = NULL;
6277 
6278         intel_fbc_disable(intel_crtc);
6279         intel_update_watermarks(crtc);
6280         intel_disable_shared_dpll(intel_crtc);
6281 
6282         domains = intel_crtc->enabled_power_domains;
6283         for_each_power_domain(domain, domains)
6284                 intel_display_power_put(dev_priv, domain);
6285         intel_crtc->enabled_power_domains = 0;
6286 
6287         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6288         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6289 }
6290 
6291 /*
6292  * turn all crtc's off, but do not adjust state
6293  * This has to be paired with a call to intel_modeset_setup_hw_state.
6294  */
6295 int intel_display_suspend(struct drm_device *dev)
6296 {
6297         struct drm_i915_private *dev_priv = to_i915(dev);
6298         struct drm_atomic_state *state;
6299         int ret;
6300 
6301         state = drm_atomic_helper_suspend(dev);
6302         ret = PTR_ERR_OR_ZERO(state);
6303         if (ret)
6304                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6305         else
6306                 dev_priv->modeset_restore_state = state;
6307         return ret;
6308 }
6309 
6310 void intel_encoder_destroy(struct drm_encoder *encoder)
6311 {
6312         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6313 
6314         drm_encoder_cleanup(encoder);
6315         kfree(intel_encoder);
6316 }
6317 
6318 /* Cross check the actual hw state with our own modeset state tracking (and it's
6319  * internal consistency). */
6320 static void intel_connector_verify_state(struct intel_connector *connector)
6321 {
6322         struct drm_crtc *crtc = connector->base.state->crtc;
6323 
6324         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6325                       connector->base.base.id,
6326                       connector->base.name);
6327 
6328         if (connector->get_hw_state(connector)) {
6329                 struct intel_encoder *encoder = connector->encoder;
6330                 struct drm_connector_state *conn_state = connector->base.state;
6331 
6332                 I915_STATE_WARN(!crtc,
6333                          "connector enabled without attached crtc\n");
6334 
6335                 if (!crtc)
6336                         return;
6337 
6338                 I915_STATE_WARN(!crtc->state->active,
6339                       "connector is active, but attached crtc isn't\n");
6340 
6341                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6342                         return;
6343 
6344                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6345                         "atomic encoder doesn't match attached encoder\n");
6346 
6347                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6348                         "attached encoder crtc differs from connector crtc\n");
6349         } else {
6350                 I915_STATE_WARN(crtc && crtc->state->active,
6351                         "attached crtc is active, but connector isn't\n");
6352                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6353                         "best encoder set without crtc!\n");
6354         }
6355 }
6356 
6357 int intel_connector_init(struct intel_connector *connector)
6358 {
6359         drm_atomic_helper_connector_reset(&connector->base);
6360 
6361         if (!connector->base.state)
6362                 return -ENOMEM;
6363 
6364         return 0;
6365 }
6366 
6367 struct intel_connector *intel_connector_alloc(void)
6368 {
6369         struct intel_connector *connector;
6370 
6371         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6372         if (!connector)
6373                 return NULL;
6374 
6375         if (intel_connector_init(connector) < 0) {
6376                 kfree(connector);
6377                 return NULL;
6378         }
6379 
6380         return connector;
6381 }
6382 
6383 /* Simple connector->get_hw_state implementation for encoders that support only
6384  * one connector and no cloning and hence the encoder state determines the state
6385  * of the connector. */
6386 bool intel_connector_get_hw_state(struct intel_connector *connector)
6387 {
6388         enum pipe pipe = 0;
6389         struct intel_encoder *encoder = connector->encoder;
6390 
6391         return encoder->get_hw_state(encoder, &pipe);
6392 }
6393 
6394 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6395 {
6396         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6397                 return crtc_state->fdi_lanes;
6398 
6399         return 0;
6400 }
6401 
6402 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6403                                      struct intel_crtc_state *pipe_config)
6404 {
6405         struct drm_atomic_state *state = pipe_config->base.state;
6406         struct intel_crtc *other_crtc;
6407         struct intel_crtc_state *other_crtc_state;
6408 
6409         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6410                       pipe_name(pipe), pipe_config->fdi_lanes);
6411         if (pipe_config->fdi_lanes > 4) {
6412                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6413                               pipe_name(pipe), pipe_config->fdi_lanes);
6414                 return -EINVAL;
6415         }
6416 
6417         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6418                 if (pipe_config->fdi_lanes > 2) {
6419                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6420                                       pipe_config->fdi_lanes);
6421                         return -EINVAL;
6422                 } else {
6423                         return 0;
6424                 }
6425         }
6426 
6427         if (INTEL_INFO(dev)->num_pipes == 2)
6428                 return 0;
6429 
6430         /* Ivybridge 3 pipe is really complicated */
6431         switch (pipe) {
6432         case PIPE_A:
6433                 return 0;
6434         case PIPE_B:
6435                 if (pipe_config->fdi_lanes <= 2)
6436                         return 0;
6437 
6438                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6439                 other_crtc_state =
6440                         intel_atomic_get_crtc_state(state, other_crtc);
6441                 if (IS_ERR(other_crtc_state))
6442                         return PTR_ERR(other_crtc_state);
6443 
6444                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6445                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6446                                       pipe_name(pipe), pipe_config->fdi_lanes);
6447                         return -EINVAL;
6448                 }
6449                 return 0;
6450         case PIPE_C:
6451                 if (pipe_config->fdi_lanes > 2) {
6452                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6453                                       pipe_name(pipe), pipe_config->fdi_lanes);
6454                         return -EINVAL;
6455                 }
6456 
6457                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6458                 other_crtc_state =
6459                         intel_atomic_get_crtc_state(state, other_crtc);
6460                 if (IS_ERR(other_crtc_state))
6461                         return PTR_ERR(other_crtc_state);
6462 
6463                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6464                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6465                         return -EINVAL;
6466                 }
6467                 return 0;
6468         default:
6469                 BUG();
6470         }
6471 }
6472 
6473 #define RETRY 1
6474 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6475                                        struct intel_crtc_state *pipe_config)
6476 {
6477         struct drm_device *dev = intel_crtc->base.dev;
6478         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6479         int lane, link_bw, fdi_dotclock, ret;
6480         bool needs_recompute = false;
6481 
6482 retry:
6483         /* FDI is a binary signal running at ~2.7GHz, encoding
6484          * each output octet as 10 bits. The actual frequency
6485          * is stored as a divider into a 100MHz clock, and the
6486          * mode pixel clock is stored in units of 1KHz.
6487          * Hence the bw of each lane in terms of the mode signal
6488          * is:
6489          */
6490         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6491 
6492         fdi_dotclock = adjusted_mode->crtc_clock;
6493 
6494         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6495                                            pipe_config->pipe_bpp);