Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_atomic.h>
 41 #include <drm/drm_atomic_helper.h>
 42 #include <drm/drm_dp_helper.h>
 43 #include <drm/drm_crtc_helper.h>
 44 #include <drm/drm_plane_helper.h>
 45 #include <drm/drm_rect.h>
 46 #include <linux/dma_remapping.h>
 47 
 48 /* Primary plane formats supported by all gen */
 49 #define COMMON_PRIMARY_FORMATS \
 50         DRM_FORMAT_C8, \
 51         DRM_FORMAT_RGB565, \
 52         DRM_FORMAT_XRGB8888, \
 53         DRM_FORMAT_ARGB8888
 54 
 55 /* Primary plane formats for gen <= 3 */
 56 static const uint32_t intel_primary_formats_gen2[] = {
 57         COMMON_PRIMARY_FORMATS,
 58         DRM_FORMAT_XRGB1555,
 59         DRM_FORMAT_ARGB1555,
 60 };
 61 
 62 /* Primary plane formats for gen >= 4 */
 63 static const uint32_t intel_primary_formats_gen4[] = {
 64         COMMON_PRIMARY_FORMATS, \
 65         DRM_FORMAT_XBGR8888,
 66         DRM_FORMAT_ABGR8888,
 67         DRM_FORMAT_XRGB2101010,
 68         DRM_FORMAT_ARGB2101010,
 69         DRM_FORMAT_XBGR2101010,
 70         DRM_FORMAT_ABGR2101010,
 71 };
 72 
 73 /* Cursor formats */
 74 static const uint32_t intel_cursor_formats[] = {
 75         DRM_FORMAT_ARGB8888,
 76 };
 77 
 78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 79 
 80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 81                                 struct intel_crtc_state *pipe_config);
 82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 83                                    struct intel_crtc_state *pipe_config);
 84 
 85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 86                           int x, int y, struct drm_framebuffer *old_fb,
 87                           struct drm_atomic_state *state);
 88 static int intel_framebuffer_init(struct drm_device *dev,
 89                                   struct intel_framebuffer *ifb,
 90                                   struct drm_mode_fb_cmd2 *mode_cmd,
 91                                   struct drm_i915_gem_object *obj);
 92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 95                                          struct intel_link_m_n *m_n,
 96                                          struct intel_link_m_n *m2_n2);
 97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
101                             const struct intel_crtc_state *pipe_config);
102 static void chv_prepare_pll(struct intel_crtc *crtc,
103                             const struct intel_crtc_state *pipe_config);
104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106 
107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108 {
109         if (!connector->mst_port)
110                 return connector->encoder;
111         else
112                 return &connector->mst_port->mst_encoders[pipe]->base;
113 }
114 
115 typedef struct {
116         int     min, max;
117 } intel_range_t;
118 
119 typedef struct {
120         int     dot_limit;
121         int     p2_slow, p2_fast;
122 } intel_p2_t;
123 
124 typedef struct intel_limit intel_limit_t;
125 struct intel_limit {
126         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
127         intel_p2_t          p2;
128 };
129 
130 int
131 intel_pch_rawclk(struct drm_device *dev)
132 {
133         struct drm_i915_private *dev_priv = dev->dev_private;
134 
135         WARN_ON(!HAS_PCH_SPLIT(dev));
136 
137         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 }
139 
140 static inline u32 /* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device *dev)
142 {
143         if (IS_GEN5(dev)) {
144                 struct drm_i915_private *dev_priv = dev->dev_private;
145                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146         } else
147                 return 27;
148 }
149 
150 static const intel_limit_t intel_limits_i8xx_dac = {
151         .dot = { .min = 25000, .max = 350000 },
152         .vco = { .min = 908000, .max = 1512000 },
153         .n = { .min = 2, .max = 16 },
154         .m = { .min = 96, .max = 140 },
155         .m1 = { .min = 18, .max = 26 },
156         .m2 = { .min = 6, .max = 16 },
157         .p = { .min = 4, .max = 128 },
158         .p1 = { .min = 2, .max = 33 },
159         .p2 = { .dot_limit = 165000,
160                 .p2_slow = 4, .p2_fast = 2 },
161 };
162 
163 static const intel_limit_t intel_limits_i8xx_dvo = {
164         .dot = { .min = 25000, .max = 350000 },
165         .vco = { .min = 908000, .max = 1512000 },
166         .n = { .min = 2, .max = 16 },
167         .m = { .min = 96, .max = 140 },
168         .m1 = { .min = 18, .max = 26 },
169         .m2 = { .min = 6, .max = 16 },
170         .p = { .min = 4, .max = 128 },
171         .p1 = { .min = 2, .max = 33 },
172         .p2 = { .dot_limit = 165000,
173                 .p2_slow = 4, .p2_fast = 4 },
174 };
175 
176 static const intel_limit_t intel_limits_i8xx_lvds = {
177         .dot = { .min = 25000, .max = 350000 },
178         .vco = { .min = 908000, .max = 1512000 },
179         .n = { .min = 2, .max = 16 },
180         .m = { .min = 96, .max = 140 },
181         .m1 = { .min = 18, .max = 26 },
182         .m2 = { .min = 6, .max = 16 },
183         .p = { .min = 4, .max = 128 },
184         .p1 = { .min = 1, .max = 6 },
185         .p2 = { .dot_limit = 165000,
186                 .p2_slow = 14, .p2_fast = 7 },
187 };
188 
189 static const intel_limit_t intel_limits_i9xx_sdvo = {
190         .dot = { .min = 20000, .max = 400000 },
191         .vco = { .min = 1400000, .max = 2800000 },
192         .n = { .min = 1, .max = 6 },
193         .m = { .min = 70, .max = 120 },
194         .m1 = { .min = 8, .max = 18 },
195         .m2 = { .min = 3, .max = 7 },
196         .p = { .min = 5, .max = 80 },
197         .p1 = { .min = 1, .max = 8 },
198         .p2 = { .dot_limit = 200000,
199                 .p2_slow = 10, .p2_fast = 5 },
200 };
201 
202 static const intel_limit_t intel_limits_i9xx_lvds = {
203         .dot = { .min = 20000, .max = 400000 },
204         .vco = { .min = 1400000, .max = 2800000 },
205         .n = { .min = 1, .max = 6 },
206         .m = { .min = 70, .max = 120 },
207         .m1 = { .min = 8, .max = 18 },
208         .m2 = { .min = 3, .max = 7 },
209         .p = { .min = 7, .max = 98 },
210         .p1 = { .min = 1, .max = 8 },
211         .p2 = { .dot_limit = 112000,
212                 .p2_slow = 14, .p2_fast = 7 },
213 };
214 
215 
216 static const intel_limit_t intel_limits_g4x_sdvo = {
217         .dot = { .min = 25000, .max = 270000 },
218         .vco = { .min = 1750000, .max = 3500000},
219         .n = { .min = 1, .max = 4 },
220         .m = { .min = 104, .max = 138 },
221         .m1 = { .min = 17, .max = 23 },
222         .m2 = { .min = 5, .max = 11 },
223         .p = { .min = 10, .max = 30 },
224         .p1 = { .min = 1, .max = 3},
225         .p2 = { .dot_limit = 270000,
226                 .p2_slow = 10,
227                 .p2_fast = 10
228         },
229 };
230 
231 static const intel_limit_t intel_limits_g4x_hdmi = {
232         .dot = { .min = 22000, .max = 400000 },
233         .vco = { .min = 1750000, .max = 3500000},
234         .n = { .min = 1, .max = 4 },
235         .m = { .min = 104, .max = 138 },
236         .m1 = { .min = 16, .max = 23 },
237         .m2 = { .min = 5, .max = 11 },
238         .p = { .min = 5, .max = 80 },
239         .p1 = { .min = 1, .max = 8},
240         .p2 = { .dot_limit = 165000,
241                 .p2_slow = 10, .p2_fast = 5 },
242 };
243 
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
245         .dot = { .min = 20000, .max = 115000 },
246         .vco = { .min = 1750000, .max = 3500000 },
247         .n = { .min = 1, .max = 3 },
248         .m = { .min = 104, .max = 138 },
249         .m1 = { .min = 17, .max = 23 },
250         .m2 = { .min = 5, .max = 11 },
251         .p = { .min = 28, .max = 112 },
252         .p1 = { .min = 2, .max = 8 },
253         .p2 = { .dot_limit = 0,
254                 .p2_slow = 14, .p2_fast = 14
255         },
256 };
257 
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
259         .dot = { .min = 80000, .max = 224000 },
260         .vco = { .min = 1750000, .max = 3500000 },
261         .n = { .min = 1, .max = 3 },
262         .m = { .min = 104, .max = 138 },
263         .m1 = { .min = 17, .max = 23 },
264         .m2 = { .min = 5, .max = 11 },
265         .p = { .min = 14, .max = 42 },
266         .p1 = { .min = 2, .max = 6 },
267         .p2 = { .dot_limit = 0,
268                 .p2_slow = 7, .p2_fast = 7
269         },
270 };
271 
272 static const intel_limit_t intel_limits_pineview_sdvo = {
273         .dot = { .min = 20000, .max = 400000},
274         .vco = { .min = 1700000, .max = 3500000 },
275         /* Pineview's Ncounter is a ring counter */
276         .n = { .min = 3, .max = 6 },
277         .m = { .min = 2, .max = 256 },
278         /* Pineview only has one combined m divider, which we treat as m2. */
279         .m1 = { .min = 0, .max = 0 },
280         .m2 = { .min = 0, .max = 254 },
281         .p = { .min = 5, .max = 80 },
282         .p1 = { .min = 1, .max = 8 },
283         .p2 = { .dot_limit = 200000,
284                 .p2_slow = 10, .p2_fast = 5 },
285 };
286 
287 static const intel_limit_t intel_limits_pineview_lvds = {
288         .dot = { .min = 20000, .max = 400000 },
289         .vco = { .min = 1700000, .max = 3500000 },
290         .n = { .min = 3, .max = 6 },
291         .m = { .min = 2, .max = 256 },
292         .m1 = { .min = 0, .max = 0 },
293         .m2 = { .min = 0, .max = 254 },
294         .p = { .min = 7, .max = 112 },
295         .p1 = { .min = 1, .max = 8 },
296         .p2 = { .dot_limit = 112000,
297                 .p2_slow = 14, .p2_fast = 14 },
298 };
299 
300 /* Ironlake / Sandybridge
301  *
302  * We calculate clock using (register_value + 2) for N/M1/M2, so here
303  * the range value for them is (actual_value - 2).
304  */
305 static const intel_limit_t intel_limits_ironlake_dac = {
306         .dot = { .min = 25000, .max = 350000 },
307         .vco = { .min = 1760000, .max = 3510000 },
308         .n = { .min = 1, .max = 5 },
309         .m = { .min = 79, .max = 127 },
310         .m1 = { .min = 12, .max = 22 },
311         .m2 = { .min = 5, .max = 9 },
312         .p = { .min = 5, .max = 80 },
313         .p1 = { .min = 1, .max = 8 },
314         .p2 = { .dot_limit = 225000,
315                 .p2_slow = 10, .p2_fast = 5 },
316 };
317 
318 static const intel_limit_t intel_limits_ironlake_single_lvds = {
319         .dot = { .min = 25000, .max = 350000 },
320         .vco = { .min = 1760000, .max = 3510000 },
321         .n = { .min = 1, .max = 3 },
322         .m = { .min = 79, .max = 118 },
323         .m1 = { .min = 12, .max = 22 },
324         .m2 = { .min = 5, .max = 9 },
325         .p = { .min = 28, .max = 112 },
326         .p1 = { .min = 2, .max = 8 },
327         .p2 = { .dot_limit = 225000,
328                 .p2_slow = 14, .p2_fast = 14 },
329 };
330 
331 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
332         .dot = { .min = 25000, .max = 350000 },
333         .vco = { .min = 1760000, .max = 3510000 },
334         .n = { .min = 1, .max = 3 },
335         .m = { .min = 79, .max = 127 },
336         .m1 = { .min = 12, .max = 22 },
337         .m2 = { .min = 5, .max = 9 },
338         .p = { .min = 14, .max = 56 },
339         .p1 = { .min = 2, .max = 8 },
340         .p2 = { .dot_limit = 225000,
341                 .p2_slow = 7, .p2_fast = 7 },
342 };
343 
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
346         .dot = { .min = 25000, .max = 350000 },
347         .vco = { .min = 1760000, .max = 3510000 },
348         .n = { .min = 1, .max = 2 },
349         .m = { .min = 79, .max = 126 },
350         .m1 = { .min = 12, .max = 22 },
351         .m2 = { .min = 5, .max = 9 },
352         .p = { .min = 28, .max = 112 },
353         .p1 = { .min = 2, .max = 8 },
354         .p2 = { .dot_limit = 225000,
355                 .p2_slow = 14, .p2_fast = 14 },
356 };
357 
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
359         .dot = { .min = 25000, .max = 350000 },
360         .vco = { .min = 1760000, .max = 3510000 },
361         .n = { .min = 1, .max = 3 },
362         .m = { .min = 79, .max = 126 },
363         .m1 = { .min = 12, .max = 22 },
364         .m2 = { .min = 5, .max = 9 },
365         .p = { .min = 14, .max = 42 },
366         .p1 = { .min = 2, .max = 6 },
367         .p2 = { .dot_limit = 225000,
368                 .p2_slow = 7, .p2_fast = 7 },
369 };
370 
371 static const intel_limit_t intel_limits_vlv = {
372          /*
373           * These are the data rate limits (measured in fast clocks)
374           * since those are the strictest limits we have. The fast
375           * clock and actual rate limits are more relaxed, so checking
376           * them would make no difference.
377           */
378         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
379         .vco = { .min = 4000000, .max = 6000000 },
380         .n = { .min = 1, .max = 7 },
381         .m1 = { .min = 2, .max = 3 },
382         .m2 = { .min = 11, .max = 156 },
383         .p1 = { .min = 2, .max = 3 },
384         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 };
386 
387 static const intel_limit_t intel_limits_chv = {
388         /*
389          * These are the data rate limits (measured in fast clocks)
390          * since those are the strictest limits we have.  The fast
391          * clock and actual rate limits are more relaxed, so checking
392          * them would make no difference.
393          */
394         .dot = { .min = 25000 * 5, .max = 540000 * 5},
395         .vco = { .min = 4800000, .max = 6480000 },
396         .n = { .min = 1, .max = 1 },
397         .m1 = { .min = 2, .max = 2 },
398         .m2 = { .min = 24 << 22, .max = 175 << 22 },
399         .p1 = { .min = 2, .max = 4 },
400         .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 };
402 
403 static void vlv_clock(int refclk, intel_clock_t *clock)
404 {
405         clock->m = clock->m1 * clock->m2;
406         clock->p = clock->p1 * clock->p2;
407         if (WARN_ON(clock->n == 0 || clock->p == 0))
408                 return;
409         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
411 }
412 
413 /**
414  * Returns whether any output on the specified pipe is of the specified type
415  */
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
417 {
418         struct drm_device *dev = crtc->base.dev;
419         struct intel_encoder *encoder;
420 
421         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
422                 if (encoder->type == type)
423                         return true;
424 
425         return false;
426 }
427 
428 /**
429  * Returns whether any output on the specified pipe will have the specified
430  * type after a staged modeset is complete, i.e., the same as
431  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432  * encoder->crtc.
433  */
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435                                       int type)
436 {
437         struct drm_atomic_state *state = crtc_state->base.state;
438         struct drm_connector_state *connector_state;
439         struct intel_encoder *encoder;
440         int i, num_connectors = 0;
441 
442         for (i = 0; i < state->num_connector; i++) {
443                 if (!state->connectors[i])
444                         continue;
445 
446                 connector_state = state->connector_states[i];
447                 if (connector_state->crtc != crtc_state->base.crtc)
448                         continue;
449 
450                 num_connectors++;
451 
452                 encoder = to_intel_encoder(connector_state->best_encoder);
453                 if (encoder->type == type)
454                         return true;
455         }
456 
457         WARN_ON(num_connectors == 0);
458 
459         return false;
460 }
461 
462 static const intel_limit_t *
463 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
464 {
465         struct drm_device *dev = crtc_state->base.crtc->dev;
466         const intel_limit_t *limit;
467 
468         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
469                 if (intel_is_dual_link_lvds(dev)) {
470                         if (refclk == 100000)
471                                 limit = &intel_limits_ironlake_dual_lvds_100m;
472                         else
473                                 limit = &intel_limits_ironlake_dual_lvds;
474                 } else {
475                         if (refclk == 100000)
476                                 limit = &intel_limits_ironlake_single_lvds_100m;
477                         else
478                                 limit = &intel_limits_ironlake_single_lvds;
479                 }
480         } else
481                 limit = &intel_limits_ironlake_dac;
482 
483         return limit;
484 }
485 
486 static const intel_limit_t *
487 intel_g4x_limit(struct intel_crtc_state *crtc_state)
488 {
489         struct drm_device *dev = crtc_state->base.crtc->dev;
490         const intel_limit_t *limit;
491 
492         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
493                 if (intel_is_dual_link_lvds(dev))
494                         limit = &intel_limits_g4x_dual_channel_lvds;
495                 else
496                         limit = &intel_limits_g4x_single_channel_lvds;
497         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
499                 limit = &intel_limits_g4x_hdmi;
500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
501                 limit = &intel_limits_g4x_sdvo;
502         } else /* The option is for other outputs */
503                 limit = &intel_limits_i9xx_sdvo;
504 
505         return limit;
506 }
507 
508 static const intel_limit_t *
509 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
510 {
511         struct drm_device *dev = crtc_state->base.crtc->dev;
512         const intel_limit_t *limit;
513 
514         if (HAS_PCH_SPLIT(dev))
515                 limit = intel_ironlake_limit(crtc_state, refclk);
516         else if (IS_G4X(dev)) {
517                 limit = intel_g4x_limit(crtc_state);
518         } else if (IS_PINEVIEW(dev)) {
519                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
520                         limit = &intel_limits_pineview_lvds;
521                 else
522                         limit = &intel_limits_pineview_sdvo;
523         } else if (IS_CHERRYVIEW(dev)) {
524                 limit = &intel_limits_chv;
525         } else if (IS_VALLEYVIEW(dev)) {
526                 limit = &intel_limits_vlv;
527         } else if (!IS_GEN2(dev)) {
528                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
529                         limit = &intel_limits_i9xx_lvds;
530                 else
531                         limit = &intel_limits_i9xx_sdvo;
532         } else {
533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534                         limit = &intel_limits_i8xx_lvds;
535                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
536                         limit = &intel_limits_i8xx_dvo;
537                 else
538                         limit = &intel_limits_i8xx_dac;
539         }
540         return limit;
541 }
542 
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk, intel_clock_t *clock)
545 {
546         clock->m = clock->m2 + 2;
547         clock->p = clock->p1 * clock->p2;
548         if (WARN_ON(clock->n == 0 || clock->p == 0))
549                 return;
550         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
552 }
553 
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555 {
556         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557 }
558 
559 static void i9xx_clock(int refclk, intel_clock_t *clock)
560 {
561         clock->m = i9xx_dpll_compute_m(clock);
562         clock->p = clock->p1 * clock->p2;
563         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564                 return;
565         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
567 }
568 
569 static void chv_clock(int refclk, intel_clock_t *clock)
570 {
571         clock->m = clock->m1 * clock->m2;
572         clock->p = clock->p1 * clock->p2;
573         if (WARN_ON(clock->n == 0 || clock->p == 0))
574                 return;
575         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576                         clock->n << 22);
577         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578 }
579 
580 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
581 /**
582  * Returns whether the given set of divisors are valid for a given refclk with
583  * the given connectors.
584  */
585 
586 static bool intel_PLL_is_valid(struct drm_device *dev,
587                                const intel_limit_t *limit,
588                                const intel_clock_t *clock)
589 {
590         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
591                 INTELPllInvalid("n out of range\n");
592         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
593                 INTELPllInvalid("p1 out of range\n");
594         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
595                 INTELPllInvalid("m2 out of range\n");
596         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
597                 INTELPllInvalid("m1 out of range\n");
598 
599         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600                 if (clock->m1 <= clock->m2)
601                         INTELPllInvalid("m1 <= m2\n");
602 
603         if (!IS_VALLEYVIEW(dev)) {
604                 if (clock->p < limit->p.min || limit->p.max < clock->p)
605                         INTELPllInvalid("p out of range\n");
606                 if (clock->m < limit->m.min || limit->m.max < clock->m)
607                         INTELPllInvalid("m out of range\n");
608         }
609 
610         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611                 INTELPllInvalid("vco out of range\n");
612         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613          * connector, etc., rather than just a single range.
614          */
615         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616                 INTELPllInvalid("dot out of range\n");
617 
618         return true;
619 }
620 
621 static bool
622 i9xx_find_best_dpll(const intel_limit_t *limit,
623                     struct intel_crtc_state *crtc_state,
624                     int target, int refclk, intel_clock_t *match_clock,
625                     intel_clock_t *best_clock)
626 {
627         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
628         struct drm_device *dev = crtc->base.dev;
629         intel_clock_t clock;
630         int err = target;
631 
632         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
633                 /*
634                  * For LVDS just rely on its current settings for dual-channel.
635                  * We haven't figured out how to reliably set up different
636                  * single/dual channel state, if we even can.
637                  */
638                 if (intel_is_dual_link_lvds(dev))
639                         clock.p2 = limit->p2.p2_fast;
640                 else
641                         clock.p2 = limit->p2.p2_slow;
642         } else {
643                 if (target < limit->p2.dot_limit)
644                         clock.p2 = limit->p2.p2_slow;
645                 else
646                         clock.p2 = limit->p2.p2_fast;
647         }
648 
649         memset(best_clock, 0, sizeof(*best_clock));
650 
651         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652              clock.m1++) {
653                 for (clock.m2 = limit->m2.min;
654                      clock.m2 <= limit->m2.max; clock.m2++) {
655                         if (clock.m2 >= clock.m1)
656                                 break;
657                         for (clock.n = limit->n.min;
658                              clock.n <= limit->n.max; clock.n++) {
659                                 for (clock.p1 = limit->p1.min;
660                                         clock.p1 <= limit->p1.max; clock.p1++) {
661                                         int this_err;
662 
663                                         i9xx_clock(refclk, &clock);
664                                         if (!intel_PLL_is_valid(dev, limit,
665                                                                 &clock))
666                                                 continue;
667                                         if (match_clock &&
668                                             clock.p != match_clock->p)
669                                                 continue;
670 
671                                         this_err = abs(clock.dot - target);
672                                         if (this_err < err) {
673                                                 *best_clock = clock;
674                                                 err = this_err;
675                                         }
676                                 }
677                         }
678                 }
679         }
680 
681         return (err != target);
682 }
683 
684 static bool
685 pnv_find_best_dpll(const intel_limit_t *limit,
686                    struct intel_crtc_state *crtc_state,
687                    int target, int refclk, intel_clock_t *match_clock,
688                    intel_clock_t *best_clock)
689 {
690         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
691         struct drm_device *dev = crtc->base.dev;
692         intel_clock_t clock;
693         int err = target;
694 
695         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
696                 /*
697                  * For LVDS just rely on its current settings for dual-channel.
698                  * We haven't figured out how to reliably set up different
699                  * single/dual channel state, if we even can.
700                  */
701                 if (intel_is_dual_link_lvds(dev))
702                         clock.p2 = limit->p2.p2_fast;
703                 else
704                         clock.p2 = limit->p2.p2_slow;
705         } else {
706                 if (target < limit->p2.dot_limit)
707                         clock.p2 = limit->p2.p2_slow;
708                 else
709                         clock.p2 = limit->p2.p2_fast;
710         }
711 
712         memset(best_clock, 0, sizeof(*best_clock));
713 
714         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715              clock.m1++) {
716                 for (clock.m2 = limit->m2.min;
717                      clock.m2 <= limit->m2.max; clock.m2++) {
718                         for (clock.n = limit->n.min;
719                              clock.n <= limit->n.max; clock.n++) {
720                                 for (clock.p1 = limit->p1.min;
721                                         clock.p1 <= limit->p1.max; clock.p1++) {
722                                         int this_err;
723 
724                                         pineview_clock(refclk, &clock);
725                                         if (!intel_PLL_is_valid(dev, limit,
726                                                                 &clock))
727                                                 continue;
728                                         if (match_clock &&
729                                             clock.p != match_clock->p)
730                                                 continue;
731 
732                                         this_err = abs(clock.dot - target);
733                                         if (this_err < err) {
734                                                 *best_clock = clock;
735                                                 err = this_err;
736                                         }
737                                 }
738                         }
739                 }
740         }
741 
742         return (err != target);
743 }
744 
745 static bool
746 g4x_find_best_dpll(const intel_limit_t *limit,
747                    struct intel_crtc_state *crtc_state,
748                    int target, int refclk, intel_clock_t *match_clock,
749                    intel_clock_t *best_clock)
750 {
751         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
752         struct drm_device *dev = crtc->base.dev;
753         intel_clock_t clock;
754         int max_n;
755         bool found;
756         /* approximately equals target * 0.00585 */
757         int err_most = (target >> 8) + (target >> 9);
758         found = false;
759 
760         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
761                 if (intel_is_dual_link_lvds(dev))
762                         clock.p2 = limit->p2.p2_fast;
763                 else
764                         clock.p2 = limit->p2.p2_slow;
765         } else {
766                 if (target < limit->p2.dot_limit)
767                         clock.p2 = limit->p2.p2_slow;
768                 else
769                         clock.p2 = limit->p2.p2_fast;
770         }
771 
772         memset(best_clock, 0, sizeof(*best_clock));
773         max_n = limit->n.max;
774         /* based on hardware requirement, prefer smaller n to precision */
775         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
776                 /* based on hardware requirement, prefere larger m1,m2 */
777                 for (clock.m1 = limit->m1.max;
778                      clock.m1 >= limit->m1.min; clock.m1--) {
779                         for (clock.m2 = limit->m2.max;
780                              clock.m2 >= limit->m2.min; clock.m2--) {
781                                 for (clock.p1 = limit->p1.max;
782                                      clock.p1 >= limit->p1.min; clock.p1--) {
783                                         int this_err;
784 
785                                         i9xx_clock(refclk, &clock);
786                                         if (!intel_PLL_is_valid(dev, limit,
787                                                                 &clock))
788                                                 continue;
789 
790                                         this_err = abs(clock.dot - target);
791                                         if (this_err < err_most) {
792                                                 *best_clock = clock;
793                                                 err_most = this_err;
794                                                 max_n = clock.n;
795                                                 found = true;
796                                         }
797                                 }
798                         }
799                 }
800         }
801         return found;
802 }
803 
804 /*
805  * Check if the calculated PLL configuration is more optimal compared to the
806  * best configuration and error found so far. Return the calculated error.
807  */
808 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809                                const intel_clock_t *calculated_clock,
810                                const intel_clock_t *best_clock,
811                                unsigned int best_error_ppm,
812                                unsigned int *error_ppm)
813 {
814         /*
815          * For CHV ignore the error and consider only the P value.
816          * Prefer a bigger P value based on HW requirements.
817          */
818         if (IS_CHERRYVIEW(dev)) {
819                 *error_ppm = 0;
820 
821                 return calculated_clock->p > best_clock->p;
822         }
823 
824         if (WARN_ON_ONCE(!target_freq))
825                 return false;
826 
827         *error_ppm = div_u64(1000000ULL *
828                                 abs(target_freq - calculated_clock->dot),
829                              target_freq);
830         /*
831          * Prefer a better P value over a better (smaller) error if the error
832          * is small. Ensure this preference for future configurations too by
833          * setting the error to 0.
834          */
835         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836                 *error_ppm = 0;
837 
838                 return true;
839         }
840 
841         return *error_ppm + 10 < best_error_ppm;
842 }
843 
844 static bool
845 vlv_find_best_dpll(const intel_limit_t *limit,
846                    struct intel_crtc_state *crtc_state,
847                    int target, int refclk, intel_clock_t *match_clock,
848                    intel_clock_t *best_clock)
849 {
850         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
851         struct drm_device *dev = crtc->base.dev;
852         intel_clock_t clock;
853         unsigned int bestppm = 1000000;
854         /* min update 19.2 MHz */
855         int max_n = min(limit->n.max, refclk / 19200);
856         bool found = false;
857 
858         target *= 5; /* fast clock */
859 
860         memset(best_clock, 0, sizeof(*best_clock));
861 
862         /* based on hardware requirement, prefer smaller n to precision */
863         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
864                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
865                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
866                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
867                                 clock.p = clock.p1 * clock.p2;
868                                 /* based on hardware requirement, prefer bigger m1,m2 values */
869                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
870                                         unsigned int ppm;
871 
872                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873                                                                      refclk * clock.m1);
874 
875                                         vlv_clock(refclk, &clock);
876 
877                                         if (!intel_PLL_is_valid(dev, limit,
878                                                                 &clock))
879                                                 continue;
880 
881                                         if (!vlv_PLL_is_optimal(dev, target,
882                                                                 &clock,
883                                                                 best_clock,
884                                                                 bestppm, &ppm))
885                                                 continue;
886 
887                                         *best_clock = clock;
888                                         bestppm = ppm;
889                                         found = true;
890                                 }
891                         }
892                 }
893         }
894 
895         return found;
896 }
897 
898 static bool
899 chv_find_best_dpll(const intel_limit_t *limit,
900                    struct intel_crtc_state *crtc_state,
901                    int target, int refclk, intel_clock_t *match_clock,
902                    intel_clock_t *best_clock)
903 {
904         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
905         struct drm_device *dev = crtc->base.dev;
906         unsigned int best_error_ppm;
907         intel_clock_t clock;
908         uint64_t m2;
909         int found = false;
910 
911         memset(best_clock, 0, sizeof(*best_clock));
912         best_error_ppm = 1000000;
913 
914         /*
915          * Based on hardware doc, the n always set to 1, and m1 always
916          * set to 2.  If requires to support 200Mhz refclk, we need to
917          * revisit this because n may not 1 anymore.
918          */
919         clock.n = 1, clock.m1 = 2;
920         target *= 5;    /* fast clock */
921 
922         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923                 for (clock.p2 = limit->p2.p2_fast;
924                                 clock.p2 >= limit->p2.p2_slow;
925                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
926                         unsigned int error_ppm;
927 
928                         clock.p = clock.p1 * clock.p2;
929 
930                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931                                         clock.n) << 22, refclk * clock.m1);
932 
933                         if (m2 > INT_MAX/clock.m1)
934                                 continue;
935 
936                         clock.m2 = m2;
937 
938                         chv_clock(refclk, &clock);
939 
940                         if (!intel_PLL_is_valid(dev, limit, &clock))
941                                 continue;
942 
943                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944                                                 best_error_ppm, &error_ppm))
945                                 continue;
946 
947                         *best_clock = clock;
948                         best_error_ppm = error_ppm;
949                         found = true;
950                 }
951         }
952 
953         return found;
954 }
955 
956 bool intel_crtc_active(struct drm_crtc *crtc)
957 {
958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959 
960         /* Be paranoid as we can arrive here with only partial
961          * state retrieved from the hardware during setup.
962          *
963          * We can ditch the adjusted_mode.crtc_clock check as soon
964          * as Haswell has gained clock readout/fastboot support.
965          *
966          * We can ditch the crtc->primary->fb check as soon as we can
967          * properly reconstruct framebuffers.
968          *
969          * FIXME: The intel_crtc->active here should be switched to
970          * crtc->state->active once we have proper CRTC states wired up
971          * for atomic.
972          */
973         return intel_crtc->active && crtc->primary->state->fb &&
974                 intel_crtc->config->base.adjusted_mode.crtc_clock;
975 }
976 
977 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978                                              enum pipe pipe)
979 {
980         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982 
983         return intel_crtc->config->cpu_transcoder;
984 }
985 
986 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987 {
988         struct drm_i915_private *dev_priv = dev->dev_private;
989         u32 reg = PIPEDSL(pipe);
990         u32 line1, line2;
991         u32 line_mask;
992 
993         if (IS_GEN2(dev))
994                 line_mask = DSL_LINEMASK_GEN2;
995         else
996                 line_mask = DSL_LINEMASK_GEN3;
997 
998         line1 = I915_READ(reg) & line_mask;
999         mdelay(5);
1000         line2 = I915_READ(reg) & line_mask;
1001 
1002         return line1 == line2;
1003 }
1004 
1005 /*
1006  * intel_wait_for_pipe_off - wait for pipe to turn off
1007  * @crtc: crtc whose pipe to wait for
1008  *
1009  * After disabling a pipe, we can't wait for vblank in the usual way,
1010  * spinning on the vblank interrupt status bit, since we won't actually
1011  * see an interrupt when the pipe is disabled.
1012  *
1013  * On Gen4 and above:
1014  *   wait for the pipe register state bit to turn off
1015  *
1016  * Otherwise:
1017  *   wait for the display line value to settle (it usually
1018  *   ends up stopping at the start of the next frame).
1019  *
1020  */
1021 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1022 {
1023         struct drm_device *dev = crtc->base.dev;
1024         struct drm_i915_private *dev_priv = dev->dev_private;
1025         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1026         enum pipe pipe = crtc->pipe;
1027 
1028         if (INTEL_INFO(dev)->gen >= 4) {
1029                 int reg = PIPECONF(cpu_transcoder);
1030 
1031                 /* Wait for the Pipe State to go off */
1032                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033                              100))
1034                         WARN(1, "pipe_off wait timed out\n");
1035         } else {
1036                 /* Wait for the display line to settle */
1037                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1038                         WARN(1, "pipe_off wait timed out\n");
1039         }
1040 }
1041 
1042 /*
1043  * ibx_digital_port_connected - is the specified port connected?
1044  * @dev_priv: i915 private structure
1045  * @port: the port to test
1046  *
1047  * Returns true if @port is connected, false otherwise.
1048  */
1049 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050                                 struct intel_digital_port *port)
1051 {
1052         u32 bit;
1053 
1054         if (HAS_PCH_IBX(dev_priv->dev)) {
1055                 switch (port->port) {
1056                 case PORT_B:
1057                         bit = SDE_PORTB_HOTPLUG;
1058                         break;
1059                 case PORT_C:
1060                         bit = SDE_PORTC_HOTPLUG;
1061                         break;
1062                 case PORT_D:
1063                         bit = SDE_PORTD_HOTPLUG;
1064                         break;
1065                 default:
1066                         return true;
1067                 }
1068         } else {
1069                 switch (port->port) {
1070                 case PORT_B:
1071                         bit = SDE_PORTB_HOTPLUG_CPT;
1072                         break;
1073                 case PORT_C:
1074                         bit = SDE_PORTC_HOTPLUG_CPT;
1075                         break;
1076                 case PORT_D:
1077                         bit = SDE_PORTD_HOTPLUG_CPT;
1078                         break;
1079                 default:
1080                         return true;
1081                 }
1082         }
1083 
1084         return I915_READ(SDEISR) & bit;
1085 }
1086 
1087 static const char *state_string(bool enabled)
1088 {
1089         return enabled ? "on" : "off";
1090 }
1091 
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094                 enum pipe pipe, bool state)
1095 {
1096         int reg;
1097         u32 val;
1098         bool cur_state;
1099 
1100         reg = DPLL(pipe);
1101         val = I915_READ(reg);
1102         cur_state = !!(val & DPLL_VCO_ENABLE);
1103         I915_STATE_WARN(cur_state != state,
1104              "PLL state assertion failure (expected %s, current %s)\n",
1105              state_string(state), state_string(cur_state));
1106 }
1107 
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110 {
1111         u32 val;
1112         bool cur_state;
1113 
1114         mutex_lock(&dev_priv->dpio_lock);
1115         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116         mutex_unlock(&dev_priv->dpio_lock);
1117 
1118         cur_state = val & DSI_PLL_VCO_EN;
1119         I915_STATE_WARN(cur_state != state,
1120              "DSI PLL state assertion failure (expected %s, current %s)\n",
1121              state_string(state), state_string(cur_state));
1122 }
1123 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125 
1126 struct intel_shared_dpll *
1127 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128 {
1129         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130 
1131         if (crtc->config->shared_dpll < 0)
1132                 return NULL;
1133 
1134         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1135 }
1136 
1137 /* For ILK+ */
1138 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139                         struct intel_shared_dpll *pll,
1140                         bool state)
1141 {
1142         bool cur_state;
1143         struct intel_dpll_hw_state hw_state;
1144 
1145         if (WARN (!pll,
1146                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1147                 return;
1148 
1149         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1150         I915_STATE_WARN(cur_state != state,
1151              "%s assertion failure (expected %s, current %s)\n",
1152              pll->name, state_string(state), state_string(cur_state));
1153 }
1154 
1155 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156                           enum pipe pipe, bool state)
1157 {
1158         int reg;
1159         u32 val;
1160         bool cur_state;
1161         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162                                                                       pipe);
1163 
1164         if (HAS_DDI(dev_priv->dev)) {
1165                 /* DDI does not have a specific FDI_TX register */
1166                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1167                 val = I915_READ(reg);
1168                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1169         } else {
1170                 reg = FDI_TX_CTL(pipe);
1171                 val = I915_READ(reg);
1172                 cur_state = !!(val & FDI_TX_ENABLE);
1173         }
1174         I915_STATE_WARN(cur_state != state,
1175              "FDI TX state assertion failure (expected %s, current %s)\n",
1176              state_string(state), state_string(cur_state));
1177 }
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180 
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182                           enum pipe pipe, bool state)
1183 {
1184         int reg;
1185         u32 val;
1186         bool cur_state;
1187 
1188         reg = FDI_RX_CTL(pipe);
1189         val = I915_READ(reg);
1190         cur_state = !!(val & FDI_RX_ENABLE);
1191         I915_STATE_WARN(cur_state != state,
1192              "FDI RX state assertion failure (expected %s, current %s)\n",
1193              state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197 
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199                                       enum pipe pipe)
1200 {
1201         int reg;
1202         u32 val;
1203 
1204         /* ILK FDI PLL is always enabled */
1205         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1206                 return;
1207 
1208         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209         if (HAS_DDI(dev_priv->dev))
1210                 return;
1211 
1212         reg = FDI_TX_CTL(pipe);
1213         val = I915_READ(reg);
1214         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216 
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218                        enum pipe pipe, bool state)
1219 {
1220         int reg;
1221         u32 val;
1222         bool cur_state;
1223 
1224         reg = FDI_RX_CTL(pipe);
1225         val = I915_READ(reg);
1226         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1227         I915_STATE_WARN(cur_state != state,
1228              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229              state_string(state), state_string(cur_state));
1230 }
1231 
1232 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233                            enum pipe pipe)
1234 {
1235         struct drm_device *dev = dev_priv->dev;
1236         int pp_reg;
1237         u32 val;
1238         enum pipe panel_pipe = PIPE_A;
1239         bool locked = true;
1240 
1241         if (WARN_ON(HAS_DDI(dev)))
1242                 return;
1243 
1244         if (HAS_PCH_SPLIT(dev)) {
1245                 u32 port_sel;
1246 
1247                 pp_reg = PCH_PP_CONTROL;
1248                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249 
1250                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252                         panel_pipe = PIPE_B;
1253                 /* XXX: else fix for eDP */
1254         } else if (IS_VALLEYVIEW(dev)) {
1255                 /* presumably write lock depends on pipe, not port select */
1256                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257                 panel_pipe = pipe;
1258         } else {
1259                 pp_reg = PP_CONTROL;
1260                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261                         panel_pipe = PIPE_B;
1262         }
1263 
1264         val = I915_READ(pp_reg);
1265         if (!(val & PANEL_POWER_ON) ||
1266             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1267                 locked = false;
1268 
1269         I915_STATE_WARN(panel_pipe == pipe && locked,
1270              "panel assertion failure, pipe %c regs locked\n",
1271              pipe_name(pipe));
1272 }
1273 
1274 static void assert_cursor(struct drm_i915_private *dev_priv,
1275                           enum pipe pipe, bool state)
1276 {
1277         struct drm_device *dev = dev_priv->dev;
1278         bool cur_state;
1279 
1280         if (IS_845G(dev) || IS_I865G(dev))
1281                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1282         else
1283                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1284 
1285         I915_STATE_WARN(cur_state != state,
1286              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287              pipe_name(pipe), state_string(state), state_string(cur_state));
1288 }
1289 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291 
1292 void assert_pipe(struct drm_i915_private *dev_priv,
1293                  enum pipe pipe, bool state)
1294 {
1295         int reg;
1296         u32 val;
1297         bool cur_state;
1298         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299                                                                       pipe);
1300 
1301         /* if we need the pipe quirk it must be always on */
1302         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1304                 state = true;
1305 
1306         if (!intel_display_power_is_enabled(dev_priv,
1307                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1308                 cur_state = false;
1309         } else {
1310                 reg = PIPECONF(cpu_transcoder);
1311                 val = I915_READ(reg);
1312                 cur_state = !!(val & PIPECONF_ENABLE);
1313         }
1314 
1315         I915_STATE_WARN(cur_state != state,
1316              "pipe %c assertion failure (expected %s, current %s)\n",
1317              pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319 
1320 static void assert_plane(struct drm_i915_private *dev_priv,
1321                          enum plane plane, bool state)
1322 {
1323         int reg;
1324         u32 val;
1325         bool cur_state;
1326 
1327         reg = DSPCNTR(plane);
1328         val = I915_READ(reg);
1329         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330         I915_STATE_WARN(cur_state != state,
1331              "plane %c assertion failure (expected %s, current %s)\n",
1332              plane_name(plane), state_string(state), state_string(cur_state));
1333 }
1334 
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337 
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339                                    enum pipe pipe)
1340 {
1341         struct drm_device *dev = dev_priv->dev;
1342         int reg, i;
1343         u32 val;
1344         int cur_pipe;
1345 
1346         /* Primary planes are fixed to pipes on gen4+ */
1347         if (INTEL_INFO(dev)->gen >= 4) {
1348                 reg = DSPCNTR(pipe);
1349                 val = I915_READ(reg);
1350                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1351                      "plane %c assertion failure, should be disabled but not\n",
1352                      plane_name(pipe));
1353                 return;
1354         }
1355 
1356         /* Need to check both planes against the pipe */
1357         for_each_pipe(dev_priv, i) {
1358                 reg = DSPCNTR(i);
1359                 val = I915_READ(reg);
1360                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361                         DISPPLANE_SEL_PIPE_SHIFT;
1362                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1363                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364                      plane_name(i), pipe_name(pipe));
1365         }
1366 }
1367 
1368 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369                                     enum pipe pipe)
1370 {
1371         struct drm_device *dev = dev_priv->dev;
1372         int reg, sprite;
1373         u32 val;
1374 
1375         if (INTEL_INFO(dev)->gen >= 9) {
1376                 for_each_sprite(dev_priv, pipe, sprite) {
1377                         val = I915_READ(PLANE_CTL(pipe, sprite));
1378                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1379                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380                              sprite, pipe_name(pipe));
1381                 }
1382         } else if (IS_VALLEYVIEW(dev)) {
1383                 for_each_sprite(dev_priv, pipe, sprite) {
1384                         reg = SPCNTR(pipe, sprite);
1385                         val = I915_READ(reg);
1386                         I915_STATE_WARN(val & SP_ENABLE,
1387                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388                              sprite_name(pipe, sprite), pipe_name(pipe));
1389                 }
1390         } else if (INTEL_INFO(dev)->gen >= 7) {
1391                 reg = SPRCTL(pipe);
1392                 val = I915_READ(reg);
1393                 I915_STATE_WARN(val & SPRITE_ENABLE,
1394                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1395                      plane_name(pipe), pipe_name(pipe));
1396         } else if (INTEL_INFO(dev)->gen >= 5) {
1397                 reg = DVSCNTR(pipe);
1398                 val = I915_READ(reg);
1399                 I915_STATE_WARN(val & DVS_ENABLE,
1400                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1401                      plane_name(pipe), pipe_name(pipe));
1402         }
1403 }
1404 
1405 static void assert_vblank_disabled(struct drm_crtc *crtc)
1406 {
1407         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1408                 drm_crtc_vblank_put(crtc);
1409 }
1410 
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1412 {
1413         u32 val;
1414         bool enabled;
1415 
1416         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1417 
1418         val = I915_READ(PCH_DREF_CONTROL);
1419         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420                             DREF_SUPERSPREAD_SOURCE_MASK));
1421         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1422 }
1423 
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425                                            enum pipe pipe)
1426 {
1427         int reg;
1428         u32 val;
1429         bool enabled;
1430 
1431         reg = PCH_TRANSCONF(pipe);
1432         val = I915_READ(reg);
1433         enabled = !!(val & TRANS_ENABLE);
1434         I915_STATE_WARN(enabled,
1435              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436              pipe_name(pipe));
1437 }
1438 
1439 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440                             enum pipe pipe, u32 port_sel, u32 val)
1441 {
1442         if ((val & DP_PORT_EN) == 0)
1443                 return false;
1444 
1445         if (HAS_PCH_CPT(dev_priv->dev)) {
1446                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449                         return false;
1450         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452                         return false;
1453         } else {
1454                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455                         return false;
1456         }
1457         return true;
1458 }
1459 
1460 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461                               enum pipe pipe, u32 val)
1462 {
1463         if ((val & SDVO_ENABLE) == 0)
1464                 return false;
1465 
1466         if (HAS_PCH_CPT(dev_priv->dev)) {
1467                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1468                         return false;
1469         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471                         return false;
1472         } else {
1473                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1474                         return false;
1475         }
1476         return true;
1477 }
1478 
1479 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480                               enum pipe pipe, u32 val)
1481 {
1482         if ((val & LVDS_PORT_EN) == 0)
1483                 return false;
1484 
1485         if (HAS_PCH_CPT(dev_priv->dev)) {
1486                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487                         return false;
1488         } else {
1489                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490                         return false;
1491         }
1492         return true;
1493 }
1494 
1495 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496                               enum pipe pipe, u32 val)
1497 {
1498         if ((val & ADPA_DAC_ENABLE) == 0)
1499                 return false;
1500         if (HAS_PCH_CPT(dev_priv->dev)) {
1501                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502                         return false;
1503         } else {
1504                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505                         return false;
1506         }
1507         return true;
1508 }
1509 
1510 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1511                                    enum pipe pipe, int reg, u32 port_sel)
1512 {
1513         u32 val = I915_READ(reg);
1514         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1515              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1516              reg, pipe_name(pipe));
1517 
1518         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1519              && (val & DP_PIPEB_SELECT),
1520              "IBX PCH dp port still using transcoder B\n");
1521 }
1522 
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524                                      enum pipe pipe, int reg)
1525 {
1526         u32 val = I915_READ(reg);
1527         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1528              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1529              reg, pipe_name(pipe));
1530 
1531         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1532              && (val & SDVO_PIPE_B_SELECT),
1533              "IBX PCH hdmi port still using transcoder B\n");
1534 }
1535 
1536 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537                                       enum pipe pipe)
1538 {
1539         int reg;
1540         u32 val;
1541 
1542         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1545 
1546         reg = PCH_ADPA;
1547         val = I915_READ(reg);
1548         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1549              "PCH VGA enabled on transcoder %c, should be disabled\n",
1550              pipe_name(pipe));
1551 
1552         reg = PCH_LVDS;
1553         val = I915_READ(reg);
1554         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1555              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1556              pipe_name(pipe));
1557 
1558         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1561 }
1562 
1563 static void intel_init_dpio(struct drm_device *dev)
1564 {
1565         struct drm_i915_private *dev_priv = dev->dev_private;
1566 
1567         if (!IS_VALLEYVIEW(dev))
1568                 return;
1569 
1570         /*
1571          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572          * CHV x1 PHY (DP/HDMI D)
1573          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574          */
1575         if (IS_CHERRYVIEW(dev)) {
1576                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578         } else {
1579                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580         }
1581 }
1582 
1583 static void vlv_enable_pll(struct intel_crtc *crtc,
1584                            const struct intel_crtc_state *pipe_config)
1585 {
1586         struct drm_device *dev = crtc->base.dev;
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588         int reg = DPLL(crtc->pipe);
1589         u32 dpll = pipe_config->dpll_hw_state.dpll;
1590 
1591         assert_pipe_disabled(dev_priv, crtc->pipe);
1592 
1593         /* No really, not for ILK+ */
1594         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595 
1596         /* PLL is protected by panel, make sure we can write it */
1597         if (IS_MOBILE(dev_priv->dev))
1598                 assert_panel_unlocked(dev_priv, crtc->pipe);
1599 
1600         I915_WRITE(reg, dpll);
1601         POSTING_READ(reg);
1602         udelay(150);
1603 
1604         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606 
1607         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1608         POSTING_READ(DPLL_MD(crtc->pipe));
1609 
1610         /* We do this three times for luck */
1611         I915_WRITE(reg, dpll);
1612         POSTING_READ(reg);
1613         udelay(150); /* wait for warmup */
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150); /* wait for warmup */
1617         I915_WRITE(reg, dpll);
1618         POSTING_READ(reg);
1619         udelay(150); /* wait for warmup */
1620 }
1621 
1622 static void chv_enable_pll(struct intel_crtc *crtc,
1623                            const struct intel_crtc_state *pipe_config)
1624 {
1625         struct drm_device *dev = crtc->base.dev;
1626         struct drm_i915_private *dev_priv = dev->dev_private;
1627         int pipe = crtc->pipe;
1628         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1629         u32 tmp;
1630 
1631         assert_pipe_disabled(dev_priv, crtc->pipe);
1632 
1633         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634 
1635         mutex_lock(&dev_priv->dpio_lock);
1636 
1637         /* Enable back the 10bit clock to display controller */
1638         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639         tmp |= DPIO_DCLKP_EN;
1640         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641 
1642         /*
1643          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644          */
1645         udelay(1);
1646 
1647         /* Enable PLL */
1648         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1649 
1650         /* Check PLL is locked */
1651         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1652                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653 
1654         /* not sure when this should be written */
1655         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1656         POSTING_READ(DPLL_MD(pipe));
1657 
1658         mutex_unlock(&dev_priv->dpio_lock);
1659 }
1660 
1661 static int intel_num_dvo_pipes(struct drm_device *dev)
1662 {
1663         struct intel_crtc *crtc;
1664         int count = 0;
1665 
1666         for_each_intel_crtc(dev, crtc)
1667                 count += crtc->active &&
1668                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1669 
1670         return count;
1671 }
1672 
1673 static void i9xx_enable_pll(struct intel_crtc *crtc)
1674 {
1675         struct drm_device *dev = crtc->base.dev;
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677         int reg = DPLL(crtc->pipe);
1678         u32 dpll = crtc->config->dpll_hw_state.dpll;
1679 
1680         assert_pipe_disabled(dev_priv, crtc->pipe);
1681 
1682         /* No really, not for ILK+ */
1683         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1684 
1685         /* PLL is protected by panel, make sure we can write it */
1686         if (IS_MOBILE(dev) && !IS_I830(dev))
1687                 assert_panel_unlocked(dev_priv, crtc->pipe);
1688 
1689         /* Enable DVO 2x clock on both PLLs if necessary */
1690         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691                 /*
1692                  * It appears to be important that we don't enable this
1693                  * for the current pipe before otherwise configuring the
1694                  * PLL. No idea how this should be handled if multiple
1695                  * DVO outputs are enabled simultaneosly.
1696                  */
1697                 dpll |= DPLL_DVO_2X_MODE;
1698                 I915_WRITE(DPLL(!crtc->pipe),
1699                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700         }
1701 
1702         /* Wait for the clocks to stabilize. */
1703         POSTING_READ(reg);
1704         udelay(150);
1705 
1706         if (INTEL_INFO(dev)->gen >= 4) {
1707                 I915_WRITE(DPLL_MD(crtc->pipe),
1708                            crtc->config->dpll_hw_state.dpll_md);
1709         } else {
1710                 /* The pixel multiplier can only be updated once the
1711                  * DPLL is enabled and the clocks are stable.
1712                  *
1713                  * So write it again.
1714                  */
1715                 I915_WRITE(reg, dpll);
1716         }
1717 
1718         /* We do this three times for luck */
1719         I915_WRITE(reg, dpll);
1720         POSTING_READ(reg);
1721         udelay(150); /* wait for warmup */
1722         I915_WRITE(reg, dpll);
1723         POSTING_READ(reg);
1724         udelay(150); /* wait for warmup */
1725         I915_WRITE(reg, dpll);
1726         POSTING_READ(reg);
1727         udelay(150); /* wait for warmup */
1728 }
1729 
1730 /**
1731  * i9xx_disable_pll - disable a PLL
1732  * @dev_priv: i915 private structure
1733  * @pipe: pipe PLL to disable
1734  *
1735  * Disable the PLL for @pipe, making sure the pipe is off first.
1736  *
1737  * Note!  This is for pre-ILK only.
1738  */
1739 static void i9xx_disable_pll(struct intel_crtc *crtc)
1740 {
1741         struct drm_device *dev = crtc->base.dev;
1742         struct drm_i915_private *dev_priv = dev->dev_private;
1743         enum pipe pipe = crtc->pipe;
1744 
1745         /* Disable DVO 2x clock on both PLLs if necessary */
1746         if (IS_I830(dev) &&
1747             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1748             intel_num_dvo_pipes(dev) == 1) {
1749                 I915_WRITE(DPLL(PIPE_B),
1750                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751                 I915_WRITE(DPLL(PIPE_A),
1752                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753         }
1754 
1755         /* Don't disable pipe or pipe PLLs if needed */
1756         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1758                 return;
1759 
1760         /* Make sure the pipe isn't still relying on us */
1761         assert_pipe_disabled(dev_priv, pipe);
1762 
1763         I915_WRITE(DPLL(pipe), 0);
1764         POSTING_READ(DPLL(pipe));
1765 }
1766 
1767 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768 {
1769         u32 val = 0;
1770 
1771         /* Make sure the pipe isn't still relying on us */
1772         assert_pipe_disabled(dev_priv, pipe);
1773 
1774         /*
1775          * Leave integrated clock source and reference clock enabled for pipe B.
1776          * The latter is needed for VGA hotplug / manual detection.
1777          */
1778         if (pipe == PIPE_B)
1779                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1780         I915_WRITE(DPLL(pipe), val);
1781         POSTING_READ(DPLL(pipe));
1782 
1783 }
1784 
1785 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786 {
1787         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1788         u32 val;
1789 
1790         /* Make sure the pipe isn't still relying on us */
1791         assert_pipe_disabled(dev_priv, pipe);
1792 
1793         /* Set PLL en = 0 */
1794         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1795         if (pipe != PIPE_A)
1796                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797         I915_WRITE(DPLL(pipe), val);
1798         POSTING_READ(DPLL(pipe));
1799 
1800         mutex_lock(&dev_priv->dpio_lock);
1801 
1802         /* Disable 10bit clock to display controller */
1803         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804         val &= ~DPIO_DCLKP_EN;
1805         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806 
1807         /* disable left/right clock distribution */
1808         if (pipe != PIPE_B) {
1809                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812         } else {
1813                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816         }
1817 
1818         mutex_unlock(&dev_priv->dpio_lock);
1819 }
1820 
1821 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822                 struct intel_digital_port *dport)
1823 {
1824         u32 port_mask;
1825         int dpll_reg;
1826 
1827         switch (dport->port) {
1828         case PORT_B:
1829                 port_mask = DPLL_PORTB_READY_MASK;
1830                 dpll_reg = DPLL(0);
1831                 break;
1832         case PORT_C:
1833                 port_mask = DPLL_PORTC_READY_MASK;
1834                 dpll_reg = DPLL(0);
1835                 break;
1836         case PORT_D:
1837                 port_mask = DPLL_PORTD_READY_MASK;
1838                 dpll_reg = DPIO_PHY_STATUS;
1839                 break;
1840         default:
1841                 BUG();
1842         }
1843 
1844         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1845                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1846                      port_name(dport->port), I915_READ(dpll_reg));
1847 }
1848 
1849 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850 {
1851         struct drm_device *dev = crtc->base.dev;
1852         struct drm_i915_private *dev_priv = dev->dev_private;
1853         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854 
1855         if (WARN_ON(pll == NULL))
1856                 return;
1857 
1858         WARN_ON(!pll->config.crtc_mask);
1859         if (pll->active == 0) {
1860                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861                 WARN_ON(pll->on);
1862                 assert_shared_dpll_disabled(dev_priv, pll);
1863 
1864                 pll->mode_set(dev_priv, pll);
1865         }
1866 }
1867 
1868 /**
1869  * intel_enable_shared_dpll - enable PCH PLL
1870  * @dev_priv: i915 private structure
1871  * @pipe: pipe PLL to enable
1872  *
1873  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874  * drives the transcoder clock.
1875  */
1876 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1877 {
1878         struct drm_device *dev = crtc->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881 
1882         if (WARN_ON(pll == NULL))
1883                 return;
1884 
1885         if (WARN_ON(pll->config.crtc_mask == 0))
1886                 return;
1887 
1888         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1889                       pll->name, pll->active, pll->on,
1890                       crtc->base.base.id);
1891 
1892         if (pll->active++) {
1893                 WARN_ON(!pll->on);
1894                 assert_shared_dpll_enabled(dev_priv, pll);
1895                 return;
1896         }
1897         WARN_ON(pll->on);
1898 
1899         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900 
1901         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1902         pll->enable(dev_priv, pll);
1903         pll->on = true;
1904 }
1905 
1906 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1907 {
1908         struct drm_device *dev = crtc->base.dev;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1911 
1912         /* PCH only available on ILK+ */
1913         BUG_ON(INTEL_INFO(dev)->gen < 5);
1914         if (WARN_ON(pll == NULL))
1915                return;
1916 
1917         if (WARN_ON(pll->config.crtc_mask == 0))
1918                 return;
1919 
1920         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921                       pll->name, pll->active, pll->on,
1922                       crtc->base.base.id);
1923 
1924         if (WARN_ON(pll->active == 0)) {
1925                 assert_shared_dpll_disabled(dev_priv, pll);
1926                 return;
1927         }
1928 
1929         assert_shared_dpll_enabled(dev_priv, pll);
1930         WARN_ON(!pll->on);
1931         if (--pll->active)
1932                 return;
1933 
1934         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1935         pll->disable(dev_priv, pll);
1936         pll->on = false;
1937 
1938         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1939 }
1940 
1941 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942                                            enum pipe pipe)
1943 {
1944         struct drm_device *dev = dev_priv->dev;
1945         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947         uint32_t reg, val, pipeconf_val;
1948 
1949         /* PCH only available on ILK+ */
1950         BUG_ON(!HAS_PCH_SPLIT(dev));
1951 
1952         /* Make sure PCH DPLL is enabled */
1953         assert_shared_dpll_enabled(dev_priv,
1954                                    intel_crtc_to_shared_dpll(intel_crtc));
1955 
1956         /* FDI must be feeding us bits for PCH ports */
1957         assert_fdi_tx_enabled(dev_priv, pipe);
1958         assert_fdi_rx_enabled(dev_priv, pipe);
1959 
1960         if (HAS_PCH_CPT(dev)) {
1961                 /* Workaround: Set the timing override bit before enabling the
1962                  * pch transcoder. */
1963                 reg = TRANS_CHICKEN2(pipe);
1964                 val = I915_READ(reg);
1965                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966                 I915_WRITE(reg, val);
1967         }
1968 
1969         reg = PCH_TRANSCONF(pipe);
1970         val = I915_READ(reg);
1971         pipeconf_val = I915_READ(PIPECONF(pipe));
1972 
1973         if (HAS_PCH_IBX(dev_priv->dev)) {
1974                 /*
1975                  * make the BPC in transcoder be consistent with
1976                  * that in pipeconf reg.
1977                  */
1978                 val &= ~PIPECONF_BPC_MASK;
1979                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1980         }
1981 
1982         val &= ~TRANS_INTERLACE_MASK;
1983         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1984                 if (HAS_PCH_IBX(dev_priv->dev) &&
1985                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1986                         val |= TRANS_LEGACY_INTERLACED_ILK;
1987                 else
1988                         val |= TRANS_INTERLACED;
1989         else
1990                 val |= TRANS_PROGRESSIVE;
1991 
1992         I915_WRITE(reg, val | TRANS_ENABLE);
1993         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1994                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1995 }
1996 
1997 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1998                                       enum transcoder cpu_transcoder)
1999 {
2000         u32 val, pipeconf_val;
2001 
2002         /* PCH only available on ILK+ */
2003         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2004 
2005         /* FDI must be feeding us bits for PCH ports */
2006         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2007         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2008 
2009         /* Workaround: set timing override bit. */
2010         val = I915_READ(_TRANSA_CHICKEN2);
2011         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2012         I915_WRITE(_TRANSA_CHICKEN2, val);
2013 
2014         val = TRANS_ENABLE;
2015         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2016 
2017         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018             PIPECONF_INTERLACED_ILK)
2019                 val |= TRANS_INTERLACED;
2020         else
2021                 val |= TRANS_PROGRESSIVE;
2022 
2023         I915_WRITE(LPT_TRANSCONF, val);
2024         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2025                 DRM_ERROR("Failed to enable PCH transcoder\n");
2026 }
2027 
2028 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029                                             enum pipe pipe)
2030 {
2031         struct drm_device *dev = dev_priv->dev;
2032         uint32_t reg, val;
2033 
2034         /* FDI relies on the transcoder */
2035         assert_fdi_tx_disabled(dev_priv, pipe);
2036         assert_fdi_rx_disabled(dev_priv, pipe);
2037 
2038         /* Ports must be off as well */
2039         assert_pch_ports_disabled(dev_priv, pipe);
2040 
2041         reg = PCH_TRANSCONF(pipe);
2042         val = I915_READ(reg);
2043         val &= ~TRANS_ENABLE;
2044         I915_WRITE(reg, val);
2045         /* wait for PCH transcoder off, transcoder state */
2046         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2047                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2048 
2049         if (!HAS_PCH_IBX(dev)) {
2050                 /* Workaround: Clear the timing override chicken bit again. */
2051                 reg = TRANS_CHICKEN2(pipe);
2052                 val = I915_READ(reg);
2053                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054                 I915_WRITE(reg, val);
2055         }
2056 }
2057 
2058 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2059 {
2060         u32 val;
2061 
2062         val = I915_READ(LPT_TRANSCONF);
2063         val &= ~TRANS_ENABLE;
2064         I915_WRITE(LPT_TRANSCONF, val);
2065         /* wait for PCH transcoder off, transcoder state */
2066         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2067                 DRM_ERROR("Failed to disable PCH transcoder\n");
2068 
2069         /* Workaround: clear timing override bit. */
2070         val = I915_READ(_TRANSA_CHICKEN2);
2071         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2072         I915_WRITE(_TRANSA_CHICKEN2, val);
2073 }
2074 
2075 /**
2076  * intel_enable_pipe - enable a pipe, asserting requirements
2077  * @crtc: crtc responsible for the pipe
2078  *
2079  * Enable @crtc's pipe, making sure that various hardware specific requirements
2080  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2081  */
2082 static void intel_enable_pipe(struct intel_crtc *crtc)
2083 {
2084         struct drm_device *dev = crtc->base.dev;
2085         struct drm_i915_private *dev_priv = dev->dev_private;
2086         enum pipe pipe = crtc->pipe;
2087         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088                                                                       pipe);
2089         enum pipe pch_transcoder;
2090         int reg;
2091         u32 val;
2092 
2093         assert_planes_disabled(dev_priv, pipe);
2094         assert_cursor_disabled(dev_priv, pipe);
2095         assert_sprites_disabled(dev_priv, pipe);
2096 
2097         if (HAS_PCH_LPT(dev_priv->dev))
2098                 pch_transcoder = TRANSCODER_A;
2099         else
2100                 pch_transcoder = pipe;
2101 
2102         /*
2103          * A pipe without a PLL won't actually be able to drive bits from
2104          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2105          * need the check.
2106          */
2107         if (!HAS_PCH_SPLIT(dev_priv->dev))
2108                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2109                         assert_dsi_pll_enabled(dev_priv);
2110                 else
2111                         assert_pll_enabled(dev_priv, pipe);
2112         else {
2113                 if (crtc->config->has_pch_encoder) {
2114                         /* if driving the PCH, we need FDI enabled */
2115                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2116                         assert_fdi_tx_pll_enabled(dev_priv,
2117                                                   (enum pipe) cpu_transcoder);
2118                 }
2119                 /* FIXME: assert CPU port conditions for SNB+ */
2120         }
2121 
2122         reg = PIPECONF(cpu_transcoder);
2123         val = I915_READ(reg);
2124         if (val & PIPECONF_ENABLE) {
2125                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2127                 return;
2128         }
2129 
2130         I915_WRITE(reg, val | PIPECONF_ENABLE);
2131         POSTING_READ(reg);
2132 }
2133 
2134 /**
2135  * intel_disable_pipe - disable a pipe, asserting requirements
2136  * @crtc: crtc whose pipes is to be disabled
2137  *
2138  * Disable the pipe of @crtc, making sure that various hardware
2139  * specific requirements are met, if applicable, e.g. plane
2140  * disabled, panel fitter off, etc.
2141  *
2142  * Will wait until the pipe has shut down before returning.
2143  */
2144 static void intel_disable_pipe(struct intel_crtc *crtc)
2145 {
2146         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2147         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2148         enum pipe pipe = crtc->pipe;
2149         int reg;
2150         u32 val;
2151 
2152         /*
2153          * Make sure planes won't keep trying to pump pixels to us,
2154          * or we might hang the display.
2155          */
2156         assert_planes_disabled(dev_priv, pipe);
2157         assert_cursor_disabled(dev_priv, pipe);
2158         assert_sprites_disabled(dev_priv, pipe);
2159 
2160         reg = PIPECONF(cpu_transcoder);
2161         val = I915_READ(reg);
2162         if ((val & PIPECONF_ENABLE) == 0)
2163                 return;
2164 
2165         /*
2166          * Double wide has implications for planes
2167          * so best keep it disabled when not needed.
2168          */
2169         if (crtc->config->double_wide)
2170                 val &= ~PIPECONF_DOUBLE_WIDE;
2171 
2172         /* Don't disable pipe or pipe PLLs if needed */
2173         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175                 val &= ~PIPECONF_ENABLE;
2176 
2177         I915_WRITE(reg, val);
2178         if ((val & PIPECONF_ENABLE) == 0)
2179                 intel_wait_for_pipe_off(crtc);
2180 }
2181 
2182 /*
2183  * Plane regs are double buffered, going from enabled->disabled needs a
2184  * trigger in order to latch.  The display address reg provides this.
2185  */
2186 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187                                enum plane plane)
2188 {
2189         struct drm_device *dev = dev_priv->dev;
2190         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2191 
2192         I915_WRITE(reg, I915_READ(reg));
2193         POSTING_READ(reg);
2194 }
2195 
2196 /**
2197  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2198  * @plane:  plane to be enabled
2199  * @crtc: crtc for the plane
2200  *
2201  * Enable @plane on @crtc, making sure that the pipe is running first.
2202  */
2203 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204                                           struct drm_crtc *crtc)
2205 {
2206         struct drm_device *dev = plane->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209 
2210         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2211         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2212 
2213         if (intel_crtc->primary_enabled)
2214                 return;
2215 
2216         intel_crtc->primary_enabled = true;
2217 
2218         dev_priv->display.update_primary_plane(crtc, plane->fb,
2219                                                crtc->x, crtc->y);
2220 
2221         /*
2222          * BDW signals flip done immediately if the plane
2223          * is disabled, even if the plane enable is already
2224          * armed to occur at the next vblank :(
2225          */
2226         if (IS_BROADWELL(dev))
2227                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2228 }
2229 
2230 /**
2231  * intel_disable_primary_hw_plane - disable the primary hardware plane
2232  * @plane: plane to be disabled
2233  * @crtc: crtc for the plane
2234  *
2235  * Disable @plane on @crtc, making sure that the pipe is running first.
2236  */
2237 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238                                            struct drm_crtc *crtc)
2239 {
2240         struct drm_device *dev = plane->dev;
2241         struct drm_i915_private *dev_priv = dev->dev_private;
2242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243 
2244         if (WARN_ON(!intel_crtc->active))
2245                 return;
2246 
2247         if (!intel_crtc->primary_enabled)
2248                 return;
2249 
2250         intel_crtc->primary_enabled = false;
2251 
2252         dev_priv->display.update_primary_plane(crtc, plane->fb,
2253                                                crtc->x, crtc->y);
2254 }
2255 
2256 static bool need_vtd_wa(struct drm_device *dev)
2257 {
2258 #ifdef CONFIG_INTEL_IOMMU
2259         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260                 return true;
2261 #endif
2262         return false;
2263 }
2264 
2265 unsigned int
2266 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267                   uint64_t fb_format_modifier)
2268 {
2269         unsigned int tile_height;
2270         uint32_t pixel_bytes;
2271 
2272         switch (fb_format_modifier) {
2273         case DRM_FORMAT_MOD_NONE:
2274                 tile_height = 1;
2275                 break;
2276         case I915_FORMAT_MOD_X_TILED:
2277                 tile_height = IS_GEN2(dev) ? 16 : 8;
2278                 break;
2279         case I915_FORMAT_MOD_Y_TILED:
2280                 tile_height = 32;
2281                 break;
2282         case I915_FORMAT_MOD_Yf_TILED:
2283                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284                 switch (pixel_bytes) {
2285                 default:
2286                 case 1:
2287                         tile_height = 64;
2288                         break;
2289                 case 2:
2290                 case 4:
2291                         tile_height = 32;
2292                         break;
2293                 case 8:
2294                         tile_height = 16;
2295                         break;
2296                 case 16:
2297                         WARN_ONCE(1,
2298                                   "128-bit pixels are not supported for display!");
2299                         tile_height = 16;
2300                         break;
2301                 }
2302                 break;
2303         default:
2304                 MISSING_CASE(fb_format_modifier);
2305                 tile_height = 1;
2306                 break;
2307         }
2308 
2309         return tile_height;
2310 }
2311 
2312 unsigned int
2313 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314                       uint32_t pixel_format, uint64_t fb_format_modifier)
2315 {
2316         return ALIGN(height, intel_tile_height(dev, pixel_format,
2317                                                fb_format_modifier));
2318 }
2319 
2320 static int
2321 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322                         const struct drm_plane_state *plane_state)
2323 {
2324         struct intel_rotation_info *info = &view->rotation_info;
2325 
2326         *view = i915_ggtt_view_normal;
2327 
2328         if (!plane_state)
2329                 return 0;
2330 
2331         if (!intel_rotation_90_or_270(plane_state->rotation))
2332                 return 0;
2333 
2334         *view = i915_ggtt_view_rotated;
2335 
2336         info->height = fb->height;
2337         info->pixel_format = fb->pixel_format;
2338         info->pitch = fb->pitches[0];
2339         info->fb_modifier = fb->modifier[0];
2340 
2341         if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2342               info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2343                 DRM_DEBUG_KMS(
2344                               "Y or Yf tiling is needed for 90/270 rotation!\n");
2345                 return -EINVAL;
2346         }
2347 
2348         return 0;
2349 }
2350 
2351 int
2352 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2353                            struct drm_framebuffer *fb,
2354                            const struct drm_plane_state *plane_state,
2355                            struct intel_engine_cs *pipelined)
2356 {
2357         struct drm_device *dev = fb->dev;
2358         struct drm_i915_private *dev_priv = dev->dev_private;
2359         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360         struct i915_ggtt_view view;
2361         u32 alignment;
2362         int ret;
2363 
2364         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365 
2366         switch (fb->modifier[0]) {
2367         case DRM_FORMAT_MOD_NONE:
2368                 if (INTEL_INFO(dev)->gen >= 9)
2369                         alignment = 256 * 1024;
2370                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2371                         alignment = 128 * 1024;
2372                 else if (INTEL_INFO(dev)->gen >= 4)
2373                         alignment = 4 * 1024;
2374                 else
2375                         alignment = 64 * 1024;
2376                 break;
2377         case I915_FORMAT_MOD_X_TILED:
2378                 if (INTEL_INFO(dev)->gen >= 9)
2379                         alignment = 256 * 1024;
2380                 else {
2381                         /* pin() will align the object as required by fence */
2382                         alignment = 0;
2383                 }
2384                 break;
2385         case I915_FORMAT_MOD_Y_TILED:
2386         case I915_FORMAT_MOD_Yf_TILED:
2387                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2388                           "Y tiling bo slipped through, driver bug!\n"))
2389                         return -EINVAL;
2390                 alignment = 1 * 1024 * 1024;
2391                 break;
2392         default:
2393                 MISSING_CASE(fb->modifier[0]);
2394                 return -EINVAL;
2395         }
2396 
2397         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2398         if (ret)
2399                 return ret;
2400 
2401         /* Note that the w/a also requires 64 PTE of padding following the
2402          * bo. We currently fill all unused PTE with the shadow page and so
2403          * we should always have valid PTE following the scanout preventing
2404          * the VT-d warning.
2405          */
2406         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2407                 alignment = 256 * 1024;
2408 
2409         /*
2410          * Global gtt pte registers are special registers which actually forward
2411          * writes to a chunk of system memory. Which means that there is no risk
2412          * that the register values disappear as soon as we call
2413          * intel_runtime_pm_put(), so it is correct to wrap only the
2414          * pin/unpin/fence and not more.
2415          */
2416         intel_runtime_pm_get(dev_priv);
2417 
2418         dev_priv->mm.interruptible = false;
2419         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2420                                                    &view);
2421         if (ret)
2422                 goto err_interruptible;
2423 
2424         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2425          * fence, whereas 965+ only requires a fence if using
2426          * framebuffer compression.  For simplicity, we always install
2427          * a fence as the cost is not that onerous.
2428          */
2429         ret = i915_gem_object_get_fence(obj);
2430         if (ret)
2431                 goto err_unpin;
2432 
2433         i915_gem_object_pin_fence(obj);
2434 
2435         dev_priv->mm.interruptible = true;
2436         intel_runtime_pm_put(dev_priv);
2437         return 0;
2438 
2439 err_unpin:
2440         i915_gem_object_unpin_from_display_plane(obj, &view);
2441 err_interruptible:
2442         dev_priv->mm.interruptible = true;
2443         intel_runtime_pm_put(dev_priv);
2444         return ret;
2445 }
2446 
2447 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2448                                const struct drm_plane_state *plane_state)
2449 {
2450         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2451         struct i915_ggtt_view view;
2452         int ret;
2453 
2454         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2455 
2456         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2457         WARN_ONCE(ret, "Couldn't get view from plane state!");
2458 
2459         i915_gem_object_unpin_fence(obj);
2460         i915_gem_object_unpin_from_display_plane(obj, &view);
2461 }
2462 
2463 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2464  * is assumed to be a power-of-two. */
2465 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2466                                              unsigned int tiling_mode,
2467                                              unsigned int cpp,
2468                                              unsigned int pitch)
2469 {
2470         if (tiling_mode != I915_TILING_NONE) {
2471                 unsigned int tile_rows, tiles;
2472 
2473                 tile_rows = *y / 8;
2474                 *y %= 8;
2475 
2476                 tiles = *x / (512/cpp);
2477                 *x %= 512/cpp;
2478 
2479                 return tile_rows * pitch * 8 + tiles * 4096;
2480         } else {
2481                 unsigned int offset;
2482 
2483                 offset = *y * pitch + *x * cpp;
2484                 *y = 0;
2485                 *x = (offset & 4095) / cpp;
2486                 return offset & -4096;
2487         }
2488 }
2489 
2490 static int i9xx_format_to_fourcc(int format)
2491 {
2492         switch (format) {
2493         case DISPPLANE_8BPP:
2494                 return DRM_FORMAT_C8;
2495         case DISPPLANE_BGRX555:
2496                 return DRM_FORMAT_XRGB1555;
2497         case DISPPLANE_BGRX565:
2498                 return DRM_FORMAT_RGB565;
2499         default:
2500         case DISPPLANE_BGRX888:
2501                 return DRM_FORMAT_XRGB8888;
2502         case DISPPLANE_RGBX888:
2503                 return DRM_FORMAT_XBGR8888;
2504         case DISPPLANE_BGRX101010:
2505                 return DRM_FORMAT_XRGB2101010;
2506         case DISPPLANE_RGBX101010:
2507                 return DRM_FORMAT_XBGR2101010;
2508         }
2509 }
2510 
2511 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2512 {
2513         switch (format) {
2514         case PLANE_CTL_FORMAT_RGB_565:
2515                 return DRM_FORMAT_RGB565;
2516         default:
2517         case PLANE_CTL_FORMAT_XRGB_8888:
2518                 if (rgb_order) {
2519                         if (alpha)
2520                                 return DRM_FORMAT_ABGR8888;
2521                         else
2522                                 return DRM_FORMAT_XBGR8888;
2523                 } else {
2524                         if (alpha)
2525                                 return DRM_FORMAT_ARGB8888;
2526                         else
2527                                 return DRM_FORMAT_XRGB8888;
2528                 }
2529         case PLANE_CTL_FORMAT_XRGB_2101010:
2530                 if (rgb_order)
2531                         return DRM_FORMAT_XBGR2101010;
2532                 else
2533                         return DRM_FORMAT_XRGB2101010;
2534         }
2535 }
2536 
2537 static bool
2538 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2539                               struct intel_initial_plane_config *plane_config)
2540 {
2541         struct drm_device *dev = crtc->base.dev;
2542         struct drm_i915_gem_object *obj = NULL;
2543         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2544         struct drm_framebuffer *fb = &plane_config->fb->base;
2545         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2546         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2547                                     PAGE_SIZE);
2548 
2549         size_aligned -= base_aligned;
2550 
2551         if (plane_config->size == 0)
2552                 return false;
2553 
2554         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555                                                              base_aligned,
2556                                                              base_aligned,
2557                                                              size_aligned);
2558         if (!obj)
2559                 return false;
2560 
2561         obj->tiling_mode = plane_config->tiling;
2562         if (obj->tiling_mode == I915_TILING_X)
2563                 obj->stride = fb->pitches[0];
2564 
2565         mode_cmd.pixel_format = fb->pixel_format;
2566         mode_cmd.width = fb->width;
2567         mode_cmd.height = fb->height;
2568         mode_cmd.pitches[0] = fb->pitches[0];
2569         mode_cmd.modifier[0] = fb->modifier[0];
2570         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571 
2572         mutex_lock(&dev->struct_mutex);
2573         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574                                    &mode_cmd, obj)) {
2575                 DRM_DEBUG_KMS("intel fb init failed\n");
2576                 goto out_unref_obj;
2577         }
2578         mutex_unlock(&dev->struct_mutex);
2579 
2580         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581         return true;
2582 
2583 out_unref_obj:
2584         drm_gem_object_unreference(&obj->base);
2585         mutex_unlock(&dev->struct_mutex);
2586         return false;
2587 }
2588 
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593         if (plane->fb == plane->state->fb)
2594                 return;
2595 
2596         if (plane->state->fb)
2597                 drm_framebuffer_unreference(plane->state->fb);
2598         plane->state->fb = plane->fb;
2599         if (plane->state->fb)
2600                 drm_framebuffer_reference(plane->state->fb);
2601 }
2602 
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605                              struct intel_initial_plane_config *plane_config)
2606 {
2607         struct drm_device *dev = intel_crtc->base.dev;
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct drm_crtc *c;
2610         struct intel_crtc *i;
2611         struct drm_i915_gem_object *obj;
2612         struct drm_plane *primary = intel_crtc->base.primary;
2613         struct drm_framebuffer *fb;
2614 
2615         if (!plane_config->fb)
2616                 return;
2617 
2618         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2619                 fb = &plane_config->fb->base;
2620                 goto valid_fb;
2621         }
2622 
2623         kfree(plane_config->fb);
2624 
2625         /*
2626          * Failed to alloc the obj, check to see if we should share
2627          * an fb with another CRTC instead
2628          */
2629         for_each_crtc(dev, c) {
2630                 i = to_intel_crtc(c);
2631 
2632                 if (c == &intel_crtc->base)
2633                         continue;
2634 
2635                 if (!i->active)
2636                         continue;
2637 
2638                 fb = c->primary->fb;
2639                 if (!fb)
2640                         continue;
2641 
2642                 obj = intel_fb_obj(fb);
2643                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2644                         drm_framebuffer_reference(fb);
2645                         goto valid_fb;
2646                 }
2647         }
2648 
2649         return;
2650 
2651 valid_fb:
2652         obj = intel_fb_obj(fb);
2653         if (obj->tiling_mode != I915_TILING_NONE)
2654                 dev_priv->preserve_bios_swizzle = true;
2655 
2656         primary->fb = fb;
2657         primary->state->crtc = &intel_crtc->base;
2658         primary->crtc = &intel_crtc->base;
2659         update_state_fb(primary);
2660         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2661 }
2662 
2663 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2664                                       struct drm_framebuffer *fb,
2665                                       int x, int y)
2666 {
2667         struct drm_device *dev = crtc->dev;
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670         struct drm_i915_gem_object *obj;
2671         int plane = intel_crtc->plane;
2672         unsigned long linear_offset;
2673         u32 dspcntr;
2674         u32 reg = DSPCNTR(plane);
2675         int pixel_size;
2676 
2677         if (!intel_crtc->primary_enabled) {
2678                 I915_WRITE(reg, 0);
2679                 if (INTEL_INFO(dev)->gen >= 4)
2680                         I915_WRITE(DSPSURF(plane), 0);
2681                 else
2682                         I915_WRITE(DSPADDR(plane), 0);
2683                 POSTING_READ(reg);
2684                 return;
2685         }
2686 
2687         obj = intel_fb_obj(fb);
2688         if (WARN_ON(obj == NULL))
2689                 return;
2690 
2691         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2692 
2693         dspcntr = DISPPLANE_GAMMA_ENABLE;
2694 
2695         dspcntr |= DISPLAY_PLANE_ENABLE;
2696 
2697         if (INTEL_INFO(dev)->gen < 4) {
2698                 if (intel_crtc->pipe == PIPE_B)
2699                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2700 
2701                 /* pipesrc and dspsize control the size that is scaled from,
2702                  * which should always be the user's requested size.
2703                  */
2704                 I915_WRITE(DSPSIZE(plane),
2705                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706                            (intel_crtc->config->pipe_src_w - 1));
2707                 I915_WRITE(DSPPOS(plane), 0);
2708         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2709                 I915_WRITE(PRIMSIZE(plane),
2710                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2711                            (intel_crtc->config->pipe_src_w - 1));
2712                 I915_WRITE(PRIMPOS(plane), 0);
2713                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2714         }
2715 
2716         switch (fb->pixel_format) {
2717         case DRM_FORMAT_C8:
2718                 dspcntr |= DISPPLANE_8BPP;
2719                 break;
2720         case DRM_FORMAT_XRGB1555:
2721         case DRM_FORMAT_ARGB1555:
2722                 dspcntr |= DISPPLANE_BGRX555;
2723                 break;
2724         case DRM_FORMAT_RGB565:
2725                 dspcntr |= DISPPLANE_BGRX565;
2726                 break;
2727         case DRM_FORMAT_XRGB8888:
2728         case DRM_FORMAT_ARGB8888:
2729                 dspcntr |= DISPPLANE_BGRX888;
2730                 break;
2731         case DRM_FORMAT_XBGR8888:
2732         case DRM_FORMAT_ABGR8888:
2733                 dspcntr |= DISPPLANE_RGBX888;
2734                 break;
2735         case DRM_FORMAT_XRGB2101010:
2736         case DRM_FORMAT_ARGB2101010:
2737                 dspcntr |= DISPPLANE_BGRX101010;
2738                 break;
2739         case DRM_FORMAT_XBGR2101010:
2740         case DRM_FORMAT_ABGR2101010:
2741                 dspcntr |= DISPPLANE_RGBX101010;
2742                 break;
2743         default:
2744                 BUG();
2745         }
2746 
2747         if (INTEL_INFO(dev)->gen >= 4 &&
2748             obj->tiling_mode != I915_TILING_NONE)
2749                 dspcntr |= DISPPLANE_TILED;
2750 
2751         if (IS_G4X(dev))
2752                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2753 
2754         linear_offset = y * fb->pitches[0] + x * pixel_size;
2755 
2756         if (INTEL_INFO(dev)->gen >= 4) {
2757                 intel_crtc->dspaddr_offset =
2758                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2759                                                        pixel_size,
2760                                                        fb->pitches[0]);
2761                 linear_offset -= intel_crtc->dspaddr_offset;
2762         } else {
2763                 intel_crtc->dspaddr_offset = linear_offset;
2764         }
2765 
2766         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2767                 dspcntr |= DISPPLANE_ROTATE_180;
2768 
2769                 x += (intel_crtc->config->pipe_src_w - 1);
2770                 y += (intel_crtc->config->pipe_src_h - 1);
2771 
2772                 /* Finding the last pixel of the last line of the display
2773                 data and adding to linear_offset*/
2774                 linear_offset +=
2775                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2776                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2777         }
2778 
2779         I915_WRITE(reg, dspcntr);
2780 
2781         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2782         if (INTEL_INFO(dev)->gen >= 4) {
2783                 I915_WRITE(DSPSURF(plane),
2784                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2785                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2786                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2787         } else
2788                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2789         POSTING_READ(reg);
2790 }
2791 
2792 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793                                           struct drm_framebuffer *fb,
2794                                           int x, int y)
2795 {
2796         struct drm_device *dev = crtc->dev;
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799         struct drm_i915_gem_object *obj;
2800         int plane = intel_crtc->plane;
2801         unsigned long linear_offset;
2802         u32 dspcntr;
2803         u32 reg = DSPCNTR(plane);
2804         int pixel_size;
2805 
2806         if (!intel_crtc->primary_enabled) {
2807                 I915_WRITE(reg, 0);
2808                 I915_WRITE(DSPSURF(plane), 0);
2809                 POSTING_READ(reg);
2810                 return;
2811         }
2812 
2813         obj = intel_fb_obj(fb);
2814         if (WARN_ON(obj == NULL))
2815                 return;
2816 
2817         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818 
2819         dspcntr = DISPPLANE_GAMMA_ENABLE;
2820 
2821         dspcntr |= DISPLAY_PLANE_ENABLE;
2822 
2823         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825 
2826         switch (fb->pixel_format) {
2827         case DRM_FORMAT_C8:
2828                 dspcntr |= DISPPLANE_8BPP;
2829                 break;
2830         case DRM_FORMAT_RGB565:
2831                 dspcntr |= DISPPLANE_BGRX565;
2832                 break;
2833         case DRM_FORMAT_XRGB8888:
2834         case DRM_FORMAT_ARGB8888:
2835                 dspcntr |= DISPPLANE_BGRX888;
2836                 break;
2837         case DRM_FORMAT_XBGR8888:
2838         case DRM_FORMAT_ABGR8888:
2839                 dspcntr |= DISPPLANE_RGBX888;
2840                 break;
2841         case DRM_FORMAT_XRGB2101010:
2842         case DRM_FORMAT_ARGB2101010:
2843                 dspcntr |= DISPPLANE_BGRX101010;
2844                 break;
2845         case DRM_FORMAT_XBGR2101010:
2846         case DRM_FORMAT_ABGR2101010:
2847                 dspcntr |= DISPPLANE_RGBX101010;
2848                 break;
2849         default:
2850                 BUG();
2851         }
2852 
2853         if (obj->tiling_mode != I915_TILING_NONE)
2854                 dspcntr |= DISPPLANE_TILED;
2855 
2856         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2857                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2858 
2859         linear_offset = y * fb->pitches[0] + x * pixel_size;
2860         intel_crtc->dspaddr_offset =
2861                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2862                                                pixel_size,
2863                                                fb->pitches[0]);
2864         linear_offset -= intel_crtc->dspaddr_offset;
2865         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2866                 dspcntr |= DISPPLANE_ROTATE_180;
2867 
2868                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2869                         x += (intel_crtc->config->pipe_src_w - 1);
2870                         y += (intel_crtc->config->pipe_src_h - 1);
2871 
2872                         /* Finding the last pixel of the last line of the display
2873                         data and adding to linear_offset*/
2874                         linear_offset +=
2875                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2876                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2877                 }
2878         }
2879 
2880         I915_WRITE(reg, dspcntr);
2881 
2882         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883         I915_WRITE(DSPSURF(plane),
2884                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887         } else {
2888                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890         }
2891         POSTING_READ(reg);
2892 }
2893 
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895                               uint32_t pixel_format)
2896 {
2897         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898 
2899         /*
2900          * The stride is either expressed as a multiple of 64 bytes
2901          * chunks for linear buffers or in number of tiles for tiled
2902          * buffers.
2903          */
2904         switch (fb_modifier) {
2905         case DRM_FORMAT_MOD_NONE:
2906                 return 64;
2907         case I915_FORMAT_MOD_X_TILED:
2908                 if (INTEL_INFO(dev)->gen == 2)
2909                         return 128;
2910                 return 512;
2911         case I915_FORMAT_MOD_Y_TILED:
2912                 /* No need to check for old gens and Y tiling since this is
2913                  * about the display engine and those will be blocked before
2914                  * we get here.
2915                  */
2916                 return 128;
2917         case I915_FORMAT_MOD_Yf_TILED:
2918                 if (bits_per_pixel == 8)
2919                         return 64;
2920                 else
2921                         return 128;
2922         default:
2923                 MISSING_CASE(fb_modifier);
2924                 return 64;
2925         }
2926 }
2927 
2928 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2929                                      struct drm_i915_gem_object *obj)
2930 {
2931         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2932 
2933         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2934                 view = &i915_ggtt_view_rotated;
2935 
2936         return i915_gem_obj_ggtt_offset_view(obj, view);
2937 }
2938 
2939 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2940                                          struct drm_framebuffer *fb,
2941                                          int x, int y)
2942 {
2943         struct drm_device *dev = crtc->dev;
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946         struct drm_i915_gem_object *obj;
2947         int pipe = intel_crtc->pipe;
2948         u32 plane_ctl, stride_div;
2949         unsigned long surf_addr;
2950 
2951         if (!intel_crtc->primary_enabled) {
2952                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2953                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2954                 POSTING_READ(PLANE_CTL(pipe, 0));
2955                 return;
2956         }
2957 
2958         plane_ctl = PLANE_CTL_ENABLE |
2959                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2960                     PLANE_CTL_PIPE_CSC_ENABLE;
2961 
2962         switch (fb->pixel_format) {
2963         case DRM_FORMAT_RGB565:
2964                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2965                 break;
2966         case DRM_FORMAT_XRGB8888:
2967                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2968                 break;
2969         case DRM_FORMAT_ARGB8888:
2970                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2971                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2972                 break;
2973         case DRM_FORMAT_XBGR8888:
2974                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2975                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2976                 break;
2977         case DRM_FORMAT_ABGR8888:
2978                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2979                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2980                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2981                 break;
2982         case DRM_FORMAT_XRGB2101010:
2983                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2984                 break;
2985         case DRM_FORMAT_XBGR2101010:
2986                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2987                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2988                 break;
2989         default:
2990                 BUG();
2991         }
2992 
2993         switch (fb->modifier[0]) {
2994         case DRM_FORMAT_MOD_NONE:
2995                 break;
2996         case I915_FORMAT_MOD_X_TILED:
2997                 plane_ctl |= PLANE_CTL_TILED_X;
2998                 break;
2999         case I915_FORMAT_MOD_Y_TILED:
3000                 plane_ctl |= PLANE_CTL_TILED_Y;
3001                 break;
3002         case I915_FORMAT_MOD_Yf_TILED:
3003                 plane_ctl |= PLANE_CTL_TILED_YF;
3004                 break;
3005         default:
3006                 MISSING_CASE(fb->modifier[0]);
3007         }
3008 
3009         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3010         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
3011                 plane_ctl |= PLANE_CTL_ROTATE_180;
3012 
3013         obj = intel_fb_obj(fb);
3014         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3015                                                fb->pixel_format);
3016         surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
3017 
3018         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3019         I915_WRITE(PLANE_POS(pipe, 0), 0);
3020         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3021         I915_WRITE(PLANE_SIZE(pipe, 0),
3022                    (intel_crtc->config->pipe_src_h - 1) << 16 |
3023                    (intel_crtc->config->pipe_src_w - 1));
3024         I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
3025         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3026 
3027         POSTING_READ(PLANE_SURF(pipe, 0));
3028 }
3029 
3030 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3031 static int
3032 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3033                            int x, int y, enum mode_set_atomic state)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037 
3038         if (dev_priv->display.disable_fbc)
3039                 dev_priv->display.disable_fbc(dev);
3040 
3041         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3042 
3043         return 0;
3044 }
3045 
3046 static void intel_complete_page_flips(struct drm_device *dev)
3047 {
3048         struct drm_crtc *crtc;
3049 
3050         for_each_crtc(dev, crtc) {
3051                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052                 enum plane plane = intel_crtc->plane;
3053 
3054                 intel_prepare_page_flip(dev, plane);
3055                 intel_finish_page_flip_plane(dev, plane);
3056         }
3057 }
3058 
3059 static void intel_update_primary_planes(struct drm_device *dev)
3060 {
3061         struct drm_i915_private *dev_priv = dev->dev_private;
3062         struct drm_crtc *crtc;
3063 
3064         for_each_crtc(dev, crtc) {
3065                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066 
3067                 drm_modeset_lock(&crtc->mutex, NULL);
3068                 /*
3069                  * FIXME: Once we have proper support for primary planes (and
3070                  * disabling them without disabling the entire crtc) allow again
3071                  * a NULL crtc->primary->fb.
3072                  */
3073                 if (intel_crtc->active && crtc->primary->fb)
3074                         dev_priv->display.update_primary_plane(crtc,
3075                                                                crtc->primary->fb,
3076                                                                crtc->x,
3077                                                                crtc->y);
3078                 drm_modeset_unlock(&crtc->mutex);
3079         }
3080 }
3081 
3082 void intel_prepare_reset(struct drm_device *dev)
3083 {
3084         struct drm_i915_private *dev_priv = to_i915(dev);
3085         struct intel_crtc *crtc;
3086 
3087         /* no reset support for gen2 */
3088         if (IS_GEN2(dev))
3089                 return;
3090 
3091         /* reset doesn't touch the display */
3092         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3093                 return;
3094 
3095         drm_modeset_lock_all(dev);
3096 
3097         /*
3098          * Disabling the crtcs gracefully seems nicer. Also the
3099          * g33 docs say we should at least disable all the planes.
3100          */
3101         for_each_intel_crtc(dev, crtc) {
3102                 if (crtc->active)
3103                         dev_priv->display.crtc_disable(&crtc->base);
3104         }
3105 }
3106 
3107 void intel_finish_reset(struct drm_device *dev)
3108 {
3109         struct drm_i915_private *dev_priv = to_i915(dev);
3110 
3111         /*
3112          * Flips in the rings will be nuked by the reset,
3113          * so complete all pending flips so that user space
3114          * will get its events and not get stuck.
3115          */
3116         intel_complete_page_flips(dev);
3117 
3118         /* no reset support for gen2 */
3119         if (IS_GEN2(dev))
3120                 return;
3121 
3122         /* reset doesn't touch the display */
3123         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3124                 /*
3125                  * Flips in the rings have been nuked by the reset,
3126                  * so update the base address of all primary
3127                  * planes to the the last fb to make sure we're
3128                  * showing the correct fb after a reset.
3129                  */
3130                 intel_update_primary_planes(dev);
3131                 return;
3132         }
3133 
3134         /*
3135          * The display has been reset as well,
3136          * so need a full re-initialization.
3137          */
3138         intel_runtime_pm_disable_interrupts(dev_priv);
3139         intel_runtime_pm_enable_interrupts(dev_priv);
3140 
3141         intel_modeset_init_hw(dev);
3142 
3143         spin_lock_irq(&dev_priv->irq_lock);
3144         if (dev_priv->display.hpd_irq_setup)
3145                 dev_priv->display.hpd_irq_setup(dev);
3146         spin_unlock_irq(&dev_priv->irq_lock);
3147 
3148         intel_modeset_setup_hw_state(dev, true);
3149 
3150         intel_hpd_init(dev_priv);
3151 
3152         drm_modeset_unlock_all(dev);
3153 }
3154 
3155 static int
3156 intel_finish_fb(struct drm_framebuffer *old_fb)
3157 {
3158         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3159         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3160         bool was_interruptible = dev_priv->mm.interruptible;
3161         int ret;
3162 
3163         /* Big Hammer, we also need to ensure that any pending
3164          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3165          * current scanout is retired before unpinning the old
3166          * framebuffer.
3167          *
3168          * This should only fail upon a hung GPU, in which case we
3169          * can safely continue.
3170          */
3171         dev_priv->mm.interruptible = false;
3172         ret = i915_gem_object_finish_gpu(obj);
3173         dev_priv->mm.interruptible = was_interruptible;
3174 
3175         return ret;
3176 }
3177 
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180         struct drm_device *dev = crtc->dev;
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3183         bool pending;
3184 
3185         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3186             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3187                 return false;
3188 
3189         spin_lock_irq(&dev->event_lock);
3190         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3191         spin_unlock_irq(&dev->event_lock);
3192 
3193         return pending;
3194 }
3195 
3196 static void intel_update_pipe_size(struct intel_crtc *crtc)
3197 {
3198         struct drm_device *dev = crtc->base.dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         const struct drm_display_mode *adjusted_mode;
3201 
3202         if (!i915.fastboot)
3203                 return;
3204 
3205         /*
3206          * Update pipe size and adjust fitter if needed: the reason for this is
3207          * that in compute_mode_changes we check the native mode (not the pfit
3208          * mode) to see if we can flip rather than do a full mode set. In the
3209          * fastboot case, we'll flip, but if we don't update the pipesrc and
3210          * pfit state, we'll end up with a big fb scanned out into the wrong
3211          * sized surface.
3212          *
3213          * To fix this properly, we need to hoist the checks up into
3214          * compute_mode_changes (or above), check the actual pfit state and
3215          * whether the platform allows pfit disable with pipe active, and only
3216          * then update the pipesrc and pfit state, even on the flip path.
3217          */
3218 
3219         adjusted_mode = &crtc->config->base.adjusted_mode;
3220 
3221         I915_WRITE(PIPESRC(crtc->pipe),
3222                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3223                    (adjusted_mode->crtc_vdisplay - 1));
3224         if (!crtc->config->pch_pfit.enabled &&
3225             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3226              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3227                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3228                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3229                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3230         }
3231         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3232         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3233 }
3234 
3235 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3236 {
3237         struct drm_device *dev = crtc->dev;
3238         struct drm_i915_private *dev_priv = dev->dev_private;
3239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240         int pipe = intel_crtc->pipe;
3241         u32 reg, temp;
3242 
3243         /* enable normal train */
3244         reg = FDI_TX_CTL(pipe);
3245         temp = I915_READ(reg);
3246         if (IS_IVYBRIDGE(dev)) {
3247                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3248                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3249         } else {
3250                 temp &= ~FDI_LINK_TRAIN_NONE;
3251                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3252         }
3253         I915_WRITE(reg, temp);
3254 
3255         reg = FDI_RX_CTL(pipe);
3256         temp = I915_READ(reg);
3257         if (HAS_PCH_CPT(dev)) {
3258                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3259                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3260         } else {
3261                 temp &= ~FDI_LINK_TRAIN_NONE;
3262                 temp |= FDI_LINK_TRAIN_NONE;
3263         }
3264         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3265 
3266         /* wait one idle pattern time */
3267         POSTING_READ(reg);
3268         udelay(1000);
3269 
3270         /* IVB wants error correction enabled */
3271         if (IS_IVYBRIDGE(dev))
3272                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3273                            FDI_FE_ERRC_ENABLE);
3274 }
3275 
3276 /* The FDI link training functions for ILK/Ibexpeak. */
3277 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282         int pipe = intel_crtc->pipe;
3283         u32 reg, temp, tries;
3284 
3285         /* FDI needs bits from pipe first */
3286         assert_pipe_enabled(dev_priv, pipe);
3287 
3288         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3289            for train result */
3290         reg = FDI_RX_IMR(pipe);
3291         temp = I915_READ(reg);
3292         temp &= ~FDI_RX_SYMBOL_LOCK;
3293         temp &= ~FDI_RX_BIT_LOCK;
3294         I915_WRITE(reg, temp);
3295         I915_READ(reg);
3296         udelay(150);
3297 
3298         /* enable CPU FDI TX and PCH FDI RX */
3299         reg = FDI_TX_CTL(pipe);
3300         temp = I915_READ(reg);
3301         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3302         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3303         temp &= ~FDI_LINK_TRAIN_NONE;
3304         temp |= FDI_LINK_TRAIN_PATTERN_1;
3305         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3306 
3307         reg = FDI_RX_CTL(pipe);
3308         temp = I915_READ(reg);
3309         temp &= ~FDI_LINK_TRAIN_NONE;
3310         temp |= FDI_LINK_TRAIN_PATTERN_1;
3311         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3312 
3313         POSTING_READ(reg);
3314         udelay(150);
3315 
3316         /* Ironlake workaround, enable clock pointer after FDI enable*/
3317         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3318         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3319                    FDI_RX_PHASE_SYNC_POINTER_EN);
3320 
3321         reg = FDI_RX_IIR(pipe);
3322         for (tries = 0; tries < 5; tries++) {
3323                 temp = I915_READ(reg);
3324                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3325 
3326                 if ((temp & FDI_RX_BIT_LOCK)) {
3327                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3328                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3329                         break;
3330                 }
3331         }
3332         if (tries == 5)
3333                 DRM_ERROR("FDI train 1 fail!\n");
3334 
3335         /* Train 2 */
3336         reg = FDI_TX_CTL(pipe);
3337         temp = I915_READ(reg);
3338         temp &= ~FDI_LINK_TRAIN_NONE;
3339         temp |= FDI_LINK_TRAIN_PATTERN_2;
3340         I915_WRITE(reg, temp);
3341 
3342         reg = FDI_RX_CTL(pipe);
3343         temp = I915_READ(reg);
3344         temp &= ~FDI_LINK_TRAIN_NONE;
3345         temp |= FDI_LINK_TRAIN_PATTERN_2;
3346         I915_WRITE(reg, temp);
3347 
3348         POSTING_READ(reg);
3349         udelay(150);
3350 
3351         reg = FDI_RX_IIR(pipe);
3352         for (tries = 0; tries < 5; tries++) {
3353                 temp = I915_READ(reg);
3354                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3355 
3356                 if (temp & FDI_RX_SYMBOL_LOCK) {
3357                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3358                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3359                         break;
3360                 }
3361         }
3362         if (tries == 5)
3363                 DRM_ERROR("FDI train 2 fail!\n");
3364 
3365         DRM_DEBUG_KMS("FDI train done\n");
3366 
3367 }
3368 
3369 static const int snb_b_fdi_train_param[] = {
3370         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3371         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3372         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3373         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3374 };
3375 
3376 /* The FDI link training functions for SNB/Cougarpoint. */
3377 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3378 {
3379         struct drm_device *dev = crtc->dev;
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382         int pipe = intel_crtc->pipe;
3383         u32 reg, temp, i, retry;
3384 
3385         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386            for train result */
3387         reg = FDI_RX_IMR(pipe);
3388         temp = I915_READ(reg);
3389         temp &= ~FDI_RX_SYMBOL_LOCK;
3390         temp &= ~FDI_RX_BIT_LOCK;
3391         I915_WRITE(reg, temp);
3392 
3393         POSTING_READ(reg);
3394         udelay(150);
3395 
3396         /* enable CPU FDI TX and PCH FDI RX */
3397         reg = FDI_TX_CTL(pipe);
3398         temp = I915_READ(reg);
3399         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3400         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3401         temp &= ~FDI_LINK_TRAIN_NONE;
3402         temp |= FDI_LINK_TRAIN_PATTERN_1;
3403         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3404         /* SNB-B */
3405         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3406         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3407 
3408         I915_WRITE(FDI_RX_MISC(pipe),
3409                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3410 
3411         reg = FDI_RX_CTL(pipe);
3412         temp = I915_READ(reg);
3413         if (HAS_PCH_CPT(dev)) {
3414                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3415                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3416         } else {
3417                 temp &= ~FDI_LINK_TRAIN_NONE;
3418                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419         }
3420         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3421 
3422         POSTING_READ(reg);
3423         udelay(150);
3424 
3425         for (i = 0; i < 4; i++) {
3426                 reg = FDI_TX_CTL(pipe);
3427                 temp = I915_READ(reg);
3428                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3429                 temp |= snb_b_fdi_train_param[i];
3430                 I915_WRITE(reg, temp);
3431 
3432                 POSTING_READ(reg);
3433                 udelay(500);
3434 
3435                 for (retry = 0; retry < 5; retry++) {
3436                         reg = FDI_RX_IIR(pipe);
3437                         temp = I915_READ(reg);
3438                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439                         if (temp & FDI_RX_BIT_LOCK) {
3440                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3441                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442                                 break;
3443                         }
3444                         udelay(50);
3445                 }
3446                 if (retry < 5)
3447                         break;
3448         }
3449         if (i == 4)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451 
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         if (IS_GEN6(dev)) {
3458                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3459                 /* SNB-B */
3460                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3461         }
3462         I915_WRITE(reg, temp);
3463 
3464         reg = FDI_RX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         if (HAS_PCH_CPT(dev)) {
3467                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3468                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3469         } else {
3470                 temp &= ~FDI_LINK_TRAIN_NONE;
3471                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3472         }
3473         I915_WRITE(reg, temp);
3474 
3475         POSTING_READ(reg);
3476         udelay(150);
3477 
3478         for (i = 0; i < 4; i++) {
3479                 reg = FDI_TX_CTL(pipe);
3480                 temp = I915_READ(reg);
3481                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3482                 temp |= snb_b_fdi_train_param[i];
3483                 I915_WRITE(reg, temp);
3484 
3485                 POSTING_READ(reg);
3486                 udelay(500);
3487 
3488                 for (retry = 0; retry < 5; retry++) {
3489                         reg = FDI_RX_IIR(pipe);
3490                         temp = I915_READ(reg);
3491                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3492                         if (temp & FDI_RX_SYMBOL_LOCK) {
3493                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3494                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3495                                 break;
3496                         }
3497                         udelay(50);
3498                 }
3499                 if (retry < 5)
3500                         break;
3501         }
3502         if (i == 4)
3503                 DRM_ERROR("FDI train 2 fail!\n");
3504 
3505         DRM_DEBUG_KMS("FDI train done.\n");
3506 }
3507 
3508 /* Manual link training for Ivy Bridge A0 parts */
3509 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3510 {
3511         struct drm_device *dev = crtc->dev;
3512         struct drm_i915_private *dev_priv = dev->dev_private;
3513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514         int pipe = intel_crtc->pipe;
3515         u32 reg, temp, i, j;
3516 
3517         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3518            for train result */
3519         reg = FDI_RX_IMR(pipe);
3520         temp = I915_READ(reg);
3521         temp &= ~FDI_RX_SYMBOL_LOCK;
3522         temp &= ~FDI_RX_BIT_LOCK;
3523         I915_WRITE(reg, temp);
3524 
3525         POSTING_READ(reg);
3526         udelay(150);
3527 
3528         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3529                       I915_READ(FDI_RX_IIR(pipe)));
3530 
3531         /* Try each vswing and preemphasis setting twice before moving on */
3532         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3533                 /* disable first in case we need to retry */
3534                 reg = FDI_TX_CTL(pipe);
3535                 temp = I915_READ(reg);
3536                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3537                 temp &= ~FDI_TX_ENABLE;
3538                 I915_WRITE(reg, temp);
3539 
3540                 reg = FDI_RX_CTL(pipe);
3541                 temp = I915_READ(reg);
3542                 temp &= ~FDI_LINK_TRAIN_AUTO;
3543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544                 temp &= ~FDI_RX_ENABLE;
3545                 I915_WRITE(reg, temp);
3546 
3547                 /* enable CPU FDI TX and PCH FDI RX */
3548                 reg = FDI_TX_CTL(pipe);
3549                 temp = I915_READ(reg);
3550                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3551                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3552                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3553                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554                 temp |= snb_b_fdi_train_param[j/2];
3555                 temp |= FDI_COMPOSITE_SYNC;
3556                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3557 
3558                 I915_WRITE(FDI_RX_MISC(pipe),
3559                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3560 
3561                 reg = FDI_RX_CTL(pipe);
3562                 temp = I915_READ(reg);
3563                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564                 temp |= FDI_COMPOSITE_SYNC;
3565                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3566 
3567                 POSTING_READ(reg);
3568                 udelay(1); /* should be 0.5us */
3569 
3570                 for (i = 0; i < 4; i++) {
3571                         reg = FDI_RX_IIR(pipe);
3572                         temp = I915_READ(reg);
3573                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3574 
3575                         if (temp & FDI_RX_BIT_LOCK ||
3576                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3577                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3578                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3579                                               i);
3580                                 break;
3581                         }
3582                         udelay(1); /* should be 0.5us */
3583                 }
3584                 if (i == 4) {
3585                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3586                         continue;
3587                 }
3588 
3589                 /* Train 2 */
3590                 reg = FDI_TX_CTL(pipe);
3591                 temp = I915_READ(reg);
3592                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3593                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3594                 I915_WRITE(reg, temp);
3595 
3596                 reg = FDI_RX_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3599                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3600                 I915_WRITE(reg, temp);
3601 
3602                 POSTING_READ(reg);
3603                 udelay(2); /* should be 1.5us */
3604 
3605                 for (i = 0; i < 4; i++) {
3606                         reg = FDI_RX_IIR(pipe);
3607                         temp = I915_READ(reg);
3608                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609 
3610                         if (temp & FDI_RX_SYMBOL_LOCK ||
3611                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3612                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3614                                               i);
3615                                 goto train_done;
3616                         }
3617                         udelay(2); /* should be 1.5us */
3618                 }
3619                 if (i == 4)
3620                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3621         }
3622 
3623 train_done:
3624         DRM_DEBUG_KMS("FDI train done.\n");
3625 }
3626 
3627 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3628 {
3629         struct drm_device *dev = intel_crtc->base.dev;
3630         struct drm_i915_private *dev_priv = dev->dev_private;
3631         int pipe = intel_crtc->pipe;
3632         u32 reg, temp;
3633 
3634 
3635         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3636         reg = FDI_RX_CTL(pipe);
3637         temp = I915_READ(reg);
3638         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3639         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3640         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3641         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3642 
3643         POSTING_READ(reg);
3644         udelay(200);
3645 
3646         /* Switch from Rawclk to PCDclk */
3647         temp = I915_READ(reg);
3648         I915_WRITE(reg, temp | FDI_PCDCLK);
3649 
3650         POSTING_READ(reg);
3651         udelay(200);
3652 
3653         /* Enable CPU FDI TX PLL, always on for Ironlake */
3654         reg = FDI_TX_CTL(pipe);
3655         temp = I915_READ(reg);
3656         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3657                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3658 
3659                 POSTING_READ(reg);
3660                 udelay(100);
3661         }
3662 }
3663 
3664 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3665 {
3666         struct drm_device *dev = intel_crtc->base.dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         int pipe = intel_crtc->pipe;
3669         u32 reg, temp;
3670 
3671         /* Switch from PCDclk to Rawclk */
3672         reg = FDI_RX_CTL(pipe);
3673         temp = I915_READ(reg);
3674         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3675 
3676         /* Disable CPU FDI TX PLL */
3677         reg = FDI_TX_CTL(pipe);
3678         temp = I915_READ(reg);
3679         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3680 
3681         POSTING_READ(reg);
3682         udelay(100);
3683 
3684         reg = FDI_RX_CTL(pipe);
3685         temp = I915_READ(reg);
3686         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3687 
3688         /* Wait for the clocks to turn off. */
3689         POSTING_READ(reg);
3690         udelay(100);
3691 }
3692 
3693 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3694 {
3695         struct drm_device *dev = crtc->dev;
3696         struct drm_i915_private *dev_priv = dev->dev_private;
3697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698         int pipe = intel_crtc->pipe;
3699         u32 reg, temp;
3700 
3701         /* disable CPU FDI tx and PCH FDI rx */
3702         reg = FDI_TX_CTL(pipe);
3703         temp = I915_READ(reg);
3704         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3705         POSTING_READ(reg);
3706 
3707         reg = FDI_RX_CTL(pipe);
3708         temp = I915_READ(reg);
3709         temp &= ~(0x7 << 16);
3710         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3711         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3712 
3713         POSTING_READ(reg);
3714         udelay(100);
3715 
3716         /* Ironlake workaround, disable clock pointer after downing FDI */
3717         if (HAS_PCH_IBX(dev))
3718                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3719 
3720         /* still set train pattern 1 */
3721         reg = FDI_TX_CTL(pipe);
3722         temp = I915_READ(reg);
3723         temp &= ~FDI_LINK_TRAIN_NONE;
3724         temp |= FDI_LINK_TRAIN_PATTERN_1;
3725         I915_WRITE(reg, temp);
3726 
3727         reg = FDI_RX_CTL(pipe);
3728         temp = I915_READ(reg);
3729         if (HAS_PCH_CPT(dev)) {
3730                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3732         } else {
3733                 temp &= ~FDI_LINK_TRAIN_NONE;
3734                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3735         }
3736         /* BPC in FDI rx is consistent with that in PIPECONF */
3737         temp &= ~(0x07 << 16);
3738         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3739         I915_WRITE(reg, temp);
3740 
3741         POSTING_READ(reg);
3742         udelay(100);
3743 }
3744 
3745 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3746 {
3747         struct intel_crtc *crtc;
3748 
3749         /* Note that we don't need to be called with mode_config.lock here
3750          * as our list of CRTC objects is static for the lifetime of the
3751          * device and so cannot disappear as we iterate. Similarly, we can
3752          * happily treat the predicates as racy, atomic checks as userspace
3753          * cannot claim and pin a new fb without at least acquring the
3754          * struct_mutex and so serialising with us.
3755          */
3756         for_each_intel_crtc(dev, crtc) {
3757                 if (atomic_read(&crtc->unpin_work_count) == 0)
3758                         continue;
3759 
3760                 if (crtc->unpin_work)
3761                         intel_wait_for_vblank(dev, crtc->pipe);
3762 
3763                 return true;
3764         }
3765 
3766         return false;
3767 }
3768 
3769 static void page_flip_completed(struct intel_crtc *intel_crtc)
3770 {
3771         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3772         struct intel_unpin_work *work = intel_crtc->unpin_work;
3773 
3774         /* ensure that the unpin work is consistent wrt ->pending. */
3775         smp_rmb();
3776         intel_crtc->unpin_work = NULL;
3777 
3778         if (work->event)
3779                 drm_send_vblank_event(intel_crtc->base.dev,
3780                                       intel_crtc->pipe,
3781                                       work->event);
3782 
3783         drm_crtc_vblank_put(&intel_crtc->base);
3784 
3785         wake_up_all(&dev_priv->pending_flip_queue);
3786         queue_work(dev_priv->wq, &work->work);
3787 
3788         trace_i915_flip_complete(intel_crtc->plane,
3789                                  work->pending_flip_obj);
3790 }
3791 
3792 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795         struct drm_i915_private *dev_priv = dev->dev_private;
3796 
3797         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3799                                        !intel_crtc_has_pending_flip(crtc),
3800                                        60*HZ) == 0)) {
3801                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3802 
3803                 spin_lock_irq(&dev->event_lock);
3804                 if (intel_crtc->unpin_work) {
3805                         WARN_ONCE(1, "Removing stuck page flip\n");
3806                         page_flip_completed(intel_crtc);
3807                 }
3808                 spin_unlock_irq(&dev->event_lock);
3809         }
3810 
3811         if (crtc->primary->fb) {
3812                 mutex_lock(&dev->struct_mutex);
3813                 intel_finish_fb(crtc->primary->fb);
3814                 mutex_unlock(&dev->struct_mutex);
3815         }
3816 }
3817 
3818 /* Program iCLKIP clock to the desired frequency */
3819 static void lpt_program_iclkip(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3824         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3825         u32 temp;
3826 
3827         mutex_lock(&dev_priv->dpio_lock);
3828 
3829         /* It is necessary to ungate the pixclk gate prior to programming
3830          * the divisors, and gate it back when it is done.
3831          */
3832         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833 
3834         /* Disable SSCCTL */
3835         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3836                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3837                                 SBI_SSCCTL_DISABLE,
3838                         SBI_ICLK);
3839 
3840         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3841         if (clock == 20000) {
3842                 auxdiv = 1;
3843                 divsel = 0x41;
3844                 phaseinc = 0x20;
3845         } else {
3846                 /* The iCLK virtual clock root frequency is in MHz,
3847                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3848                  * divisors, it is necessary to divide one by another, so we
3849                  * convert the virtual clock precision to KHz here for higher
3850                  * precision.
3851                  */
3852                 u32 iclk_virtual_root_freq = 172800 * 1000;
3853                 u32 iclk_pi_range = 64;
3854                 u32 desired_divisor, msb_divisor_value, pi_value;
3855 
3856                 desired_divisor = (iclk_virtual_root_freq / clock);
3857                 msb_divisor_value = desired_divisor / iclk_pi_range;
3858                 pi_value = desired_divisor % iclk_pi_range;
3859 
3860                 auxdiv = 0;
3861                 divsel = msb_divisor_value - 2;
3862                 phaseinc = pi_value;
3863         }
3864 
3865         /* This should not happen with any sane values */
3866         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3867                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3868         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3869                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3870 
3871         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3872                         clock,
3873                         auxdiv,
3874                         divsel,
3875                         phasedir,
3876                         phaseinc);
3877 
3878         /* Program SSCDIVINTPHASE6 */
3879         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3880         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3881         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3882         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3883         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3884         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3885         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3886         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3887 
3888         /* Program SSCAUXDIV */
3889         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3890         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3891         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3892         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3893 
3894         /* Enable modulator and associated divider */
3895         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3896         temp &= ~SBI_SSCCTL_DISABLE;
3897         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3898 
3899         /* Wait for initialization time */
3900         udelay(24);
3901 
3902         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903 
3904         mutex_unlock(&dev_priv->dpio_lock);
3905 }
3906 
3907 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3908                                                 enum pipe pch_transcoder)
3909 {
3910         struct drm_device *dev = crtc->base.dev;
3911         struct drm_i915_private *dev_priv = dev->dev_private;
3912         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3913 
3914         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3915                    I915_READ(HTOTAL(cpu_transcoder)));
3916         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3917                    I915_READ(HBLANK(cpu_transcoder)));
3918         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3919                    I915_READ(HSYNC(cpu_transcoder)));
3920 
3921         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3922                    I915_READ(VTOTAL(cpu_transcoder)));
3923         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3924                    I915_READ(VBLANK(cpu_transcoder)));
3925         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3926                    I915_READ(VSYNC(cpu_transcoder)));
3927         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3928                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3929 }
3930 
3931 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3932 {
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934         uint32_t temp;
3935 
3936         temp = I915_READ(SOUTH_CHICKEN1);
3937         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3938                 return;
3939 
3940         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3941         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3942 
3943         temp &= ~FDI_BC_BIFURCATION_SELECT;
3944         if (enable)
3945                 temp |= FDI_BC_BIFURCATION_SELECT;
3946 
3947         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3948         I915_WRITE(SOUTH_CHICKEN1, temp);
3949         POSTING_READ(SOUTH_CHICKEN1);
3950 }
3951 
3952 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3953 {
3954         struct drm_device *dev = intel_crtc->base.dev;
3955 
3956         switch (intel_crtc->pipe) {
3957         case PIPE_A:
3958                 break;
3959         case PIPE_B:
3960                 if (intel_crtc->config->fdi_lanes > 2)
3961                         cpt_set_fdi_bc_bifurcation(dev, false);
3962                 else
3963                         cpt_set_fdi_bc_bifurcation(dev, true);
3964 
3965                 break;
3966         case PIPE_C:
3967                 cpt_set_fdi_bc_bifurcation(dev, true);
3968 
3969                 break;
3970         default:
3971                 BUG();
3972         }
3973 }
3974 
3975 /*
3976  * Enable PCH resources required for PCH ports:
3977  *   - PCH PLLs
3978  *   - FDI training & RX/TX
3979  *   - update transcoder timings
3980  *   - DP transcoding bits
3981  *   - transcoder
3982  */
3983 static void ironlake_pch_enable(struct drm_crtc *crtc)
3984 {
3985         struct drm_device *dev = crtc->dev;
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988         int pipe = intel_crtc->pipe;
3989         u32 reg, temp;
3990 
3991         assert_pch_transcoder_disabled(dev_priv, pipe);
3992 
3993         if (IS_IVYBRIDGE(dev))
3994                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3995 
3996         /* Write the TU size bits before fdi link training, so that error
3997          * detection works. */
3998         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3999                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4000 
4001         /* For PCH output, training FDI link */
4002         dev_priv->display.fdi_link_train(crtc);
4003 
4004         /* We need to program the right clock selection before writing the pixel
4005          * mutliplier into the DPLL. */
4006         if (HAS_PCH_CPT(dev)) {
4007                 u32 sel;
4008 
4009                 temp = I915_READ(PCH_DPLL_SEL);
4010                 temp |= TRANS_DPLL_ENABLE(pipe);
4011                 sel = TRANS_DPLLB_SEL(pipe);
4012                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4013                         temp |= sel;
4014                 else
4015                         temp &= ~sel;
4016                 I915_WRITE(PCH_DPLL_SEL, temp);
4017         }
4018 
4019         /* XXX: pch pll's can be enabled any time before we enable the PCH
4020          * transcoder, and we actually should do this to not upset any PCH
4021          * transcoder that already use the clock when we share it.
4022          *
4023          * Note that enable_shared_dpll tries to do the right thing, but
4024          * get_shared_dpll unconditionally resets the pll - we need that to have
4025          * the right LVDS enable sequence. */
4026         intel_enable_shared_dpll(intel_crtc);
4027 
4028         /* set transcoder timing, panel must allow it */
4029         assert_panel_unlocked(dev_priv, pipe);
4030         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4031 
4032         intel_fdi_normal_train(crtc);
4033 
4034         /* For PCH DP, enable TRANS_DP_CTL */
4035         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4036                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4037                 reg = TRANS_DP_CTL(pipe);
4038                 temp = I915_READ(reg);
4039                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4040                           TRANS_DP_SYNC_MASK |
4041                           TRANS_DP_BPC_MASK);
4042                 temp |= (TRANS_DP_OUTPUT_ENABLE |
4043                          TRANS_DP_ENH_FRAMING);
4044                 temp |= bpc << 9; /* same format but at 11:9 */
4045 
4046                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4047                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4048                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4049                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4050 
4051                 switch (intel_trans_dp_port_sel(crtc)) {
4052                 case PCH_DP_B:
4053                         temp |= TRANS_DP_PORT_SEL_B;
4054                         break;
4055                 case PCH_DP_C:
4056                         temp |= TRANS_DP_PORT_SEL_C;
4057                         break;
4058                 case PCH_DP_D:
4059                         temp |= TRANS_DP_PORT_SEL_D;
4060                         break;
4061                 default:
4062                         BUG();
4063                 }
4064 
4065                 I915_WRITE(reg, temp);
4066         }
4067 
4068         ironlake_enable_pch_transcoder(dev_priv, pipe);
4069 }
4070 
4071 static void lpt_pch_enable(struct drm_crtc *crtc)
4072 {
4073         struct drm_device *dev = crtc->dev;
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4076         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4077 
4078         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4079 
4080         lpt_program_iclkip(crtc);
4081 
4082         /* Set transcoder timing. */
4083         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4084 
4085         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4086 }
4087 
4088 void intel_put_shared_dpll(struct intel_crtc *crtc)
4089 {
4090         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4091 
4092         if (pll == NULL)
4093                 return;
4094 
4095         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4096                 WARN(1, "bad %s crtc mask\n", pll->name);
4097                 return;
4098         }
4099 
4100         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4101         if (pll->config.crtc_mask == 0) {
4102                 WARN_ON(pll->on);
4103                 WARN_ON(pll->active);
4104         }
4105 
4106         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4107 }
4108 
4109 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4110                                                 struct intel_crtc_state *crtc_state)
4111 {
4112         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4113         struct intel_shared_dpll *pll;
4114         enum intel_dpll_id i;
4115 
4116         if (HAS_PCH_IBX(dev_priv->dev)) {
4117                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4118                 i = (enum intel_dpll_id) crtc->pipe;
4119                 pll = &dev_priv->shared_dplls[i];
4120 
4121                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4122                               crtc->base.base.id, pll->name);
4123 
4124                 WARN_ON(pll->new_config->crtc_mask);
4125 
4126                 goto found;
4127         }
4128 
4129         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4130                 pll = &dev_priv->shared_dplls[i];
4131 
4132                 /* Only want to check enabled timings first */
4133                 if (pll->new_config->crtc_mask == 0)
4134                         continue;
4135 
4136                 if (memcmp(&crtc_state->dpll_hw_state,
4137                            &pll->new_config->hw_state,
4138                            sizeof(pll->new_config->hw_state)) == 0) {
4139                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4140                                       crtc->base.base.id, pll->name,
4141                                       pll->new_config->crtc_mask,
4142                                       pll->active);
4143                         goto found;
4144                 }
4145         }
4146 
4147         /* Ok no matching timings, maybe there's a free one? */
4148         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4149                 pll = &dev_priv->shared_dplls[i];
4150                 if (pll->new_config->crtc_mask == 0) {
4151                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4152                                       crtc->base.base.id, pll->name);
4153                         goto found;
4154                 }
4155         }
4156 
4157         return NULL;
4158 
4159 found:
4160         if (pll->new_config->crtc_mask == 0)
4161                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4162 
4163         crtc_state->shared_dpll = i;
4164         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4165                          pipe_name(crtc->pipe));
4166 
4167         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4168 
4169         return pll;
4170 }
4171 
4172 /**
4173  * intel_shared_dpll_start_config - start a new PLL staged config
4174  * @dev_priv: DRM device
4175  * @clear_pipes: mask of pipes that will have their PLLs freed
4176  *
4177  * Starts a new PLL staged config, copying the current config but
4178  * releasing the references of pipes specified in clear_pipes.
4179  */
4180 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4181                                           unsigned clear_pipes)
4182 {
4183         struct intel_shared_dpll *pll;
4184         enum intel_dpll_id i;
4185 
4186         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4187                 pll = &dev_priv->shared_dplls[i];
4188 
4189                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4190                                           GFP_KERNEL);
4191                 if (!pll->new_config)
4192                         goto cleanup;
4193 
4194                 pll->new_config->crtc_mask &= ~clear_pipes;
4195         }
4196 
4197         return 0;
4198 
4199 cleanup:
4200         while (--i >= 0) {
4201                 pll = &dev_priv->shared_dplls[i];
4202                 kfree(pll->new_config);
4203                 pll->new_config = NULL;
4204         }
4205 
4206         return -ENOMEM;
4207 }
4208 
4209 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4210 {
4211         struct intel_shared_dpll *pll;
4212         enum intel_dpll_id i;
4213 
4214         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4215                 pll = &dev_priv->shared_dplls[i];
4216 
4217                 WARN_ON(pll->new_config == &pll->config);
4218 
4219                 pll->config = *pll->new_config;
4220                 kfree(pll->new_config);
4221                 pll->new_config = NULL;
4222         }
4223 }
4224 
4225 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4226 {
4227         struct intel_shared_dpll *pll;
4228         enum intel_dpll_id i;
4229 
4230         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231                 pll = &dev_priv->shared_dplls[i];
4232 
4233                 WARN_ON(pll->new_config == &pll->config);
4234 
4235                 kfree(pll->new_config);
4236                 pll->new_config = NULL;
4237         }
4238 }
4239 
4240 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4241 {
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243         int dslreg = PIPEDSL(pipe);
4244         u32 temp;
4245 
4246         temp = I915_READ(dslreg);
4247         udelay(500);
4248         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4249                 if (wait_for(I915_READ(dslreg) != temp, 5))
4250                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4251         }
4252 }
4253 
4254 static void skylake_pfit_enable(struct intel_crtc *crtc)
4255 {
4256         struct drm_device *dev = crtc->base.dev;
4257         struct drm_i915_private *dev_priv = dev->dev_private;
4258         int pipe = crtc->pipe;
4259 
4260         if (crtc->config->pch_pfit.enabled) {
4261                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4262                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4263                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4264         }
4265 }
4266 
4267 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4268 {
4269         struct drm_device *dev = crtc->base.dev;
4270         struct drm_i915_private *dev_priv = dev->dev_private;
4271         int pipe = crtc->pipe;
4272 
4273         if (crtc->config->pch_pfit.enabled) {
4274                 /* Force use of hard-coded filter coefficients
4275                  * as some pre-programmed values are broken,
4276                  * e.g. x201.
4277                  */
4278                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4279                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4280                                                  PF_PIPE_SEL_IVB(pipe));
4281                 else
4282                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4283                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4284                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4285         }
4286 }
4287 
4288 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4289 {
4290         struct drm_device *dev = crtc->dev;
4291         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4292         struct drm_plane *plane;
4293         struct intel_plane *intel_plane;
4294 
4295         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4296                 intel_plane = to_intel_plane(plane);
4297                 if (intel_plane->pipe == pipe)
4298                         intel_plane_restore(&intel_plane->base);
4299         }
4300 }
4301 
4302 /*
4303  * Disable a plane internally without actually modifying the plane's state.
4304  * This will allow us to easily restore the plane later by just reprogramming
4305  * its state.
4306  */
4307 static void disable_plane_internal(struct drm_plane *plane)
4308 {
4309         struct intel_plane *intel_plane = to_intel_plane(plane);
4310         struct drm_plane_state *state =
4311                 plane->funcs->atomic_duplicate_state(plane);
4312         struct intel_plane_state *intel_state = to_intel_plane_state(state);
4313 
4314         intel_state->visible = false;
4315         intel_plane->commit_plane(plane, intel_state);
4316 
4317         intel_plane_destroy_state(plane, state);
4318 }
4319 
4320 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4321 {
4322         struct drm_device *dev = crtc->dev;
4323         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4324         struct drm_plane *plane;
4325         struct intel_plane *intel_plane;
4326 
4327         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4328                 intel_plane = to_intel_plane(plane);
4329                 if (plane->fb && intel_plane->pipe == pipe)
4330                         disable_plane_internal(plane);
4331         }
4332 }
4333 
4334 void hsw_enable_ips(struct intel_crtc *crtc)
4335 {
4336         struct drm_device *dev = crtc->base.dev;
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338 
4339         if (!crtc->config->ips_enabled)
4340                 return;
4341 
4342         /* We can only enable IPS after we enable a plane and wait for a vblank */
4343         intel_wait_for_vblank(dev, crtc->pipe);
4344 
4345         assert_plane_enabled(dev_priv, crtc->plane);
4346         if (IS_BROADWELL(dev)) {
4347                 mutex_lock(&dev_priv->rps.hw_lock);
4348                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4349                 mutex_unlock(&dev_priv->rps.hw_lock);
4350                 /* Quoting Art Runyan: "its not safe to expect any particular
4351                  * value in IPS_CTL bit 31 after enabling IPS through the
4352                  * mailbox." Moreover, the mailbox may return a bogus state,
4353                  * so we need to just enable it and continue on.
4354                  */
4355         } else {
4356                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4357                 /* The bit only becomes 1 in the next vblank, so this wait here
4358                  * is essentially intel_wait_for_vblank. If we don't have this
4359                  * and don't wait for vblanks until the end of crtc_enable, then
4360                  * the HW state readout code will complain that the expected
4361                  * IPS_CTL value is not the one we read. */
4362                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4363                         DRM_ERROR("Timed out waiting for IPS enable\n");
4364         }
4365 }
4366 
4367 void hsw_disable_ips(struct intel_crtc *crtc)
4368 {
4369         struct drm_device *dev = crtc->base.dev;
4370         struct drm_i915_private *dev_priv = dev->dev_private;
4371 
4372         if (!crtc->config->ips_enabled)
4373                 return;
4374 
4375         assert_plane_enabled(dev_priv, crtc->plane);
4376         if (IS_BROADWELL(dev)) {
4377                 mutex_lock(&dev_priv->rps.hw_lock);
4378                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4379                 mutex_unlock(&dev_priv->rps.hw_lock);
4380                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4381                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4382                         DRM_ERROR("Timed out waiting for IPS disable\n");
4383         } else {
4384                 I915_WRITE(IPS_CTL, 0);
4385                 POSTING_READ(IPS_CTL);
4386         }
4387 
4388         /* We need to wait for a vblank before we can disable the plane. */
4389         intel_wait_for_vblank(dev, crtc->pipe);
4390 }
4391 
4392 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4393 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4394 {
4395         struct drm_device *dev = crtc->dev;
4396         struct drm_i915_private *dev_priv = dev->dev_private;
4397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398         enum pipe pipe = intel_crtc->pipe;
4399         int palreg = PALETTE(pipe);
4400         int i;
4401         bool reenable_ips = false;
4402 
4403         /* The clocks have to be on to load the palette. */
4404         if (!crtc->state->enable || !intel_crtc->active)
4405                 return;
4406 
4407         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4408                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4409                         assert_dsi_pll_enabled(dev_priv);
4410                 else
4411                         assert_pll_enabled(dev_priv, pipe);
4412         }
4413 
4414         /* use legacy palette for Ironlake */
4415         if (!HAS_GMCH_DISPLAY(dev))
4416                 palreg = LGC_PALETTE(pipe);
4417 
4418         /* Workaround : Do not read or write the pipe palette/gamma data while
4419          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4420          */
4421         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4422             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4423              GAMMA_MODE_MODE_SPLIT)) {
4424                 hsw_disable_ips(intel_crtc);
4425                 reenable_ips = true;
4426         }
4427 
4428         for (i = 0; i < 256; i++) {
4429                 I915_WRITE(palreg + 4 * i,
4430                            (intel_crtc->lut_r[i] << 16) |
4431                            (intel_crtc->lut_g[i] << 8) |
4432                            intel_crtc->lut_b[i]);
4433         }
4434 
4435         if (reenable_ips)
4436                 hsw_enable_ips(intel_crtc);
4437 }
4438 
4439 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4440 {
4441         if (!enable && intel_crtc->overlay) {
4442                 struct drm_device *dev = intel_crtc->base.dev;
4443                 struct drm_i915_private *dev_priv = dev->dev_private;
4444 
4445                 mutex_lock(&dev->struct_mutex);
4446                 dev_priv->mm.interruptible = false;
4447                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4448                 dev_priv->mm.interruptible = true;
4449                 mutex_unlock(&dev->struct_mutex);
4450         }
4451 
4452         /* Let userspace switch the overlay on again. In most cases userspace
4453          * has to recompute where to put it anyway.
4454          */
4455 }
4456 
4457 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4458 {
4459         struct drm_device *dev = crtc->dev;
4460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461         int pipe = intel_crtc->pipe;
4462 
4463         intel_enable_primary_hw_plane(crtc->primary, crtc);
4464         intel_enable_sprite_planes(crtc);
4465         intel_crtc_update_cursor(crtc, true);
4466         intel_crtc_dpms_overlay(intel_crtc, true);
4467 
4468         hsw_enable_ips(intel_crtc);
4469 
4470         mutex_lock(&dev->struct_mutex);
4471         intel_fbc_update(dev);
4472         mutex_unlock(&dev->struct_mutex);
4473 
4474         /*
4475          * FIXME: Once we grow proper nuclear flip support out of this we need
4476          * to compute the mask of flip planes precisely. For the time being
4477          * consider this a flip from a NULL plane.
4478          */
4479         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4480 }
4481 
4482 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4483 {
4484         struct drm_device *dev = crtc->dev;
4485         struct drm_i915_private *dev_priv = dev->dev_private;
4486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4487         int pipe = intel_crtc->pipe;
4488 
4489         intel_crtc_wait_for_pending_flips(crtc);
4490 
4491         if (dev_priv->fbc.crtc == intel_crtc)
4492                 intel_fbc_disable(dev);
4493 
4494         hsw_disable_ips(intel_crtc);
4495 
4496         intel_crtc_dpms_overlay(intel_crtc, false);
4497         intel_crtc_update_cursor(crtc, false);
4498         intel_disable_sprite_planes(crtc);
4499         intel_disable_primary_hw_plane(crtc->primary, crtc);
4500 
4501         /*
4502          * FIXME: Once we grow proper nuclear flip support out of this we need
4503          * to compute the mask of flip planes precisely. For the time being
4504          * consider this a flip to a NULL plane.
4505          */
4506         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4507 }
4508 
4509 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4510 {
4511         struct drm_device *dev = crtc->dev;
4512         struct drm_i915_private *dev_priv = dev->dev_private;
4513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514         struct intel_encoder *encoder;
4515         int pipe = intel_crtc->pipe;
4516 
4517         WARN_ON(!crtc->state->enable);
4518 
4519         if (intel_crtc->active)
4520                 return;
4521 
4522         if (intel_crtc->config->has_pch_encoder)
4523                 intel_prepare_shared_dpll(intel_crtc);
4524 
4525         if (intel_crtc->config->has_dp_encoder)
4526                 intel_dp_set_m_n(intel_crtc, M1_N1);
4527 
4528         intel_set_pipe_timings(intel_crtc);
4529 
4530         if (intel_crtc->config->has_pch_encoder) {
4531                 intel_cpu_transcoder_set_m_n(intel_crtc,
4532                                      &intel_crtc->config->fdi_m_n, NULL);
4533         }
4534 
4535         ironlake_set_pipeconf(crtc);
4536 
4537         intel_crtc->active = true;
4538 
4539         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4540         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4541 
4542         for_each_encoder_on_crtc(dev, crtc, encoder)
4543                 if (encoder->pre_enable)
4544                         encoder->pre_enable(encoder);
4545 
4546         if (intel_crtc->config->has_pch_encoder) {
4547                 /* Note: FDI PLL enabling _must_ be done before we enable the
4548                  * cpu pipes, hence this is separate from all the other fdi/pch
4549                  * enabling. */
4550                 ironlake_fdi_pll_enable(intel_crtc);
4551         } else {
4552                 assert_fdi_tx_disabled(dev_priv, pipe);
4553                 assert_fdi_rx_disabled(dev_priv, pipe);
4554         }
4555 
4556         ironlake_pfit_enable(intel_crtc);
4557 
4558         /*
4559          * On ILK+ LUT must be loaded before the pipe is running but with
4560          * clocks enabled
4561          */
4562         intel_crtc_load_lut(crtc);
4563 
4564         intel_update_watermarks(crtc);
4565         intel_enable_pipe(intel_crtc);
4566 
4567         if (intel_crtc->config->has_pch_encoder)
4568                 ironlake_pch_enable(crtc);
4569 
4570         assert_vblank_disabled(crtc);
4571         drm_crtc_vblank_on(crtc);
4572 
4573         for_each_encoder_on_crtc(dev, crtc, encoder)
4574                 encoder->enable(encoder);
4575 
4576         if (HAS_PCH_CPT(dev))
4577                 cpt_verify_modeset(dev, intel_crtc->pipe);
4578 
4579         intel_crtc_enable_planes(crtc);
4580 }
4581 
4582 /* IPS only exists on ULT machines and is tied to pipe A. */
4583 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4584 {
4585         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4586 }
4587 
4588 /*
4589  * This implements the workaround described in the "notes" section of the mode
4590  * set sequence documentation. When going from no pipes or single pipe to
4591  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4592  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4593  */
4594 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4595 {
4596         struct drm_device *dev = crtc->base.dev;
4597         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4598 
4599         /* We want to get the other_active_crtc only if there's only 1 other
4600          * active crtc. */
4601         for_each_intel_crtc(dev, crtc_it) {
4602                 if (!crtc_it->active || crtc_it == crtc)
4603                         continue;
4604 
4605                 if (other_active_crtc)
4606                         return;
4607 
4608                 other_active_crtc = crtc_it;
4609         }
4610         if (!other_active_crtc)
4611                 return;
4612 
4613         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4614         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4615 }
4616 
4617 static void haswell_crtc_enable(struct drm_crtc *crtc)
4618 {
4619         struct drm_device *dev = crtc->dev;
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622         struct intel_encoder *encoder;
4623         int pipe = intel_crtc->pipe;
4624 
4625         WARN_ON(!crtc->state->enable);
4626 
4627         if (intel_crtc->active)
4628                 return;
4629 
4630         if (intel_crtc_to_shared_dpll(intel_crtc))
4631                 intel_enable_shared_dpll(intel_crtc);
4632 
4633         if (intel_crtc->config->has_dp_encoder)
4634                 intel_dp_set_m_n(intel_crtc, M1_N1);
4635 
4636         intel_set_pipe_timings(intel_crtc);
4637 
4638         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4639                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4640                            intel_crtc->config->pixel_multiplier - 1);
4641         }
4642 
4643         if (intel_crtc->config->has_pch_encoder) {
4644                 intel_cpu_transcoder_set_m_n(intel_crtc,
4645                                      &intel_crtc->config->fdi_m_n, NULL);
4646         }
4647 
4648         haswell_set_pipeconf(crtc);
4649 
4650         intel_set_pipe_csc(crtc);
4651 
4652         intel_crtc->active = true;
4653 
4654         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4655         for_each_encoder_on_crtc(dev, crtc, encoder)
4656                 if (encoder->pre_enable)
4657                         encoder->pre_enable(encoder);
4658 
4659         if (intel_crtc->config->has_pch_encoder) {
4660                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4661                                                       true);
4662                 dev_priv->display.fdi_link_train(crtc);
4663         }
4664 
4665         intel_ddi_enable_pipe_clock(intel_crtc);
4666 
4667         if (IS_SKYLAKE(dev))
4668                 skylake_pfit_enable(intel_crtc);
4669         else
4670                 ironlake_pfit_enable(intel_crtc);
4671 
4672         /*
4673          * On ILK+ LUT must be loaded before the pipe is running but with
4674          * clocks enabled
4675          */
4676         intel_crtc_load_lut(crtc);
4677 
4678         intel_ddi_set_pipe_settings(crtc);
4679         intel_ddi_enable_transcoder_func(crtc);
4680 
4681         intel_update_watermarks(crtc);
4682         intel_enable_pipe(intel_crtc);
4683 
4684         if (intel_crtc->config->has_pch_encoder)
4685                 lpt_pch_enable(crtc);
4686 
4687         if (intel_crtc->config->dp_encoder_is_mst)
4688                 intel_ddi_set_vc_payload_alloc(crtc, true);
4689 
4690         assert_vblank_disabled(crtc);
4691         drm_crtc_vblank_on(crtc);
4692 
4693         for_each_encoder_on_crtc(dev, crtc, encoder) {
4694                 encoder->enable(encoder);
4695                 intel_opregion_notify_encoder(encoder, true);
4696         }
4697 
4698         /* If we change the relative order between pipe/planes enabling, we need
4699          * to change the workaround. */
4700         haswell_mode_set_planes_workaround(intel_crtc);
4701         intel_crtc_enable_planes(crtc);
4702 }
4703 
4704 static void skylake_pfit_disable(struct intel_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->base.dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         int pipe = crtc->pipe;
4709 
4710         /* To avoid upsetting the power well on haswell only disable the pfit if
4711          * it's in use. The hw state code will make sure we get this right. */
4712         if (crtc->config->pch_pfit.enabled) {
4713                 I915_WRITE(PS_CTL(pipe), 0);
4714                 I915_WRITE(PS_WIN_POS(pipe), 0);
4715                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4716         }
4717 }
4718 
4719 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4720 {
4721         struct drm_device *dev = crtc->base.dev;
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723         int pipe = crtc->pipe;
4724 
4725         /* To avoid upsetting the power well on haswell only disable the pfit if
4726          * it's in use. The hw state code will make sure we get this right. */
4727         if (crtc->config->pch_pfit.enabled) {
4728                 I915_WRITE(PF_CTL(pipe), 0);
4729                 I915_WRITE(PF_WIN_POS(pipe), 0);
4730                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4731         }
4732 }
4733 
4734 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4735 {
4736         struct drm_device *dev = crtc->dev;
4737         struct drm_i915_private *dev_priv = dev->dev_private;
4738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739         struct intel_encoder *encoder;
4740         int pipe = intel_crtc->pipe;
4741         u32 reg, temp;
4742 
4743         if (!intel_crtc->active)
4744                 return;
4745 
4746         intel_crtc_disable_planes(crtc);
4747 
4748         for_each_encoder_on_crtc(dev, crtc, encoder)
4749                 encoder->disable(encoder);
4750 
4751         drm_crtc_vblank_off(crtc);
4752         assert_vblank_disabled(crtc);
4753 
4754         if (intel_crtc->config->has_pch_encoder)
4755                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756 
4757         intel_disable_pipe(intel_crtc);
4758 
4759         ironlake_pfit_disable(intel_crtc);
4760 
4761         for_each_encoder_on_crtc(dev, crtc, encoder)
4762                 if (encoder->post_disable)
4763                         encoder->post_disable(encoder);
4764 
4765         if (intel_crtc->config->has_pch_encoder) {
4766                 ironlake_fdi_disable(crtc);
4767 
4768                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4769 
4770                 if (HAS_PCH_CPT(dev)) {
4771                         /* disable TRANS_DP_CTL */
4772                         reg = TRANS_DP_CTL(pipe);
4773                         temp = I915_READ(reg);
4774                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4775                                   TRANS_DP_PORT_SEL_MASK);
4776                         temp |= TRANS_DP_PORT_SEL_NONE;
4777                         I915_WRITE(reg, temp);
4778 
4779                         /* disable DPLL_SEL */
4780                         temp = I915_READ(PCH_DPLL_SEL);
4781                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4782                         I915_WRITE(PCH_DPLL_SEL, temp);
4783                 }
4784 
4785                 /* disable PCH DPLL */
4786                 intel_disable_shared_dpll(intel_crtc);
4787 
4788                 ironlake_fdi_pll_disable(intel_crtc);
4789         }
4790 
4791         intel_crtc->active = false;
4792         intel_update_watermarks(crtc);
4793 
4794         mutex_lock(&dev->struct_mutex);
4795         intel_fbc_update(dev);
4796         mutex_unlock(&dev->struct_mutex);
4797 }
4798 
4799 static void haswell_crtc_disable(struct drm_crtc *crtc)
4800 {
4801         struct drm_device *dev = crtc->dev;
4802         struct drm_i915_private *dev_priv = dev->dev_private;
4803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4804         struct intel_encoder *encoder;
4805         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4806 
4807         if (!intel_crtc->active)
4808                 return;
4809 
4810         intel_crtc_disable_planes(crtc);
4811 
4812         for_each_encoder_on_crtc(dev, crtc, encoder) {
4813                 intel_opregion_notify_encoder(encoder, false);
4814                 encoder->disable(encoder);
4815         }
4816 
4817         drm_crtc_vblank_off(crtc);
4818         assert_vblank_disabled(crtc);
4819 
4820         if (intel_crtc->config->has_pch_encoder)
4821                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4822                                                       false);
4823         intel_disable_pipe(intel_crtc);
4824 
4825         if (intel_crtc->config->dp_encoder_is_mst)
4826                 intel_ddi_set_vc_payload_alloc(crtc, false);
4827 
4828         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4829 
4830         if (IS_SKYLAKE(dev))
4831                 skylake_pfit_disable(intel_crtc);
4832         else
4833                 ironlake_pfit_disable(intel_crtc);
4834 
4835         intel_ddi_disable_pipe_clock(intel_crtc);
4836 
4837         if (intel_crtc->config->has_pch_encoder) {
4838                 lpt_disable_pch_transcoder(dev_priv);
4839                 intel_ddi_fdi_disable(crtc);
4840         }
4841 
4842         for_each_encoder_on_crtc(dev, crtc, encoder)
4843                 if (encoder->post_disable)
4844                         encoder->post_disable(encoder);
4845 
4846         intel_crtc->active = false;
4847         intel_update_watermarks(crtc);
4848 
4849         mutex_lock(&dev->struct_mutex);
4850         intel_fbc_update(dev);
4851         mutex_unlock(&dev->struct_mutex);
4852 
4853         if (intel_crtc_to_shared_dpll(intel_crtc))
4854                 intel_disable_shared_dpll(intel_crtc);
4855 }
4856 
4857 static void ironlake_crtc_off(struct drm_crtc *crtc)
4858 {
4859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860         intel_put_shared_dpll(intel_crtc);
4861 }
4862 
4863 
4864 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4865 {
4866         struct drm_device *dev = crtc->base.dev;
4867         struct drm_i915_private *dev_priv = dev->dev_private;
4868         struct intel_crtc_state *pipe_config = crtc->config;
4869 
4870         if (!pipe_config->gmch_pfit.control)
4871                 return;
4872 
4873         /*
4874          * The panel fitter should only be adjusted whilst the pipe is disabled,
4875          * according to register description and PRM.
4876          */
4877         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4878         assert_pipe_disabled(dev_priv, crtc->pipe);
4879 
4880         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4881         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4882 
4883         /* Border color in case we don't scale up to the full screen. Black by
4884          * default, change to something else for debugging. */
4885         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4886 }
4887 
4888 static enum intel_display_power_domain port_to_power_domain(enum port port)
4889 {
4890         switch (port) {
4891         case PORT_A:
4892                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4893         case PORT_B:
4894                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4895         case PORT_C:
4896                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4897         case PORT_D:
4898                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4899         default:
4900                 WARN_ON_ONCE(1);
4901                 return POWER_DOMAIN_PORT_OTHER;
4902         }
4903 }
4904 
4905 #define for_each_power_domain(domain, mask)                             \
4906         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4907                 if ((1 << (domain)) & (mask))
4908 
4909 enum intel_display_power_domain
4910 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4911 {
4912         struct drm_device *dev = intel_encoder->base.dev;
4913         struct intel_digital_port *intel_dig_port;
4914 
4915         switch (intel_encoder->type) {
4916         case INTEL_OUTPUT_UNKNOWN:
4917                 /* Only DDI platforms should ever use this output type */
4918                 WARN_ON_ONCE(!HAS_DDI(dev));
4919         case INTEL_OUTPUT_DISPLAYPORT:
4920         case INTEL_OUTPUT_HDMI:
4921         case INTEL_OUTPUT_EDP:
4922                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4923                 return port_to_power_domain(intel_dig_port->port);
4924         case INTEL_OUTPUT_DP_MST:
4925                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4926                 return port_to_power_domain(intel_dig_port->port);
4927         case INTEL_OUTPUT_ANALOG:
4928                 return POWER_DOMAIN_PORT_CRT;
4929         case INTEL_OUTPUT_DSI:
4930                 return POWER_DOMAIN_PORT_DSI;
4931         default:
4932                 return POWER_DOMAIN_PORT_OTHER;
4933         }
4934 }
4935 
4936 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4937 {
4938         struct drm_device *dev = crtc->dev;
4939         struct intel_encoder *intel_encoder;
4940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941         enum pipe pipe = intel_crtc->pipe;
4942         unsigned long mask;
4943         enum transcoder transcoder;
4944 
4945         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4946 
4947         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4948         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4949         if (intel_crtc->config->pch_pfit.enabled ||
4950             intel_crtc->config->pch_pfit.force_thru)
4951                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4952 
4953         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4954                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4955 
4956         return mask;
4957 }
4958 
4959 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
4960 {
4961         struct drm_device *dev = state->dev;
4962         struct drm_i915_private *dev_priv = dev->dev_private;
4963         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4964         struct intel_crtc *crtc;
4965 
4966         /*
4967          * First get all needed power domains, then put all unneeded, to avoid
4968          * any unnecessary toggling of the power wells.
4969          */
4970         for_each_intel_crtc(dev, crtc) {
4971                 enum intel_display_power_domain domain;
4972 
4973                 if (!crtc->base.state->enable)
4974                         continue;
4975 
4976                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4977 
4978                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4979                         intel_display_power_get(dev_priv, domain);
4980         }
4981 
4982         if (dev_priv->display.modeset_global_resources)
4983                 dev_priv->display.modeset_global_resources(state);
4984 
4985         for_each_intel_crtc(dev, crtc) {
4986                 enum intel_display_power_domain domain;
4987 
4988                 for_each_power_domain(domain, crtc->enabled_power_domains)
4989                         intel_display_power_put(dev_priv, domain);
4990 
4991                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4992         }
4993 
4994         intel_display_set_init_power(dev_priv, false);
4995 }
4996 
4997 /* returns HPLL frequency in kHz */
4998 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4999 {
5000         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5001 
5002         /* Obtain SKU information */
5003         mutex_lock(&dev_priv->dpio_lock);
5004         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5005                 CCK_FUSE_HPLL_FREQ_MASK;
5006         mutex_unlock(&dev_priv->dpio_lock);
5007 
5008         return vco_freq[hpll_freq] * 1000;
5009 }
5010 
5011 static void vlv_update_cdclk(struct drm_device *dev)
5012 {
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014 
5015         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5016         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5017                          dev_priv->vlv_cdclk_freq);
5018 
5019         /*
5020          * Program the gmbus_freq based on the cdclk frequency.
5021          * BSpec erroneously claims we should aim for 4MHz, but
5022          * in fact 1MHz is the correct frequency.
5023          */
5024         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
5025 }
5026 
5027 /* Adjust CDclk dividers to allow high res or save power if possible */
5028 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5029 {
5030         struct drm_i915_private *dev_priv = dev->dev_private;
5031         u32 val, cmd;
5032 
5033         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5034 
5035         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5036                 cmd = 2;
5037         else if (cdclk == 266667)
5038                 cmd = 1;
5039         else
5040                 cmd = 0;
5041 
5042         mutex_lock(&dev_priv->rps.hw_lock);
5043         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5044         val &= ~DSPFREQGUAR_MASK;
5045         val |= (cmd << DSPFREQGUAR_SHIFT);
5046         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5047         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5048                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5049                      50)) {
5050                 DRM_ERROR("timed out waiting for CDclk change\n");
5051         }
5052         mutex_unlock(&dev_priv->rps.hw_lock);
5053 
5054         if (cdclk == 400000) {
5055                 u32 divider;
5056 
5057                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5058 
5059                 mutex_lock(&dev_priv->dpio_lock);
5060                 /* adjust cdclk divider */
5061                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5062                 val &= ~DISPLAY_FREQUENCY_VALUES;
5063                 val |= divider;
5064                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5065 
5066                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5067                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5068                              50))
5069                         DRM_ERROR("timed out waiting for CDclk change\n");
5070                 mutex_unlock(&dev_priv->dpio_lock);
5071         }
5072 
5073         mutex_lock(&dev_priv->dpio_lock);
5074         /* adjust self-refresh exit latency value */
5075         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5076         val &= ~0x7f;
5077 
5078         /*
5079          * For high bandwidth configs, we set a higher latency in the bunit
5080          * so that the core display fetch happens in time to avoid underruns.
5081          */
5082         if (cdclk == 400000)
5083                 val |= 4500 / 250; /* 4.5 usec */
5084         else
5085                 val |= 3000 / 250; /* 3.0 usec */
5086         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5087         mutex_unlock(&dev_priv->dpio_lock);
5088 
5089         vlv_update_cdclk(dev);
5090 }
5091 
5092 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5093 {
5094         struct drm_i915_private *dev_priv = dev->dev_private;
5095         u32 val, cmd;
5096 
5097         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5098 
5099         switch (cdclk) {
5100         case 333333:
5101         case 320000:
5102         case 266667:
5103         case 200000:
5104                 break;
5105         default:
5106                 MISSING_CASE(cdclk);
5107                 return;
5108         }
5109 
5110         /*
5111          * Specs are full of misinformation, but testing on actual
5112          * hardware has shown that we just need to write the desired
5113          * CCK divider into the Punit register.
5114          */
5115         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5116 
5117         mutex_lock(&dev_priv->rps.hw_lock);
5118         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5119         val &= ~DSPFREQGUAR_MASK_CHV;
5120         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5121         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5122         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5123                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5124                      50)) {
5125                 DRM_ERROR("timed out waiting for CDclk change\n");
5126         }
5127         mutex_unlock(&dev_priv->rps.hw_lock);
5128 
5129         vlv_update_cdclk(dev);
5130 }
5131 
5132 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5133                                  int max_pixclk)
5134 {
5135         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5136         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5137 
5138         /*
5139          * Really only a few cases to deal with, as only 4 CDclks are supported:
5140          *   200MHz
5141          *   267MHz
5142          *   320/333MHz (depends on HPLL freq)
5143          *   400MHz (VLV only)
5144          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5145          * of the lower bin and adjust if needed.
5146          *
5147          * We seem to get an unstable or solid color picture at 200MHz.
5148          * Not sure what's wrong. For now use 200MHz only when all pipes
5149          * are off.
5150          */
5151         if (!IS_CHERRYVIEW(dev_priv) &&
5152             max_pixclk > freq_320*limit/100)
5153                 return 400000;
5154         else if (max_pixclk > 266667*limit/100)
5155                 return freq_320;
5156         else if (max_pixclk > 0)
5157                 return 266667;
5158         else
5159                 return 200000;
5160 }
5161 
5162 /* compute the max pixel clock for new configuration */
5163 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5164 {
5165         struct drm_device *dev = dev_priv->dev;
5166         struct intel_crtc *intel_crtc;
5167         int max_pixclk = 0;
5168 
5169         for_each_intel_crtc(dev, intel_crtc) {
5170                 if (intel_crtc->new_enabled)
5171                         max_pixclk = max(max_pixclk,
5172                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5173         }
5174 
5175         return max_pixclk;
5176 }
5177 
5178 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5179                                             unsigned *prepare_pipes)
5180 {
5181         struct drm_i915_private *dev_priv = dev->dev_private;
5182         struct intel_crtc *intel_crtc;
5183         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5184 
5185         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5186             dev_priv->vlv_cdclk_freq)
5187                 return;
5188 
5189         /* disable/enable all currently active pipes while we change cdclk */
5190         for_each_intel_crtc(dev, intel_crtc)
5191                 if (intel_crtc->base.state->enable)
5192                         *prepare_pipes |= (1 << intel_crtc->pipe);
5193 }
5194 
5195 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5196 {
5197         unsigned int credits, default_credits;
5198 
5199         if (IS_CHERRYVIEW(dev_priv))
5200                 default_credits = PFI_CREDIT(12);
5201         else
5202                 default_credits = PFI_CREDIT(8);
5203 
5204         if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5205                 /* CHV suggested value is 31 or 63 */
5206                 if (IS_CHERRYVIEW(dev_priv))
5207                         credits = PFI_CREDIT_31;
5208                 else
5209                         credits = PFI_CREDIT(15);
5210         } else {
5211                 credits = default_credits;
5212         }
5213 
5214         /*
5215          * WA - write default credits before re-programming
5216          * FIXME: should we also set the resend bit here?
5217          */
5218         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5219                    default_credits);
5220 
5221         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5222                    credits | PFI_CREDIT_RESEND);
5223 
5224         /*
5225          * FIXME is this guaranteed to clear
5226          * immediately or should we poll for it?
5227          */
5228         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5229 }
5230 
5231 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5232 {
5233         struct drm_device *dev = state->dev;
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5236         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5237 
5238         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5239                 /*
5240                  * FIXME: We can end up here with all power domains off, yet
5241                  * with a CDCLK frequency other than the minimum. To account
5242                  * for this take the PIPE-A power domain, which covers the HW
5243                  * blocks needed for the following programming. This can be
5244                  * removed once it's guaranteed that we get here either with
5245                  * the minimum CDCLK set, or the required power domains
5246                  * enabled.
5247                  */
5248                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5249 
5250                 if (IS_CHERRYVIEW(dev))
5251                         cherryview_set_cdclk(dev, req_cdclk);
5252                 else
5253                         valleyview_set_cdclk(dev, req_cdclk);
5254 
5255                 vlv_program_pfi_credits(dev_priv);
5256 
5257                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5258         }
5259 }
5260 
5261 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5262 {
5263         struct drm_device *dev = crtc->dev;
5264         struct drm_i915_private *dev_priv = to_i915(dev);
5265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266         struct intel_encoder *encoder;
5267         int pipe = intel_crtc->pipe;
5268         bool is_dsi;
5269 
5270         WARN_ON(!crtc->state->enable);
5271 
5272         if (intel_crtc->active)
5273                 return;
5274 
5275         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5276 
5277         if (!is_dsi) {
5278                 if (IS_CHERRYVIEW(dev))
5279                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5280                 else
5281                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5282         }
5283 
5284         if (intel_crtc->config->has_dp_encoder)
5285                 intel_dp_set_m_n(intel_crtc, M1_N1);
5286 
5287         intel_set_pipe_timings(intel_crtc);
5288 
5289         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5290                 struct drm_i915_private *dev_priv = dev->dev_private;
5291 
5292                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5293                 I915_WRITE(CHV_CANVAS(pipe), 0);
5294         }
5295 
5296         i9xx_set_pipeconf(intel_crtc);
5297 
5298         intel_crtc->active = true;
5299 
5300         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5301 
5302         for_each_encoder_on_crtc(dev, crtc, encoder)
5303                 if (encoder->pre_pll_enable)
5304                         encoder->pre_pll_enable(encoder);
5305 
5306         if (!is_dsi) {
5307                 if (IS_CHERRYVIEW(dev))
5308                         chv_enable_pll(intel_crtc, intel_crtc->config);
5309                 else
5310                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5311         }
5312 
5313         for_each_encoder_on_crtc(dev, crtc, encoder)
5314                 if (encoder->pre_enable)
5315                         encoder->pre_enable(encoder);
5316 
5317         i9xx_pfit_enable(intel_crtc);
5318 
5319         intel_crtc_load_lut(crtc);
5320 
5321         intel_update_watermarks(crtc);
5322         intel_enable_pipe(intel_crtc);
5323 
5324         assert_vblank_disabled(crtc);
5325         drm_crtc_vblank_on(crtc);
5326 
5327         for_each_encoder_on_crtc(dev, crtc, encoder)
5328                 encoder->enable(encoder);
5329 
5330         intel_crtc_enable_planes(crtc);
5331 
5332         /* Underruns don't raise interrupts, so check manually. */
5333         i9xx_check_fifo_underruns(dev_priv);
5334 }
5335 
5336 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5337 {
5338         struct drm_device *dev = crtc->base.dev;
5339         struct drm_i915_private *dev_priv = dev->dev_private;
5340 
5341         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5342         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5343 }
5344 
5345 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5346 {
5347         struct drm_device *dev = crtc->dev;
5348         struct drm_i915_private *dev_priv = to_i915(dev);
5349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350         struct intel_encoder *encoder;
5351         int pipe = intel_crtc->pipe;
5352 
5353         WARN_ON(!crtc->state->enable);
5354 
5355         if (intel_crtc->active)
5356                 return;
5357 
5358         i9xx_set_pll_dividers(intel_crtc);
5359 
5360         if (intel_crtc->config->has_dp_encoder)
5361                 intel_dp_set_m_n(intel_crtc, M1_N1);
5362 
5363         intel_set_pipe_timings(intel_crtc);
5364 
5365         i9xx_set_pipeconf(intel_crtc);
5366 
5367         intel_crtc->active = true;
5368 
5369         if (!IS_GEN2(dev))
5370                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5371 
5372         for_each_encoder_on_crtc(dev, crtc, encoder)
5373                 if (encoder->pre_enable)
5374                         encoder->pre_enable(encoder);
5375 
5376         i9xx_enable_pll(intel_crtc);
5377 
5378         i9xx_pfit_enable(intel_crtc);
5379 
5380         intel_crtc_load_lut(crtc);
5381 
5382         intel_update_watermarks(crtc);
5383         intel_enable_pipe(intel_crtc);
5384 
5385         assert_vblank_disabled(crtc);
5386         drm_crtc_vblank_on(crtc);
5387 
5388         for_each_encoder_on_crtc(dev, crtc, encoder)
5389                 encoder->enable(encoder);
5390 
5391         intel_crtc_enable_planes(crtc);
5392 
5393         /*
5394          * Gen2 reports pipe underruns whenever all planes are disabled.
5395          * So don't enable underrun reporting before at least some planes
5396          * are enabled.
5397          * FIXME: Need to fix the logic to work when we turn off all planes
5398          * but leave the pipe running.
5399          */
5400         if (IS_GEN2(dev))
5401                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5402 
5403         /* Underruns don't raise interrupts, so check manually. */
5404         i9xx_check_fifo_underruns(dev_priv);
5405 }
5406 
5407 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5408 {
5409         struct drm_device *dev = crtc->base.dev;
5410         struct drm_i915_private *dev_priv = dev->dev_private;
5411 
5412         if (!crtc->config->gmch_pfit.control)
5413                 return;
5414 
5415         assert_pipe_disabled(dev_priv, crtc->pipe);
5416 
5417         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5418                          I915_READ(PFIT_CONTROL));
5419         I915_WRITE(PFIT_CONTROL, 0);
5420 }
5421 
5422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5423 {
5424         struct drm_device *dev = crtc->dev;
5425         struct drm_i915_private *dev_priv = dev->dev_private;
5426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427         struct intel_encoder *encoder;
5428         int pipe = intel_crtc->pipe;
5429 
5430         if (!intel_crtc->active)
5431                 return;
5432 
5433         /*
5434          * Gen2 reports pipe underruns whenever all planes are disabled.
5435          * So diasble underrun reporting before all the planes get disabled.
5436          * FIXME: Need to fix the logic to work when we turn off all planes
5437          * but leave the pipe running.
5438          */
5439         if (IS_GEN2(dev))
5440                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5441 
5442         /*
5443          * Vblank time updates from the shadow to live plane control register
5444          * are blocked if the memory self-refresh mode is active at that
5445          * moment. So to make sure the plane gets truly disabled, disable
5446          * first the self-refresh mode. The self-refresh enable bit in turn
5447          * will be checked/applied by the HW only at the next frame start
5448          * event which is after the vblank start event, so we need to have a
5449          * wait-for-vblank between disabling the plane and the pipe.
5450          */
5451         intel_set_memory_cxsr(dev_priv, false);
5452         intel_crtc_disable_planes(crtc);
5453 
5454         /*
5455          * On gen2 planes are double buffered but the pipe isn't, so we must
5456          * wait for planes to fully turn off before disabling the pipe.
5457          * We also need to wait on all gmch platforms because of the
5458          * self-refresh mode constraint explained above.
5459          */
5460         intel_wait_for_vblank(dev, pipe);
5461 
5462         for_each_encoder_on_crtc(dev, crtc, encoder)
5463                 encoder->disable(encoder);
5464 
5465         drm_crtc_vblank_off(crtc);
5466         assert_vblank_disabled(crtc);
5467 
5468         intel_disable_pipe(intel_crtc);
5469 
5470         i9xx_pfit_disable(intel_crtc);
5471 
5472         for_each_encoder_on_crtc(dev, crtc, encoder)
5473                 if (encoder->post_disable)
5474                         encoder->post_disable(encoder);
5475 
5476         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5477                 if (IS_CHERRYVIEW(dev))
5478                         chv_disable_pll(dev_priv, pipe);
5479                 else if (IS_VALLEYVIEW(dev))
5480                         vlv_disable_pll(dev_priv, pipe);
5481                 else
5482                         i9xx_disable_pll(intel_crtc);
5483         }
5484 
5485         if (!IS_GEN2(dev))
5486                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5487 
5488         intel_crtc->active = false;
5489         intel_update_watermarks(crtc);
5490 
5491         mutex_lock(&dev->struct_mutex);
5492         intel_fbc_update(dev);
5493         mutex_unlock(&dev->struct_mutex);
5494 }
5495 
5496 static void i9xx_crtc_off(struct drm_crtc *crtc)
5497 {
5498 }
5499 
5500 /* Master function to enable/disable CRTC and corresponding power wells */
5501 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5502 {
5503         struct drm_device *dev = crtc->dev;
5504         struct drm_i915_private *dev_priv = dev->dev_private;
5505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5506         enum intel_display_power_domain domain;
5507         unsigned long domains;
5508 
5509         if (enable) {
5510                 if (!intel_crtc->active) {
5511                         domains = get_crtc_power_domains(crtc);
5512                         for_each_power_domain(domain, domains)
5513                                 intel_display_power_get(dev_priv, domain);
5514                         intel_crtc->enabled_power_domains = domains;
5515 
5516                         dev_priv->display.crtc_enable(crtc);
5517                 }
5518         } else {
5519                 if (intel_crtc->active) {
5520                         dev_priv->display.crtc_disable(crtc);
5521 
5522                         domains = intel_crtc->enabled_power_domains;
5523                         for_each_power_domain(domain, domains)
5524                                 intel_display_power_put(dev_priv, domain);
5525                         intel_crtc->enabled_power_domains = 0;
5526                 }
5527         }
5528 }
5529 
5530 /**
5531  * Sets the power management mode of the pipe and plane.
5532  */
5533 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5534 {
5535         struct drm_device *dev = crtc->dev;
5536         struct intel_encoder *intel_encoder;
5537         bool enable = false;
5538 
5539         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5540                 enable |= intel_encoder->connectors_active;
5541 
5542         intel_crtc_control(crtc, enable);
5543 }
5544 
5545 static void intel_crtc_disable(struct drm_crtc *crtc)
5546 {
5547         struct drm_device *dev = crtc->dev;
5548         struct drm_connector *connector;
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550 
5551         /* crtc should still be enabled when we disable it. */
5552         WARN_ON(!crtc->state->enable);
5553 
5554         dev_priv->display.crtc_disable(crtc);
5555         dev_priv->display.off(crtc);
5556 
5557         crtc->primary->funcs->disable_plane(crtc->primary);
5558 
5559         /* Update computed state. */
5560         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5561                 if (!connector->encoder || !connector->encoder->crtc)
5562                         continue;
5563 
5564                 if (connector->encoder->crtc != crtc)
5565                         continue;
5566 
5567                 connector->dpms = DRM_MODE_DPMS_OFF;
5568                 to_intel_encoder(connector->encoder)->connectors_active = false;
5569         }
5570 }
5571 
5572 void intel_encoder_destroy(struct drm_encoder *encoder)
5573 {
5574         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5575 
5576         drm_encoder_cleanup(encoder);
5577         kfree(intel_encoder);
5578 }
5579 
5580 /* Simple dpms helper for encoders with just one connector, no cloning and only
5581  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5582  * state of the entire output pipe. */
5583 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5584 {
5585         if (mode == DRM_MODE_DPMS_ON) {
5586                 encoder->connectors_active = true;
5587 
5588                 intel_crtc_update_dpms(encoder->base.crtc);
5589         } else {
5590                 encoder->connectors_active = false;
5591 
5592                 intel_crtc_update_dpms(encoder->base.crtc);
5593         }
5594 }
5595 
5596 /* Cross check the actual hw state with our own modeset state tracking (and it's
5597  * internal consistency). */
5598 static void intel_connector_check_state(struct intel_connector *connector)
5599 {
5600         if (connector->get_hw_state(connector)) {
5601                 struct intel_encoder *encoder = connector->encoder;
5602                 struct drm_crtc *crtc;
5603                 bool encoder_enabled;
5604                 enum pipe pipe;
5605 
5606                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5607                               connector->base.base.id,
5608                               connector->base.name);
5609 
5610                 /* there is no real hw state for MST connectors */
5611                 if (connector->mst_port)
5612                         return;
5613 
5614                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5615                      "wrong connector dpms state\n");
5616                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5617                      "active connector not linked to encoder\n");
5618 
5619                 if (encoder) {
5620                         I915_STATE_WARN(!encoder->connectors_active,
5621                              "encoder->connectors_active not set\n");
5622 
5623                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5624                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5625                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5626                                 return;
5627 
5628                         crtc = encoder->base.crtc;
5629 
5630                         I915_STATE_WARN(!crtc->state->enable,
5631                                         "crtc not enabled\n");
5632                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5633                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5634                              "encoder active on the wrong pipe\n");
5635                 }
5636         }
5637 }
5638 
5639 int intel_connector_init(struct intel_connector *connector)
5640 {
5641         struct drm_connector_state *connector_state;
5642 
5643         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
5644         if (!connector_state)
5645                 return -ENOMEM;
5646 
5647         connector->base.state = connector_state;
5648         return 0;
5649 }
5650 
5651 struct intel_connector *intel_connector_alloc(void)
5652 {
5653         struct intel_connector *connector;
5654 
5655         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5656         if (!connector)
5657                 return NULL;
5658 
5659         if (intel_connector_init(connector) < 0) {
5660                 kfree(connector);
5661                 return NULL;
5662         }
5663 
5664         return connector;
5665 }
5666 
5667 /* Even simpler default implementation, if there's really no special case to
5668  * consider. */
5669 void intel_connector_dpms(struct drm_connector *connector, int mode)
5670 {
5671         /* All the simple cases only support two dpms states. */
5672         if (mode != DRM_MODE_DPMS_ON)
5673                 mode = DRM_MODE_DPMS_OFF;
5674 
5675         if (mode == connector->dpms)
5676                 return;
5677 
5678         connector->dpms = mode;
5679 
5680         /* Only need to change hw state when actually enabled */
5681         if (connector->encoder)
5682                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5683 
5684         intel_modeset_check_state(connector->dev);
5685 }
5686 
5687 /* Simple connector->get_hw_state implementation for encoders that support only
5688  * one connector and no cloning and hence the encoder state determines the state
5689  * of the connector. */
5690 bool intel_connector_get_hw_state(struct intel_connector *connector)
5691 {
5692         enum pipe pipe = 0;
5693         struct intel_encoder *encoder = connector->encoder;
5694 
5695         return encoder->get_hw_state(encoder, &pipe);
5696 }
5697 
5698 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5699 {
5700         struct intel_crtc *crtc =
5701                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5702 
5703         if (crtc->base.state->enable &&
5704             crtc->config->has_pch_encoder)
5705                 return crtc->config->fdi_lanes;
5706 
5707         return 0;
5708 }
5709 
5710 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5711                                      struct intel_crtc_state *pipe_config)
5712 {
5713         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5714                       pipe_name(pipe), pipe_config->fdi_lanes);
5715         if (pipe_config->fdi_lanes > 4) {
5716                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5717                               pipe_name(pipe), pipe_config->fdi_lanes);
5718                 return false;
5719         }
5720 
5721         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5722                 if (pipe_config->fdi_lanes > 2) {
5723                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5724                                       pipe_config->fdi_lanes);
5725                         return false;
5726                 } else {
5727                         return true;
5728                 }
5729         }
5730 
5731         if (INTEL_INFO(dev)->num_pipes == 2)
5732                 return true;
5733 
5734         /* Ivybridge 3 pipe is really complicated */
5735         switch (pipe) {
5736         case PIPE_A:
5737                 return true;
5738         case PIPE_B:
5739                 if (pipe_config->fdi_lanes > 2 &&
5740                     pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5741                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5742                                       pipe_name(pipe), pipe_config->fdi_lanes);
5743                         return false;
5744                 }
5745                 return true;
5746         case PIPE_C:
5747                 if (pipe_config->fdi_lanes > 2) {
5748                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5749                                       pipe_name(pipe), pipe_config->fdi_lanes);
5750                         return false;
5751                 }
5752                 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5753                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5754                         return false;
5755                 }
5756                 return true;
5757         default:
5758                 BUG();
5759         }
5760 }
5761 
5762 #define RETRY 1
5763 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5764                                        struct intel_crtc_state *pipe_config)
5765 {
5766         struct drm_device *dev = intel_crtc->base.dev;
5767         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5768         int lane, link_bw, fdi_dotclock;
5769         bool setup_ok, needs_recompute = false;
5770 
5771 retry:
5772         /* FDI is a binary signal running at ~2.7GHz, encoding
5773          * each output octet as 10 bits. The actual frequency
5774          * is stored as a divider into a 100MHz clock, and the
5775          * mode pixel clock is stored in units of 1KHz.
5776          * Hence the bw of each lane in terms of the mode signal
5777          * is:
5778          */
5779         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5780 
5781         fdi_dotclock = adjusted_mode->crtc_clock;
5782 
5783         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5784                                            pipe_config->pipe_bpp);
5785 
5786         pipe_config->fdi_lanes = lane;
5787 
5788         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5789                                link_bw, &pipe_config->fdi_m_n);
5790 
5791         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5792                                             intel_crtc->pipe, pipe_config);
5793         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5794                 pipe_config->pipe_bpp -= 2*3;
5795                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5796                               pipe_config->pipe_bpp);
5797                 needs_recompute = true;
5798                 pipe_config->bw_constrained = true;
5799 
5800                 goto retry;
5801         }
5802 
5803         if (needs_recompute)
5804                 return RETRY;
5805 
5806         return setup_ok ? 0 : -EINVAL;
5807 }
5808 
5809 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5810                                    struct intel_crtc_state *pipe_config)
5811 {
5812         pipe_config->ips_enabled = i915.enable_ips &&
5813                                    hsw_crtc_supports_ips(crtc) &&
5814                                    pipe_config->pipe_bpp <= 24;
5815 }
5816 
5817 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5818                                      struct intel_crtc_state *pipe_config)
5819 {
5820         struct drm_device *dev = crtc->base.dev;
5821         struct drm_i915_private *dev_priv = dev->dev_private;
5822         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5823 
5824         /* FIXME should check pixel clock limits on all platforms */
5825         if (INTEL_INFO(dev)->gen < 4) {
5826                 int clock_limit =
5827                         dev_priv->display.get_display_clock_speed(dev);
5828 
5829                 /*
5830                  * Enable pixel doubling when the dot clock
5831                  * is > 90% of the (display) core speed.
5832                  *
5833                  * GDG double wide on either pipe,
5834                  * otherwise pipe A only.
5835                  */
5836                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5837                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5838                         clock_limit *= 2;
5839                         pipe_config->double_wide = true;
5840                 }
5841 
5842                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5843                         return -EINVAL;
5844         }
5845 
5846         /*
5847          * Pipe horizontal size must be even in:
5848          * - DVO ganged mode
5849          * - LVDS dual channel mode
5850          * - Double wide pipe
5851          */
5852         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
5853              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5854                 pipe_config->pipe_src_w &= ~1;
5855 
5856         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5857          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5858          */
5859         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5860                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5861                 return -EINVAL;
5862 
5863         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5864                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5865         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5866                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5867                  * for lvds. */
5868                 pipe_config->pipe_bpp = 8*3;
5869         }
5870 
5871         if (HAS_IPS(dev))
5872                 hsw_compute_ips_config(crtc, pipe_config);
5873 
5874         if (pipe_config->has_pch_encoder)
5875                 return ironlake_fdi_compute_config(crtc, pipe_config);
5876 
5877         return 0;
5878 }
5879 
5880 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5881 {
5882         struct drm_i915_private *dev_priv = dev->dev_private;
5883         u32 val;
5884         int divider;
5885 
5886         if (dev_priv->hpll_freq == 0)
5887                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5888 
5889         mutex_lock(&dev_priv->dpio_lock);
5890         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5891         mutex_unlock(&dev_priv->dpio_lock);
5892 
5893         divider = val & DISPLAY_FREQUENCY_VALUES;
5894 
5895         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5896              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5897              "cdclk change in progress\n");
5898 
5899         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5900 }
5901 
5902 static int i945_get_display_clock_speed(struct drm_device *dev)
5903 {
5904         return 400000;
5905 }
5906 
5907 static int i915_get_display_clock_speed(struct drm_device *dev)
5908 {
5909         return 333000;
5910 }
5911 
5912 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5913 {
5914         return 200000;
5915 }
5916 
5917 static int pnv_get_display_clock_speed(struct drm_device *dev)
5918 {
5919         u16 gcfgc = 0;
5920 
5921         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5922 
5923         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5924         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5925                 return 267000;
5926         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5927                 return 333000;
5928         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5929                 return 444000;
5930         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5931                 return 200000;
5932         default:
5933                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5934         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5935                 return 133000;
5936         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5937                 return 167000;
5938         }
5939 }
5940 
5941 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5942 {
5943         u16 gcfgc = 0;
5944 
5945         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5946 
5947         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5948                 return 133000;
5949         else {
5950                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5951                 case GC_DISPLAY_CLOCK_333_MHZ:
5952                         return 333000;
5953                 default:
5954                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5955                         return 190000;
5956                 }
5957         }
5958 }
5959 
5960 static int i865_get_display_clock_speed(struct drm_device *dev)
5961 {
5962         return 266000;
5963 }
5964 
5965 static int i855_get_display_clock_speed(struct drm_device *dev)
5966 {
5967         u16 hpllcc = 0;
5968         /* Assume that the hardware is in the high speed state.  This
5969          * should be the default.
5970          */
5971         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5972         case GC_CLOCK_133_200:
5973         case GC_CLOCK_100_200:
5974                 return 200000;
5975         case GC_CLOCK_166_250:
5976                 return 250000;
5977         case GC_CLOCK_100_133:
5978                 return 133000;
5979         }
5980 
5981         /* Shouldn't happen */
5982         return 0;
5983 }
5984 
5985 static int i830_get_display_clock_speed(struct drm_device *dev)
5986 {
5987         return 133000;
5988 }
5989 
5990 static void
5991 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5992 {
5993         while (*num > DATA_LINK_M_N_MASK ||
5994                *den > DATA_LINK_M_N_MASK) {
5995                 *num >>= 1;
5996                 *den >>= 1;
5997         }
5998 }
5999 
6000 static void compute_m_n(unsigned int m, unsigned int n,
6001                         uint32_t *ret_m, uint32_t *ret_n)
6002 {
6003         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6004         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6005         intel_reduce_m_n_ratio(ret_m, ret_n);
6006 }
6007 
6008 void
6009 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6010                        int pixel_clock, int link_clock,
6011                        struct intel_link_m_n *m_n)
6012 {
6013         m_n->tu = 64;
6014 
6015         compute_m_n(bits_per_pixel * pixel_clock,
6016                     link_clock * nlanes * 8,
6017                     &m_n->gmch_m, &m_n->gmch_n);
6018 
6019         compute_m_n(pixel_clock, link_clock,
6020                     &m_n->link_m, &m_n->link_n);
6021 }
6022 
6023 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6024 {
6025         if (i915.panel_use_ssc >= 0)
6026                 return i915.panel_use_ssc != 0;
6027         return dev_priv->vbt.lvds_use_ssc
6028                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6029 }
6030 
6031 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6032                            int num_connectors)
6033 {
6034         struct drm_device *dev = crtc_state->base.crtc->dev;
6035         struct drm_i915_private *dev_priv = dev->dev_private;
6036         int refclk;
6037 
6038         WARN_ON(!crtc_state->base.state);
6039 
6040         if (IS_VALLEYVIEW(dev)) {
6041                 refclk = 100000;
6042         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6043             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6044                 refclk = dev_priv->vbt.lvds_ssc_freq;
6045                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6046         } else if (!IS_GEN2(dev)) {
6047                 refclk = 96000;
6048         } else {
6049                 refclk = 48000;
6050         }
6051 
6052         return refclk;
6053 }
6054 
6055 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6056 {
6057         return (1 << dpll->n) << 16 | dpll->m2;
6058 }
6059 
6060 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6061 {
6062         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6063 }
6064 
6065 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6066                                      struct intel_crtc_state *crtc_state,
6067                                      intel_clock_t *reduced_clock)
6068 {
6069         struct drm_device *dev = crtc->base.dev;
6070         u32 fp, fp2 = 0;
6071 
6072         if (IS_PINEVIEW(dev)) {
6073                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6074                 if (reduced_clock)
6075                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6076         } else {
6077                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6078                 if (reduced_clock)
6079                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6080         }
6081 
6082         crtc_state->dpll_hw_state.fp0 = fp;
6083 
6084         crtc->lowfreq_avail = false;
6085         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6086             reduced_clock) {
6087                 crtc_state->dpll_hw_state.fp1 = fp2;
6088                 crtc->lowfreq_avail = true;
6089         } else {
6090                 crtc_state->dpll_hw_state.fp1 = fp;
6091         }
6092 }
6093 
6094 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6095                 pipe)
6096 {
6097         u32 reg_val;
6098 
6099         /*
6100          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6101          * and set it to a reasonable value instead.
6102          */
6103         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6104         reg_val &= 0xffffff00;
6105         reg_val |= 0x00000030;
6106         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6107 
6108         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6109         reg_val &= 0x8cffffff;
6110         reg_val = 0x8c000000;
6111         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6112 
6113         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6114         reg_val &= 0xffffff00;
6115         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6116 
6117         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6118         reg_val &= 0x00ffffff;
6119         reg_val |= 0xb0000000;
6120         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6121 }
6122 
6123 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6124                                          struct intel_link_m_n *m_n)
6125 {
6126         struct drm_device *dev = crtc->base.dev;
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128         int pipe = crtc->pipe;
6129 
6130         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6131         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6132         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6133         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6134 }
6135 
6136 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6137                                          struct intel_link_m_n *m_n,
6138                                          struct intel_link_m_n *m2_n2)
6139 {
6140         struct drm_device *dev = crtc->base.dev;
6141         struct drm_i915_private *dev_priv = dev->dev_private;
6142         int pipe = crtc->pipe;
6143         enum transcoder transcoder = crtc->config->cpu_transcoder;
6144 
6145         if (INTEL_INFO(dev)->gen >= 5) {
6146                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6147                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6148                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6149                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6150                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6151                  * for gen < 8) and if DRRS is supported (to make sure the
6152                  * registers are not unnecessarily accessed).
6153                  */
6154                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6155                         crtc->config->has_drrs) {
6156                         I915_WRITE(PIPE_DATA_M2(transcoder),
6157                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6158                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6159                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6160                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6161                 }
6162         } else {
6163                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6164                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6165                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6166                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6167         }
6168 }
6169 
6170 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6171 {
6172         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6173 
6174         if (m_n == M1_N1) {
6175                 dp_m_n = &crtc->config->dp_m_n;
6176                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6177         } else if (m_n == M2_N2) {
6178 
6179                 /*
6180                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6181                  * needs to be programmed into M1_N1.
6182                  */
6183                 dp_m_n = &crtc->config->dp_m2_n2;
6184         } else {
6185                 DRM_ERROR("Unsupported divider value\n");
6186                 return;
6187         }
6188 
6189         if (crtc->config->has_pch_encoder)
6190                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6191         else
6192                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6193 }
6194 
6195 static void vlv_update_pll(struct intel_crtc *crtc,
6196                            struct intel_crtc_state *pipe_config)
6197 {
6198         u32 dpll, dpll_md;
6199 
6200         /*
6201          * Enable DPIO clock input. We should never disable the reference
6202          * clock for pipe B, since VGA hotplug / manual detection depends
6203          * on it.
6204          */
6205         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6206                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6207         /* We should never disable this, set it here for state tracking */
6208         if (crtc->pipe == PIPE_B)
6209                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6210         dpll |= DPLL_VCO_ENABLE;
6211         pipe_config->dpll_hw_state.dpll = dpll;
6212 
6213         dpll_md = (pipe_config->pixel_multiplier - 1)
6214                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6215         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6216 }
6217 
6218 static void vlv_prepare_pll(struct intel_crtc *crtc,
6219                             const struct intel_crtc_state *pipe_config)
6220 {
6221         struct drm_device *dev = crtc->base.dev;
6222         struct drm_i915_private *dev_priv = dev->dev_private;
6223         int pipe = crtc->pipe;
6224         u32 mdiv;
6225         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6226         u32 coreclk, reg_val;
6227 
6228         mutex_lock(&dev_priv->dpio_lock);
6229 
6230         bestn = pipe_config->dpll.n;
6231         bestm1 = pipe_config->dpll.m1;
6232         bestm2 = pipe_config->dpll.m2;
6233         bestp1 = pipe_config->dpll.p1;
6234         bestp2 = pipe_config->dpll.p2;
6235 
6236         /* See eDP HDMI DPIO driver vbios notes doc */
6237 
6238         /* PLL B needs special handling */
6239         if (pipe == PIPE_B)
6240                 vlv_pllb_recal_opamp(dev_priv, pipe);
6241 
6242         /* Set up Tx target for periodic Rcomp update */
6243         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6244 
6245         /* Disable target IRef on PLL */
6246         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6247         reg_val &= 0x00ffffff;
6248         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6249 
6250         /* Disable fast lock */
6251         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6252 
6253         /* Set idtafcrecal before PLL is enabled */
6254         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6255         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6256         mdiv |= ((bestn << DPIO_N_SHIFT));
6257         mdiv |= (1 << DPIO_K_SHIFT);
6258 
6259         /*
6260          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6261          * but we don't support that).
6262          * Note: don't use the DAC post divider as it seems unstable.
6263          */
6264         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6265         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6266 
6267         mdiv |= DPIO_ENABLE_CALIBRATION;
6268         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6269 
6270         /* Set HBR and RBR LPF coefficients */
6271         if (pipe_config->port_clock == 162000 ||
6272             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6273             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6274                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6275                                  0x009f0003);
6276         else
6277                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6278                                  0x00d0000f);
6279 
6280         if (pipe_config->has_dp_encoder) {
6281                 /* Use SSC source */
6282                 if (pipe == PIPE_A)
6283                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6284                                          0x0df40000);
6285                 else
6286                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6287                                          0x0df70000);
6288         } else { /* HDMI or VGA */
6289                 /* Use bend source */
6290                 if (pipe == PIPE_A)
6291                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6292                                          0x0df70000);
6293                 else
6294                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6295                                          0x0df40000);
6296         }
6297 
6298         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6299         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6300         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6301             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6302                 coreclk |= 0x01000000;
6303         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6304 
6305         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6306         mutex_unlock(&dev_priv->dpio_lock);
6307 }
6308 
6309 static void chv_update_pll(struct intel_crtc *crtc,
6310                            struct intel_crtc_state *pipe_config)
6311 {
6312         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6313                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6314                 DPLL_VCO_ENABLE;
6315         if (crtc->pipe != PIPE_A)
6316                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6317 
6318         pipe_config->dpll_hw_state.dpll_md =
6319                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6320 }
6321 
6322 static void chv_prepare_pll(struct intel_crtc *crtc,
6323                             const struct intel_crtc_state *pipe_config)
6324 {
6325         struct drm_device *dev = crtc->base.dev;
6326         struct drm_i915_private *dev_priv = dev->dev_private;
6327         int pipe = crtc->pipe;
6328         int dpll_reg = DPLL(crtc->pipe);
6329         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6330         u32 loopfilter, tribuf_calcntr;
6331         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6332         u32 dpio_val;
6333         int vco;
6334 
6335         bestn = pipe_config->dpll.n;
6336         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6337         bestm1 = pipe_config->dpll.m1;
6338         bestm2 = pipe_config->dpll.m2 >> 22;
6339         bestp1 = pipe_config->dpll.p1;
6340         bestp2 = pipe_config->dpll.p2;
6341         vco = pipe_config->dpll.vco;
6342         dpio_val = 0;
6343         loopfilter = 0;
6344 
6345         /*
6346          * Enable Refclk and SSC
6347          */
6348         I915_WRITE(dpll_reg,
6349                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6350 
6351         mutex_lock(&dev_priv->dpio_lock);
6352 
6353         /* p1 and p2 divider */
6354         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6355                         5 << DPIO_CHV_S1_DIV_SHIFT |
6356                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6357                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6358                         1 << DPIO_CHV_K_DIV_SHIFT);
6359 
6360         /* Feedback post-divider - m2 */
6361         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6362 
6363         /* Feedback refclk divider - n and m1 */
6364         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6365                         DPIO_CHV_M1_DIV_BY_2 |
6366                         1 << DPIO_CHV_N_DIV_SHIFT);
6367 
6368         /* M2 fraction division */
6369         if (bestm2_frac)
6370                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6371 
6372         /* M2 fraction division enable */
6373         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6374         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6375         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6376         if (bestm2_frac)
6377                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6378         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6379 
6380         /* Program digital lock detect threshold */
6381         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6382         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6383                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6384         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6385         if (!bestm2_frac)
6386                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6387         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6388 
6389         /* Loop filter */
6390         if (vco == 5400000) {
6391                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6392                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6393                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6394                 tribuf_calcntr = 0x9;
6395         } else if (vco <= 6200000) {
6396                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6397                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6398                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6399                 tribuf_calcntr = 0x9;
6400         } else if (vco <= 6480000) {
6401                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6402                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6403                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6404                 tribuf_calcntr = 0x8;
6405         } else {
6406                 /* Not supported. Apply the same limits as in the max case */
6407                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6408                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6409                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6410                 tribuf_calcntr = 0;
6411         }
6412         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6413 
6414         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6415         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6416         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6417         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6418 
6419         /* AFC Recal */
6420         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6421                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6422                         DPIO_AFC_RECAL);
6423 
6424         mutex_unlock(&dev_priv->dpio_lock);
6425 }
6426 
6427 /**
6428  * vlv_force_pll_on - forcibly enable just the PLL
6429  * @dev_priv: i915 private structure
6430  * @pipe: pipe PLL to enable
6431  * @dpll: PLL configuration
6432  *
6433  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6434  * in cases where we need the PLL enabled even when @pipe is not going to
6435  * be enabled.
6436  */
6437 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6438                       const struct dpll *dpll)
6439 {
6440         struct intel_crtc *crtc =
6441                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6442         struct intel_crtc_state pipe_config = {
6443                 .base.crtc = &crtc->base,
6444                 .pixel_multiplier = 1,
6445                 .dpll = *dpll,
6446         };
6447 
6448         if (IS_CHERRYVIEW(dev)) {
6449                 chv_update_pll(crtc, &pipe_config);
6450                 chv_prepare_pll(crtc, &pipe_config);
6451                 chv_enable_pll(crtc, &pipe_config);
6452         } else {
6453                 vlv_update_pll(crtc, &pipe_config);
6454                 vlv_prepare_pll(crtc, &pipe_config);
6455                 vlv_enable_pll(crtc, &pipe_config);
6456         }
6457 }
6458 
6459 /**<