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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_dp_helper.h>
 41 #include <drm/drm_crtc_helper.h>
 42 #include <drm/drm_plane_helper.h>
 43 #include <drm/drm_rect.h>
 44 #include <linux/dma_remapping.h>
 45 
 46 /* Primary plane formats supported by all gen */
 47 #define COMMON_PRIMARY_FORMATS \
 48         DRM_FORMAT_C8, \
 49         DRM_FORMAT_RGB565, \
 50         DRM_FORMAT_XRGB8888, \
 51         DRM_FORMAT_ARGB8888
 52 
 53 /* Primary plane formats for gen <= 3 */
 54 static const uint32_t intel_primary_formats_gen2[] = {
 55         COMMON_PRIMARY_FORMATS,
 56         DRM_FORMAT_XRGB1555,
 57         DRM_FORMAT_ARGB1555,
 58 };
 59 
 60 /* Primary plane formats for gen >= 4 */
 61 static const uint32_t intel_primary_formats_gen4[] = {
 62         COMMON_PRIMARY_FORMATS, \
 63         DRM_FORMAT_XBGR8888,
 64         DRM_FORMAT_ABGR8888,
 65         DRM_FORMAT_XRGB2101010,
 66         DRM_FORMAT_ARGB2101010,
 67         DRM_FORMAT_XBGR2101010,
 68         DRM_FORMAT_ABGR2101010,
 69 };
 70 
 71 /* Cursor formats */
 72 static const uint32_t intel_cursor_formats[] = {
 73         DRM_FORMAT_ARGB8888,
 74 };
 75 
 76 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
 77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
 78 
 79 static void intel_increase_pllclock(struct drm_device *dev,
 80                                     enum pipe pipe);
 81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 82 
 83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 84                                 struct intel_crtc_config *pipe_config);
 85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 86                                    struct intel_crtc_config *pipe_config);
 87 
 88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 89                           int x, int y, struct drm_framebuffer *old_fb);
 90 static int intel_framebuffer_init(struct drm_device *dev,
 91                                   struct intel_framebuffer *ifb,
 92                                   struct drm_mode_fb_cmd2 *mode_cmd,
 93                                   struct drm_i915_gem_object *obj);
 94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
 95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 98                                          struct intel_link_m_n *m_n);
 99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 
104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105 {
106         if (!connector->mst_port)
107                 return connector->encoder;
108         else
109                 return &connector->mst_port->mst_encoders[pipe]->base;
110 }
111 
112 typedef struct {
113         int     min, max;
114 } intel_range_t;
115 
116 typedef struct {
117         int     dot_limit;
118         int     p2_slow, p2_fast;
119 } intel_p2_t;
120 
121 typedef struct intel_limit intel_limit_t;
122 struct intel_limit {
123         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
124         intel_p2_t          p2;
125 };
126 
127 int
128 intel_pch_rawclk(struct drm_device *dev)
129 {
130         struct drm_i915_private *dev_priv = dev->dev_private;
131 
132         WARN_ON(!HAS_PCH_SPLIT(dev));
133 
134         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 }
136 
137 static inline u32 /* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device *dev)
139 {
140         if (IS_GEN5(dev)) {
141                 struct drm_i915_private *dev_priv = dev->dev_private;
142                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143         } else
144                 return 27;
145 }
146 
147 static const intel_limit_t intel_limits_i8xx_dac = {
148         .dot = { .min = 25000, .max = 350000 },
149         .vco = { .min = 908000, .max = 1512000 },
150         .n = { .min = 2, .max = 16 },
151         .m = { .min = 96, .max = 140 },
152         .m1 = { .min = 18, .max = 26 },
153         .m2 = { .min = 6, .max = 16 },
154         .p = { .min = 4, .max = 128 },
155         .p1 = { .min = 2, .max = 33 },
156         .p2 = { .dot_limit = 165000,
157                 .p2_slow = 4, .p2_fast = 2 },
158 };
159 
160 static const intel_limit_t intel_limits_i8xx_dvo = {
161         .dot = { .min = 25000, .max = 350000 },
162         .vco = { .min = 908000, .max = 1512000 },
163         .n = { .min = 2, .max = 16 },
164         .m = { .min = 96, .max = 140 },
165         .m1 = { .min = 18, .max = 26 },
166         .m2 = { .min = 6, .max = 16 },
167         .p = { .min = 4, .max = 128 },
168         .p1 = { .min = 2, .max = 33 },
169         .p2 = { .dot_limit = 165000,
170                 .p2_slow = 4, .p2_fast = 4 },
171 };
172 
173 static const intel_limit_t intel_limits_i8xx_lvds = {
174         .dot = { .min = 25000, .max = 350000 },
175         .vco = { .min = 908000, .max = 1512000 },
176         .n = { .min = 2, .max = 16 },
177         .m = { .min = 96, .max = 140 },
178         .m1 = { .min = 18, .max = 26 },
179         .m2 = { .min = 6, .max = 16 },
180         .p = { .min = 4, .max = 128 },
181         .p1 = { .min = 1, .max = 6 },
182         .p2 = { .dot_limit = 165000,
183                 .p2_slow = 14, .p2_fast = 7 },
184 };
185 
186 static const intel_limit_t intel_limits_i9xx_sdvo = {
187         .dot = { .min = 20000, .max = 400000 },
188         .vco = { .min = 1400000, .max = 2800000 },
189         .n = { .min = 1, .max = 6 },
190         .m = { .min = 70, .max = 120 },
191         .m1 = { .min = 8, .max = 18 },
192         .m2 = { .min = 3, .max = 7 },
193         .p = { .min = 5, .max = 80 },
194         .p1 = { .min = 1, .max = 8 },
195         .p2 = { .dot_limit = 200000,
196                 .p2_slow = 10, .p2_fast = 5 },
197 };
198 
199 static const intel_limit_t intel_limits_i9xx_lvds = {
200         .dot = { .min = 20000, .max = 400000 },
201         .vco = { .min = 1400000, .max = 2800000 },
202         .n = { .min = 1, .max = 6 },
203         .m = { .min = 70, .max = 120 },
204         .m1 = { .min = 8, .max = 18 },
205         .m2 = { .min = 3, .max = 7 },
206         .p = { .min = 7, .max = 98 },
207         .p1 = { .min = 1, .max = 8 },
208         .p2 = { .dot_limit = 112000,
209                 .p2_slow = 14, .p2_fast = 7 },
210 };
211 
212 
213 static const intel_limit_t intel_limits_g4x_sdvo = {
214         .dot = { .min = 25000, .max = 270000 },
215         .vco = { .min = 1750000, .max = 3500000},
216         .n = { .min = 1, .max = 4 },
217         .m = { .min = 104, .max = 138 },
218         .m1 = { .min = 17, .max = 23 },
219         .m2 = { .min = 5, .max = 11 },
220         .p = { .min = 10, .max = 30 },
221         .p1 = { .min = 1, .max = 3},
222         .p2 = { .dot_limit = 270000,
223                 .p2_slow = 10,
224                 .p2_fast = 10
225         },
226 };
227 
228 static const intel_limit_t intel_limits_g4x_hdmi = {
229         .dot = { .min = 22000, .max = 400000 },
230         .vco = { .min = 1750000, .max = 3500000},
231         .n = { .min = 1, .max = 4 },
232         .m = { .min = 104, .max = 138 },
233         .m1 = { .min = 16, .max = 23 },
234         .m2 = { .min = 5, .max = 11 },
235         .p = { .min = 5, .max = 80 },
236         .p1 = { .min = 1, .max = 8},
237         .p2 = { .dot_limit = 165000,
238                 .p2_slow = 10, .p2_fast = 5 },
239 };
240 
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242         .dot = { .min = 20000, .max = 115000 },
243         .vco = { .min = 1750000, .max = 3500000 },
244         .n = { .min = 1, .max = 3 },
245         .m = { .min = 104, .max = 138 },
246         .m1 = { .min = 17, .max = 23 },
247         .m2 = { .min = 5, .max = 11 },
248         .p = { .min = 28, .max = 112 },
249         .p1 = { .min = 2, .max = 8 },
250         .p2 = { .dot_limit = 0,
251                 .p2_slow = 14, .p2_fast = 14
252         },
253 };
254 
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256         .dot = { .min = 80000, .max = 224000 },
257         .vco = { .min = 1750000, .max = 3500000 },
258         .n = { .min = 1, .max = 3 },
259         .m = { .min = 104, .max = 138 },
260         .m1 = { .min = 17, .max = 23 },
261         .m2 = { .min = 5, .max = 11 },
262         .p = { .min = 14, .max = 42 },
263         .p1 = { .min = 2, .max = 6 },
264         .p2 = { .dot_limit = 0,
265                 .p2_slow = 7, .p2_fast = 7
266         },
267 };
268 
269 static const intel_limit_t intel_limits_pineview_sdvo = {
270         .dot = { .min = 20000, .max = 400000},
271         .vco = { .min = 1700000, .max = 3500000 },
272         /* Pineview's Ncounter is a ring counter */
273         .n = { .min = 3, .max = 6 },
274         .m = { .min = 2, .max = 256 },
275         /* Pineview only has one combined m divider, which we treat as m2. */
276         .m1 = { .min = 0, .max = 0 },
277         .m2 = { .min = 0, .max = 254 },
278         .p = { .min = 5, .max = 80 },
279         .p1 = { .min = 1, .max = 8 },
280         .p2 = { .dot_limit = 200000,
281                 .p2_slow = 10, .p2_fast = 5 },
282 };
283 
284 static const intel_limit_t intel_limits_pineview_lvds = {
285         .dot = { .min = 20000, .max = 400000 },
286         .vco = { .min = 1700000, .max = 3500000 },
287         .n = { .min = 3, .max = 6 },
288         .m = { .min = 2, .max = 256 },
289         .m1 = { .min = 0, .max = 0 },
290         .m2 = { .min = 0, .max = 254 },
291         .p = { .min = 7, .max = 112 },
292         .p1 = { .min = 1, .max = 8 },
293         .p2 = { .dot_limit = 112000,
294                 .p2_slow = 14, .p2_fast = 14 },
295 };
296 
297 /* Ironlake / Sandybridge
298  *
299  * We calculate clock using (register_value + 2) for N/M1/M2, so here
300  * the range value for them is (actual_value - 2).
301  */
302 static const intel_limit_t intel_limits_ironlake_dac = {
303         .dot = { .min = 25000, .max = 350000 },
304         .vco = { .min = 1760000, .max = 3510000 },
305         .n = { .min = 1, .max = 5 },
306         .m = { .min = 79, .max = 127 },
307         .m1 = { .min = 12, .max = 22 },
308         .m2 = { .min = 5, .max = 9 },
309         .p = { .min = 5, .max = 80 },
310         .p1 = { .min = 1, .max = 8 },
311         .p2 = { .dot_limit = 225000,
312                 .p2_slow = 10, .p2_fast = 5 },
313 };
314 
315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
316         .dot = { .min = 25000, .max = 350000 },
317         .vco = { .min = 1760000, .max = 3510000 },
318         .n = { .min = 1, .max = 3 },
319         .m = { .min = 79, .max = 118 },
320         .m1 = { .min = 12, .max = 22 },
321         .m2 = { .min = 5, .max = 9 },
322         .p = { .min = 28, .max = 112 },
323         .p1 = { .min = 2, .max = 8 },
324         .p2 = { .dot_limit = 225000,
325                 .p2_slow = 14, .p2_fast = 14 },
326 };
327 
328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329         .dot = { .min = 25000, .max = 350000 },
330         .vco = { .min = 1760000, .max = 3510000 },
331         .n = { .min = 1, .max = 3 },
332         .m = { .min = 79, .max = 127 },
333         .m1 = { .min = 12, .max = 22 },
334         .m2 = { .min = 5, .max = 9 },
335         .p = { .min = 14, .max = 56 },
336         .p1 = { .min = 2, .max = 8 },
337         .p2 = { .dot_limit = 225000,
338                 .p2_slow = 7, .p2_fast = 7 },
339 };
340 
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343         .dot = { .min = 25000, .max = 350000 },
344         .vco = { .min = 1760000, .max = 3510000 },
345         .n = { .min = 1, .max = 2 },
346         .m = { .min = 79, .max = 126 },
347         .m1 = { .min = 12, .max = 22 },
348         .m2 = { .min = 5, .max = 9 },
349         .p = { .min = 28, .max = 112 },
350         .p1 = { .min = 2, .max = 8 },
351         .p2 = { .dot_limit = 225000,
352                 .p2_slow = 14, .p2_fast = 14 },
353 };
354 
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356         .dot = { .min = 25000, .max = 350000 },
357         .vco = { .min = 1760000, .max = 3510000 },
358         .n = { .min = 1, .max = 3 },
359         .m = { .min = 79, .max = 126 },
360         .m1 = { .min = 12, .max = 22 },
361         .m2 = { .min = 5, .max = 9 },
362         .p = { .min = 14, .max = 42 },
363         .p1 = { .min = 2, .max = 6 },
364         .p2 = { .dot_limit = 225000,
365                 .p2_slow = 7, .p2_fast = 7 },
366 };
367 
368 static const intel_limit_t intel_limits_vlv = {
369          /*
370           * These are the data rate limits (measured in fast clocks)
371           * since those are the strictest limits we have. The fast
372           * clock and actual rate limits are more relaxed, so checking
373           * them would make no difference.
374           */
375         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376         .vco = { .min = 4000000, .max = 6000000 },
377         .n = { .min = 1, .max = 7 },
378         .m1 = { .min = 2, .max = 3 },
379         .m2 = { .min = 11, .max = 156 },
380         .p1 = { .min = 2, .max = 3 },
381         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 };
383 
384 static const intel_limit_t intel_limits_chv = {
385         /*
386          * These are the data rate limits (measured in fast clocks)
387          * since those are the strictest limits we have.  The fast
388          * clock and actual rate limits are more relaxed, so checking
389          * them would make no difference.
390          */
391         .dot = { .min = 25000 * 5, .max = 540000 * 5},
392         .vco = { .min = 4860000, .max = 6700000 },
393         .n = { .min = 1, .max = 1 },
394         .m1 = { .min = 2, .max = 2 },
395         .m2 = { .min = 24 << 22, .max = 175 << 22 },
396         .p1 = { .min = 2, .max = 4 },
397         .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 };
399 
400 static void vlv_clock(int refclk, intel_clock_t *clock)
401 {
402         clock->m = clock->m1 * clock->m2;
403         clock->p = clock->p1 * clock->p2;
404         if (WARN_ON(clock->n == 0 || clock->p == 0))
405                 return;
406         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
408 }
409 
410 /**
411  * Returns whether any output on the specified pipe is of the specified type
412  */
413 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
414 {
415         struct drm_device *dev = crtc->dev;
416         struct intel_encoder *encoder;
417 
418         for_each_encoder_on_crtc(dev, crtc, encoder)
419                 if (encoder->type == type)
420                         return true;
421 
422         return false;
423 }
424 
425 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
426                                                 int refclk)
427 {
428         struct drm_device *dev = crtc->dev;
429         const intel_limit_t *limit;
430 
431         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
432                 if (intel_is_dual_link_lvds(dev)) {
433                         if (refclk == 100000)
434                                 limit = &intel_limits_ironlake_dual_lvds_100m;
435                         else
436                                 limit = &intel_limits_ironlake_dual_lvds;
437                 } else {
438                         if (refclk == 100000)
439                                 limit = &intel_limits_ironlake_single_lvds_100m;
440                         else
441                                 limit = &intel_limits_ironlake_single_lvds;
442                 }
443         } else
444                 limit = &intel_limits_ironlake_dac;
445 
446         return limit;
447 }
448 
449 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
450 {
451         struct drm_device *dev = crtc->dev;
452         const intel_limit_t *limit;
453 
454         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
455                 if (intel_is_dual_link_lvds(dev))
456                         limit = &intel_limits_g4x_dual_channel_lvds;
457                 else
458                         limit = &intel_limits_g4x_single_channel_lvds;
459         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
460                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
461                 limit = &intel_limits_g4x_hdmi;
462         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
463                 limit = &intel_limits_g4x_sdvo;
464         } else /* The option is for other outputs */
465                 limit = &intel_limits_i9xx_sdvo;
466 
467         return limit;
468 }
469 
470 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
471 {
472         struct drm_device *dev = crtc->dev;
473         const intel_limit_t *limit;
474 
475         if (HAS_PCH_SPLIT(dev))
476                 limit = intel_ironlake_limit(crtc, refclk);
477         else if (IS_G4X(dev)) {
478                 limit = intel_g4x_limit(crtc);
479         } else if (IS_PINEVIEW(dev)) {
480                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
481                         limit = &intel_limits_pineview_lvds;
482                 else
483                         limit = &intel_limits_pineview_sdvo;
484         } else if (IS_CHERRYVIEW(dev)) {
485                 limit = &intel_limits_chv;
486         } else if (IS_VALLEYVIEW(dev)) {
487                 limit = &intel_limits_vlv;
488         } else if (!IS_GEN2(dev)) {
489                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
490                         limit = &intel_limits_i9xx_lvds;
491                 else
492                         limit = &intel_limits_i9xx_sdvo;
493         } else {
494                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
495                         limit = &intel_limits_i8xx_lvds;
496                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
497                         limit = &intel_limits_i8xx_dvo;
498                 else
499                         limit = &intel_limits_i8xx_dac;
500         }
501         return limit;
502 }
503 
504 /* m1 is reserved as 0 in Pineview, n is a ring counter */
505 static void pineview_clock(int refclk, intel_clock_t *clock)
506 {
507         clock->m = clock->m2 + 2;
508         clock->p = clock->p1 * clock->p2;
509         if (WARN_ON(clock->n == 0 || clock->p == 0))
510                 return;
511         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
512         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
513 }
514 
515 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
516 {
517         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
518 }
519 
520 static void i9xx_clock(int refclk, intel_clock_t *clock)
521 {
522         clock->m = i9xx_dpll_compute_m(clock);
523         clock->p = clock->p1 * clock->p2;
524         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
525                 return;
526         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
527         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
528 }
529 
530 static void chv_clock(int refclk, intel_clock_t *clock)
531 {
532         clock->m = clock->m1 * clock->m2;
533         clock->p = clock->p1 * clock->p2;
534         if (WARN_ON(clock->n == 0 || clock->p == 0))
535                 return;
536         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
537                         clock->n << 22);
538         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
539 }
540 
541 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
542 /**
543  * Returns whether the given set of divisors are valid for a given refclk with
544  * the given connectors.
545  */
546 
547 static bool intel_PLL_is_valid(struct drm_device *dev,
548                                const intel_limit_t *limit,
549                                const intel_clock_t *clock)
550 {
551         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
552                 INTELPllInvalid("n out of range\n");
553         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
554                 INTELPllInvalid("p1 out of range\n");
555         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
556                 INTELPllInvalid("m2 out of range\n");
557         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
558                 INTELPllInvalid("m1 out of range\n");
559 
560         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
561                 if (clock->m1 <= clock->m2)
562                         INTELPllInvalid("m1 <= m2\n");
563 
564         if (!IS_VALLEYVIEW(dev)) {
565                 if (clock->p < limit->p.min || limit->p.max < clock->p)
566                         INTELPllInvalid("p out of range\n");
567                 if (clock->m < limit->m.min || limit->m.max < clock->m)
568                         INTELPllInvalid("m out of range\n");
569         }
570 
571         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
572                 INTELPllInvalid("vco out of range\n");
573         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
574          * connector, etc., rather than just a single range.
575          */
576         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
577                 INTELPllInvalid("dot out of range\n");
578 
579         return true;
580 }
581 
582 static bool
583 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
584                     int target, int refclk, intel_clock_t *match_clock,
585                     intel_clock_t *best_clock)
586 {
587         struct drm_device *dev = crtc->dev;
588         intel_clock_t clock;
589         int err = target;
590 
591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592                 /*
593                  * For LVDS just rely on its current settings for dual-channel.
594                  * We haven't figured out how to reliably set up different
595                  * single/dual channel state, if we even can.
596                  */
597                 if (intel_is_dual_link_lvds(dev))
598                         clock.p2 = limit->p2.p2_fast;
599                 else
600                         clock.p2 = limit->p2.p2_slow;
601         } else {
602                 if (target < limit->p2.dot_limit)
603                         clock.p2 = limit->p2.p2_slow;
604                 else
605                         clock.p2 = limit->p2.p2_fast;
606         }
607 
608         memset(best_clock, 0, sizeof(*best_clock));
609 
610         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
611              clock.m1++) {
612                 for (clock.m2 = limit->m2.min;
613                      clock.m2 <= limit->m2.max; clock.m2++) {
614                         if (clock.m2 >= clock.m1)
615                                 break;
616                         for (clock.n = limit->n.min;
617                              clock.n <= limit->n.max; clock.n++) {
618                                 for (clock.p1 = limit->p1.min;
619                                         clock.p1 <= limit->p1.max; clock.p1++) {
620                                         int this_err;
621 
622                                         i9xx_clock(refclk, &clock);
623                                         if (!intel_PLL_is_valid(dev, limit,
624                                                                 &clock))
625                                                 continue;
626                                         if (match_clock &&
627                                             clock.p != match_clock->p)
628                                                 continue;
629 
630                                         this_err = abs(clock.dot - target);
631                                         if (this_err < err) {
632                                                 *best_clock = clock;
633                                                 err = this_err;
634                                         }
635                                 }
636                         }
637                 }
638         }
639 
640         return (err != target);
641 }
642 
643 static bool
644 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
645                    int target, int refclk, intel_clock_t *match_clock,
646                    intel_clock_t *best_clock)
647 {
648         struct drm_device *dev = crtc->dev;
649         intel_clock_t clock;
650         int err = target;
651 
652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653                 /*
654                  * For LVDS just rely on its current settings for dual-channel.
655                  * We haven't figured out how to reliably set up different
656                  * single/dual channel state, if we even can.
657                  */
658                 if (intel_is_dual_link_lvds(dev))
659                         clock.p2 = limit->p2.p2_fast;
660                 else
661                         clock.p2 = limit->p2.p2_slow;
662         } else {
663                 if (target < limit->p2.dot_limit)
664                         clock.p2 = limit->p2.p2_slow;
665                 else
666                         clock.p2 = limit->p2.p2_fast;
667         }
668 
669         memset(best_clock, 0, sizeof(*best_clock));
670 
671         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672              clock.m1++) {
673                 for (clock.m2 = limit->m2.min;
674                      clock.m2 <= limit->m2.max; clock.m2++) {
675                         for (clock.n = limit->n.min;
676                              clock.n <= limit->n.max; clock.n++) {
677                                 for (clock.p1 = limit->p1.min;
678                                         clock.p1 <= limit->p1.max; clock.p1++) {
679                                         int this_err;
680 
681                                         pineview_clock(refclk, &clock);
682                                         if (!intel_PLL_is_valid(dev, limit,
683                                                                 &clock))
684                                                 continue;
685                                         if (match_clock &&
686                                             clock.p != match_clock->p)
687                                                 continue;
688 
689                                         this_err = abs(clock.dot - target);
690                                         if (this_err < err) {
691                                                 *best_clock = clock;
692                                                 err = this_err;
693                                         }
694                                 }
695                         }
696                 }
697         }
698 
699         return (err != target);
700 }
701 
702 static bool
703 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
704                    int target, int refclk, intel_clock_t *match_clock,
705                    intel_clock_t *best_clock)
706 {
707         struct drm_device *dev = crtc->dev;
708         intel_clock_t clock;
709         int max_n;
710         bool found;
711         /* approximately equals target * 0.00585 */
712         int err_most = (target >> 8) + (target >> 9);
713         found = false;
714 
715         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
716                 if (intel_is_dual_link_lvds(dev))
717                         clock.p2 = limit->p2.p2_fast;
718                 else
719                         clock.p2 = limit->p2.p2_slow;
720         } else {
721                 if (target < limit->p2.dot_limit)
722                         clock.p2 = limit->p2.p2_slow;
723                 else
724                         clock.p2 = limit->p2.p2_fast;
725         }
726 
727         memset(best_clock, 0, sizeof(*best_clock));
728         max_n = limit->n.max;
729         /* based on hardware requirement, prefer smaller n to precision */
730         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
731                 /* based on hardware requirement, prefere larger m1,m2 */
732                 for (clock.m1 = limit->m1.max;
733                      clock.m1 >= limit->m1.min; clock.m1--) {
734                         for (clock.m2 = limit->m2.max;
735                              clock.m2 >= limit->m2.min; clock.m2--) {
736                                 for (clock.p1 = limit->p1.max;
737                                      clock.p1 >= limit->p1.min; clock.p1--) {
738                                         int this_err;
739 
740                                         i9xx_clock(refclk, &clock);
741                                         if (!intel_PLL_is_valid(dev, limit,
742                                                                 &clock))
743                                                 continue;
744 
745                                         this_err = abs(clock.dot - target);
746                                         if (this_err < err_most) {
747                                                 *best_clock = clock;
748                                                 err_most = this_err;
749                                                 max_n = clock.n;
750                                                 found = true;
751                                         }
752                                 }
753                         }
754                 }
755         }
756         return found;
757 }
758 
759 static bool
760 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
761                    int target, int refclk, intel_clock_t *match_clock,
762                    intel_clock_t *best_clock)
763 {
764         struct drm_device *dev = crtc->dev;
765         intel_clock_t clock;
766         unsigned int bestppm = 1000000;
767         /* min update 19.2 MHz */
768         int max_n = min(limit->n.max, refclk / 19200);
769         bool found = false;
770 
771         target *= 5; /* fast clock */
772 
773         memset(best_clock, 0, sizeof(*best_clock));
774 
775         /* based on hardware requirement, prefer smaller n to precision */
776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
778                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
779                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
780                                 clock.p = clock.p1 * clock.p2;
781                                 /* based on hardware requirement, prefer bigger m1,m2 values */
782                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
783                                         unsigned int ppm, diff;
784 
785                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
786                                                                      refclk * clock.m1);
787 
788                                         vlv_clock(refclk, &clock);
789 
790                                         if (!intel_PLL_is_valid(dev, limit,
791                                                                 &clock))
792                                                 continue;
793 
794                                         diff = abs(clock.dot - target);
795                                         ppm = div_u64(1000000ULL * diff, target);
796 
797                                         if (ppm < 100 && clock.p > best_clock->p) {
798                                                 bestppm = 0;
799                                                 *best_clock = clock;
800                                                 found = true;
801                                         }
802 
803                                         if (bestppm >= 10 && ppm < bestppm - 10) {
804                                                 bestppm = ppm;
805                                                 *best_clock = clock;
806                                                 found = true;
807                                         }
808                                 }
809                         }
810                 }
811         }
812 
813         return found;
814 }
815 
816 static bool
817 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
818                    int target, int refclk, intel_clock_t *match_clock,
819                    intel_clock_t *best_clock)
820 {
821         struct drm_device *dev = crtc->dev;
822         intel_clock_t clock;
823         uint64_t m2;
824         int found = false;
825 
826         memset(best_clock, 0, sizeof(*best_clock));
827 
828         /*
829          * Based on hardware doc, the n always set to 1, and m1 always
830          * set to 2.  If requires to support 200Mhz refclk, we need to
831          * revisit this because n may not 1 anymore.
832          */
833         clock.n = 1, clock.m1 = 2;
834         target *= 5;    /* fast clock */
835 
836         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
837                 for (clock.p2 = limit->p2.p2_fast;
838                                 clock.p2 >= limit->p2.p2_slow;
839                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840 
841                         clock.p = clock.p1 * clock.p2;
842 
843                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
844                                         clock.n) << 22, refclk * clock.m1);
845 
846                         if (m2 > INT_MAX/clock.m1)
847                                 continue;
848 
849                         clock.m2 = m2;
850 
851                         chv_clock(refclk, &clock);
852 
853                         if (!intel_PLL_is_valid(dev, limit, &clock))
854                                 continue;
855 
856                         /* based on hardware requirement, prefer bigger p
857                          */
858                         if (clock.p > best_clock->p) {
859                                 *best_clock = clock;
860                                 found = true;
861                         }
862                 }
863         }
864 
865         return found;
866 }
867 
868 bool intel_crtc_active(struct drm_crtc *crtc)
869 {
870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
871 
872         /* Be paranoid as we can arrive here with only partial
873          * state retrieved from the hardware during setup.
874          *
875          * We can ditch the adjusted_mode.crtc_clock check as soon
876          * as Haswell has gained clock readout/fastboot support.
877          *
878          * We can ditch the crtc->primary->fb check as soon as we can
879          * properly reconstruct framebuffers.
880          */
881         return intel_crtc->active && crtc->primary->fb &&
882                 intel_crtc->config.adjusted_mode.crtc_clock;
883 }
884 
885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
886                                              enum pipe pipe)
887 {
888         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890 
891         return intel_crtc->config.cpu_transcoder;
892 }
893 
894 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
895 {
896         struct drm_i915_private *dev_priv = dev->dev_private;
897         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
898 
899         frame = I915_READ(frame_reg);
900 
901         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902                 WARN(1, "vblank wait timed out\n");
903 }
904 
905 /**
906  * intel_wait_for_vblank - wait for vblank on a given pipe
907  * @dev: drm device
908  * @pipe: pipe to wait for
909  *
910  * Wait for vblank to occur on a given pipe.  Needed for various bits of
911  * mode setting code.
912  */
913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
914 {
915         struct drm_i915_private *dev_priv = dev->dev_private;
916         int pipestat_reg = PIPESTAT(pipe);
917 
918         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
919                 g4x_wait_for_vblank(dev, pipe);
920                 return;
921         }
922 
923         /* Clear existing vblank status. Note this will clear any other
924          * sticky status fields as well.
925          *
926          * This races with i915_driver_irq_handler() with the result
927          * that either function could miss a vblank event.  Here it is not
928          * fatal, as we will either wait upon the next vblank interrupt or
929          * timeout.  Generally speaking intel_wait_for_vblank() is only
930          * called during modeset at which time the GPU should be idle and
931          * should *not* be performing page flips and thus not waiting on
932          * vblanks...
933          * Currently, the result of us stealing a vblank from the irq
934          * handler is that a single frame will be skipped during swapbuffers.
935          */
936         I915_WRITE(pipestat_reg,
937                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
938 
939         /* Wait for vblank interrupt bit to set */
940         if (wait_for(I915_READ(pipestat_reg) &
941                      PIPE_VBLANK_INTERRUPT_STATUS,
942                      50))
943                 DRM_DEBUG_KMS("vblank wait timed out\n");
944 }
945 
946 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
947 {
948         struct drm_i915_private *dev_priv = dev->dev_private;
949         u32 reg = PIPEDSL(pipe);
950         u32 line1, line2;
951         u32 line_mask;
952 
953         if (IS_GEN2(dev))
954                 line_mask = DSL_LINEMASK_GEN2;
955         else
956                 line_mask = DSL_LINEMASK_GEN3;
957 
958         line1 = I915_READ(reg) & line_mask;
959         mdelay(5);
960         line2 = I915_READ(reg) & line_mask;
961 
962         return line1 == line2;
963 }
964 
965 /*
966  * intel_wait_for_pipe_off - wait for pipe to turn off
967  * @dev: drm device
968  * @pipe: pipe to wait for
969  *
970  * After disabling a pipe, we can't wait for vblank in the usual way,
971  * spinning on the vblank interrupt status bit, since we won't actually
972  * see an interrupt when the pipe is disabled.
973  *
974  * On Gen4 and above:
975  *   wait for the pipe register state bit to turn off
976  *
977  * Otherwise:
978  *   wait for the display line value to settle (it usually
979  *   ends up stopping at the start of the next frame).
980  *
981  */
982 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
983 {
984         struct drm_i915_private *dev_priv = dev->dev_private;
985         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
986                                                                       pipe);
987 
988         if (INTEL_INFO(dev)->gen >= 4) {
989                 int reg = PIPECONF(cpu_transcoder);
990 
991                 /* Wait for the Pipe State to go off */
992                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
993                              100))
994                         WARN(1, "pipe_off wait timed out\n");
995         } else {
996                 /* Wait for the display line to settle */
997                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
998                         WARN(1, "pipe_off wait timed out\n");
999         }
1000 }
1001 
1002 /*
1003  * ibx_digital_port_connected - is the specified port connected?
1004  * @dev_priv: i915 private structure
1005  * @port: the port to test
1006  *
1007  * Returns true if @port is connected, false otherwise.
1008  */
1009 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010                                 struct intel_digital_port *port)
1011 {
1012         u32 bit;
1013 
1014         if (HAS_PCH_IBX(dev_priv->dev)) {
1015                 switch (port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         } else {
1029                 switch (port->port) {
1030                 case PORT_B:
1031                         bit = SDE_PORTB_HOTPLUG_CPT;
1032                         break;
1033                 case PORT_C:
1034                         bit = SDE_PORTC_HOTPLUG_CPT;
1035                         break;
1036                 case PORT_D:
1037                         bit = SDE_PORTD_HOTPLUG_CPT;
1038                         break;
1039                 default:
1040                         return true;
1041                 }
1042         }
1043 
1044         return I915_READ(SDEISR) & bit;
1045 }
1046 
1047 static const char *state_string(bool enabled)
1048 {
1049         return enabled ? "on" : "off";
1050 }
1051 
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054                 enum pipe pipe, bool state)
1055 {
1056         int reg;
1057         u32 val;
1058         bool cur_state;
1059 
1060         reg = DPLL(pipe);
1061         val = I915_READ(reg);
1062         cur_state = !!(val & DPLL_VCO_ENABLE);
1063         WARN(cur_state != state,
1064              "PLL state assertion failure (expected %s, current %s)\n",
1065              state_string(state), state_string(cur_state));
1066 }
1067 
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1070 {
1071         u32 val;
1072         bool cur_state;
1073 
1074         mutex_lock(&dev_priv->dpio_lock);
1075         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076         mutex_unlock(&dev_priv->dpio_lock);
1077 
1078         cur_state = val & DSI_PLL_VCO_EN;
1079         WARN(cur_state != state,
1080              "DSI PLL state assertion failure (expected %s, current %s)\n",
1081              state_string(state), state_string(cur_state));
1082 }
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1085 
1086 struct intel_shared_dpll *
1087 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1088 {
1089         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1090 
1091         if (crtc->config.shared_dpll < 0)
1092                 return NULL;
1093 
1094         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1095 }
1096 
1097 /* For ILK+ */
1098 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099                         struct intel_shared_dpll *pll,
1100                         bool state)
1101 {
1102         bool cur_state;
1103         struct intel_dpll_hw_state hw_state;
1104 
1105         if (WARN (!pll,
1106                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1107                 return;
1108 
1109         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110         WARN(cur_state != state,
1111              "%s assertion failure (expected %s, current %s)\n",
1112              pll->name, state_string(state), state_string(cur_state));
1113 }
1114 
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116                           enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123 
1124         if (HAS_DDI(dev_priv->dev)) {
1125                 /* DDI does not have a specific FDI_TX register */
1126                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129         } else {
1130                 reg = FDI_TX_CTL(pipe);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & FDI_TX_ENABLE);
1133         }
1134         WARN(cur_state != state,
1135              "FDI TX state assertion failure (expected %s, current %s)\n",
1136              state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140 
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142                           enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147 
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX state assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157 
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159                                       enum pipe pipe)
1160 {
1161         int reg;
1162         u32 val;
1163 
1164         /* ILK FDI PLL is always enabled */
1165         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1166                 return;
1167 
1168         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169         if (HAS_DDI(dev_priv->dev))
1170                 return;
1171 
1172         reg = FDI_TX_CTL(pipe);
1173         val = I915_READ(reg);
1174         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176 
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183 
1184         reg = FDI_RX_CTL(pipe);
1185         val = I915_READ(reg);
1186         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187         WARN(cur_state != state,
1188              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189              state_string(state), state_string(cur_state));
1190 }
1191 
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         int pp_reg, lvds_reg;
1196         u32 val;
1197         enum pipe panel_pipe = PIPE_A;
1198         bool locked = true;
1199 
1200         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201                 pp_reg = PCH_PP_CONTROL;
1202                 lvds_reg = PCH_LVDS;
1203         } else {
1204                 pp_reg = PP_CONTROL;
1205                 lvds_reg = LVDS;
1206         }
1207 
1208         val = I915_READ(pp_reg);
1209         if (!(val & PANEL_POWER_ON) ||
1210             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211                 locked = false;
1212 
1213         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214                 panel_pipe = PIPE_B;
1215 
1216         WARN(panel_pipe == pipe && locked,
1217              "panel assertion failure, pipe %c regs locked\n",
1218              pipe_name(pipe));
1219 }
1220 
1221 static void assert_cursor(struct drm_i915_private *dev_priv,
1222                           enum pipe pipe, bool state)
1223 {
1224         struct drm_device *dev = dev_priv->dev;
1225         bool cur_state;
1226 
1227         if (IS_845G(dev) || IS_I865G(dev))
1228                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1229         else
1230                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1231 
1232         WARN(cur_state != state,
1233              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1234              pipe_name(pipe), state_string(state), state_string(cur_state));
1235 }
1236 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1237 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1238 
1239 void assert_pipe(struct drm_i915_private *dev_priv,
1240                  enum pipe pipe, bool state)
1241 {
1242         int reg;
1243         u32 val;
1244         bool cur_state;
1245         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1246                                                                       pipe);
1247 
1248         /* if we need the pipe A quirk it must be always on */
1249         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1250                 state = true;
1251 
1252         if (!intel_display_power_enabled(dev_priv,
1253                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1254                 cur_state = false;
1255         } else {
1256                 reg = PIPECONF(cpu_transcoder);
1257                 val = I915_READ(reg);
1258                 cur_state = !!(val & PIPECONF_ENABLE);
1259         }
1260 
1261         WARN(cur_state != state,
1262              "pipe %c assertion failure (expected %s, current %s)\n",
1263              pipe_name(pipe), state_string(state), state_string(cur_state));
1264 }
1265 
1266 static void assert_plane(struct drm_i915_private *dev_priv,
1267                          enum plane plane, bool state)
1268 {
1269         int reg;
1270         u32 val;
1271         bool cur_state;
1272 
1273         reg = DSPCNTR(plane);
1274         val = I915_READ(reg);
1275         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1276         WARN(cur_state != state,
1277              "plane %c assertion failure (expected %s, current %s)\n",
1278              plane_name(plane), state_string(state), state_string(cur_state));
1279 }
1280 
1281 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1282 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1283 
1284 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1285                                    enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int reg, i;
1289         u32 val;
1290         int cur_pipe;
1291 
1292         /* Primary planes are fixed to pipes on gen4+ */
1293         if (INTEL_INFO(dev)->gen >= 4) {
1294                 reg = DSPCNTR(pipe);
1295                 val = I915_READ(reg);
1296                 WARN(val & DISPLAY_PLANE_ENABLE,
1297                      "plane %c assertion failure, should be disabled but not\n",
1298                      plane_name(pipe));
1299                 return;
1300         }
1301 
1302         /* Need to check both planes against the pipe */
1303         for_each_pipe(i) {
1304                 reg = DSPCNTR(i);
1305                 val = I915_READ(reg);
1306                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1307                         DISPPLANE_SEL_PIPE_SHIFT;
1308                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1309                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1310                      plane_name(i), pipe_name(pipe));
1311         }
1312 }
1313 
1314 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1315                                     enum pipe pipe)
1316 {
1317         struct drm_device *dev = dev_priv->dev;
1318         int reg, sprite;
1319         u32 val;
1320 
1321         if (IS_VALLEYVIEW(dev)) {
1322                 for_each_sprite(pipe, sprite) {
1323                         reg = SPCNTR(pipe, sprite);
1324                         val = I915_READ(reg);
1325                         WARN(val & SP_ENABLE,
1326                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327                              sprite_name(pipe, sprite), pipe_name(pipe));
1328                 }
1329         } else if (INTEL_INFO(dev)->gen >= 7) {
1330                 reg = SPRCTL(pipe);
1331                 val = I915_READ(reg);
1332                 WARN(val & SPRITE_ENABLE,
1333                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334                      plane_name(pipe), pipe_name(pipe));
1335         } else if (INTEL_INFO(dev)->gen >= 5) {
1336                 reg = DVSCNTR(pipe);
1337                 val = I915_READ(reg);
1338                 WARN(val & DVS_ENABLE,
1339                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340                      plane_name(pipe), pipe_name(pipe));
1341         }
1342 }
1343 
1344 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1345 {
1346         u32 val;
1347         bool enabled;
1348 
1349         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1350 
1351         val = I915_READ(PCH_DREF_CONTROL);
1352         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1353                             DREF_SUPERSPREAD_SOURCE_MASK));
1354         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1355 }
1356 
1357 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1358                                            enum pipe pipe)
1359 {
1360         int reg;
1361         u32 val;
1362         bool enabled;
1363 
1364         reg = PCH_TRANSCONF(pipe);
1365         val = I915_READ(reg);
1366         enabled = !!(val & TRANS_ENABLE);
1367         WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371 
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377 
1378         if (HAS_PCH_CPT(dev_priv->dev)) {
1379                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1380                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1381                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1382                         return false;
1383         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1384                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1385                         return false;
1386         } else {
1387                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1388                         return false;
1389         }
1390         return true;
1391 }
1392 
1393 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1394                               enum pipe pipe, u32 val)
1395 {
1396         if ((val & SDVO_ENABLE) == 0)
1397                 return false;
1398 
1399         if (HAS_PCH_CPT(dev_priv->dev)) {
1400                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1401                         return false;
1402         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1403                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1404                         return false;
1405         } else {
1406                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1407                         return false;
1408         }
1409         return true;
1410 }
1411 
1412 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1413                               enum pipe pipe, u32 val)
1414 {
1415         if ((val & LVDS_PORT_EN) == 0)
1416                 return false;
1417 
1418         if (HAS_PCH_CPT(dev_priv->dev)) {
1419                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1420                         return false;
1421         } else {
1422                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1423                         return false;
1424         }
1425         return true;
1426 }
1427 
1428 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1429                               enum pipe pipe, u32 val)
1430 {
1431         if ((val & ADPA_DAC_ENABLE) == 0)
1432                 return false;
1433         if (HAS_PCH_CPT(dev_priv->dev)) {
1434                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1435                         return false;
1436         } else {
1437                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1438                         return false;
1439         }
1440         return true;
1441 }
1442 
1443 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1444                                    enum pipe pipe, int reg, u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              reg, pipe_name(pipe));
1450 
1451         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455 
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, int reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              reg, pipe_name(pipe));
1463 
1464         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468 
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         int reg;
1473         u32 val;
1474 
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1477         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1478 
1479         reg = PCH_ADPA;
1480         val = I915_READ(reg);
1481         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1482              "PCH VGA enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484 
1485         reg = PCH_LVDS;
1486         val = I915_READ(reg);
1487         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1488              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1489              pipe_name(pipe));
1490 
1491         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1492         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1493         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1494 }
1495 
1496 static void intel_init_dpio(struct drm_device *dev)
1497 {
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499 
1500         if (!IS_VALLEYVIEW(dev))
1501                 return;
1502 
1503         /*
1504          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1505          * CHV x1 PHY (DP/HDMI D)
1506          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1507          */
1508         if (IS_CHERRYVIEW(dev)) {
1509                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1510                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1511         } else {
1512                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1513         }
1514 }
1515 
1516 static void intel_reset_dpio(struct drm_device *dev)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519 
1520         if (IS_CHERRYVIEW(dev)) {
1521                 enum dpio_phy phy;
1522                 u32 val;
1523 
1524                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525                         /* Poll for phypwrgood signal */
1526                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527                                                 PHY_POWERGOOD(phy), 1))
1528                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529 
1530                         /*
1531                          * Deassert common lane reset for PHY.
1532                          *
1533                          * This should only be done on init and resume from S3
1534                          * with both PLLs disabled, or we risk losing DPIO and
1535                          * PLL synchronization.
1536                          */
1537                         val = I915_READ(DISPLAY_PHY_CONTROL);
1538                         I915_WRITE(DISPLAY_PHY_CONTROL,
1539                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540                 }
1541         }
1542 }
1543 
1544 static void vlv_enable_pll(struct intel_crtc *crtc)
1545 {
1546         struct drm_device *dev = crtc->base.dev;
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548         int reg = DPLL(crtc->pipe);
1549         u32 dpll = crtc->config.dpll_hw_state.dpll;
1550 
1551         assert_pipe_disabled(dev_priv, crtc->pipe);
1552 
1553         /* No really, not for ILK+ */
1554         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1555 
1556         /* PLL is protected by panel, make sure we can write it */
1557         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1558                 assert_panel_unlocked(dev_priv, crtc->pipe);
1559 
1560         I915_WRITE(reg, dpll);
1561         POSTING_READ(reg);
1562         udelay(150);
1563 
1564         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1565                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1566 
1567         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1568         POSTING_READ(DPLL_MD(crtc->pipe));
1569 
1570         /* We do this three times for luck */
1571         I915_WRITE(reg, dpll);
1572         POSTING_READ(reg);
1573         udelay(150); /* wait for warmup */
1574         I915_WRITE(reg, dpll);
1575         POSTING_READ(reg);
1576         udelay(150); /* wait for warmup */
1577         I915_WRITE(reg, dpll);
1578         POSTING_READ(reg);
1579         udelay(150); /* wait for warmup */
1580 }
1581 
1582 static void chv_enable_pll(struct intel_crtc *crtc)
1583 {
1584         struct drm_device *dev = crtc->base.dev;
1585         struct drm_i915_private *dev_priv = dev->dev_private;
1586         int pipe = crtc->pipe;
1587         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1588         u32 tmp;
1589 
1590         assert_pipe_disabled(dev_priv, crtc->pipe);
1591 
1592         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1593 
1594         mutex_lock(&dev_priv->dpio_lock);
1595 
1596         /* Enable back the 10bit clock to display controller */
1597         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1598         tmp |= DPIO_DCLKP_EN;
1599         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1600 
1601         /*
1602          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1603          */
1604         udelay(1);
1605 
1606         /* Enable PLL */
1607         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1608 
1609         /* Check PLL is locked */
1610         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1611                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1612 
1613         /* not sure when this should be written */
1614         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1615         POSTING_READ(DPLL_MD(pipe));
1616 
1617         mutex_unlock(&dev_priv->dpio_lock);
1618 }
1619 
1620 static void i9xx_enable_pll(struct intel_crtc *crtc)
1621 {
1622         struct drm_device *dev = crtc->base.dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         int reg = DPLL(crtc->pipe);
1625         u32 dpll = crtc->config.dpll_hw_state.dpll;
1626 
1627         assert_pipe_disabled(dev_priv, crtc->pipe);
1628 
1629         /* No really, not for ILK+ */
1630         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1631 
1632         /* PLL is protected by panel, make sure we can write it */
1633         if (IS_MOBILE(dev) && !IS_I830(dev))
1634                 assert_panel_unlocked(dev_priv, crtc->pipe);
1635 
1636         I915_WRITE(reg, dpll);
1637 
1638         /* Wait for the clocks to stabilize. */
1639         POSTING_READ(reg);
1640         udelay(150);
1641 
1642         if (INTEL_INFO(dev)->gen >= 4) {
1643                 I915_WRITE(DPLL_MD(crtc->pipe),
1644                            crtc->config.dpll_hw_state.dpll_md);
1645         } else {
1646                 /* The pixel multiplier can only be updated once the
1647                  * DPLL is enabled and the clocks are stable.
1648                  *
1649                  * So write it again.
1650                  */
1651                 I915_WRITE(reg, dpll);
1652         }
1653 
1654         /* We do this three times for luck */
1655         I915_WRITE(reg, dpll);
1656         POSTING_READ(reg);
1657         udelay(150); /* wait for warmup */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664 }
1665 
1666 /**
1667  * i9xx_disable_pll - disable a PLL
1668  * @dev_priv: i915 private structure
1669  * @pipe: pipe PLL to disable
1670  *
1671  * Disable the PLL for @pipe, making sure the pipe is off first.
1672  *
1673  * Note!  This is for pre-ILK only.
1674  */
1675 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         /* Don't disable pipe A or pipe A PLLs if needed */
1678         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1679                 return;
1680 
1681         /* Make sure the pipe isn't still relying on us */
1682         assert_pipe_disabled(dev_priv, pipe);
1683 
1684         I915_WRITE(DPLL(pipe), 0);
1685         POSTING_READ(DPLL(pipe));
1686 }
1687 
1688 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1689 {
1690         u32 val = 0;
1691 
1692         /* Make sure the pipe isn't still relying on us */
1693         assert_pipe_disabled(dev_priv, pipe);
1694 
1695         /*
1696          * Leave integrated clock source and reference clock enabled for pipe B.
1697          * The latter is needed for VGA hotplug / manual detection.
1698          */
1699         if (pipe == PIPE_B)
1700                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1701         I915_WRITE(DPLL(pipe), val);
1702         POSTING_READ(DPLL(pipe));
1703 
1704 }
1705 
1706 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1707 {
1708         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1709         u32 val;
1710 
1711         /* Make sure the pipe isn't still relying on us */
1712         assert_pipe_disabled(dev_priv, pipe);
1713 
1714         /* Set PLL en = 0 */
1715         val = DPLL_SSC_REF_CLOCK_CHV;
1716         if (pipe != PIPE_A)
1717                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1718         I915_WRITE(DPLL(pipe), val);
1719         POSTING_READ(DPLL(pipe));
1720 
1721         mutex_lock(&dev_priv->dpio_lock);
1722 
1723         /* Disable 10bit clock to display controller */
1724         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1725         val &= ~DPIO_DCLKP_EN;
1726         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1727 
1728         /* disable left/right clock distribution */
1729         if (pipe != PIPE_B) {
1730                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1731                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1732                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1733         } else {
1734                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1735                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1736                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1737         }
1738 
1739         mutex_unlock(&dev_priv->dpio_lock);
1740 }
1741 
1742 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1743                 struct intel_digital_port *dport)
1744 {
1745         u32 port_mask;
1746         int dpll_reg;
1747 
1748         switch (dport->port) {
1749         case PORT_B:
1750                 port_mask = DPLL_PORTB_READY_MASK;
1751                 dpll_reg = DPLL(0);
1752                 break;
1753         case PORT_C:
1754                 port_mask = DPLL_PORTC_READY_MASK;
1755                 dpll_reg = DPLL(0);
1756                 break;
1757         case PORT_D:
1758                 port_mask = DPLL_PORTD_READY_MASK;
1759                 dpll_reg = DPIO_PHY_STATUS;
1760                 break;
1761         default:
1762                 BUG();
1763         }
1764 
1765         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1766                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1767                      port_name(dport->port), I915_READ(dpll_reg));
1768 }
1769 
1770 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1771 {
1772         struct drm_device *dev = crtc->base.dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775 
1776         if (WARN_ON(pll == NULL))
1777                 return;
1778 
1779         WARN_ON(!pll->refcount);
1780         if (pll->active == 0) {
1781                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1782                 WARN_ON(pll->on);
1783                 assert_shared_dpll_disabled(dev_priv, pll);
1784 
1785                 pll->mode_set(dev_priv, pll);
1786         }
1787 }
1788 
1789 /**
1790  * intel_enable_shared_dpll - enable PCH PLL
1791  * @dev_priv: i915 private structure
1792  * @pipe: pipe PLL to enable
1793  *
1794  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1795  * drives the transcoder clock.
1796  */
1797 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1798 {
1799         struct drm_device *dev = crtc->base.dev;
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1802 
1803         if (WARN_ON(pll == NULL))
1804                 return;
1805 
1806         if (WARN_ON(pll->refcount == 0))
1807                 return;
1808 
1809         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1810                       pll->name, pll->active, pll->on,
1811                       crtc->base.base.id);
1812 
1813         if (pll->active++) {
1814                 WARN_ON(!pll->on);
1815                 assert_shared_dpll_enabled(dev_priv, pll);
1816                 return;
1817         }
1818         WARN_ON(pll->on);
1819 
1820         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1821 
1822         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1823         pll->enable(dev_priv, pll);
1824         pll->on = true;
1825 }
1826 
1827 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1828 {
1829         struct drm_device *dev = crtc->base.dev;
1830         struct drm_i915_private *dev_priv = dev->dev_private;
1831         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1832 
1833         /* PCH only available on ILK+ */
1834         BUG_ON(INTEL_INFO(dev)->gen < 5);
1835         if (WARN_ON(pll == NULL))
1836                return;
1837 
1838         if (WARN_ON(pll->refcount == 0))
1839                 return;
1840 
1841         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1842                       pll->name, pll->active, pll->on,
1843                       crtc->base.base.id);
1844 
1845         if (WARN_ON(pll->active == 0)) {
1846                 assert_shared_dpll_disabled(dev_priv, pll);
1847                 return;
1848         }
1849 
1850         assert_shared_dpll_enabled(dev_priv, pll);
1851         WARN_ON(!pll->on);
1852         if (--pll->active)
1853                 return;
1854 
1855         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1856         pll->disable(dev_priv, pll);
1857         pll->on = false;
1858 
1859         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1860 }
1861 
1862 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1863                                            enum pipe pipe)
1864 {
1865         struct drm_device *dev = dev_priv->dev;
1866         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1868         uint32_t reg, val, pipeconf_val;
1869 
1870         /* PCH only available on ILK+ */
1871         BUG_ON(INTEL_INFO(dev)->gen < 5);
1872 
1873         /* Make sure PCH DPLL is enabled */
1874         assert_shared_dpll_enabled(dev_priv,
1875                                    intel_crtc_to_shared_dpll(intel_crtc));
1876 
1877         /* FDI must be feeding us bits for PCH ports */
1878         assert_fdi_tx_enabled(dev_priv, pipe);
1879         assert_fdi_rx_enabled(dev_priv, pipe);
1880 
1881         if (HAS_PCH_CPT(dev)) {
1882                 /* Workaround: Set the timing override bit before enabling the
1883                  * pch transcoder. */
1884                 reg = TRANS_CHICKEN2(pipe);
1885                 val = I915_READ(reg);
1886                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1887                 I915_WRITE(reg, val);
1888         }
1889 
1890         reg = PCH_TRANSCONF(pipe);
1891         val = I915_READ(reg);
1892         pipeconf_val = I915_READ(PIPECONF(pipe));
1893 
1894         if (HAS_PCH_IBX(dev_priv->dev)) {
1895                 /*
1896                  * make the BPC in transcoder be consistent with
1897                  * that in pipeconf reg.
1898                  */
1899                 val &= ~PIPECONF_BPC_MASK;
1900                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1901         }
1902 
1903         val &= ~TRANS_INTERLACE_MASK;
1904         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1905                 if (HAS_PCH_IBX(dev_priv->dev) &&
1906                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1907                         val |= TRANS_LEGACY_INTERLACED_ILK;
1908                 else
1909                         val |= TRANS_INTERLACED;
1910         else
1911                 val |= TRANS_PROGRESSIVE;
1912 
1913         I915_WRITE(reg, val | TRANS_ENABLE);
1914         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1915                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1916 }
1917 
1918 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1919                                       enum transcoder cpu_transcoder)
1920 {
1921         u32 val, pipeconf_val;
1922 
1923         /* PCH only available on ILK+ */
1924         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1925 
1926         /* FDI must be feeding us bits for PCH ports */
1927         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1928         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1929 
1930         /* Workaround: set timing override bit. */
1931         val = I915_READ(_TRANSA_CHICKEN2);
1932         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1933         I915_WRITE(_TRANSA_CHICKEN2, val);
1934 
1935         val = TRANS_ENABLE;
1936         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1937 
1938         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1939             PIPECONF_INTERLACED_ILK)
1940                 val |= TRANS_INTERLACED;
1941         else
1942                 val |= TRANS_PROGRESSIVE;
1943 
1944         I915_WRITE(LPT_TRANSCONF, val);
1945         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1946                 DRM_ERROR("Failed to enable PCH transcoder\n");
1947 }
1948 
1949 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1950                                             enum pipe pipe)
1951 {
1952         struct drm_device *dev = dev_priv->dev;
1953         uint32_t reg, val;
1954 
1955         /* FDI relies on the transcoder */
1956         assert_fdi_tx_disabled(dev_priv, pipe);
1957         assert_fdi_rx_disabled(dev_priv, pipe);
1958 
1959         /* Ports must be off as well */
1960         assert_pch_ports_disabled(dev_priv, pipe);
1961 
1962         reg = PCH_TRANSCONF(pipe);
1963         val = I915_READ(reg);
1964         val &= ~TRANS_ENABLE;
1965         I915_WRITE(reg, val);
1966         /* wait for PCH transcoder off, transcoder state */
1967         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1968                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1969 
1970         if (!HAS_PCH_IBX(dev)) {
1971                 /* Workaround: Clear the timing override chicken bit again. */
1972                 reg = TRANS_CHICKEN2(pipe);
1973                 val = I915_READ(reg);
1974                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1975                 I915_WRITE(reg, val);
1976         }
1977 }
1978 
1979 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1980 {
1981         u32 val;
1982 
1983         val = I915_READ(LPT_TRANSCONF);
1984         val &= ~TRANS_ENABLE;
1985         I915_WRITE(LPT_TRANSCONF, val);
1986         /* wait for PCH transcoder off, transcoder state */
1987         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1988                 DRM_ERROR("Failed to disable PCH transcoder\n");
1989 
1990         /* Workaround: clear timing override bit. */
1991         val = I915_READ(_TRANSA_CHICKEN2);
1992         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1993         I915_WRITE(_TRANSA_CHICKEN2, val);
1994 }
1995 
1996 /**
1997  * intel_enable_pipe - enable a pipe, asserting requirements
1998  * @crtc: crtc responsible for the pipe
1999  *
2000  * Enable @crtc's pipe, making sure that various hardware specific requirements
2001  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2002  */
2003 static void intel_enable_pipe(struct intel_crtc *crtc)
2004 {
2005         struct drm_device *dev = crtc->base.dev;
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         enum pipe pipe = crtc->pipe;
2008         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2009                                                                       pipe);
2010         enum pipe pch_transcoder;
2011         int reg;
2012         u32 val;
2013 
2014         assert_planes_disabled(dev_priv, pipe);
2015         assert_cursor_disabled(dev_priv, pipe);
2016         assert_sprites_disabled(dev_priv, pipe);
2017 
2018         if (HAS_PCH_LPT(dev_priv->dev))
2019                 pch_transcoder = TRANSCODER_A;
2020         else
2021                 pch_transcoder = pipe;
2022 
2023         /*
2024          * A pipe without a PLL won't actually be able to drive bits from
2025          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2026          * need the check.
2027          */
2028         if (!HAS_PCH_SPLIT(dev_priv->dev))
2029                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2030                         assert_dsi_pll_enabled(dev_priv);
2031                 else
2032                         assert_pll_enabled(dev_priv, pipe);
2033         else {
2034                 if (crtc->config.has_pch_encoder) {
2035                         /* if driving the PCH, we need FDI enabled */
2036                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2037                         assert_fdi_tx_pll_enabled(dev_priv,
2038                                                   (enum pipe) cpu_transcoder);
2039                 }
2040                 /* FIXME: assert CPU port conditions for SNB+ */
2041         }
2042 
2043         reg = PIPECONF(cpu_transcoder);
2044         val = I915_READ(reg);
2045         if (val & PIPECONF_ENABLE) {
2046                 WARN_ON(!(pipe == PIPE_A &&
2047                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2048                 return;
2049         }
2050 
2051         I915_WRITE(reg, val | PIPECONF_ENABLE);
2052         POSTING_READ(reg);
2053 }
2054 
2055 /**
2056  * intel_disable_pipe - disable a pipe, asserting requirements
2057  * @dev_priv: i915 private structure
2058  * @pipe: pipe to disable
2059  *
2060  * Disable @pipe, making sure that various hardware specific requirements
2061  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2062  *
2063  * @pipe should be %PIPE_A or %PIPE_B.
2064  *
2065  * Will wait until the pipe has shut down before returning.
2066  */
2067 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2068                                enum pipe pipe)
2069 {
2070         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2071                                                                       pipe);
2072         int reg;
2073         u32 val;
2074 
2075         /*
2076          * Make sure planes won't keep trying to pump pixels to us,
2077          * or we might hang the display.
2078          */
2079         assert_planes_disabled(dev_priv, pipe);
2080         assert_cursor_disabled(dev_priv, pipe);
2081         assert_sprites_disabled(dev_priv, pipe);
2082 
2083         /* Don't disable pipe A or pipe A PLLs if needed */
2084         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2085                 return;
2086 
2087         reg = PIPECONF(cpu_transcoder);
2088         val = I915_READ(reg);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 return;
2091 
2092         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2093         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2094 }
2095 
2096 /*
2097  * Plane regs are double buffered, going from enabled->disabled needs a
2098  * trigger in order to latch.  The display address reg provides this.
2099  */
2100 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2101                                enum plane plane)
2102 {
2103         struct drm_device *dev = dev_priv->dev;
2104         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2105 
2106         I915_WRITE(reg, I915_READ(reg));
2107         POSTING_READ(reg);
2108 }
2109 
2110 /**
2111  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2112  * @dev_priv: i915 private structure
2113  * @plane: plane to enable
2114  * @pipe: pipe being fed
2115  *
2116  * Enable @plane on @pipe, making sure that @pipe is running first.
2117  */
2118 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2119                                           enum plane plane, enum pipe pipe)
2120 {
2121         struct drm_device *dev = dev_priv->dev;
2122         struct intel_crtc *intel_crtc =
2123                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2124         int reg;
2125         u32 val;
2126 
2127         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128         assert_pipe_enabled(dev_priv, pipe);
2129 
2130         if (intel_crtc->primary_enabled)
2131                 return;
2132 
2133         intel_crtc->primary_enabled = true;
2134 
2135         reg = DSPCNTR(plane);
2136         val = I915_READ(reg);
2137         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2138 
2139         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2140         intel_flush_primary_plane(dev_priv, plane);
2141 
2142         /*
2143          * BDW signals flip done immediately if the plane
2144          * is disabled, even if the plane enable is already
2145          * armed to occur at the next vblank :(
2146          */
2147         if (IS_BROADWELL(dev))
2148                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2149 }
2150 
2151 /**
2152  * intel_disable_primary_hw_plane - disable the primary hardware plane
2153  * @dev_priv: i915 private structure
2154  * @plane: plane to disable
2155  * @pipe: pipe consuming the data
2156  *
2157  * Disable @plane; should be an independent operation.
2158  */
2159 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2160                                            enum plane plane, enum pipe pipe)
2161 {
2162         struct intel_crtc *intel_crtc =
2163                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2164         int reg;
2165         u32 val;
2166 
2167         if (!intel_crtc->primary_enabled)
2168                 return;
2169 
2170         intel_crtc->primary_enabled = false;
2171 
2172         reg = DSPCNTR(plane);
2173         val = I915_READ(reg);
2174         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2175 
2176         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2177         intel_flush_primary_plane(dev_priv, plane);
2178 }
2179 
2180 static bool need_vtd_wa(struct drm_device *dev)
2181 {
2182 #ifdef CONFIG_INTEL_IOMMU
2183         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2184                 return true;
2185 #endif
2186         return false;
2187 }
2188 
2189 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2190 {
2191         int tile_height;
2192 
2193         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2194         return ALIGN(height, tile_height);
2195 }
2196 
2197 int
2198 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2199                            struct drm_i915_gem_object *obj,
2200                            struct intel_engine_cs *pipelined)
2201 {
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         u32 alignment;
2204         int ret;
2205 
2206         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2207 
2208         switch (obj->tiling_mode) {
2209         case I915_TILING_NONE:
2210                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2211                         alignment = 128 * 1024;
2212                 else if (INTEL_INFO(dev)->gen >= 4)
2213                         alignment = 4 * 1024;
2214                 else
2215                         alignment = 64 * 1024;
2216                 break;
2217         case I915_TILING_X:
2218                 /* pin() will align the object as required by fence */
2219                 alignment = 0;
2220                 break;
2221         case I915_TILING_Y:
2222                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2223                 return -EINVAL;
2224         default:
2225                 BUG();
2226         }
2227 
2228         /* Note that the w/a also requires 64 PTE of padding following the
2229          * bo. We currently fill all unused PTE with the shadow page and so
2230          * we should always have valid PTE following the scanout preventing
2231          * the VT-d warning.
2232          */
2233         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2234                 alignment = 256 * 1024;
2235 
2236         /*
2237          * Global gtt pte registers are special registers which actually forward
2238          * writes to a chunk of system memory. Which means that there is no risk
2239          * that the register values disappear as soon as we call
2240          * intel_runtime_pm_put(), so it is correct to wrap only the
2241          * pin/unpin/fence and not more.
2242          */
2243         intel_runtime_pm_get(dev_priv);
2244 
2245         dev_priv->mm.interruptible = false;
2246         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2247         if (ret)
2248                 goto err_interruptible;
2249 
2250         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2251          * fence, whereas 965+ only requires a fence if using
2252          * framebuffer compression.  For simplicity, we always install
2253          * a fence as the cost is not that onerous.
2254          */
2255         ret = i915_gem_object_get_fence(obj);
2256         if (ret)
2257                 goto err_unpin;
2258 
2259         i915_gem_object_pin_fence(obj);
2260 
2261         dev_priv->mm.interruptible = true;
2262         intel_runtime_pm_put(dev_priv);
2263         return 0;
2264 
2265 err_unpin:
2266         i915_gem_object_unpin_from_display_plane(obj);
2267 err_interruptible:
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return ret;
2271 }
2272 
2273 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2274 {
2275         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2276 
2277         i915_gem_object_unpin_fence(obj);
2278         i915_gem_object_unpin_from_display_plane(obj);
2279 }
2280 
2281 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2282  * is assumed to be a power-of-two. */
2283 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2284                                              unsigned int tiling_mode,
2285                                              unsigned int cpp,
2286                                              unsigned int pitch)
2287 {
2288         if (tiling_mode != I915_TILING_NONE) {
2289                 unsigned int tile_rows, tiles;
2290 
2291                 tile_rows = *y / 8;
2292                 *y %= 8;
2293 
2294                 tiles = *x / (512/cpp);
2295                 *x %= 512/cpp;
2296 
2297                 return tile_rows * pitch * 8 + tiles * 4096;
2298         } else {
2299                 unsigned int offset;
2300 
2301                 offset = *y * pitch + *x * cpp;
2302                 *y = 0;
2303                 *x = (offset & 4095) / cpp;
2304                 return offset & -4096;
2305         }
2306 }
2307 
2308 int intel_format_to_fourcc(int format)
2309 {
2310         switch (format) {
2311         case DISPPLANE_8BPP:
2312                 return DRM_FORMAT_C8;
2313         case DISPPLANE_BGRX555:
2314                 return DRM_FORMAT_XRGB1555;
2315         case DISPPLANE_BGRX565:
2316                 return DRM_FORMAT_RGB565;
2317         default:
2318         case DISPPLANE_BGRX888:
2319                 return DRM_FORMAT_XRGB8888;
2320         case DISPPLANE_RGBX888:
2321                 return DRM_FORMAT_XBGR8888;
2322         case DISPPLANE_BGRX101010:
2323                 return DRM_FORMAT_XRGB2101010;
2324         case DISPPLANE_RGBX101010:
2325                 return DRM_FORMAT_XBGR2101010;
2326         }
2327 }
2328 
2329 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2330                                   struct intel_plane_config *plane_config)
2331 {
2332         struct drm_device *dev = crtc->base.dev;
2333         struct drm_i915_gem_object *obj = NULL;
2334         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2335         u32 base = plane_config->base;
2336 
2337         if (plane_config->size == 0)
2338                 return false;
2339 
2340         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2341                                                              plane_config->size);
2342         if (!obj)
2343                 return false;
2344 
2345         if (plane_config->tiled) {
2346                 obj->tiling_mode = I915_TILING_X;
2347                 obj->stride = crtc->base.primary->fb->pitches[0];
2348         }
2349 
2350         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2351         mode_cmd.width = crtc->base.primary->fb->width;
2352         mode_cmd.height = crtc->base.primary->fb->height;
2353         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2354 
2355         mutex_lock(&dev->struct_mutex);
2356 
2357         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2358                                    &mode_cmd, obj)) {
2359                 DRM_DEBUG_KMS("intel fb init failed\n");
2360                 goto out_unref_obj;
2361         }
2362 
2363         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2364         mutex_unlock(&dev->struct_mutex);
2365 
2366         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2367         return true;
2368 
2369 out_unref_obj:
2370         drm_gem_object_unreference(&obj->base);
2371         mutex_unlock(&dev->struct_mutex);
2372         return false;
2373 }
2374 
2375 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2376                                  struct intel_plane_config *plane_config)
2377 {
2378         struct drm_device *dev = intel_crtc->base.dev;
2379         struct drm_crtc *c;
2380         struct intel_crtc *i;
2381         struct drm_i915_gem_object *obj;
2382 
2383         if (!intel_crtc->base.primary->fb)
2384                 return;
2385 
2386         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2387                 return;
2388 
2389         kfree(intel_crtc->base.primary->fb);
2390         intel_crtc->base.primary->fb = NULL;
2391 
2392         /*
2393          * Failed to alloc the obj, check to see if we should share
2394          * an fb with another CRTC instead
2395          */
2396         for_each_crtc(dev, c) {
2397                 i = to_intel_crtc(c);
2398 
2399                 if (c == &intel_crtc->base)
2400                         continue;
2401 
2402                 if (!i->active)
2403                         continue;
2404 
2405                 obj = intel_fb_obj(c->primary->fb);
2406                 if (obj == NULL)
2407                         continue;
2408 
2409                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2410                         drm_framebuffer_reference(c->primary->fb);
2411                         intel_crtc->base.primary->fb = c->primary->fb;
2412                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2413                         break;
2414                 }
2415         }
2416 }
2417 
2418 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2419                                       struct drm_framebuffer *fb,
2420                                       int x, int y)
2421 {
2422         struct drm_device *dev = crtc->dev;
2423         struct drm_i915_private *dev_priv = dev->dev_private;
2424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2425         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2426         int plane = intel_crtc->plane;
2427         unsigned long linear_offset;
2428         u32 dspcntr;
2429         u32 reg;
2430 
2431         reg = DSPCNTR(plane);
2432         dspcntr = I915_READ(reg);
2433         /* Mask out pixel format bits in case we change it */
2434         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2435         switch (fb->pixel_format) {
2436         case DRM_FORMAT_C8:
2437                 dspcntr |= DISPPLANE_8BPP;
2438                 break;
2439         case DRM_FORMAT_XRGB1555:
2440         case DRM_FORMAT_ARGB1555:
2441                 dspcntr |= DISPPLANE_BGRX555;
2442                 break;
2443         case DRM_FORMAT_RGB565:
2444                 dspcntr |= DISPPLANE_BGRX565;
2445                 break;
2446         case DRM_FORMAT_XRGB8888:
2447         case DRM_FORMAT_ARGB8888:
2448                 dspcntr |= DISPPLANE_BGRX888;
2449                 break;
2450         case DRM_FORMAT_XBGR8888:
2451         case DRM_FORMAT_ABGR8888:
2452                 dspcntr |= DISPPLANE_RGBX888;
2453                 break;
2454         case DRM_FORMAT_XRGB2101010:
2455         case DRM_FORMAT_ARGB2101010:
2456                 dspcntr |= DISPPLANE_BGRX101010;
2457                 break;
2458         case DRM_FORMAT_XBGR2101010:
2459         case DRM_FORMAT_ABGR2101010:
2460                 dspcntr |= DISPPLANE_RGBX101010;
2461                 break;
2462         default:
2463                 BUG();
2464         }
2465 
2466         if (INTEL_INFO(dev)->gen >= 4) {
2467                 if (obj->tiling_mode != I915_TILING_NONE)
2468                         dspcntr |= DISPPLANE_TILED;
2469                 else
2470                         dspcntr &= ~DISPPLANE_TILED;
2471         }
2472 
2473         if (IS_G4X(dev))
2474                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2475 
2476         I915_WRITE(reg, dspcntr);
2477 
2478         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2479 
2480         if (INTEL_INFO(dev)->gen >= 4) {
2481                 intel_crtc->dspaddr_offset =
2482                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2483                                                        fb->bits_per_pixel / 8,
2484                                                        fb->pitches[0]);
2485                 linear_offset -= intel_crtc->dspaddr_offset;
2486         } else {
2487                 intel_crtc->dspaddr_offset = linear_offset;
2488         }
2489 
2490         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2491                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2492                       fb->pitches[0]);
2493         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2494         if (INTEL_INFO(dev)->gen >= 4) {
2495                 I915_WRITE(DSPSURF(plane),
2496                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2497                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2498                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2499         } else
2500                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2501         POSTING_READ(reg);
2502 }
2503 
2504 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2505                                           struct drm_framebuffer *fb,
2506                                           int x, int y)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2512         int plane = intel_crtc->plane;
2513         unsigned long linear_offset;
2514         u32 dspcntr;
2515         u32 reg;
2516 
2517         reg = DSPCNTR(plane);
2518         dspcntr = I915_READ(reg);
2519         /* Mask out pixel format bits in case we change it */
2520         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2521         switch (fb->pixel_format) {
2522         case DRM_FORMAT_C8:
2523                 dspcntr |= DISPPLANE_8BPP;
2524                 break;
2525         case DRM_FORMAT_RGB565:
2526                 dspcntr |= DISPPLANE_BGRX565;
2527                 break;
2528         case DRM_FORMAT_XRGB8888:
2529         case DRM_FORMAT_ARGB8888:
2530                 dspcntr |= DISPPLANE_BGRX888;
2531                 break;
2532         case DRM_FORMAT_XBGR8888:
2533         case DRM_FORMAT_ABGR8888:
2534                 dspcntr |= DISPPLANE_RGBX888;
2535                 break;
2536         case DRM_FORMAT_XRGB2101010:
2537         case DRM_FORMAT_ARGB2101010:
2538                 dspcntr |= DISPPLANE_BGRX101010;
2539                 break;
2540         case DRM_FORMAT_XBGR2101010:
2541         case DRM_FORMAT_ABGR2101010:
2542                 dspcntr |= DISPPLANE_RGBX101010;
2543                 break;
2544         default:
2545                 BUG();
2546         }
2547 
2548         if (obj->tiling_mode != I915_TILING_NONE)
2549                 dspcntr |= DISPPLANE_TILED;
2550         else
2551                 dspcntr &= ~DISPPLANE_TILED;
2552 
2553         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2554                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2555         else
2556                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2557 
2558         I915_WRITE(reg, dspcntr);
2559 
2560         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2561         intel_crtc->dspaddr_offset =
2562                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2563                                                fb->bits_per_pixel / 8,
2564                                                fb->pitches[0]);
2565         linear_offset -= intel_crtc->dspaddr_offset;
2566 
2567         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2568                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2569                       fb->pitches[0]);
2570         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2571         I915_WRITE(DSPSURF(plane),
2572                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2573         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2574                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2575         } else {
2576                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2577                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2578         }
2579         POSTING_READ(reg);
2580 }
2581 
2582 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2583 static int
2584 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2585                            int x, int y, enum mode_set_atomic state)
2586 {
2587         struct drm_device *dev = crtc->dev;
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589 
2590         if (dev_priv->display.disable_fbc)
2591                 dev_priv->display.disable_fbc(dev);
2592         intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2593 
2594         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2595 
2596         return 0;
2597 }
2598 
2599 void intel_display_handle_reset(struct drm_device *dev)
2600 {
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602         struct drm_crtc *crtc;
2603 
2604         /*
2605          * Flips in the rings have been nuked by the reset,
2606          * so complete all pending flips so that user space
2607          * will get its events and not get stuck.
2608          *
2609          * Also update the base address of all primary
2610          * planes to the the last fb to make sure we're
2611          * showing the correct fb after a reset.
2612          *
2613          * Need to make two loops over the crtcs so that we
2614          * don't try to grab a crtc mutex before the
2615          * pending_flip_queue really got woken up.
2616          */
2617 
2618         for_each_crtc(dev, crtc) {
2619                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620                 enum plane plane = intel_crtc->plane;
2621 
2622                 intel_prepare_page_flip(dev, plane);
2623                 intel_finish_page_flip_plane(dev, plane);
2624         }
2625 
2626         for_each_crtc(dev, crtc) {
2627                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2628 
2629                 drm_modeset_lock(&crtc->mutex, NULL);
2630                 /*
2631                  * FIXME: Once we have proper support for primary planes (and
2632                  * disabling them without disabling the entire crtc) allow again
2633                  * a NULL crtc->primary->fb.
2634                  */
2635                 if (intel_crtc->active && crtc->primary->fb)
2636                         dev_priv->display.update_primary_plane(crtc,
2637                                                                crtc->primary->fb,
2638                                                                crtc->x,
2639                                                                crtc->y);
2640                 drm_modeset_unlock(&crtc->mutex);
2641         }
2642 }
2643 
2644 static int
2645 intel_finish_fb(struct drm_framebuffer *old_fb)
2646 {
2647         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2648         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2649         bool was_interruptible = dev_priv->mm.interruptible;
2650         int ret;
2651 
2652         /* Big Hammer, we also need to ensure that any pending
2653          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2654          * current scanout is retired before unpinning the old
2655          * framebuffer.
2656          *
2657          * This should only fail upon a hung GPU, in which case we
2658          * can safely continue.
2659          */
2660         dev_priv->mm.interruptible = false;
2661         ret = i915_gem_object_finish_gpu(obj);
2662         dev_priv->mm.interruptible = was_interruptible;
2663 
2664         return ret;
2665 }
2666 
2667 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2668 {
2669         struct drm_device *dev = crtc->dev;
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2672         unsigned long flags;
2673         bool pending;
2674 
2675         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2676             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2677                 return false;
2678 
2679         spin_lock_irqsave(&dev->event_lock, flags);
2680         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2681         spin_unlock_irqrestore(&dev->event_lock, flags);
2682 
2683         return pending;
2684 }
2685 
2686 static int
2687 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2688                     struct drm_framebuffer *fb)
2689 {
2690         struct drm_device *dev = crtc->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693         enum pipe pipe = intel_crtc->pipe;
2694         struct drm_framebuffer *old_fb = crtc->primary->fb;
2695         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2696         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2697         int ret;
2698 
2699         if (intel_crtc_has_pending_flip(crtc)) {
2700                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2701                 return -EBUSY;
2702         }
2703 
2704         /* no fb bound */
2705         if (!fb) {
2706                 DRM_ERROR("No FB bound\n");
2707                 return 0;
2708         }
2709 
2710         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2711                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2712                           plane_name(intel_crtc->plane),
2713                           INTEL_INFO(dev)->num_pipes);
2714                 return -EINVAL;
2715         }
2716 
2717         mutex_lock(&dev->struct_mutex);
2718         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2719         if (ret == 0)
2720                 i915_gem_track_fb(old_obj, obj,
2721                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2722         mutex_unlock(&dev->struct_mutex);
2723         if (ret != 0) {
2724                 DRM_ERROR("pin & fence failed\n");
2725                 return ret;
2726         }
2727 
2728         /*
2729          * Update pipe size and adjust fitter if needed: the reason for this is
2730          * that in compute_mode_changes we check the native mode (not the pfit
2731          * mode) to see if we can flip rather than do a full mode set. In the
2732          * fastboot case, we'll flip, but if we don't update the pipesrc and
2733          * pfit state, we'll end up with a big fb scanned out into the wrong
2734          * sized surface.
2735          *
2736          * To fix this properly, we need to hoist the checks up into
2737          * compute_mode_changes (or above), check the actual pfit state and
2738          * whether the platform allows pfit disable with pipe active, and only
2739          * then update the pipesrc and pfit state, even on the flip path.
2740          */
2741         if (i915.fastboot) {
2742                 const struct drm_display_mode *adjusted_mode =
2743                         &intel_crtc->config.adjusted_mode;
2744 
2745                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2746                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2747                            (adjusted_mode->crtc_vdisplay - 1));
2748                 if (!intel_crtc->config.pch_pfit.enabled &&
2749                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2750                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2751                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2752                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2753                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2754                 }
2755                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2756                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2757         }
2758 
2759         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2760 
2761         if (intel_crtc->active)
2762                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2763 
2764         crtc->primary->fb = fb;
2765         crtc->x = x;
2766         crtc->y = y;
2767 
2768         if (old_fb) {
2769                 if (intel_crtc->active && old_fb != fb)
2770                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2771                 mutex_lock(&dev->struct_mutex);
2772                 intel_unpin_fb_obj(old_obj);
2773                 mutex_unlock(&dev->struct_mutex);
2774         }
2775 
2776         mutex_lock(&dev->struct_mutex);
2777         intel_update_fbc(dev);
2778         mutex_unlock(&dev->struct_mutex);
2779 
2780         return 0;
2781 }
2782 
2783 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2784 {
2785         struct drm_device *dev = crtc->dev;
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788         int pipe = intel_crtc->pipe;
2789         u32 reg, temp;
2790 
2791         /* enable normal train */
2792         reg = FDI_TX_CTL(pipe);
2793         temp = I915_READ(reg);
2794         if (IS_IVYBRIDGE(dev)) {
2795                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2796                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2797         } else {
2798                 temp &= ~FDI_LINK_TRAIN_NONE;
2799                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2800         }
2801         I915_WRITE(reg, temp);
2802 
2803         reg = FDI_RX_CTL(pipe);
2804         temp = I915_READ(reg);
2805         if (HAS_PCH_CPT(dev)) {
2806                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2807                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2808         } else {
2809                 temp &= ~FDI_LINK_TRAIN_NONE;
2810                 temp |= FDI_LINK_TRAIN_NONE;
2811         }
2812         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2813 
2814         /* wait one idle pattern time */
2815         POSTING_READ(reg);
2816         udelay(1000);
2817 
2818         /* IVB wants error correction enabled */
2819         if (IS_IVYBRIDGE(dev))
2820                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2821                            FDI_FE_ERRC_ENABLE);
2822 }
2823 
2824 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2825 {
2826         return crtc->base.enabled && crtc->active &&
2827                 crtc->config.has_pch_encoder;
2828 }
2829 
2830 static void ivb_modeset_global_resources(struct drm_device *dev)
2831 {
2832         struct drm_i915_private *dev_priv = dev->dev_private;
2833         struct intel_crtc *pipe_B_crtc =
2834                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2835         struct intel_crtc *pipe_C_crtc =
2836                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2837         uint32_t temp;
2838 
2839         /*
2840          * When everything is off disable fdi C so that we could enable fdi B
2841          * with all lanes. Note that we don't care about enabled pipes without
2842          * an enabled pch encoder.
2843          */
2844         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2845             !pipe_has_enabled_pch(pipe_C_crtc)) {
2846                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2847                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2848 
2849                 temp = I915_READ(SOUTH_CHICKEN1);
2850                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2851                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2852                 I915_WRITE(SOUTH_CHICKEN1, temp);
2853         }
2854 }
2855 
2856 /* The FDI link training functions for ILK/Ibexpeak. */
2857 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2858 {
2859         struct drm_device *dev = crtc->dev;
2860         struct drm_i915_private *dev_priv = dev->dev_private;
2861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2862         int pipe = intel_crtc->pipe;
2863         u32 reg, temp, tries;
2864 
2865         /* FDI needs bits from pipe first */
2866         assert_pipe_enabled(dev_priv, pipe);
2867 
2868         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2869            for train result */
2870         reg = FDI_RX_IMR(pipe);
2871         temp = I915_READ(reg);
2872         temp &= ~FDI_RX_SYMBOL_LOCK;
2873         temp &= ~FDI_RX_BIT_LOCK;
2874         I915_WRITE(reg, temp);
2875         I915_READ(reg);
2876         udelay(150);
2877 
2878         /* enable CPU FDI TX and PCH FDI RX */
2879         reg = FDI_TX_CTL(pipe);
2880         temp = I915_READ(reg);
2881         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2882         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2883         temp &= ~FDI_LINK_TRAIN_NONE;
2884         temp |= FDI_LINK_TRAIN_PATTERN_1;
2885         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2886 
2887         reg = FDI_RX_CTL(pipe);
2888         temp = I915_READ(reg);
2889         temp &= ~FDI_LINK_TRAIN_NONE;
2890         temp |= FDI_LINK_TRAIN_PATTERN_1;
2891         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2892 
2893         POSTING_READ(reg);
2894         udelay(150);
2895 
2896         /* Ironlake workaround, enable clock pointer after FDI enable*/
2897         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2898         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2899                    FDI_RX_PHASE_SYNC_POINTER_EN);
2900 
2901         reg = FDI_RX_IIR(pipe);
2902         for (tries = 0; tries < 5; tries++) {
2903                 temp = I915_READ(reg);
2904                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2905 
2906                 if ((temp & FDI_RX_BIT_LOCK)) {
2907                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2908                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2909                         break;
2910                 }
2911         }
2912         if (tries == 5)
2913                 DRM_ERROR("FDI train 1 fail!\n");
2914 
2915         /* Train 2 */
2916         reg = FDI_TX_CTL(pipe);
2917         temp = I915_READ(reg);
2918         temp &= ~FDI_LINK_TRAIN_NONE;
2919         temp |= FDI_LINK_TRAIN_PATTERN_2;
2920         I915_WRITE(reg, temp);
2921 
2922         reg = FDI_RX_CTL(pipe);
2923         temp = I915_READ(reg);
2924         temp &= ~FDI_LINK_TRAIN_NONE;
2925         temp |= FDI_LINK_TRAIN_PATTERN_2;
2926         I915_WRITE(reg, temp);
2927 
2928         POSTING_READ(reg);
2929         udelay(150);
2930 
2931         reg = FDI_RX_IIR(pipe);
2932         for (tries = 0; tries < 5; tries++) {
2933                 temp = I915_READ(reg);
2934                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2935 
2936                 if (temp & FDI_RX_SYMBOL_LOCK) {
2937                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2938                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2939                         break;
2940                 }
2941         }
2942         if (tries == 5)
2943                 DRM_ERROR("FDI train 2 fail!\n");
2944 
2945         DRM_DEBUG_KMS("FDI train done\n");
2946 
2947 }
2948 
2949 static const int snb_b_fdi_train_param[] = {
2950         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2951         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2952         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2953         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2954 };
2955 
2956 /* The FDI link training functions for SNB/Cougarpoint. */
2957 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2958 {
2959         struct drm_device *dev = crtc->dev;
2960         struct drm_i915_private *dev_priv = dev->dev_private;
2961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2962         int pipe = intel_crtc->pipe;
2963         u32 reg, temp, i, retry;
2964 
2965         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2966            for train result */
2967         reg = FDI_RX_IMR(pipe);
2968         temp = I915_READ(reg);
2969         temp &= ~FDI_RX_SYMBOL_LOCK;
2970         temp &= ~FDI_RX_BIT_LOCK;
2971         I915_WRITE(reg, temp);
2972 
2973         POSTING_READ(reg);
2974         udelay(150);
2975 
2976         /* enable CPU FDI TX and PCH FDI RX */
2977         reg = FDI_TX_CTL(pipe);
2978         temp = I915_READ(reg);
2979         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2980         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2981         temp &= ~FDI_LINK_TRAIN_NONE;
2982         temp |= FDI_LINK_TRAIN_PATTERN_1;
2983         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2984         /* SNB-B */
2985         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2986         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2987 
2988         I915_WRITE(FDI_RX_MISC(pipe),
2989                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2990 
2991         reg = FDI_RX_CTL(pipe);
2992         temp = I915_READ(reg);
2993         if (HAS_PCH_CPT(dev)) {
2994                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2995                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2996         } else {
2997                 temp &= ~FDI_LINK_TRAIN_NONE;
2998                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2999         }
3000         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3001 
3002         POSTING_READ(reg);
3003         udelay(150);
3004 
3005         for (i = 0; i < 4; i++) {
3006                 reg = FDI_TX_CTL(pipe);
3007                 temp = I915_READ(reg);
3008                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3009                 temp |= snb_b_fdi_train_param[i];
3010                 I915_WRITE(reg, temp);
3011 
3012                 POSTING_READ(reg);
3013                 udelay(500);
3014 
3015                 for (retry = 0; retry < 5; retry++) {
3016                         reg = FDI_RX_IIR(pipe);
3017                         temp = I915_READ(reg);
3018                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3019                         if (temp & FDI_RX_BIT_LOCK) {
3020                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3021                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3022                                 break;
3023                         }
3024                         udelay(50);
3025                 }
3026                 if (retry < 5)
3027                         break;
3028         }
3029         if (i == 4)
3030                 DRM_ERROR("FDI train 1 fail!\n");
3031 
3032         /* Train 2 */
3033         reg = FDI_TX_CTL(pipe);
3034         temp = I915_READ(reg);
3035         temp &= ~FDI_LINK_TRAIN_NONE;
3036         temp |= FDI_LINK_TRAIN_PATTERN_2;
3037         if (IS_GEN6(dev)) {
3038                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3039                 /* SNB-B */
3040                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3041         }
3042         I915_WRITE(reg, temp);
3043 
3044         reg = FDI_RX_CTL(pipe);
3045         temp = I915_READ(reg);
3046         if (HAS_PCH_CPT(dev)) {
3047                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3048                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3049         } else {
3050                 temp &= ~FDI_LINK_TRAIN_NONE;
3051                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3052         }
3053         I915_WRITE(reg, temp);
3054 
3055         POSTING_READ(reg);
3056         udelay(150);
3057 
3058         for (i = 0; i < 4; i++) {
3059                 reg = FDI_TX_CTL(pipe);
3060                 temp = I915_READ(reg);
3061                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3062                 temp |= snb_b_fdi_train_param[i];
3063                 I915_WRITE(reg, temp);
3064 
3065                 POSTING_READ(reg);
3066                 udelay(500);
3067 
3068                 for (retry = 0; retry < 5; retry++) {
3069                         reg = FDI_RX_IIR(pipe);
3070                         temp = I915_READ(reg);
3071                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3072                         if (temp & FDI_RX_SYMBOL_LOCK) {
3073                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3074                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3075                                 break;
3076                         }
3077                         udelay(50);
3078                 }
3079                 if (retry < 5)
3080                         break;
3081         }
3082         if (i == 4)
3083                 DRM_ERROR("FDI train 2 fail!\n");
3084 
3085         DRM_DEBUG_KMS("FDI train done.\n");
3086 }
3087 
3088 /* Manual link training for Ivy Bridge A0 parts */
3089 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3090 {
3091         struct drm_device *dev = crtc->dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3094         int pipe = intel_crtc->pipe;
3095         u32 reg, temp, i, j;
3096 
3097         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3098            for train result */
3099         reg = FDI_RX_IMR(pipe);
3100         temp = I915_READ(reg);
3101         temp &= ~FDI_RX_SYMBOL_LOCK;
3102         temp &= ~FDI_RX_BIT_LOCK;
3103         I915_WRITE(reg, temp);
3104 
3105         POSTING_READ(reg);
3106         udelay(150);
3107 
3108         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3109                       I915_READ(FDI_RX_IIR(pipe)));
3110 
3111         /* Try each vswing and preemphasis setting twice before moving on */
3112         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3113                 /* disable first in case we need to retry */
3114                 reg = FDI_TX_CTL(pipe);
3115                 temp = I915_READ(reg);
3116                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3117                 temp &= ~FDI_TX_ENABLE;
3118                 I915_WRITE(reg, temp);
3119 
3120                 reg = FDI_RX_CTL(pipe);
3121                 temp = I915_READ(reg);
3122                 temp &= ~FDI_LINK_TRAIN_AUTO;
3123                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3124                 temp &= ~FDI_RX_ENABLE;
3125                 I915_WRITE(reg, temp);
3126 
3127                 /* enable CPU FDI TX and PCH FDI RX */
3128                 reg = FDI_TX_CTL(pipe);
3129                 temp = I915_READ(reg);
3130                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3131                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3132                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3133                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3134                 temp |= snb_b_fdi_train_param[j/2];
3135                 temp |= FDI_COMPOSITE_SYNC;
3136                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3137 
3138                 I915_WRITE(FDI_RX_MISC(pipe),
3139                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3140 
3141                 reg = FDI_RX_CTL(pipe);
3142                 temp = I915_READ(reg);
3143                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3144                 temp |= FDI_COMPOSITE_SYNC;
3145                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3146 
3147                 POSTING_READ(reg);
3148                 udelay(1); /* should be 0.5us */
3149 
3150                 for (i = 0; i < 4; i++) {
3151                         reg = FDI_RX_IIR(pipe);
3152                         temp = I915_READ(reg);
3153                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3154 
3155                         if (temp & FDI_RX_BIT_LOCK ||
3156                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3157                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3158                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3159                                               i);
3160                                 break;
3161                         }
3162                         udelay(1); /* should be 0.5us */
3163                 }
3164                 if (i == 4) {
3165                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3166                         continue;
3167                 }
3168 
3169                 /* Train 2 */
3170                 reg = FDI_TX_CTL(pipe);
3171                 temp = I915_READ(reg);
3172                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3173                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3174                 I915_WRITE(reg, temp);
3175 
3176                 reg = FDI_RX_CTL(pipe);
3177                 temp = I915_READ(reg);
3178                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3179                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3180                 I915_WRITE(reg, temp);
3181 
3182                 POSTING_READ(reg);
3183                 udelay(2); /* should be 1.5us */
3184 
3185                 for (i = 0; i < 4; i++) {
3186                         reg = FDI_RX_IIR(pipe);
3187                         temp = I915_READ(reg);
3188                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3189 
3190                         if (temp & FDI_RX_SYMBOL_LOCK ||
3191                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3192                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3193                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3194                                               i);
3195                                 goto train_done;
3196                         }
3197                         udelay(2); /* should be 1.5us */
3198                 }
3199                 if (i == 4)
3200                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3201         }
3202 
3203 train_done:
3204         DRM_DEBUG_KMS("FDI train done.\n");
3205 }
3206 
3207 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3208 {
3209         struct drm_device *dev = intel_crtc->base.dev;
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211         int pipe = intel_crtc->pipe;
3212         u32 reg, temp;
3213 
3214 
3215         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3216         reg = FDI_RX_CTL(pipe);
3217         temp = I915_READ(reg);
3218         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3219         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3220         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3221         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3222 
3223         POSTING_READ(reg);
3224         udelay(200);
3225 
3226         /* Switch from Rawclk to PCDclk */
3227         temp = I915_READ(reg);
3228         I915_WRITE(reg, temp | FDI_PCDCLK);
3229 
3230         POSTING_READ(reg);
3231         udelay(200);
3232 
3233         /* Enable CPU FDI TX PLL, always on for Ironlake */
3234         reg = FDI_TX_CTL(pipe);
3235         temp = I915_READ(reg);
3236         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3237                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3238 
3239                 POSTING_READ(reg);
3240                 udelay(100);
3241         }
3242 }
3243 
3244 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3245 {
3246         struct drm_device *dev = intel_crtc->base.dev;
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         int pipe = intel_crtc->pipe;
3249         u32 reg, temp;
3250 
3251         /* Switch from PCDclk to Rawclk */
3252         reg = FDI_RX_CTL(pipe);
3253         temp = I915_READ(reg);
3254         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3255 
3256         /* Disable CPU FDI TX PLL */
3257         reg = FDI_TX_CTL(pipe);
3258         temp = I915_READ(reg);
3259         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3260 
3261         POSTING_READ(reg);
3262         udelay(100);
3263 
3264         reg = FDI_RX_CTL(pipe);
3265         temp = I915_READ(reg);
3266         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3267 
3268         /* Wait for the clocks to turn off. */
3269         POSTING_READ(reg);
3270         udelay(100);
3271 }
3272 
3273 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3274 {
3275         struct drm_device *dev = crtc->dev;
3276         struct drm_i915_private *dev_priv = dev->dev_private;
3277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3278         int pipe = intel_crtc->pipe;
3279         u32 reg, temp;
3280 
3281         /* disable CPU FDI tx and PCH FDI rx */
3282         reg = FDI_TX_CTL(pipe);
3283         temp = I915_READ(reg);
3284         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3285         POSTING_READ(reg);
3286 
3287         reg = FDI_RX_CTL(pipe);
3288         temp = I915_READ(reg);
3289         temp &= ~(0x7 << 16);
3290         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3291         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3292 
3293         POSTING_READ(reg);
3294         udelay(100);
3295 
3296         /* Ironlake workaround, disable clock pointer after downing FDI */
3297         if (HAS_PCH_IBX(dev))
3298                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3299 
3300         /* still set train pattern 1 */
3301         reg = FDI_TX_CTL(pipe);
3302         temp = I915_READ(reg);
3303         temp &= ~FDI_LINK_TRAIN_NONE;
3304         temp |= FDI_LINK_TRAIN_PATTERN_1;
3305         I915_WRITE(reg, temp);
3306 
3307         reg = FDI_RX_CTL(pipe);
3308         temp = I915_READ(reg);
3309         if (HAS_PCH_CPT(dev)) {
3310                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3311                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3312         } else {
3313                 temp &= ~FDI_LINK_TRAIN_NONE;
3314                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3315         }
3316         /* BPC in FDI rx is consistent with that in PIPECONF */
3317         temp &= ~(0x07 << 16);
3318         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3319         I915_WRITE(reg, temp);
3320 
3321         POSTING_READ(reg);
3322         udelay(100);
3323 }
3324 
3325 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3326 {
3327         struct intel_crtc *crtc;
3328 
3329         /* Note that we don't need to be called with mode_config.lock here
3330          * as our list of CRTC objects is static for the lifetime of the
3331          * device and so cannot disappear as we iterate. Similarly, we can
3332          * happily treat the predicates as racy, atomic checks as userspace
3333          * cannot claim and pin a new fb without at least acquring the
3334          * struct_mutex and so serialising with us.
3335          */
3336         for_each_intel_crtc(dev, crtc) {
3337                 if (atomic_read(&crtc->unpin_work_count) == 0)
3338                         continue;
3339 
3340                 if (crtc->unpin_work)
3341                         intel_wait_for_vblank(dev, crtc->pipe);
3342 
3343                 return true;
3344         }
3345 
3346         return false;
3347 }
3348 
3349 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353 
3354         if (crtc->primary->fb == NULL)
3355                 return;
3356 
3357         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3358 
3359         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3360                                    !intel_crtc_has_pending_flip(crtc),
3361                                    60*HZ) == 0);
3362 
3363         mutex_lock(&dev->struct_mutex);
3364         intel_finish_fb(crtc->primary->fb);
3365         mutex_unlock(&dev->struct_mutex);
3366 }
3367 
3368 /* Program iCLKIP clock to the desired frequency */
3369 static void lpt_program_iclkip(struct drm_crtc *crtc)
3370 {
3371         struct drm_device *dev = crtc->dev;
3372         struct drm_i915_private *dev_priv = dev->dev_private;
3373         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3374         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3375         u32 temp;
3376 
3377         mutex_lock(&dev_priv->dpio_lock);
3378 
3379         /* It is necessary to ungate the pixclk gate prior to programming
3380          * the divisors, and gate it back when it is done.
3381          */
3382         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3383 
3384         /* Disable SSCCTL */
3385         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3386                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3387                                 SBI_SSCCTL_DISABLE,
3388                         SBI_ICLK);
3389 
3390         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3391         if (clock == 20000) {
3392                 auxdiv = 1;
3393                 divsel = 0x41;
3394                 phaseinc = 0x20;
3395         } else {
3396                 /* The iCLK virtual clock root frequency is in MHz,
3397                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3398                  * divisors, it is necessary to divide one by another, so we
3399                  * convert the virtual clock precision to KHz here for higher
3400                  * precision.
3401                  */
3402                 u32 iclk_virtual_root_freq = 172800 * 1000;
3403                 u32 iclk_pi_range = 64;
3404                 u32 desired_divisor, msb_divisor_value, pi_value;
3405 
3406                 desired_divisor = (iclk_virtual_root_freq / clock);
3407                 msb_divisor_value = desired_divisor / iclk_pi_range;
3408                 pi_value = desired_divisor % iclk_pi_range;
3409 
3410                 auxdiv = 0;
3411                 divsel = msb_divisor_value - 2;
3412                 phaseinc = pi_value;
3413         }
3414 
3415         /* This should not happen with any sane values */
3416         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3417                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3418         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3419                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3420 
3421         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3422                         clock,
3423                         auxdiv,
3424                         divsel,
3425                         phasedir,
3426                         phaseinc);
3427 
3428         /* Program SSCDIVINTPHASE6 */
3429         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3430         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3431         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3432         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3433         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3434         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3435         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3436         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3437 
3438         /* Program SSCAUXDIV */
3439         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3440         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3441         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3442         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3443 
3444         /* Enable modulator and associated divider */
3445         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3446         temp &= ~SBI_SSCCTL_DISABLE;
3447         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3448 
3449         /* Wait for initialization time */
3450         udelay(24);
3451 
3452         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3453 
3454         mutex_unlock(&dev_priv->dpio_lock);
3455 }
3456 
3457 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3458                                                 enum pipe pch_transcoder)
3459 {
3460         struct drm_device *dev = crtc->base.dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3463 
3464         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3465                    I915_READ(HTOTAL(cpu_transcoder)));
3466         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3467                    I915_READ(HBLANK(cpu_transcoder)));
3468         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3469                    I915_READ(HSYNC(cpu_transcoder)));
3470 
3471         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3472                    I915_READ(VTOTAL(cpu_transcoder)));
3473         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3474                    I915_READ(VBLANK(cpu_transcoder)));
3475         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3476                    I915_READ(VSYNC(cpu_transcoder)));
3477         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3478                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3479 }
3480 
3481 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3482 {
3483         struct drm_i915_private *dev_priv = dev->dev_private;
3484         uint32_t temp;
3485 
3486         temp = I915_READ(SOUTH_CHICKEN1);
3487         if (temp & FDI_BC_BIFURCATION_SELECT)
3488                 return;
3489 
3490         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3491         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3492 
3493         temp |= FDI_BC_BIFURCATION_SELECT;
3494         DRM_DEBUG_KMS("enabling fdi C rx\n");
3495         I915_WRITE(SOUTH_CHICKEN1, temp);
3496         POSTING_READ(SOUTH_CHICKEN1);
3497 }
3498 
3499 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3500 {
3501         struct drm_device *dev = intel_crtc->base.dev;
3502         struct drm_i915_private *dev_priv = dev->dev_private;
3503 
3504         switch (intel_crtc->pipe) {
3505         case PIPE_A:
3506                 break;
3507         case PIPE_B:
3508                 if (intel_crtc->config.fdi_lanes > 2)
3509                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3510                 else
3511                         cpt_enable_fdi_bc_bifurcation(dev);
3512 
3513                 break;
3514         case PIPE_C:
3515                 cpt_enable_fdi_bc_bifurcation(dev);
3516 
3517                 break;
3518         default:
3519                 BUG();
3520         }
3521 }
3522 
3523 /*
3524  * Enable PCH resources required for PCH ports:
3525  *   - PCH PLLs
3526  *   - FDI training & RX/TX
3527  *   - update transcoder timings
3528  *   - DP transcoding bits
3529  *   - transcoder
3530  */
3531 static void ironlake_pch_enable(struct drm_crtc *crtc)
3532 {
3533         struct drm_device *dev = crtc->dev;
3534         struct drm_i915_private *dev_priv = dev->dev_private;
3535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3536         int pipe = intel_crtc->pipe;
3537         u32 reg, temp;
3538 
3539         assert_pch_transcoder_disabled(dev_priv, pipe);
3540 
3541         if (IS_IVYBRIDGE(dev))
3542                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3543 
3544         /* Write the TU size bits before fdi link training, so that error
3545          * detection works. */
3546         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3547                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3548 
3549         /* For PCH output, training FDI link */
3550         dev_priv->display.fdi_link_train(crtc);
3551 
3552         /* We need to program the right clock selection before writing the pixel
3553          * mutliplier into the DPLL. */
3554         if (HAS_PCH_CPT(dev)) {
3555                 u32 sel;
3556 
3557                 temp = I915_READ(PCH_DPLL_SEL);
3558                 temp |= TRANS_DPLL_ENABLE(pipe);
3559                 sel = TRANS_DPLLB_SEL(pipe);
3560                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3561                         temp |= sel;
3562                 else
3563                         temp &= ~sel;
3564                 I915_WRITE(PCH_DPLL_SEL, temp);
3565         }
3566 
3567         /* XXX: pch pll's can be enabled any time before we enable the PCH
3568          * transcoder, and we actually should do this to not upset any PCH
3569          * transcoder that already use the clock when we share it.
3570          *
3571          * Note that enable_shared_dpll tries to do the right thing, but
3572          * get_shared_dpll unconditionally resets the pll - we need that to have
3573          * the right LVDS enable sequence. */
3574         intel_enable_shared_dpll(intel_crtc);
3575 
3576         /* set transcoder timing, panel must allow it */
3577         assert_panel_unlocked(dev_priv, pipe);
3578         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3579 
3580         intel_fdi_normal_train(crtc);
3581 
3582         /* For PCH DP, enable TRANS_DP_CTL */
3583         if (HAS_PCH_CPT(dev) &&
3584             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3585              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3586                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3587                 reg = TRANS_DP_CTL(pipe);
3588                 temp = I915_READ(reg);
3589                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3590                           TRANS_DP_SYNC_MASK |
3591                           TRANS_DP_BPC_MASK);
3592                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3593                          TRANS_DP_ENH_FRAMING);
3594                 temp |= bpc << 9; /* same format but at 11:9 */
3595 
3596                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3597                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3598                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3599                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3600 
3601                 switch (intel_trans_dp_port_sel(crtc)) {
3602                 case PCH_DP_B:
3603                         temp |= TRANS_DP_PORT_SEL_B;
3604                         break;
3605                 case PCH_DP_C:
3606                         temp |= TRANS_DP_PORT_SEL_C;
3607                         break;
3608                 case PCH_DP_D:
3609                         temp |= TRANS_DP_PORT_SEL_D;
3610                         break;
3611                 default:
3612                         BUG();
3613                 }
3614 
3615                 I915_WRITE(reg, temp);
3616         }
3617 
3618         ironlake_enable_pch_transcoder(dev_priv, pipe);
3619 }
3620 
3621 static void lpt_pch_enable(struct drm_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3627 
3628         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3629 
3630         lpt_program_iclkip(crtc);
3631 
3632         /* Set transcoder timing. */
3633         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3634 
3635         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3636 }
3637 
3638 void intel_put_shared_dpll(struct intel_crtc *crtc)
3639 {
3640         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3641 
3642         if (pll == NULL)
3643                 return;
3644 
3645         if (pll->refcount == 0) {
3646                 WARN(1, "bad %s refcount\n", pll->name);
3647                 return;
3648         }
3649 
3650         if (--pll->refcount == 0) {
3651                 WARN_ON(pll->on);
3652                 WARN_ON(pll->active);
3653         }
3654 
3655         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3656 }
3657 
3658 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3659 {
3660         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3661         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3662         enum intel_dpll_id i;
3663 
3664         if (pll) {
3665                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3666                               crtc->base.base.id, pll->name);
3667                 intel_put_shared_dpll(crtc);
3668         }
3669 
3670         if (HAS_PCH_IBX(dev_priv->dev)) {
3671                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3672                 i = (enum intel_dpll_id) crtc->pipe;
3673                 pll = &dev_priv->shared_dplls[i];
3674 
3675                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3676                               crtc->base.base.id, pll->name);
3677 
3678                 WARN_ON(pll->refcount);
3679 
3680                 goto found;
3681         }
3682 
3683         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3684                 pll = &dev_priv->shared_dplls[i];
3685 
3686                 /* Only want to check enabled timings first */
3687                 if (pll->refcount == 0)
3688                         continue;
3689 
3690                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3691                            sizeof(pll->hw_state)) == 0) {
3692                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3693                                       crtc->base.base.id,
3694                                       pll->name, pll->refcount, pll->active);
3695 
3696                         goto found;
3697                 }
3698         }
3699 
3700         /* Ok no matching timings, maybe there's a free one? */
3701         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3702                 pll = &dev_priv->shared_dplls[i];
3703                 if (pll->refcount == 0) {
3704                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3705                                       crtc->base.base.id, pll->name);
3706                         goto found;
3707                 }
3708         }
3709 
3710         return NULL;
3711 
3712 found:
3713         if (pll->refcount == 0)
3714                 pll->hw_state = crtc->config.dpll_hw_state;
3715 
3716         crtc->config.shared_dpll = i;
3717         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3718                          pipe_name(crtc->pipe));
3719 
3720         pll->refcount++;
3721 
3722         return pll;
3723 }
3724 
3725 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3726 {
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728         int dslreg = PIPEDSL(pipe);
3729         u32 temp;
3730 
3731         temp = I915_READ(dslreg);
3732         udelay(500);
3733         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3734                 if (wait_for(I915_READ(dslreg) != temp, 5))
3735                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3736         }
3737 }
3738 
3739 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3740 {
3741         struct drm_device *dev = crtc->base.dev;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         int pipe = crtc->pipe;
3744 
3745         if (crtc->config.pch_pfit.enabled) {
3746                 /* Force use of hard-coded filter coefficients
3747                  * as some pre-programmed values are broken,
3748                  * e.g. x201.
3749                  */
3750                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3751                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3752                                                  PF_PIPE_SEL_IVB(pipe));
3753                 else
3754                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3755                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3756                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3757         }
3758 }
3759 
3760 static void intel_enable_planes(struct drm_crtc *crtc)
3761 {
3762         struct drm_device *dev = crtc->dev;
3763         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3764         struct drm_plane *plane;
3765         struct intel_plane *intel_plane;
3766 
3767         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3768                 intel_plane = to_intel_plane(plane);
3769                 if (intel_plane->pipe == pipe)
3770                         intel_plane_restore(&intel_plane->base);
3771         }
3772 }
3773 
3774 static void intel_disable_planes(struct drm_crtc *crtc)
3775 {
3776         struct drm_device *dev = crtc->dev;
3777         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3778         struct drm_plane *plane;
3779         struct intel_plane *intel_plane;
3780 
3781         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3782                 intel_plane = to_intel_plane(plane);
3783                 if (intel_plane->pipe == pipe)
3784                         intel_plane_disable(&intel_plane->base);
3785         }
3786 }
3787 
3788 void hsw_enable_ips(struct intel_crtc *crtc)
3789 {
3790         struct drm_device *dev = crtc->base.dev;
3791         struct drm_i915_private *dev_priv = dev->dev_private;
3792 
3793         if (!crtc->config.ips_enabled)
3794                 return;
3795 
3796         /* We can only enable IPS after we enable a plane and wait for a vblank */
3797         intel_wait_for_vblank(dev, crtc->pipe);
3798 
3799         assert_plane_enabled(dev_priv, crtc->plane);
3800         if (IS_BROADWELL(dev)) {
3801                 mutex_lock(&dev_priv->rps.hw_lock);
3802                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3803                 mutex_unlock(&dev_priv->rps.hw_lock);
3804                 /* Quoting Art Runyan: "its not safe to expect any particular
3805                  * value in IPS_CTL bit 31 after enabling IPS through the
3806                  * mailbox." Moreover, the mailbox may return a bogus state,
3807                  * so we need to just enable it and continue on.
3808                  */
3809         } else {
3810                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3811                 /* The bit only becomes 1 in the next vblank, so this wait here
3812                  * is essentially intel_wait_for_vblank. If we don't have this
3813                  * and don't wait for vblanks until the end of crtc_enable, then
3814                  * the HW state readout code will complain that the expected
3815                  * IPS_CTL value is not the one we read. */
3816                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3817                         DRM_ERROR("Timed out waiting for IPS enable\n");
3818         }
3819 }
3820 
3821 void hsw_disable_ips(struct intel_crtc *crtc)
3822 {
3823         struct drm_device *dev = crtc->base.dev;
3824         struct drm_i915_private *dev_priv = dev->dev_private;
3825 
3826         if (!crtc->config.ips_enabled)
3827                 return;
3828 
3829         assert_plane_enabled(dev_priv, crtc->plane);
3830         if (IS_BROADWELL(dev)) {
3831                 mutex_lock(&dev_priv->rps.hw_lock);
3832                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3833                 mutex_unlock(&dev_priv->rps.hw_lock);
3834                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3835                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3836                         DRM_ERROR("Timed out waiting for IPS disable\n");
3837         } else {
3838                 I915_WRITE(IPS_CTL, 0);
3839                 POSTING_READ(IPS_CTL);
3840         }
3841 
3842         /* We need to wait for a vblank before we can disable the plane. */
3843         intel_wait_for_vblank(dev, crtc->pipe);
3844 }
3845 
3846 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3847 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3848 {
3849         struct drm_device *dev = crtc->dev;
3850         struct drm_i915_private *dev_priv = dev->dev_private;
3851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3852         enum pipe pipe = intel_crtc->pipe;
3853         int palreg = PALETTE(pipe);
3854         int i;
3855         bool reenable_ips = false;
3856 
3857         /* The clocks have to be on to load the palette. */
3858         if (!crtc->enabled || !intel_crtc->active)
3859                 return;
3860 
3861         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3862                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3863                         assert_dsi_pll_enabled(dev_priv);
3864                 else
3865                         assert_pll_enabled(dev_priv, pipe);
3866         }
3867 
3868         /* use legacy palette for Ironlake */
3869         if (!HAS_GMCH_DISPLAY(dev))
3870                 palreg = LGC_PALETTE(pipe);
3871 
3872         /* Workaround : Do not read or write the pipe palette/gamma data while
3873          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3874          */
3875         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3876             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3877              GAMMA_MODE_MODE_SPLIT)) {
3878                 hsw_disable_ips(intel_crtc);
3879                 reenable_ips = true;
3880         }
3881 
3882         for (i = 0; i < 256; i++) {
3883                 I915_WRITE(palreg + 4 * i,
3884                            (intel_crtc->lut_r[i] << 16) |
3885                            (intel_crtc->lut_g[i] << 8) |
3886                            intel_crtc->lut_b[i]);
3887         }
3888 
3889         if (reenable_ips)
3890                 hsw_enable_ips(intel_crtc);
3891 }
3892 
3893 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3894 {
3895         if (!enable && intel_crtc->overlay) {
3896                 struct drm_device *dev = intel_crtc->base.dev;
3897                 struct drm_i915_private *dev_priv = dev->dev_private;
3898 
3899                 mutex_lock(&dev->struct_mutex);
3900                 dev_priv->mm.interruptible = false;
3901                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3902                 dev_priv->mm.interruptible = true;
3903                 mutex_unlock(&dev->struct_mutex);
3904         }
3905 
3906         /* Let userspace switch the overlay on again. In most cases userspace
3907          * has to recompute where to put it anyway.
3908          */
3909 }
3910 
3911 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3912 {
3913         struct drm_device *dev = crtc->dev;
3914         struct drm_i915_private *dev_priv = dev->dev_private;
3915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916         int pipe = intel_crtc->pipe;
3917         int plane = intel_crtc->plane;
3918 
3919         drm_vblank_on(dev, pipe);
3920 
3921         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3922         intel_enable_planes(crtc);
3923         intel_crtc_update_cursor(crtc, true);
3924         intel_crtc_dpms_overlay(intel_crtc, true);
3925 
3926         hsw_enable_ips(intel_crtc);
3927 
3928         mutex_lock(&dev->struct_mutex);
3929         intel_update_fbc(dev);
3930         mutex_unlock(&dev->struct_mutex);
3931 
3932         /*
3933          * FIXME: Once we grow proper nuclear flip support out of this we need
3934          * to compute the mask of flip planes precisely. For the time being
3935          * consider this a flip from a NULL plane.
3936          */
3937         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3938 }
3939 
3940 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3941 {
3942         struct drm_device *dev = crtc->dev;
3943         struct drm_i915_private *dev_priv = dev->dev_private;
3944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3945         int pipe = intel_crtc->pipe;
3946         int plane = intel_crtc->plane;
3947 
3948         intel_crtc_wait_for_pending_flips(crtc);
3949 
3950         if (dev_priv->fbc.plane == plane)
3951                 intel_disable_fbc(dev);
3952 
3953         hsw_disable_ips(intel_crtc);
3954 
3955         intel_crtc_dpms_overlay(intel_crtc, false);
3956         intel_crtc_update_cursor(crtc, false);
3957         intel_disable_planes(crtc);
3958         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3959 
3960         /*
3961          * FIXME: Once we grow proper nuclear flip support out of this we need
3962          * to compute the mask of flip planes precisely. For the time being
3963          * consider this a flip to a NULL plane.
3964          */
3965         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3966 
3967         drm_vblank_off(dev, pipe);
3968 }
3969 
3970 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3971 {
3972         struct drm_device *dev = crtc->dev;
3973         struct drm_i915_private *dev_priv = dev->dev_private;
3974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975         struct intel_encoder *encoder;
3976         int pipe = intel_crtc->pipe;
3977         enum plane plane = intel_crtc->plane;
3978 
3979         WARN_ON(!crtc->enabled);
3980 
3981         if (intel_crtc->active)
3982                 return;
3983 
3984         if (intel_crtc->config.has_pch_encoder)
3985                 intel_prepare_shared_dpll(intel_crtc);
3986 
3987         if (intel_crtc->config.has_dp_encoder)
3988                 intel_dp_set_m_n(intel_crtc);
3989 
3990         intel_set_pipe_timings(intel_crtc);
3991 
3992         if (intel_crtc->config.has_pch_encoder) {
3993                 intel_cpu_transcoder_set_m_n(intel_crtc,
3994                                              &intel_crtc->config.fdi_m_n);
3995         }
3996 
3997         ironlake_set_pipeconf(crtc);
3998 
3999         /* Set up the display plane register */
4000         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4001         POSTING_READ(DSPCNTR(plane));
4002 
4003         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4004                                                crtc->x, crtc->y);
4005 
4006         intel_crtc->active = true;
4007 
4008         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4009         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4010 
4011         for_each_encoder_on_crtc(dev, crtc, encoder)
4012                 if (encoder->pre_enable)
4013                         encoder->pre_enable(encoder);
4014 
4015         if (intel_crtc->config.has_pch_encoder) {
4016                 /* Note: FDI PLL enabling _must_ be done before we enable the
4017                  * cpu pipes, hence this is separate from all the other fdi/pch
4018                  * enabling. */
4019                 ironlake_fdi_pll_enable(intel_crtc);
4020         } else {
4021                 assert_fdi_tx_disabled(dev_priv, pipe);
4022                 assert_fdi_rx_disabled(dev_priv, pipe);
4023         }
4024 
4025         ironlake_pfit_enable(intel_crtc);
4026 
4027         /*
4028          * On ILK+ LUT must be loaded before the pipe is running but with
4029          * clocks enabled
4030          */
4031         intel_crtc_load_lut(crtc);
4032 
4033         intel_update_watermarks(crtc);
4034         intel_enable_pipe(intel_crtc);
4035 
4036         if (intel_crtc->config.has_pch_encoder)
4037                 ironlake_pch_enable(crtc);
4038 
4039         for_each_encoder_on_crtc(dev, crtc, encoder)
4040                 encoder->enable(encoder);
4041 
4042         if (HAS_PCH_CPT(dev))
4043                 cpt_verify_modeset(dev, intel_crtc->pipe);
4044 
4045         intel_crtc_enable_planes(crtc);
4046 }
4047 
4048 /* IPS only exists on ULT machines and is tied to pipe A. */
4049 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4050 {
4051         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4052 }
4053 
4054 /*
4055  * This implements the workaround described in the "notes" section of the mode
4056  * set sequence documentation. When going from no pipes or single pipe to
4057  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4058  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4059  */
4060 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4061 {
4062         struct drm_device *dev = crtc->base.dev;
4063         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4064 
4065         /* We want to get the other_active_crtc only if there's only 1 other
4066          * active crtc. */
4067         for_each_intel_crtc(dev, crtc_it) {
4068                 if (!crtc_it->active || crtc_it == crtc)
4069                         continue;
4070 
4071                 if (other_active_crtc)
4072                         return;
4073 
4074                 other_active_crtc = crtc_it;
4075         }
4076         if (!other_active_crtc)
4077                 return;
4078 
4079         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4080         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4081 }
4082 
4083 static void haswell_crtc_enable(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088         struct intel_encoder *encoder;
4089         int pipe = intel_crtc->pipe;
4090         enum plane plane = intel_crtc->plane;
4091 
4092         WARN_ON(!crtc->enabled);
4093 
4094         if (intel_crtc->active)
4095                 return;
4096 
4097         if (intel_crtc_to_shared_dpll(intel_crtc))
4098                 intel_enable_shared_dpll(intel_crtc);
4099 
4100         if (intel_crtc->config.has_dp_encoder)
4101                 intel_dp_set_m_n(intel_crtc);
4102 
4103         intel_set_pipe_timings(intel_crtc);
4104 
4105         if (intel_crtc->config.has_pch_encoder) {
4106                 intel_cpu_transcoder_set_m_n(intel_crtc,
4107                                              &intel_crtc->config.fdi_m_n);
4108         }
4109 
4110         haswell_set_pipeconf(crtc);
4111 
4112         intel_set_pipe_csc(crtc);
4113 
4114         /* Set up the display plane register */
4115         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4116         POSTING_READ(DSPCNTR(plane));
4117 
4118         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4119                                                crtc->x, crtc->y);
4120 
4121         intel_crtc->active = true;
4122 
4123         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4124         for_each_encoder_on_crtc(dev, crtc, encoder)
4125                 if (encoder->pre_enable)
4126                         encoder->pre_enable(encoder);
4127 
4128         if (intel_crtc->config.has_pch_encoder) {
4129                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4130                 dev_priv->display.fdi_link_train(crtc);
4131         }
4132 
4133         intel_ddi_enable_pipe_clock(intel_crtc);
4134 
4135         ironlake_pfit_enable(intel_crtc);
4136 
4137         /*
4138          * On ILK+ LUT must be loaded before the pipe is running but with
4139          * clocks enabled
4140          */
4141         intel_crtc_load_lut(crtc);
4142 
4143         intel_ddi_set_pipe_settings(crtc);
4144         intel_ddi_enable_transcoder_func(crtc);
4145 
4146         intel_update_watermarks(crtc);
4147         intel_enable_pipe(intel_crtc);
4148 
4149         if (intel_crtc->config.has_pch_encoder)
4150                 lpt_pch_enable(crtc);
4151 
4152         if (intel_crtc->config.dp_encoder_is_mst)
4153                 intel_ddi_set_vc_payload_alloc(crtc, true);
4154 
4155         for_each_encoder_on_crtc(dev, crtc, encoder) {
4156                 encoder->enable(encoder);
4157                 intel_opregion_notify_encoder(encoder, true);
4158         }
4159 
4160         /* If we change the relative order between pipe/planes enabling, we need
4161          * to change the workaround. */
4162         haswell_mode_set_planes_workaround(intel_crtc);
4163         intel_crtc_enable_planes(crtc);
4164 }
4165 
4166 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4167 {
4168         struct drm_device *dev = crtc->base.dev;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         int pipe = crtc->pipe;
4171 
4172         /* To avoid upsetting the power well on haswell only disable the pfit if
4173          * it's in use. The hw state code will make sure we get this right. */
4174         if (crtc->config.pch_pfit.enabled) {
4175                 I915_WRITE(PF_CTL(pipe), 0);
4176                 I915_WRITE(PF_WIN_POS(pipe), 0);
4177                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4178         }
4179 }
4180 
4181 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4182 {
4183         struct drm_device *dev = crtc->dev;
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186         struct intel_encoder *encoder;
4187         int pipe = intel_crtc->pipe;
4188         u32 reg, temp;
4189 
4190         if (!intel_crtc->active)
4191                 return;
4192 
4193         intel_crtc_disable_planes(crtc);
4194 
4195         for_each_encoder_on_crtc(dev, crtc, encoder)
4196                 encoder->disable(encoder);
4197 
4198         if (intel_crtc->config.has_pch_encoder)
4199                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4200 
4201         intel_disable_pipe(dev_priv, pipe);
4202         ironlake_pfit_disable(intel_crtc);
4203 
4204         for_each_encoder_on_crtc(dev, crtc, encoder)
4205                 if (encoder->post_disable)
4206                         encoder->post_disable(encoder);
4207 
4208         if (intel_crtc->config.has_pch_encoder) {
4209                 ironlake_fdi_disable(crtc);
4210 
4211                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4212                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4213 
4214                 if (HAS_PCH_CPT(dev)) {
4215                         /* disable TRANS_DP_CTL */
4216                         reg = TRANS_DP_CTL(pipe);
4217                         temp = I915_READ(reg);
4218                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4219                                   TRANS_DP_PORT_SEL_MASK);
4220                         temp |= TRANS_DP_PORT_SEL_NONE;
4221                         I915_WRITE(reg, temp);
4222 
4223                         /* disable DPLL_SEL */
4224                         temp = I915_READ(PCH_DPLL_SEL);
4225                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4226                         I915_WRITE(PCH_DPLL_SEL, temp);
4227                 }
4228 
4229                 /* disable PCH DPLL */
4230                 intel_disable_shared_dpll(intel_crtc);
4231 
4232                 ironlake_fdi_pll_disable(intel_crtc);
4233         }
4234 
4235         intel_crtc->active = false;
4236         intel_update_watermarks(crtc);
4237 
4238         mutex_lock(&dev->struct_mutex);
4239         intel_update_fbc(dev);
4240         mutex_unlock(&dev->struct_mutex);
4241 }
4242 
4243 static void haswell_crtc_disable(struct drm_crtc *crtc)
4244 {
4245         struct drm_device *dev = crtc->dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248         struct intel_encoder *encoder;
4249         int pipe = intel_crtc->pipe;
4250         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4251 
4252         if (!intel_crtc->active)
4253                 return;
4254 
4255         intel_crtc_disable_planes(crtc);
4256 
4257         for_each_encoder_on_crtc(dev, crtc, encoder) {
4258                 intel_opregion_notify_encoder(encoder, false);
4259                 encoder->disable(encoder);
4260         }
4261 
4262         if (intel_crtc->config.has_pch_encoder)
4263                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4264         intel_disable_pipe(dev_priv, pipe);
4265 
4266         if (intel_crtc->config.dp_encoder_is_mst)
4267                 intel_ddi_set_vc_payload_alloc(crtc, false);
4268 
4269         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4270 
4271         ironlake_pfit_disable(intel_crtc);
4272 
4273         intel_ddi_disable_pipe_clock(intel_crtc);
4274 
4275         if (intel_crtc->config.has_pch_encoder) {
4276                 lpt_disable_pch_transcoder(dev_priv);
4277                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4278                 intel_ddi_fdi_disable(crtc);
4279         }
4280 
4281         for_each_encoder_on_crtc(dev, crtc, encoder)
4282                 if (encoder->post_disable)
4283                         encoder->post_disable(encoder);
4284 
4285         intel_crtc->active = false;
4286         intel_update_watermarks(crtc);
4287 
4288         mutex_lock(&dev->struct_mutex);
4289         intel_update_fbc(dev);
4290         mutex_unlock(&dev->struct_mutex);
4291 
4292         if (intel_crtc_to_shared_dpll(intel_crtc))
4293                 intel_disable_shared_dpll(intel_crtc);
4294 }
4295 
4296 static void ironlake_crtc_off(struct drm_crtc *crtc)
4297 {
4298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299         intel_put_shared_dpll(intel_crtc);
4300 }
4301 
4302 
4303 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4304 {
4305         struct drm_device *dev = crtc->base.dev;
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307         struct intel_crtc_config *pipe_config = &crtc->config;
4308 
4309         if (!crtc->config.gmch_pfit.control)
4310                 return;
4311 
4312         /*
4313          * The panel fitter should only be adjusted whilst the pipe is disabled,
4314          * according to register description and PRM.
4315          */
4316         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4317         assert_pipe_disabled(dev_priv, crtc->pipe);
4318 
4319         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4320         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4321 
4322         /* Border color in case we don't scale up to the full screen. Black by
4323          * default, change to something else for debugging. */
4324         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4325 }
4326 
4327 static enum intel_display_power_domain port_to_power_domain(enum port port)
4328 {
4329         switch (port) {
4330         case PORT_A:
4331                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4332         case PORT_B:
4333                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4334         case PORT_C:
4335                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4336         case PORT_D:
4337                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4338         default:
4339                 WARN_ON_ONCE(1);
4340                 return POWER_DOMAIN_PORT_OTHER;
4341         }
4342 }
4343 
4344 #define for_each_power_domain(domain, mask)                             \
4345         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4346                 if ((1 << (domain)) & (mask))
4347 
4348 enum intel_display_power_domain
4349 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4350 {
4351         struct drm_device *dev = intel_encoder->base.dev;
4352         struct intel_digital_port *intel_dig_port;
4353 
4354         switch (intel_encoder->type) {
4355         case INTEL_OUTPUT_UNKNOWN:
4356                 /* Only DDI platforms should ever use this output type */
4357                 WARN_ON_ONCE(!HAS_DDI(dev));
4358         case INTEL_OUTPUT_DISPLAYPORT:
4359         case INTEL_OUTPUT_HDMI:
4360         case INTEL_OUTPUT_EDP:
4361                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4362                 return port_to_power_domain(intel_dig_port->port);
4363         case INTEL_OUTPUT_DP_MST:
4364                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4365                 return port_to_power_domain(intel_dig_port->port);
4366         case INTEL_OUTPUT_ANALOG:
4367                 return POWER_DOMAIN_PORT_CRT;
4368         case INTEL_OUTPUT_DSI:
4369                 return POWER_DOMAIN_PORT_DSI;
4370         default:
4371                 return POWER_DOMAIN_PORT_OTHER;
4372         }
4373 }
4374 
4375 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4376 {
4377         struct drm_device *dev = crtc->dev;
4378         struct intel_encoder *intel_encoder;
4379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4380         enum pipe pipe = intel_crtc->pipe;
4381         unsigned long mask;
4382         enum transcoder transcoder;
4383 
4384         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4385 
4386         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4387         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4388         if (intel_crtc->config.pch_pfit.enabled ||
4389             intel_crtc->config.pch_pfit.force_thru)
4390                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4391 
4392         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4393                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4394 
4395         return mask;
4396 }
4397 
4398 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4399                                   bool enable)
4400 {
4401         if (dev_priv->power_domains.init_power_on == enable)
4402                 return;
4403 
4404         if (enable)
4405                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4406         else
4407                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4408 
4409         dev_priv->power_domains.init_power_on = enable;
4410 }
4411 
4412 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4413 {
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4416         struct intel_crtc *crtc;
4417 
4418         /*
4419          * First get all needed power domains, then put all unneeded, to avoid
4420          * any unnecessary toggling of the power wells.
4421          */
4422         for_each_intel_crtc(dev, crtc) {
4423                 enum intel_display_power_domain domain;
4424 
4425                 if (!crtc->base.enabled)
4426                         continue;
4427 
4428                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4429 
4430                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4431                         intel_display_power_get(dev_priv, domain);
4432         }
4433 
4434         for_each_intel_crtc(dev, crtc) {
4435                 enum intel_display_power_domain domain;
4436 
4437                 for_each_power_domain(domain, crtc->enabled_power_domains)
4438                         intel_display_power_put(dev_priv, domain);
4439 
4440                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4441         }
4442 
4443         intel_display_set_init_power(dev_priv, false);
4444 }
4445 
4446 /* returns HPLL frequency in kHz */
4447 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4448 {
4449         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4450 
4451         /* Obtain SKU information */
4452         mutex_lock(&dev_priv->dpio_lock);
4453         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4454                 CCK_FUSE_HPLL_FREQ_MASK;
4455         mutex_unlock(&dev_priv->dpio_lock);
4456 
4457         return vco_freq[hpll_freq] * 1000;
4458 }
4459 
4460 static void vlv_update_cdclk(struct drm_device *dev)
4461 {
4462         struct drm_i915_private *dev_priv = dev->dev_private;
4463 
4464         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4465         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4466                          dev_priv->vlv_cdclk_freq);
4467 
4468         /*
4469          * Program the gmbus_freq based on the cdclk frequency.
4470          * BSpec erroneously claims we should aim for 4MHz, but
4471          * in fact 1MHz is the correct frequency.
4472          */
4473         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4474 }
4475 
4476 /* Adjust CDclk dividers to allow high res or save power if possible */
4477 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4478 {
4479         struct drm_i915_private *dev_priv = dev->dev_private;
4480         u32 val, cmd;
4481 
4482         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4483 
4484         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4485                 cmd = 2;
4486         else if (cdclk == 266667)
4487                 cmd = 1;
4488         else
4489                 cmd = 0;
4490 
4491         mutex_lock(&dev_priv->rps.hw_lock);
4492         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4493         val &= ~DSPFREQGUAR_MASK;
4494         val |= (cmd << DSPFREQGUAR_SHIFT);
4495         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4496         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4497                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4498                      50)) {
4499                 DRM_ERROR("timed out waiting for CDclk change\n");
4500         }
4501         mutex_unlock(&dev_priv->rps.hw_lock);
4502 
4503         if (cdclk == 400000) {
4504                 u32 divider, vco;
4505 
4506                 vco = valleyview_get_vco(dev_priv);
4507                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4508 
4509                 mutex_lock(&dev_priv->dpio_lock);
4510                 /* adjust cdclk divider */
4511                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4512                 val &= ~DISPLAY_FREQUENCY_VALUES;
4513                 val |= divider;
4514                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4515 
4516                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4517                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4518                              50))
4519                         DRM_ERROR("timed out waiting for CDclk change\n");
4520                 mutex_unlock(&dev_priv->dpio_lock);
4521         }
4522 
4523         mutex_lock(&dev_priv->dpio_lock);
4524         /* adjust self-refresh exit latency value */
4525         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4526         val &= ~0x7f;
4527 
4528         /*
4529          * For high bandwidth configs, we set a higher latency in the bunit
4530          * so that the core display fetch happens in time to avoid underruns.
4531          */
4532         if (cdclk == 400000)
4533                 val |= 4500 / 250; /* 4.5 usec */
4534         else
4535                 val |= 3000 / 250; /* 3.0 usec */
4536         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4537         mutex_unlock(&dev_priv->dpio_lock);
4538 
4539         vlv_update_cdclk(dev);
4540 }
4541 
4542 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4543                                  int max_pixclk)
4544 {
4545         int vco = valleyview_get_vco(dev_priv);
4546         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4547 
4548         /*
4549          * Really only a few cases to deal with, as only 4 CDclks are supported:
4550          *   200MHz
4551          *   267MHz
4552          *   320/333MHz (depends on HPLL freq)
4553          *   400MHz
4554          * So we check to see whether we're above 90% of the lower bin and
4555          * adjust if needed.
4556          *
4557          * We seem to get an unstable or solid color picture at 200MHz.
4558          * Not sure what's wrong. For now use 200MHz only when all pipes
4559          * are off.
4560          */
4561         if (max_pixclk > freq_320*9/10)
4562                 return 400000;
4563         else if (max_pixclk > 266667*9/10)
4564                 return freq_320;
4565         else if (max_pixclk > 0)
4566                 return 266667;
4567         else
4568                 return 200000;
4569 }
4570 
4571 /* compute the max pixel clock for new configuration */
4572 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4573 {
4574         struct drm_device *dev = dev_priv->dev;
4575         struct intel_crtc *intel_crtc;
4576         int max_pixclk = 0;
4577 
4578         for_each_intel_crtc(dev, intel_crtc) {
4579                 if (intel_crtc->new_enabled)
4580                         max_pixclk = max(max_pixclk,
4581                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4582         }
4583 
4584         return max_pixclk;
4585 }
4586 
4587 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4588                                             unsigned *prepare_pipes)
4589 {
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         struct intel_crtc *intel_crtc;
4592         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4593 
4594         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4595             dev_priv->vlv_cdclk_freq)
4596                 return;
4597 
4598         /* disable/enable all currently active pipes while we change cdclk */
4599         for_each_intel_crtc(dev, intel_crtc)
4600                 if (intel_crtc->base.enabled)
4601                         *prepare_pipes |= (1 << intel_crtc->pipe);
4602 }
4603 
4604 static void valleyview_modeset_global_resources(struct drm_device *dev)
4605 {
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4608         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4609 
4610         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4611                 valleyview_set_cdclk(dev, req_cdclk);
4612         modeset_update_crtc_power_domains(dev);
4613 }
4614 
4615 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4616 {
4617         struct drm_device *dev = crtc->dev;
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4620         struct intel_encoder *encoder;
4621         int pipe = intel_crtc->pipe;
4622         int plane = intel_crtc->plane;
4623         bool is_dsi;
4624         u32 dspcntr;
4625 
4626         WARN_ON(!crtc->enabled);
4627 
4628         if (intel_crtc->active)
4629                 return;
4630 
4631         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4632 
4633         if (!is_dsi && !IS_CHERRYVIEW(dev))
4634                 vlv_prepare_pll(intel_crtc);
4635 
4636         /* Set up the display plane register */
4637         dspcntr = DISPPLANE_GAMMA_ENABLE;
4638 
4639         if (intel_crtc->config.has_dp_encoder)
4640                 intel_dp_set_m_n(intel_crtc);
4641 
4642         intel_set_pipe_timings(intel_crtc);
4643 
4644         /* pipesrc and dspsize control the size that is scaled from,
4645          * which should always be the user's requested size.
4646          */
4647         I915_WRITE(DSPSIZE(plane),
4648                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4649                    (intel_crtc->config.pipe_src_w - 1));
4650         I915_WRITE(DSPPOS(plane), 0);
4651 
4652         i9xx_set_pipeconf(intel_crtc);
4653 
4654         I915_WRITE(DSPCNTR(plane), dspcntr);
4655         POSTING_READ(DSPCNTR(plane));
4656 
4657         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4658                                                crtc->x, crtc->y);
4659 
4660         intel_crtc->active = true;
4661 
4662         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4663 
4664         for_each_encoder_on_crtc(dev, crtc, encoder)
4665                 if (encoder->pre_pll_enable)
4666                         encoder->pre_pll_enable(encoder);
4667 
4668         if (!is_dsi) {
4669                 if (IS_CHERRYVIEW(dev))
4670                         chv_enable_pll(intel_crtc);
4671                 else
4672                         vlv_enable_pll(intel_crtc);
4673         }
4674 
4675         for_each_encoder_on_crtc(dev, crtc, encoder)
4676                 if (encoder->pre_enable)
4677                         encoder->pre_enable(encoder);
4678 
4679         i9xx_pfit_enable(intel_crtc);
4680 
4681         intel_crtc_load_lut(crtc);
4682 
4683         intel_update_watermarks(crtc);
4684         intel_enable_pipe(intel_crtc);
4685 
4686         for_each_encoder_on_crtc(dev, crtc, encoder)
4687                 encoder->enable(encoder);
4688 
4689         intel_crtc_enable_planes(crtc);
4690 
4691         /* Underruns don't raise interrupts, so check manually. */
4692         i9xx_check_fifo_underruns(dev);
4693 }
4694 
4695 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4696 {
4697         struct drm_device *dev = crtc->base.dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699 
4700         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4701         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4702 }
4703 
4704 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         struct intel_encoder *encoder;
4710         int pipe = intel_crtc->pipe;
4711         int plane = intel_crtc->plane;
4712         u32 dspcntr;
4713 
4714         WARN_ON(!crtc->enabled);
4715 
4716         if (intel_crtc->active)
4717                 return;
4718 
4719         i9xx_set_pll_dividers(intel_crtc);
4720 
4721         /* Set up the display plane register */
4722         dspcntr = DISPPLANE_GAMMA_ENABLE;
4723 
4724         if (pipe == 0)
4725                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4726         else
4727                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4728 
4729         if (intel_crtc->config.has_dp_encoder)
4730                 intel_dp_set_m_n(intel_crtc);
4731 
4732         intel_set_pipe_timings(intel_crtc);
4733 
4734         /* pipesrc and dspsize control the size that is scaled from,
4735          * which should always be the user's requested size.
4736          */
4737         I915_WRITE(DSPSIZE(plane),
4738                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4739                    (intel_crtc->config.pipe_src_w - 1));
4740         I915_WRITE(DSPPOS(plane), 0);
4741 
4742         i9xx_set_pipeconf(intel_crtc);
4743 
4744         I915_WRITE(DSPCNTR(plane), dspcntr);
4745         POSTING_READ(DSPCNTR(plane));
4746 
4747         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4748                                                crtc->x, crtc->y);
4749 
4750         intel_crtc->active = true;
4751 
4752         if (!IS_GEN2(dev))
4753                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4754 
4755         for_each_encoder_on_crtc(dev, crtc, encoder)
4756                 if (encoder->pre_enable)
4757                         encoder->pre_enable(encoder);
4758 
4759         i9xx_enable_pll(intel_crtc);
4760 
4761         i9xx_pfit_enable(intel_crtc);
4762 
4763         intel_crtc_load_lut(crtc);
4764 
4765         intel_update_watermarks(crtc);
4766         intel_enable_pipe(intel_crtc);
4767 
4768         for_each_encoder_on_crtc(dev, crtc, encoder)
4769                 encoder->enable(encoder);
4770 
4771         intel_crtc_enable_planes(crtc);
4772 
4773         /*
4774          * Gen2 reports pipe underruns whenever all planes are disabled.
4775          * So don't enable underrun reporting before at least some planes
4776          * are enabled.
4777          * FIXME: Need to fix the logic to work when we turn off all planes
4778          * but leave the pipe running.
4779          */
4780         if (IS_GEN2(dev))
4781                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4782 
4783         /* Underruns don't raise interrupts, so check manually. */
4784         i9xx_check_fifo_underruns(dev);
4785 }
4786 
4787 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4788 {
4789         struct drm_device *dev = crtc->base.dev;
4790         struct drm_i915_private *dev_priv = dev->dev_private;
4791 
4792         if (!crtc->config.gmch_pfit.control)
4793                 return;
4794 
4795         assert_pipe_disabled(dev_priv, crtc->pipe);
4796 
4797         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4798                          I915_READ(PFIT_CONTROL));
4799         I915_WRITE(PFIT_CONTROL, 0);
4800 }
4801 
4802 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4803 {
4804         struct drm_device *dev = crtc->dev;
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4807         struct intel_encoder *encoder;
4808         int pipe = intel_crtc->pipe;
4809 
4810         if (!intel_crtc->active)
4811                 return;
4812 
4813         /*
4814          * Gen2 reports pipe underruns whenever all planes are disabled.
4815          * So diasble underrun reporting before all the planes get disabled.
4816          * FIXME: Need to fix the logic to work when we turn off all planes
4817          * but leave the pipe running.
4818          */
4819         if (IS_GEN2(dev))
4820                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4821 
4822         /*
4823          * Vblank time updates from the shadow to live plane control register
4824          * are blocked if the memory self-refresh mode is active at that
4825          * moment. So to make sure the plane gets truly disabled, disable
4826          * first the self-refresh mode. The self-refresh enable bit in turn
4827          * will be checked/applied by the HW only at the next frame start
4828          * event which is after the vblank start event, so we need to have a
4829          * wait-for-vblank between disabling the plane and the pipe.
4830          */
4831         intel_set_memory_cxsr(dev_priv, false);
4832         intel_crtc_disable_planes(crtc);
4833 
4834         for_each_encoder_on_crtc(dev, crtc, encoder)
4835                 encoder->disable(encoder);
4836 
4837         /*
4838          * On gen2 planes are double buffered but the pipe isn't, so we must
4839          * wait for planes to fully turn off before disabling the pipe.
4840          * We also need to wait on all gmch platforms because of the
4841          * self-refresh mode constraint explained above.
4842          */
4843         intel_wait_for_vblank(dev, pipe);
4844 
4845         intel_disable_pipe(dev_priv, pipe);
4846 
4847         i9xx_pfit_disable(intel_crtc);
4848 
4849         for_each_encoder_on_crtc(dev, crtc, encoder)
4850                 if (encoder->post_disable)
4851                         encoder->post_disable(encoder);
4852 
4853         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4854                 if (IS_CHERRYVIEW(dev))
4855                         chv_disable_pll(dev_priv, pipe);
4856                 else if (IS_VALLEYVIEW(dev))
4857                         vlv_disable_pll(dev_priv, pipe);
4858                 else
4859                         i9xx_disable_pll(dev_priv, pipe);
4860         }
4861 
4862         if (!IS_GEN2(dev))
4863                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4864 
4865         intel_crtc->active = false;
4866         intel_update_watermarks(crtc);
4867 
4868         mutex_lock(&dev->struct_mutex);
4869         intel_update_fbc(dev);
4870         mutex_unlock(&dev->struct_mutex);
4871 }
4872 
4873 static void i9xx_crtc_off(struct drm_crtc *crtc)
4874 {
4875 }
4876 
4877 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4878                                     bool enabled)
4879 {
4880         struct drm_device *dev = crtc->dev;
4881         struct drm_i915_master_private *master_priv;
4882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883         int pipe = intel_crtc->pipe;
4884 
4885         if (!dev->primary->master)
4886                 return;
4887 
4888         master_priv = dev->primary->master->driver_priv;
4889         if (!master_priv->sarea_priv)
4890                 return;
4891 
4892         switch (pipe) {
4893         case 0:
4894                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4895                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4896                 break;
4897         case 1:
4898                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4899                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4900                 break;
4901         default:
4902                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4903                 break;
4904         }
4905 }
4906 
4907 /* Master function to enable/disable CRTC and corresponding power wells */
4908 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4909 {
4910         struct drm_device *dev = crtc->dev;
4911         struct drm_i915_private *dev_priv = dev->dev_private;
4912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4913         enum intel_display_power_domain domain;
4914         unsigned long domains;
4915 
4916         if (enable) {
4917                 if (!intel_crtc->active) {
4918                         domains = get_crtc_power_domains(crtc);
4919                         for_each_power_domain(domain, domains)
4920                                 intel_display_power_get(dev_priv, domain);
4921                         intel_crtc->enabled_power_domains = domains;
4922 
4923                         dev_priv->display.crtc_enable(crtc);
4924                 }
4925         } else {
4926                 if (intel_crtc->active) {
4927                         dev_priv->display.crtc_disable(crtc);
4928 
4929                         domains = intel_crtc->enabled_power_domains;
4930                         for_each_power_domain(domain, domains)
4931                                 intel_display_power_put(dev_priv, domain);
4932                         intel_crtc->enabled_power_domains = 0;
4933                 }
4934         }
4935 }
4936 
4937 /**
4938  * Sets the power management mode of the pipe and plane.
4939  */
4940 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4941 {
4942         struct drm_device *dev = crtc->dev;
4943         struct intel_encoder *intel_encoder;
4944         bool enable = false;
4945 
4946         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4947                 enable |= intel_encoder->connectors_active;
4948 
4949         intel_crtc_control(crtc, enable);
4950 
4951         intel_crtc_update_sarea(crtc, enable);
4952 }
4953 
4954 static void intel_crtc_disable(struct drm_crtc *crtc)
4955 {
4956         struct drm_device *dev = crtc->dev;
4957         struct drm_connector *connector;
4958         struct drm_i915_private *dev_priv = dev->dev_private;
4959         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4960         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4961 
4962         /* crtc should still be enabled when we disable it. */
4963         WARN_ON(!crtc->enabled);
4964 
4965         dev_priv->display.crtc_disable(crtc);
4966         intel_crtc_update_sarea(crtc, false);
4967         dev_priv->display.off(crtc);
4968 
4969         if (crtc->primary->fb) {
4970                 mutex_lock(&dev->struct_mutex);
4971                 intel_unpin_fb_obj(old_obj);
4972                 i915_gem_track_fb(old_obj, NULL,
4973                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
4974                 mutex_unlock(&dev->struct_mutex);
4975                 crtc->primary->fb = NULL;
4976         }
4977 
4978         /* Update computed state. */
4979         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4980                 if (!connector->encoder || !connector->encoder->crtc)
4981                         continue;
4982 
4983                 if (connector->encoder->crtc != crtc)
4984                         continue;
4985 
4986                 connector->dpms = DRM_MODE_DPMS_OFF;
4987                 to_intel_encoder(connector->encoder)->connectors_active = false;
4988         }
4989 }
4990 
4991 void intel_encoder_destroy(struct drm_encoder *encoder)
4992 {
4993         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4994 
4995         drm_encoder_cleanup(encoder);
4996         kfree(intel_encoder);
4997 }
4998 
4999 /* Simple dpms helper for encoders with just one connector, no cloning and only
5000  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5001  * state of the entire output pipe. */
5002 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5003 {
5004         if (mode == DRM_MODE_DPMS_ON) {
5005                 encoder->connectors_active = true;
5006 
5007                 intel_crtc_update_dpms(encoder->base.crtc);
5008         } else {
5009                 encoder->connectors_active = false;
5010 
5011                 intel_crtc_update_dpms(encoder->base.crtc);
5012         }
5013 }
5014 
5015 /* Cross check the actual hw state with our own modeset state tracking (and it's
5016  * internal consistency). */
5017 static void intel_connector_check_state(struct intel_connector *connector)
5018 {
5019         if (connector->get_hw_state(connector)) {
5020                 struct intel_encoder *encoder = connector->encoder;
5021                 struct drm_crtc *crtc;
5022                 bool encoder_enabled;
5023                 enum pipe pipe;
5024 
5025                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5026                               connector->base.base.id,
5027                               connector->base.name);
5028 
5029                 /* there is no real hw state for MST connectors */
5030                 if (connector->mst_port)
5031                         return;
5032 
5033                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5034                      "wrong connector dpms state\n");
5035                 WARN(connector->base.encoder != &encoder->base,
5036                      "active connector not linked to encoder\n");
5037 
5038                 if (encoder) {
5039                         WARN(!encoder->connectors_active,
5040                              "encoder->connectors_active not set\n");
5041 
5042                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5043                         WARN(!encoder_enabled, "encoder not enabled\n");
5044                         if (WARN_ON(!encoder->base.crtc))
5045                                 return;
5046 
5047                         crtc = encoder->base.crtc;
5048 
5049                         WARN(!crtc->enabled, "crtc not enabled\n");
5050                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5051                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5052                              "encoder active on the wrong pipe\n");
5053                 }
5054         }
5055 }
5056 
5057 /* Even simpler default implementation, if there's really no special case to
5058  * consider. */
5059 void intel_connector_dpms(struct drm_connector *connector, int mode)
5060 {
5061         /* All the simple cases only support two dpms states. */
5062         if (mode != DRM_MODE_DPMS_ON)
5063                 mode = DRM_MODE_DPMS_OFF;
5064 
5065         if (mode == connector->dpms)
5066                 return;
5067 
5068         connector->dpms = mode;
5069 
5070         /* Only need to change hw state when actually enabled */
5071         if (connector->encoder)
5072                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5073 
5074         intel_modeset_check_state(connector->dev);
5075 }
5076 
5077 /* Simple connector->get_hw_state implementation for encoders that support only
5078  * one connector and no cloning and hence the encoder state determines the state
5079  * of the connector. */
5080 bool intel_connector_get_hw_state(struct intel_connector *connector)
5081 {
5082         enum pipe pipe = 0;
5083         struct intel_encoder *encoder = connector->encoder;
5084 
5085         return encoder->get_hw_state(encoder, &pipe);
5086 }
5087 
5088 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5089                                      struct intel_crtc_config *pipe_config)
5090 {
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092         struct intel_crtc *pipe_B_crtc =
5093                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5094 
5095         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5096                       pipe_name(pipe), pipe_config->fdi_lanes);
5097         if (pipe_config->fdi_lanes > 4) {
5098                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5099                               pipe_name(pipe), pipe_config->fdi_lanes);
5100                 return false;
5101         }
5102 
5103         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5104                 if (pipe_config->fdi_lanes > 2) {
5105                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5106                                       pipe_config->fdi_lanes);
5107                         return false;
5108                 } else {
5109                         return true;
5110                 }
5111         }
5112 
5113         if (INTEL_INFO(dev)->num_pipes == 2)
5114                 return true;
5115 
5116         /* Ivybridge 3 pipe is really complicated */
5117         switch (pipe) {
5118         case PIPE_A:
5119                 return true;
5120         case PIPE_B:
5121                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5122                     pipe_config->fdi_lanes > 2) {
5123                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5124                                       pipe_name(pipe), pipe_config->fdi_lanes);
5125                         return false;
5126                 }
5127                 return true;
5128         case PIPE_C:
5129                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5130                     pipe_B_crtc->config.fdi_lanes <= 2) {
5131                         if (pipe_config->fdi_lanes > 2) {
5132                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5133                                               pipe_name(pipe), pipe_config->fdi_lanes);
5134                                 return false;
5135                         }
5136                 } else {
5137                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5138                         return false;
5139                 }
5140                 return true;
5141         default:
5142                 BUG();
5143         }
5144 }
5145 
5146 #define RETRY 1
5147 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5148                                        struct intel_crtc_config *pipe_config)
5149 {
5150         struct drm_device *dev = intel_crtc->base.dev;
5151         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5152         int lane, link_bw, fdi_dotclock;
5153         bool setup_ok, needs_recompute = false;
5154 
5155 retry:
5156         /* FDI is a binary signal running at ~2.7GHz, encoding
5157          * each output octet as 10 bits. The actual frequency
5158          * is stored as a divider into a 100MHz clock, and the
5159          * mode pixel clock is stored in units of 1KHz.
5160          * Hence the bw of each lane in terms of the mode signal
5161          * is:
5162          */
5163         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5164 
5165         fdi_dotclock = adjusted_mode->crtc_clock;
5166 
5167         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5168                                            pipe_config->pipe_bpp);
5169 
5170         pipe_config->fdi_lanes = lane;
5171 
5172         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5173                                link_bw, &pipe_config->fdi_m_n);
5174 
5175         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5176                                             intel_crtc->pipe, pipe_config);
5177         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5178                 pipe_config->pipe_bpp -= 2*3;
5179                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5180                               pipe_config->pipe_bpp);
5181                 needs_recompute = true;
5182                 pipe_config->bw_constrained = true;
5183 
5184                 goto retry;
5185         }
5186 
5187         if (needs_recompute)
5188                 return RETRY;
5189 
5190         return setup_ok ? 0 : -EINVAL;
5191 }
5192 
5193 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5194                                    struct intel_crtc_config *pipe_config)
5195 {
5196         pipe_config->ips_enabled = i915.enable_ips &&
5197                                    hsw_crtc_supports_ips(crtc) &&
5198                                    pipe_config->pipe_bpp <= 24;
5199 }
5200 
5201 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5202                                      struct intel_crtc_config *pipe_config)
5203 {
5204         struct drm_device *dev = crtc->base.dev;
5205         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5206 
5207         /* FIXME should check pixel clock limits on all platforms */
5208         if (INTEL_INFO(dev)->gen < 4) {
5209                 struct drm_i915_private *dev_priv = dev->dev_private;
5210                 int clock_limit =
5211                         dev_priv->display.get_display_clock_speed(dev);
5212 
5213                 /*
5214                  * Enable pixel doubling when the dot clock
5215                  * is > 90% of the (display) core speed.
5216                  *
5217                  * GDG double wide on either pipe,
5218                  * otherwise pipe A only.
5219                  */
5220                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5221                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5222                         clock_limit *= 2;
5223                         pipe_config->double_wide = true;
5224                 }
5225 
5226                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5227                         return -EINVAL;
5228         }
5229 
5230         /*
5231          * Pipe horizontal size must be even in:
5232          * - DVO ganged mode
5233          * - LVDS dual channel mode
5234          * - Double wide pipe
5235          */
5236         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5237              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5238                 pipe_config->pipe_src_w &= ~1;
5239 
5240         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5241          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5242          */
5243         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5244                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5245                 return -EINVAL;
5246 
5247         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5248                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5249         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5250                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5251                  * for lvds. */
5252                 pipe_config->pipe_bpp = 8*3;
5253         }
5254 
5255         if (HAS_IPS(dev))
5256                 hsw_compute_ips_config(crtc, pipe_config);
5257 
5258         /*
5259          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5260          * old clock survives for now.
5261          */
5262         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5263                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5264 
5265         if (pipe_config->has_pch_encoder)
5266                 return ironlake_fdi_compute_config(crtc, pipe_config);
5267 
5268         return 0;
5269 }
5270 
5271 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274         int vco = valleyview_get_vco(dev_priv);
5275         u32 val;
5276         int divider;
5277 
5278         mutex_lock(&dev_priv->dpio_lock);
5279         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5280         mutex_unlock(&dev_priv->dpio_lock);
5281 
5282         divider = val & DISPLAY_FREQUENCY_VALUES;
5283 
5284         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5285              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5286              "cdclk change in progress\n");
5287 
5288         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5289 }
5290 
5291 static int i945_get_display_clock_speed(struct drm_device *dev)
5292 {
5293         return 400000;
5294 }
5295 
5296 static int i915_get_display_clock_speed(struct drm_device *dev)
5297 {
5298         return 333000;
5299 }
5300 
5301 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5302 {
5303         return 200000;
5304 }
5305 
5306 static int pnv_get_display_clock_speed(struct drm_device *dev)
5307 {
5308         u16 gcfgc = 0;
5309 
5310         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5311 
5312         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5313         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5314                 return 267000;
5315         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5316                 return 333000;
5317         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5318                 return 444000;
5319         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5320                 return 200000;
5321         default:
5322                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5323         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5324                 return 133000;
5325         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5326                 return 167000;
5327         }
5328 }
5329 
5330 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5331 {
5332         u16 gcfgc = 0;
5333 
5334         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5335 
5336         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5337                 return 133000;
5338         else {
5339                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5340                 case GC_DISPLAY_CLOCK_333_MHZ:
5341                         return 333000;
5342                 default:
5343                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5344                         return 190000;
5345                 }
5346         }
5347 }
5348 
5349 static int i865_get_display_clock_speed(struct drm_device *dev)
5350 {
5351         return 266000;
5352 }
5353 
5354 static int i855_get_display_clock_speed(struct drm_device *dev)
5355 {
5356         u16 hpllcc = 0;
5357         /* Assume that the hardware is in the high speed state.  This
5358          * should be the default.
5359          */
5360         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5361         case GC_CLOCK_133_200:
5362         case GC_CLOCK_100_200:
5363                 return 200000;
5364         case GC_CLOCK_166_250:
5365                 return 250000;
5366         case GC_CLOCK_100_133:
5367                 return 133000;
5368         }
5369 
5370         /* Shouldn't happen */
5371         return 0;
5372 }
5373 
5374 static int i830_get_display_clock_speed(struct drm_device *dev)
5375 {
5376         return 133000;
5377 }
5378 
5379 static void
5380 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5381 {
5382         while (*num > DATA_LINK_M_N_MASK ||
5383                *den > DATA_LINK_M_N_MASK) {
5384                 *num >>= 1;
5385                 *den >>= 1;
5386         }
5387 }
5388 
5389 static void compute_m_n(unsigned int m, unsigned int n,
5390                         uint32_t *ret_m, uint32_t *ret_n)
5391 {
5392         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5393         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5394         intel_reduce_m_n_ratio(ret_m, ret_n);
5395 }
5396 
5397 void
5398 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5399                        int pixel_clock, int link_clock,
5400                        struct intel_link_m_n *m_n)
5401 {
5402         m_n->tu = 64;
5403 
5404         compute_m_n(bits_per_pixel * pixel_clock,
5405                     link_clock * nlanes * 8,
5406                     &m_n->gmch_m, &m_n->gmch_n);
5407 
5408         compute_m_n(pixel_clock, link_clock,
5409                     &m_n->link_m, &m_n->link_n);
5410 }
5411 
5412 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5413 {
5414         if (i915.panel_use_ssc >= 0)
5415                 return i915.panel_use_ssc != 0;
5416         return dev_priv->vbt.lvds_use_ssc
5417                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5418 }
5419 
5420 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5421 {
5422         struct drm_device *dev = crtc->dev;
5423         struct drm_i915_private *dev_priv = dev->dev_private;
5424         int refclk;
5425 
5426         if (IS_VALLEYVIEW(dev)) {
5427                 refclk = 100000;
5428         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5429             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5430                 refclk = dev_priv->vbt.lvds_ssc_freq;
5431                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5432         } else if (!IS_GEN2(dev)) {
5433                 refclk = 96000;
5434         } else {
5435                 refclk = 48000;
5436         }
5437 
5438         return refclk;
5439 }
5440 
5441 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5442 {
5443         return (1 << dpll->n) << 16 | dpll->m2;
5444 }
5445 
5446 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5447 {
5448         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5449 }
5450 
5451 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5452                                      intel_clock_t *reduced_clock)
5453 {
5454         struct drm_device *dev = crtc->base.dev;
5455         u32 fp, fp2 = 0;
5456 
5457         if (IS_PINEVIEW(dev)) {
5458                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5459                 if (reduced_clock)
5460                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5461         } else {
5462                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5463                 if (reduced_clock)
5464                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5465         }
5466 
5467         crtc->config.dpll_hw_state.fp0 = fp;
5468 
5469         crtc->lowfreq_avail = false;
5470         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5471             reduced_clock && i915.powersave) {
5472                 crtc->config.dpll_hw_state.fp1 = fp2;
5473                 crtc->lowfreq_avail = true;
5474         } else {
5475                 crtc->config.dpll_hw_state.fp1 = fp;
5476         }
5477 }
5478 
5479 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5480                 pipe)
5481 {
5482         u32 reg_val;
5483 
5484         /*
5485          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5486          * and set it to a reasonable value instead.
5487          */
5488         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5489         reg_val &= 0xffffff00;
5490         reg_val |= 0x00000030;
5491         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5492 
5493         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5494         reg_val &= 0x8cffffff;
5495         reg_val = 0x8c000000;
5496         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5497 
5498         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5499         reg_val &= 0xffffff00;
5500         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5501 
5502         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5503         reg_val &= 0x00ffffff;
5504         reg_val |= 0xb0000000;
5505         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5506 }
5507 
5508 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5509                                          struct intel_link_m_n *m_n)
5510 {
5511         struct drm_device *dev = crtc->base.dev;
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513         int pipe = crtc->pipe;
5514 
5515         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5516         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5517         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5518         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5519 }
5520 
5521 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5522                                          struct intel_link_m_n *m_n)
5523 {
5524         struct drm_device *dev = crtc->base.dev;
5525         struct drm_i915_private *dev_priv = dev->dev_private;
5526         int pipe = crtc->pipe;
5527         enum transcoder transcoder = crtc->config.cpu_transcoder;
5528 
5529         if (INTEL_INFO(dev)->gen >= 5) {
5530                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5531                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5532                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5533                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5534         } else {
5535                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5536                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5537                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5538                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5539         }
5540 }
5541 
5542 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5543 {
5544         if (crtc->config.has_pch_encoder)
5545                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5546         else
5547                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5548 }
5549 
5550 static void vlv_update_pll(struct intel_crtc *crtc)
5551 {
5552         u32 dpll, dpll_md;
5553 
5554         /*
5555          * Enable DPIO clock input. We should never disable the reference
5556          * clock for pipe B, since VGA hotplug / manual detection depends
5557          * on it.
5558          */
5559         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5560                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5561         /* We should never disable this, set it here for state tracking */
5562         if (crtc->pipe == PIPE_B)
5563                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5564         dpll |= DPLL_VCO_ENABLE;
5565         crtc->config.dpll_hw_state.dpll = dpll;
5566 
5567         dpll_md = (crtc->config.pixel_multiplier - 1)
5568                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5569         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5570 }
5571 
5572 static void vlv_prepare_pll(struct intel_crtc *crtc)
5573 {
5574         struct drm_device *dev = crtc->base.dev;
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576         int pipe = crtc->pipe;
5577         u32 mdiv;
5578         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5579         u32 coreclk, reg_val;
5580 
5581         mutex_lock(&dev_priv->dpio_lock);
5582 
5583         bestn = crtc->config.dpll.n;
5584         bestm1 = crtc->config.dpll.m1;
5585         bestm2 = crtc->config.dpll.m2;
5586         bestp1 = crtc->config.dpll.p1;
5587         bestp2 = crtc->config.dpll.p2;
5588 
5589         /* See eDP HDMI DPIO driver vbios notes doc */
5590 
5591         /* PLL B needs special handling */
5592         if (pipe == PIPE_B)
5593                 vlv_pllb_recal_opamp(dev_priv, pipe);
5594 
5595         /* Set up Tx target for periodic Rcomp update */
5596         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5597 
5598         /* Disable target IRef on PLL */
5599         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5600         reg_val &= 0x00ffffff;
5601         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5602 
5603         /* Disable fast lock */
5604         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5605 
5606         /* Set idtafcrecal before PLL is enabled */
5607         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5608         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5609         mdiv |= ((bestn << DPIO_N_SHIFT));
5610         mdiv |= (1 << DPIO_K_SHIFT);
5611 
5612         /*
5613          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5614          * but we don't support that).
5615          * Note: don't use the DAC post divider as it seems unstable.
5616          */
5617         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5618         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5619 
5620         mdiv |= DPIO_ENABLE_CALIBRATION;
5621         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5622 
5623         /* Set HBR and RBR LPF coefficients */
5624         if (crtc->config.port_clock == 162000 ||
5625             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5626             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5627                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5628                                  0x009f0003);
5629         else
5630                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5631                                  0x00d0000f);
5632 
5633         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5634             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5635                 /* Use SSC source */
5636                 if (pipe == PIPE_A)
5637                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5638                                          0x0df40000);
5639                 else
5640                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5641                                          0x0df70000);
5642         } else { /* HDMI or VGA */
5643                 /* Use bend source */
5644                 if (pipe == PIPE_A)
5645                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5646                                          0x0df70000);
5647                 else
5648                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5649                                          0x0df40000);
5650         }
5651 
5652         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5653         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5654         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5655             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5656                 coreclk |= 0x01000000;
5657         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5658 
5659         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5660         mutex_unlock(&dev_priv->dpio_lock);
5661 }
5662 
5663 static void chv_update_pll(struct intel_crtc *crtc)
5664 {
5665         struct drm_device *dev = crtc->base.dev;
5666         struct drm_i915_private *dev_priv = dev->dev_private;
5667         int pipe = crtc->pipe;
5668         int dpll_reg = DPLL(crtc->pipe);
5669         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5670         u32 loopfilter, intcoeff;
5671         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5672         int refclk;
5673 
5674         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5675                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5676                 DPLL_VCO_ENABLE;
5677         if (pipe != PIPE_A)
5678                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5679 
5680         crtc->config.dpll_hw_state.dpll_md =
5681                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5682 
5683         bestn = crtc->config.dpll.n;
5684         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5685         bestm1 = crtc->config.dpll.m1;
5686         bestm2 = crtc->config.dpll.m2 >> 22;
5687         bestp1 = crtc->config.dpll.p1;
5688         bestp2 = crtc->config.dpll.p2;
5689 
5690         /*
5691          * Enable Refclk and SSC
5692          */
5693         I915_WRITE(dpll_reg,
5694                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5695 
5696         mutex_lock(&dev_priv->dpio_lock);
5697 
5698         /* p1 and p2 divider */
5699         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5700                         5 << DPIO_CHV_S1_DIV_SHIFT |
5701                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5702                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5703                         1 << DPIO_CHV_K_DIV_SHIFT);
5704 
5705         /* Feedback post-divider - m2 */
5706         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5707 
5708         /* Feedback refclk divider - n and m1 */
5709         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5710                         DPIO_CHV_M1_DIV_BY_2 |
5711                         1 << DPIO_CHV_N_DIV_SHIFT);
5712 
5713         /* M2 fraction division */
5714         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5715 
5716         /* M2 fraction division enable */
5717         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5718                        DPIO_CHV_FRAC_DIV_EN |
5719                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5720 
5721         /* Loop filter */
5722         refclk = i9xx_get_refclk(&crtc->base, 0);
5723         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5724                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5725         if (refclk == 100000)
5726                 intcoeff = 11;
5727         else if (refclk == 38400)
5728                 intcoeff = 10;
5729         else
5730                 intcoeff = 9;
5731         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5732         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5733 
5734         /* AFC Recal */
5735         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5736                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5737                         DPIO_AFC_RECAL);
5738 
5739         mutex_unlock(&dev_priv->dpio_lock);
5740 }
5741 
5742 static void i9xx_update_pll(struct intel_crtc *crtc,
5743                             intel_clock_t *reduced_clock,
5744                             int num_connectors)
5745 {
5746         struct drm_device *dev = crtc->base.dev;
5747         struct drm_i915_private *dev_priv = dev->dev_private;
5748         u32 dpll;
5749         bool is_sdvo;
5750         struct dpll *clock = &crtc->config.dpll;
5751 
5752         i9xx_update_pll_dividers(crtc, reduced_clock);
5753 
5754         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5755                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5756 
5757         dpll = DPLL_VGA_MODE_DIS;
5758 
5759         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5760                 dpll |= DPLLB_MODE_LVDS;
5761         else
5762                 dpll |= DPLLB_MODE_DAC_SERIAL;
5763 
5764         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5765                 dpll |= (crtc->config.pixel_multiplier - 1)
5766                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5767         }
5768 
5769         if (is_sdvo)
5770                 dpll |= DPLL_SDVO_HIGH_SPEED;
5771 
5772         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5773                 dpll |= DPLL_SDVO_HIGH_SPEED;
5774 
5775         /* compute bitmask from p1 value */
5776         if (IS_PINEVIEW(dev))
5777                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5778         else {
5779                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5780                 if (IS_G4X(dev) && reduced_clock)
5781                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5782         }
5783         switch (clock->p2) {
5784         case 5:
5785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5786                 break;
5787         case 7:
5788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5789                 break;
5790         case 10:
5791                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5792                 break;
5793         case 14:
5794                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5795                 break;
5796         }
5797         if (INTEL_INFO(dev)->gen >= 4)
5798                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5799 
5800         if (crtc->config.sdvo_tv_clock)
5801                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5802         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5803                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5804                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5805         else
5806                 dpll |= PLL_REF_INPUT_DREFCLK;
5807 
5808         dpll |= DPLL_VCO_ENABLE;
5809         crtc->config.dpll_hw_state.dpll = dpll;
5810 
5811         if (INTEL_INFO(dev)->gen >= 4) {
5812                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5813                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5814                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5815         }
5816 }
5817 
5818 static void i8xx_update_pll(struct intel_crtc *crtc,
5819                             intel_clock_t *reduced_clock,
5820                             int num_connectors)
5821 {
5822         struct drm_device *dev = crtc->base.dev;
5823         struct drm_i915_private *dev_priv = dev->dev_private;
5824         u32 dpll;
5825         struct dpll *clock = &crtc->config.dpll;
5826 
5827         i9xx_update_pll_dividers(crtc, reduced_clock);
5828 
5829         dpll = DPLL_VGA_MODE_DIS;
5830 
5831         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5832                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5833         } else {
5834                 if (clock->p1 == 2)
5835                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5836                 else
5837                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5838                 if (clock->p2 == 4)
5839                         dpll |= PLL_P2_DIVIDE_BY_4;
5840         }
5841 
5842         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5843                 dpll |= DPLL_DVO_2X_MODE;
5844 
5845         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5846                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5847                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5848         else
5849                 dpll |= PLL_REF_INPUT_DREFCLK;
5850 
5851         dpll |= DPLL_VCO_ENABLE;
5852         crtc->config.dpll_hw_state.dpll = dpll;
5853 }
5854 
5855 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5856 {
5857         struct drm_device *dev = intel_crtc->base.dev;
5858         struct drm_i915_private *dev_priv = dev->dev_private;
5859         enum pipe pipe = intel_crtc->pipe;
5860         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5861         struct drm_display_mode *adjusted_mode =
5862                 &intel_crtc->config.adjusted_mode;
5863         uint32_t crtc_vtotal, crtc_vblank_end;
5864         int vsyncshift = 0;
5865 
5866         /* We need to be careful not to changed the adjusted mode, for otherwise
5867          * the hw state checker will get angry at the mismatch. */
5868         crtc_vtotal = adjusted_mode->crtc_vtotal;
5869         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5870 
5871         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5872                 /* the chip adds 2 halflines automatically */
5873                 crtc_vtotal -= 1;
5874                 crtc_vblank_end -= 1;
5875 
5876                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5877                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5878                 else
5879                         vsyncshift = adjusted_mode->crtc_hsync_start -
5880                                 adjusted_mode->crtc_htotal / 2;
5881                 if (vsyncshift < 0)
5882                         vsyncshift += adjusted_mode->crtc_htotal;
5883         }
5884 
5885         if (INTEL_INFO(dev)->gen > 3)
5886                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5887 
5888         I915_WRITE(HTOTAL(cpu_transcoder),
5889                    (adjusted_mode->crtc_hdisplay - 1) |
5890                    ((adjusted_mode->crtc_htotal - 1) << 16));
5891         I915_WRITE(HBLANK(cpu_transcoder),
5892                    (adjusted_mode->crtc_hblank_start - 1) |
5893                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5894         I915_WRITE(HSYNC(cpu_transcoder),
5895                    (adjusted_mode->crtc_hsync_start - 1) |
5896                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5897 
5898         I915_WRITE(VTOTAL(cpu_transcoder),
5899                    (adjusted_mode->crtc_vdisplay - 1) |
5900                    ((crtc_vtotal - 1) << 16));
5901         I915_WRITE(VBLANK(cpu_transcoder),
5902                    (adjusted_mode->crtc_vblank_start - 1) |
5903                    ((crtc_vblank_end - 1) << 16));
5904         I915_WRITE(VSYNC(cpu_transcoder),
5905                    (adjusted_mode->crtc_vsync_start - 1) |
5906                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5907 
5908         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5909          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5910          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5911          * bits. */
5912         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5913             (pipe == PIPE_B || pipe == PIPE_C))
5914                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5915 
5916         /* pipesrc controls the size that is scaled from, which should
5917          * always be the user's requested size.
5918          */
5919         I915_WRITE(PIPESRC(pipe),
5920                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5921                    (intel_crtc->config.pipe_src_h - 1));
5922 }
5923 
5924 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5925                                    struct intel_crtc_config *pipe_config)
5926 {
5927         struct drm_device *dev = crtc->base.dev;
5928         struct drm_i915_private *dev_priv = dev->dev_private;
5929         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5930         uint32_t tmp;
5931 
5932         tmp = I915_READ(HTOTAL(cpu_transcoder));
5933         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5934         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5935         tmp = I915_READ(HBLANK(cpu_transcoder));
5936         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5937         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5938         tmp = I915_READ(HSYNC(cpu_transcoder));
5939         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5940         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5941 
5942         tmp = I915_READ(VTOTAL(cpu_transcoder));
5943         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5944         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5945         tmp = I915_READ(VBLANK(cpu_transcoder));
5946         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5947         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5948         tmp = I915_READ(VSYNC(cpu_transcoder));
5949         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5950         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5951 
5952         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5953                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5954                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5955                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5956         }
5957 
5958         tmp = I915_READ(PIPESRC(crtc->pipe));
5959         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5960         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5961 
5962         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5963         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5964 }
5965 
5966 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5967                                  struct intel_crtc_config *pipe_config)
5968 {
5969         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5970         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5971         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5972         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5973 
5974         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5975         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5976         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5977         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5978 
5979         mode->flags = pipe_config->adjusted_mode.flags;
5980 
5981         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5982         mode->flags |= pipe_config->adjusted_mode.flags;
5983 }
5984 
5985 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5986 {
5987         struct drm_device *dev = intel_crtc->base.dev;
5988         struct drm_i915_private *dev_priv = dev->dev_private;
5989         uint32_t pipeconf;
5990 
5991         pipeconf = 0;
5992 
5993         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5994             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5995                 pipeconf |= PIPECONF_ENABLE;
5996 
5997         if (intel_crtc->config.double_wide)
5998                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5999 
6000         /* only g4x and later have fancy bpc/dither controls */
6001         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6002                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6003                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6004                         pipeconf |= PIPECONF_DITHER_EN |
6005                                     PIPECONF_DITHER_TYPE_SP;
6006 
6007                 switch (intel_crtc->config.pipe_bpp) {
6008                 case 18:
6009                         pipeconf |= PIPECONF_6BPC;
6010                         break;
6011                 case 24:
6012                         pipeconf |= PIPECONF_8BPC;
6013                         break;
6014                 case 30:
6015                         pipeconf |= PIPECONF_10BPC;
6016                         break;
6017                 default:
6018                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6019                         BUG();
6020                 }
6021         }
6022 
6023         if (HAS_PIPE_CXSR(dev)) {
6024                 if (intel_crtc->lowfreq_avail) {
6025                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6026                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6027                 } else {
6028                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6029                 }
6030         }
6031 
6032         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6033                 if (INTEL_INFO(dev)->gen < 4 ||
6034                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6035                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6036                 else
6037                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6038         } else
6039                 pipeconf |= PIPECONF_PROGRESSIVE;
6040 
6041         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6042                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6043 
6044         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6045         POSTING_READ(PIPECONF(intel_crtc->pipe));
6046 }
6047 
6048 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6049                               int x, int y,
6050                               struct drm_framebuffer *fb)
6051 {
6052         struct drm_device *dev = crtc->dev;
6053         struct drm_i915_private *dev_priv = dev->dev_private;
6054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055         int refclk, num_connectors = 0;
6056         intel_clock_t clock, reduced_clock;
6057         bool ok, has_reduced_clock = false;
6058         bool is_lvds = false, is_dsi = false;
6059         struct intel_encoder *encoder;
6060         const intel_limit_t *limit;
6061 
6062         for_each_encoder_on_crtc(dev, crtc, encoder) {
6063                 switch (encoder->type) {
6064                 case INTEL_OUTPUT_LVDS:
6065                         is_lvds = true;
6066                         break;
6067                 case INTEL_OUTPUT_DSI:
6068                         is_dsi = true;
6069                         break;
6070                 }
6071 
6072                 num_connectors++;
6073         }
6074 
6075         if (is_dsi)
6076                 return 0;
6077 
6078         if (!intel_crtc->config.clock_set) {
6079                 refclk = i9xx_get_refclk(crtc, num_connectors);
6080 
6081                 /*
6082                  * Returns a set of divisors for the desired target clock with
6083                  * the given refclk, or FALSE.  The returned values represent
6084                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6085                  * 2) / p1 / p2.
6086                  */
6087                 limit = intel_limit(crtc, refclk);
6088                 ok = dev_priv->display.find_dpll(limit, crtc,
6089                                                  intel_crtc->config.port_clock,
6090                                                  refclk, NULL, &clock);
6091                 if (!ok) {
6092                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6093                         return -EINVAL;
6094                 }
6095 
6096                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6097                         /*
6098                          * Ensure we match the reduced clock's P to the target
6099                          * clock.  If the clocks don't match, we can't switch
6100                          * the display clock by using the FP0/FP1. In such case
6101                          * we will disable the LVDS downclock feature.
6102                          */
6103                         has_reduced_clock =
6104                                 dev_priv->display.find_dpll(limit, crtc,
6105                                                             dev_priv->lvds_downclock,
6106                                                             refclk, &clock,
6107                                                             &reduced_clock);
6108                 }
6109                 /* Compat-code for transition, will disappear. */
6110                 intel_crtc->config.dpll.n = clock.n;
6111                 intel_crtc->config.dpll.m1 = clock.m1;
6112                 intel_crtc->config.dpll.m2 = clock.m2;
6113                 intel_crtc->config.dpll.p1 = clock.p1;
6114                 intel_crtc->config.dpll.p2 = clock.p2;
6115         }
6116 
6117         if (IS_GEN2(dev)) {
6118                 i8xx_update_pll(intel_crtc,
6119                                 has_reduced_clock ? &reduced_clock : NULL,
6120                                 num_connectors);
6121         } else if (IS_CHERRYVIEW(dev)) {
6122                 chv_update_pll(intel_crtc);
6123         } else if (IS_VALLEYVIEW(dev)) {
6124                 vlv_update_pll(intel_crtc);
6125         } else {
6126                 i9xx_update_pll(intel_crtc,
6127                                 has_reduced_clock ? &reduced_clock : NULL,
6128                                 num_connectors);
6129         }
6130 
6131         return 0;
6132 }
6133 
6134 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6135                                  struct intel_crtc_config *pipe_config)
6136 {
6137         struct drm_device *dev = crtc->base.dev;
6138         struct drm_i915_private *dev_priv = dev->dev_private;
6139         uint32_t tmp;
6140 
6141         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6142                 return;
6143 
6144         tmp = I915_READ(PFIT_CONTROL);
6145         if (!(tmp & PFIT_ENABLE))
6146                 return;
6147 
6148         /* Check whether the pfit is attached to our pipe. */
6149         if (INTEL_INFO(dev)->gen < 4) {
6150                 if (crtc->pipe != PIPE_B)
6151                         return;
6152         } else {
6153                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6154                         return;
6155         }
6156 
6157         pipe_config->gmch_pfit.control = tmp;
6158         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6159         if (INTEL_INFO(dev)->gen < 5)
6160                 pipe_config->gmch_pfit.lvds_border_bits =
6161                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6162 }
6163 
6164 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6165                                struct intel_crtc_config *pipe_config)
6166 {
6167         struct drm_device *dev = crtc->base.dev;
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169         int pipe = pipe_config->cpu_transcoder;
6170         intel_clock_t clock;
6171         u32 mdiv;
6172         int refclk = 100000;
6173 
6174         /* In case of MIPI DPLL will not even be used */
6175         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6176                 return;
6177 
6178         mutex_lock(&dev_priv->dpio_lock);
6179         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6180         mutex_unlock(&dev_priv->dpio_lock);
6181 
6182         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6183         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6184         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6185         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6186         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6187 
6188         vlv_clock(refclk, &clock);
6189 
6190         /* clock.dot is the fast clock */
6191         pipe_config->port_clock = clock.dot / 5;
6192 }
6193 
6194 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6195                                   struct intel_plane_config *plane_config)
6196 {
6197         struct drm_device *dev = crtc->base.dev;
6198         struct drm_i915_private *dev_priv = dev->dev_private;
6199         u32 val, base, offset;
6200         int pipe = crtc->pipe, plane = crtc->plane;
6201         int fourcc, pixel_format;
6202         int aligned_height;
6203 
6204         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6205         if (!crtc->base.primary->fb) {
6206                 DRM_DEBUG_KMS("failed to alloc fb\n");
6207                 return;
6208         }
6209 
6210         val = I915_READ(DSPCNTR(plane));
6211 
6212         if (INTEL_INFO(dev)->gen >= 4)
6213                 if (val & DISPPLANE_TILED)
6214                         plane_config->tiled = true;
6215 
6216         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6217         fourcc = intel_format_to_fourcc(pixel_format);
6218         crtc->base.primary->fb->pixel_format = fourcc;
6219         crtc->base.primary->fb->bits_per_pixel =
6220                 drm_format_plane_cpp(fourcc, 0) * 8;
6221 
6222         if (INTEL_INFO(dev)->gen >= 4) {
6223                 if (plane_config->tiled)
6224                         offset = I915_READ(DSPTILEOFF(plane));
6225                 else
6226                         offset = I915_READ(DSPLINOFF(plane));
6227                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6228         } else {
6229                 base = I915_READ(DSPADDR(plane));
6230         }
6231         plane_config->base = base;
6232 
6233         val = I915_READ(PIPESRC(pipe));
6234         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6235         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6236 
6237         val = I915_READ(DSPSTRIDE(pipe));
6238         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6239 
6240         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6241                                             plane_config->tiled);
6242 
6243         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6244                                         aligned_height);
6245 
6246         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6247                       pipe, plane, crtc->base.primary->fb->width,
6248                       crtc->base.primary->fb->height,
6249                       crtc->base.primary->fb->bits_per_pixel, base,
6250                       crtc->base.primary->fb->pitches[0],
6251                       plane_config->size);
6252 
6253 }
6254 
6255 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6256                                struct intel_crtc_config *pipe_config)
6257 {
6258         struct drm_device *dev = crtc->base.dev;
6259         struct drm_i915_private *dev_priv = dev->dev_private;
6260         int pipe = pipe_config->cpu_transcoder;
6261         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6262         intel_clock_t clock;
6263         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6264         int refclk = 100000;
6265 
6266         mutex_lock(&dev_priv->dpio_lock);
6267         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6268         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6269         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6270         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6271         mutex_unlock(&dev_priv->dpio_lock);
6272 
6273         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6274         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6275         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6276         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6277         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6278 
6279         chv_clock(refclk, &clock);
6280 
6281         /* clock.dot is the fast clock */
6282         pipe_config->port_clock = clock.dot / 5;
6283 }
6284 
6285 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6286                                  struct intel_crtc_config *pipe_config)
6287 {
6288         struct drm_device *dev = crtc->base.dev;
6289         struct drm_i915_private *dev_priv = dev->dev_private;
6290         uint32_t tmp;
6291 
6292         if (!intel_display_power_enabled(dev_priv,
6293                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6294                 return false;
6295 
6296         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6297         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6298 
6299         tmp = I915_READ(PIPECONF(crtc->pipe));
6300         if (!(tmp & PIPECONF_ENABLE))
6301                 return false;
6302 
6303         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6304                 switch (tmp & PIPECONF_BPC_MASK) {
6305                 case PIPECONF_6BPC:
6306                         pipe_config->pipe_bpp = 18;
6307                         break;
6308                 case PIPECONF_8BPC:
6309                         pipe_config->pipe_bpp = 24;
6310                         break;
6311                 case PIPECONF_10BPC:
6312                         pipe_config->pipe_bpp = 30;
6313                         break;
6314                 default:
6315                         break;
6316                 }
6317         }
6318 
6319         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6320                 pipe_config->limited_color_range = true;
6321 
6322         if (INTEL_INFO(dev)->gen < 4)
6323                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6324 
6325         intel_get_pipe_timings(crtc, pipe_config);
6326 
6327         i9xx_get_pfit_config(crtc, pipe_config);
6328 
6329         if (INTEL_INFO(dev)->gen >= 4) {
6330                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6331                 pipe_config->pixel_multiplier =
6332                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6333                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6334                 pipe_config->dpll_hw_state.dpll_md = tmp;
6335         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6336                 tmp = I915_READ(DPLL(crtc->pipe));
6337                 pipe_config->pixel_multiplier =
6338                         ((tmp & SDVO_MULTIPLIER_MASK)
6339                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6340         } else {
6341                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6342                  * port and will be fixed up in the encoder->get_config
6343                  * function. */
6344                 pipe_config->pixel_multiplier = 1;
6345         }
6346         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6347         if (!IS_VALLEYVIEW(dev)) {
6348                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6349                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6350         } else {
6351                 /* Mask out read-only status bits. */
6352                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6353                                                      DPLL_PORTC_READY_MASK |
6354                                                      DPLL_PORTB_READY_MASK);
6355         }
6356 
6357         if (IS_CHERRYVIEW(dev))
6358                 chv_crtc_clock_get(crtc, pipe_config);
6359         else if (IS_VALLEYVIEW(dev))
6360                 vlv_crtc_clock_get(crtc, pipe_config);
6361         else
6362                 i9xx_crtc_clock_get(crtc, pipe_config);
6363 
6364         return true;
6365 }
6366 
6367 static void ironlake_init_pch_refclk(struct drm_device *dev)
6368 {
6369         struct drm_i915_private *dev_priv = dev->dev_private;
6370         struct drm_mode_config *mode_config = &dev->mode_config;
6371         struct intel_encoder *encoder;
6372         u32 val, final;
6373         bool has_lvds = false;
6374         bool has_cpu_edp = false;
6375         bool has_panel = false;
6376         bool has_ck505 = false;
6377         bool can_ssc = false;
6378 
6379         /* We need to take the global config into account */
6380         list_for_each_entry(encoder, &mode_config->encoder_list,
6381                             base.head) {
6382                 switch (encoder->type) {
6383                 case INTEL_OUTPUT_LVDS:
6384                         has_panel = true;
6385                         has_lvds = true;
6386                         break;
6387                 case INTEL_OUTPUT_EDP:
6388                         has_panel = true;
6389                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6390                                 has_cpu_edp = true;
6391                         break;
6392                 }
6393         }
6394 
6395         if (HAS_PCH_IBX(dev)) {
6396                 has_ck505 = dev_priv->vbt.display_clock_mode;