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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_dp_helper.h>
 41 #include <drm/drm_crtc_helper.h>
 42 #include <drm/drm_plane_helper.h>
 43 #include <drm/drm_rect.h>
 44 #include <linux/dma_remapping.h>
 45 
 46 /* Primary plane formats supported by all gen */
 47 #define COMMON_PRIMARY_FORMATS \
 48         DRM_FORMAT_C8, \
 49         DRM_FORMAT_RGB565, \
 50         DRM_FORMAT_XRGB8888, \
 51         DRM_FORMAT_ARGB8888
 52 
 53 /* Primary plane formats for gen <= 3 */
 54 static const uint32_t intel_primary_formats_gen2[] = {
 55         COMMON_PRIMARY_FORMATS,
 56         DRM_FORMAT_XRGB1555,
 57         DRM_FORMAT_ARGB1555,
 58 };
 59 
 60 /* Primary plane formats for gen >= 4 */
 61 static const uint32_t intel_primary_formats_gen4[] = {
 62         COMMON_PRIMARY_FORMATS, \
 63         DRM_FORMAT_XBGR8888,
 64         DRM_FORMAT_ABGR8888,
 65         DRM_FORMAT_XRGB2101010,
 66         DRM_FORMAT_ARGB2101010,
 67         DRM_FORMAT_XBGR2101010,
 68         DRM_FORMAT_ABGR2101010,
 69 };
 70 
 71 /* Cursor formats */
 72 static const uint32_t intel_cursor_formats[] = {
 73         DRM_FORMAT_ARGB8888,
 74 };
 75 
 76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 77 
 78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 79                                 struct intel_crtc_config *pipe_config);
 80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 81                                    struct intel_crtc_config *pipe_config);
 82 
 83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 84                           int x, int y, struct drm_framebuffer *old_fb);
 85 static int intel_framebuffer_init(struct drm_device *dev,
 86                                   struct intel_framebuffer *ifb,
 87                                   struct drm_mode_fb_cmd2 *mode_cmd,
 88                                   struct drm_i915_gem_object *obj);
 89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 92                                          struct intel_link_m_n *m_n,
 93                                          struct intel_link_m_n *m2_n2);
 94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 97 static void vlv_prepare_pll(struct intel_crtc *crtc,
 98                             const struct intel_crtc_config *pipe_config);
 99 static void chv_prepare_pll(struct intel_crtc *crtc,
100                             const struct intel_crtc_config *pipe_config);
101 
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103 {
104         if (!connector->mst_port)
105                 return connector->encoder;
106         else
107                 return &connector->mst_port->mst_encoders[pipe]->base;
108 }
109 
110 typedef struct {
111         int     min, max;
112 } intel_range_t;
113 
114 typedef struct {
115         int     dot_limit;
116         int     p2_slow, p2_fast;
117 } intel_p2_t;
118 
119 typedef struct intel_limit intel_limit_t;
120 struct intel_limit {
121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
122         intel_p2_t          p2;
123 };
124 
125 int
126 intel_pch_rawclk(struct drm_device *dev)
127 {
128         struct drm_i915_private *dev_priv = dev->dev_private;
129 
130         WARN_ON(!HAS_PCH_SPLIT(dev));
131 
132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 }
134 
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
137 {
138         if (IS_GEN5(dev)) {
139                 struct drm_i915_private *dev_priv = dev->dev_private;
140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141         } else
142                 return 27;
143 }
144 
145 static const intel_limit_t intel_limits_i8xx_dac = {
146         .dot = { .min = 25000, .max = 350000 },
147         .vco = { .min = 908000, .max = 1512000 },
148         .n = { .min = 2, .max = 16 },
149         .m = { .min = 96, .max = 140 },
150         .m1 = { .min = 18, .max = 26 },
151         .m2 = { .min = 6, .max = 16 },
152         .p = { .min = 4, .max = 128 },
153         .p1 = { .min = 2, .max = 33 },
154         .p2 = { .dot_limit = 165000,
155                 .p2_slow = 4, .p2_fast = 2 },
156 };
157 
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159         .dot = { .min = 25000, .max = 350000 },
160         .vco = { .min = 908000, .max = 1512000 },
161         .n = { .min = 2, .max = 16 },
162         .m = { .min = 96, .max = 140 },
163         .m1 = { .min = 18, .max = 26 },
164         .m2 = { .min = 6, .max = 16 },
165         .p = { .min = 4, .max = 128 },
166         .p1 = { .min = 2, .max = 33 },
167         .p2 = { .dot_limit = 165000,
168                 .p2_slow = 4, .p2_fast = 4 },
169 };
170 
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172         .dot = { .min = 25000, .max = 350000 },
173         .vco = { .min = 908000, .max = 1512000 },
174         .n = { .min = 2, .max = 16 },
175         .m = { .min = 96, .max = 140 },
176         .m1 = { .min = 18, .max = 26 },
177         .m2 = { .min = 6, .max = 16 },
178         .p = { .min = 4, .max = 128 },
179         .p1 = { .min = 1, .max = 6 },
180         .p2 = { .dot_limit = 165000,
181                 .p2_slow = 14, .p2_fast = 7 },
182 };
183 
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185         .dot = { .min = 20000, .max = 400000 },
186         .vco = { .min = 1400000, .max = 2800000 },
187         .n = { .min = 1, .max = 6 },
188         .m = { .min = 70, .max = 120 },
189         .m1 = { .min = 8, .max = 18 },
190         .m2 = { .min = 3, .max = 7 },
191         .p = { .min = 5, .max = 80 },
192         .p1 = { .min = 1, .max = 8 },
193         .p2 = { .dot_limit = 200000,
194                 .p2_slow = 10, .p2_fast = 5 },
195 };
196 
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198         .dot = { .min = 20000, .max = 400000 },
199         .vco = { .min = 1400000, .max = 2800000 },
200         .n = { .min = 1, .max = 6 },
201         .m = { .min = 70, .max = 120 },
202         .m1 = { .min = 8, .max = 18 },
203         .m2 = { .min = 3, .max = 7 },
204         .p = { .min = 7, .max = 98 },
205         .p1 = { .min = 1, .max = 8 },
206         .p2 = { .dot_limit = 112000,
207                 .p2_slow = 14, .p2_fast = 7 },
208 };
209 
210 
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212         .dot = { .min = 25000, .max = 270000 },
213         .vco = { .min = 1750000, .max = 3500000},
214         .n = { .min = 1, .max = 4 },
215         .m = { .min = 104, .max = 138 },
216         .m1 = { .min = 17, .max = 23 },
217         .m2 = { .min = 5, .max = 11 },
218         .p = { .min = 10, .max = 30 },
219         .p1 = { .min = 1, .max = 3},
220         .p2 = { .dot_limit = 270000,
221                 .p2_slow = 10,
222                 .p2_fast = 10
223         },
224 };
225 
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227         .dot = { .min = 22000, .max = 400000 },
228         .vco = { .min = 1750000, .max = 3500000},
229         .n = { .min = 1, .max = 4 },
230         .m = { .min = 104, .max = 138 },
231         .m1 = { .min = 16, .max = 23 },
232         .m2 = { .min = 5, .max = 11 },
233         .p = { .min = 5, .max = 80 },
234         .p1 = { .min = 1, .max = 8},
235         .p2 = { .dot_limit = 165000,
236                 .p2_slow = 10, .p2_fast = 5 },
237 };
238 
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240         .dot = { .min = 20000, .max = 115000 },
241         .vco = { .min = 1750000, .max = 3500000 },
242         .n = { .min = 1, .max = 3 },
243         .m = { .min = 104, .max = 138 },
244         .m1 = { .min = 17, .max = 23 },
245         .m2 = { .min = 5, .max = 11 },
246         .p = { .min = 28, .max = 112 },
247         .p1 = { .min = 2, .max = 8 },
248         .p2 = { .dot_limit = 0,
249                 .p2_slow = 14, .p2_fast = 14
250         },
251 };
252 
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254         .dot = { .min = 80000, .max = 224000 },
255         .vco = { .min = 1750000, .max = 3500000 },
256         .n = { .min = 1, .max = 3 },
257         .m = { .min = 104, .max = 138 },
258         .m1 = { .min = 17, .max = 23 },
259         .m2 = { .min = 5, .max = 11 },
260         .p = { .min = 14, .max = 42 },
261         .p1 = { .min = 2, .max = 6 },
262         .p2 = { .dot_limit = 0,
263                 .p2_slow = 7, .p2_fast = 7
264         },
265 };
266 
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268         .dot = { .min = 20000, .max = 400000},
269         .vco = { .min = 1700000, .max = 3500000 },
270         /* Pineview's Ncounter is a ring counter */
271         .n = { .min = 3, .max = 6 },
272         .m = { .min = 2, .max = 256 },
273         /* Pineview only has one combined m divider, which we treat as m2. */
274         .m1 = { .min = 0, .max = 0 },
275         .m2 = { .min = 0, .max = 254 },
276         .p = { .min = 5, .max = 80 },
277         .p1 = { .min = 1, .max = 8 },
278         .p2 = { .dot_limit = 200000,
279                 .p2_slow = 10, .p2_fast = 5 },
280 };
281 
282 static const intel_limit_t intel_limits_pineview_lvds = {
283         .dot = { .min = 20000, .max = 400000 },
284         .vco = { .min = 1700000, .max = 3500000 },
285         .n = { .min = 3, .max = 6 },
286         .m = { .min = 2, .max = 256 },
287         .m1 = { .min = 0, .max = 0 },
288         .m2 = { .min = 0, .max = 254 },
289         .p = { .min = 7, .max = 112 },
290         .p1 = { .min = 1, .max = 8 },
291         .p2 = { .dot_limit = 112000,
292                 .p2_slow = 14, .p2_fast = 14 },
293 };
294 
295 /* Ironlake / Sandybridge
296  *
297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
298  * the range value for them is (actual_value - 2).
299  */
300 static const intel_limit_t intel_limits_ironlake_dac = {
301         .dot = { .min = 25000, .max = 350000 },
302         .vco = { .min = 1760000, .max = 3510000 },
303         .n = { .min = 1, .max = 5 },
304         .m = { .min = 79, .max = 127 },
305         .m1 = { .min = 12, .max = 22 },
306         .m2 = { .min = 5, .max = 9 },
307         .p = { .min = 5, .max = 80 },
308         .p1 = { .min = 1, .max = 8 },
309         .p2 = { .dot_limit = 225000,
310                 .p2_slow = 10, .p2_fast = 5 },
311 };
312 
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314         .dot = { .min = 25000, .max = 350000 },
315         .vco = { .min = 1760000, .max = 3510000 },
316         .n = { .min = 1, .max = 3 },
317         .m = { .min = 79, .max = 118 },
318         .m1 = { .min = 12, .max = 22 },
319         .m2 = { .min = 5, .max = 9 },
320         .p = { .min = 28, .max = 112 },
321         .p1 = { .min = 2, .max = 8 },
322         .p2 = { .dot_limit = 225000,
323                 .p2_slow = 14, .p2_fast = 14 },
324 };
325 
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327         .dot = { .min = 25000, .max = 350000 },
328         .vco = { .min = 1760000, .max = 3510000 },
329         .n = { .min = 1, .max = 3 },
330         .m = { .min = 79, .max = 127 },
331         .m1 = { .min = 12, .max = 22 },
332         .m2 = { .min = 5, .max = 9 },
333         .p = { .min = 14, .max = 56 },
334         .p1 = { .min = 2, .max = 8 },
335         .p2 = { .dot_limit = 225000,
336                 .p2_slow = 7, .p2_fast = 7 },
337 };
338 
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341         .dot = { .min = 25000, .max = 350000 },
342         .vco = { .min = 1760000, .max = 3510000 },
343         .n = { .min = 1, .max = 2 },
344         .m = { .min = 79, .max = 126 },
345         .m1 = { .min = 12, .max = 22 },
346         .m2 = { .min = 5, .max = 9 },
347         .p = { .min = 28, .max = 112 },
348         .p1 = { .min = 2, .max = 8 },
349         .p2 = { .dot_limit = 225000,
350                 .p2_slow = 14, .p2_fast = 14 },
351 };
352 
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354         .dot = { .min = 25000, .max = 350000 },
355         .vco = { .min = 1760000, .max = 3510000 },
356         .n = { .min = 1, .max = 3 },
357         .m = { .min = 79, .max = 126 },
358         .m1 = { .min = 12, .max = 22 },
359         .m2 = { .min = 5, .max = 9 },
360         .p = { .min = 14, .max = 42 },
361         .p1 = { .min = 2, .max = 6 },
362         .p2 = { .dot_limit = 225000,
363                 .p2_slow = 7, .p2_fast = 7 },
364 };
365 
366 static const intel_limit_t intel_limits_vlv = {
367          /*
368           * These are the data rate limits (measured in fast clocks)
369           * since those are the strictest limits we have. The fast
370           * clock and actual rate limits are more relaxed, so checking
371           * them would make no difference.
372           */
373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374         .vco = { .min = 4000000, .max = 6000000 },
375         .n = { .min = 1, .max = 7 },
376         .m1 = { .min = 2, .max = 3 },
377         .m2 = { .min = 11, .max = 156 },
378         .p1 = { .min = 2, .max = 3 },
379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 };
381 
382 static const intel_limit_t intel_limits_chv = {
383         /*
384          * These are the data rate limits (measured in fast clocks)
385          * since those are the strictest limits we have.  The fast
386          * clock and actual rate limits are more relaxed, so checking
387          * them would make no difference.
388          */
389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
390         .vco = { .min = 4860000, .max = 6700000 },
391         .n = { .min = 1, .max = 1 },
392         .m1 = { .min = 2, .max = 2 },
393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
394         .p1 = { .min = 2, .max = 4 },
395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 };
397 
398 static void vlv_clock(int refclk, intel_clock_t *clock)
399 {
400         clock->m = clock->m1 * clock->m2;
401         clock->p = clock->p1 * clock->p2;
402         if (WARN_ON(clock->n == 0 || clock->p == 0))
403                 return;
404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
406 }
407 
408 /**
409  * Returns whether any output on the specified pipe is of the specified type
410  */
411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
412 {
413         struct drm_device *dev = crtc->base.dev;
414         struct intel_encoder *encoder;
415 
416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417                 if (encoder->type == type)
418                         return true;
419 
420         return false;
421 }
422 
423 /**
424  * Returns whether any output on the specified pipe will have the specified
425  * type after a staged modeset is complete, i.e., the same as
426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427  * encoder->crtc.
428  */
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430 {
431         struct drm_device *dev = crtc->base.dev;
432         struct intel_encoder *encoder;
433 
434         for_each_intel_encoder(dev, encoder)
435                 if (encoder->new_crtc == crtc && encoder->type == type)
436                         return true;
437 
438         return false;
439 }
440 
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
442                                                 int refclk)
443 {
444         struct drm_device *dev = crtc->base.dev;
445         const intel_limit_t *limit;
446 
447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448                 if (intel_is_dual_link_lvds(dev)) {
449                         if (refclk == 100000)
450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
451                         else
452                                 limit = &intel_limits_ironlake_dual_lvds;
453                 } else {
454                         if (refclk == 100000)
455                                 limit = &intel_limits_ironlake_single_lvds_100m;
456                         else
457                                 limit = &intel_limits_ironlake_single_lvds;
458                 }
459         } else
460                 limit = &intel_limits_ironlake_dac;
461 
462         return limit;
463 }
464 
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
466 {
467         struct drm_device *dev = crtc->base.dev;
468         const intel_limit_t *limit;
469 
470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471                 if (intel_is_dual_link_lvds(dev))
472                         limit = &intel_limits_g4x_dual_channel_lvds;
473                 else
474                         limit = &intel_limits_g4x_single_channel_lvds;
475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477                 limit = &intel_limits_g4x_hdmi;
478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479                 limit = &intel_limits_g4x_sdvo;
480         } else /* The option is for other outputs */
481                 limit = &intel_limits_i9xx_sdvo;
482 
483         return limit;
484 }
485 
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
487 {
488         struct drm_device *dev = crtc->base.dev;
489         const intel_limit_t *limit;
490 
491         if (HAS_PCH_SPLIT(dev))
492                 limit = intel_ironlake_limit(crtc, refclk);
493         else if (IS_G4X(dev)) {
494                 limit = intel_g4x_limit(crtc);
495         } else if (IS_PINEVIEW(dev)) {
496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497                         limit = &intel_limits_pineview_lvds;
498                 else
499                         limit = &intel_limits_pineview_sdvo;
500         } else if (IS_CHERRYVIEW(dev)) {
501                 limit = &intel_limits_chv;
502         } else if (IS_VALLEYVIEW(dev)) {
503                 limit = &intel_limits_vlv;
504         } else if (!IS_GEN2(dev)) {
505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506                         limit = &intel_limits_i9xx_lvds;
507                 else
508                         limit = &intel_limits_i9xx_sdvo;
509         } else {
510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511                         limit = &intel_limits_i8xx_lvds;
512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513                         limit = &intel_limits_i8xx_dvo;
514                 else
515                         limit = &intel_limits_i8xx_dac;
516         }
517         return limit;
518 }
519 
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
522 {
523         clock->m = clock->m2 + 2;
524         clock->p = clock->p1 * clock->p2;
525         if (WARN_ON(clock->n == 0 || clock->p == 0))
526                 return;
527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530 
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532 {
533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534 }
535 
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
537 {
538         clock->m = i9xx_dpll_compute_m(clock);
539         clock->p = clock->p1 * clock->p2;
540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541                 return;
542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
544 }
545 
546 static void chv_clock(int refclk, intel_clock_t *clock)
547 {
548         clock->m = clock->m1 * clock->m2;
549         clock->p = clock->p1 * clock->p2;
550         if (WARN_ON(clock->n == 0 || clock->p == 0))
551                 return;
552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553                         clock->n << 22);
554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 }
556 
557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
558 /**
559  * Returns whether the given set of divisors are valid for a given refclk with
560  * the given connectors.
561  */
562 
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564                                const intel_limit_t *limit,
565                                const intel_clock_t *clock)
566 {
567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
568                 INTELPllInvalid("n out of range\n");
569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
570                 INTELPllInvalid("p1 out of range\n");
571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
572                 INTELPllInvalid("m2 out of range\n");
573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
574                 INTELPllInvalid("m1 out of range\n");
575 
576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577                 if (clock->m1 <= clock->m2)
578                         INTELPllInvalid("m1 <= m2\n");
579 
580         if (!IS_VALLEYVIEW(dev)) {
581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
582                         INTELPllInvalid("p out of range\n");
583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
584                         INTELPllInvalid("m out of range\n");
585         }
586 
587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588                 INTELPllInvalid("vco out of range\n");
589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590          * connector, etc., rather than just a single range.
591          */
592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593                 INTELPllInvalid("dot out of range\n");
594 
595         return true;
596 }
597 
598 static bool
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600                     int target, int refclk, intel_clock_t *match_clock,
601                     intel_clock_t *best_clock)
602 {
603         struct drm_device *dev = crtc->base.dev;
604         intel_clock_t clock;
605         int err = target;
606 
607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
608                 /*
609                  * For LVDS just rely on its current settings for dual-channel.
610                  * We haven't figured out how to reliably set up different
611                  * single/dual channel state, if we even can.
612                  */
613                 if (intel_is_dual_link_lvds(dev))
614                         clock.p2 = limit->p2.p2_fast;
615                 else
616                         clock.p2 = limit->p2.p2_slow;
617         } else {
618                 if (target < limit->p2.dot_limit)
619                         clock.p2 = limit->p2.p2_slow;
620                 else
621                         clock.p2 = limit->p2.p2_fast;
622         }
623 
624         memset(best_clock, 0, sizeof(*best_clock));
625 
626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627              clock.m1++) {
628                 for (clock.m2 = limit->m2.min;
629                      clock.m2 <= limit->m2.max; clock.m2++) {
630                         if (clock.m2 >= clock.m1)
631                                 break;
632                         for (clock.n = limit->n.min;
633                              clock.n <= limit->n.max; clock.n++) {
634                                 for (clock.p1 = limit->p1.min;
635                                         clock.p1 <= limit->p1.max; clock.p1++) {
636                                         int this_err;
637 
638                                         i9xx_clock(refclk, &clock);
639                                         if (!intel_PLL_is_valid(dev, limit,
640                                                                 &clock))
641                                                 continue;
642                                         if (match_clock &&
643                                             clock.p != match_clock->p)
644                                                 continue;
645 
646                                         this_err = abs(clock.dot - target);
647                                         if (this_err < err) {
648                                                 *best_clock = clock;
649                                                 err = this_err;
650                                         }
651                                 }
652                         }
653                 }
654         }
655 
656         return (err != target);
657 }
658 
659 static bool
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661                    int target, int refclk, intel_clock_t *match_clock,
662                    intel_clock_t *best_clock)
663 {
664         struct drm_device *dev = crtc->base.dev;
665         intel_clock_t clock;
666         int err = target;
667 
668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 /*
670                  * For LVDS just rely on its current settings for dual-channel.
671                  * We haven't figured out how to reliably set up different
672                  * single/dual channel state, if we even can.
673                  */
674                 if (intel_is_dual_link_lvds(dev))
675                         clock.p2 = limit->p2.p2_fast;
676                 else
677                         clock.p2 = limit->p2.p2_slow;
678         } else {
679                 if (target < limit->p2.dot_limit)
680                         clock.p2 = limit->p2.p2_slow;
681                 else
682                         clock.p2 = limit->p2.p2_fast;
683         }
684 
685         memset(best_clock, 0, sizeof(*best_clock));
686 
687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688              clock.m1++) {
689                 for (clock.m2 = limit->m2.min;
690                      clock.m2 <= limit->m2.max; clock.m2++) {
691                         for (clock.n = limit->n.min;
692                              clock.n <= limit->n.max; clock.n++) {
693                                 for (clock.p1 = limit->p1.min;
694                                         clock.p1 <= limit->p1.max; clock.p1++) {
695                                         int this_err;
696 
697                                         pineview_clock(refclk, &clock);
698                                         if (!intel_PLL_is_valid(dev, limit,
699                                                                 &clock))
700                                                 continue;
701                                         if (match_clock &&
702                                             clock.p != match_clock->p)
703                                                 continue;
704 
705                                         this_err = abs(clock.dot - target);
706                                         if (this_err < err) {
707                                                 *best_clock = clock;
708                                                 err = this_err;
709                                         }
710                                 }
711                         }
712                 }
713         }
714 
715         return (err != target);
716 }
717 
718 static bool
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720                    int target, int refclk, intel_clock_t *match_clock,
721                    intel_clock_t *best_clock)
722 {
723         struct drm_device *dev = crtc->base.dev;
724         intel_clock_t clock;
725         int max_n;
726         bool found;
727         /* approximately equals target * 0.00585 */
728         int err_most = (target >> 8) + (target >> 9);
729         found = false;
730 
731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732                 if (intel_is_dual_link_lvds(dev))
733                         clock.p2 = limit->p2.p2_fast;
734                 else
735                         clock.p2 = limit->p2.p2_slow;
736         } else {
737                 if (target < limit->p2.dot_limit)
738                         clock.p2 = limit->p2.p2_slow;
739                 else
740                         clock.p2 = limit->p2.p2_fast;
741         }
742 
743         memset(best_clock, 0, sizeof(*best_clock));
744         max_n = limit->n.max;
745         /* based on hardware requirement, prefer smaller n to precision */
746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747                 /* based on hardware requirement, prefere larger m1,m2 */
748                 for (clock.m1 = limit->m1.max;
749                      clock.m1 >= limit->m1.min; clock.m1--) {
750                         for (clock.m2 = limit->m2.max;
751                              clock.m2 >= limit->m2.min; clock.m2--) {
752                                 for (clock.p1 = limit->p1.max;
753                                      clock.p1 >= limit->p1.min; clock.p1--) {
754                                         int this_err;
755 
756                                         i9xx_clock(refclk, &clock);
757                                         if (!intel_PLL_is_valid(dev, limit,
758                                                                 &clock))
759                                                 continue;
760 
761                                         this_err = abs(clock.dot - target);
762                                         if (this_err < err_most) {
763                                                 *best_clock = clock;
764                                                 err_most = this_err;
765                                                 max_n = clock.n;
766                                                 found = true;
767                                         }
768                                 }
769                         }
770                 }
771         }
772         return found;
773 }
774 
775 static bool
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777                    int target, int refclk, intel_clock_t *match_clock,
778                    intel_clock_t *best_clock)
779 {
780         struct drm_device *dev = crtc->base.dev;
781         intel_clock_t clock;
782         unsigned int bestppm = 1000000;
783         /* min update 19.2 MHz */
784         int max_n = min(limit->n.max, refclk / 19200);
785         bool found = false;
786 
787         target *= 5; /* fast clock */
788 
789         memset(best_clock, 0, sizeof(*best_clock));
790 
791         /* based on hardware requirement, prefer smaller n to precision */
792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796                                 clock.p = clock.p1 * clock.p2;
797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799                                         unsigned int ppm, diff;
800 
801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802                                                                      refclk * clock.m1);
803 
804                                         vlv_clock(refclk, &clock);
805 
806                                         if (!intel_PLL_is_valid(dev, limit,
807                                                                 &clock))
808                                                 continue;
809 
810                                         diff = abs(clock.dot - target);
811                                         ppm = div_u64(1000000ULL * diff, target);
812 
813                                         if (ppm < 100 && clock.p > best_clock->p) {
814                                                 bestppm = 0;
815                                                 *best_clock = clock;
816                                                 found = true;
817                                         }
818 
819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
820                                                 bestppm = ppm;
821                                                 *best_clock = clock;
822                                                 found = true;
823                                         }
824                                 }
825                         }
826                 }
827         }
828 
829         return found;
830 }
831 
832 static bool
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834                    int target, int refclk, intel_clock_t *match_clock,
835                    intel_clock_t *best_clock)
836 {
837         struct drm_device *dev = crtc->base.dev;
838         intel_clock_t clock;
839         uint64_t m2;
840         int found = false;
841 
842         memset(best_clock, 0, sizeof(*best_clock));
843 
844         /*
845          * Based on hardware doc, the n always set to 1, and m1 always
846          * set to 2.  If requires to support 200Mhz refclk, we need to
847          * revisit this because n may not 1 anymore.
848          */
849         clock.n = 1, clock.m1 = 2;
850         target *= 5;    /* fast clock */
851 
852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853                 for (clock.p2 = limit->p2.p2_fast;
854                                 clock.p2 >= limit->p2.p2_slow;
855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856 
857                         clock.p = clock.p1 * clock.p2;
858 
859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860                                         clock.n) << 22, refclk * clock.m1);
861 
862                         if (m2 > INT_MAX/clock.m1)
863                                 continue;
864 
865                         clock.m2 = m2;
866 
867                         chv_clock(refclk, &clock);
868 
869                         if (!intel_PLL_is_valid(dev, limit, &clock))
870                                 continue;
871 
872                         /* based on hardware requirement, prefer bigger p
873                          */
874                         if (clock.p > best_clock->p) {
875                                 *best_clock = clock;
876                                 found = true;
877                         }
878                 }
879         }
880 
881         return found;
882 }
883 
884 bool intel_crtc_active(struct drm_crtc *crtc)
885 {
886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887 
888         /* Be paranoid as we can arrive here with only partial
889          * state retrieved from the hardware during setup.
890          *
891          * We can ditch the adjusted_mode.crtc_clock check as soon
892          * as Haswell has gained clock readout/fastboot support.
893          *
894          * We can ditch the crtc->primary->fb check as soon as we can
895          * properly reconstruct framebuffers.
896          */
897         return intel_crtc->active && crtc->primary->fb &&
898                 intel_crtc->config.adjusted_mode.crtc_clock;
899 }
900 
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902                                              enum pipe pipe)
903 {
904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906 
907         return intel_crtc->config.cpu_transcoder;
908 }
909 
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911 {
912         struct drm_i915_private *dev_priv = dev->dev_private;
913         u32 reg = PIPEDSL(pipe);
914         u32 line1, line2;
915         u32 line_mask;
916 
917         if (IS_GEN2(dev))
918                 line_mask = DSL_LINEMASK_GEN2;
919         else
920                 line_mask = DSL_LINEMASK_GEN3;
921 
922         line1 = I915_READ(reg) & line_mask;
923         mdelay(5);
924         line2 = I915_READ(reg) & line_mask;
925 
926         return line1 == line2;
927 }
928 
929 /*
930  * intel_wait_for_pipe_off - wait for pipe to turn off
931  * @crtc: crtc whose pipe to wait for
932  *
933  * After disabling a pipe, we can't wait for vblank in the usual way,
934  * spinning on the vblank interrupt status bit, since we won't actually
935  * see an interrupt when the pipe is disabled.
936  *
937  * On Gen4 and above:
938  *   wait for the pipe register state bit to turn off
939  *
940  * Otherwise:
941  *   wait for the display line value to settle (it usually
942  *   ends up stopping at the start of the next frame).
943  *
944  */
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
946 {
947         struct drm_device *dev = crtc->base.dev;
948         struct drm_i915_private *dev_priv = dev->dev_private;
949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950         enum pipe pipe = crtc->pipe;
951 
952         if (INTEL_INFO(dev)->gen >= 4) {
953                 int reg = PIPECONF(cpu_transcoder);
954 
955                 /* Wait for the Pipe State to go off */
956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957                              100))
958                         WARN(1, "pipe_off wait timed out\n");
959         } else {
960                 /* Wait for the display line to settle */
961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962                         WARN(1, "pipe_off wait timed out\n");
963         }
964 }
965 
966 /*
967  * ibx_digital_port_connected - is the specified port connected?
968  * @dev_priv: i915 private structure
969  * @port: the port to test
970  *
971  * Returns true if @port is connected, false otherwise.
972  */
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974                                 struct intel_digital_port *port)
975 {
976         u32 bit;
977 
978         if (HAS_PCH_IBX(dev_priv->dev)) {
979                 switch (port->port) {
980                 case PORT_B:
981                         bit = SDE_PORTB_HOTPLUG;
982                         break;
983                 case PORT_C:
984                         bit = SDE_PORTC_HOTPLUG;
985                         break;
986                 case PORT_D:
987                         bit = SDE_PORTD_HOTPLUG;
988                         break;
989                 default:
990                         return true;
991                 }
992         } else {
993                 switch (port->port) {
994                 case PORT_B:
995                         bit = SDE_PORTB_HOTPLUG_CPT;
996                         break;
997                 case PORT_C:
998                         bit = SDE_PORTC_HOTPLUG_CPT;
999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007 
1008         return I915_READ(SDEISR) & bit;
1009 }
1010 
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015 
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023 
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031 
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037 
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041 
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049 
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054 
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057 
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060 
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068 
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072 
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078 
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087 
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104 
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111 
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121 
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127 
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131 
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135 
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140 
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147 
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155 
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164 
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167 
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170 
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173 
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187 
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192 
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197 
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203 
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208 
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215 
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224 
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229 
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238 
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243 
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250 
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258 
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261 
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269 
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279 
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291 
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298 
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328 
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334 
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339 
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341 
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347 
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354 
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362 
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368 
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383 
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389 
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402 
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408 
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418 
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433 
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441 
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446 
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454 
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459 
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465 
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469 
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475 
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481 
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486 
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490 
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493 
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506 
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514 
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516 
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519 
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523 
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527 
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530 
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533 
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545 
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554 
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556 
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558 
1559         mutex_lock(&dev_priv->dpio_lock);
1560 
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565 
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570 
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573 
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577 
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581 
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584 
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589 
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593 
1594         return count;
1595 }
1596 
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603 
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605 
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608 
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612 
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625 
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629 
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641 
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653 
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668 
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678 
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683 
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686 
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690 
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694 
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697 
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706 
1707 }
1708 
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713 
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716 
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723 
1724         mutex_lock(&dev_priv->dpio_lock);
1725 
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730 
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741 
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744 
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750 
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767 
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772 
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778 
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781 
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787 
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791 
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805 
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808 
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811 
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815 
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822 
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824 
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829 
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835 
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840 
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843 
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847 
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852 
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857 
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861 
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864 
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872 
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875 
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879 
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883 
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892 
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896 
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905 
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915 
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920 
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925 
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928 
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932 
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937 
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940 
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946 
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951 
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957 
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961 
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964 
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972 
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981 
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985 
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992 
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998 
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016 
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020 
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025 
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045 
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053 
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057 
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075 
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083 
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088 
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095 
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100 
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105 
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115 
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119 
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136 
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139 
2140         intel_crtc->primary_enabled = true;
2141 
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144 
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153 
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167 
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169 
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172 
2173         intel_crtc->primary_enabled = false;
2174 
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178 
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187 
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191 
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195 
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206 
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208 
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234 
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242 
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251 
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256 
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265 
2266         i915_gem_object_pin_fence(obj);
2267 
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271 
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279 
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283 
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287 
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297 
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300 
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303 
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307 
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314 
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335 
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343 
2344         if (plane_config->size == 0)
2345                 return false;
2346 
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351 
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356 
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361 
2362         mutex_lock(&dev->struct_mutex);
2363 
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369 
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372 
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375 
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381 
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390 
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393 
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396 
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399 
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406 
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409 
2410                 if (!i->active)
2411                         continue;
2412 
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416 
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420 
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428 
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442 
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452 
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456 
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458 
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460 
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462 
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466 
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481 
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512 
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516 
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519 
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521 
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531 
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534 
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537 
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544 
2545         I915_WRITE(reg, dspcntr);
2546 
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560 
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574 
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581 
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585 
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587 
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589 
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591 
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594 
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621 
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624 
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627 
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636 
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640 
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648 
2649         I915_WRITE(reg, dspcntr);
2650 
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665 
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677 
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684 
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688 
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710 
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713 
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729 
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733 
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735 
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740 
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748 
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751 
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759 
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762 
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764 
2765         return 0;
2766 }
2767 
2768 static void intel_complete_page_flips(struct drm_device *dev)
2769 {
2770         struct drm_crtc *crtc;
2771 
2772         for_each_crtc(dev, crtc) {
2773                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774                 enum plane plane = intel_crtc->plane;
2775 
2776                 intel_prepare_page_flip(dev, plane);
2777                 intel_finish_page_flip_plane(dev, plane);
2778         }
2779 }
2780 
2781 static void intel_update_primary_planes(struct drm_device *dev)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct drm_crtc *crtc;
2785 
2786         for_each_crtc(dev, crtc) {
2787                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788 
2789                 drm_modeset_lock(&crtc->mutex, NULL);
2790                 /*
2791                  * FIXME: Once we have proper support for primary planes (and
2792                  * disabling them without disabling the entire crtc) allow again
2793                  * a NULL crtc->primary->fb.
2794                  */
2795                 if (intel_crtc->active && crtc->primary->fb)
2796                         dev_priv->display.update_primary_plane(crtc,
2797                                                                crtc->primary->fb,
2798                                                                crtc->x,
2799                                                                crtc->y);
2800                 drm_modeset_unlock(&crtc->mutex);
2801         }
2802 }
2803 
2804 void intel_prepare_reset(struct drm_device *dev)
2805 {
2806         struct drm_i915_private *dev_priv = to_i915(dev);
2807         struct intel_crtc *crtc;
2808 
2809         /* no reset support for gen2 */
2810         if (IS_GEN2(dev))
2811                 return;
2812 
2813         /* reset doesn't touch the display */
2814         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2815                 return;
2816 
2817         drm_modeset_lock_all(dev);
2818 
2819         /*
2820          * Disabling the crtcs gracefully seems nicer. Also the
2821          * g33 docs say we should at least disable all the planes.
2822          */
2823         for_each_intel_crtc(dev, crtc) {
2824                 if (crtc->active)
2825                         dev_priv->display.crtc_disable(&crtc->base);
2826         }
2827 }
2828 
2829 void intel_finish_reset(struct drm_device *dev)
2830 {
2831         struct drm_i915_private *dev_priv = to_i915(dev);
2832 
2833         /*
2834          * Flips in the rings will be nuked by the reset,
2835          * so complete all pending flips so that user space
2836          * will get its events and not get stuck.
2837          */
2838         intel_complete_page_flips(dev);
2839 
2840         /* no reset support for gen2 */
2841         if (IS_GEN2(dev))
2842                 return;
2843 
2844         /* reset doesn't touch the display */
2845         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2846                 /*
2847                  * Flips in the rings have been nuked by the reset,
2848                  * so update the base address of all primary
2849                  * planes to the the last fb to make sure we're
2850                  * showing the correct fb after a reset.
2851                  */
2852                 intel_update_primary_planes(dev);
2853                 return;
2854         }
2855 
2856         /*
2857          * The display has been reset as well,
2858          * so need a full re-initialization.
2859          */
2860         intel_runtime_pm_disable_interrupts(dev_priv);
2861         intel_runtime_pm_enable_interrupts(dev_priv);
2862 
2863         intel_modeset_init_hw(dev);
2864 
2865         spin_lock_irq(&dev_priv->irq_lock);
2866         if (dev_priv->display.hpd_irq_setup)
2867                 dev_priv->display.hpd_irq_setup(dev);
2868         spin_unlock_irq(&dev_priv->irq_lock);
2869 
2870         intel_modeset_setup_hw_state(dev, true);
2871 
2872         intel_hpd_init(dev_priv);
2873 
2874         drm_modeset_unlock_all(dev);
2875 }
2876 
2877 static int
2878 intel_finish_fb(struct drm_framebuffer *old_fb)
2879 {
2880         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2881         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2882         bool was_interruptible = dev_priv->mm.interruptible;
2883         int ret;
2884 
2885         /* Big Hammer, we also need to ensure that any pending
2886          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2887          * current scanout is retired before unpinning the old
2888          * framebuffer.
2889          *
2890          * This should only fail upon a hung GPU, in which case we
2891          * can safely continue.
2892          */
2893         dev_priv->mm.interruptible = false;
2894         ret = i915_gem_object_finish_gpu(obj);
2895         dev_priv->mm.interruptible = was_interruptible;
2896 
2897         return ret;
2898 }
2899 
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905         bool pending;
2906 
2907         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2908             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2909                 return false;
2910 
2911         spin_lock_irq(&dev->event_lock);
2912         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2913         spin_unlock_irq(&dev->event_lock);
2914 
2915         return pending;
2916 }
2917 
2918 static void intel_update_pipe_size(struct intel_crtc *crtc)
2919 {
2920         struct drm_device *dev = crtc->base.dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         const struct drm_display_mode *adjusted_mode;
2923 
2924         if (!i915.fastboot)
2925                 return;
2926 
2927         /*
2928          * Update pipe size and adjust fitter if needed: the reason for this is
2929          * that in compute_mode_changes we check the native mode (not the pfit
2930          * mode) to see if we can flip rather than do a full mode set. In the
2931          * fastboot case, we'll flip, but if we don't update the pipesrc and
2932          * pfit state, we'll end up with a big fb scanned out into the wrong
2933          * sized surface.
2934          *
2935          * To fix this properly, we need to hoist the checks up into
2936          * compute_mode_changes (or above), check the actual pfit state and
2937          * whether the platform allows pfit disable with pipe active, and only
2938          * then update the pipesrc and pfit state, even on the flip path.
2939          */
2940 
2941         adjusted_mode = &crtc->config.adjusted_mode;
2942 
2943         I915_WRITE(PIPESRC(crtc->pipe),
2944                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2945                    (adjusted_mode->crtc_vdisplay - 1));
2946         if (!crtc->config.pch_pfit.enabled &&
2947             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2948              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2949                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2950                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2951                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2952         }
2953         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2954         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2955 }
2956 
2957 static int
2958 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2959                     struct drm_framebuffer *fb)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         enum pipe pipe = intel_crtc->pipe;
2965         struct drm_framebuffer *old_fb = crtc->primary->fb;
2966         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2967         int ret;
2968 
2969         if (intel_crtc_has_pending_flip(crtc)) {
2970                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2971                 return -EBUSY;
2972         }
2973 
2974         /* no fb bound */
2975         if (!fb) {
2976                 DRM_ERROR("No FB bound\n");
2977                 return 0;
2978         }
2979 
2980         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2981                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2982                           plane_name(intel_crtc->plane),
2983                           INTEL_INFO(dev)->num_pipes);
2984                 return -EINVAL;
2985         }
2986 
2987         mutex_lock(&dev->struct_mutex);
2988         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2989         if (ret == 0)
2990                 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2991                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2992         mutex_unlock(&dev->struct_mutex);
2993         if (ret != 0) {
2994                 DRM_ERROR("pin & fence failed\n");
2995                 return ret;
2996         }
2997 
2998         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2999 
3000         if (intel_crtc->active)
3001                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
3002 
3003         crtc->primary->fb = fb;
3004         crtc->x = x;
3005         crtc->y = y;
3006 
3007         if (old_fb) {
3008                 if (intel_crtc->active && old_fb != fb)
3009                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3010                 mutex_lock(&dev->struct_mutex);
3011                 intel_unpin_fb_obj(old_obj);
3012                 mutex_unlock(&dev->struct_mutex);
3013         }
3014 
3015         mutex_lock(&dev->struct_mutex);
3016         intel_update_fbc(dev);
3017         mutex_unlock(&dev->struct_mutex);
3018 
3019         return 0;
3020 }
3021 
3022 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3023 {
3024         struct drm_device *dev = crtc->dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027         int pipe = intel_crtc->pipe;
3028         u32 reg, temp;
3029 
3030         /* enable normal train */
3031         reg = FDI_TX_CTL(pipe);
3032         temp = I915_READ(reg);
3033         if (IS_IVYBRIDGE(dev)) {
3034                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3035                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3036         } else {
3037                 temp &= ~FDI_LINK_TRAIN_NONE;
3038                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3039         }
3040         I915_WRITE(reg, temp);
3041 
3042         reg = FDI_RX_CTL(pipe);
3043         temp = I915_READ(reg);
3044         if (HAS_PCH_CPT(dev)) {
3045                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3047         } else {
3048                 temp &= ~FDI_LINK_TRAIN_NONE;
3049                 temp |= FDI_LINK_TRAIN_NONE;
3050         }
3051         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3052 
3053         /* wait one idle pattern time */
3054         POSTING_READ(reg);
3055         udelay(1000);
3056 
3057         /* IVB wants error correction enabled */
3058         if (IS_IVYBRIDGE(dev))
3059                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3060                            FDI_FE_ERRC_ENABLE);
3061 }
3062 
3063 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3064 {
3065         return crtc->base.enabled && crtc->active &&
3066                 crtc->config.has_pch_encoder;
3067 }
3068 
3069 static void ivb_modeset_global_resources(struct drm_device *dev)
3070 {
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *pipe_B_crtc =
3073                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3074         struct intel_crtc *pipe_C_crtc =
3075                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3076         uint32_t temp;
3077 
3078         /*
3079          * When everything is off disable fdi C so that we could enable fdi B
3080          * with all lanes. Note that we don't care about enabled pipes without
3081          * an enabled pch encoder.
3082          */
3083         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3084             !pipe_has_enabled_pch(pipe_C_crtc)) {
3085                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3086                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3087 
3088                 temp = I915_READ(SOUTH_CHICKEN1);
3089                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3090                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091                 I915_WRITE(SOUTH_CHICKEN1, temp);
3092         }
3093 }
3094 
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3097 {
3098         struct drm_device *dev = crtc->dev;
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101         int pipe = intel_crtc->pipe;
3102         u32 reg, temp, tries;
3103 
3104         /* FDI needs bits from pipe first */
3105         assert_pipe_enabled(dev_priv, pipe);
3106 
3107         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108            for train result */
3109         reg = FDI_RX_IMR(pipe);
3110         temp = I915_READ(reg);
3111         temp &= ~FDI_RX_SYMBOL_LOCK;
3112         temp &= ~FDI_RX_BIT_LOCK;
3113         I915_WRITE(reg, temp);
3114         I915_READ(reg);
3115         udelay(150);
3116 
3117         /* enable CPU FDI TX and PCH FDI RX */
3118         reg = FDI_TX_CTL(pipe);
3119         temp = I915_READ(reg);
3120         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3121         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3122         temp &= ~FDI_LINK_TRAIN_NONE;
3123         temp |= FDI_LINK_TRAIN_PATTERN_1;
3124         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3125 
3126         reg = FDI_RX_CTL(pipe);
3127         temp = I915_READ(reg);
3128         temp &= ~FDI_LINK_TRAIN_NONE;
3129         temp |= FDI_LINK_TRAIN_PATTERN_1;
3130         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3131 
3132         POSTING_READ(reg);
3133         udelay(150);
3134 
3135         /* Ironlake workaround, enable clock pointer after FDI enable*/
3136         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3137         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3138                    FDI_RX_PHASE_SYNC_POINTER_EN);
3139 
3140         reg = FDI_RX_IIR(pipe);
3141         for (tries = 0; tries < 5; tries++) {
3142                 temp = I915_READ(reg);
3143                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3144 
3145                 if ((temp & FDI_RX_BIT_LOCK)) {
3146                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3147                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3148                         break;
3149                 }
3150         }
3151         if (tries == 5)
3152                 DRM_ERROR("FDI train 1 fail!\n");
3153 
3154         /* Train 2 */
3155         reg = FDI_TX_CTL(pipe);
3156         temp = I915_READ(reg);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_2;
3159         I915_WRITE(reg, temp);
3160 
3161         reg = FDI_RX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         temp &= ~FDI_LINK_TRAIN_NONE;
3164         temp |= FDI_LINK_TRAIN_PATTERN_2;
3165         I915_WRITE(reg, temp);
3166 
3167         POSTING_READ(reg);
3168         udelay(150);
3169 
3170         reg = FDI_RX_IIR(pipe);
3171         for (tries = 0; tries < 5; tries++) {
3172                 temp = I915_READ(reg);
3173                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3174 
3175                 if (temp & FDI_RX_SYMBOL_LOCK) {
3176                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3177                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3178                         break;
3179                 }
3180         }
3181         if (tries == 5)
3182                 DRM_ERROR("FDI train 2 fail!\n");
3183 
3184         DRM_DEBUG_KMS("FDI train done\n");
3185 
3186 }
3187 
3188 static const int snb_b_fdi_train_param[] = {
3189         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3190         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3191         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3192         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3193 };
3194 
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201         int pipe = intel_crtc->pipe;
3202         u32 reg, temp, i, retry;
3203 
3204         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3205            for train result */
3206         reg = FDI_RX_IMR(pipe);
3207         temp = I915_READ(reg);
3208         temp &= ~FDI_RX_SYMBOL_LOCK;
3209         temp &= ~FDI_RX_BIT_LOCK;
3210         I915_WRITE(reg, temp);
3211 
3212         POSTING_READ(reg);
3213         udelay(150);
3214 
3215         /* enable CPU FDI TX and PCH FDI RX */
3216         reg = FDI_TX_CTL(pipe);
3217         temp = I915_READ(reg);
3218         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3219         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3220         temp &= ~FDI_LINK_TRAIN_NONE;
3221         temp |= FDI_LINK_TRAIN_PATTERN_1;
3222         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3223         /* SNB-B */
3224         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3225         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3226 
3227         I915_WRITE(FDI_RX_MISC(pipe),
3228                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3229 
3230         reg = FDI_RX_CTL(pipe);
3231         temp = I915_READ(reg);
3232         if (HAS_PCH_CPT(dev)) {
3233                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3234                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3235         } else {
3236                 temp &= ~FDI_LINK_TRAIN_NONE;
3237                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3238         }
3239         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3240 
3241         POSTING_READ(reg);
3242         udelay(150);
3243 
3244         for (i = 0; i < 4; i++) {
3245                 reg = FDI_TX_CTL(pipe);
3246                 temp = I915_READ(reg);
3247                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3248                 temp |= snb_b_fdi_train_param[i];
3249                 I915_WRITE(reg, temp);
3250 
3251                 POSTING_READ(reg);
3252                 udelay(500);
3253 
3254                 for (retry = 0; retry < 5; retry++) {
3255                         reg = FDI_RX_IIR(pipe);
3256                         temp = I915_READ(reg);
3257                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3258                         if (temp & FDI_RX_BIT_LOCK) {
3259                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3260                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3261                                 break;
3262                         }
3263                         udelay(50);
3264                 }
3265                 if (retry < 5)
3266                         break;
3267         }
3268         if (i == 4)
3269                 DRM_ERROR("FDI train 1 fail!\n");
3270 
3271         /* Train 2 */
3272         reg = FDI_TX_CTL(pipe);
3273         temp = I915_READ(reg);
3274         temp &= ~FDI_LINK_TRAIN_NONE;
3275         temp |= FDI_LINK_TRAIN_PATTERN_2;
3276         if (IS_GEN6(dev)) {
3277                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278                 /* SNB-B */
3279                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3280         }
3281         I915_WRITE(reg, temp);
3282 
3283         reg = FDI_RX_CTL(pipe);
3284         temp = I915_READ(reg);
3285         if (HAS_PCH_CPT(dev)) {
3286                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3287                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3288         } else {
3289                 temp &= ~FDI_LINK_TRAIN_NONE;
3290                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3291         }
3292         I915_WRITE(reg, temp);
3293 
3294         POSTING_READ(reg);
3295         udelay(150);
3296 
3297         for (i = 0; i < 4; i++) {
3298                 reg = FDI_TX_CTL(pipe);
3299                 temp = I915_READ(reg);
3300                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3301                 temp |= snb_b_fdi_train_param[i];
3302                 I915_WRITE(reg, temp);
3303 
3304                 POSTING_READ(reg);
3305                 udelay(500);
3306 
3307                 for (retry = 0; retry < 5; retry++) {
3308                         reg = FDI_RX_IIR(pipe);
3309                         temp = I915_READ(reg);
3310                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3311                         if (temp & FDI_RX_SYMBOL_LOCK) {
3312                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3313                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3314                                 break;
3315                         }
3316                         udelay(50);
3317                 }
3318                 if (retry < 5)
3319                         break;
3320         }
3321         if (i == 4)
3322                 DRM_ERROR("FDI train 2 fail!\n");
3323 
3324         DRM_DEBUG_KMS("FDI train done.\n");
3325 }
3326 
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3329 {
3330         struct drm_device *dev = crtc->dev;
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333         int pipe = intel_crtc->pipe;
3334         u32 reg, temp, i, j;
3335 
3336         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3337            for train result */
3338         reg = FDI_RX_IMR(pipe);
3339         temp = I915_READ(reg);
3340         temp &= ~FDI_RX_SYMBOL_LOCK;
3341         temp &= ~FDI_RX_BIT_LOCK;
3342         I915_WRITE(reg, temp);
3343 
3344         POSTING_READ(reg);
3345         udelay(150);
3346 
3347         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348                       I915_READ(FDI_RX_IIR(pipe)));
3349 
3350         /* Try each vswing and preemphasis setting twice before moving on */
3351         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3352                 /* disable first in case we need to retry */
3353                 reg = FDI_TX_CTL(pipe);
3354                 temp = I915_READ(reg);
3355                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3356                 temp &= ~FDI_TX_ENABLE;
3357                 I915_WRITE(reg, temp);
3358 
3359                 reg = FDI_RX_CTL(pipe);
3360                 temp = I915_READ(reg);
3361                 temp &= ~FDI_LINK_TRAIN_AUTO;
3362                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363                 temp &= ~FDI_RX_ENABLE;
3364                 I915_WRITE(reg, temp);
3365 
3366                 /* enable CPU FDI TX and PCH FDI RX */
3367                 reg = FDI_TX_CTL(pipe);
3368                 temp = I915_READ(reg);
3369                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3370                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3371                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3372                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3373                 temp |= snb_b_fdi_train_param[j/2];
3374                 temp |= FDI_COMPOSITE_SYNC;
3375                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3376 
3377                 I915_WRITE(FDI_RX_MISC(pipe),
3378                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3379 
3380                 reg = FDI_RX_CTL(pipe);
3381                 temp = I915_READ(reg);
3382                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3383                 temp |= FDI_COMPOSITE_SYNC;
3384                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3385 
3386                 POSTING_READ(reg);
3387                 udelay(1); /* should be 0.5us */
3388 
3389                 for (i = 0; i < 4; i++) {
3390                         reg = FDI_RX_IIR(pipe);
3391                         temp = I915_READ(reg);
3392                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393 
3394                         if (temp & FDI_RX_BIT_LOCK ||
3395                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3396                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3397                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3398                                               i);
3399                                 break;
3400                         }
3401                         udelay(1); /* should be 0.5us */
3402                 }
3403                 if (i == 4) {
3404                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3405                         continue;
3406                 }
3407 
3408                 /* Train 2 */
3409                 reg = FDI_TX_CTL(pipe);
3410                 temp = I915_READ(reg);
3411                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3413                 I915_WRITE(reg, temp);
3414 
3415                 reg = FDI_RX_CTL(pipe);
3416                 temp = I915_READ(reg);
3417                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3419                 I915_WRITE(reg, temp);
3420 
3421                 POSTING_READ(reg);
3422                 udelay(2); /* should be 1.5us */
3423 
3424                 for (i = 0; i < 4; i++) {
3425                         reg = FDI_RX_IIR(pipe);
3426                         temp = I915_READ(reg);
3427                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428 
3429                         if (temp & FDI_RX_SYMBOL_LOCK ||
3430                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3431                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3433                                               i);
3434                                 goto train_done;
3435                         }
3436                         udelay(2); /* should be 1.5us */
3437                 }
3438                 if (i == 4)
3439                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3440         }
3441 
3442 train_done:
3443         DRM_DEBUG_KMS("FDI train done.\n");
3444 }
3445 
3446 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3447 {
3448         struct drm_device *dev = intel_crtc->base.dev;
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450         int pipe = intel_crtc->pipe;
3451         u32 reg, temp;
3452 
3453 
3454         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3458         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3459         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3460         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3461 
3462         POSTING_READ(reg);
3463         udelay(200);
3464 
3465         /* Switch from Rawclk to PCDclk */
3466         temp = I915_READ(reg);
3467         I915_WRITE(reg, temp | FDI_PCDCLK);
3468 
3469         POSTING_READ(reg);
3470         udelay(200);
3471 
3472         /* Enable CPU FDI TX PLL, always on for Ironlake */
3473         reg = FDI_TX_CTL(pipe);
3474         temp = I915_READ(reg);
3475         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3476                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3477 
3478                 POSTING_READ(reg);
3479                 udelay(100);
3480         }
3481 }
3482 
3483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3484 {
3485         struct drm_device *dev = intel_crtc->base.dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         int pipe = intel_crtc->pipe;
3488         u32 reg, temp;
3489 
3490         /* Switch from PCDclk to Rawclk */
3491         reg = FDI_RX_CTL(pipe);
3492         temp = I915_READ(reg);
3493         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3494 
3495         /* Disable CPU FDI TX PLL */
3496         reg = FDI_TX_CTL(pipe);
3497         temp = I915_READ(reg);
3498         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3499 
3500         POSTING_READ(reg);
3501         udelay(100);
3502 
3503         reg = FDI_RX_CTL(pipe);
3504         temp = I915_READ(reg);
3505         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3506 
3507         /* Wait for the clocks to turn off. */
3508         POSTING_READ(reg);
3509         udelay(100);
3510 }
3511 
3512 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3513 {
3514         struct drm_device *dev = crtc->dev;
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517         int pipe = intel_crtc->pipe;
3518         u32 reg, temp;
3519 
3520         /* disable CPU FDI tx and PCH FDI rx */
3521         reg = FDI_TX_CTL(pipe);
3522         temp = I915_READ(reg);
3523         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3524         POSTING_READ(reg);
3525 
3526         reg = FDI_RX_CTL(pipe);
3527         temp = I915_READ(reg);
3528         temp &= ~(0x7 << 16);
3529         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3530         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3531 
3532         POSTING_READ(reg);
3533         udelay(100);
3534 
3535         /* Ironlake workaround, disable clock pointer after downing FDI */
3536         if (HAS_PCH_IBX(dev))
3537                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3538 
3539         /* still set train pattern 1 */
3540         reg = FDI_TX_CTL(pipe);
3541         temp = I915_READ(reg);
3542         temp &= ~FDI_LINK_TRAIN_NONE;
3543         temp |= FDI_LINK_TRAIN_PATTERN_1;
3544         I915_WRITE(reg, temp);
3545 
3546         reg = FDI_RX_CTL(pipe);
3547         temp = I915_READ(reg);
3548         if (HAS_PCH_CPT(dev)) {
3549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3551         } else {
3552                 temp &= ~FDI_LINK_TRAIN_NONE;
3553                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3554         }
3555         /* BPC in FDI rx is consistent with that in PIPECONF */
3556         temp &= ~(0x07 << 16);
3557         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3558         I915_WRITE(reg, temp);
3559 
3560         POSTING_READ(reg);
3561         udelay(100);
3562 }
3563 
3564 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3565 {
3566         struct intel_crtc *crtc;
3567 
3568         /* Note that we don't need to be called with mode_config.lock here
3569          * as our list of CRTC objects is static for the lifetime of the
3570          * device and so cannot disappear as we iterate. Similarly, we can
3571          * happily treat the predicates as racy, atomic checks as userspace
3572          * cannot claim and pin a new fb without at least acquring the
3573          * struct_mutex and so serialising with us.
3574          */
3575         for_each_intel_crtc(dev, crtc) {
3576                 if (atomic_read(&crtc->unpin_work_count) == 0)
3577                         continue;
3578 
3579                 if (crtc->unpin_work)
3580                         intel_wait_for_vblank(dev, crtc->pipe);
3581 
3582                 return true;
3583         }
3584 
3585         return false;
3586 }
3587 
3588 static void page_flip_completed(struct intel_crtc *intel_crtc)
3589 {
3590         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3591         struct intel_unpin_work *work = intel_crtc->unpin_work;
3592 
3593         /* ensure that the unpin work is consistent wrt ->pending. */
3594         smp_rmb();
3595         intel_crtc->unpin_work = NULL;
3596 
3597         if (work->event)
3598                 drm_send_vblank_event(intel_crtc->base.dev,
3599                                       intel_crtc->pipe,
3600                                       work->event);
3601 
3602         drm_crtc_vblank_put(&intel_crtc->base);
3603 
3604         wake_up_all(&dev_priv->pending_flip_queue);
3605         queue_work(dev_priv->wq, &work->work);
3606 
3607         trace_i915_flip_complete(intel_crtc->plane,
3608                                  work->pending_flip_obj);
3609 }
3610 
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3612 {
3613         struct drm_device *dev = crtc->dev;
3614         struct drm_i915_private *dev_priv = dev->dev_private;
3615 
3616         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3617         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3618                                        !intel_crtc_has_pending_flip(crtc),
3619                                        60*HZ) == 0)) {
3620                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621 
3622                 spin_lock_irq(&dev->event_lock);
3623                 if (intel_crtc->unpin_work) {
3624                         WARN_ONCE(1, "Removing stuck page flip\n");
3625                         page_flip_completed(intel_crtc);
3626                 }
3627                 spin_unlock_irq(&dev->event_lock);
3628         }
3629 
3630         if (crtc->primary->fb) {
3631                 mutex_lock(&dev->struct_mutex);
3632                 intel_finish_fb(crtc->primary->fb);
3633                 mutex_unlock(&dev->struct_mutex);
3634         }
3635 }
3636 
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3643         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3644         u32 temp;
3645 
3646         mutex_lock(&dev_priv->dpio_lock);
3647 
3648         /* It is necessary to ungate the pixclk gate prior to programming
3649          * the divisors, and gate it back when it is done.
3650          */
3651         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3652 
3653         /* Disable SSCCTL */
3654         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3655                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3656                                 SBI_SSCCTL_DISABLE,
3657                         SBI_ICLK);
3658 
3659         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660         if (clock == 20000) {
3661                 auxdiv = 1;
3662                 divsel = 0x41;
3663                 phaseinc = 0x20;
3664         } else {
3665                 /* The iCLK virtual clock root frequency is in MHz,
3666                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3667                  * divisors, it is necessary to divide one by another, so we
3668                  * convert the virtual clock precision to KHz here for higher
3669                  * precision.
3670                  */
3671                 u32 iclk_virtual_root_freq = 172800 * 1000;
3672                 u32 iclk_pi_range = 64;
3673                 u32 desired_divisor, msb_divisor_value, pi_value;
3674 
3675                 desired_divisor = (iclk_virtual_root_freq / clock);
3676                 msb_divisor_value = desired_divisor / iclk_pi_range;
3677                 pi_value = desired_divisor % iclk_pi_range;
3678 
3679                 auxdiv = 0;
3680                 divsel = msb_divisor_value - 2;
3681                 phaseinc = pi_value;
3682         }
3683 
3684         /* This should not happen with any sane values */
3685         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3686                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3687         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3688                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3689 
3690         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3691                         clock,
3692                         auxdiv,
3693                         divsel,
3694                         phasedir,
3695                         phaseinc);
3696 
3697         /* Program SSCDIVINTPHASE6 */
3698         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3699         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3700         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3701         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3702         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3703         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3704         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3705         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3706 
3707         /* Program SSCAUXDIV */
3708         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3709         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3711         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3712 
3713         /* Enable modulator and associated divider */
3714         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3715         temp &= ~SBI_SSCCTL_DISABLE;
3716         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3717 
3718         /* Wait for initialization time */
3719         udelay(24);
3720 
3721         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3722 
3723         mutex_unlock(&dev_priv->dpio_lock);
3724 }
3725 
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3727                                                 enum pipe pch_transcoder)
3728 {
3729         struct drm_device *dev = crtc->base.dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3732 
3733         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3734                    I915_READ(HTOTAL(cpu_transcoder)));
3735         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3736                    I915_READ(HBLANK(cpu_transcoder)));
3737         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3738                    I915_READ(HSYNC(cpu_transcoder)));
3739 
3740         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3741                    I915_READ(VTOTAL(cpu_transcoder)));
3742         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3743                    I915_READ(VBLANK(cpu_transcoder)));
3744         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3745                    I915_READ(VSYNC(cpu_transcoder)));
3746         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3747                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3748 }
3749 
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3751 {
3752         struct drm_i915_private *dev_priv = dev->dev_private;
3753         uint32_t temp;
3754 
3755         temp = I915_READ(SOUTH_CHICKEN1);
3756         if (temp & FDI_BC_BIFURCATION_SELECT)
3757                 return;
3758 
3759         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3760         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3761 
3762         temp |= FDI_BC_BIFURCATION_SELECT;
3763         DRM_DEBUG_KMS("enabling fdi C rx\n");
3764         I915_WRITE(SOUTH_CHICKEN1, temp);
3765         POSTING_READ(SOUTH_CHICKEN1);
3766 }
3767 
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3769 {
3770         struct drm_device *dev = intel_crtc->base.dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772 
3773         switch (intel_crtc->pipe) {
3774         case PIPE_A:
3775                 break;
3776         case PIPE_B:
3777                 if (intel_crtc->config.fdi_lanes > 2)
3778                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3779                 else
3780                         cpt_enable_fdi_bc_bifurcation(dev);
3781 
3782                 break;
3783         case PIPE_C:
3784                 cpt_enable_fdi_bc_bifurcation(dev);
3785 
3786                 break;
3787         default:
3788                 BUG();
3789         }
3790 }
3791 
3792 /*
3793  * Enable PCH resources required for PCH ports:
3794  *   - PCH PLLs
3795  *   - FDI training & RX/TX
3796  *   - update transcoder timings
3797  *   - DP transcoding bits
3798  *   - transcoder
3799  */
3800 static void ironlake_pch_enable(struct drm_crtc *crtc)
3801 {
3802         struct drm_device *dev = crtc->dev;
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805         int pipe = intel_crtc->pipe;
3806         u32 reg, temp;
3807 
3808         assert_pch_transcoder_disabled(dev_priv, pipe);
3809 
3810         if (IS_IVYBRIDGE(dev))
3811                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3812 
3813         /* Write the TU size bits before fdi link training, so that error
3814          * detection works. */
3815         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3816                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3817 
3818         /* For PCH output, training FDI link */
3819         dev_priv->display.fdi_link_train(crtc);
3820 
3821         /* We need to program the right clock selection before writing the pixel
3822          * mutliplier into the DPLL. */
3823         if (HAS_PCH_CPT(dev)) {
3824                 u32 sel;
3825 
3826                 temp = I915_READ(PCH_DPLL_SEL);
3827                 temp |= TRANS_DPLL_ENABLE(pipe);
3828                 sel = TRANS_DPLLB_SEL(pipe);
3829                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3830                         temp |= sel;
3831                 else
3832                         temp &= ~sel;
3833                 I915_WRITE(PCH_DPLL_SEL, temp);
3834         }
3835 
3836         /* XXX: pch pll's can be enabled any time before we enable the PCH
3837          * transcoder, and we actually should do this to not upset any PCH
3838          * transcoder that already use the clock when we share it.
3839          *
3840          * Note that enable_shared_dpll tries to do the right thing, but
3841          * get_shared_dpll unconditionally resets the pll - we need that to have
3842          * the right LVDS enable sequence. */
3843         intel_enable_shared_dpll(intel_crtc);
3844 
3845         /* set transcoder timing, panel must allow it */
3846         assert_panel_unlocked(dev_priv, pipe);
3847         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3848 
3849         intel_fdi_normal_train(crtc);
3850 
3851         /* For PCH DP, enable TRANS_DP_CTL */
3852         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3853                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3854                 reg = TRANS_DP_CTL(pipe);
3855                 temp = I915_READ(reg);
3856                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3857                           TRANS_DP_SYNC_MASK |
3858                           TRANS_DP_BPC_MASK);
3859                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3860                          TRANS_DP_ENH_FRAMING);
3861                 temp |= bpc << 9; /* same format but at 11:9 */
3862 
3863                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3864                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3865                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3866                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3867 
3868                 switch (intel_trans_dp_port_sel(crtc)) {
3869                 case PCH_DP_B:
3870                         temp |= TRANS_DP_PORT_SEL_B;
3871                         break;
3872                 case PCH_DP_C:
3873                         temp |= TRANS_DP_PORT_SEL_C;
3874                         break;
3875                 case PCH_DP_D:
3876                         temp |= TRANS_DP_PORT_SEL_D;
3877                         break;
3878                 default:
3879                         BUG();
3880                 }
3881 
3882                 I915_WRITE(reg, temp);
3883         }
3884 
3885         ironlake_enable_pch_transcoder(dev_priv, pipe);
3886 }
3887 
3888 static void lpt_pch_enable(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3894 
3895         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3896 
3897         lpt_program_iclkip(crtc);
3898 
3899         /* Set transcoder timing. */
3900         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3901 
3902         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3903 }
3904 
3905 void intel_put_shared_dpll(struct intel_crtc *crtc)
3906 {
3907         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3908 
3909         if (pll == NULL)
3910                 return;
3911 
3912         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3913                 WARN(1, "bad %s crtc mask\n", pll->name);
3914                 return;
3915         }
3916 
3917         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3918         if (pll->config.crtc_mask == 0) {
3919                 WARN_ON(pll->on);
3920                 WARN_ON(pll->active);
3921         }
3922 
3923         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3924 }
3925 
3926 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3927 {
3928         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3929         struct intel_shared_dpll *pll;
3930         enum intel_dpll_id i;
3931 
3932         if (HAS_PCH_IBX(dev_priv->dev)) {
3933                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3934                 i = (enum intel_dpll_id) crtc->pipe;
3935                 pll = &dev_priv->shared_dplls[i];
3936 
3937                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3938                               crtc->base.base.id, pll->name);
3939 
3940                 WARN_ON(pll->new_config->crtc_mask);
3941 
3942                 goto found;
3943         }
3944 
3945         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3946                 pll = &dev_priv->shared_dplls[i];
3947 
3948                 /* Only want to check enabled timings first */
3949                 if (pll->new_config->crtc_mask == 0)
3950                         continue;
3951 
3952                 if (memcmp(&crtc->new_config->dpll_hw_state,
3953                            &pll->new_config->hw_state,
3954                            sizeof(pll->new_config->hw_state)) == 0) {
3955                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3956                                       crtc->base.base.id, pll->name,
3957                                       pll->new_config->crtc_mask,
3958                                       pll->active);
3959                         goto found;
3960                 }
3961         }
3962 
3963         /* Ok no matching timings, maybe there's a free one? */
3964         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3965                 pll = &dev_priv->shared_dplls[i];
3966                 if (pll->new_config->crtc_mask == 0) {
3967                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3968                                       crtc->base.base.id, pll->name);
3969                         goto found;
3970                 }
3971         }
3972 
3973         return NULL;
3974 
3975 found:
3976         if (pll->new_config->crtc_mask == 0)
3977                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3978 
3979         crtc->new_config->shared_dpll = i;
3980         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3981                          pipe_name(crtc->pipe));
3982 
3983         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3984 
3985         return pll;
3986 }
3987 
3988 /**
3989  * intel_shared_dpll_start_config - start a new PLL staged config
3990  * @dev_priv: DRM device
3991  * @clear_pipes: mask of pipes that will have their PLLs freed
3992  *
3993  * Starts a new PLL staged config, copying the current config but
3994  * releasing the references of pipes specified in clear_pipes.
3995  */
3996 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3997                                           unsigned clear_pipes)
3998 {
3999         struct intel_shared_dpll *pll;
4000         enum intel_dpll_id i;
4001 
4002         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4003                 pll = &dev_priv->shared_dplls[i];
4004 
4005                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4006                                           GFP_KERNEL);
4007                 if (!pll->new_config)
4008                         goto cleanup;
4009 
4010                 pll->new_config->crtc_mask &= ~clear_pipes;
4011         }
4012 
4013         return 0;
4014 
4015 cleanup:
4016         while (--i >= 0) {
4017                 pll = &dev_priv->shared_dplls[i];
4018                 kfree(pll->new_config);
4019                 pll->new_config = NULL;
4020         }
4021 
4022         return -ENOMEM;
4023 }
4024 
4025 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4026 {
4027         struct intel_shared_dpll *pll;
4028         enum intel_dpll_id i;
4029 
4030         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4031                 pll = &dev_priv->shared_dplls[i];
4032 
4033                 WARN_ON(pll->new_config == &pll->config);
4034 
4035                 pll->config = *pll->new_config;
4036                 kfree(pll->new_config);
4037                 pll->new_config = NULL;
4038         }
4039 }
4040 
4041 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4042 {
4043         struct intel_shared_dpll *pll;
4044         enum intel_dpll_id i;
4045 
4046         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4047                 pll = &dev_priv->shared_dplls[i];
4048 
4049                 WARN_ON(pll->new_config == &pll->config);
4050 
4051                 kfree(pll->new_config);
4052                 pll->new_config = NULL;
4053         }
4054 }
4055 
4056 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4057 {
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059         int dslreg = PIPEDSL(pipe);
4060         u32 temp;
4061 
4062         temp = I915_READ(dslreg);
4063         udelay(500);
4064         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4065                 if (wait_for(I915_READ(dslreg) != temp, 5))
4066                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4067         }
4068 }
4069 
4070 static void skylake_pfit_enable(struct intel_crtc *crtc)
4071 {
4072         struct drm_device *dev = crtc->base.dev;
4073         struct drm_i915_private *dev_priv = dev->dev_private;
4074         int pipe = crtc->pipe;
4075 
4076         if (crtc->config.pch_pfit.enabled) {
4077                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4078                 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4079                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4080         }
4081 }
4082 
4083 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->base.dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         int pipe = crtc->pipe;
4088 
4089         if (crtc->config.pch_pfit.enabled) {
4090                 /* Force use of hard-coded filter coefficients
4091                  * as some pre-programmed values are broken,
4092                  * e.g. x201.
4093                  */
4094                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4095                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4096                                                  PF_PIPE_SEL_IVB(pipe));
4097                 else
4098                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4099                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4100                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4101         }
4102 }
4103 
4104 static void intel_enable_planes(struct drm_crtc *crtc)
4105 {
4106         struct drm_device *dev = crtc->dev;
4107         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4108         struct drm_plane *plane;
4109         struct intel_plane *intel_plane;
4110 
4111         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4112                 intel_plane = to_intel_plane(plane);
4113                 if (intel_plane->pipe == pipe)
4114                         intel_plane_restore(&intel_plane->base);
4115         }
4116 }
4117 
4118 static void intel_disable_planes(struct drm_crtc *crtc)
4119 {
4120         struct drm_device *dev = crtc->dev;
4121         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4122         struct drm_plane *plane;
4123         struct intel_plane *intel_plane;
4124 
4125         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4126                 intel_plane = to_intel_plane(plane);
4127                 if (intel_plane->pipe == pipe)
4128                         intel_plane_disable(&intel_plane->base);
4129         }
4130 }
4131 
4132 void hsw_enable_ips(struct intel_crtc *crtc)
4133 {
4134         struct drm_device *dev = crtc->base.dev;
4135         struct drm_i915_private *dev_priv = dev->dev_private;
4136 
4137         if (!crtc->config.ips_enabled)
4138                 return;
4139 
4140         /* We can only enable IPS after we enable a plane and wait for a vblank */
4141         intel_wait_for_vblank(dev, crtc->pipe);
4142 
4143         assert_plane_enabled(dev_priv, crtc->plane);
4144         if (IS_BROADWELL(dev)) {
4145                 mutex_lock(&dev_priv->rps.hw_lock);
4146                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4147                 mutex_unlock(&dev_priv->rps.hw_lock);
4148                 /* Quoting Art Runyan: "its not safe to expect any particular
4149                  * value in IPS_CTL bit 31 after enabling IPS through the
4150                  * mailbox." Moreover, the mailbox may return a bogus state,
4151                  * so we need to just enable it and continue on.
4152                  */
4153         } else {
4154                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4155                 /* The bit only becomes 1 in the next vblank, so this wait here
4156                  * is essentially intel_wait_for_vblank. If we don't have this
4157                  * and don't wait for vblanks until the end of crtc_enable, then
4158                  * the HW state readout code will complain that the expected
4159                  * IPS_CTL value is not the one we read. */
4160                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4161                         DRM_ERROR("Timed out waiting for IPS enable\n");
4162         }
4163 }
4164 
4165 void hsw_disable_ips(struct intel_crtc *crtc)
4166 {
4167         struct drm_device *dev = crtc->base.dev;
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169 
4170         if (!crtc->config.ips_enabled)
4171                 return;
4172 
4173         assert_plane_enabled(dev_priv, crtc->plane);
4174         if (IS_BROADWELL(dev)) {
4175                 mutex_lock(&dev_priv->rps.hw_lock);
4176                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4177                 mutex_unlock(&dev_priv->rps.hw_lock);
4178                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4179                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4180                         DRM_ERROR("Timed out waiting for IPS disable\n");
4181         } else {
4182                 I915_WRITE(IPS_CTL, 0);
4183                 POSTING_READ(IPS_CTL);
4184         }
4185 
4186         /* We need to wait for a vblank before we can disable the plane. */
4187         intel_wait_for_vblank(dev, crtc->pipe);
4188 }
4189 
4190 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4191 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4192 {
4193         struct drm_device *dev = crtc->dev;
4194         struct drm_i915_private *dev_priv = dev->dev_private;
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         enum pipe pipe = intel_crtc->pipe;
4197         int palreg = PALETTE(pipe);
4198         int i;
4199         bool reenable_ips = false;
4200 
4201         /* The clocks have to be on to load the palette. */
4202         if (!crtc->enabled || !intel_crtc->active)
4203                 return;
4204 
4205         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4206                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4207                         assert_dsi_pll_enabled(dev_priv);
4208                 else
4209                         assert_pll_enabled(dev_priv, pipe);
4210         }
4211 
4212         /* use legacy palette for Ironlake */
4213         if (!HAS_GMCH_DISPLAY(dev))
4214                 palreg = LGC_PALETTE(pipe);
4215 
4216         /* Workaround : Do not read or write the pipe palette/gamma data while
4217          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4218          */
4219         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4220             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4221              GAMMA_MODE_MODE_SPLIT)) {
4222                 hsw_disable_ips(intel_crtc);
4223                 reenable_ips = true;
4224         }
4225 
4226         for (i = 0; i < 256; i++) {
4227                 I915_WRITE(palreg + 4 * i,
4228                            (intel_crtc->lut_r[i] << 16) |
4229                            (intel_crtc->lut_g[i] << 8) |
4230                            intel_crtc->lut_b[i]);
4231         }
4232 
4233         if (reenable_ips)
4234                 hsw_enable_ips(intel_crtc);
4235 }
4236 
4237 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4238 {
4239         if (!enable && intel_crtc->overlay) {
4240                 struct drm_device *dev = intel_crtc->base.dev;
4241                 struct drm_i915_private *dev_priv = dev->dev_private;
4242 
4243                 mutex_lock(&dev->struct_mutex);
4244                 dev_priv->mm.interruptible = false;
4245                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4246                 dev_priv->mm.interruptible = true;
4247                 mutex_unlock(&dev->struct_mutex);
4248         }
4249 
4250         /* Let userspace switch the overlay on again. In most cases userspace
4251          * has to recompute where to put it anyway.
4252          */
4253 }
4254 
4255 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4256 {
4257         struct drm_device *dev = crtc->dev;
4258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259         int pipe = intel_crtc->pipe;
4260 
4261         intel_enable_primary_hw_plane(crtc->primary, crtc);
4262         intel_enable_planes(crtc);
4263         intel_crtc_update_cursor(crtc, true);
4264         intel_crtc_dpms_overlay(intel_crtc, true);
4265 
4266         hsw_enable_ips(intel_crtc);
4267 
4268         mutex_lock(&dev->struct_mutex);
4269         intel_update_fbc(dev);
4270         mutex_unlock(&dev->struct_mutex);
4271 
4272         /*
4273          * FIXME: Once we grow proper nuclear flip support out of this we need
4274          * to compute the mask of flip planes precisely. For the time being
4275          * consider this a flip from a NULL plane.
4276          */
4277         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4278 }
4279 
4280 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285         int pipe = intel_crtc->pipe;
4286         int plane = intel_crtc->plane;
4287 
4288         intel_crtc_wait_for_pending_flips(crtc);
4289 
4290         if (dev_priv->fbc.plane == plane)
4291                 intel_disable_fbc(dev);
4292 
4293         hsw_disable_ips(intel_crtc);
4294 
4295         intel_crtc_dpms_overlay(intel_crtc, false);
4296         intel_crtc_update_cursor(crtc, false);
4297         intel_disable_planes(crtc);
4298         intel_disable_primary_hw_plane(crtc->primary, crtc);
4299 
4300         /*
4301          * FIXME: Once we grow proper nuclear flip support out of this we need
4302          * to compute the mask of flip planes precisely. For the time being
4303          * consider this a flip to a NULL plane.
4304          */
4305         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4306 }
4307 
4308 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4309 {
4310         struct drm_device *dev = crtc->dev;
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313         struct intel_encoder *encoder;
4314         int pipe = intel_crtc->pipe;
4315 
4316         WARN_ON(!crtc->enabled);
4317 
4318         if (intel_crtc->active)
4319                 return;
4320 
4321         if (intel_crtc->config.has_pch_encoder)
4322                 intel_prepare_shared_dpll(intel_crtc);
4323 
4324         if (intel_crtc->config.has_dp_encoder)
4325                 intel_dp_set_m_n(intel_crtc);
4326 
4327         intel_set_pipe_timings(intel_crtc);
4328 
4329         if (intel_crtc->config.has_pch_encoder) {
4330                 intel_cpu_transcoder_set_m_n(intel_crtc,
4331                                      &intel_crtc->config.fdi_m_n, NULL);
4332         }
4333 
4334         ironlake_set_pipeconf(crtc);
4335 
4336         intel_crtc->active = true;
4337 
4338         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4339         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4340 
4341         for_each_encoder_on_crtc(dev, crtc, encoder)
4342                 if (encoder->pre_enable)
4343                         encoder->pre_enable(encoder);
4344 
4345         if (intel_crtc->config.has_pch_encoder) {
4346                 /* Note: FDI PLL enabling _must_ be done before we enable the
4347                  * cpu pipes, hence this is separate from all the other fdi/pch
4348                  * enabling. */
4349                 ironlake_fdi_pll_enable(intel_crtc);
4350         } else {
4351                 assert_fdi_tx_disabled(dev_priv, pipe);
4352                 assert_fdi_rx_disabled(dev_priv, pipe);
4353         }
4354 
4355         ironlake_pfit_enable(intel_crtc);
4356 
4357         /*
4358          * On ILK+ LUT must be loaded before the pipe is running but with
4359          * clocks enabled
4360          */
4361         intel_crtc_load_lut(crtc);
4362 
4363         intel_update_watermarks(crtc);
4364         intel_enable_pipe(intel_crtc);
4365 
4366         if (intel_crtc->config.has_pch_encoder)
4367                 ironlake_pch_enable(crtc);
4368 
4369         for_each_encoder_on_crtc(dev, crtc, encoder)
4370                 encoder->enable(encoder);
4371 
4372         if (HAS_PCH_CPT(dev))
4373                 cpt_verify_modeset(dev, intel_crtc->pipe);
4374 
4375         assert_vblank_disabled(crtc);
4376         drm_crtc_vblank_on(crtc);
4377 
4378         intel_crtc_enable_planes(crtc);
4379 }
4380 
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4383 {
4384         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4385 }
4386 
4387 /*
4388  * This implements the workaround described in the "notes" section of the mode
4389  * set sequence documentation. When going from no pipes or single pipe to
4390  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4392  */
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4394 {
4395         struct drm_device *dev = crtc->base.dev;
4396         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4397 
4398         /* We want to get the other_active_crtc only if there's only 1 other
4399          * active crtc. */
4400         for_each_intel_crtc(dev, crtc_it) {
4401                 if (!crtc_it->active || crtc_it == crtc)
4402                         continue;
4403 
4404                 if (other_active_crtc)
4405                         return;
4406 
4407                 other_active_crtc = crtc_it;
4408         }
4409         if (!other_active_crtc)
4410                 return;
4411 
4412         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4414 }
4415 
4416 static void haswell_crtc_enable(struct drm_crtc *crtc)
4417 {
4418         struct drm_device *dev = crtc->dev;
4419         struct drm_i915_private *dev_priv = dev->dev_private;
4420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421         struct intel_encoder *encoder;
4422         int pipe = intel_crtc->pipe;
4423 
4424         WARN_ON(!crtc->enabled);
4425 
4426         if (intel_crtc->active)
4427                 return;
4428 
4429         if (intel_crtc_to_shared_dpll(intel_crtc))
4430                 intel_enable_shared_dpll(intel_crtc);
4431 
4432         if (intel_crtc->config.has_dp_encoder)
4433                 intel_dp_set_m_n(intel_crtc);
4434 
4435         intel_set_pipe_timings(intel_crtc);
4436 
4437         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4438                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4439                            intel_crtc->config.pixel_multiplier - 1);
4440         }
4441 
4442         if (intel_crtc->config.has_pch_encoder) {
4443                 intel_cpu_transcoder_set_m_n(intel_crtc,
4444                                      &intel_crtc->config.fdi_m_n, NULL);
4445         }
4446 
4447         haswell_set_pipeconf(crtc);
4448 
4449         intel_set_pipe_csc(crtc);
4450 
4451         intel_crtc->active = true;
4452 
4453         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4454         for_each_encoder_on_crtc(dev, crtc, encoder)
4455                 if (encoder->pre_enable)
4456                         encoder->pre_enable(encoder);
4457 
4458         if (intel_crtc->config.has_pch_encoder) {
4459                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4460                                                       true);
4461                 dev_priv->display.fdi_link_train(crtc);
4462         }
4463 
4464         intel_ddi_enable_pipe_clock(intel_crtc);
4465 
4466         if (IS_SKYLAKE(dev))
4467                 skylake_pfit_enable(intel_crtc);
4468         else
4469                 ironlake_pfit_enable(intel_crtc);
4470 
4471         /*
4472          * On ILK+ LUT must be loaded before the pipe is running but with
4473          * clocks enabled
4474          */
4475         intel_crtc_load_lut(crtc);
4476 
4477         intel_ddi_set_pipe_settings(crtc);
4478         intel_ddi_enable_transcoder_func(crtc);
4479 
4480         intel_update_watermarks(crtc);
4481         intel_enable_pipe(intel_crtc);
4482 
4483         if (intel_crtc->config.has_pch_encoder)
4484                 lpt_pch_enable(crtc);
4485 
4486         if (intel_crtc->config.dp_encoder_is_mst)
4487                 intel_ddi_set_vc_payload_alloc(crtc, true);
4488 
4489         for_each_encoder_on_crtc(dev, crtc, encoder) {
4490                 encoder->enable(encoder);
4491                 intel_opregion_notify_encoder(encoder, true);
4492         }
4493 
4494         assert_vblank_disabled(crtc);
4495         drm_crtc_vblank_on(crtc);
4496 
4497         /* If we change the relative order between pipe/planes enabling, we need
4498          * to change the workaround. */
4499         haswell_mode_set_planes_workaround(intel_crtc);
4500         intel_crtc_enable_planes(crtc);
4501 }
4502 
4503 static void skylake_pfit_disable(struct intel_crtc *crtc)
4504 {
4505         struct drm_device *dev = crtc->base.dev;
4506         struct drm_i915_private *dev_priv = dev->dev_private;
4507         int pipe = crtc->pipe;
4508 
4509         /* To avoid upsetting the power well on haswell only disable the pfit if
4510          * it's in use. The hw state code will make sure we get this right. */
4511         if (crtc->config.pch_pfit.enabled) {
4512                 I915_WRITE(PS_CTL(pipe), 0);
4513                 I915_WRITE(PS_WIN_POS(pipe), 0);
4514                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4515         }
4516 }
4517 
4518 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4519 {
4520         struct drm_device *dev = crtc->base.dev;
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522         int pipe = crtc->pipe;
4523 
4524         /* To avoid upsetting the power well on haswell only disable the pfit if
4525          * it's in use. The hw state code will make sure we get this right. */
4526         if (crtc->config.pch_pfit.enabled) {
4527                 I915_WRITE(PF_CTL(pipe), 0);
4528                 I915_WRITE(PF_WIN_POS(pipe), 0);
4529                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4530         }
4531 }
4532 
4533 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4534 {
4535         struct drm_device *dev = crtc->dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538         struct intel_encoder *encoder;
4539         int pipe = intel_crtc->pipe;
4540         u32 reg, temp;
4541 
4542         if (!intel_crtc->active)
4543                 return;
4544 
4545         intel_crtc_disable_planes(crtc);
4546 
4547         drm_crtc_vblank_off(crtc);
4548         assert_vblank_disabled(crtc);
4549 
4550         for_each_encoder_on_crtc(dev, crtc, encoder)
4551                 encoder->disable(encoder);
4552 
4553         if (intel_crtc->config.has_pch_encoder)
4554                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4555 
4556         intel_disable_pipe(intel_crtc);
4557 
4558         ironlake_pfit_disable(intel_crtc);
4559 
4560         for_each_encoder_on_crtc(dev, crtc, encoder)
4561                 if (encoder->post_disable)
4562                         encoder->post_disable(encoder);
4563 
4564         if (intel_crtc->config.has_pch_encoder) {
4565                 ironlake_fdi_disable(crtc);
4566 
4567                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4568 
4569                 if (HAS_PCH_CPT(dev)) {
4570                         /* disable TRANS_DP_CTL */
4571                         reg = TRANS_DP_CTL(pipe);
4572                         temp = I915_READ(reg);
4573                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4574                                   TRANS_DP_PORT_SEL_MASK);
4575                         temp |= TRANS_DP_PORT_SEL_NONE;
4576                         I915_WRITE(reg, temp);
4577 
4578                         /* disable DPLL_SEL */
4579                         temp = I915_READ(PCH_DPLL_SEL);
4580                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4581                         I915_WRITE(PCH_DPLL_SEL, temp);
4582                 }
4583 
4584                 /* disable PCH DPLL */
4585                 intel_disable_shared_dpll(intel_crtc);
4586 
4587                 ironlake_fdi_pll_disable(intel_crtc);
4588         }
4589 
4590         intel_crtc->active = false;
4591         intel_update_watermarks(crtc);
4592 
4593         mutex_lock(&dev->struct_mutex);
4594         intel_update_fbc(dev);
4595         mutex_unlock(&dev->struct_mutex);
4596 }
4597 
4598 static void haswell_crtc_disable(struct drm_crtc *crtc)
4599 {
4600         struct drm_device *dev = crtc->dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4603         struct intel_encoder *encoder;
4604         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4605 
4606         if (!intel_crtc->active)
4607                 return;
4608 
4609         intel_crtc_disable_planes(crtc);
4610 
4611         drm_crtc_vblank_off(crtc);
4612         assert_vblank_disabled(crtc);
4613 
4614         for_each_encoder_on_crtc(dev, crtc, encoder) {
4615                 intel_opregion_notify_encoder(encoder, false);
4616                 encoder->disable(encoder);
4617         }
4618 
4619         if (intel_crtc->config.has_pch_encoder)
4620                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4621                                                       false);
4622         intel_disable_pipe(intel_crtc);
4623 
4624         if (intel_crtc->config.dp_encoder_is_mst)
4625                 intel_ddi_set_vc_payload_alloc(crtc, false);
4626 
4627         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4628 
4629         if (IS_SKYLAKE(dev))
4630                 skylake_pfit_disable(intel_crtc);
4631         else
4632                 ironlake_pfit_disable(intel_crtc);
4633 
4634         intel_ddi_disable_pipe_clock(intel_crtc);
4635 
4636         if (intel_crtc->config.has_pch_encoder) {
4637                 lpt_disable_pch_transcoder(dev_priv);
4638                 intel_ddi_fdi_disable(crtc);
4639         }
4640 
4641         for_each_encoder_on_crtc(dev, crtc, encoder)
4642                 if (encoder->post_disable)
4643                         encoder->post_disable(encoder);
4644 
4645         intel_crtc->active = false;
4646         intel_update_watermarks(crtc);
4647 
4648         mutex_lock(&dev->struct_mutex);
4649         intel_update_fbc(dev);
4650         mutex_unlock(&dev->struct_mutex);
4651 
4652         if (intel_crtc_to_shared_dpll(intel_crtc))
4653                 intel_disable_shared_dpll(intel_crtc);
4654 }
4655 
4656 static void ironlake_crtc_off(struct drm_crtc *crtc)
4657 {
4658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659         intel_put_shared_dpll(intel_crtc);
4660 }
4661 
4662 
4663 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4664 {
4665         struct drm_device *dev = crtc->base.dev;
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         struct intel_crtc_config *pipe_config = &crtc->config;
4668 
4669         if (!crtc->config.gmch_pfit.control)
4670                 return;
4671 
4672         /*
4673          * The panel fitter should only be adjusted whilst the pipe is disabled,
4674          * according to register description and PRM.
4675          */
4676         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4677         assert_pipe_disabled(dev_priv, crtc->pipe);
4678 
4679         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4680         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4681 
4682         /* Border color in case we don't scale up to the full screen. Black by
4683          * default, change to something else for debugging. */
4684         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4685 }
4686 
4687 static enum intel_display_power_domain port_to_power_domain(enum port port)
4688 {
4689         switch (port) {
4690         case PORT_A:
4691                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4692         case PORT_B:
4693                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4694         case PORT_C:
4695                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4696         case PORT_D:
4697                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4698         default:
4699                 WARN_ON_ONCE(1);
4700                 return POWER_DOMAIN_PORT_OTHER;
4701         }
4702 }
4703 
4704 #define for_each_power_domain(domain, mask)                             \
4705         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4706                 if ((1 << (domain)) & (mask))
4707 
4708 enum intel_display_power_domain
4709 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4710 {
4711         struct drm_device *dev = intel_encoder->base.dev;
4712         struct intel_digital_port *intel_dig_port;
4713 
4714         switch (intel_encoder->type) {
4715         case INTEL_OUTPUT_UNKNOWN:
4716                 /* Only DDI platforms should ever use this output type */
4717                 WARN_ON_ONCE(!HAS_DDI(dev));
4718         case INTEL_OUTPUT_DISPLAYPORT:
4719         case INTEL_OUTPUT_HDMI:
4720         case INTEL_OUTPUT_EDP:
4721                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4722                 return port_to_power_domain(intel_dig_port->port);
4723         case INTEL_OUTPUT_DP_MST:
4724                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4725                 return port_to_power_domain(intel_dig_port->port);
4726         case INTEL_OUTPUT_ANALOG:
4727                 return POWER_DOMAIN_PORT_CRT;
4728         case INTEL_OUTPUT_DSI:
4729                 return POWER_DOMAIN_PORT_DSI;
4730         default:
4731                 return POWER_DOMAIN_PORT_OTHER;
4732         }
4733 }
4734 
4735 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4736 {
4737         struct drm_device *dev = crtc->dev;
4738         struct intel_encoder *intel_encoder;
4739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740         enum pipe pipe = intel_crtc->pipe;
4741         unsigned long mask;
4742         enum transcoder transcoder;
4743 
4744         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4745 
4746         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4747         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4748         if (intel_crtc->config.pch_pfit.enabled ||
4749             intel_crtc->config.pch_pfit.force_thru)
4750                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4751 
4752         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4753                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4754 
4755         return mask;
4756 }
4757 
4758 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4759 {
4760         struct drm_i915_private *dev_priv = dev->dev_private;
4761         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4762         struct intel_crtc *crtc;
4763 
4764         /*
4765          * First get all needed power domains, then put all unneeded, to avoid
4766          * any unnecessary toggling of the power wells.
4767          */
4768         for_each_intel_crtc(dev, crtc) {
4769                 enum intel_display_power_domain domain;
4770 
4771                 if (!crtc->base.enabled)
4772                         continue;
4773 
4774                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4775 
4776                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4777                         intel_display_power_get(dev_priv, domain);
4778         }
4779 
4780         if (dev_priv->display.modeset_global_resources)
4781                 dev_priv->display.modeset_global_resources(dev);
4782 
4783         for_each_intel_crtc(dev, crtc) {
4784                 enum intel_display_power_domain domain;
4785 
4786                 for_each_power_domain(domain, crtc->enabled_power_domains)
4787                         intel_display_power_put(dev_priv, domain);
4788 
4789                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4790         }
4791 
4792         intel_display_set_init_power(dev_priv, false);
4793 }
4794 
4795 /* returns HPLL frequency in kHz */
4796 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4797 {
4798         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4799 
4800         /* Obtain SKU information */
4801         mutex_lock(&dev_priv->dpio_lock);
4802         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4803                 CCK_FUSE_HPLL_FREQ_MASK;
4804         mutex_unlock(&dev_priv->dpio_lock);
4805 
4806         return vco_freq[hpll_freq] * 1000;
4807 }
4808 
4809 static void vlv_update_cdclk(struct drm_device *dev)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812 
4813         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4814         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4815                          dev_priv->vlv_cdclk_freq);
4816 
4817         /*
4818          * Program the gmbus_freq based on the cdclk frequency.
4819          * BSpec erroneously claims we should aim for 4MHz, but
4820          * in fact 1MHz is the correct frequency.
4821          */
4822         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4823 }
4824 
4825 /* Adjust CDclk dividers to allow high res or save power if possible */
4826 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4827 {
4828         struct drm_i915_private *dev_priv = dev->dev_private;
4829         u32 val, cmd;
4830 
4831         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4832 
4833         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4834                 cmd = 2;
4835         else if (cdclk == 266667)
4836                 cmd = 1;
4837         else
4838                 cmd = 0;
4839 
4840         mutex_lock(&dev_priv->rps.hw_lock);
4841         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4842         val &= ~DSPFREQGUAR_MASK;
4843         val |= (cmd << DSPFREQGUAR_SHIFT);
4844         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4845         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4846                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4847                      50)) {
4848                 DRM_ERROR("timed out waiting for CDclk change\n");
4849         }
4850         mutex_unlock(&dev_priv->rps.hw_lock);
4851 
4852         if (cdclk == 400000) {
4853                 u32 divider;
4854 
4855                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4856 
4857                 mutex_lock(&dev_priv->dpio_lock);
4858                 /* adjust cdclk divider */
4859                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4860                 val &= ~DISPLAY_FREQUENCY_VALUES;
4861                 val |= divider;
4862                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4863 
4864                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4865                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4866                              50))
4867                         DRM_ERROR("timed out waiting for CDclk change\n");
4868                 mutex_unlock(&dev_priv->dpio_lock);
4869         }
4870 
4871         mutex_lock(&dev_priv->dpio_lock);
4872         /* adjust self-refresh exit latency value */
4873         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4874         val &= ~0x7f;
4875 
4876         /*
4877          * For high bandwidth configs, we set a higher latency in the bunit
4878          * so that the core display fetch happens in time to avoid underruns.
4879          */
4880         if (cdclk == 400000)
4881                 val |= 4500 / 250; /* 4.5 usec */
4882         else
4883                 val |= 3000 / 250; /* 3.0 usec */
4884         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4885         mutex_unlock(&dev_priv->dpio_lock);
4886 
4887         vlv_update_cdclk(dev);
4888 }
4889 
4890 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4891 {
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893         u32 val, cmd;
4894 
4895         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4896 
4897         switch (cdclk) {
4898         case 400000:
4899                 cmd = 3;
4900                 break;
4901         case 333333:
4902         case 320000:
4903                 cmd = 2;
4904                 break;
4905         case 266667:
4906                 cmd = 1;
4907                 break;
4908         case 200000:
4909                 cmd = 0;
4910                 break;
4911         default:
4912                 WARN_ON(1);
4913                 return;
4914         }
4915 
4916         mutex_lock(&dev_priv->rps.hw_lock);
4917         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4918         val &= ~DSPFREQGUAR_MASK_CHV;
4919         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4920         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4921         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4922                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4923                      50)) {
4924                 DRM_ERROR("timed out waiting for CDclk change\n");
4925         }
4926         mutex_unlock(&dev_priv->rps.hw_lock);
4927 
4928         vlv_update_cdclk(dev);
4929 }
4930 
4931 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4932                                  int max_pixclk)
4933 {
4934         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4935 
4936         /* FIXME: Punit isn't quite ready yet */
4937         if (IS_CHERRYVIEW(dev_priv->dev))
4938                 return 400000;
4939 
4940         /*
4941          * Really only a few cases to deal with, as only 4 CDclks are supported:
4942          *   200MHz
4943          *   267MHz
4944          *   320/333MHz (depends on HPLL freq)
4945          *   400MHz
4946          * So we check to see whether we're above 90% of the lower bin and
4947          * adjust if needed.
4948          *
4949          * We seem to get an unstable or solid color picture at 200MHz.
4950          * Not sure what's wrong. For now use 200MHz only when all pipes
4951          * are off.
4952          */
4953         if (max_pixclk > freq_320*9/10)
4954                 return 400000;
4955         else if (max_pixclk > 266667*9/10)
4956                 return freq_320;
4957         else if (max_pixclk > 0)
4958                 return 266667;
4959         else
4960                 return 200000;
4961 }
4962 
4963 /* compute the max pixel clock for new configuration */
4964 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4965 {
4966         struct drm_device *dev = dev_priv->dev;
4967         struct intel_crtc *intel_crtc;
4968         int max_pixclk = 0;
4969 
4970         for_each_intel_crtc(dev, intel_crtc) {
4971                 if (intel_crtc->new_enabled)
4972                         max_pixclk = max(max_pixclk,
4973                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4974         }
4975 
4976         return max_pixclk;
4977 }
4978 
4979 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4980                                             unsigned *prepare_pipes)
4981 {
4982         struct drm_i915_private *dev_priv = dev->dev_private;
4983         struct intel_crtc *intel_crtc;
4984         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4985 
4986         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4987             dev_priv->vlv_cdclk_freq)
4988                 return;
4989 
4990         /* disable/enable all currently active pipes while we change cdclk */
4991         for_each_intel_crtc(dev, intel_crtc)
4992                 if (intel_crtc->base.enabled)
4993                         *prepare_pipes |= (1 << intel_crtc->pipe);
4994 }
4995 
4996 static void valleyview_modeset_global_resources(struct drm_device *dev)
4997 {
4998         struct drm_i915_private *dev_priv = dev->dev_private;
4999         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5000         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5001 
5002         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5003                 /*
5004                  * FIXME: We can end up here with all power domains off, yet
5005                  * with a CDCLK frequency other than the minimum. To account
5006                  * for this take the PIPE-A power domain, which covers the HW
5007                  * blocks needed for the following programming. This can be
5008                  * removed once it's guaranteed that we get here either with
5009                  * the minimum CDCLK set, or the required power domains
5010                  * enabled.
5011                  */
5012                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5013 
5014                 if (IS_CHERRYVIEW(dev))
5015                         cherryview_set_cdclk(dev, req_cdclk);
5016                 else
5017                         valleyview_set_cdclk(dev, req_cdclk);
5018 
5019                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5020         }
5021 }
5022 
5023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = to_i915(dev);
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         struct intel_encoder *encoder;
5029         int pipe = intel_crtc->pipe;
5030         bool is_dsi;
5031 
5032         WARN_ON(!crtc->enabled);
5033 
5034         if (intel_crtc->active)
5035                 return;
5036 
5037         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5038 
5039         if (!is_dsi) {
5040                 if (IS_CHERRYVIEW(dev))
5041                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
5042                 else
5043                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
5044         }
5045 
5046         if (intel_crtc->config.has_dp_encoder)
5047                 intel_dp_set_m_n(intel_crtc);
5048 
5049         intel_set_pipe_timings(intel_crtc);
5050 
5051         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5052                 struct drm_i915_private *dev_priv = dev->dev_private;
5053 
5054                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5055                 I915_WRITE(CHV_CANVAS(pipe), 0);
5056         }
5057 
5058         i9xx_set_pipeconf(intel_crtc);
5059 
5060         intel_crtc->active = true;
5061 
5062         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5063 
5064         for_each_encoder_on_crtc(dev, crtc, encoder)
5065                 if (encoder->pre_pll_enable)
5066                         encoder->pre_pll_enable(encoder);
5067 
5068         if (!is_dsi) {
5069                 if (IS_CHERRYVIEW(dev))
5070                         chv_enable_pll(intel_crtc, &intel_crtc->config);
5071                 else
5072                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
5073         }
5074 
5075         for_each_encoder_on_crtc(dev, crtc, encoder)
5076                 if (encoder->pre_enable)
5077                         encoder->pre_enable(encoder);
5078 
5079         i9xx_pfit_enable(intel_crtc);
5080 
5081         intel_crtc_load_lut(crtc);
5082 
5083         intel_update_watermarks(crtc);
5084         intel_enable_pipe(intel_crtc);
5085 
5086         for_each_encoder_on_crtc(dev, crtc, encoder)
5087                 encoder->enable(encoder);
5088 
5089         assert_vblank_disabled(crtc);
5090         drm_crtc_vblank_on(crtc);
5091 
5092         intel_crtc_enable_planes(crtc);
5093 
5094         /* Underruns don't raise interrupts, so check manually. */
5095         i9xx_check_fifo_underruns(dev_priv);
5096 }
5097 
5098 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5099 {
5100         struct drm_device *dev = crtc->base.dev;
5101         struct drm_i915_private *dev_priv = dev->dev_private;
5102 
5103         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5104         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5105 }
5106 
5107 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5108 {
5109         struct drm_device *dev = crtc->dev;
5110         struct drm_i915_private *dev_priv = to_i915(dev);
5111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112         struct intel_encoder *encoder;
5113         int pipe = intel_crtc->pipe;
5114 
5115         WARN_ON(!crtc->enabled);
5116 
5117         if (intel_crtc->active)
5118                 return;
5119 
5120         i9xx_set_pll_dividers(intel_crtc);
5121 
5122         if (intel_crtc->config.has_dp_encoder)
5123                 intel_dp_set_m_n(intel_crtc);
5124 
5125         intel_set_pipe_timings(intel_crtc);
5126 
5127         i9xx_set_pipeconf(intel_crtc);
5128 
5129         intel_crtc->active = true;
5130 
5131         if (!IS_GEN2(dev))
5132                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5133 
5134         for_each_encoder_on_crtc(dev, crtc, encoder)
5135                 if (encoder->pre_enable)
5136                         encoder->pre_enable(encoder);
5137 
5138         i9xx_enable_pll(intel_crtc);
5139 
5140         i9xx_pfit_enable(intel_crtc);
5141 
5142         intel_crtc_load_lut(crtc);
5143 
5144         intel_update_watermarks(crtc);
5145         intel_enable_pipe(intel_crtc);
5146 
5147         for_each_encoder_on_crtc(dev, crtc, encoder)
5148                 encoder->enable(encoder);
5149 
5150         assert_vblank_disabled(crtc);
5151         drm_crtc_vblank_on(crtc);
5152 
5153         intel_crtc_enable_planes(crtc);
5154 
5155         /*
5156          * Gen2 reports pipe underruns whenever all planes are disabled.
5157          * So don't enable underrun reporting before at least some planes
5158          * are enabled.
5159          * FIXME: Need to fix the logic to work when we turn off all planes
5160          * but leave the pipe running.
5161          */
5162         if (IS_GEN2(dev))
5163                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5164 
5165         /* Underruns don't raise interrupts, so check manually. */
5166         i9xx_check_fifo_underruns(dev_priv);
5167 }
5168 
5169 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5170 {
5171         struct drm_device *dev = crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173 
5174         if (!crtc->config.gmch_pfit.control)
5175                 return;
5176 
5177         assert_pipe_disabled(dev_priv, crtc->pipe);
5178 
5179         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5180                          I915_READ(PFIT_CONTROL));
5181         I915_WRITE(PFIT_CONTROL, 0);
5182 }
5183 
5184 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5185 {
5186         struct drm_device *dev = crtc->dev;
5187         struct drm_i915_private *dev_priv = dev->dev_private;
5188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189         struct intel_encoder *encoder;
5190         int pipe = intel_crtc->pipe;
5191 
5192         if (!intel_crtc->active)
5193                 return;
5194 
5195         /*
5196          * Gen2 reports pipe underruns whenever all planes are disabled.
5197          * So diasble underrun reporting before all the planes get disabled.
5198          * FIXME: Need to fix the logic to work when we turn off all planes
5199          * but leave the pipe running.
5200          */
5201         if (IS_GEN2(dev))
5202                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5203 
5204         /*
5205          * Vblank time updates from the shadow to live plane control register
5206          * are blocked if the memory self-refresh mode is active at that
5207          * moment. So to make sure the plane gets truly disabled, disable
5208          * first the self-refresh mode. The self-refresh enable bit in turn
5209          * will be checked/applied by the HW only at the next frame start
5210          * event which is after the vblank start event, so we need to have a
5211          * wait-for-vblank between disabling the plane and the pipe.
5212          */
5213         intel_set_memory_cxsr(dev_priv, false);
5214         intel_crtc_disable_planes(crtc);
5215 
5216         /*
5217          * On gen2 planes are double buffered but the pipe isn't, so we must
5218          * wait for planes to fully turn off before disabling the pipe.
5219          * We also need to wait on all gmch platforms because of the
5220          * self-refresh mode constraint explained above.
5221          */
5222         intel_wait_for_vblank(dev, pipe);
5223 
5224         drm_crtc_vblank_off(crtc);
5225         assert_vblank_disabled(crtc);
5226 
5227         for_each_encoder_on_crtc(dev, crtc, encoder)
5228                 encoder->disable(encoder);
5229 
5230         intel_disable_pipe(intel_crtc);
5231 
5232         i9xx_pfit_disable(intel_crtc);
5233 
5234         for_each_encoder_on_crtc(dev, crtc, encoder)
5235                 if (encoder->post_disable)
5236                         encoder->post_disable(encoder);
5237 
5238         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5239                 if (IS_CHERRYVIEW(dev))
5240                         chv_disable_pll(dev_priv, pipe);
5241                 else if (IS_VALLEYVIEW(dev))
5242                         vlv_disable_pll(dev_priv, pipe);
5243                 else
5244                         i9xx_disable_pll(intel_crtc);
5245         }
5246 
5247         if (!IS_GEN2(dev))
5248                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5249 
5250         intel_crtc->active = false;
5251         intel_update_watermarks(crtc);
5252 
5253         mutex_lock(&dev->struct_mutex);
5254         intel_update_fbc(dev);
5255         mutex_unlock(&dev->struct_mutex);
5256 }
5257 
5258 static void i9xx_crtc_off(struct drm_crtc *crtc)
5259 {
5260 }
5261 
5262 /* Master function to enable/disable CRTC and corresponding power wells */
5263 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5264 {
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268         enum intel_display_power_domain domain;
5269         unsigned long domains;
5270 
5271         if (enable) {
5272                 if (!intel_crtc->active) {
5273                         domains = get_crtc_power_domains(crtc);
5274                         for_each_power_domain(domain, domains)
5275                                 intel_display_power_get(dev_priv, domain);
5276                         intel_crtc->enabled_power_domains = domains;
5277 
5278                         dev_priv->display.crtc_enable(crtc);
5279                 }
5280         } else {
5281                 if (intel_crtc->active) {
5282                         dev_priv->display.crtc_disable(crtc);
5283 
5284                         domains = intel_crtc->enabled_power_domains;
5285                         for_each_power_domain(domain, domains)
5286                                 intel_display_power_put(dev_priv, domain);
5287                         intel_crtc->enabled_power_domains = 0;
5288                 }
5289         }
5290 }
5291 
5292 /**
5293  * Sets the power management mode of the pipe and plane.
5294  */
5295 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5296 {
5297         struct drm_device *dev = crtc->dev;
5298         struct intel_encoder *intel_encoder;
5299         bool enable = false;
5300 
5301         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5302                 enable |= intel_encoder->connectors_active;
5303 
5304         intel_crtc_control(crtc, enable);
5305 }
5306 
5307 static void intel_crtc_disable(struct drm_crtc *crtc)
5308 {
5309         struct drm_device *dev = crtc->dev;
5310         struct drm_connector *connector;
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5313         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5314 
5315         /* crtc should still be enabled when we disable it. */
5316         WARN_ON(!crtc->enabled);
5317 
5318         dev_priv->display.crtc_disable(crtc);
5319         dev_priv->display.off(crtc);
5320 
5321         if (crtc->primary->fb) {
5322                 mutex_lock(&dev->struct_mutex);
5323                 intel_unpin_fb_obj(old_obj);
5324                 i915_gem_track_fb(old_obj, NULL,
5325                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5326                 mutex_unlock(&dev->struct_mutex);
5327                 crtc->primary->fb = NULL;
5328         }
5329 
5330         /* Update computed state. */
5331         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5332                 if (!connector->encoder || !connector->encoder->crtc)
5333                         continue;
5334 
5335                 if (connector->encoder->crtc != crtc)
5336                         continue;
5337 
5338                 connector->dpms = DRM_MODE_DPMS_OFF;
5339                 to_intel_encoder(connector->encoder)->connectors_active = false;
5340         }
5341 }
5342 
5343 void intel_encoder_destroy(struct drm_encoder *encoder)
5344 {
5345         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5346 
5347         drm_encoder_cleanup(encoder);
5348         kfree(intel_encoder);
5349 }
5350 
5351 /* Simple dpms helper for encoders with just one connector, no cloning and only
5352  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5353  * state of the entire output pipe. */
5354 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5355 {
5356         if (mode == DRM_MODE_DPMS_ON) {
5357                 encoder->connectors_active = true;
5358 
5359                 intel_crtc_update_dpms(encoder->base.crtc);
5360         } else {
5361                 encoder->connectors_active = false;
5362 
5363                 intel_crtc_update_dpms(encoder->base.crtc);
5364         }
5365 }
5366 
5367 /* Cross check the actual hw state with our own modeset state tracking (and it's
5368  * internal consistency). */
5369 static void intel_connector_check_state(struct intel_connector *connector)
5370 {
5371         if (connector->get_hw_state(connector)) {
5372                 struct intel_encoder *encoder = connector->encoder;
5373                 struct drm_crtc *crtc;
5374                 bool encoder_enabled;
5375                 enum pipe pipe;
5376 
5377                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5378                               connector->base.base.id,
5379                               connector->base.name);
5380 
5381                 /* there is no real hw state for MST connectors */
5382                 if (connector->mst_port)
5383                         return;
5384 
5385                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5386                      "wrong connector dpms state\n");
5387                 WARN(connector->base.encoder != &encoder->base,
5388                      "active connector not linked to encoder\n");
5389 
5390                 if (encoder) {
5391                         WARN(!encoder->connectors_active,
5392                              "encoder->connectors_active not set\n");
5393 
5394                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5395                         WARN(!encoder_enabled, "encoder not enabled\n");
5396                         if (WARN_ON(!encoder->base.crtc))
5397                                 return;
5398 
5399                         crtc = encoder->base.crtc;
5400 
5401                         WARN(!crtc->enabled, "crtc not enabled\n");
5402                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5403                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5404                              "encoder active on the wrong pipe\n");
5405                 }
5406         }
5407 }
5408 
5409 /* Even simpler default implementation, if there's really no special case to
5410  * consider. */
5411 void intel_connector_dpms(struct drm_connector *connector, int mode)
5412 {
5413         /* All the simple cases only support two dpms states. */
5414         if (mode != DRM_MODE_DPMS_ON)
5415                 mode = DRM_MODE_DPMS_OFF;
5416 
5417         if (mode == connector->dpms)
5418                 return;
5419 
5420         connector->dpms = mode;
5421 
5422         /* Only need to change hw state when actually enabled */
5423         if (connector->encoder)
5424                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5425 
5426         intel_modeset_check_state(connector->dev);
5427 }
5428 
5429 /* Simple connector->get_hw_state implementation for encoders that support only
5430  * one connector and no cloning and hence the encoder state determines the state
5431  * of the connector. */
5432 bool intel_connector_get_hw_state(struct intel_connector *connector)
5433 {
5434         enum pipe pipe = 0;
5435         struct intel_encoder *encoder = connector->encoder;
5436 
5437         return encoder->get_hw_state(encoder, &pipe);
5438 }
5439 
5440 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5441                                      struct intel_crtc_config *pipe_config)
5442 {
5443         struct drm_i915_private *dev_priv = dev->dev_private;
5444         struct intel_crtc *pipe_B_crtc =
5445                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5446 
5447         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5448                       pipe_name(pipe), pipe_config->fdi_lanes);
5449         if (pipe_config->fdi_lanes > 4) {
5450                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5451                               pipe_name(pipe), pipe_config->fdi_lanes);
5452                 return false;
5453         }
5454 
5455         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5456                 if (pipe_config->fdi_lanes > 2) {
5457                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5458                                       pipe_config->fdi_lanes);
5459                         return false;
5460                 } else {
5461                         return true;
5462                 }
5463         }
5464 
5465         if (INTEL_INFO(dev)->num_pipes == 2)
5466                 return true;
5467 
5468         /* Ivybridge 3 pipe is really complicated */
5469         switch (pipe) {
5470         case PIPE_A:
5471                 return true;
5472         case PIPE_B:
5473                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5474                     pipe_config->fdi_lanes > 2) {
5475                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5476                                       pipe_name(pipe), pipe_config->fdi_lanes);
5477                         return false;
5478                 }
5479                 return true;
5480         case PIPE_C:
5481                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5482                     pipe_B_crtc->config.fdi_lanes <= 2) {
5483                         if (pipe_config->fdi_lanes > 2) {
5484                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5485                                               pipe_name(pipe), pipe_config->fdi_lanes);
5486                                 return false;
5487                         }
5488                 } else {
5489                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5490                         return false;
5491                 }
5492                 return true;
5493         default:
5494                 BUG();
5495         }
5496 }
5497 
5498 #define RETRY 1
5499 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5500                                        struct intel_crtc_config *pipe_config)
5501 {
5502         struct drm_device *dev = intel_crtc->base.dev;
5503         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5504         int lane, link_bw, fdi_dotclock;
5505         bool setup_ok, needs_recompute = false;
5506 
5507 retry:
5508         /* FDI is a binary signal running at ~2.7GHz, encoding
5509          * each output octet as 10 bits. The actual frequency
5510          * is stored as a divider into a 100MHz clock, and the
5511          * mode pixel clock is stored in units of 1KHz.
5512          * Hence the bw of each lane in terms of the mode signal
5513          * is:
5514          */
5515         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5516 
5517         fdi_dotclock = adjusted_mode->crtc_clock;
5518 
5519         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5520                                            pipe_config->pipe_bpp);
5521 
5522         pipe_config->fdi_lanes = lane;
5523 
5524         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5525                                link_bw, &pipe_config->fdi_m_n);
5526 
5527         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5528                                             intel_crtc->pipe, pipe_config);
5529         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5530                 pipe_config->pipe_bpp -= 2*3;
5531                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5532                               pipe_config->pipe_bpp);
5533                 needs_recompute = true;
5534                 pipe_config->bw_constrained = true;
5535 
5536                 goto retry;
5537         }
5538 
5539         if (needs_recompute)
5540                 return RETRY;
5541 
5542         return setup_ok ? 0 : -EINVAL;
5543 }
5544 
5545 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5546                                    struct intel_crtc_config *pipe_config)
5547 {
5548         pipe_config->ips_enabled = i915.enable_ips &&
5549                                    hsw_crtc_supports_ips(crtc) &&
5550                                    pipe_config->pipe_bpp <= 24;
5551 }
5552 
5553 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5554                                      struct intel_crtc_config *pipe_config)
5555 {
5556         struct drm_device *dev = crtc->base.dev;
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5559 
5560         /* FIXME should check pixel clock limits on all platforms */
5561         if (INTEL_INFO(dev)->gen < 4) {
5562                 int clock_limit =
5563                         dev_priv->display.get_display_clock_speed(dev);
5564 
5565                 /*
5566                  * Enable pixel doubling when the dot clock
5567                  * is > 90% of the (display) core speed.
5568                  *
5569                  * GDG double wide on either pipe,
5570                  * otherwise pipe A only.
5571                  */
5572                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5573                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5574                         clock_limit *= 2;
5575                         pipe_config->double_wide = true;
5576                 }
5577 
5578                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5579                         return -EINVAL;
5580         }
5581 
5582         /*
5583          * Pipe horizontal size must be even in:
5584          * - DVO ganged mode
5585          * - LVDS dual channel mode
5586          * - Double wide pipe
5587          */
5588         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5589              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5590                 pipe_config->pipe_src_w &= ~1;
5591 
5592         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5593          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5594          */
5595         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5596                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5597                 return -EINVAL;
5598 
5599         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5600                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5601         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5602                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5603                  * for lvds. */
5604                 pipe_config->pipe_bpp = 8*3;
5605         }
5606 
5607         if (HAS_IPS(dev))
5608                 hsw_compute_ips_config(crtc, pipe_config);
5609 
5610         if (pipe_config->has_pch_encoder)
5611                 return ironlake_fdi_compute_config(crtc, pipe_config);
5612 
5613         return 0;
5614 }
5615 
5616 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5617 {
5618         struct drm_i915_private *dev_priv = dev->dev_private;
5619         u32 val;
5620         int divider;
5621 
5622         /* FIXME: Punit isn't quite ready yet */
5623         if (IS_CHERRYVIEW(dev))
5624                 return 400000;
5625 
5626         if (dev_priv->hpll_freq == 0)
5627                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5628 
5629         mutex_lock(&dev_priv->dpio_lock);
5630         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5631         mutex_unlock(&dev_priv->dpio_lock);
5632 
5633         divider = val & DISPLAY_FREQUENCY_VALUES;
5634 
5635         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5636              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5637              "cdclk change in progress\n");
5638 
5639         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5640 }
5641 
5642 static int i945_get_display_clock_speed(struct drm_device *dev)
5643 {
5644         return 400000;
5645 }
5646 
5647 static int i915_get_display_clock_speed(struct drm_device *dev)
5648 {
5649         return 333000;
5650 }
5651 
5652 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5653 {
5654         return 200000;
5655 }
5656 
5657 static int pnv_get_display_clock_speed(struct drm_device *dev)
5658 {
5659         u16 gcfgc = 0;
5660 
5661         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5662 
5663         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5664         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5665                 return 267000;
5666         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5667                 return 333000;
5668         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5669                 return 444000;
5670         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5671                 return 200000;
5672         default:
5673                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5674         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5675                 return 133000;
5676         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5677                 return 167000;
5678         }
5679 }
5680 
5681 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5682 {
5683         u16 gcfgc = 0;
5684 
5685         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5686 
5687         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5688                 return 133000;
5689         else {
5690                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5691                 case GC_DISPLAY_CLOCK_333_MHZ:
5692                         return 333000;
5693                 default:
5694                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5695                         return 190000;
5696                 }
5697         }
5698 }
5699 
5700 static int i865_get_display_clock_speed(struct drm_device *dev)
5701 {
5702         return 266000;
5703 }
5704 
5705 static int i855_get_display_clock_speed(struct drm_device *dev)
5706 {
5707         u16 hpllcc = 0;
5708         /* Assume that the hardware is in the high speed state.  This
5709          * should be the default.
5710          */
5711         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5712         case GC_CLOCK_133_200:
5713         case GC_CLOCK_100_200:
5714                 return 200000;
5715         case GC_CLOCK_166_250:
5716                 return 250000;
5717         case GC_CLOCK_100_133:
5718                 return 133000;
5719         }
5720 
5721         /* Shouldn't happen */
5722         return 0;
5723 }
5724 
5725 static int i830_get_display_clock_speed(struct drm_device *dev)
5726 {
5727         return 133000;
5728 }
5729 
5730 static void
5731 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5732 {
5733         while (*num > DATA_LINK_M_N_MASK ||
5734                *den > DATA_LINK_M_N_MASK) {
5735                 *num >>= 1;
5736                 *den >>= 1;
5737         }
5738 }
5739 
5740 static void compute_m_n(unsigned int m, unsigned int n,
5741                         uint32_t *ret_m, uint32_t *ret_n)
5742 {
5743         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5744         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5745         intel_reduce_m_n_ratio(ret_m, ret_n);
5746 }
5747 
5748 void
5749 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5750                        int pixel_clock, int link_clock,
5751                        struct intel_link_m_n *m_n)
5752 {
5753         m_n->tu = 64;
5754 
5755         compute_m_n(bits_per_pixel * pixel_clock,
5756                     link_clock * nlanes * 8,
5757                     &m_n->gmch_m, &m_n->gmch_n);
5758 
5759         compute_m_n(pixel_clock, link_clock,
5760                     &m_n->link_m, &m_n->link_n);
5761 }
5762 
5763 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5764 {
5765         if (i915.panel_use_ssc >= 0)
5766                 return i915.panel_use_ssc != 0;
5767         return dev_priv->vbt.lvds_use_ssc
5768                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5769 }
5770 
5771 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5772 {
5773         struct drm_device *dev = crtc->base.dev;
5774         struct drm_i915_private *dev_priv = dev->dev_private;
5775         int refclk;
5776 
5777         if (IS_VALLEYVIEW(dev)) {
5778                 refclk = 100000;
5779         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5780             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5781                 refclk = dev_priv->vbt.lvds_ssc_freq;
5782                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5783         } else if (!IS_GEN2(dev)) {
5784                 refclk = 96000;
5785         } else {
5786                 refclk = 48000;
5787         }
5788 
5789         return refclk;
5790 }
5791 
5792 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5793 {
5794         return (1 << dpll->n) << 16 | dpll->m2;
5795 }
5796 
5797 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5798 {
5799         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5800 }
5801 
5802 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5803                                      intel_clock_t *reduced_clock)
5804 {
5805         struct drm_device *dev = crtc->base.dev;
5806         u32 fp, fp2 = 0;
5807 
5808         if (IS_PINEVIEW(dev)) {
5809                 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5810                 if (reduced_clock)
5811                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5812         } else {
5813                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5814                 if (reduced_clock)
5815                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5816         }
5817 
5818         crtc->new_config->dpll_hw_state.fp0 = fp;
5819 
5820         crtc->lowfreq_avail = false;
5821         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5822             reduced_clock && i915.powersave) {
5823                 crtc->new_config->dpll_hw_state.fp1 = fp2;
5824                 crtc->lowfreq_avail = true;
5825         } else {
5826                 crtc->new_config->dpll_hw_state.fp1 = fp;
5827         }
5828 }
5829 
5830 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5831                 pipe)
5832 {
5833         u32 reg_val;
5834 
5835         /*
5836          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5837          * and set it to a reasonable value instead.
5838          */
5839         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5840         reg_val &= 0xffffff00;
5841         reg_val |= 0x00000030;
5842         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5843 
5844         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5845         reg_val &= 0x8cffffff;
5846         reg_val = 0x8c000000;
5847         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5848 
5849         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5850         reg_val &= 0xffffff00;
5851         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5852 
5853         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5854         reg_val &= 0x00ffffff;
5855         reg_val |= 0xb0000000;
5856         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5857 }
5858 
5859 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5860                                          struct intel_link_m_n *m_n)
5861 {
5862         struct drm_device *dev = crtc->base.dev;
5863         struct drm_i915_private *dev_priv = dev->dev_private;
5864         int pipe = crtc->pipe;
5865 
5866         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5867         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5868         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5869         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5870 }
5871 
5872 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5873                                          struct intel_link_m_n *m_n,
5874                                          struct intel_link_m_n *m2_n2)
5875 {
5876         struct drm_device *dev = crtc->base.dev;
5877         struct drm_i915_private *dev_priv = dev->dev_private;
5878         int pipe = crtc->pipe;
5879         enum transcoder transcoder = crtc->config.cpu_transcoder;
5880 
5881         if (INTEL_INFO(dev)->gen >= 5) {
5882                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5883                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5884                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5885                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5886                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5887                  * for gen < 8) and if DRRS is supported (to make sure the
5888                  * registers are not unnecessarily accessed).
5889                  */
5890                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5891                         crtc->config.has_drrs) {
5892                         I915_WRITE(PIPE_DATA_M2(transcoder),
5893                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5894                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5895                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5896                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5897                 }
5898         } else {
5899                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5900                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5901                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5902                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5903         }
5904 }
5905 
5906 void intel_dp_set_m_n(struct intel_crtc *crtc)
5907 {
5908         if (crtc->config.has_pch_encoder)
5909                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5910         else
5911                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5912                                                    &crtc->config.dp_m2_n2);
5913 }
5914 
5915 static void vlv_update_pll(struct intel_crtc *crtc,
5916                            struct intel_crtc_config *pipe_config)
5917 {
5918         u32 dpll, dpll_md;
5919 
5920         /*
5921          * Enable DPIO clock input. We should never disable the reference
5922          * clock for pipe B, since VGA hotplug / manual detection depends
5923          * on it.
5924          */
5925         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5926                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5927         /* We should never disable this, set it here for state tracking */
5928         if (crtc->pipe == PIPE_B)
5929                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5930         dpll |= DPLL_VCO_ENABLE;
5931         pipe_config->dpll_hw_state.dpll = dpll;
5932 
5933         dpll_md = (pipe_config->pixel_multiplier - 1)
5934                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5935         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5936 }
5937 
5938 static void vlv_prepare_pll(struct intel_crtc *crtc,
5939                             const struct intel_crtc_config *pipe_config)
5940 {
5941         struct drm_device *dev = crtc->base.dev;
5942         struct drm_i915_private *dev_priv = dev->dev_private;
5943         int pipe = crtc->pipe;
5944         u32 mdiv;
5945         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5946         u32 coreclk, reg_val;
5947 
5948         mutex_lock(&dev_priv->dpio_lock);
5949 
5950         bestn = pipe_config->dpll.n;
5951         bestm1 = pipe_config->dpll.m1;
5952         bestm2 = pipe_config->dpll.m2;
5953         bestp1 = pipe_config->dpll.p1;
5954         bestp2 = pipe_config->dpll.p2;
5955 
5956         /* See eDP HDMI DPIO driver vbios notes doc */
5957 
5958         /* PLL B needs special handling */
5959         if (pipe == PIPE_B)
5960                 vlv_pllb_recal_opamp(dev_priv, pipe);
5961 
5962         /* Set up Tx target for periodic Rcomp update */
5963         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5964 
5965         /* Disable target IRef on PLL */
5966         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5967         reg_val &= 0x00ffffff;
5968         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5969 
5970         /* Disable fast lock */
5971         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5972 
5973         /* Set idtafcrecal before PLL is enabled */
5974         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5975         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5976         mdiv |= ((bestn << DPIO_N_SHIFT));
5977         mdiv |= (1 << DPIO_K_SHIFT);
5978 
5979         /*
5980          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5981          * but we don't support that).
5982          * Note: don't use the DAC post divider as it seems unstable.
5983          */
5984         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5985         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5986 
5987         mdiv |= DPIO_ENABLE_CALIBRATION;
5988         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5989 
5990         /* Set HBR and RBR LPF coefficients */
5991         if (pipe_config->port_clock == 162000 ||
5992             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5993             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5994                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5995                                  0x009f0003);
5996         else
5997                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5998                                  0x00d0000f);
5999 
6000         if (crtc->config.has_dp_encoder) {
6001                 /* Use SSC source */
6002                 if (pipe == PIPE_A)
6003                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6004                                          0x0df40000);
6005                 else
6006                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6007                                          0x0df70000);
6008         } else { /* HDMI or VGA */
6009                 /* Use bend source */
6010                 if (pipe == PIPE_A)
6011                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6012                                          0x0df70000);
6013                 else
6014                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6015                                          0x0df40000);
6016         }
6017 
6018         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6019         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6020         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6021             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6022                 coreclk |= 0x01000000;
6023         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6024 
6025         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6026         mutex_unlock(&dev_priv->dpio_lock);
6027 }
6028 
6029 static void chv_update_pll(struct intel_crtc *crtc,
6030                            struct intel_crtc_config *pipe_config)
6031 {
6032         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6033                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6034                 DPLL_VCO_ENABLE;
6035         if (crtc->pipe != PIPE_A)
6036                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6037 
6038         pipe_config->dpll_hw_state.dpll_md =
6039                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6040 }
6041 
6042 static void chv_prepare_pll(struct intel_crtc *crtc,
6043                             const struct intel_crtc_config *pipe_config)
6044 {
6045         struct drm_device *dev = crtc->base.dev;
6046         struct drm_i915_private *dev_priv = dev->dev_private;
6047         int pipe = crtc->pipe;
6048         int dpll_reg = DPLL(crtc->pipe);
6049         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6050         u32 loopfilter, intcoeff;
6051         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6052         int refclk;
6053 
6054         bestn = pipe_config->dpll.n;
6055         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6056         bestm1 = pipe_config->dpll.m1;
6057         bestm2 = pipe_config->dpll.m2 >> 22;
6058         bestp1 = pipe_config->dpll.p1;
6059         bestp2 = pipe_config->dpll.p2;
6060 
6061         /*
6062          * Enable Refclk and SSC
6063          */
6064         I915_WRITE(dpll_reg,
6065                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6066 
6067         mutex_lock(&dev_priv->dpio_lock);
6068 
6069         /* p1 and p2 divider */
6070         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6071                         5 << DPIO_CHV_S1_DIV_SHIFT |
6072                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6073                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6074                         1 << DPIO_CHV_K_DIV_SHIFT);
6075 
6076         /* Feedback post-divider - m2 */
6077         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6078 
6079         /* Feedback refclk divider - n and m1 */
6080         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6081                         DPIO_CHV_M1_DIV_BY_2 |
6082                         1 << DPIO_CHV_N_DIV_SHIFT);
6083 
6084         /* M2 fraction division */
6085         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6086 
6087         /* M2 fraction division enable */
6088         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6089                        DPIO_CHV_FRAC_DIV_EN |
6090                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6091 
6092         /* Loop filter */
6093         refclk = i9xx_get_refclk(crtc, 0);
6094         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6095                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6096         if (refclk == 100000)
6097                 intcoeff = 11;
6098         else if (refclk == 38400)
6099                 intcoeff = 10;
6100         else
6101                 intcoeff = 9;
6102         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6103         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6104 
6105         /* AFC Recal */
6106         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6107                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6108                         DPIO_AFC_RECAL);
6109 
6110         mutex_unlock(&dev_priv->dpio_lock);
6111 }
6112 
6113 /**
6114  * vlv_force_pll_on - forcibly enable just the PLL
6115  * @dev_priv: i915 private structure
6116  * @pipe: pipe PLL to enable
6117  * @dpll: PLL configuration
6118  *
6119  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6120  * in cases where we need the PLL enabled even when @pipe is not going to
6121  * be enabled.
6122  */
6123 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6124                       const struct dpll *dpll)
6125 {
6126         struct intel_crtc *crtc =
6127                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6128         struct intel_crtc_config pipe_config = {
6129                 .pixel_multiplier = 1,
6130                 .dpll = *dpll,
6131         };
6132 
6133         if (IS_CHERRYVIEW(dev)) {
6134                 chv_update_pll(crtc, &pipe_config);
6135                 chv_prepare_pll(crtc, &pipe_config);
6136                 chv_enable_pll(crtc, &pipe_config);
6137         } else {
6138                 vlv_update_pll(crtc, &pipe_config);
6139                 vlv_prepare_pll(crtc, &pipe_config);
6140                 vlv_enable_pll(crtc, &pipe_config);
6141         }
6142 }
6143 
6144 /**
6145  * vlv_force_pll_off - forcibly disable just the PLL
6146  * @dev_priv: i915 private structure
6147  * @pipe: pipe PLL to disable
6148  *
6149  * Disable the PLL for @pipe. To be used in cases where we need
6150  * the PLL enabled even when @pipe is not going to be enabled.
6151  */
6152 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6153 {
6154         if (IS_CHERRYVIEW(dev))
6155                 chv_disable_pll(to_i915(dev), pipe);
6156         else
6157                 vlv_disable_pll(to_i915(dev), pipe);
6158 }
6159 
6160 static void i9xx_update_pll(struct intel_crtc *crtc,
6161                             intel_clock_t *reduced_clock,
6162                             int num_connectors)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         u32 dpll;
6167         bool is_sdvo;
6168         struct dpll *clock = &crtc->new_config->dpll;
6169 
6170         i9xx_update_pll_dividers(crtc, reduced_clock);
6171 
6172         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6173                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6174 
6175         dpll = DPLL_VGA_MODE_DIS;
6176 
6177         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6178                 dpll |= DPLLB_MODE_LVDS;
6179         else
6180                 dpll |= DPLLB_MODE_DAC_SERIAL;
6181 
6182         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6183                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6184                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6185         }
6186 
6187         if (is_sdvo)
6188                 dpll |= DPLL_SDVO_HIGH_SPEED;
6189 
6190         if (crtc->new_config->has_dp_encoder)
6191                 dpll |= DPLL_SDVO_HIGH_SPEED;
6192 
6193         /* compute bitmask from p1 value */
6194         if (IS_PINEVIEW(dev))
6195                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6196         else {
6197                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6198                 if (IS_G4X(dev) && reduced_clock)
6199                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6200         }
6201         switch (clock->p2) {
6202         case 5:
6203                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6204                 break;
6205         case 7:
6206                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6207                 break;
6208         case 10:
6209                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6210                 break;
6211         case 14:
6212                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6213                 break;
6214         }
6215         if (INTEL_INFO(dev)->gen >= 4)
6216                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6217 
6218         if (crtc->new_config->sdvo_tv_clock)
6219                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6220         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6221                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6222                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6223         else
6224                 dpll |= PLL_REF_INPUT_DREFCLK;
6225 
6226         dpll |= DPLL_VCO_ENABLE;
6227         crtc->new_config->dpll_hw_state.dpll = dpll;
6228 
6229         if (INTEL_INFO(dev)->gen >= 4) {
6230                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6231                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6232                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6233         }
6234 }
6235 
6236 static void i8xx_update_pll(struct intel_crtc *crtc,
6237                             intel_clock_t *reduced_clock,
6238                             int num_connectors)
6239 {
6240         struct drm_device *dev = crtc->base.dev;
6241         struct drm_i915_private *dev_priv = dev->dev_private;
6242         u32 dpll;
6243         struct dpll *clock = &crtc->new_config->dpll;
6244 
6245         i9xx_update_pll_dividers(crtc, reduced_clock);
6246 
6247         dpll = DPLL_VGA_MODE_DIS;
6248 
6249         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6250                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6251         } else {
6252                 if (clock->p1 == 2)
6253                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6254                 else
6255                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6256                 if (clock->p2 == 4)
6257                         dpll |= PLL_P2_DIVIDE_BY_4;
6258         }
6259 
6260         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6261                 dpll |= DPLL_DVO_2X_MODE;
6262 
6263         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6264                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6265                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6266         else
6267                 dpll |= PLL_REF_INPUT_DREFCLK;
6268 
6269         dpll |= DPLL_VCO_ENABLE;
6270         crtc->new_config->dpll_hw_state.dpll = dpll;
6271 }
6272 
6273 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6274 {
6275         struct drm_device *dev = intel_crtc->base.dev;
6276         struct drm_i915_private *dev_priv = dev->dev_private;
6277         enum pipe pipe = intel_crtc->pipe;
6278         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6279         struct drm_display_mode *adjusted_mode =
6280                 &intel_crtc->config.adjusted_mode;
6281         uint32_t crtc_vtotal, crtc_vblank_end;
6282         int vsyncshift = 0;
6283 
6284         /* We need to be careful not to changed the adjusted mode, for otherwise
6285          * the hw state checker will get angry at the mismatch. */
6286         crtc_vtotal = adjusted_mode->crtc_vtotal;
6287         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6288 
6289         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6290                 /* the chip adds 2 halflines automatically */
6291                 crtc_vtotal -= 1;
6292                 crtc_vblank_end -= 1;
6293 
6294                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6295                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6296                 else
6297                         vsyncshift = adjusted_mode->crtc_hsync_start -
6298                                 adjusted_mode->crtc_htotal / 2;
6299                 if (vsyncshift < 0)
6300                         vsyncshift += adjusted_mode->crtc_htotal;
6301         }
6302 
6303         if (INTEL_INFO(dev)->gen > 3)
6304                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6305 
6306         I915_WRITE(HTOTAL(cpu_transcoder),
6307                    (adjusted_mode->crtc_hdisplay - 1) |
6308                    ((adjusted_mode->crtc_htotal - 1) << 16));
6309         I915_WRITE(HBLANK(cpu_transcoder),
6310                    (adjusted_mode->crtc_hblank_start - 1) |
6311                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6312         I915_WRITE(HSYNC(cpu_transcoder),
6313                    (adjusted_mode->crtc_hsync_start - 1) |
6314                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6315 
6316         I915_WRITE(VTOTAL(cpu_transcoder),
6317                    (adjusted_mode->crtc_vdisplay - 1) |
6318                    ((crtc_vtotal - 1) << 16));
6319         I915_WRITE(VBLANK(cpu_transcoder),
6320                    (adjusted_mode->crtc_vblank_start - 1) |
6321                    ((crtc_vblank_end - 1) << 16));
6322         I915_WRITE(VSYNC(cpu_transcoder),
6323                    (adjusted_mode->crtc_vsync_start - 1) |
6324                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6325 
6326         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6327          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6328          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6329          * bits. */
6330         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6331             (pipe == PIPE_B || pipe == PIPE_C))
6332                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6333 
6334         /* pipesrc controls the size that is scaled from, which should
6335          * always be the user's requested size.
6336          */
6337         I915_WRITE(PIPESRC(pipe),
6338                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6339                    (intel_crtc->config.pipe_src_h - 1));
6340 }
6341 
6342 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6343                                    struct intel_crtc_config *pipe_config)
6344 {
6345         struct drm_device *dev = crtc->base.dev;
6346         struct drm_i915_private *dev_priv = dev->dev_private;
6347         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6348         uint32_t tmp;
6349 
6350         tmp = I915_READ(HTOTAL(cpu_transcoder));
6351         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6352         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6353         tmp = I915_READ(HBLANK(cpu_transcoder));
6354         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6355         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6356         tmp = I915_READ(HSYNC(cpu_transcoder));
6357         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6358         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6359 
6360         tmp = I915_READ(VTOTAL(cpu_transcoder));
6361         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6362         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6363         tmp = I915_READ(VBLANK(cpu_transcoder));
6364         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6365         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6366         tmp = I915_READ(VSYNC(cpu_transcoder));
6367         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6368         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6369 
6370         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6371                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6372                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6373                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6374         }
6375 
6376         tmp = I915_READ(PIPESRC(crtc->pipe));
6377         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6378         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6379 
6380         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6381         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6382 }
6383 
6384 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6385                                  struct intel_crtc_config *pipe_config)
6386 {
6387         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6388         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6389         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6390         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6391 
6392         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6393         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6394         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6395         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6396 
6397         mode->flags = pipe_config->adjusted_mode.flags;
6398 
6399         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6400         mode->flags |= pipe_config->adjusted_mode.flags;
6401 }
6402 
6403 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6404 {
6405         struct drm_device *dev = intel_crtc->base.dev;
6406         struct drm_i915_private *dev_priv = dev->dev_private;
6407         uint32_t pipeconf;
6408 
6409         pipeconf = 0;
6410 
6411         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6412             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6413                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6414 
6415         if (intel_crtc->config.double_wide)
6416                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6417