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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include "intel_frontbuffer.h"
 38 #include <drm/i915_drm.h>
 39 #include "i915_drv.h"
 40 #include "intel_dsi.h"
 41 #include "i915_trace.h"
 42 #include <drm/drm_atomic.h>
 43 #include <drm/drm_atomic_helper.h>
 44 #include <drm/drm_dp_helper.h>
 45 #include <drm/drm_crtc_helper.h>
 46 #include <drm/drm_plane_helper.h>
 47 #include <drm/drm_rect.h>
 48 #include <linux/dma_remapping.h>
 49 #include <linux/reservation.h>
 50 
 51 static bool is_mmio_work(struct intel_flip_work *work)
 52 {
 53         return work->mmio_work.func;
 54 }
 55 
 56 /* Primary plane formats for gen <= 3 */
 57 static const uint32_t i8xx_primary_formats[] = {
 58         DRM_FORMAT_C8,
 59         DRM_FORMAT_RGB565,
 60         DRM_FORMAT_XRGB1555,
 61         DRM_FORMAT_XRGB8888,
 62 };
 63 
 64 /* Primary plane formats for gen >= 4 */
 65 static const uint32_t i965_primary_formats[] = {
 66         DRM_FORMAT_C8,
 67         DRM_FORMAT_RGB565,
 68         DRM_FORMAT_XRGB8888,
 69         DRM_FORMAT_XBGR8888,
 70         DRM_FORMAT_XRGB2101010,
 71         DRM_FORMAT_XBGR2101010,
 72 };
 73 
 74 static const uint32_t skl_primary_formats[] = {
 75         DRM_FORMAT_C8,
 76         DRM_FORMAT_RGB565,
 77         DRM_FORMAT_XRGB8888,
 78         DRM_FORMAT_XBGR8888,
 79         DRM_FORMAT_ARGB8888,
 80         DRM_FORMAT_ABGR8888,
 81         DRM_FORMAT_XRGB2101010,
 82         DRM_FORMAT_XBGR2101010,
 83         DRM_FORMAT_YUYV,
 84         DRM_FORMAT_YVYU,
 85         DRM_FORMAT_UYVY,
 86         DRM_FORMAT_VYUY,
 87 };
 88 
 89 /* Cursor formats */
 90 static const uint32_t intel_cursor_formats[] = {
 91         DRM_FORMAT_ARGB8888,
 92 };
 93 
 94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 95                                 struct intel_crtc_state *pipe_config);
 96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 97                                    struct intel_crtc_state *pipe_config);
 98 
 99 static int intel_framebuffer_init(struct drm_device *dev,
100                                   struct intel_framebuffer *ifb,
101                                   struct drm_mode_fb_cmd2 *mode_cmd,
102                                   struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107                                          struct intel_link_m_n *m_n,
108                                          struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113                             const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115                             const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_i915_private *dev_priv,
119                              struct intel_crtc *crtc,
120                              struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128 
129 struct intel_limit {
130         struct {
131                 int min, max;
132         } dot, vco, n, m, m1, m2, p, p1;
133 
134         struct {
135                 int dot_limit;
136                 int p2_slow, p2_fast;
137         } p2;
138 };
139 
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144 
145         /* Obtain SKU information */
146         mutex_lock(&dev_priv->sb_lock);
147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148                 CCK_FUSE_HPLL_FREQ_MASK;
149         mutex_unlock(&dev_priv->sb_lock);
150 
151         return vco_freq[hpll_freq] * 1000;
152 }
153 
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155                       const char *name, u32 reg, int ref_freq)
156 {
157         u32 val;
158         int divider;
159 
160         mutex_lock(&dev_priv->sb_lock);
161         val = vlv_cck_read(dev_priv, reg);
162         mutex_unlock(&dev_priv->sb_lock);
163 
164         divider = val & CCK_FREQUENCY_VALUES;
165 
166         WARN((val & CCK_FREQUENCY_STATUS) !=
167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
168              "%s change in progress\n", name);
169 
170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172 
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174                                   const char *name, u32 reg)
175 {
176         if (dev_priv->hpll_freq == 0)
177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178 
179         return vlv_get_cck_clock(dev_priv, name, reg,
180                                  dev_priv->hpll_freq);
181 }
182 
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188 
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192         /* RAWCLK_FREQ_VLV register updated from power well code */
193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196 
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200         uint32_t clkcfg;
201 
202         /* hrawclock is 1/4 the FSB frequency */
203         clkcfg = I915_READ(CLKCFG);
204         switch (clkcfg & CLKCFG_FSB_MASK) {
205         case CLKCFG_FSB_400:
206                 return 100000;
207         case CLKCFG_FSB_533:
208                 return 133333;
209         case CLKCFG_FSB_667:
210                 return 166667;
211         case CLKCFG_FSB_800:
212                 return 200000;
213         case CLKCFG_FSB_1067:
214                 return 266667;
215         case CLKCFG_FSB_1333:
216                 return 333333;
217         /* these two are just a guess; one of them might be right */
218         case CLKCFG_FSB_1600:
219         case CLKCFG_FSB_1600_ALT:
220                 return 400000;
221         default:
222                 return 133333;
223         }
224 }
225 
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228         if (HAS_PCH_SPLIT(dev_priv))
229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234         else
235                 return; /* no rawclk on other platforms, or no need to know it */
236 
237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239 
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243                 return;
244 
245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246                                                       CCK_CZ_CLOCK_CONTROL);
247 
248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250 
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253                     const struct intel_crtc_state *pipe_config)
254 {
255         if (HAS_DDI(dev_priv))
256                 return pipe_config->port_clock; /* SPLL */
257         else if (IS_GEN5(dev_priv))
258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259         else
260                 return 270000;
261 }
262 
263 static const struct intel_limit intel_limits_i8xx_dac = {
264         .dot = { .min = 25000, .max = 350000 },
265         .vco = { .min = 908000, .max = 1512000 },
266         .n = { .min = 2, .max = 16 },
267         .m = { .min = 96, .max = 140 },
268         .m1 = { .min = 18, .max = 26 },
269         .m2 = { .min = 6, .max = 16 },
270         .p = { .min = 4, .max = 128 },
271         .p1 = { .min = 2, .max = 33 },
272         .p2 = { .dot_limit = 165000,
273                 .p2_slow = 4, .p2_fast = 2 },
274 };
275 
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277         .dot = { .min = 25000, .max = 350000 },
278         .vco = { .min = 908000, .max = 1512000 },
279         .n = { .min = 2, .max = 16 },
280         .m = { .min = 96, .max = 140 },
281         .m1 = { .min = 18, .max = 26 },
282         .m2 = { .min = 6, .max = 16 },
283         .p = { .min = 4, .max = 128 },
284         .p1 = { .min = 2, .max = 33 },
285         .p2 = { .dot_limit = 165000,
286                 .p2_slow = 4, .p2_fast = 4 },
287 };
288 
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290         .dot = { .min = 25000, .max = 350000 },
291         .vco = { .min = 908000, .max = 1512000 },
292         .n = { .min = 2, .max = 16 },
293         .m = { .min = 96, .max = 140 },
294         .m1 = { .min = 18, .max = 26 },
295         .m2 = { .min = 6, .max = 16 },
296         .p = { .min = 4, .max = 128 },
297         .p1 = { .min = 1, .max = 6 },
298         .p2 = { .dot_limit = 165000,
299                 .p2_slow = 14, .p2_fast = 7 },
300 };
301 
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303         .dot = { .min = 20000, .max = 400000 },
304         .vco = { .min = 1400000, .max = 2800000 },
305         .n = { .min = 1, .max = 6 },
306         .m = { .min = 70, .max = 120 },
307         .m1 = { .min = 8, .max = 18 },
308         .m2 = { .min = 3, .max = 7 },
309         .p = { .min = 5, .max = 80 },
310         .p1 = { .min = 1, .max = 8 },
311         .p2 = { .dot_limit = 200000,
312                 .p2_slow = 10, .p2_fast = 5 },
313 };
314 
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316         .dot = { .min = 20000, .max = 400000 },
317         .vco = { .min = 1400000, .max = 2800000 },
318         .n = { .min = 1, .max = 6 },
319         .m = { .min = 70, .max = 120 },
320         .m1 = { .min = 8, .max = 18 },
321         .m2 = { .min = 3, .max = 7 },
322         .p = { .min = 7, .max = 98 },
323         .p1 = { .min = 1, .max = 8 },
324         .p2 = { .dot_limit = 112000,
325                 .p2_slow = 14, .p2_fast = 7 },
326 };
327 
328 
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330         .dot = { .min = 25000, .max = 270000 },
331         .vco = { .min = 1750000, .max = 3500000},
332         .n = { .min = 1, .max = 4 },
333         .m = { .min = 104, .max = 138 },
334         .m1 = { .min = 17, .max = 23 },
335         .m2 = { .min = 5, .max = 11 },
336         .p = { .min = 10, .max = 30 },
337         .p1 = { .min = 1, .max = 3},
338         .p2 = { .dot_limit = 270000,
339                 .p2_slow = 10,
340                 .p2_fast = 10
341         },
342 };
343 
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345         .dot = { .min = 22000, .max = 400000 },
346         .vco = { .min = 1750000, .max = 3500000},
347         .n = { .min = 1, .max = 4 },
348         .m = { .min = 104, .max = 138 },
349         .m1 = { .min = 16, .max = 23 },
350         .m2 = { .min = 5, .max = 11 },
351         .p = { .min = 5, .max = 80 },
352         .p1 = { .min = 1, .max = 8},
353         .p2 = { .dot_limit = 165000,
354                 .p2_slow = 10, .p2_fast = 5 },
355 };
356 
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358         .dot = { .min = 20000, .max = 115000 },
359         .vco = { .min = 1750000, .max = 3500000 },
360         .n = { .min = 1, .max = 3 },
361         .m = { .min = 104, .max = 138 },
362         .m1 = { .min = 17, .max = 23 },
363         .m2 = { .min = 5, .max = 11 },
364         .p = { .min = 28, .max = 112 },
365         .p1 = { .min = 2, .max = 8 },
366         .p2 = { .dot_limit = 0,
367                 .p2_slow = 14, .p2_fast = 14
368         },
369 };
370 
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372         .dot = { .min = 80000, .max = 224000 },
373         .vco = { .min = 1750000, .max = 3500000 },
374         .n = { .min = 1, .max = 3 },
375         .m = { .min = 104, .max = 138 },
376         .m1 = { .min = 17, .max = 23 },
377         .m2 = { .min = 5, .max = 11 },
378         .p = { .min = 14, .max = 42 },
379         .p1 = { .min = 2, .max = 6 },
380         .p2 = { .dot_limit = 0,
381                 .p2_slow = 7, .p2_fast = 7
382         },
383 };
384 
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386         .dot = { .min = 20000, .max = 400000},
387         .vco = { .min = 1700000, .max = 3500000 },
388         /* Pineview's Ncounter is a ring counter */
389         .n = { .min = 3, .max = 6 },
390         .m = { .min = 2, .max = 256 },
391         /* Pineview only has one combined m divider, which we treat as m2. */
392         .m1 = { .min = 0, .max = 0 },
393         .m2 = { .min = 0, .max = 254 },
394         .p = { .min = 5, .max = 80 },
395         .p1 = { .min = 1, .max = 8 },
396         .p2 = { .dot_limit = 200000,
397                 .p2_slow = 10, .p2_fast = 5 },
398 };
399 
400 static const struct intel_limit intel_limits_pineview_lvds = {
401         .dot = { .min = 20000, .max = 400000 },
402         .vco = { .min = 1700000, .max = 3500000 },
403         .n = { .min = 3, .max = 6 },
404         .m = { .min = 2, .max = 256 },
405         .m1 = { .min = 0, .max = 0 },
406         .m2 = { .min = 0, .max = 254 },
407         .p = { .min = 7, .max = 112 },
408         .p1 = { .min = 1, .max = 8 },
409         .p2 = { .dot_limit = 112000,
410                 .p2_slow = 14, .p2_fast = 14 },
411 };
412 
413 /* Ironlake / Sandybridge
414  *
415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
416  * the range value for them is (actual_value - 2).
417  */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419         .dot = { .min = 25000, .max = 350000 },
420         .vco = { .min = 1760000, .max = 3510000 },
421         .n = { .min = 1, .max = 5 },
422         .m = { .min = 79, .max = 127 },
423         .m1 = { .min = 12, .max = 22 },
424         .m2 = { .min = 5, .max = 9 },
425         .p = { .min = 5, .max = 80 },
426         .p1 = { .min = 1, .max = 8 },
427         .p2 = { .dot_limit = 225000,
428                 .p2_slow = 10, .p2_fast = 5 },
429 };
430 
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432         .dot = { .min = 25000, .max = 350000 },
433         .vco = { .min = 1760000, .max = 3510000 },
434         .n = { .min = 1, .max = 3 },
435         .m = { .min = 79, .max = 118 },
436         .m1 = { .min = 12, .max = 22 },
437         .m2 = { .min = 5, .max = 9 },
438         .p = { .min = 28, .max = 112 },
439         .p1 = { .min = 2, .max = 8 },
440         .p2 = { .dot_limit = 225000,
441                 .p2_slow = 14, .p2_fast = 14 },
442 };
443 
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445         .dot = { .min = 25000, .max = 350000 },
446         .vco = { .min = 1760000, .max = 3510000 },
447         .n = { .min = 1, .max = 3 },
448         .m = { .min = 79, .max = 127 },
449         .m1 = { .min = 12, .max = 22 },
450         .m2 = { .min = 5, .max = 9 },
451         .p = { .min = 14, .max = 56 },
452         .p1 = { .min = 2, .max = 8 },
453         .p2 = { .dot_limit = 225000,
454                 .p2_slow = 7, .p2_fast = 7 },
455 };
456 
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459         .dot = { .min = 25000, .max = 350000 },
460         .vco = { .min = 1760000, .max = 3510000 },
461         .n = { .min = 1, .max = 2 },
462         .m = { .min = 79, .max = 126 },
463         .m1 = { .min = 12, .max = 22 },
464         .m2 = { .min = 5, .max = 9 },
465         .p = { .min = 28, .max = 112 },
466         .p1 = { .min = 2, .max = 8 },
467         .p2 = { .dot_limit = 225000,
468                 .p2_slow = 14, .p2_fast = 14 },
469 };
470 
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472         .dot = { .min = 25000, .max = 350000 },
473         .vco = { .min = 1760000, .max = 3510000 },
474         .n = { .min = 1, .max = 3 },
475         .m = { .min = 79, .max = 126 },
476         .m1 = { .min = 12, .max = 22 },
477         .m2 = { .min = 5, .max = 9 },
478         .p = { .min = 14, .max = 42 },
479         .p1 = { .min = 2, .max = 6 },
480         .p2 = { .dot_limit = 225000,
481                 .p2_slow = 7, .p2_fast = 7 },
482 };
483 
484 static const struct intel_limit intel_limits_vlv = {
485          /*
486           * These are the data rate limits (measured in fast clocks)
487           * since those are the strictest limits we have. The fast
488           * clock and actual rate limits are more relaxed, so checking
489           * them would make no difference.
490           */
491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492         .vco = { .min = 4000000, .max = 6000000 },
493         .n = { .min = 1, .max = 7 },
494         .m1 = { .min = 2, .max = 3 },
495         .m2 = { .min = 11, .max = 156 },
496         .p1 = { .min = 2, .max = 3 },
497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499 
500 static const struct intel_limit intel_limits_chv = {
501         /*
502          * These are the data rate limits (measured in fast clocks)
503          * since those are the strictest limits we have.  The fast
504          * clock and actual rate limits are more relaxed, so checking
505          * them would make no difference.
506          */
507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
508         .vco = { .min = 4800000, .max = 6480000 },
509         .n = { .min = 1, .max = 1 },
510         .m1 = { .min = 2, .max = 2 },
511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
512         .p1 = { .min = 2, .max = 4 },
513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515 
516 static const struct intel_limit intel_limits_bxt = {
517         /* FIXME: find real dot limits */
518         .dot = { .min = 0, .max = INT_MAX },
519         .vco = { .min = 4800000, .max = 6700000 },
520         .n = { .min = 1, .max = 1 },
521         .m1 = { .min = 2, .max = 2 },
522         /* FIXME: find real m2 limits */
523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
524         .p1 = { .min = 2, .max = 4 },
525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527 
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531         return drm_atomic_crtc_needs_modeset(state);
532 }
533 
534 /*
535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538  * The helpers' return value is the rate of the clock that is fed to the
539  * display engine's pipe which can be the above fast dot clock rate or a
540  * divided-down version of it.
541  */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545         clock->m = clock->m2 + 2;
546         clock->p = clock->p1 * clock->p2;
547         if (WARN_ON(clock->n == 0 || clock->p == 0))
548                 return 0;
549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551 
552         return clock->dot;
553 }
554 
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559 
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562         clock->m = i9xx_dpll_compute_m(clock);
563         clock->p = clock->p1 * clock->p2;
564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565                 return 0;
566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 
569         return clock->dot;
570 }
571 
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574         clock->m = clock->m1 * clock->m2;
575         clock->p = clock->p1 * clock->p2;
576         if (WARN_ON(clock->n == 0 || clock->p == 0))
577                 return 0;
578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580 
581         return clock->dot / 5;
582 }
583 
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586         clock->m = clock->m1 * clock->m2;
587         clock->p = clock->p1 * clock->p2;
588         if (WARN_ON(clock->n == 0 || clock->p == 0))
589                 return 0;
590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591                         clock->n << 22);
592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593 
594         return clock->dot / 5;
595 }
596 
597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599  * Returns whether the given set of divisors are valid for a given refclk with
600  * the given connectors.
601  */
602 
603 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
604                                const struct intel_limit *limit,
605                                const struct dpll *clock)
606 {
607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
608                 INTELPllInvalid("n out of range\n");
609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
610                 INTELPllInvalid("p1 out of range\n");
611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
612                 INTELPllInvalid("m2 out of range\n");
613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
614                 INTELPllInvalid("m1 out of range\n");
615 
616         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
617             !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
618                 if (clock->m1 <= clock->m2)
619                         INTELPllInvalid("m1 <= m2\n");
620 
621         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
622             !IS_BROXTON(dev_priv)) {
623                 if (clock->p < limit->p.min || limit->p.max < clock->p)
624                         INTELPllInvalid("p out of range\n");
625                 if (clock->m < limit->m.min || limit->m.max < clock->m)
626                         INTELPllInvalid("m out of range\n");
627         }
628 
629         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
630                 INTELPllInvalid("vco out of range\n");
631         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632          * connector, etc., rather than just a single range.
633          */
634         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
635                 INTELPllInvalid("dot out of range\n");
636 
637         return true;
638 }
639 
640 static int
641 i9xx_select_p2_div(const struct intel_limit *limit,
642                    const struct intel_crtc_state *crtc_state,
643                    int target)
644 {
645         struct drm_device *dev = crtc_state->base.crtc->dev;
646 
647         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648                 /*
649                  * For LVDS just rely on its current settings for dual-channel.
650                  * We haven't figured out how to reliably set up different
651                  * single/dual channel state, if we even can.
652                  */
653                 if (intel_is_dual_link_lvds(dev))
654                         return limit->p2.p2_fast;
655                 else
656                         return limit->p2.p2_slow;
657         } else {
658                 if (target < limit->p2.dot_limit)
659                         return limit->p2.p2_slow;
660                 else
661                         return limit->p2.p2_fast;
662         }
663 }
664 
665 /*
666  * Returns a set of divisors for the desired target clock with the given
667  * refclk, or FALSE.  The returned values represent the clock equation:
668  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669  *
670  * Target and reference clocks are specified in kHz.
671  *
672  * If match_clock is provided, then best_clock P divider must match the P
673  * divider from @match_clock used for LVDS downclocking.
674  */
675 static bool
676 i9xx_find_best_dpll(const struct intel_limit *limit,
677                     struct intel_crtc_state *crtc_state,
678                     int target, int refclk, struct dpll *match_clock,
679                     struct dpll *best_clock)
680 {
681         struct drm_device *dev = crtc_state->base.crtc->dev;
682         struct dpll clock;
683         int err = target;
684 
685         memset(best_clock, 0, sizeof(*best_clock));
686 
687         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688 
689         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690              clock.m1++) {
691                 for (clock.m2 = limit->m2.min;
692                      clock.m2 <= limit->m2.max; clock.m2++) {
693                         if (clock.m2 >= clock.m1)
694                                 break;
695                         for (clock.n = limit->n.min;
696                              clock.n <= limit->n.max; clock.n++) {
697                                 for (clock.p1 = limit->p1.min;
698                                         clock.p1 <= limit->p1.max; clock.p1++) {
699                                         int this_err;
700 
701                                         i9xx_calc_dpll_params(refclk, &clock);
702                                         if (!intel_PLL_is_valid(to_i915(dev),
703                                                                 limit,
704                                                                 &clock))
705                                                 continue;
706                                         if (match_clock &&
707                                             clock.p != match_clock->p)
708                                                 continue;
709 
710                                         this_err = abs(clock.dot - target);
711                                         if (this_err < err) {
712                                                 *best_clock = clock;
713                                                 err = this_err;
714                                         }
715                                 }
716                         }
717                 }
718         }
719 
720         return (err != target);
721 }
722 
723 /*
724  * Returns a set of divisors for the desired target clock with the given
725  * refclk, or FALSE.  The returned values represent the clock equation:
726  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
727  *
728  * Target and reference clocks are specified in kHz.
729  *
730  * If match_clock is provided, then best_clock P divider must match the P
731  * divider from @match_clock used for LVDS downclocking.
732  */
733 static bool
734 pnv_find_best_dpll(const struct intel_limit *limit,
735                    struct intel_crtc_state *crtc_state,
736                    int target, int refclk, struct dpll *match_clock,
737                    struct dpll *best_clock)
738 {
739         struct drm_device *dev = crtc_state->base.crtc->dev;
740         struct dpll clock;
741         int err = target;
742 
743         memset(best_clock, 0, sizeof(*best_clock));
744 
745         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746 
747         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748              clock.m1++) {
749                 for (clock.m2 = limit->m2.min;
750                      clock.m2 <= limit->m2.max; clock.m2++) {
751                         for (clock.n = limit->n.min;
752                              clock.n <= limit->n.max; clock.n++) {
753                                 for (clock.p1 = limit->p1.min;
754                                         clock.p1 <= limit->p1.max; clock.p1++) {
755                                         int this_err;
756 
757                                         pnv_calc_dpll_params(refclk, &clock);
758                                         if (!intel_PLL_is_valid(to_i915(dev),
759                                                                 limit,
760                                                                 &clock))
761                                                 continue;
762                                         if (match_clock &&
763                                             clock.p != match_clock->p)
764                                                 continue;
765 
766                                         this_err = abs(clock.dot - target);
767                                         if (this_err < err) {
768                                                 *best_clock = clock;
769                                                 err = this_err;
770                                         }
771                                 }
772                         }
773                 }
774         }
775 
776         return (err != target);
777 }
778 
779 /*
780  * Returns a set of divisors for the desired target clock with the given
781  * refclk, or FALSE.  The returned values represent the clock equation:
782  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
783  *
784  * Target and reference clocks are specified in kHz.
785  *
786  * If match_clock is provided, then best_clock P divider must match the P
787  * divider from @match_clock used for LVDS downclocking.
788  */
789 static bool
790 g4x_find_best_dpll(const struct intel_limit *limit,
791                    struct intel_crtc_state *crtc_state,
792                    int target, int refclk, struct dpll *match_clock,
793                    struct dpll *best_clock)
794 {
795         struct drm_device *dev = crtc_state->base.crtc->dev;
796         struct dpll clock;
797         int max_n;
798         bool found = false;
799         /* approximately equals target * 0.00585 */
800         int err_most = (target >> 8) + (target >> 9);
801 
802         memset(best_clock, 0, sizeof(*best_clock));
803 
804         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
805 
806         max_n = limit->n.max;
807         /* based on hardware requirement, prefer smaller n to precision */
808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809                 /* based on hardware requirement, prefere larger m1,m2 */
810                 for (clock.m1 = limit->m1.max;
811                      clock.m1 >= limit->m1.min; clock.m1--) {
812                         for (clock.m2 = limit->m2.max;
813                              clock.m2 >= limit->m2.min; clock.m2--) {
814                                 for (clock.p1 = limit->p1.max;
815                                      clock.p1 >= limit->p1.min; clock.p1--) {
816                                         int this_err;
817 
818                                         i9xx_calc_dpll_params(refclk, &clock);
819                                         if (!intel_PLL_is_valid(to_i915(dev),
820                                                                 limit,
821                                                                 &clock))
822                                                 continue;
823 
824                                         this_err = abs(clock.dot - target);
825                                         if (this_err < err_most) {
826                                                 *best_clock = clock;
827                                                 err_most = this_err;
828                                                 max_n = clock.n;
829                                                 found = true;
830                                         }
831                                 }
832                         }
833                 }
834         }
835         return found;
836 }
837 
838 /*
839  * Check if the calculated PLL configuration is more optimal compared to the
840  * best configuration and error found so far. Return the calculated error.
841  */
842 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
843                                const struct dpll *calculated_clock,
844                                const struct dpll *best_clock,
845                                unsigned int best_error_ppm,
846                                unsigned int *error_ppm)
847 {
848         /*
849          * For CHV ignore the error and consider only the P value.
850          * Prefer a bigger P value based on HW requirements.
851          */
852         if (IS_CHERRYVIEW(to_i915(dev))) {
853                 *error_ppm = 0;
854 
855                 return calculated_clock->p > best_clock->p;
856         }
857 
858         if (WARN_ON_ONCE(!target_freq))
859                 return false;
860 
861         *error_ppm = div_u64(1000000ULL *
862                                 abs(target_freq - calculated_clock->dot),
863                              target_freq);
864         /*
865          * Prefer a better P value over a better (smaller) error if the error
866          * is small. Ensure this preference for future configurations too by
867          * setting the error to 0.
868          */
869         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
870                 *error_ppm = 0;
871 
872                 return true;
873         }
874 
875         return *error_ppm + 10 < best_error_ppm;
876 }
877 
878 /*
879  * Returns a set of divisors for the desired target clock with the given
880  * refclk, or FALSE.  The returned values represent the clock equation:
881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882  */
883 static bool
884 vlv_find_best_dpll(const struct intel_limit *limit,
885                    struct intel_crtc_state *crtc_state,
886                    int target, int refclk, struct dpll *match_clock,
887                    struct dpll *best_clock)
888 {
889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890         struct drm_device *dev = crtc->base.dev;
891         struct dpll clock;
892         unsigned int bestppm = 1000000;
893         /* min update 19.2 MHz */
894         int max_n = min(limit->n.max, refclk / 19200);
895         bool found = false;
896 
897         target *= 5; /* fast clock */
898 
899         memset(best_clock, 0, sizeof(*best_clock));
900 
901         /* based on hardware requirement, prefer smaller n to precision */
902         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
903                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
904                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
905                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
906                                 clock.p = clock.p1 * clock.p2;
907                                 /* based on hardware requirement, prefer bigger m1,m2 values */
908                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
909                                         unsigned int ppm;
910 
911                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
912                                                                      refclk * clock.m1);
913 
914                                         vlv_calc_dpll_params(refclk, &clock);
915 
916                                         if (!intel_PLL_is_valid(to_i915(dev),
917                                                                 limit,
918                                                                 &clock))
919                                                 continue;
920 
921                                         if (!vlv_PLL_is_optimal(dev, target,
922                                                                 &clock,
923                                                                 best_clock,
924                                                                 bestppm, &ppm))
925                                                 continue;
926 
927                                         *best_clock = clock;
928                                         bestppm = ppm;
929                                         found = true;
930                                 }
931                         }
932                 }
933         }
934 
935         return found;
936 }
937 
938 /*
939  * Returns a set of divisors for the desired target clock with the given
940  * refclk, or FALSE.  The returned values represent the clock equation:
941  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
942  */
943 static bool
944 chv_find_best_dpll(const struct intel_limit *limit,
945                    struct intel_crtc_state *crtc_state,
946                    int target, int refclk, struct dpll *match_clock,
947                    struct dpll *best_clock)
948 {
949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
950         struct drm_device *dev = crtc->base.dev;
951         unsigned int best_error_ppm;
952         struct dpll clock;
953         uint64_t m2;
954         int found = false;
955 
956         memset(best_clock, 0, sizeof(*best_clock));
957         best_error_ppm = 1000000;
958 
959         /*
960          * Based on hardware doc, the n always set to 1, and m1 always
961          * set to 2.  If requires to support 200Mhz refclk, we need to
962          * revisit this because n may not 1 anymore.
963          */
964         clock.n = 1, clock.m1 = 2;
965         target *= 5;    /* fast clock */
966 
967         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
968                 for (clock.p2 = limit->p2.p2_fast;
969                                 clock.p2 >= limit->p2.p2_slow;
970                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971                         unsigned int error_ppm;
972 
973                         clock.p = clock.p1 * clock.p2;
974 
975                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
976                                         clock.n) << 22, refclk * clock.m1);
977 
978                         if (m2 > INT_MAX/clock.m1)
979                                 continue;
980 
981                         clock.m2 = m2;
982 
983                         chv_calc_dpll_params(refclk, &clock);
984 
985                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
986                                 continue;
987 
988                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
989                                                 best_error_ppm, &error_ppm))
990                                 continue;
991 
992                         *best_clock = clock;
993                         best_error_ppm = error_ppm;
994                         found = true;
995                 }
996         }
997 
998         return found;
999 }
1000 
1001 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1002                         struct dpll *best_clock)
1003 {
1004         int refclk = 100000;
1005         const struct intel_limit *limit = &intel_limits_bxt;
1006 
1007         return chv_find_best_dpll(limit, crtc_state,
1008                                   target_clock, refclk, NULL, best_clock);
1009 }
1010 
1011 bool intel_crtc_active(struct intel_crtc *crtc)
1012 {
1013         /* Be paranoid as we can arrive here with only partial
1014          * state retrieved from the hardware during setup.
1015          *
1016          * We can ditch the adjusted_mode.crtc_clock check as soon
1017          * as Haswell has gained clock readout/fastboot support.
1018          *
1019          * We can ditch the crtc->primary->fb check as soon as we can
1020          * properly reconstruct framebuffers.
1021          *
1022          * FIXME: The intel_crtc->active here should be switched to
1023          * crtc->state->active once we have proper CRTC states wired up
1024          * for atomic.
1025          */
1026         return crtc->active && crtc->base.primary->state->fb &&
1027                 crtc->config->base.adjusted_mode.crtc_clock;
1028 }
1029 
1030 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1031                                              enum pipe pipe)
1032 {
1033         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1034 
1035         return crtc->config->cpu_transcoder;
1036 }
1037 
1038 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         i915_reg_t reg = PIPEDSL(pipe);
1041         u32 line1, line2;
1042         u32 line_mask;
1043 
1044         if (IS_GEN2(dev_priv))
1045                 line_mask = DSL_LINEMASK_GEN2;
1046         else
1047                 line_mask = DSL_LINEMASK_GEN3;
1048 
1049         line1 = I915_READ(reg) & line_mask;
1050         msleep(5);
1051         line2 = I915_READ(reg) & line_mask;
1052 
1053         return line1 == line2;
1054 }
1055 
1056 /*
1057  * intel_wait_for_pipe_off - wait for pipe to turn off
1058  * @crtc: crtc whose pipe to wait for
1059  *
1060  * After disabling a pipe, we can't wait for vblank in the usual way,
1061  * spinning on the vblank interrupt status bit, since we won't actually
1062  * see an interrupt when the pipe is disabled.
1063  *
1064  * On Gen4 and above:
1065  *   wait for the pipe register state bit to turn off
1066  *
1067  * Otherwise:
1068  *   wait for the display line value to settle (it usually
1069  *   ends up stopping at the start of the next frame).
1070  *
1071  */
1072 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 {
1074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077 
1078         if (INTEL_GEN(dev_priv) >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080 
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092 
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099 
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106 
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112 
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116 
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122 
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129 
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150 
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159 
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164 
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168 
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172 
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176 
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182 
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189 
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1191 {
1192         i915_reg_t pp_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196 
1197         if (WARN_ON(HAS_DDI(dev_priv)))
1198                 return;
1199 
1200         if (HAS_PCH_SPLIT(dev_priv)) {
1201                 u32 port_sel;
1202 
1203                 pp_reg = PP_CONTROL(0);
1204                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1205 
1206                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1207                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1208                         panel_pipe = PIPE_B;
1209                 /* XXX: else fix for eDP */
1210         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1211                 /* presumably write lock depends on pipe, not port select */
1212                 pp_reg = PP_CONTROL(pipe);
1213                 panel_pipe = pipe;
1214         } else {
1215                 pp_reg = PP_CONTROL(0);
1216                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1217                         panel_pipe = PIPE_B;
1218         }
1219 
1220         val = I915_READ(pp_reg);
1221         if (!(val & PANEL_POWER_ON) ||
1222             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1223                 locked = false;
1224 
1225         I915_STATE_WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229 
1230 static void assert_cursor(struct drm_i915_private *dev_priv,
1231                           enum pipe pipe, bool state)
1232 {
1233         bool cur_state;
1234 
1235         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
1236                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1237         else
1238                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1239 
1240         I915_STATE_WARN(cur_state != state,
1241              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242                         pipe_name(pipe), onoff(state), onoff(cur_state));
1243 }
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1246 
1247 void assert_pipe(struct drm_i915_private *dev_priv,
1248                  enum pipe pipe, bool state)
1249 {
1250         bool cur_state;
1251         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1252                                                                       pipe);
1253         enum intel_display_power_domain power_domain;
1254 
1255         /* if we need the pipe quirk it must be always on */
1256         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1257             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1258                 state = true;
1259 
1260         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1261         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1262                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1263                 cur_state = !!(val & PIPECONF_ENABLE);
1264 
1265                 intel_display_power_put(dev_priv, power_domain);
1266         } else {
1267                 cur_state = false;
1268         }
1269 
1270         I915_STATE_WARN(cur_state != state,
1271              "pipe %c assertion failure (expected %s, current %s)\n",
1272                         pipe_name(pipe), onoff(state), onoff(cur_state));
1273 }
1274 
1275 static void assert_plane(struct drm_i915_private *dev_priv,
1276                          enum plane plane, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280 
1281         val = I915_READ(DSPCNTR(plane));
1282         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "plane %c assertion failure (expected %s, current %s)\n",
1285                         plane_name(plane), onoff(state), onoff(cur_state));
1286 }
1287 
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1290 
1291 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe)
1293 {
1294         int i;
1295 
1296         /* Primary planes are fixed to pipes on gen4+ */
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 u32 val = I915_READ(DSPCNTR(pipe));
1299                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1300                      "plane %c assertion failure, should be disabled but not\n",
1301                      plane_name(pipe));
1302                 return;
1303         }
1304 
1305         /* Need to check both planes against the pipe */
1306         for_each_pipe(dev_priv, i) {
1307                 u32 val = I915_READ(DSPCNTR(i));
1308                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1309                         DISPPLANE_SEL_PIPE_SHIFT;
1310                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1311                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312                      plane_name(i), pipe_name(pipe));
1313         }
1314 }
1315 
1316 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         int sprite;
1320 
1321         if (INTEL_GEN(dev_priv) >= 9) {
1322                 for_each_sprite(dev_priv, pipe, sprite) {
1323                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1324                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1325                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326                              sprite, pipe_name(pipe));
1327                 }
1328         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1329                 for_each_sprite(dev_priv, pipe, sprite) {
1330                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1331                         I915_STATE_WARN(val & SP_ENABLE,
1332                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333                              sprite_name(pipe, sprite), pipe_name(pipe));
1334                 }
1335         } else if (INTEL_GEN(dev_priv) >= 7) {
1336                 u32 val = I915_READ(SPRCTL(pipe));
1337                 I915_STATE_WARN(val & SPRITE_ENABLE,
1338                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339                      plane_name(pipe), pipe_name(pipe));
1340         } else if (INTEL_GEN(dev_priv) >= 5) {
1341                 u32 val = I915_READ(DVSCNTR(pipe));
1342                 I915_STATE_WARN(val & DVS_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         }
1346 }
1347 
1348 static void assert_vblank_disabled(struct drm_crtc *crtc)
1349 {
1350         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1351                 drm_crtc_vblank_put(crtc);
1352 }
1353 
1354 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                     enum pipe pipe)
1356 {
1357         u32 val;
1358         bool enabled;
1359 
1360         val = I915_READ(PCH_TRANSCONF(pipe));
1361         enabled = !!(val & TRANS_ENABLE);
1362         I915_STATE_WARN(enabled,
1363              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364              pipe_name(pipe));
1365 }
1366 
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368                             enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370         if ((val & DP_PORT_EN) == 0)
1371                 return false;
1372 
1373         if (HAS_PCH_CPT(dev_priv)) {
1374                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386 
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392 
1393         if (HAS_PCH_CPT(dev_priv)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405 
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411 
1412         if (HAS_PCH_CPT(dev_priv)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421 
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436 
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, i915_reg_t reg,
1439                                    u32 port_sel)
1440 {
1441         u32 val = I915_READ(reg);
1442         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444              i915_mmio_reg_offset(reg), pipe_name(pipe));
1445 
1446         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1447              && (val & DP_PIPEB_SELECT),
1448              "IBX PCH dp port still using transcoder B\n");
1449 }
1450 
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452                                      enum pipe pipe, i915_reg_t reg)
1453 {
1454         u32 val = I915_READ(reg);
1455         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457              i915_mmio_reg_offset(reg), pipe_name(pipe));
1458 
1459         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1460              && (val & SDVO_PIPE_B_SELECT),
1461              "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463 
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465                                       enum pipe pipe)
1466 {
1467         u32 val;
1468 
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472 
1473         val = I915_READ(PCH_ADPA);
1474         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475              "PCH VGA enabled on transcoder %c, should be disabled\n",
1476              pipe_name(pipe));
1477 
1478         val = I915_READ(PCH_LVDS);
1479         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482 
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487 
1488 static void _vlv_enable_pll(struct intel_crtc *crtc,
1489                             const struct intel_crtc_state *pipe_config)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1492         enum pipe pipe = crtc->pipe;
1493 
1494         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1495         POSTING_READ(DPLL(pipe));
1496         udelay(150);
1497 
1498         if (intel_wait_for_register(dev_priv,
1499                                     DPLL(pipe),
1500                                     DPLL_LOCK_VLV,
1501                                     DPLL_LOCK_VLV,
1502                                     1))
1503                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1504 }
1505 
1506 static void vlv_enable_pll(struct intel_crtc *crtc,
1507                            const struct intel_crtc_state *pipe_config)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510         enum pipe pipe = crtc->pipe;
1511 
1512         assert_pipe_disabled(dev_priv, pipe);
1513 
1514         /* PLL is protected by panel, make sure we can write it */
1515         assert_panel_unlocked(dev_priv, pipe);
1516 
1517         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1518                 _vlv_enable_pll(crtc, pipe_config);
1519 
1520         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1521         POSTING_READ(DPLL_MD(pipe));
1522 }
1523 
1524 
1525 static void _chv_enable_pll(struct intel_crtc *crtc,
1526                             const struct intel_crtc_state *pipe_config)
1527 {
1528         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1529         enum pipe pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532 
1533         mutex_lock(&dev_priv->sb_lock);
1534 
1535         /* Enable back the 10bit clock to display controller */
1536         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1537         tmp |= DPIO_DCLKP_EN;
1538         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1539 
1540         mutex_unlock(&dev_priv->sb_lock);
1541 
1542         /*
1543          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544          */
1545         udelay(1);
1546 
1547         /* Enable PLL */
1548         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1549 
1550         /* Check PLL is locked */
1551         if (intel_wait_for_register(dev_priv,
1552                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1553                                     1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555 }
1556 
1557 static void chv_enable_pll(struct intel_crtc *crtc,
1558                            const struct intel_crtc_state *pipe_config)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561         enum pipe pipe = crtc->pipe;
1562 
1563         assert_pipe_disabled(dev_priv, pipe);
1564 
1565         /* PLL is protected by panel, make sure we can write it */
1566         assert_panel_unlocked(dev_priv, pipe);
1567 
1568         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1569                 _chv_enable_pll(crtc, pipe_config);
1570 
1571         if (pipe != PIPE_A) {
1572                 /*
1573                  * WaPixelRepeatModeFixForC0:chv
1574                  *
1575                  * DPLLCMD is AWOL. Use chicken bits to propagate
1576                  * the value from DPLLBMD to either pipe B or C.
1577                  */
1578                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1579                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1580                 I915_WRITE(CBR4_VLV, 0);
1581                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1582 
1583                 /*
1584                  * DPLLB VGA mode also seems to cause problems.
1585                  * We should always have it disabled.
1586                  */
1587                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1588         } else {
1589                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1590                 POSTING_READ(DPLL_MD(pipe));
1591         }
1592 }
1593 
1594 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1595 {
1596         struct intel_crtc *crtc;
1597         int count = 0;
1598 
1599         for_each_intel_crtc(&dev_priv->drm, crtc) {
1600                 count += crtc->base.state->active &&
1601                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1602         }
1603 
1604         return count;
1605 }
1606 
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1610         i915_reg_t reg = DPLL(crtc->pipe);
1611         u32 dpll = crtc->config->dpll_hw_state.dpll;
1612 
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614 
1615         /* PLL is protected by panel, make sure we can write it */
1616         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1617                 assert_panel_unlocked(dev_priv, crtc->pipe);
1618 
1619         /* Enable DVO 2x clock on both PLLs if necessary */
1620         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1621                 /*
1622                  * It appears to be important that we don't enable this
1623                  * for the current pipe before otherwise configuring the
1624                  * PLL. No idea how this should be handled if multiple
1625                  * DVO outputs are enabled simultaneosly.
1626                  */
1627                 dpll |= DPLL_DVO_2X_MODE;
1628                 I915_WRITE(DPLL(!crtc->pipe),
1629                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1630         }
1631 
1632         /*
1633          * Apparently we need to have VGA mode enabled prior to changing
1634          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635          * dividers, even though the register value does change.
1636          */
1637         I915_WRITE(reg, 0);
1638 
1639         I915_WRITE(reg, dpll);
1640 
1641         /* Wait for the clocks to stabilize. */
1642         POSTING_READ(reg);
1643         udelay(150);
1644 
1645         if (INTEL_GEN(dev_priv) >= 4) {
1646                 I915_WRITE(DPLL_MD(crtc->pipe),
1647                            crtc->config->dpll_hw_state.dpll_md);
1648         } else {
1649                 /* The pixel multiplier can only be updated once the
1650                  * DPLL is enabled and the clocks are stable.
1651                  *
1652                  * So write it again.
1653                  */
1654                 I915_WRITE(reg, dpll);
1655         }
1656 
1657         /* We do this three times for luck */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667 }
1668 
1669 /**
1670  * i9xx_disable_pll - disable a PLL
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe PLL to disable
1673  *
1674  * Disable the PLL for @pipe, making sure the pipe is off first.
1675  *
1676  * Note!  This is for pre-ILK only.
1677  */
1678 static void i9xx_disable_pll(struct intel_crtc *crtc)
1679 {
1680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681         enum pipe pipe = crtc->pipe;
1682 
1683         /* Disable DVO 2x clock on both PLLs if necessary */
1684         if (IS_I830(dev_priv) &&
1685             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1686             !intel_num_dvo_pipes(dev_priv)) {
1687                 I915_WRITE(DPLL(PIPE_B),
1688                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1689                 I915_WRITE(DPLL(PIPE_A),
1690                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1691         }
1692 
1693         /* Don't disable pipe or pipe PLLs if needed */
1694         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1695             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1696                 return;
1697 
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700 
1701         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1702         POSTING_READ(DPLL(pipe));
1703 }
1704 
1705 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1706 {
1707         u32 val;
1708 
1709         /* Make sure the pipe isn't still relying on us */
1710         assert_pipe_disabled(dev_priv, pipe);
1711 
1712         val = DPLL_INTEGRATED_REF_CLK_VLV |
1713                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1714         if (pipe != PIPE_A)
1715                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1716 
1717         I915_WRITE(DPLL(pipe), val);
1718         POSTING_READ(DPLL(pipe));
1719 }
1720 
1721 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1724         u32 val;
1725 
1726         /* Make sure the pipe isn't still relying on us */
1727         assert_pipe_disabled(dev_priv, pipe);
1728 
1729         val = DPLL_SSC_REF_CLK_CHV |
1730                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1731         if (pipe != PIPE_A)
1732                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1733 
1734         I915_WRITE(DPLL(pipe), val);
1735         POSTING_READ(DPLL(pipe));
1736 
1737         mutex_lock(&dev_priv->sb_lock);
1738 
1739         /* Disable 10bit clock to display controller */
1740         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1741         val &= ~DPIO_DCLKP_EN;
1742         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1743 
1744         mutex_unlock(&dev_priv->sb_lock);
1745 }
1746 
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748                          struct intel_digital_port *dport,
1749                          unsigned int expected_mask)
1750 {
1751         u32 port_mask;
1752         i915_reg_t dpll_reg;
1753 
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 expected_mask <<= 4;
1763                 break;
1764         case PORT_D:
1765                 port_mask = DPLL_PORTD_READY_MASK;
1766                 dpll_reg = DPIO_PHY_STATUS;
1767                 break;
1768         default:
1769                 BUG();
1770         }
1771 
1772         if (intel_wait_for_register(dev_priv,
1773                                     dpll_reg, port_mask, expected_mask,
1774                                     1000))
1775                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1777 }
1778 
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1780                                            enum pipe pipe)
1781 {
1782         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1783                                                                 pipe);
1784         i915_reg_t reg;
1785         uint32_t val, pipeconf_val;
1786 
1787         /* Make sure PCH DPLL is enabled */
1788         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1789 
1790         /* FDI must be feeding us bits for PCH ports */
1791         assert_fdi_tx_enabled(dev_priv, pipe);
1792         assert_fdi_rx_enabled(dev_priv, pipe);
1793 
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Set the timing override bit before enabling the
1796                  * pch transcoder. */
1797                 reg = TRANS_CHICKEN2(pipe);
1798                 val = I915_READ(reg);
1799                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800                 I915_WRITE(reg, val);
1801         }
1802 
1803         reg = PCH_TRANSCONF(pipe);
1804         val = I915_READ(reg);
1805         pipeconf_val = I915_READ(PIPECONF(pipe));
1806 
1807         if (HAS_PCH_IBX(dev_priv)) {
1808                 /*
1809                  * Make the BPC in transcoder be consistent with
1810                  * that in pipeconf reg. For HDMI we must use 8bpc
1811                  * here for both 8bpc and 12bpc.
1812                  */
1813                 val &= ~PIPECONF_BPC_MASK;
1814                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1815                         val |= PIPECONF_8BPC;
1816                 else
1817                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1818         }
1819 
1820         val &= ~TRANS_INTERLACE_MASK;
1821         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1822                 if (HAS_PCH_IBX(dev_priv) &&
1823                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1824                         val |= TRANS_LEGACY_INTERLACED_ILK;
1825                 else
1826                         val |= TRANS_INTERLACED;
1827         else
1828                 val |= TRANS_PROGRESSIVE;
1829 
1830         I915_WRITE(reg, val | TRANS_ENABLE);
1831         if (intel_wait_for_register(dev_priv,
1832                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1833                                     100))
1834                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1835 }
1836 
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838                                       enum transcoder cpu_transcoder)
1839 {
1840         u32 val, pipeconf_val;
1841 
1842         /* FDI must be feeding us bits for PCH ports */
1843         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1844         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1845 
1846         /* Workaround: set timing override bit. */
1847         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1848         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1849         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1850 
1851         val = TRANS_ENABLE;
1852         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1853 
1854         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1855             PIPECONF_INTERLACED_ILK)
1856                 val |= TRANS_INTERLACED;
1857         else
1858                 val |= TRANS_PROGRESSIVE;
1859 
1860         I915_WRITE(LPT_TRANSCONF, val);
1861         if (intel_wait_for_register(dev_priv,
1862                                     LPT_TRANSCONF,
1863                                     TRANS_STATE_ENABLE,
1864                                     TRANS_STATE_ENABLE,
1865                                     100))
1866                 DRM_ERROR("Failed to enable PCH transcoder\n");
1867 }
1868 
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1870                                             enum pipe pipe)
1871 {
1872         i915_reg_t reg;
1873         uint32_t val;
1874 
1875         /* FDI relies on the transcoder */
1876         assert_fdi_tx_disabled(dev_priv, pipe);
1877         assert_fdi_rx_disabled(dev_priv, pipe);
1878 
1879         /* Ports must be off as well */
1880         assert_pch_ports_disabled(dev_priv, pipe);
1881 
1882         reg = PCH_TRANSCONF(pipe);
1883         val = I915_READ(reg);
1884         val &= ~TRANS_ENABLE;
1885         I915_WRITE(reg, val);
1886         /* wait for PCH transcoder off, transcoder state */
1887         if (intel_wait_for_register(dev_priv,
1888                                     reg, TRANS_STATE_ENABLE, 0,
1889                                     50))
1890                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1891 
1892         if (HAS_PCH_CPT(dev_priv)) {
1893                 /* Workaround: Clear the timing override chicken bit again. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899 }
1900 
1901 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1902 {
1903         u32 val;
1904 
1905         val = I915_READ(LPT_TRANSCONF);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(LPT_TRANSCONF, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (intel_wait_for_register(dev_priv,
1910                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1911                                     50))
1912                 DRM_ERROR("Failed to disable PCH transcoder\n");
1913 
1914         /* Workaround: clear timing override bit. */
1915         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1916         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1918 }
1919 
1920 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923 
1924         WARN_ON(!crtc->config->has_pch_encoder);
1925 
1926         if (HAS_PCH_LPT(dev_priv))
1927                 return TRANSCODER_A;
1928         else
1929                 return (enum transcoder) crtc->pipe;
1930 }
1931 
1932 /**
1933  * intel_enable_pipe - enable a pipe, asserting requirements
1934  * @crtc: crtc responsible for the pipe
1935  *
1936  * Enable @crtc's pipe, making sure that various hardware specific requirements
1937  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1938  */
1939 static void intel_enable_pipe(struct intel_crtc *crtc)
1940 {
1941         struct drm_device *dev = crtc->base.dev;
1942         struct drm_i915_private *dev_priv = to_i915(dev);
1943         enum pipe pipe = crtc->pipe;
1944         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1945         i915_reg_t reg;
1946         u32 val;
1947 
1948         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1949 
1950         assert_planes_disabled(dev_priv, pipe);
1951         assert_cursor_disabled(dev_priv, pipe);
1952         assert_sprites_disabled(dev_priv, pipe);
1953 
1954         /*
1955          * A pipe without a PLL won't actually be able to drive bits from
1956          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1957          * need the check.
1958          */
1959         if (HAS_GMCH_DISPLAY(dev_priv)) {
1960                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1961                         assert_dsi_pll_enabled(dev_priv);
1962                 else
1963                         assert_pll_enabled(dev_priv, pipe);
1964         } else {
1965                 if (crtc->config->has_pch_encoder) {
1966                         /* if driving the PCH, we need FDI enabled */
1967                         assert_fdi_rx_pll_enabled(dev_priv,
1968                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1969                         assert_fdi_tx_pll_enabled(dev_priv,
1970                                                   (enum pipe) cpu_transcoder);
1971                 }
1972                 /* FIXME: assert CPU port conditions for SNB+ */
1973         }
1974 
1975         reg = PIPECONF(cpu_transcoder);
1976         val = I915_READ(reg);
1977         if (val & PIPECONF_ENABLE) {
1978                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1979                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1980                 return;
1981         }
1982 
1983         I915_WRITE(reg, val | PIPECONF_ENABLE);
1984         POSTING_READ(reg);
1985 
1986         /*
1987          * Until the pipe starts DSL will read as 0, which would cause
1988          * an apparent vblank timestamp jump, which messes up also the
1989          * frame count when it's derived from the timestamps. So let's
1990          * wait for the pipe to start properly before we call
1991          * drm_crtc_vblank_on()
1992          */
1993         if (dev->max_vblank_count == 0 &&
1994             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1995                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1996 }
1997 
1998 /**
1999  * intel_disable_pipe - disable a pipe, asserting requirements
2000  * @crtc: crtc whose pipes is to be disabled
2001  *
2002  * Disable the pipe of @crtc, making sure that various hardware
2003  * specific requirements are met, if applicable, e.g. plane
2004  * disabled, panel fitter off, etc.
2005  *
2006  * Will wait until the pipe has shut down before returning.
2007  */
2008 static void intel_disable_pipe(struct intel_crtc *crtc)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2012         enum pipe pipe = crtc->pipe;
2013         i915_reg_t reg;
2014         u32 val;
2015 
2016         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2017 
2018         /*
2019          * Make sure planes won't keep trying to pump pixels to us,
2020          * or we might hang the display.
2021          */
2022         assert_planes_disabled(dev_priv, pipe);
2023         assert_cursor_disabled(dev_priv, pipe);
2024         assert_sprites_disabled(dev_priv, pipe);
2025 
2026         reg = PIPECONF(cpu_transcoder);
2027         val = I915_READ(reg);
2028         if ((val & PIPECONF_ENABLE) == 0)
2029                 return;
2030 
2031         /*
2032          * Double wide has implications for planes
2033          * so best keep it disabled when not needed.
2034          */
2035         if (crtc->config->double_wide)
2036                 val &= ~PIPECONF_DOUBLE_WIDE;
2037 
2038         /* Don't disable pipe or pipe PLLs if needed */
2039         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2040             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2041                 val &= ~PIPECONF_ENABLE;
2042 
2043         I915_WRITE(reg, val);
2044         if ((val & PIPECONF_ENABLE) == 0)
2045                 intel_wait_for_pipe_off(crtc);
2046 }
2047 
2048 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2049 {
2050         return IS_GEN2(dev_priv) ? 2048 : 4096;
2051 }
2052 
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2054                                            uint64_t fb_modifier, unsigned int cpp)
2055 {
2056         switch (fb_modifier) {
2057         case DRM_FORMAT_MOD_NONE:
2058                 return cpp;
2059         case I915_FORMAT_MOD_X_TILED:
2060                 if (IS_GEN2(dev_priv))
2061                         return 128;
2062                 else
2063                         return 512;
2064         case I915_FORMAT_MOD_Y_TILED:
2065                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2066                         return 128;
2067                 else
2068                         return 512;
2069         case I915_FORMAT_MOD_Yf_TILED:
2070                 switch (cpp) {
2071                 case 1:
2072                         return 64;
2073                 case 2:
2074                 case 4:
2075                         return 128;
2076                 case 8:
2077                 case 16:
2078                         return 256;
2079                 default:
2080                         MISSING_CASE(cpp);
2081                         return cpp;
2082                 }
2083                 break;
2084         default:
2085                 MISSING_CASE(fb_modifier);
2086                 return cpp;
2087         }
2088 }
2089 
2090 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2091                                uint64_t fb_modifier, unsigned int cpp)
2092 {
2093         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2094                 return 1;
2095         else
2096                 return intel_tile_size(dev_priv) /
2097                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2098 }
2099 
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2102                             unsigned int *tile_width,
2103                             unsigned int *tile_height,
2104                             uint64_t fb_modifier,
2105                             unsigned int cpp)
2106 {
2107         unsigned int tile_width_bytes =
2108                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2109 
2110         *tile_width = tile_width_bytes / cpp;
2111         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2112 }
2113 
2114 unsigned int
2115 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2116                       uint32_t pixel_format, uint64_t fb_modifier)
2117 {
2118         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2119         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2120 
2121         return ALIGN(height, tile_height);
2122 }
2123 
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2125 {
2126         unsigned int size = 0;
2127         int i;
2128 
2129         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2130                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2131 
2132         return size;
2133 }
2134 
2135 static void
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2137                         const struct drm_framebuffer *fb,
2138                         unsigned int rotation)
2139 {
2140         if (drm_rotation_90_or_270(rotation)) {
2141                 *view = i915_ggtt_view_rotated;
2142                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2143         } else {
2144                 *view = i915_ggtt_view_normal;
2145         }
2146 }
2147 
2148 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2149 {
2150         if (INTEL_INFO(dev_priv)->gen >= 9)
2151                 return 256 * 1024;
2152         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2153                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2154                 return 128 * 1024;
2155         else if (INTEL_INFO(dev_priv)->gen >= 4)
2156                 return 4 * 1024;
2157         else
2158                 return 0;
2159 }
2160 
2161 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2162                                          uint64_t fb_modifier)
2163 {
2164         switch (fb_modifier) {
2165         case DRM_FORMAT_MOD_NONE:
2166                 return intel_linear_alignment(dev_priv);
2167         case I915_FORMAT_MOD_X_TILED:
2168                 if (INTEL_INFO(dev_priv)->gen >= 9)
2169                         return 256 * 1024;
2170                 return 0;
2171         case I915_FORMAT_MOD_Y_TILED:
2172         case I915_FORMAT_MOD_Yf_TILED:
2173                 return 1 * 1024 * 1024;
2174         default:
2175                 MISSING_CASE(fb_modifier);
2176                 return 0;
2177         }
2178 }
2179 
2180 struct i915_vma *
2181 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2182 {
2183         struct drm_device *dev = fb->dev;
2184         struct drm_i915_private *dev_priv = to_i915(dev);
2185         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2186         struct i915_ggtt_view view;
2187         struct i915_vma *vma;
2188         u32 alignment;
2189 
2190         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2191 
2192         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2193 
2194         intel_fill_fb_ggtt_view(&view, fb, rotation);
2195 
2196         /* Note that the w/a also requires 64 PTE of padding following the
2197          * bo. We currently fill all unused PTE with the shadow page and so
2198          * we should always have valid PTE following the scanout preventing
2199          * the VT-d warning.
2200          */
2201         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2202                 alignment = 256 * 1024;
2203 
2204         /*
2205          * Global gtt pte registers are special registers which actually forward
2206          * writes to a chunk of system memory. Which means that there is no risk
2207          * that the register values disappear as soon as we call
2208          * intel_runtime_pm_put(), so it is correct to wrap only the
2209          * pin/unpin/fence and not more.
2210          */
2211         intel_runtime_pm_get(dev_priv);
2212 
2213         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2214         if (IS_ERR(vma))
2215                 goto err;
2216 
2217         if (i915_vma_is_map_and_fenceable(vma)) {
2218                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219                  * fence, whereas 965+ only requires a fence if using
2220                  * framebuffer compression.  For simplicity, we always, when
2221                  * possible, install a fence as the cost is not that onerous.
2222                  *
2223                  * If we fail to fence the tiled scanout, then either the
2224                  * modeset will reject the change (which is highly unlikely as
2225                  * the affected systems, all but one, do not have unmappable
2226                  * space) or we will not be able to enable full powersaving
2227                  * techniques (also likely not to apply due to various limits
2228                  * FBC and the like impose on the size of the buffer, which
2229                  * presumably we violated anyway with this unmappable buffer).
2230                  * Anyway, it is presumably better to stumble onwards with
2231                  * something and try to run the system in a "less than optimal"
2232                  * mode that matches the user configuration.
2233                  */
2234                 if (i915_vma_get_fence(vma) == 0)
2235                         i915_vma_pin_fence(vma);
2236         }
2237 
2238         i915_vma_get(vma);
2239 err:
2240         intel_runtime_pm_put(dev_priv);
2241         return vma;
2242 }
2243 
2244 void intel_unpin_fb_vma(struct i915_vma *vma)
2245 {
2246         lockdep_assert_held(&vma->vm->dev->struct_mutex);
2247 
2248         if (WARN_ON_ONCE(!vma))
2249                 return;
2250 
2251         i915_vma_unpin_fence(vma);
2252         i915_gem_object_unpin_from_display_plane(vma);
2253         i915_vma_put(vma);
2254 }
2255 
2256 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2257                           unsigned int rotation)
2258 {
2259         if (drm_rotation_90_or_270(rotation))
2260                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2261         else
2262                 return fb->pitches[plane];
2263 }
2264 
2265 /*
2266  * Convert the x/y offsets into a linear offset.
2267  * Only valid with 0/180 degree rotation, which is fine since linear
2268  * offset is only used with linear buffers on pre-hsw and tiled buffers
2269  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2270  */
2271 u32 intel_fb_xy_to_linear(int x, int y,
2272                           const struct intel_plane_state *state,
2273                           int plane)
2274 {
2275         const struct drm_framebuffer *fb = state->base.fb;
2276         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2277         unsigned int pitch = fb->pitches[plane];
2278 
2279         return y * pitch + x * cpp;
2280 }
2281 
2282 /*
2283  * Add the x/y offsets derived from fb->offsets[] to the user
2284  * specified plane src x/y offsets. The resulting x/y offsets
2285  * specify the start of scanout from the beginning of the gtt mapping.
2286  */
2287 void intel_add_fb_offsets(int *x, int *y,
2288                           const struct intel_plane_state *state,
2289                           int plane)
2290 
2291 {
2292         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2293         unsigned int rotation = state->base.rotation;
2294 
2295         if (drm_rotation_90_or_270(rotation)) {
2296                 *x += intel_fb->rotated[plane].x;
2297                 *y += intel_fb->rotated[plane].y;
2298         } else {
2299                 *x += intel_fb->normal[plane].x;
2300                 *y += intel_fb->normal[plane].y;
2301         }
2302 }
2303 
2304 /*
2305  * Input tile dimensions and pitch must already be
2306  * rotated to match x and y, and in pixel units.
2307  */
2308 static u32 _intel_adjust_tile_offset(int *x, int *y,
2309                                      unsigned int tile_width,
2310                                      unsigned int tile_height,
2311                                      unsigned int tile_size,
2312                                      unsigned int pitch_tiles,
2313                                      u32 old_offset,
2314                                      u32 new_offset)
2315 {
2316         unsigned int pitch_pixels = pitch_tiles * tile_width;
2317         unsigned int tiles;
2318 
2319         WARN_ON(old_offset & (tile_size - 1));
2320         WARN_ON(new_offset & (tile_size - 1));
2321         WARN_ON(new_offset > old_offset);
2322 
2323         tiles = (old_offset - new_offset) / tile_size;
2324 
2325         *y += tiles / pitch_tiles * tile_height;
2326         *x += tiles % pitch_tiles * tile_width;
2327 
2328         /* minimize x in case it got needlessly big */
2329         *y += *x / pitch_pixels * tile_height;
2330         *x %= pitch_pixels;
2331 
2332         return new_offset;
2333 }
2334 
2335 /*
2336  * Adjust the tile offset by moving the difference into
2337  * the x/y offsets.
2338  */
2339 static u32 intel_adjust_tile_offset(int *x, int *y,
2340                                     const struct intel_plane_state *state, int plane,
2341                                     u32 old_offset, u32 new_offset)
2342 {
2343         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2344         const struct drm_framebuffer *fb = state->base.fb;
2345         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2346         unsigned int rotation = state->base.rotation;
2347         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2348 
2349         WARN_ON(new_offset > old_offset);
2350 
2351         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2352                 unsigned int tile_size, tile_width, tile_height;
2353                 unsigned int pitch_tiles;
2354 
2355                 tile_size = intel_tile_size(dev_priv);
2356                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2357                                 fb->modifier, cpp);
2358 
2359                 if (drm_rotation_90_or_270(rotation)) {
2360                         pitch_tiles = pitch / tile_height;
2361                         swap(tile_width, tile_height);
2362                 } else {
2363                         pitch_tiles = pitch / (tile_width * cpp);
2364                 }
2365 
2366                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2367                                           tile_size, pitch_tiles,
2368                                           old_offset, new_offset);
2369         } else {
2370                 old_offset += *y * pitch + *x * cpp;
2371 
2372                 *y = (old_offset - new_offset) / pitch;
2373                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2374         }
2375 
2376         return new_offset;
2377 }
2378 
2379 /*
2380  * Computes the linear offset to the base tile and adjusts
2381  * x, y. bytes per pixel is assumed to be a power-of-two.
2382  *
2383  * In the 90/270 rotated case, x and y are assumed
2384  * to be already rotated to match the rotated GTT view, and
2385  * pitch is the tile_height aligned framebuffer height.
2386  *
2387  * This function is used when computing the derived information
2388  * under intel_framebuffer, so using any of that information
2389  * here is not allowed. Anything under drm_framebuffer can be
2390  * used. This is why the user has to pass in the pitch since it
2391  * is specified in the rotated orientation.
2392  */
2393 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2394                                       int *x, int *y,
2395                                       const struct drm_framebuffer *fb, int plane,
2396                                       unsigned int pitch,
2397                                       unsigned int rotation,
2398                                       u32 alignment)
2399 {
2400         uint64_t fb_modifier = fb->modifier;
2401         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2402         u32 offset, offset_aligned;
2403 
2404         if (alignment)
2405                 alignment--;
2406 
2407         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2408                 unsigned int tile_size, tile_width, tile_height;
2409                 unsigned int tile_rows, tiles, pitch_tiles;
2410 
2411                 tile_size = intel_tile_size(dev_priv);
2412                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2413                                 fb_modifier, cpp);
2414 
2415                 if (drm_rotation_90_or_270(rotation)) {
2416                         pitch_tiles = pitch / tile_height;
2417                         swap(tile_width, tile_height);
2418                 } else {
2419                         pitch_tiles = pitch / (tile_width * cpp);
2420                 }
2421 
2422                 tile_rows = *y / tile_height;
2423                 *y %= tile_height;
2424 
2425                 tiles = *x / tile_width;
2426                 *x %= tile_width;
2427 
2428                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2429                 offset_aligned = offset & ~alignment;
2430 
2431                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2432                                           tile_size, pitch_tiles,
2433                                           offset, offset_aligned);
2434         } else {
2435                 offset = *y * pitch + *x * cpp;
2436                 offset_aligned = offset & ~alignment;
2437 
2438                 *y = (offset & alignment) / pitch;
2439                 *x = ((offset & alignment) - *y * pitch) / cpp;
2440         }
2441 
2442         return offset_aligned;
2443 }
2444 
2445 u32 intel_compute_tile_offset(int *x, int *y,
2446                               const struct intel_plane_state *state,
2447                               int plane)
2448 {
2449         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2450         const struct drm_framebuffer *fb = state->base.fb;
2451         unsigned int rotation = state->base.rotation;
2452         int pitch = intel_fb_pitch(fb, plane, rotation);
2453         u32 alignment;
2454 
2455         /* AUX_DIST needs only 4K alignment */
2456         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2457                 alignment = 4096;
2458         else
2459                 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2460 
2461         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2462                                           rotation, alignment);
2463 }
2464 
2465 /* Convert the fb->offset[] linear offset into x/y offsets */
2466 static void intel_fb_offset_to_xy(int *x, int *y,
2467                                   const struct drm_framebuffer *fb, int plane)
2468 {
2469         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2470         unsigned int pitch = fb->pitches[plane];
2471         u32 linear_offset = fb->offsets[plane];
2472 
2473         *y = linear_offset / pitch;
2474         *x = linear_offset % pitch / cpp;
2475 }
2476 
2477 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2478 {
2479         switch (fb_modifier) {
2480         case I915_FORMAT_MOD_X_TILED:
2481                 return I915_TILING_X;
2482         case I915_FORMAT_MOD_Y_TILED:
2483                 return I915_TILING_Y;
2484         default:
2485                 return I915_TILING_NONE;
2486         }
2487 }
2488 
2489 static int
2490 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2491                    struct drm_framebuffer *fb)
2492 {
2493         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2494         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2495         u32 gtt_offset_rotated = 0;
2496         unsigned int max_size = 0;
2497         uint32_t format = fb->pixel_format;
2498         int i, num_planes = drm_format_num_planes(format);
2499         unsigned int tile_size = intel_tile_size(dev_priv);
2500 
2501         for (i = 0; i < num_planes; i++) {
2502                 unsigned int width, height;
2503                 unsigned int cpp, size;
2504                 u32 offset;
2505                 int x, y;
2506 
2507                 cpp = drm_format_plane_cpp(format, i);
2508                 width = drm_format_plane_width(fb->width, format, i);
2509                 height = drm_format_plane_height(fb->height, format, i);
2510 
2511                 intel_fb_offset_to_xy(&x, &y, fb, i);
2512 
2513                 /*
2514                  * The fence (if used) is aligned to the start of the object
2515                  * so having the framebuffer wrap around across the edge of the
2516                  * fenced region doesn't really work. We have no API to configure
2517                  * the fence start offset within the object (nor could we probably
2518                  * on gen2/3). So it's just easier if we just require that the
2519                  * fb layout agrees with the fence layout. We already check that the
2520                  * fb stride matches the fence stride elsewhere.
2521                  */
2522                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2523                     (x + width) * cpp > fb->pitches[i]) {
2524                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2525                                   i, fb->offsets[i]);
2526                         return -EINVAL;
2527                 }
2528 
2529                 /*
2530                  * First pixel of the framebuffer from
2531                  * the start of the normal gtt mapping.
2532                  */
2533                 intel_fb->normal[i].x = x;
2534                 intel_fb->normal[i].y = y;
2535 
2536                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2537                                                     fb, 0, fb->pitches[i],
2538                                                     DRM_ROTATE_0, tile_size);
2539                 offset /= tile_size;
2540 
2541                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2542                         unsigned int tile_width, tile_height;
2543                         unsigned int pitch_tiles;
2544                         struct drm_rect r;
2545 
2546                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2547                                         fb->modifier, cpp);
2548 
2549                         rot_info->plane[i].offset = offset;
2550                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2551                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2552                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2553 
2554                         intel_fb->rotated[i].pitch =
2555                                 rot_info->plane[i].height * tile_height;
2556 
2557                         /* how many tiles does this plane need */
2558                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2559                         /*
2560                          * If the plane isn't horizontally tile aligned,
2561                          * we need one more tile.
2562                          */
2563                         if (x != 0)
2564                                 size++;
2565 
2566                         /* rotate the x/y offsets to match the GTT view */
2567                         r.x1 = x;
2568                         r.y1 = y;
2569                         r.x2 = x + width;
2570                         r.y2 = y + height;
2571                         drm_rect_rotate(&r,
2572                                         rot_info->plane[i].width * tile_width,
2573                                         rot_info->plane[i].height * tile_height,
2574                                         DRM_ROTATE_270);
2575                         x = r.x1;
2576                         y = r.y1;
2577 
2578                         /* rotate the tile dimensions to match the GTT view */
2579                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2580                         swap(tile_width, tile_height);
2581 
2582                         /*
2583                          * We only keep the x/y offsets, so push all of the
2584                          * gtt offset into the x/y offsets.
2585                          */
2586                         _intel_adjust_tile_offset(&x, &y,
2587                                                   tile_width, tile_height,
2588                                                   tile_size, pitch_tiles,
2589                                                   gtt_offset_rotated * tile_size, 0);
2590 
2591                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2592 
2593                         /*
2594                          * First pixel of the framebuffer from
2595                          * the start of the rotated gtt mapping.
2596                          */
2597                         intel_fb->rotated[i].x = x;
2598                         intel_fb->rotated[i].y = y;
2599                 } else {
2600                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2601                                             x * cpp, tile_size);
2602                 }
2603 
2604                 /* how many tiles in total needed in the bo */
2605                 max_size = max(max_size, offset + size);
2606         }
2607 
2608         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2609                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2610                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2611                 return -EINVAL;
2612         }
2613 
2614         return 0;
2615 }
2616 
2617 static int i9xx_format_to_fourcc(int format)
2618 {
2619         switch (format) {
2620         case DISPPLANE_8BPP:
2621                 return DRM_FORMAT_C8;
2622         case DISPPLANE_BGRX555:
2623                 return DRM_FORMAT_XRGB1555;
2624         case DISPPLANE_BGRX565:
2625                 return DRM_FORMAT_RGB565;
2626         default:
2627         case DISPPLANE_BGRX888:
2628                 return DRM_FORMAT_XRGB8888;
2629         case DISPPLANE_RGBX888:
2630                 return DRM_FORMAT_XBGR8888;
2631         case DISPPLANE_BGRX101010:
2632                 return DRM_FORMAT_XRGB2101010;
2633         case DISPPLANE_RGBX101010:
2634                 return DRM_FORMAT_XBGR2101010;
2635         }
2636 }
2637 
2638 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2639 {
2640         switch (format) {
2641         case PLANE_CTL_FORMAT_RGB_565:
2642                 return DRM_FORMAT_RGB565;
2643         default:
2644         case PLANE_CTL_FORMAT_XRGB_8888:
2645                 if (rgb_order) {
2646                         if (alpha)
2647                                 return DRM_FORMAT_ABGR8888;
2648                         else
2649                                 return DRM_FORMAT_XBGR8888;
2650                 } else {
2651                         if (alpha)
2652                                 return DRM_FORMAT_ARGB8888;
2653                         else
2654                                 return DRM_FORMAT_XRGB8888;
2655                 }
2656         case PLANE_CTL_FORMAT_XRGB_2101010:
2657                 if (rgb_order)
2658                         return DRM_FORMAT_XBGR2101010;
2659                 else
2660                         return DRM_FORMAT_XRGB2101010;
2661         }
2662 }
2663 
2664 static bool
2665 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2666                               struct intel_initial_plane_config *plane_config)
2667 {
2668         struct drm_device *dev = crtc->base.dev;
2669         struct drm_i915_private *dev_priv = to_i915(dev);
2670         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2671         struct drm_i915_gem_object *obj = NULL;
2672         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2673         struct drm_framebuffer *fb = &plane_config->fb->base;
2674         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2675         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2676                                     PAGE_SIZE);
2677 
2678         size_aligned -= base_aligned;
2679 
2680         if (plane_config->size == 0)
2681                 return false;
2682 
2683         /* If the FB is too big, just don't use it since fbdev is not very
2684          * important and we should probably use that space with FBC or other
2685          * features. */
2686         if (size_aligned * 2 > ggtt->stolen_usable_size)
2687                 return false;
2688 
2689         mutex_lock(&dev->struct_mutex);
2690 
2691         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2692                                                              base_aligned,
2693                                                              base_aligned,
2694                                                              size_aligned);
2695         if (!obj) {
2696                 mutex_unlock(&dev->struct_mutex);
2697                 return false;
2698         }
2699 
2700         if (plane_config->tiling == I915_TILING_X)
2701                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2702 
2703         mode_cmd.pixel_format = fb->pixel_format;
2704         mode_cmd.width = fb->width;
2705         mode_cmd.height = fb->height;
2706         mode_cmd.pitches[0] = fb->pitches[0];
2707         mode_cmd.modifier[0] = fb->modifier;
2708         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2709 
2710         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2711                                    &mode_cmd, obj)) {
2712                 DRM_DEBUG_KMS("intel fb init failed\n");
2713                 goto out_unref_obj;
2714         }
2715 
2716         mutex_unlock(&dev->struct_mutex);
2717 
2718         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2719         return true;
2720 
2721 out_unref_obj:
2722         i915_gem_object_put(obj);
2723         mutex_unlock(&dev->struct_mutex);
2724         return false;
2725 }
2726 
2727 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2728 static void
2729 update_state_fb(struct drm_plane *plane)
2730 {
2731         if (plane->fb == plane->state->fb)
2732                 return;
2733 
2734         if (plane->state->fb)
2735                 drm_framebuffer_unreference(plane->state->fb);
2736         plane->state->fb = plane->fb;
2737         if (plane->state->fb)
2738                 drm_framebuffer_reference(plane->state->fb);
2739 }
2740 
2741 static void
2742 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2743                              struct intel_initial_plane_config *plane_config)
2744 {
2745         struct drm_device *dev = intel_crtc->base.dev;
2746         struct drm_i915_private *dev_priv = to_i915(dev);
2747         struct drm_crtc *c;
2748         struct drm_i915_gem_object *obj;
2749         struct drm_plane *primary = intel_crtc->base.primary;
2750         struct drm_plane_state *plane_state = primary->state;
2751         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2752         struct intel_plane *intel_plane = to_intel_plane(primary);
2753         struct intel_plane_state *intel_state =
2754                 to_intel_plane_state(plane_state);
2755         struct drm_framebuffer *fb;
2756 
2757         if (!plane_config->fb)
2758                 return;
2759 
2760         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2761                 fb = &plane_config->fb->base;
2762                 goto valid_fb;
2763         }
2764 
2765         kfree(plane_config->fb);
2766 
2767         /*
2768          * Failed to alloc the obj, check to see if we should share
2769          * an fb with another CRTC instead
2770          */
2771         for_each_crtc(dev, c) {
2772                 struct intel_plane_state *state;
2773 
2774                 if (c == &intel_crtc->base)
2775                         continue;
2776 
2777                 if (!to_intel_crtc(c)->active)
2778                         continue;
2779 
2780                 state = to_intel_plane_state(c->primary->state);
2781                 if (!state->vma)
2782                         continue;
2783 
2784                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2785                         fb = c->primary->fb;
2786                         drm_framebuffer_reference(fb);
2787                         goto valid_fb;
2788                 }
2789         }
2790 
2791         /*
2792          * We've failed to reconstruct the BIOS FB.  Current display state
2793          * indicates that the primary plane is visible, but has a NULL FB,
2794          * which will lead to problems later if we don't fix it up.  The
2795          * simplest solution is to just disable the primary plane now and
2796          * pretend the BIOS never had it enabled.
2797          */
2798         to_intel_plane_state(plane_state)->base.visible = false;
2799         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2800         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2801         intel_plane->disable_plane(primary, &intel_crtc->base);
2802 
2803         return;
2804 
2805 valid_fb:
2806         mutex_lock(&dev->struct_mutex);
2807         intel_state->vma =
2808                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2809         mutex_unlock(&dev->struct_mutex);
2810         if (IS_ERR(intel_state->vma)) {
2811                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2812                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2813 
2814                 intel_state->vma = NULL;
2815                 drm_framebuffer_unreference(fb);
2816                 return;
2817         }
2818 
2819         plane_state->src_x = 0;
2820         plane_state->src_y = 0;
2821         plane_state->src_w = fb->width << 16;
2822         plane_state->src_h = fb->height << 16;
2823 
2824         plane_state->crtc_x = 0;
2825         plane_state->crtc_y = 0;
2826         plane_state->crtc_w = fb->width;
2827         plane_state->crtc_h = fb->height;
2828 
2829         intel_state->base.src = drm_plane_state_src(plane_state);
2830         intel_state->base.dst = drm_plane_state_dest(plane_state);
2831 
2832         obj = intel_fb_obj(fb);
2833         if (i915_gem_object_is_tiled(obj))
2834                 dev_priv->preserve_bios_swizzle = true;
2835 
2836         drm_framebuffer_reference(fb);
2837         primary->fb = primary->state->fb = fb;
2838         primary->crtc = primary->state->crtc = &intel_crtc->base;
2839         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2840         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2841                   &obj->frontbuffer_bits);
2842 }
2843 
2844 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2845                                unsigned int rotation)
2846 {
2847         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2848 
2849         switch (fb->modifier) {
2850         case DRM_FORMAT_MOD_NONE:
2851         case I915_FORMAT_MOD_X_TILED:
2852                 switch (cpp) {
2853                 case 8:
2854                         return 4096;
2855                 case 4:
2856                 case 2:
2857                 case 1:
2858                         return 8192;
2859                 default:
2860                         MISSING_CASE(cpp);
2861                         break;
2862                 }
2863                 break;
2864         case I915_FORMAT_MOD_Y_TILED:
2865         case I915_FORMAT_MOD_Yf_TILED:
2866                 switch (cpp) {
2867                 case 8:
2868                         return 2048;
2869                 case 4:
2870                         return 4096;
2871                 case 2:
2872                 case 1:
2873                         return 8192;
2874                 default:
2875                         MISSING_CASE(cpp);
2876                         break;
2877                 }
2878                 break;
2879         default:
2880                 MISSING_CASE(fb->modifier);
2881         }
2882 
2883         return 2048;
2884 }
2885 
2886 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2887 {
2888         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2889         const struct drm_framebuffer *fb = plane_state->base.fb;
2890         unsigned int rotation = plane_state->base.rotation;
2891         int x = plane_state->base.src.x1 >> 16;
2892         int y = plane_state->base.src.y1 >> 16;
2893         int w = drm_rect_width(&plane_state->base.src) >> 16;
2894         int h = drm_rect_height(&plane_state->base.src) >> 16;
2895         int max_width = skl_max_plane_width(fb, 0, rotation);
2896         int max_height = 4096;
2897         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2898 
2899         if (w > max_width || h > max_height) {
2900                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2901                               w, h, max_width, max_height);
2902                 return -EINVAL;
2903         }
2904 
2905         intel_add_fb_offsets(&x, &y, plane_state, 0);
2906         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2907 
2908         alignment = intel_surf_alignment(dev_priv, fb->modifier);
2909 
2910         /*
2911          * AUX surface offset is specified as the distance from the
2912          * main surface offset, and it must be non-negative. Make
2913          * sure that is what we will get.
2914          */
2915         if (offset > aux_offset)
2916                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2917                                                   offset, aux_offset & ~(alignment - 1));
2918 
2919         /*
2920          * When using an X-tiled surface, the plane blows up
2921          * if the x offset + width exceed the stride.
2922          *
2923          * TODO: linear and Y-tiled seem fine, Yf untested,
2924          */
2925         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2926                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2927 
2928                 while ((x + w) * cpp > fb->pitches[0]) {
2929                         if (offset == 0) {
2930                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2931                                 return -EINVAL;
2932                         }
2933 
2934                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2935                                                           offset, offset - alignment);
2936                 }
2937         }
2938 
2939         plane_state->main.offset = offset;
2940         plane_state->main.x = x;
2941         plane_state->main.y = y;
2942 
2943         return 0;
2944 }
2945 
2946 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2947 {
2948         const struct drm_framebuffer *fb = plane_state->base.fb;
2949         unsigned int rotation = plane_state->base.rotation;
2950         int max_width = skl_max_plane_width(fb, 1, rotation);
2951         int max_height = 4096;
2952         int x = plane_state->base.src.x1 >> 17;
2953         int y = plane_state->base.src.y1 >> 17;
2954         int w = drm_rect_width(&plane_state->base.src) >> 17;
2955         int h = drm_rect_height(&plane_state->base.src) >> 17;
2956         u32 offset;
2957 
2958         intel_add_fb_offsets(&x, &y, plane_state, 1);
2959         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2960 
2961         /* FIXME not quite sure how/if these apply to the chroma plane */
2962         if (w > max_width || h > max_height) {
2963                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2964                               w, h, max_width, max_height);
2965                 return -EINVAL;
2966         }
2967 
2968         plane_state->aux.offset = offset;
2969         plane_state->aux.x = x;
2970         plane_state->aux.y = y;
2971 
2972         return 0;
2973 }
2974 
2975 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2976 {
2977         const struct drm_framebuffer *fb = plane_state->base.fb;
2978         unsigned int rotation = plane_state->base.rotation;
2979         int ret;
2980 
2981         if (!plane_state->base.visible)
2982                 return 0;
2983 
2984         /* Rotate src coordinates to match rotated GTT view */
2985         if (drm_rotation_90_or_270(rotation))
2986                 drm_rect_rotate(&plane_state->base.src,
2987                                 fb->width << 16, fb->height << 16,
2988                                 DRM_ROTATE_270);
2989 
2990         /*
2991          * Handle the AUX surface first since
2992          * the main surface setup depends on it.
2993          */
2994         if (fb->pixel_format == DRM_FORMAT_NV12) {
2995                 ret = skl_check_nv12_aux_surface(plane_state);
2996                 if (ret)
2997                         return ret;
2998         } else {
2999                 plane_state->aux.offset = ~0xfff;
3000                 plane_state->aux.x = 0;
3001                 plane_state->aux.y = 0;
3002         }
3003 
3004         ret = skl_check_main_surface(plane_state);
3005         if (ret)
3006                 return ret;
3007 
3008         return 0;
3009 }
3010 
3011 static void i9xx_update_primary_plane(struct drm_plane *primary,
3012                                       const struct intel_crtc_state *crtc_state,
3013                                       const struct intel_plane_state *plane_state)
3014 {
3015         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3017         struct drm_framebuffer *fb = plane_state->base.fb;
3018         int plane = intel_crtc->plane;
3019         u32 linear_offset;
3020         u32 dspcntr;
3021         i915_reg_t reg = DSPCNTR(plane);
3022         unsigned int rotation = plane_state->base.rotation;
3023         int x = plane_state->base.src.x1 >> 16;
3024         int y = plane_state->base.src.y1 >> 16;
3025 
3026         dspcntr = DISPPLANE_GAMMA_ENABLE;
3027 
3028         dspcntr |= DISPLAY_PLANE_ENABLE;
3029 
3030         if (INTEL_GEN(dev_priv) < 4) {
3031                 if (intel_crtc->pipe == PIPE_B)
3032                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3033 
3034                 /* pipesrc and dspsize control the size that is scaled from,
3035                  * which should always be the user's requested size.
3036                  */
3037                 I915_WRITE(DSPSIZE(plane),
3038                            ((crtc_state->pipe_src_h - 1) << 16) |
3039                            (crtc_state->pipe_src_w - 1));
3040                 I915_WRITE(DSPPOS(plane), 0);
3041         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3042                 I915_WRITE(PRIMSIZE(plane),
3043                            ((crtc_state->pipe_src_h - 1) << 16) |
3044                            (crtc_state->pipe_src_w - 1));
3045                 I915_WRITE(PRIMPOS(plane), 0);
3046                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3047         }
3048 
3049         switch (fb->pixel_format) {
3050         case DRM_FORMAT_C8:
3051                 dspcntr |= DISPPLANE_8BPP;
3052                 break;
3053         case DRM_FORMAT_XRGB1555:
3054                 dspcntr |= DISPPLANE_BGRX555;
3055                 break;
3056         case DRM_FORMAT_RGB565:
3057                 dspcntr |= DISPPLANE_BGRX565;
3058                 break;
3059         case DRM_FORMAT_XRGB8888:
3060                 dspcntr |= DISPPLANE_BGRX888;
3061                 break;
3062         case DRM_FORMAT_XBGR8888:
3063                 dspcntr |= DISPPLANE_RGBX888;
3064                 break;
3065         case DRM_FORMAT_XRGB2101010:
3066                 dspcntr |= DISPPLANE_BGRX101010;
3067                 break;
3068         case DRM_FORMAT_XBGR2101010:
3069                 dspcntr |= DISPPLANE_RGBX101010;
3070                 break;
3071         default:
3072                 BUG();
3073         }
3074 
3075         if (INTEL_GEN(dev_priv) >= 4 &&
3076             fb->modifier == I915_FORMAT_MOD_X_TILED)
3077                 dspcntr |= DISPPLANE_TILED;
3078 
3079         if (rotation & DRM_ROTATE_180)
3080                 dspcntr |= DISPPLANE_ROTATE_180;
3081 
3082         if (rotation & DRM_REFLECT_X)
3083                 dspcntr |= DISPPLANE_MIRROR;
3084 
3085         if (IS_G4X(dev_priv))
3086                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3087 
3088         intel_add_fb_offsets(&x, &y, plane_state, 0);
3089 
3090         if (INTEL_GEN(dev_priv) >= 4)
3091                 intel_crtc->dspaddr_offset =
3092                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3093 
3094         if (rotation & DRM_ROTATE_180) {
3095                 x += crtc_state->pipe_src_w - 1;
3096                 y += crtc_state->pipe_src_h - 1;
3097         } else if (rotation & DRM_REFLECT_X) {
3098                 x += crtc_state->pipe_src_w - 1;
3099         }
3100 
3101         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3102 
3103         if (INTEL_GEN(dev_priv) < 4)
3104                 intel_crtc->dspaddr_offset = linear_offset;
3105 
3106         intel_crtc->adjusted_x = x;
3107         intel_crtc->adjusted_y = y;
3108 
3109         I915_WRITE(reg, dspcntr);
3110 
3111         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3112         if (INTEL_GEN(dev_priv) >= 4) {
3113                 I915_WRITE(DSPSURF(plane),
3114                            intel_plane_ggtt_offset(plane_state) +
3115                            intel_crtc->dspaddr_offset);
3116                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3117                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3118         } else {
3119                 I915_WRITE(DSPADDR(plane),
3120                            intel_plane_ggtt_offset(plane_state) +
3121                            intel_crtc->dspaddr_offset);
3122         }
3123         POSTING_READ(reg);
3124 }
3125 
3126 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3127                                        struct drm_crtc *crtc)
3128 {
3129         struct drm_device *dev = crtc->dev;
3130         struct drm_i915_private *dev_priv = to_i915(dev);
3131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3132         int plane = intel_crtc->plane;
3133 
3134         I915_WRITE(DSPCNTR(plane), 0);
3135         if (INTEL_INFO(dev_priv)->gen >= 4)
3136                 I915_WRITE(DSPSURF(plane), 0);
3137         else
3138                 I915_WRITE(DSPADDR(plane), 0);
3139         POSTING_READ(DSPCNTR(plane));
3140 }
3141 
3142 static void ironlake_update_primary_plane(struct drm_plane *primary,
3143                                           const struct intel_crtc_state *crtc_state,
3144                                           const struct intel_plane_state *plane_state)
3145 {
3146         struct drm_device *dev = primary->dev;
3147         struct drm_i915_private *dev_priv = to_i915(dev);
3148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3149         struct drm_framebuffer *fb = plane_state->base.fb;
3150         int plane = intel_crtc->plane;
3151         u32 linear_offset;
3152         u32 dspcntr;
3153         i915_reg_t reg = DSPCNTR(plane);
3154         unsigned int rotation = plane_state->base.rotation;
3155         int x = plane_state->base.src.x1 >> 16;
3156         int y = plane_state->base.src.y1 >> 16;
3157 
3158         dspcntr = DISPPLANE_GAMMA_ENABLE;
3159         dspcntr |= DISPLAY_PLANE_ENABLE;
3160 
3161         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3162                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3163 
3164         switch (fb->pixel_format) {
3165         case DRM_FORMAT_C8:
3166                 dspcntr |= DISPPLANE_8BPP;
3167                 break;
3168         case DRM_FORMAT_RGB565:
3169                 dspcntr |= DISPPLANE_BGRX565;
3170                 break;
3171         case DRM_FORMAT_XRGB8888:
3172                 dspcntr |= DISPPLANE_BGRX888;
3173                 break;
3174         case DRM_FORMAT_XBGR8888:
3175                 dspcntr |= DISPPLANE_RGBX888;
3176                 break;
3177         case DRM_FORMAT_XRGB2101010:
3178                 dspcntr |= DISPPLANE_BGRX101010;
3179                 break;
3180         case DRM_FORMAT_XBGR2101010:
3181                 dspcntr |= DISPPLANE_RGBX101010;
3182                 break;
3183         default:
3184                 BUG();
3185         }
3186 
3187         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3188                 dspcntr |= DISPPLANE_TILED;
3189 
3190         if (rotation & DRM_ROTATE_180)
3191                 dspcntr |= DISPPLANE_ROTATE_180;
3192 
3193         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3194                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3195 
3196         intel_add_fb_offsets(&x, &y, plane_state, 0);
3197 
3198         intel_crtc->dspaddr_offset =
3199                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3200 
3201         /* HSW+ does this automagically in hardware */
3202         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3203             rotation & DRM_ROTATE_180) {
3204                 x += crtc_state->pipe_src_w - 1;
3205                 y += crtc_state->pipe_src_h - 1;
3206         }
3207 
3208         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3209 
3210         intel_crtc->adjusted_x = x;
3211         intel_crtc->adjusted_y = y;
3212 
3213         I915_WRITE(reg, dspcntr);
3214 
3215         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3216         I915_WRITE(DSPSURF(plane),
3217                    intel_plane_ggtt_offset(plane_state) +
3218                    intel_crtc->dspaddr_offset);
3219         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3220                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3221         } else {
3222                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3223                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3224         }
3225         POSTING_READ(reg);
3226 }
3227 
3228 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3229                               uint64_t fb_modifier, uint32_t pixel_format)
3230 {
3231         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3232                 return 64;
3233         } else {
3234                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3235 
3236                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3237         }
3238 }
3239 
3240 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3241 {
3242         struct drm_device *dev = intel_crtc->base.dev;
3243         struct drm_i915_private *dev_priv = to_i915(dev);
3244 
3245         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3246         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3247         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3248 }
3249 
3250 /*
3251  * This function detaches (aka. unbinds) unused scalers in hardware
3252  */
3253 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3254 {
3255         struct intel_crtc_scaler_state *scaler_state;
3256         int i;
3257 
3258         scaler_state = &intel_crtc->config->scaler_state;
3259 
3260         /* loop through and disable scalers that aren't in use */
3261         for (i = 0; i < intel_crtc->num_scalers; i++) {
3262                 if (!scaler_state->scalers[i].in_use)
3263                         skl_detach_scaler(intel_crtc, i);
3264         }
3265 }
3266 
3267 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3268                      unsigned int rotation)
3269 {
3270         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3271         u32 stride = intel_fb_pitch(fb, plane, rotation);
3272 
3273         /*
3274          * The stride is either expressed as a multiple of 64 bytes chunks for
3275          * linear buffers or in number of tiles for tiled buffers.
3276          */
3277         if (drm_rotation_90_or_270(rotation)) {
3278                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3279 
3280                 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3281         } else {
3282                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3283                                                     fb->pixel_format);
3284         }
3285 
3286         return stride;
3287 }
3288 
3289 u32 skl_plane_ctl_format(uint32_t pixel_format)
3290 {
3291         switch (pixel_format) {
3292         case DRM_FORMAT_C8:
3293                 return PLANE_CTL_FORMAT_INDEXED;
3294         case DRM_FORMAT_RGB565:
3295                 return PLANE_CTL_FORMAT_RGB_565;
3296         case DRM_FORMAT_XBGR8888:
3297                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3298         case DRM_FORMAT_XRGB8888:
3299                 return PLANE_CTL_FORMAT_XRGB_8888;
3300         /*
3301          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3302          * to be already pre-multiplied. We need to add a knob (or a different
3303          * DRM_FORMAT) for user-space to configure that.
3304          */
3305         case DRM_FORMAT_ABGR8888:
3306                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3307                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3308         case DRM_FORMAT_ARGB8888:
3309                 return PLANE_CTL_FORMAT_XRGB_8888 |
3310                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3311         case DRM_FORMAT_XRGB2101010:
3312                 return PLANE_CTL_FORMAT_XRGB_2101010;
3313         case DRM_FORMAT_XBGR2101010:
3314                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3315         case DRM_FORMAT_YUYV:
3316                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3317         case DRM_FORMAT_YVYU:
3318                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3319         case DRM_FORMAT_UYVY:
3320                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3321         case DRM_FORMAT_VYUY:
3322                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3323         default:
3324                 MISSING_CASE(pixel_format);
3325         }
3326 
3327         return 0;
3328 }
3329 
3330 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3331 {
3332         switch (fb_modifier) {
3333         case DRM_FORMAT_MOD_NONE:
3334                 break;
3335         case I915_FORMAT_MOD_X_TILED:
3336                 return PLANE_CTL_TILED_X;
3337         case I915_FORMAT_MOD_Y_TILED:
3338                 return PLANE_CTL_TILED_Y;
3339         case I915_FORMAT_MOD_Yf_TILED:
3340                 return PLANE_CTL_TILED_YF;
3341         default:
3342                 MISSING_CASE(fb_modifier);
3343         }
3344 
3345         return 0;
3346 }
3347 
3348 u32 skl_plane_ctl_rotation(unsigned int rotation)
3349 {
3350         switch (rotation) {
3351         case DRM_ROTATE_0:
3352                 break;
3353         /*
3354          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3355          * while i915 HW rotation is clockwise, thats why this swapping.
3356          */
3357         case DRM_ROTATE_90:
3358                 return PLANE_CTL_ROTATE_270;
3359         case DRM_ROTATE_180:
3360                 return PLANE_CTL_ROTATE_180;
3361         case DRM_ROTATE_270:
3362                 return PLANE_CTL_ROTATE_90;
3363         default:
3364                 MISSING_CASE(rotation);
3365         }
3366 
3367         return 0;
3368 }
3369 
3370 static void skylake_update_primary_plane(struct drm_plane *plane,
3371                                          const struct intel_crtc_state *crtc_state,
3372                                          const struct intel_plane_state *plane_state)
3373 {
3374         struct drm_device *dev = plane->dev;
3375         struct drm_i915_private *dev_priv = to_i915(dev);
3376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3377         struct drm_framebuffer *fb = plane_state->base.fb;
3378         int pipe = intel_crtc->pipe;
3379         u32 plane_ctl;
3380         unsigned int rotation = plane_state->base.rotation;
3381         u32 stride = skl_plane_stride(fb, 0, rotation);
3382         u32 surf_addr = plane_state->main.offset;
3383         int scaler_id = plane_state->scaler_id;
3384         int src_x = plane_state->main.x;
3385         int src_y = plane_state->main.y;
3386         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3387         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3388         int dst_x = plane_state->base.dst.x1;
3389         int dst_y = plane_state->base.dst.y1;
3390         int dst_w = drm_rect_width(&plane_state->base.dst);
3391         int dst_h = drm_rect_height(&plane_state->base.dst);
3392 
3393         plane_ctl = PLANE_CTL_ENABLE |
3394                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3395                     PLANE_CTL_PIPE_CSC_ENABLE;
3396 
3397         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3398         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3399         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3400         plane_ctl |= skl_plane_ctl_rotation(rotation);
3401 
3402         /* Sizes are 0 based */
3403         src_w--;
3404         src_h--;
3405         dst_w--;
3406         dst_h--;
3407 
3408         intel_crtc->dspaddr_offset = surf_addr;
3409 
3410         intel_crtc->adjusted_x = src_x;
3411         intel_crtc->adjusted_y = src_y;
3412 
3413         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3414         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3415         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3416         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3417 
3418         if (scaler_id >= 0) {
3419                 uint32_t ps_ctrl = 0;
3420 
3421                 WARN_ON(!dst_w || !dst_h);
3422                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3423                         crtc_state->scaler_state.scalers[scaler_id].mode;
3424                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3425                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3426                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3427                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3428                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3429         } else {
3430                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3431         }
3432 
3433         I915_WRITE(PLANE_SURF(pipe, 0),
3434                    intel_plane_ggtt_offset(plane_state) + surf_addr);
3435 
3436         POSTING_READ(PLANE_SURF(pipe, 0));
3437 }
3438 
3439 static void skylake_disable_primary_plane(struct drm_plane *primary,
3440                                           struct drm_crtc *crtc)
3441 {
3442         struct drm_device *dev = crtc->dev;
3443         struct drm_i915_private *dev_priv = to_i915(dev);
3444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445         int pipe = intel_crtc->pipe;
3446 
3447         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3448         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3449         POSTING_READ(PLANE_SURF(pipe, 0));
3450 }
3451 
3452 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3453 static int
3454 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3455                            int x, int y, enum mode_set_atomic state)
3456 {
3457         /* Support for kgdboc is disabled, this needs a major rework. */
3458         DRM_ERROR("legacy panic handler not supported any more.\n");
3459 
3460         return -ENODEV;
3461 }
3462 
3463 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3464 {
3465         struct intel_crtc *crtc;
3466 
3467         for_each_intel_crtc(&dev_priv->drm, crtc)
3468                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3469 }
3470 
3471 static void intel_update_primary_planes(struct drm_device *dev)
3472 {
3473         struct drm_crtc *crtc;
3474 
3475         for_each_crtc(dev, crtc) {
3476                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3477                 struct intel_plane_state *plane_state =
3478                         to_intel_plane_state(plane->base.state);
3479 
3480                 if (plane_state->base.visible)
3481                         plane->update_plane(&plane->base,
3482                                             to_intel_crtc_state(crtc->state),
3483                                             plane_state);
3484         }
3485 }
3486 
3487 static int
3488 __intel_display_resume(struct drm_device *dev,
3489                        struct drm_atomic_state *state)
3490 {
3491         struct drm_crtc_state *crtc_state;
3492         struct drm_crtc *crtc;
3493         int i, ret;
3494 
3495         intel_modeset_setup_hw_state(dev);
3496         i915_redisable_vga(to_i915(dev));
3497 
3498         if (!state)
3499                 return 0;
3500 
3501         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3502                 /*
3503                  * Force recalculation even if we restore
3504                  * current state. With fast modeset this may not result
3505                  * in a modeset when the state is compatible.
3506                  */
3507                 crtc_state->mode_changed = true;
3508         }
3509 
3510         /* ignore any reset values/BIOS leftovers in the WM registers */
3511         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3512 
3513         ret = drm_atomic_commit(state);
3514 
3515         WARN_ON(ret == -EDEADLK);
3516         return ret;
3517 }
3518 
3519 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3520 {
3521         return intel_has_gpu_reset(dev_priv) &&
3522                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3523 }
3524 
3525 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3526 {
3527         struct drm_device *dev = &dev_priv->drm;
3528         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3529         struct drm_atomic_state *state;
3530         int ret;
3531 
3532         /*
3533          * Need mode_config.mutex so that we don't
3534          * trample ongoing ->detect() and whatnot.
3535          */
3536         mutex_lock(&dev->mode_config.mutex);
3537         drm_modeset_acquire_init(ctx, 0);
3538         while (1) {
3539                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3540                 if (ret != -EDEADLK)
3541                         break;
3542 
3543                 drm_modeset_backoff(ctx);
3544         }
3545 
3546         /* reset doesn't touch the display, but flips might get nuked anyway, */
3547         if (!i915.force_reset_modeset_test &&
3548             !gpu_reset_clobbers_display(dev_priv))
3549                 return;
3550 
3551         /*
3552          * Disabling the crtcs gracefully seems nicer. Also the
3553          * g33 docs say we should at least disable all the planes.
3554          */
3555         state = drm_atomic_helper_duplicate_state(dev, ctx);
3556         if (IS_ERR(state)) {
3557                 ret = PTR_ERR(state);
3558                 state = NULL;
3559                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3560                 goto err;
3561         }
3562 
3563         ret = drm_atomic_helper_disable_all(dev, ctx);
3564         if (ret) {
3565                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3566                 goto err;
3567         }
3568 
3569         dev_priv->modeset_restore_state = state;
3570         state->acquire_ctx = ctx;
3571         return;
3572 
3573 err:
3574         drm_atomic_state_put(state);
3575 }
3576 
3577 void intel_finish_reset(struct drm_i915_private *dev_priv)
3578 {
3579         struct drm_device *dev = &dev_priv->drm;
3580         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3581         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3582         int ret;
3583 
3584         /*
3585          * Flips in the rings will be nuked by the reset,
3586          * so complete all pending flips so that user space
3587          * will get its events and not get stuck.
3588          */
3589         intel_complete_page_flips(dev_priv);
3590 
3591         dev_priv->modeset_restore_state = NULL;
3592 
3593         /* reset doesn't touch the display */
3594         if (!gpu_reset_clobbers_display(dev_priv)) {
3595                 if (!state) {
3596                         /*
3597                          * Flips in the rings have been nuked by the reset,
3598                          * so update the base address of all primary
3599                          * planes to the the last fb to make sure we're
3600                          * showing the correct fb after a reset.
3601                          *
3602                          * FIXME: Atomic will make this obsolete since we won't schedule
3603                          * CS-based flips (which might get lost in gpu resets) any more.
3604                          */
3605                         intel_update_primary_planes(dev);
3606                 } else {
3607                         ret = __intel_display_resume(dev, state);
3608                         if (ret)
3609                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3610                 }
3611         } else {
3612                 /*
3613                  * The display has been reset as well,
3614                  * so need a full re-initialization.
3615                  */
3616                 intel_runtime_pm_disable_interrupts(dev_priv);
3617                 intel_runtime_pm_enable_interrupts(dev_priv);
3618 
3619                 intel_pps_unlock_regs_wa(dev_priv);
3620                 intel_modeset_init_hw(dev);
3621 
3622                 spin_lock_irq(&dev_priv->irq_lock);
3623                 if (dev_priv->display.hpd_irq_setup)
3624                         dev_priv->display.hpd_irq_setup(dev_priv);
3625                 spin_unlock_irq(&dev_priv->irq_lock);
3626 
3627                 ret = __intel_display_resume(dev, state);
3628                 if (ret)
3629                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3630 
3631                 intel_hpd_init(dev_priv);
3632         }
3633 
3634         if (state)
3635                 drm_atomic_state_put(state);
3636         drm_modeset_drop_locks(ctx);
3637         drm_modeset_acquire_fini(ctx);
3638         mutex_unlock(&dev->mode_config.mutex);
3639 }
3640 
3641 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3642 {
3643         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3644 
3645         if (i915_reset_in_progress(error))
3646                 return true;
3647 
3648         if (crtc->reset_count != i915_reset_count(error))
3649                 return true;
3650 
3651         return false;
3652 }
3653 
3654 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3655 {
3656         struct drm_device *dev = crtc->dev;
3657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658         bool pending;
3659 
3660         if (abort_flip_on_reset(intel_crtc))
3661                 return false;
3662 
3663         spin_lock_irq(&dev->event_lock);
3664         pending = to_intel_crtc(crtc)->flip_work != NULL;
3665         spin_unlock_irq(&dev->event_lock);
3666 
3667         return pending;
3668 }
3669 
3670 static void intel_update_pipe_config(struct intel_crtc *crtc,
3671                                      struct intel_crtc_state *old_crtc_state)
3672 {
3673         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3674         struct intel_crtc_state *pipe_config =
3675                 to_intel_crtc_state(crtc->base.state);
3676 
3677         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3678         crtc->base.mode = crtc->base.state->mode;
3679 
3680         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3681                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3682                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3683 
3684         /*
3685          * Update pipe size and adjust fitter if needed: the reason for this is
3686          * that in compute_mode_changes we check the native mode (not the pfit
3687          * mode) to see if we can flip rather than do a full mode set. In the
3688          * fastboot case, we'll flip, but if we don't update the pipesrc and
3689          * pfit state, we'll end up with a big fb scanned out into the wrong
3690          * sized surface.
3691          */
3692 
3693         I915_WRITE(PIPESRC(crtc->pipe),
3694                    ((pipe_config->pipe_src_w - 1) << 16) |
3695                    (pipe_config->pipe_src_h - 1));
3696 
3697         /* on skylake this is done by detaching scalers */
3698         if (INTEL_GEN(dev_priv) >= 9) {
3699                 skl_detach_scalers(crtc);
3700 
3701                 if (pipe_config->pch_pfit.enabled)
3702                         skylake_pfit_enable(crtc);
3703         } else if (HAS_PCH_SPLIT(dev_priv)) {
3704                 if (pipe_config->pch_pfit.enabled)
3705                         ironlake_pfit_enable(crtc);
3706                 else if (old_crtc_state->pch_pfit.enabled)
3707                         ironlake_pfit_disable(crtc, true);
3708         }
3709 }
3710 
3711 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3712 {
3713         struct drm_device *dev = crtc->dev;
3714         struct drm_i915_private *dev_priv = to_i915(dev);
3715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716         int pipe = intel_crtc->pipe;
3717         i915_reg_t reg;
3718         u32 temp;
3719 
3720         /* enable normal train */
3721         reg = FDI_TX_CTL(pipe);
3722         temp = I915_READ(reg);
3723         if (IS_IVYBRIDGE(dev_priv)) {
3724                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3725                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3726         } else {
3727                 temp &= ~FDI_LINK_TRAIN_NONE;
3728                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3729         }
3730         I915_WRITE(reg, temp);
3731 
3732         reg = FDI_RX_CTL(pipe);
3733         temp = I915_READ(reg);
3734         if (HAS_PCH_CPT(dev_priv)) {
3735                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3736                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3737         } else {
3738                 temp &= ~FDI_LINK_TRAIN_NONE;
3739                 temp |= FDI_LINK_TRAIN_NONE;
3740         }
3741         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3742 
3743         /* wait one idle pattern time */
3744         POSTING_READ(reg);
3745         udelay(1000);
3746 
3747         /* IVB wants error correction enabled */
3748         if (IS_IVYBRIDGE(dev_priv))
3749                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3750                            FDI_FE_ERRC_ENABLE);
3751 }
3752 
3753 /* The FDI link training functions for ILK/Ibexpeak. */
3754 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3755 {
3756         struct drm_device *dev = crtc->dev;
3757         struct drm_i915_private *dev_priv = to_i915(dev);
3758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759         int pipe = intel_crtc->pipe;
3760         i915_reg_t reg;
3761         u32 temp, tries;
3762 
3763         /* FDI needs bits from pipe first */
3764         assert_pipe_enabled(dev_priv, pipe);
3765 
3766         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3767            for train result */
3768         reg = FDI_RX_IMR(pipe);
3769         temp = I915_READ(reg);
3770         temp &= ~FDI_RX_SYMBOL_LOCK;
3771         temp &= ~FDI_RX_BIT_LOCK;
3772         I915_WRITE(reg, temp);
3773         I915_READ(reg);
3774         udelay(150);
3775 
3776         /* enable CPU FDI TX and PCH FDI RX */
3777         reg = FDI_TX_CTL(pipe);
3778         temp = I915_READ(reg);
3779         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3780         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3781         temp &= ~FDI_LINK_TRAIN_NONE;
3782         temp |= FDI_LINK_TRAIN_PATTERN_1;
3783         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3784 
3785         reg = FDI_RX_CTL(pipe);
3786         temp = I915_READ(reg);
3787         temp &= ~FDI_LINK_TRAIN_NONE;
3788         temp |= FDI_LINK_TRAIN_PATTERN_1;
3789         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3790 
3791         POSTING_READ(reg);
3792         udelay(150);
3793 
3794         /* Ironlake workaround, enable clock pointer after FDI enable*/
3795         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3796         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3797                    FDI_RX_PHASE_SYNC_POINTER_EN);
3798 
3799         reg = FDI_RX_IIR(pipe);
3800         for (tries = 0; tries < 5; tries++) {
3801                 temp = I915_READ(reg);
3802                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3803 
3804                 if ((temp & FDI_RX_BIT_LOCK)) {
3805                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3806                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3807                         break;
3808                 }
3809         }
3810         if (tries == 5)
3811                 DRM_ERROR("FDI train 1 fail!\n");
3812 
3813         /* Train 2 */
3814         reg = FDI_TX_CTL(pipe);
3815         temp = I915_READ(reg);
3816         temp &= ~FDI_LINK_TRAIN_NONE;
3817         temp |= FDI_LINK_TRAIN_PATTERN_2;
3818         I915_WRITE(reg, temp);
3819 
3820         reg = FDI_RX_CTL(pipe);
3821         temp = I915_READ(reg);
3822         temp &= ~FDI_LINK_TRAIN_NONE;
3823         temp |= FDI_LINK_TRAIN_PATTERN_2;
3824         I915_WRITE(reg, temp);
3825 
3826         POSTING_READ(reg);
3827         udelay(150);
3828 
3829         reg = FDI_RX_IIR(pipe);
3830         for (tries = 0; tries < 5; tries++) {
3831                 temp = I915_READ(reg);
3832                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3833 
3834                 if (temp & FDI_RX_SYMBOL_LOCK) {
3835                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3836                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3837                         break;
3838                 }
3839         }
3840         if (tries == 5)
3841                 DRM_ERROR("FDI train 2 fail!\n");
3842 
3843         DRM_DEBUG_KMS("FDI train done\n");
3844 
3845 }
3846 
3847 static const int snb_b_fdi_train_param[] = {
3848         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3849         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3850         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3851         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3852 };
3853 
3854 /* The FDI link training functions for SNB/Cougarpoint. */
3855 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3856 {
3857         struct drm_device *dev = crtc->dev;
3858         struct drm_i915_private *dev_priv = to_i915(dev);
3859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3860         int pipe = intel_crtc->pipe;
3861         i915_reg_t reg;
3862         u32 temp, i, retry;
3863 
3864         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3865            for train result */
3866         reg = FDI_RX_IMR(pipe);
3867         temp = I915_READ(reg);
3868         temp &= ~FDI_RX_SYMBOL_LOCK;
3869         temp &= ~FDI_RX_BIT_LOCK;
3870         I915_WRITE(reg, temp);
3871 
3872         POSTING_READ(reg);
3873         udelay(150);
3874 
3875         /* enable CPU FDI TX and PCH FDI RX */
3876         reg = FDI_TX_CTL(pipe);
3877         temp = I915_READ(reg);
3878         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3879         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3880         temp &= ~FDI_LINK_TRAIN_NONE;
3881         temp |= FDI_LINK_TRAIN_PATTERN_1;
3882         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3883         /* SNB-B */
3884         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3885         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3886 
3887         I915_WRITE(FDI_RX_MISC(pipe),
3888                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3889 
3890         reg = FDI_RX_CTL(pipe);
3891         temp = I915_READ(reg);
3892         if (HAS_PCH_CPT(dev_priv)) {
3893                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3894                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3895         } else {
3896                 temp &= ~FDI_LINK_TRAIN_NONE;
3897                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3898         }
3899         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3900 
3901         POSTING_READ(reg);
3902         udelay(150);
3903 
3904         for (i = 0; i < 4; i++) {
3905                 reg = FDI_TX_CTL(pipe);
3906                 temp = I915_READ(reg);
3907                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908                 temp |= snb_b_fdi_train_param[i];
3909                 I915_WRITE(reg, temp);
3910 
3911                 POSTING_READ(reg);
3912                 udelay(500);
3913 
3914                 for (retry = 0; retry < 5; retry++) {
3915                         reg = FDI_RX_IIR(pipe);
3916                         temp = I915_READ(reg);
3917                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3918                         if (temp & FDI_RX_BIT_LOCK) {
3919                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3920                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3921                                 break;
3922                         }
3923                         udelay(50);
3924                 }
3925                 if (retry < 5)
3926                         break;
3927         }
3928         if (i == 4)
3929                 DRM_ERROR("FDI train 1 fail!\n");
3930 
3931         /* Train 2 */
3932         reg = FDI_TX_CTL(pipe);
3933         temp = I915_READ(reg);
3934         temp &= ~FDI_LINK_TRAIN_NONE;
3935         temp |= FDI_LINK_TRAIN_PATTERN_2;
3936         if (IS_GEN6(dev_priv)) {
3937                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3938                 /* SNB-B */
3939                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3940         }
3941         I915_WRITE(reg, temp);
3942 
3943         reg = FDI_RX_CTL(pipe);
3944         temp = I915_READ(reg);
3945         if (HAS_PCH_CPT(dev_priv)) {
3946                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3947                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3948         } else {
3949                 temp &= ~FDI_LINK_TRAIN_NONE;
3950                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3951         }
3952         I915_WRITE(reg, temp);
3953 
3954         POSTING_READ(reg);
3955         udelay(150);
3956 
3957         for (i = 0; i < 4; i++) {
3958                 reg = FDI_TX_CTL(pipe);
3959                 temp = I915_READ(reg);
3960                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3961                 temp |= snb_b_fdi_train_param[i];
3962                 I915_WRITE(reg, temp);
3963 
3964                 POSTING_READ(reg);
3965                 udelay(500);
3966 
3967                 for (retry = 0; retry < 5; retry++) {
3968                         reg = FDI_RX_IIR(pipe);
3969                         temp = I915_READ(reg);
3970                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3971                         if (temp & FDI_RX_SYMBOL_LOCK) {
3972                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3973                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3974                                 break;
3975                         }
3976                         udelay(50);
3977                 }
3978                 if (retry < 5)
3979                         break;
3980         }
3981         if (i == 4)
3982                 DRM_ERROR("FDI train 2 fail!\n");
3983 
3984         DRM_DEBUG_KMS("FDI train done.\n");
3985 }
3986 
3987 /* Manual link training for Ivy Bridge A0 parts */
3988 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3989 {
3990         struct drm_device *dev = crtc->dev;
3991         struct drm_i915_private *dev_priv = to_i915(dev);
3992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3993         int pipe = intel_crtc->pipe;
3994         i915_reg_t reg;
3995         u32 temp, i, j;
3996 
3997         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3998            for train result */
3999         reg = FDI_RX_IMR(pipe);
4000         temp = I915_READ(reg);
4001         temp &= ~FDI_RX_SYMBOL_LOCK;
4002         temp &= ~FDI_RX_BIT_LOCK;
4003         I915_WRITE(reg, temp);
4004 
4005         POSTING_READ(reg);
4006         udelay(150);
4007 
4008         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4009                       I915_READ(FDI_RX_IIR(pipe)));
4010 
4011         /* Try each vswing and preemphasis setting twice before moving on */
4012         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4013                 /* disable first in case we need to retry */
4014                 reg = FDI_TX_CTL(pipe);
4015                 temp = I915_READ(reg);
4016                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4017                 temp &= ~FDI_TX_ENABLE;
4018                 I915_WRITE(reg, temp);
4019 
4020                 reg = FDI_RX_CTL(pipe);
4021                 temp = I915_READ(reg);
4022                 temp &= ~FDI_LINK_TRAIN_AUTO;
4023                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4024                 temp &= ~FDI_RX_ENABLE;
4025                 I915_WRITE(reg, temp);
4026 
4027                 /* enable CPU FDI TX and PCH FDI RX */
4028                 reg = FDI_TX_CTL(pipe);
4029                 temp = I915_READ(reg);
4030                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4031                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4032                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4033                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4034                 temp |= snb_b_fdi_train_param[j/2];
4035                 temp |= FDI_COMPOSITE_SYNC;
4036                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4037 
4038                 I915_WRITE(FDI_RX_MISC(pipe),
4039                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4040 
4041                 reg = FDI_RX_CTL(pipe);
4042                 temp = I915_READ(reg);
4043                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4044                 temp |= FDI_COMPOSITE_SYNC;
4045                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4046 
4047                 POSTING_READ(reg);
4048                 udelay(1); /* should be 0.5us */
4049 
4050                 for (i = 0; i < 4; i++) {
4051                         reg = FDI_RX_IIR(pipe);
4052                         temp = I915_READ(reg);
4053                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4054 
4055                         if (temp & FDI_RX_BIT_LOCK ||
4056                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4057                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4058                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4059                                               i);
4060                                 break;
4061                         }
4062                         udelay(1); /* should be 0.5us */
4063                 }
4064                 if (i == 4) {
4065                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4066                         continue;
4067                 }
4068 
4069                 /* Train 2 */
4070                 reg = FDI_TX_CTL(pipe);
4071                 temp = I915_READ(reg);
4072                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4073                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4074                 I915_WRITE(reg, temp);
4075 
4076                 reg = FDI_RX_CTL(pipe);
4077                 temp = I915_READ(reg);
4078                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4079                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4080                 I915_WRITE(reg, temp);
4081 
4082                 POSTING_READ(reg);
4083                 udelay(2); /* should be 1.5us */
4084 
4085                 for (i = 0; i < 4; i++) {
4086                         reg = FDI_RX_IIR(pipe);
4087                         temp = I915_READ(reg);
4088                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4089 
4090                         if (temp & FDI_RX_SYMBOL_LOCK ||
4091                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4092                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4093                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4094                                               i);
4095                                 goto train_done;
4096                         }
4097                         udelay(2); /* should be 1.5us */
4098                 }
4099                 if (i == 4)
4100                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4101         }
4102 
4103 train_done:
4104         DRM_DEBUG_KMS("FDI train done.\n");
4105 }
4106 
4107 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4108 {
4109         struct drm_device *dev = intel_crtc->base.dev;
4110         struct drm_i915_private *dev_priv = to_i915(dev);
4111         int pipe = intel_crtc->pipe;
4112         i915_reg_t reg;
4113         u32 temp;
4114 
4115         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4116         reg = FDI_RX_CTL(pipe);
4117         temp = I915_READ(reg);
4118         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4119         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4120         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4121         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4122 
4123         POSTING_READ(reg);
4124         udelay(200);
4125 
4126         /* Switch from Rawclk to PCDclk */
4127         temp = I915_READ(reg);
4128         I915_WRITE(reg, temp | FDI_PCDCLK);
4129 
4130         POSTING_READ(reg);
4131         udelay(200);
4132 
4133         /* Enable CPU FDI TX PLL, always on for Ironlake */
4134         reg = FDI_TX_CTL(pipe);
4135         temp = I915_READ(reg);
4136         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4137                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4138 
4139                 POSTING_READ(reg);
4140                 udelay(100);
4141         }
4142 }
4143 
4144 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4145 {
4146         struct drm_device *dev = intel_crtc->base.dev;
4147         struct drm_i915_private *dev_priv = to_i915(dev);
4148         int pipe = intel_crtc->pipe;
4149         i915_reg_t reg;
4150         u32 temp;
4151 
4152         /* Switch from PCDclk to Rawclk */
4153         reg = FDI_RX_CTL(pipe);
4154         temp = I915_READ(reg);
4155         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4156 
4157         /* Disable CPU FDI TX PLL */
4158         reg = FDI_TX_CTL(pipe);
4159         temp = I915_READ(reg);
4160         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4161 
4162         POSTING_READ(reg);
4163         udelay(100);
4164 
4165         reg = FDI_RX_CTL(pipe);
4166         temp = I915_READ(reg);
4167         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4168 
4169         /* Wait for the clocks to turn off. */
4170         POSTING_READ(reg);
4171         udelay(100);
4172 }
4173 
4174 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4175 {
4176         struct drm_device *dev = crtc->dev;
4177         struct drm_i915_private *dev_priv = to_i915(dev);
4178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179         int pipe = intel_crtc->pipe;
4180         i915_reg_t reg;
4181         u32 temp;
4182 
4183         /* disable CPU FDI tx and PCH FDI rx */
4184         reg = FDI_TX_CTL(pipe);
4185         temp = I915_READ(reg);
4186         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4187         POSTING_READ(reg);
4188 
4189         reg = FDI_RX_CTL(pipe);
4190         temp = I915_READ(reg);
4191         temp &= ~(0x7 << 16);
4192         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4193         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4194 
4195         POSTING_READ(reg);
4196         udelay(100);
4197 
4198         /* Ironlake workaround, disable clock pointer after downing FDI */
4199         if (HAS_PCH_IBX(dev_priv))
4200                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4201 
4202         /* still set train pattern 1 */
4203         reg = FDI_TX_CTL(pipe);
4204         temp = I915_READ(reg);
4205         temp &= ~FDI_LINK_TRAIN_NONE;
4206         temp |= FDI_LINK_TRAIN_PATTERN_1;
4207         I915_WRITE(reg, temp);
4208 
4209         reg = FDI_RX_CTL(pipe);
4210         temp = I915_READ(reg);
4211         if (HAS_PCH_CPT(dev_priv)) {
4212                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4213                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4214         } else {
4215                 temp &= ~FDI_LINK_TRAIN_NONE;
4216                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4217         }
4218         /* BPC in FDI rx is consistent with that in PIPECONF */
4219         temp &= ~(0x07 << 16);
4220         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4221         I915_WRITE(reg, temp);
4222 
4223         POSTING_READ(reg);
4224         udelay(100);
4225 }
4226 
4227 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4228 {
4229         struct drm_i915_private *dev_priv = to_i915(dev);
4230         struct intel_crtc *crtc;
4231 
4232         /* Note that we don't need to be called with mode_config.lock here
4233          * as our list of CRTC objects is static for the lifetime of the
4234          * device and so cannot disappear as we iterate. Similarly, we can
4235          * happily treat the predicates as racy, atomic checks as userspace
4236          * cannot claim and pin a new fb without at least acquring the
4237          * struct_mutex and so serialising with us.
4238          */
4239         for_each_intel_crtc(dev, crtc) {
4240                 if (atomic_read(&crtc->unpin_work_count) == 0)
4241                         continue;
4242 
4243                 if (crtc->flip_work)
4244                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4245 
4246                 return true;
4247         }
4248 
4249         return false;
4250 }
4251 
4252 static void page_flip_completed(struct intel_crtc *intel_crtc)
4253 {
4254         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4255         struct intel_flip_work *work = intel_crtc->flip_work;
4256 
4257         intel_crtc->flip_work = NULL;
4258 
4259         if (work->event)
4260                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4261 
4262         drm_crtc_vblank_put(&intel_crtc->base);
4263 
4264         wake_up_all(&dev_priv->pending_flip_queue);
4265         trace_i915_flip_complete(intel_crtc->plane,
4266                                  work->pending_flip_obj);
4267 
4268         queue_work(dev_priv->wq, &work->unpin_work);
4269 }
4270 
4271 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4272 {
4273         struct drm_device *dev = crtc->dev;
4274         struct drm_i915_private *dev_priv = to_i915(dev);
4275         long ret;
4276 
4277         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4278 
4279         ret = wait_event_interruptible_timeout(
4280                                         dev_priv->pending_flip_queue,
4281                                         !intel_crtc_has_pending_flip(crtc),
4282                                         60*HZ);
4283 
4284         if (ret < 0)
4285                 return ret;
4286 
4287         if (ret == 0) {
4288                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289                 struct intel_flip_work *work;
4290 
4291                 spin_lock_irq(&dev->event_lock);
4292                 work = intel_crtc->flip_work;
4293                 if (work && !is_mmio_work(work)) {
4294                         WARN_ONCE(1, "Removing stuck page flip\n");
4295                         page_flip_completed(intel_crtc);
4296                 }
4297                 spin_unlock_irq(&dev->event_lock);
4298         }
4299 
4300         return 0;
4301 }
4302 
4303 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4304 {
4305         u32 temp;
4306 
4307         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4308 
4309         mutex_lock(&dev_priv->sb_lock);
4310 
4311         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4312         temp |= SBI_SSCCTL_DISABLE;
4313         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4314 
4315         mutex_unlock(&dev_priv->sb_lock);
4316 }
4317 
4318 /* Program iCLKIP clock to the desired frequency */
4319 static void lpt_program_iclkip(struct drm_crtc *crtc)
4320 {
4321         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4322         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4323         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4324         u32 temp;
4325 
4326         lpt_disable_iclkip(dev_priv);
4327 
4328         /* The iCLK virtual clock root frequency is in MHz,
4329          * but the adjusted_mode->crtc_clock in in KHz. To get the
4330          * divisors, it is necessary to divide one by another, so we
4331          * convert the virtual clock precision to KHz here for higher
4332          * precision.
4333          */
4334         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4335                 u32 iclk_virtual_root_freq = 172800 * 1000;
4336                 u32 iclk_pi_range = 64;
4337                 u32 desired_divisor;
4338 
4339                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4340                                                     clock << auxdiv);
4341                 divsel = (desired_divisor / iclk_pi_range) - 2;
4342                 phaseinc = desired_divisor % iclk_pi_range;
4343 
4344                 /*
4345                  * Near 20MHz is a corner case which is
4346                  * out of range for the 7-bit divisor
4347                  */
4348                 if (divsel <= 0x7f)
4349                         break;
4350         }
4351 
4352         /* This should not happen with any sane values */
4353         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4354                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4355         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4356                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4357 
4358         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4359                         clock,
4360                         auxdiv,
4361                         divsel,
4362                         phasedir,
4363                         phaseinc);
4364 
4365         mutex_lock(&dev_priv->sb_lock);
4366 
4367         /* Program SSCDIVINTPHASE6 */
4368         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4369         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4370         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4371         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4372         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4373         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4374         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4375         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4376 
4377         /* Program SSCAUXDIV */
4378         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4379         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4380         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4381         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4382 
4383         /* Enable modulator and associated divider */
4384         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4385         temp &= ~SBI_SSCCTL_DISABLE;
4386         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4387 
4388         mutex_unlock(&dev_priv->sb_lock);
4389 
4390         /* Wait for initialization time */
4391         udelay(24);
4392 
4393         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4394 }
4395 
4396 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4397 {
4398         u32 divsel, phaseinc, auxdiv;
4399         u32 iclk_virtual_root_freq = 172800 * 1000;
4400         u32 iclk_pi_range = 64;
4401         u32 desired_divisor;
4402         u32 temp;
4403 
4404         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4405                 return 0;
4406 
4407         mutex_lock(&dev_priv->sb_lock);
4408 
4409         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4410         if (temp & SBI_SSCCTL_DISABLE) {
4411                 mutex_unlock(&dev_priv->sb_lock);
4412                 return 0;
4413         }
4414 
4415         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4416         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4417                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4418         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4419                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4420 
4421         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4422         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4423                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4424 
4425         mutex_unlock(&dev_priv->sb_lock);
4426 
4427         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4428 
4429         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4430                                  desired_divisor << auxdiv);
4431 }
4432 
4433 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4434                                                 enum pipe pch_transcoder)
4435 {
4436         struct drm_device *dev = crtc->base.dev;
4437         struct drm_i915_private *dev_priv = to_i915(dev);
4438         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4439 
4440         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4441                    I915_READ(HTOTAL(cpu_transcoder)));
4442         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4443                    I915_READ(HBLANK(cpu_transcoder)));
4444         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4445                    I915_READ(HSYNC(cpu_transcoder)));
4446 
4447         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4448                    I915_READ(VTOTAL(cpu_transcoder)));
4449         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4450                    I915_READ(VBLANK(cpu_transcoder)));
4451         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4452                    I915_READ(VSYNC(cpu_transcoder)));
4453         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4454                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4455 }
4456 
4457 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4458 {
4459         struct drm_i915_private *dev_priv = to_i915(dev);
4460         uint32_t temp;
4461 
4462         temp = I915_READ(SOUTH_CHICKEN1);
4463         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4464                 return;
4465 
4466         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4467         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4468 
4469         temp &= ~FDI_BC_BIFURCATION_SELECT;
4470         if (enable)
4471                 temp |= FDI_BC_BIFURCATION_SELECT;
4472 
4473         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4474         I915_WRITE(SOUTH_CHICKEN1, temp);
4475         POSTING_READ(SOUTH_CHICKEN1);
4476 }
4477 
4478 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4479 {
4480         struct drm_device *dev = intel_crtc->base.dev;
4481 
4482         switch (intel_crtc->pipe) {
4483         case PIPE_A:
4484                 break;
4485         case PIPE_B:
4486                 if (intel_crtc->config->fdi_lanes > 2)
4487                         cpt_set_fdi_bc_bifurcation(dev, false);
4488                 else
4489                         cpt_set_fdi_bc_bifurcation(dev, true);
4490 
4491                 break;
4492         case PIPE_C:
4493                 cpt_set_fdi_bc_bifurcation(dev, true);
4494 
4495                 break;
4496         default:
4497                 BUG();
4498         }
4499 }
4500 
4501 /* Return which DP Port should be selected for Transcoder DP control */
4502 static enum port
4503 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4504 {
4505         struct drm_device *dev = crtc->dev;
4506         struct intel_encoder *encoder;
4507 
4508         for_each_encoder_on_crtc(dev, crtc, encoder) {
4509                 if (encoder->type == INTEL_OUTPUT_DP ||
4510                     encoder->type == INTEL_OUTPUT_EDP)
4511                         return enc_to_dig_port(&encoder->base)->port;
4512         }
4513 
4514         return -1;
4515 }
4516 
4517 /*
4518  * Enable PCH resources required for PCH ports:
4519  *   - PCH PLLs
4520  *   - FDI training & RX/TX
4521  *   - update transcoder timings
4522  *   - DP transcoding bits
4523  *   - transcoder
4524  */
4525 static void ironlake_pch_enable(struct drm_crtc *crtc)
4526 {
4527         struct drm_device *dev = crtc->dev;
4528         struct drm_i915_private *dev_priv = to_i915(dev);
4529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4530         int pipe = intel_crtc->pipe;
4531         u32 temp;
4532 
4533         assert_pch_transcoder_disabled(dev_priv, pipe);
4534 
4535         if (IS_IVYBRIDGE(dev_priv))
4536                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4537 
4538         /* Write the TU size bits before fdi link training, so that error
4539          * detection works. */
4540         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4541                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4542 
4543         /* For PCH output, training FDI link */
4544         dev_priv->display.fdi_link_train(crtc);
4545 
4546         /* We need to program the right clock selection before writing the pixel
4547          * mutliplier into the DPLL. */
4548         if (HAS_PCH_CPT(dev_priv)) {
4549                 u32 sel;
4550 
4551                 temp = I915_READ(PCH_DPLL_SEL);
4552                 temp |= TRANS_DPLL_ENABLE(pipe);
4553                 sel = TRANS_DPLLB_SEL(pipe);
4554                 if (intel_crtc->config->shared_dpll ==
4555                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4556                         temp |= sel;
4557                 else
4558                         temp &= ~sel;
4559                 I915_WRITE(PCH_DPLL_SEL, temp);
4560         }
4561 
4562         /* XXX: pch pll's can be enabled any time before we enable the PCH
4563          * transcoder, and we actually should do this to not upset any PCH
4564          * transcoder that already use the clock when we share it.
4565          *
4566          * Note that enable_shared_dpll tries to do the right thing, but
4567          * get_shared_dpll unconditionally resets the pll - we need that to have
4568          * the right LVDS enable sequence. */
4569         intel_enable_shared_dpll(intel_crtc);
4570 
4571         /* set transcoder timing, panel must allow it */
4572         assert_panel_unlocked(dev_priv, pipe);
4573         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4574 
4575         intel_fdi_normal_train(crtc);
4576 
4577         /* For PCH DP, enable TRANS_DP_CTL */
4578         if (HAS_PCH_CPT(dev_priv) &&
4579             intel_crtc_has_dp_encoder(intel_crtc->config)) {
4580                 const struct drm_display_mode *adjusted_mode =
4581                         &intel_crtc->config->base.adjusted_mode;
4582                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4583                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4584                 temp = I915_READ(reg);
4585                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4586                           TRANS_DP_SYNC_MASK |
4587                           TRANS_DP_BPC_MASK);
4588                 temp |= TRANS_DP_OUTPUT_ENABLE;
4589                 temp |= bpc << 9; /* same format but at 11:9 */
4590 
4591                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4592                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4593                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4594                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4595 
4596                 switch (intel_trans_dp_port_sel(crtc)) {
4597                 case PORT_B:
4598                         temp |= TRANS_DP_PORT_SEL_B;
4599                         break;
4600                 case PORT_C:
4601                         temp |= TRANS_DP_PORT_SEL_C;
4602                         break;
4603                 case PORT_D:
4604                         temp |= TRANS_DP_PORT_SEL_D;
4605                         break;
4606                 default:
4607                         BUG();
4608                 }
4609 
4610                 I915_WRITE(reg, temp);
4611         }
4612 
4613         ironlake_enable_pch_transcoder(dev_priv, pipe);
4614 }
4615 
4616 static void lpt_pch_enable(struct drm_crtc *crtc)
4617 {
4618         struct drm_device *dev = crtc->dev;
4619         struct drm_i915_private *dev_priv = to_i915(dev);
4620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4621         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4622 
4623         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4624 
4625         lpt_program_iclkip(crtc);
4626 
4627         /* Set transcoder timing. */
4628         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4629 
4630         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4631 }
4632 
4633 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4634 {
4635         struct drm_i915_private *dev_priv = to_i915(dev);
4636         i915_reg_t dslreg = PIPEDSL(pipe);
4637         u32 temp;
4638 
4639         temp = I915_READ(dslreg);
4640         udelay(500);
4641         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4642                 if (wait_for(I915_READ(dslreg) != temp, 5))
4643                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4644         }
4645 }
4646 
4647 static int
4648 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4649                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4650                   int src_w, int src_h, int dst_w, int dst_h)
4651 {
4652         struct intel_crtc_scaler_state *scaler_state =
4653                 &crtc_state->scaler_state;
4654         struct intel_crtc *intel_crtc =
4655                 to_intel_crtc(crtc_state->base.crtc);
4656         int need_scaling;
4657 
4658         need_scaling = drm_rotation_90_or_270(rotation) ?
4659                 (src_h != dst_w || src_w != dst_h):
4660                 (src_w != dst_w || src_h != dst_h);
4661 
4662         /*
4663          * if plane is being disabled or scaler is no more required or force detach
4664          *  - free scaler binded to this plane/crtc
4665          *  - in order to do this, update crtc->scaler_usage
4666          *
4667          * Here scaler state in crtc_state is set free so that
4668          * scaler can be assigned to other user. Actual register
4669          * update to free the scaler is done in plane/panel-fit programming.
4670          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4671          */
4672         if (force_detach || !need_scaling) {
4673                 if (*scaler_id >= 0) {
4674                         scaler_state->scaler_users &= ~(1 << scaler_user);
4675                         scaler_state->scalers[*scaler_id].in_use = 0;
4676 
4677                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4678                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4679                                 intel_crtc->pipe, scaler_user, *scaler_id,
4680                                 scaler_state->scaler_users);
4681                         *scaler_id = -1;
4682                 }
4683                 return 0;
4684         }
4685 
4686         /* range checks */
4687         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4688                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4689 
4690                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4691                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4692                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4693                         "size is out of scaler range\n",
4694                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4695                 return -EINVAL;
4696         }
4697 
4698         /* mark this plane as a scaler user in crtc_state */
4699         scaler_state->scaler_users |= (1 << scaler_user);
4700         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4701                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4702                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4703                 scaler_state->scaler_users);
4704 
4705         return 0;
4706 }
4707 
4708 /**
4709  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4710  *
4711  * @state: crtc's scaler state
4712  *
4713  * Return
4714  *     0 - scaler_usage updated successfully
4715  *    error - requested scaling cannot be supported or other error condition
4716  */
4717 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4718 {
4719         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4720 
4721         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4722                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4723                 state->pipe_src_w, state->pipe_src_h,
4724                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4725 }
4726 
4727 /**
4728  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4729  *
4730  * @state: crtc's scaler state
4731  * @plane_state: atomic plane state to update
4732  *
4733  * Return
4734  *     0 - scaler_usage updated successfully
4735  *    error - requested scaling cannot be supported or other error condition
4736  */
4737 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4738                                    struct intel_plane_state *plane_state)
4739 {
4740 
4741         struct intel_plane *intel_plane =
4742                 to_intel_plane(plane_state->base.plane);
4743         struct drm_framebuffer *fb = plane_state->base.fb;
4744         int ret;
4745 
4746         bool force_detach = !fb || !plane_state->base.visible;
4747 
4748         ret = skl_update_scaler(crtc_state, force_detach,
4749                                 drm_plane_index(&intel_plane->base),
4750                                 &plane_state->scaler_id,
4751                                 plane_state->base.rotation,
4752                                 drm_rect_width(&plane_state->base.src) >> 16,
4753                                 drm_rect_height(&plane_state->base.src) >> 16,
4754                                 drm_rect_width(&plane_state->base.dst),
4755                                 drm_rect_height(&plane_state->base.dst));
4756 
4757         if (ret || plane_state->scaler_id < 0)
4758                 return ret;
4759 
4760         /* check colorkey */
4761         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4762                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4763                               intel_plane->base.base.id,
4764                               intel_plane->base.name);
4765                 return -EINVAL;
4766         }
4767 
4768         /* Check src format */
4769         switch (fb->pixel_format) {
4770         case DRM_FORMAT_RGB565:
4771         case DRM_FORMAT_XBGR8888:
4772         case DRM_FORMAT_XRGB8888:
4773         case DRM_FORMAT_ABGR8888:
4774         case DRM_FORMAT_ARGB8888:
4775         case DRM_FORMAT_XRGB2101010:
4776         case DRM_FORMAT_XBGR2101010:
4777         case DRM_FORMAT_YUYV:
4778         case DRM_FORMAT_YVYU:
4779         case DRM_FORMAT_UYVY:
4780         case DRM_FORMAT_VYUY:
4781                 break;
4782         default:
4783                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4784                               intel_plane->base.base.id, intel_plane->base.name,
4785                               fb->base.id, fb->pixel_format);
4786                 return -EINVAL;
4787         }
4788 
4789         return 0;
4790 }
4791 
4792 static void skylake_scaler_disable(struct intel_crtc *crtc)
4793 {
4794         int i;
4795 
4796         for (i = 0; i < crtc->num_scalers; i++)
4797                 skl_detach_scaler(crtc, i);
4798 }
4799 
4800 static void skylake_pfit_enable(struct intel_crtc *crtc)
4801 {
4802         struct drm_device *dev = crtc->base.dev;
4803         struct drm_i915_private *dev_priv = to_i915(dev);
4804         int pipe = crtc->pipe;
4805         struct intel_crtc_scaler_state *scaler_state =
4806                 &crtc->config->scaler_state;
4807 
4808         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4809 
4810         if (crtc->config->pch_pfit.enabled) {
4811                 int id;
4812 
4813                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4814                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4815                         return;
4816                 }
4817 
4818                 id = scaler_state->scaler_id;
4819                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4820                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4821                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4822                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4823 
4824                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4825         }
4826 }
4827 
4828 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4829 {
4830         struct drm_device *dev = crtc->base.dev;
4831         struct drm_i915_private *dev_priv = to_i915(dev);
4832         int pipe = crtc->pipe;
4833 
4834         if (crtc->config->pch_pfit.enabled) {
4835                 /* Force use of hard-coded filter coefficients
4836                  * as some pre-programmed values are broken,
4837                  * e.g. x201.
4838                  */
4839                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4840                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4841                                                  PF_PIPE_SEL_IVB(pipe));
4842                 else
4843                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4844                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4845                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4846         }
4847 }
4848 
4849 void hsw_enable_ips(struct intel_crtc *crtc)
4850 {
4851         struct drm_device *dev = crtc->base.dev;
4852         struct drm_i915_private *dev_priv = to_i915(dev);
4853 
4854         if (!crtc->config->ips_enabled)
4855                 return;
4856 
4857         /*
4858          * We can only enable IPS after we enable a plane and wait for a vblank
4859          * This function is called from post_plane_update, which is run after
4860          * a vblank wait.
4861          */
4862 
4863         assert_plane_enabled(dev_priv, crtc->plane);
4864         if (IS_BROADWELL(dev_priv)) {
4865                 mutex_lock(&dev_priv->rps.hw_lock);
4866                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4867                 mutex_unlock(&dev_priv->rps.hw_lock);
4868                 /* Quoting Art Runyan: "its not safe to expect any particular
4869                  * value in IPS_CTL bit 31 after enabling IPS through the
4870                  * mailbox." Moreover, the mailbox may return a bogus state,
4871                  * so we need to just enable it and continue on.
4872                  */
4873         } else {
4874                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4875                 /* The bit only becomes 1 in the next vblank, so this wait here
4876                  * is essentially intel_wait_for_vblank. If we don't have this
4877                  * and don't wait for vblanks until the end of crtc_enable, then
4878                  * the HW state readout code will complain that the expected
4879                  * IPS_CTL value is not the one we read. */
4880                 if (intel_wait_for_register(dev_priv,
4881                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4882                                             50))
4883                         DRM_ERROR("Timed out waiting for IPS enable\n");
4884         }
4885 }
4886 
4887 void hsw_disable_ips(struct intel_crtc *crtc)
4888 {
4889         struct drm_device *dev = crtc->base.dev;
4890         struct drm_i915_private *dev_priv = to_i915(dev);
4891 
4892         if (!crtc->config->ips_enabled)
4893                 return;
4894 
4895         assert_plane_enabled(dev_priv, crtc->plane);
4896         if (IS_BROADWELL(dev_priv)) {
4897                 mutex_lock(&dev_priv->rps.hw_lock);
4898                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4899                 mutex_unlock(&dev_priv->rps.hw_lock);
4900                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4901                 if (intel_wait_for_register(dev_priv,
4902                                             IPS_CTL, IPS_ENABLE, 0,
4903                                             42))
4904                         DRM_ERROR("Timed out waiting for IPS disable\n");
4905         } else {
4906                 I915_WRITE(IPS_CTL, 0);
4907                 POSTING_READ(IPS_CTL);
4908         }
4909 
4910         /* We need to wait for a vblank before we can disable the plane. */
4911         intel_wait_for_vblank(dev_priv, crtc->pipe);
4912 }
4913 
4914 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4915 {
4916         if (intel_crtc->overlay) {
4917                 struct drm_device *dev = intel_crtc->base.dev;
4918                 struct drm_i915_private *dev_priv = to_i915(dev);
4919 
4920                 mutex_lock(&dev->struct_mutex);
4921                 dev_priv->mm.interruptible = false;
4922                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4923                 dev_priv->mm.interruptible = true;
4924                 mutex_unlock(&dev->struct_mutex);
4925         }
4926 
4927         /* Let userspace switch the overlay on again. In most cases userspace
4928          * has to recompute where to put it anyway.
4929          */
4930 }
4931 
4932 /**
4933  * intel_post_enable_primary - Perform operations after enabling primary plane
4934  * @crtc: the CRTC whose primary plane was just enabled
4935  *
4936  * Performs potentially sleeping operations that must be done after the primary
4937  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4938  * called due to an explicit primary plane update, or due to an implicit
4939  * re-enable that is caused when a sprite plane is updated to no longer
4940  * completely hide the primary plane.
4941  */
4942 static void
4943 intel_post_enable_primary(struct drm_crtc *crtc)
4944 {
4945         struct drm_device *dev = crtc->dev;
4946         struct drm_i915_private *dev_priv = to_i915(dev);
4947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948         int pipe = intel_crtc->pipe;
4949 
4950         /*
4951          * FIXME IPS should be fine as long as one plane is
4952          * enabled, but in practice it seems to have problems
4953          * when going from primary only to sprite only and vice
4954          * versa.
4955          */
4956         hsw_enable_ips(intel_crtc);
4957 
4958         /*
4959          * Gen2 reports pipe underruns whenever all planes are disabled.
4960          * So don't enable underrun reporting before at least some planes
4961          * are enabled.
4962          * FIXME: Need to fix the logic to work when we turn off all planes
4963          * but leave the pipe running.
4964          */
4965         if (IS_GEN2(dev_priv))
4966                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4967 
4968         /* Underruns don't always raise interrupts, so check manually. */
4969         intel_check_cpu_fifo_underruns(dev_priv);
4970         intel_check_pch_fifo_underruns(dev_priv);
4971 }
4972 
4973 /* FIXME move all this to pre_plane_update() with proper state tracking */
4974 static void
4975 intel_pre_disable_primary(struct drm_crtc *crtc)
4976 {
4977         struct drm_device *dev = crtc->dev;
4978         struct drm_i915_private *dev_priv = to_i915(dev);
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         int pipe = intel_crtc->pipe;
4981 
4982         /*
4983          * Gen2 reports pipe underruns whenever all planes are disabled.
4984          * So diasble underrun reporting before all the planes get disabled.
4985          * FIXME: Need to fix the logic to work when we turn off all planes
4986          * but leave the pipe running.
4987          */
4988         if (IS_GEN2(dev_priv))
4989                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4990 
4991         /*
4992          * FIXME IPS should be fine as long as one plane is
4993          * enabled, but in practice it seems to have problems
4994          * when going from primary only to sprite only and vice
4995          * versa.
4996          */
4997         hsw_disable_ips(intel_crtc);
4998 }
4999 
5000 /* FIXME get rid of this and use pre_plane_update */
5001 static void
5002 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5003 {
5004         struct drm_device *dev = crtc->dev;
5005         struct drm_i915_private *dev_priv = to_i915(dev);
5006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007         int pipe = intel_crtc->pipe;
5008 
5009         intel_pre_disable_primary(crtc);
5010 
5011         /*
5012          * Vblank time updates from the shadow to live plane control register
5013          * are blocked if the memory self-refresh mode is active at that
5014          * moment. So to make sure the plane gets truly disabled, disable
5015          * first the self-refresh mode. The self-refresh enable bit in turn
5016          * will be checked/applied by the HW only at the next frame start
5017          * event which is after the vblank start event, so we need to have a
5018          * wait-for-vblank between disabling the plane and the pipe.
5019          */
5020         if (HAS_GMCH_DISPLAY(dev_priv)) {
5021                 intel_set_memory_cxsr(dev_priv, false);
5022                 dev_priv->wm.vlv.cxsr = false;
5023                 intel_wait_for_vblank(dev_priv, pipe);
5024         }
5025 }
5026 
5027 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5028 {
5029         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5030         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5031         struct intel_crtc_state *pipe_config =
5032                 to_intel_crtc_state(crtc->base.state);
5033         struct drm_plane *primary = crtc->base.primary;
5034         struct drm_plane_state *old_pri_state =
5035                 drm_atomic_get_existing_plane_state(old_state, primary);
5036 
5037         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5038 
5039         crtc->wm.cxsr_allowed = true;
5040 
5041         if (pipe_config->update_wm_post && pipe_config->base.active)
5042                 intel_update_watermarks(crtc);
5043 
5044         if (old_pri_state) {
5045                 struct intel_plane_state *primary_state =
5046                         to_intel_plane_state(primary->state);
5047                 struct intel_plane_state *old_primary_state =
5048                         to_intel_plane_state(old_pri_state);
5049 
5050                 intel_fbc_post_update(crtc);
5051 
5052                 if (primary_state->base.visible &&
5053                     (needs_modeset(&pipe_config->base) ||
5054                      !old_primary_state->base.visible))
5055                         intel_post_enable_primary(&crtc->base);
5056         }
5057 }
5058 
5059 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5060 {
5061         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5062         struct drm_device *dev = crtc->base.dev;
5063         struct drm_i915_private *dev_priv = to_i915(dev);
5064         struct intel_crtc_state *pipe_config =
5065                 to_intel_crtc_state(crtc->base.state);
5066         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5067         struct drm_plane *primary = crtc->base.primary;
5068         struct drm_plane_state *old_pri_state =
5069                 drm_atomic_get_existing_plane_state(old_state, primary);
5070         bool modeset = needs_modeset(&pipe_config->base);
5071         struct intel_atomic_state *old_intel_state =
5072                 to_intel_atomic_state(old_state);
5073 
5074         if (old_pri_state) {
5075                 struct intel_plane_state *primary_state =
5076                         to_intel_plane_state(primary->state);
5077                 struct intel_plane_state *old_primary_state =
5078                         to_intel_plane_state(old_pri_state);
5079 
5080                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5081 
5082                 if (old_primary_state->base.visible &&
5083                     (modeset || !primary_state->base.visible))
5084                         intel_pre_disable_primary(&crtc->base);
5085         }
5086 
5087         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5088                 crtc->wm.cxsr_allowed = false;
5089 
5090                 /*
5091                  * Vblank time updates from the shadow to live plane control register
5092                  * are blocked if the memory self-refresh mode is active at that
5093                  * moment. So to make sure the plane gets truly disabled, disable
5094                  * first the self-refresh mode. The self-refresh enable bit in turn
5095                  * will be checked/applied by the HW only at the next frame start
5096                  * event which is after the vblank start event, so we need to have a
5097                  * wait-for-vblank between disabling the plane and the pipe.
5098                  */
5099                 if (old_crtc_state->base.active) {
5100                         intel_set_memory_cxsr(dev_priv, false);
5101                         dev_priv->wm.vlv.cxsr = false;
5102                         intel_wait_for_vblank(dev_priv, crtc->pipe);
5103                 }
5104         }
5105 
5106         /*
5107          * IVB workaround: must disable low power watermarks for at least
5108          * one frame before enabling scaling.  LP watermarks can be re-enabled
5109          * when scaling is disabled.
5110          *
5111          * WaCxSRDisabledForSpriteScaling:ivb
5112          */
5113         if (pipe_config->disable_lp_wm) {
5114                 ilk_disable_lp_wm(dev);
5115                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5116         }
5117 
5118         /*
5119          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5120          * watermark programming here.
5121          */
5122         if (needs_modeset(&pipe_config->base))
5123                 return;
5124 
5125         /*
5126          * For platforms that support atomic watermarks, program the
5127          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5128          * will be the intermediate values that are safe for both pre- and
5129          * post- vblank; when vblank happens, the 'active' values will be set
5130          * to the final 'target' values and we'll do this again to get the
5131          * optimal watermarks.  For gen9+ platforms, the values we program here
5132          * will be the final target values which will get automatically latched
5133          * at vblank time; no further programming will be necessary.
5134          *
5135          * If a platform hasn't been transitioned to atomic watermarks yet,
5136          * we'll continue to update watermarks the old way, if flags tell
5137          * us to.
5138          */
5139         if (dev_priv->display.initial_watermarks != NULL)
5140                 dev_priv->display.initial_watermarks(old_intel_state,
5141                                                      pipe_config);
5142         else if (pipe_config->update_wm_pre)
5143                 intel_update_watermarks(crtc);
5144 }
5145 
5146 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5147 {
5148         struct drm_device *dev = crtc->dev;
5149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150         struct drm_plane *p;
5151         int pipe = intel_crtc->pipe;
5152 
5153         intel_crtc_dpms_overlay_disable(intel_crtc);
5154 
5155         drm_for_each_plane_mask(p, dev, plane_mask)
5156                 to_intel_plane(p)->disable_plane(p, crtc);
5157 
5158         /*
5159          * FIXME: Once we grow proper nuclear flip support out of this we need
5160          * to compute the mask of flip planes precisely. For the time being
5161          * consider this a flip to a NULL plane.
5162          */
5163         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5164 }
5165 
5166 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5167                                           struct intel_crtc_state *crtc_state,
5168                                           struct drm_atomic_state *old_state)
5169 {
5170         struct drm_connector_state *old_conn_state;
5171         struct drm_connector *conn;
5172         int i;
5173 
5174         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5175                 struct drm_connector_state *conn_state = conn->state;
5176                 struct intel_encoder *encoder =
5177                         to_intel_encoder(conn_state->best_encoder);
5178 
5179                 if (conn_state->crtc != crtc)
5180                         continue;
5181 
5182                 if (encoder->pre_pll_enable)
5183                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5184         }
5185 }
5186 
5187 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5188                                       struct intel_crtc_state *crtc_state,
5189                                       struct drm_atomic_state *old_state)
5190 {
5191         struct drm_connector_state *old_conn_state;
5192         struct drm_connector *conn;
5193         int i;
5194 
5195         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5196                 struct drm_connector_state *conn_state = conn->state;
5197                 struct intel_encoder *encoder =
5198                         to_intel_encoder(conn_state->best_encoder);
5199 
5200                 if (conn_state->crtc != crtc)
5201                         continue;
5202 
5203                 if (encoder->pre_enable)
5204                         encoder->pre_enable(encoder, crtc_state, conn_state);
5205         }
5206 }
5207 
5208 static void intel_encoders_enable(struct drm_crtc *crtc,
5209                                   struct intel_crtc_state *crtc_state,
5210                                   struct drm_atomic_state *old_state)
5211 {
5212         struct drm_connector_state *old_conn_state;
5213         struct drm_connector *conn;
5214         int i;
5215 
5216         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5217                 struct drm_connector_state *conn_state = conn->state;
5218                 struct intel_encoder *encoder =
5219                         to_intel_encoder(conn_state->best_encoder);
5220 
5221                 if (conn_state->crtc != crtc)
5222                         continue;
5223 
5224                 encoder->enable(encoder, crtc_state, conn_state);
5225                 intel_opregion_notify_encoder(encoder, true);
5226         }
5227 }
5228 
5229 static void intel_encoders_disable(struct drm_crtc *crtc,
5230                                    struct intel_crtc_state *old_crtc_state,
5231                                    struct drm_atomic_state *old_state)
5232 {
5233         struct drm_connector_state *old_conn_state;
5234         struct drm_connector *conn;
5235         int i;
5236 
5237         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5238                 struct intel_encoder *encoder =
5239                         to_intel_encoder(old_conn_state->best_encoder);
5240 
5241                 if (old_conn_state->crtc != crtc)
5242                         continue;
5243 
5244                 intel_opregion_notify_encoder(encoder, false);
5245                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5246         }
5247 }
5248 
5249 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5250                                         struct intel_crtc_state *old_crtc_state,
5251                                         struct drm_atomic_state *old_state)
5252 {
5253         struct drm_connector_state *old_conn_state;
5254         struct drm_connector *conn;
5255         int i;
5256 
5257         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5258                 struct intel_encoder *encoder =
5259                         to_intel_encoder(old_conn_state->best_encoder);
5260 
5261                 if (old_conn_state->crtc != crtc)
5262                         continue;
5263 
5264                 if (encoder->post_disable)
5265                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5266         }
5267 }
5268 
5269 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5270                                             struct intel_crtc_state *old_crtc_state,
5271                                             struct drm_atomic_state *old_state)
5272 {
5273         struct drm_connector_state *old_conn_state;
5274         struct drm_connector *conn;
5275         int i;
5276 
5277         for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5278                 struct intel_encoder *encoder =
5279                         to_intel_encoder(old_conn_state->best_encoder);
5280 
5281                 if (old_conn_state->crtc != crtc)
5282                         continue;
5283 
5284                 if (encoder->post_pll_disable)
5285                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5286         }
5287 }
5288 
5289 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5290                                  struct drm_atomic_state *old_state)
5291 {
5292         struct drm_crtc *crtc = pipe_config->base.crtc;
5293         struct drm_device *dev = crtc->dev;
5294         struct drm_i915_private *dev_priv = to_i915(dev);
5295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5296         int pipe = intel_crtc->pipe;
5297         struct intel_atomic_state *old_intel_state =
5298                 to_intel_atomic_state(old_state);
5299 
5300         if (WARN_ON(intel_crtc->active))
5301                 return;
5302 
5303         /*
5304          * Sometimes spurious CPU pipe underruns happen during FDI
5305          * training, at least with VGA+HDMI cloning. Suppress them.
5306          *
5307          * On ILK we get an occasional spurious CPU pipe underruns
5308          * between eDP port A enable and vdd enable. Also PCH port
5309          * enable seems to result in the occasional CPU pipe underrun.
5310          *
5311          * Spurious PCH underruns also occur during PCH enabling.
5312          */
5313         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5314                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5315         if (intel_crtc->config->has_pch_encoder)
5316                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5317 
5318         if (intel_crtc->config->has_pch_encoder)
5319                 intel_prepare_shared_dpll(intel_crtc);
5320 
5321         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5322                 intel_dp_set_m_n(intel_crtc, M1_N1);
5323 
5324         intel_set_pipe_timings(intel_crtc);
5325         intel_set_pipe_src_size(intel_crtc);
5326 
5327         if (intel_crtc->config->has_pch_encoder) {
5328                 intel_cpu_transcoder_set_m_n(intel_crtc,
5329                                      &intel_crtc->config->fdi_m_n, NULL);
5330         }
5331 
5332         ironlake_set_pipeconf(crtc);
5333 
5334         intel_crtc->active = true;
5335 
5336         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5337 
5338         if (intel_crtc->config->has_pch_encoder) {
5339                 /* Note: FDI PLL enabling _must_ be done before we enable the
5340                  * cpu pipes, hence this is separate from all the other fdi/pch
5341                  * enabling. */
5342                 ironlake_fdi_pll_enable(intel_crtc);
5343         } else {
5344                 assert_fdi_tx_disabled(dev_priv, pipe);
5345                 assert_fdi_rx_disabled(dev_priv, pipe);
5346         }
5347 
5348         ironlake_pfit_enable(intel_crtc);
5349 
5350         /*
5351          * On ILK+ LUT must be loaded before the pipe is running but with
5352          * clocks enabled
5353          */
5354         intel_color_load_luts(&pipe_config->base);
5355 
5356         if (dev_priv->display.initial_watermarks != NULL)
5357                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5358         intel_enable_pipe(intel_crtc);
5359 
5360         if (intel_crtc->config->has_pch_encoder)
5361                 ironlake_pch_enable(crtc);
5362 
5363         assert_vblank_disabled(crtc);
5364         drm_crtc_vblank_on(crtc);
5365 
5366         intel_encoders_enable(crtc, pipe_config, old_state);
5367 
5368         if (HAS_PCH_CPT(dev_priv))
5369                 cpt_verify_modeset(dev, intel_crtc->pipe);
5370 
5371         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5372         if (intel_crtc->config->has_pch_encoder)
5373                 intel_wait_for_vblank(dev_priv, pipe);
5374         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5375         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5376 }
5377 
5378 /* IPS only exists on ULT machines and is tied to pipe A. */
5379 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5380 {
5381         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5382 }
5383 
5384 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5385                                 struct drm_atomic_state *old_state)
5386 {
5387         struct drm_crtc *crtc = pipe_config->base.crtc;
5388         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5390         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5391         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5392         struct intel_atomic_state *old_intel_state =
5393                 to_intel_atomic_state(old_state);
5394 
5395         if (WARN_ON(intel_crtc->active))
5396                 return;
5397 
5398         if (intel_crtc->config->has_pch_encoder)
5399                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5400                                                       false);
5401 
5402         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5403 
5404         if (intel_crtc->config->shared_dpll)
5405                 intel_enable_shared_dpll(intel_crtc);
5406 
5407         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5408                 intel_dp_set_m_n(intel_crtc, M1_N1);
5409 
5410         if (!transcoder_is_dsi(cpu_transcoder))
5411                 intel_set_pipe_timings(intel_crtc);
5412 
5413         intel_set_pipe_src_size(intel_crtc);
5414 
5415         if (cpu_transcoder != TRANSCODER_EDP &&
5416             !transcoder_is_dsi(cpu_transcoder)) {
5417                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5418                            intel_crtc->config->pixel_multiplier - 1);
5419         }
5420 
5421         if (intel_crtc->config->has_pch_encoder) {
5422                 intel_cpu_transcoder_set_m_n(intel_crtc,
5423                                      &intel_crtc->config->fdi_m_n, NULL);
5424         }
5425 
5426         if (!transcoder_is_dsi(cpu_transcoder))
5427                 haswell_set_pipeconf(crtc);
5428 
5429         haswell_set_pipemisc(crtc);
5430 
5431         intel_color_set_csc(&pipe_config->base);
5432 
5433         intel_crtc->active = true;
5434 
5435         if (intel_crtc->config->has_pch_encoder)
5436                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5437         else
5438                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5439 
5440         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5441 
5442         if (intel_crtc->config->has_pch_encoder)
5443                 dev_priv->display.fdi_link_train(crtc);
5444 
5445         if (!transcoder_is_dsi(cpu_transcoder))
5446                 intel_ddi_enable_pipe_clock(intel_crtc);
5447 
5448         if (INTEL_GEN(dev_priv) >= 9)
5449                 skylake_pfit_enable(intel_crtc);
5450         else
5451                 ironlake_pfit_enable(intel_crtc);
5452 
5453         /*
5454          * On ILK+ LUT must be loaded before the pipe is running but with
5455          * clocks enabled
5456          */
5457         intel_color_load_luts(&pipe_config->base);
5458 
5459         intel_ddi_set_pipe_settings(crtc);
5460         if (!transcoder_is_dsi(cpu_transcoder))
5461                 intel_ddi_enable_transcoder_func(crtc);
5462 
5463         if (dev_priv->display.initial_watermarks != NULL)
5464                 dev_priv->display.initial_watermarks(old_intel_state,
5465                                                      pipe_config);
5466         else
5467                 intel_update_watermarks(intel_crtc);
5468 
5469         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5470         if (!transcoder_is_dsi(cpu_transcoder))
5471                 intel_enable_pipe(intel_crtc);
5472 
5473         if (intel_crtc->config->has_pch_encoder)
5474                 lpt_pch_enable(crtc);
5475 
5476         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5477                 intel_ddi_set_vc_payload_alloc(crtc, true);
5478 
5479         assert_vblank_disabled(crtc);
5480         drm_crtc_vblank_on(crtc);
5481 
5482         intel_encoders_enable(crtc, pipe_config, old_state);
5483 
5484         if (intel_crtc->config->has_pch_encoder) {
5485                 intel_wait_for_vblank(dev_priv, pipe);
5486                 intel_wait_for_vblank(dev_priv, pipe);
5487                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5488                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5489                                                       true);
5490         }
5491 
5492         /* If we change the relative order between pipe/planes enabling, we need
5493          * to change the workaround. */
5494         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5495         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5496                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5497                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5498         }
5499 }
5500 
5501 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5502 {
5503         struct drm_device *dev = crtc->base.dev;
5504         struct drm_i915_private *dev_priv = to_i915(dev);
5505         int pipe = crtc->pipe;
5506 
5507         /* To avoid upsetting the power well on haswell only disable the pfit if
5508          * it's in use. The hw state code will make sure we get this right. */
5509         if (force || crtc->config->pch_pfit.enabled) {
5510                 I915_WRITE(PF_CTL(pipe), 0);
5511                 I915_WRITE(PF_WIN_POS(pipe), 0);
5512                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5513         }
5514 }
5515 
5516 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5517                                   struct drm_atomic_state *old_state)
5518 {
5519         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5520         struct drm_device *dev = crtc->dev;
5521         struct drm_i915_private *dev_priv = to_i915(dev);
5522         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5523         int pipe = intel_crtc->pipe;
5524 
5525         /*
5526          * Sometimes spurious CPU pipe underruns happen when the
5527          * pipe is already disabled, but FDI RX/TX is still enabled.
5528          * Happens at least with VGA+HDMI cloning. Suppress them.
5529          */
5530         if (intel_crtc->config->has_pch_encoder) {
5531                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5532                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5533         }
5534 
5535         intel_encoders_disable(crtc, old_crtc_state, old_state);
5536 
5537         drm_crtc_vblank_off(crtc);
5538         assert_vblank_disabled(crtc);
5539 
5540         intel_disable_pipe(intel_crtc);
5541 
5542         ironlake_pfit_disable(intel_crtc, false);
5543 
5544         if (intel_crtc->config->has_pch_encoder)
5545                 ironlake_fdi_disable(crtc);
5546 
5547         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5548 
5549         if (intel_crtc->config->has_pch_encoder) {
5550                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5551 
5552                 if (HAS_PCH_CPT(dev_priv)) {
5553                         i915_reg_t reg;
5554                         u32 temp;
5555 
5556                         /* disable TRANS_DP_CTL */
5557                         reg = TRANS_DP_CTL(pipe);
5558                         temp = I915_READ(reg);
5559                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5560                                   TRANS_DP_PORT_SEL_MASK);
5561                         temp |= TRANS_DP_PORT_SEL_NONE;
5562                         I915_WRITE(reg, temp);
5563 
5564                         /* disable DPLL_SEL */
5565                         temp = I915_READ(PCH_DPLL_SEL);
5566                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5567                         I915_WRITE(PCH_DPLL_SEL, temp);
5568                 }
5569 
5570                 ironlake_fdi_pll_disable(intel_crtc);
5571         }
5572 
5573         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5574         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5575 }
5576 
5577 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5578                                  struct drm_atomic_state *old_state)
5579 {
5580         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5581         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5583         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5584 
5585         if (intel_crtc->config->has_pch_encoder)
5586                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5587                                                       false);
5588 
5589         intel_encoders_disable(crtc, old_crtc_state, old_state);
5590 
5591         drm_crtc_vblank_off(crtc);
5592         assert_vblank_disabled(crtc);
5593 
5594         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5595         if (!transcoder_is_dsi(cpu_transcoder))
5596                 intel_disable_pipe(intel_crtc);
5597 
5598         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5599                 intel_ddi_set_vc_payload_alloc(crtc, false);
5600 
5601         if (!transcoder_is_dsi(cpu_transcoder))
5602                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5603 
5604         if (INTEL_GEN(dev_priv) >= 9)
5605                 skylake_scaler_disable(intel_crtc);
5606         else
5607                 ironlake_pfit_disable(intel_crtc, false);
5608 
5609         if (!transcoder_is_dsi(cpu_transcoder))
5610                 intel_ddi_disable_pipe_clock(intel_crtc);
5611 
5612         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5613 
5614         if (old_crtc_state->has_pch_encoder)
5615                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5616                                                       true);
5617 }
5618 
5619 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5620 {
5621         struct drm_device *dev = crtc->base.dev;
5622         struct drm_i915_private *dev_priv = to_i915(dev);
5623         struct intel_crtc_state *pipe_config = crtc->config;
5624 
5625         if (!pipe_config->gmch_pfit.control)
5626                 return;
5627 
5628         /*
5629          * The panel fitter should only be adjusted whilst the pipe is disabled,
5630          * according to register description and PRM.
5631          */
5632         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5633         assert_pipe_disabled(dev_priv, crtc->pipe);
5634 
5635         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5636         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5637 
5638         /* Border color in case we don't scale up to the full screen. Black by
5639          * default, change to something else for debugging. */
5640         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5641 }
5642 
5643 static enum intel_display_power_domain port_to_power_domain(enum port port)
5644 {
5645         switch (port) {
5646         case PORT_A:
5647                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5648         case PORT_B:
5649                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5650         case PORT_C:
5651                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5652         case PORT_D:
5653                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5654         case PORT_E:
5655                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5656         default:
5657                 MISSING_CASE(port);
5658                 return POWER_DOMAIN_PORT_OTHER;
5659         }
5660 }
5661 
5662 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5663 {
5664         switch (port) {
5665         case PORT_A:
5666                 return POWER_DOMAIN_AUX_A;
5667         case PORT_B:
5668                 return POWER_DOMAIN_AUX_B;
5669         case PORT_C:
5670                 return POWER_DOMAIN_AUX_C;
5671         case PORT_D:
5672                 return POWER_DOMAIN_AUX_D;
5673         case PORT_E:
5674                 /* FIXME: Check VBT for actual wiring of PORT E */
5675                 return POWER_DOMAIN_AUX_D;
5676         default:
5677                 MISSING_CASE(port);
5678                 return POWER_DOMAIN_AUX_A;
5679         }
5680 }
5681 
5682 enum intel_display_power_domain
5683 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5684 {
5685         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5686         struct intel_digital_port *intel_dig_port;
5687 
5688         switch (intel_encoder->type) {
5689         case INTEL_OUTPUT_UNKNOWN:
5690                 /* Only DDI platforms should ever use this output type */
5691                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5692         case INTEL_OUTPUT_DP:
5693         case INTEL_OUTPUT_HDMI:
5694         case INTEL_OUTPUT_EDP:
5695                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5696                 return port_to_power_domain(intel_dig_port->port);
5697         case INTEL_OUTPUT_DP_MST:
5698                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5699                 return port_to_power_domain(intel_dig_port->port);
5700         case INTEL_OUTPUT_ANALOG:
5701                 return POWER_DOMAIN_PORT_CRT;
5702         case INTEL_OUTPUT_DSI:
5703                 return POWER_DOMAIN_PORT_DSI;
5704         default:
5705                 return POWER_DOMAIN_PORT_OTHER;
5706         }
5707 }
5708 
5709 enum intel_display_power_domain
5710 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5711 {
5712         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5713         struct intel_digital_port *intel_dig_port;
5714 
5715         switch (intel_encoder->type) {
5716         case INTEL_OUTPUT_UNKNOWN:
5717         case INTEL_OUTPUT_HDMI:
5718                 /*
5719                  * Only DDI platforms should ever use these output types.
5720                  * We can get here after the HDMI detect code has already set
5721                  * the type of the shared encoder. Since we can't be sure
5722                  * what's the status of the given connectors, play safe and
5723                  * run the DP detection too.
5724                  */
5725                 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5726         case INTEL_OUTPUT_DP:
5727         case INTEL_OUTPUT_EDP:
5728                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5729                 return port_to_aux_power_domain(intel_dig_port->port);
5730         case INTEL_OUTPUT_DP_MST:
5731                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5732                 return port_to_aux_power_domain(intel_dig_port->port);
5733         default:
5734                 MISSING_CASE(intel_encoder->type);
5735                 return POWER_DOMAIN_AUX_A;
5736         }
5737 }
5738 
5739 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5740                                             struct intel_crtc_state *crtc_state)
5741 {
5742         struct drm_device *dev = crtc->dev;
5743         struct drm_encoder *encoder;
5744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5745         enum pipe pipe = intel_crtc->pipe;
5746         unsigned long mask;
5747         enum transcoder transcoder = crtc_state->cpu_transcoder;
5748 
5749         if (!crtc_state->base.active)
5750                 return 0;
5751 
5752         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5753         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5754         if (crtc_state->pch_pfit.enabled ||
5755             crtc_state->pch_pfit.force_thru)
5756                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5757 
5758         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5759                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5760 
5761                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5762         }
5763 
5764         if (crtc_state->shared_dpll)
5765                 mask |= BIT(POWER_DOMAIN_PLLS);
5766 
5767         return mask;
5768 }
5769 
5770 static unsigned long
5771 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5772                                struct intel_crtc_state *crtc_state)
5773 {
5774         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5776         enum intel_display_power_domain domain;
5777         unsigned long domains, new_domains, old_domains;
5778 
5779         old_domains = intel_crtc->enabled_power_domains;
5780         intel_crtc->enabled_power_domains = new_domains =
5781                 get_crtc_power_domains(crtc, crtc_state);
5782 
5783         domains = new_domains & ~old_domains;
5784 
5785         for_each_power_domain(domain, domains)
5786                 intel_display_power_get(dev_priv, domain);
5787 
5788         return old_domains & ~new_domains;
5789 }
5790 
5791 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5792                                       unsigned long domains)
5793 {
5794         enum intel_display_power_domain domain;
5795 
5796         for_each_power_domain(domain, domains)
5797                 intel_display_power_put(dev_priv, domain);
5798 }
5799 
5800 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5801 {
5802         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5803 
5804         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5805             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5806                 return max_cdclk_freq;
5807         else if (IS_CHERRYVIEW(dev_priv))
5808                 return max_cdclk_freq*95/100;
5809         else if (INTEL_INFO(dev_priv)->gen < 4)
5810                 return 2*max_cdclk_freq*90/100;
5811         else
5812                 return max_cdclk_freq*90/100;
5813 }
5814 
5815 static int skl_calc_cdclk(int max_pixclk, int vco);
5816 
5817 static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
5818 {
5819         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5820                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5821                 int max_cdclk, vco;
5822 
5823                 vco = dev_priv->skl_preferred_vco_freq;
5824                 WARN_ON(vco != 8100000 && vco != 8640000);
5825 
5826                 /*
5827                  * Use the lower (vco 8640) cdclk values as a
5828                  * first guess. skl_calc_cdclk() will correct it
5829                  * if the preferred vco is 8100 instead.
5830                  */
5831                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5832                         max_cdclk = 617143;
5833                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5834                         max_cdclk = 540000;
5835                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5836                         max_cdclk = 432000;
5837                 else
5838                         max_cdclk = 308571;
5839 
5840                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5841         } else if (IS_BROXTON(dev_priv)) {
5842                 dev_priv->max_cdclk_freq = 624000;
5843         } else if (IS_BROADWELL(dev_priv))  {
5844                 /*
5845                  * FIXME with extra cooling we can allow
5846                  * 540 MHz for ULX and 675 Mhz for ULT.
5847                  * How can we know if extra cooling is
5848                  * available? PCI ID, VTB, something else?
5849                  */
5850                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5851                         dev_priv->max_cdclk_freq = 450000;
5852                 else if (IS_BDW_ULX(dev_priv))
5853                         dev_priv->max_cdclk_freq = 450000;
5854                 else if (IS_BDW_ULT(dev_priv))
5855                         dev_priv->max_cdclk_freq = 540000;
5856                 else
5857                         dev_priv->max_cdclk_freq = 675000;
5858         } else if (IS_CHERRYVIEW(dev_priv)) {
5859                 dev_priv->max_cdclk_freq = 320000;
5860         } else if (IS_VALLEYVIEW(dev_priv)) {
5861                 dev_priv->max_cdclk_freq = 400000;
5862         } else {
5863                 /* otherwise assume cdclk is fixed */
5864                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5865         }
5866 
5867         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5868 
5869         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5870                          dev_priv->max_cdclk_freq);
5871 
5872         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5873                          dev_priv->max_dotclk_freq);
5874 }
5875 
5876 static void intel_update_cdclk(struct drm_i915_private *dev_priv)
5877 {
5878         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5879 
5880         if (INTEL_GEN(dev_priv) >= 9)
5881                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5882                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5883                                  dev_priv->cdclk_pll.ref);
5884         else
5885                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5886                                  dev_priv->cdclk_freq);
5887 
5888         /*
5889          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5890          * Programmng [sic] note: bit[9:2] should be programmed to the number
5891          * of cdclk that generates 4MHz reference clock freq which is used to
5892          * generate GMBus clock. This will vary with the cdclk freq.
5893          */
5894         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5895                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5896 }
5897 
5898 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5899 static int skl_cdclk_decimal(int cdclk)
5900 {
5901         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5902 }
5903 
5904 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5905 {
5906         int ratio;
5907 
5908         if (cdclk == dev_priv->cdclk_pll.ref)
5909                 return 0;
5910 
5911         switch (cdclk) {
5912         default:
5913                 MISSING_CASE(cdclk);
5914         case 144000:
5915         case 288000:
5916         case 384000:
5917         case 576000:
5918                 ratio = 60;
5919                 break;
5920         case 624000:
5921                 ratio = 65;
5922                 break;
5923         }
5924 
5925         return dev_priv->cdclk_pll.ref * ratio;
5926 }
5927 
5928 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5929 {
5930         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5931 
5932         /* Timeout 200us */
5933         if (intel_wait_for_register(dev_priv,
5934                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5935                                     1))
5936                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5937 
5938         dev_priv->cdclk_pll.vco = 0;
5939 }
5940 
5941 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5942 {
5943         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5944         u32 val;
5945 
5946         val = I915_READ(BXT_DE_PLL_CTL);
5947         val &= ~BXT_DE_PLL_RATIO_MASK;
5948         val |= BXT_DE_PLL_RATIO(ratio);
5949         I915_WRITE(BXT_DE_PLL_CTL, val);
5950 
5951         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5952 
5953         /* Timeout 200us */
5954         if (intel_wait_for_register(dev_priv,
5955                                     BXT_DE_PLL_ENABLE,
5956                                     BXT_DE_PLL_LOCK,
5957                                     BXT_DE_PLL_LOCK,
5958                                     1))
5959                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5960 
5961         dev_priv->cdclk_pll.vco = vco;
5962 }
5963 
5964 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5965 {
5966         u32 val, divider;
5967         int vco, ret;
5968 
5969         vco = bxt_de_pll_vco(dev_priv, cdclk);
5970 
5971         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5972 
5973         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5974         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5975         case 8:
5976                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5977                 break;
5978         case 4:
5979                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5980                 break;
5981         case 3:
5982                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5983                 break;
5984         case 2:
5985                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5986                 break;
5987         default:
5988                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5989                 WARN_ON(vco != 0);
5990 
5991                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5992                 break;
5993         }
5994 
5995         /* Inform power controller of upcoming frequency change */
5996         mutex_lock(&dev_priv->rps.hw_lock);
5997         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5998                                       0x80000000);
5999         mutex_unlock(&dev_priv->rps.hw_lock);
6000 
6001         if (ret) {
6002                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6003                           ret, cdclk);
6004                 return;
6005         }
6006 
6007         if (dev_priv->cdclk_pll.vco != 0 &&
6008             dev_priv->cdclk_pll.vco != vco)
6009                 bxt_de_pll_disable(dev_priv);
6010 
6011         if (dev_priv->cdclk_pll.vco != vco)
6012                 bxt_de_pll_enable(dev_priv, vco);
6013 
6014         val = divider | skl_cdclk_decimal(cdclk);
6015         /*
6016          * FIXME if only the cd2x divider needs changing, it could be done
6017          * without shutting off the pipe (if only one pipe is active).
6018          */
6019         val |= BXT_CDCLK_CD2X_PIPE_NONE;
6020         /*
6021          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6022          * enable otherwise.
6023          */
6024         if (cdclk >= 500000)
6025                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6026         I915_WRITE(CDCLK_CTL, val);
6027 
6028         mutex_lock(&dev_priv->rps.hw_lock);
6029         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6030                                       DIV_ROUND_UP(cdclk, 25000));
6031         mutex_unlock(&dev_priv->rps.hw_lock);
6032 
6033         if (ret) {
6034                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6035                           ret, cdclk);
6036                 return;
6037         }
6038 
6039         intel_update_cdclk(dev_priv);
6040 }
6041 
6042 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6043 {
6044         u32 cdctl, expected;
6045 
6046         intel_update_cdclk(dev_priv);
6047 
6048         if (dev_priv->cdclk_pll.vco == 0 ||
6049             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6050                 goto sanitize;
6051 
6052         /* DPLL okay; verify the cdclock
6053          *
6054          * Some BIOS versions leave an incorrect decimal frequency value and
6055          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6056          * so sanitize this register.
6057          */
6058         cdctl = I915_READ(CDCLK_CTL);
6059         /*
6060          * Let's ignore the pipe field, since BIOS could have configured the
6061          * dividers both synching to an active pipe, or asynchronously
6062          * (PIPE_NONE).
6063          */
6064         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6065 
6066         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6067                    skl_cdclk_decimal(dev_priv->cdclk_freq);
6068         /*
6069          * Disable SSA Precharge when CD clock frequency < 500 MHz,
6070          * enable otherwise.
6071          */
6072         if (dev_priv->cdclk_freq >= 500000)
6073                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6074 
6075         if (cdctl == expected)
6076                 /* All well; nothing to sanitize */
6077                 return;
6078 
6079 sanitize:
6080         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6081 
6082         /* force cdclk programming */
6083         dev_priv->cdclk_freq = 0;
6084 
6085         /* force full PLL disable + enable */
6086         dev_priv->cdclk_pll.vco = -1;
6087 }
6088 
6089 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6090 {
6091         bxt_sanitize_cdclk(dev_priv);
6092 
6093         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6094                 return;
6095 
6096         /*
6097          * FIXME:
6098          * - The initial CDCLK needs to be read from VBT.
6099          *   Need to make this change after VBT has changes for BXT.
6100          */
6101         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6102 }
6103 
6104 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6105 {
6106         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6107 }
6108 
6109 static int skl_calc_cdclk(int max_pixclk, int vco)
6110 {
6111         if (vco == 8640000) {
6112                 if (max_pixclk > 540000)
6113                         return 617143;
6114                 else if (max_pixclk > 432000)
6115                         return 540000;
6116                 else if (max_pixclk > 308571)
6117                         return 432000;
6118                 else
6119                         return 308571;
6120         } else {
6121                 if (max_pixclk > 540000)
6122                         return 675000;
6123                 else if (max_pixclk > 450000)
6124                         return 540000;
6125                 else if (max_pixclk > 337500)
6126                         return 450000;
6127                 else
6128                         return 337500;
6129         }
6130 }
6131 
6132 static void
6133 skl_dpll0_update(struct drm_i915_private *dev_priv)
6134 {
6135         u32 val;
6136 
6137         dev_priv->cdclk_pll.ref = 24000;
6138         dev_priv->cdclk_pll.vco = 0;
6139 
6140         val = I915_READ(LCPLL1_CTL);
6141         if ((val & LCPLL_PLL_ENABLE) == 0)
6142                 return;
6143 
6144         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6145                 return;
6146 
6147         val = I915_READ(DPLL_CTRL1);
6148 
6149         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6150                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6151                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6152                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6153                 return;
6154 
6155         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6156         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6157         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6158         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6159         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6160                 dev_priv->cdclk_pll.vco = 8100000;
6161                 break;
6162         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6163         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6164                 dev_priv->cdclk_pll.vco = 8640000;
6165                 break;
6166         default:
6167                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6168                 break;
6169         }
6170 }
6171 
6172 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6173 {
6174         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6175 
6176         dev_priv->skl_preferred_vco_freq = vco;
6177 
6178         if (changed)
6179                 intel_update_max_cdclk(dev_priv);
6180 }
6181 
6182 static void
6183 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6184 {
6185         int min_cdclk = skl_calc_cdclk(0, vco);
6186         u32 val;
6187 
6188         WARN_ON(vco != 8100000 && vco != 8640000);
6189 
6190         /* select the minimum CDCLK before enabling DPLL 0 */
6191         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6192         I915_WRITE(CDCLK_CTL, val);
6193         POSTING_READ(CDCLK_CTL);
6194 
6195         /*
6196          * We always enable DPLL0 with the lowest link rate possible, but still
6197          * taking into account the VCO required to operate the eDP panel at the
6198          * desired frequency. The usual DP link rates operate with a VCO of
6199          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6200          * The modeset code is responsible for the selection of the exact link
6201          * rate later on, with the constraint of choosing a frequency that
6202          * works with vco.
6203          */
6204         val = I915_READ(DPLL_CTRL1);
6205 
6206         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6207                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6208         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6209         if (vco == 8640000)
6210                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6211                                             SKL_DPLL0);
6212         else
6213                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6214                                             SKL_DPLL0);
6215 
6216         I915_WRITE(DPLL_CTRL1, val);
6217         POSTING_READ(DPLL_CTRL1);
6218 
6219         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6220 
6221         if (intel_wait_for_register(dev_priv,
6222                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6223                                     5))
6224                 DRM_ERROR("DPLL0 not locked\n");
6225 
6226         dev_priv->cdclk_pll.vco = vco;
6227 
6228         /* We'll want to keep using the current vco from now on. */
6229         skl_set_preferred_cdclk_vco(dev_priv, vco);
6230 }
6231 
6232 static void
6233 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6234 {
6235         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6236         if (intel_wait_for_register(dev_priv,
6237                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6238                                    1))
6239                 DRM_ERROR("Couldn't disable DPLL0\n");
6240 
6241         dev_priv->cdclk_pll.vco = 0;
6242 }
6243 
6244 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6245 {
6246         u32 freq_select, pcu_ack;
6247         int ret;
6248 
6249         WARN_ON((cdclk == 24000) != (vco == 0));
6250 
6251         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6252 
6253         mutex_lock(&dev_priv->rps.hw_lock);
6254         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6255                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
6256                                 SKL_CDCLK_READY_FOR_CHANGE,
6257                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
6258         mutex_unlock(&dev_priv->rps.hw_lock);
6259         if (ret) {
6260                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6261                           ret);
6262                 return;
6263         }
6264 
6265         /* set CDCLK_CTL */
6266         switch (cdclk) {
6267         case 450000:
6268         case 432000:
6269                 freq_select = CDCLK_FREQ_450_432;
6270                 pcu_ack = 1;
6271                 break;
6272         case 540000:
6273                 freq_select = CDCLK_FREQ_540;
6274                 pcu_ack = 2;
6275                 break;
6276         case 308571:
6277         case 337500:
6278         default:
6279                 freq_select = CDCLK_FREQ_337_308;
6280                 pcu_ack = 0;
6281                 break;
6282         case 617143:
6283         case 675000:
6284                 freq_select = CDCLK_FREQ_675_617;
6285                 pcu_ack = 3;
6286                 break;
6287         }
6288 
6289         if (dev_priv->cdclk_pll.vco != 0 &&
6290             dev_priv->cdclk_pll.vco != vco)
6291                 skl_dpll0_disable(dev_priv);
6292 
6293         if (dev_priv->cdclk_pll.vco != vco)
6294                 skl_dpll0_enable(dev_priv, vco);
6295 
6296         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6297         POSTING_READ(CDCLK_CTL);
6298 
6299         /* inform PCU of the change */
6300         mutex_lock(&dev_priv->rps.hw_lock);
6301         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6302         mutex_unlock(&dev_priv->rps.hw_lock);
6303 
6304         intel_update_cdclk(dev_priv);
6305 }
6306 
6307 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6308 
6309 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6310 {
6311         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6312 }
6313 
6314 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6315 {
6316         int cdclk, vco;
6317 
6318         skl_sanitize_cdclk(dev_priv);
6319 
6320         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6321                 /*
6322                  * Use the current vco as our initial
6323                  * guess as to what the preferred vco is.
6324                  */
6325                 if (dev_priv->skl_preferred_vco_freq == 0)
6326                         skl_set_preferred_cdclk_vco(dev_priv,
6327                                                     dev_priv->cdclk_pll.vco);
6328                 return;
6329         }
6330 
6331         vco = dev_priv->skl_preferred_vco_freq;
6332         if (vco == 0)
6333                 vco = 8100000;
6334         cdclk = skl_calc_cdclk(0, vco);
6335 
6336         skl_set_cdclk(dev_priv, cdclk, vco);
6337 }
6338 
6339 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6340 {
6341         uint32_t cdctl, expected;
6342 
6343         /*
6344          * check if the pre-os intialized the display
6345          * There is SWF18 scratchpad register defined which is set by the
6346          * pre-os which can be used by the OS drivers to check the status
6347          */
6348         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6349                 goto sanitize;
6350 
6351         intel_update_cdclk(dev_priv);
6352         /* Is PLL enabled and locked ? */
6353         if (dev_priv->cdclk_pll.vco == 0 ||
6354             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6355                 goto sanitize;
6356 
6357         /* DPLL okay; verify the cdclock
6358          *
6359          * Noticed in some instances that the freq selection is correct but
6360          * decimal part is programmed wrong from BIOS where pre-os does not
6361          * enable display. Verify the same as well.
6362          */
6363         cdctl = I915_READ(CDCLK_CTL);
6364         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6365                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6366         if (cdctl == expected)
6367                 /* All well; nothing to sanitize */
6368                 return;
6369 
6370 sanitize:
6371         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6372 
6373         /* force cdclk programming */
6374         dev_priv->cdclk_freq = 0;
6375         /* force full PLL disable + enable */
6376         dev_priv->cdclk_pll.vco = -1;
6377 }
6378 
6379 /* Adjust CDclk dividers to allow high res or save power if possible */
6380 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6381 {
6382         struct drm_i915_private *dev_priv = to_i915(dev);
6383         u32 val, cmd;
6384 
6385         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6386                                         != dev_priv->cdclk_freq);
6387 
6388         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6389                 cmd = 2;
6390         else if (cdclk == 266667)
6391                 cmd = 1;
6392         else
6393                 cmd = 0;
6394 
6395         mutex_lock(&dev_priv->rps.hw_lock);
6396         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6397         val &= ~DSPFREQGUAR_MASK;
6398         val |= (cmd << DSPFREQGUAR_SHIFT);
6399         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6400         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6401                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6402                      50)) {
6403                 DRM_ERROR("timed out waiting for CDclk change\n");
6404         }
6405         mutex_unlock(&dev_priv->rps.hw_lock);
6406 
6407         mutex_lock(&dev_priv->sb_lock);
6408 
6409         if (cdclk == 400000) {
6410                 u32 divider;
6411 
6412                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6413 
6414                 /* adjust cdclk divider */
6415                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6416                 val &= ~CCK_FREQUENCY_VALUES;
6417                 val |= divider;
6418                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6419 
6420                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6421                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6422                              50))
6423                         DRM_ERROR("timed out waiting for CDclk change\n");
6424         }
6425 
6426         /* adjust self-refresh exit latency value */
6427         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6428         val &= ~0x7f;
6429 
6430         /*
6431          * For high bandwidth configs, we set a higher latency in the bunit
6432          * so that the core display fetch happens in time to avoid underruns.
6433          */
6434         if (cdclk == 400000)
6435                 val |= 4500 / 250; /* 4.5 usec */
6436         else
6437                 val |= 3000 / 250; /* 3.0 usec */
6438         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6439 
6440         mutex_unlock(&dev_priv->sb_lock);
6441 
6442         intel_update_cdclk(dev_priv);
6443 }
6444 
6445 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6446 {
6447         struct drm_i915_private *dev_priv = to_i915(dev);
6448         u32 val, cmd;
6449 
6450         WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6451                                                 != dev_priv->cdclk_freq);
6452 
6453         switch (cdclk) {
6454         case 333333:
6455         case 320000:
6456         case 266667:
6457         case 200000:
6458                 break;
6459         default:
6460                 MISSING_CASE(cdclk);
6461                 return;
6462         }
6463 
6464         /*
6465          * Specs are full of misinformation, but testing on actual
6466          * hardware has shown that we just need to write the desired
6467          * CCK divider into the Punit register.
6468          */
6469         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6470 
6471         mutex_lock(&dev_priv->rps.hw_lock);
6472         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6473         val &= ~DSPFREQGUAR_MASK_CHV;
6474         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6475         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6476         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6477                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6478                      50)) {
6479                 DRM_ERROR("timed out waiting for CDclk change\n");
6480         }
6481         mutex_unlock(&dev_priv->rps.hw_lock);