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Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_atomic.h>
 41 #include <drm/drm_atomic_helper.h>
 42 #include <drm/drm_dp_helper.h>
 43 #include <drm/drm_crtc_helper.h>
 44 #include <drm/drm_plane_helper.h>
 45 #include <drm/drm_rect.h>
 46 #include <linux/dma_remapping.h>
 47 #include <linux/reservation.h>
 48 #include <linux/dma-buf.h>
 49 
 50 /* Primary plane formats for gen <= 3 */
 51 static const uint32_t i8xx_primary_formats[] = {
 52         DRM_FORMAT_C8,
 53         DRM_FORMAT_RGB565,
 54         DRM_FORMAT_XRGB1555,
 55         DRM_FORMAT_XRGB8888,
 56 };
 57 
 58 /* Primary plane formats for gen >= 4 */
 59 static const uint32_t i965_primary_formats[] = {
 60         DRM_FORMAT_C8,
 61         DRM_FORMAT_RGB565,
 62         DRM_FORMAT_XRGB8888,
 63         DRM_FORMAT_XBGR8888,
 64         DRM_FORMAT_XRGB2101010,
 65         DRM_FORMAT_XBGR2101010,
 66 };
 67 
 68 static const uint32_t skl_primary_formats[] = {
 69         DRM_FORMAT_C8,
 70         DRM_FORMAT_RGB565,
 71         DRM_FORMAT_XRGB8888,
 72         DRM_FORMAT_XBGR8888,
 73         DRM_FORMAT_ARGB8888,
 74         DRM_FORMAT_ABGR8888,
 75         DRM_FORMAT_XRGB2101010,
 76         DRM_FORMAT_XBGR2101010,
 77         DRM_FORMAT_YUYV,
 78         DRM_FORMAT_YVYU,
 79         DRM_FORMAT_UYVY,
 80         DRM_FORMAT_VYUY,
 81 };
 82 
 83 /* Cursor formats */
 84 static const uint32_t intel_cursor_formats[] = {
 85         DRM_FORMAT_ARGB8888,
 86 };
 87 
 88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 89 
 90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 91                                 struct intel_crtc_state *pipe_config);
 92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 93                                    struct intel_crtc_state *pipe_config);
 94 
 95 static int intel_framebuffer_init(struct drm_device *dev,
 96                                   struct intel_framebuffer *ifb,
 97                                   struct drm_mode_fb_cmd2 *mode_cmd,
 98                                   struct drm_i915_gem_object *obj);
 99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102                                          struct intel_link_m_n *m_n,
103                                          struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108                             const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110                             const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114         struct intel_crtc_state *crtc_state);
115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
116                            int num_connectors);
117 static void skylake_pfit_enable(struct intel_crtc *crtc);
118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
121 static void intel_pre_disable_primary(struct drm_crtc *crtc);
122 
123 typedef struct {
124         int     min, max;
125 } intel_range_t;
126 
127 typedef struct {
128         int     dot_limit;
129         int     p2_slow, p2_fast;
130 } intel_p2_t;
131 
132 typedef struct intel_limit intel_limit_t;
133 struct intel_limit {
134         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
135         intel_p2_t          p2;
136 };
137 
138 /* returns HPLL frequency in kHz */
139 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
140 {
141         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142 
143         /* Obtain SKU information */
144         mutex_lock(&dev_priv->sb_lock);
145         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146                 CCK_FUSE_HPLL_FREQ_MASK;
147         mutex_unlock(&dev_priv->sb_lock);
148 
149         return vco_freq[hpll_freq] * 1000;
150 }
151 
152 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
153                                   const char *name, u32 reg)
154 {
155         u32 val;
156         int divider;
157 
158         if (dev_priv->hpll_freq == 0)
159                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
160 
161         mutex_lock(&dev_priv->sb_lock);
162         val = vlv_cck_read(dev_priv, reg);
163         mutex_unlock(&dev_priv->sb_lock);
164 
165         divider = val & CCK_FREQUENCY_VALUES;
166 
167         WARN((val & CCK_FREQUENCY_STATUS) !=
168              (divider << CCK_FREQUENCY_STATUS_SHIFT),
169              "%s change in progress\n", name);
170 
171         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
172 }
173 
174 int
175 intel_pch_rawclk(struct drm_device *dev)
176 {
177         struct drm_i915_private *dev_priv = dev->dev_private;
178 
179         WARN_ON(!HAS_PCH_SPLIT(dev));
180 
181         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
182 }
183 
184 /* hrawclock is 1/4 the FSB frequency */
185 int intel_hrawclk(struct drm_device *dev)
186 {
187         struct drm_i915_private *dev_priv = dev->dev_private;
188         uint32_t clkcfg;
189 
190         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
191         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
192                 return 200;
193 
194         clkcfg = I915_READ(CLKCFG);
195         switch (clkcfg & CLKCFG_FSB_MASK) {
196         case CLKCFG_FSB_400:
197                 return 100;
198         case CLKCFG_FSB_533:
199                 return 133;
200         case CLKCFG_FSB_667:
201                 return 166;
202         case CLKCFG_FSB_800:
203                 return 200;
204         case CLKCFG_FSB_1067:
205                 return 266;
206         case CLKCFG_FSB_1333:
207                 return 333;
208         /* these two are just a guess; one of them might be right */
209         case CLKCFG_FSB_1600:
210         case CLKCFG_FSB_1600_ALT:
211                 return 400;
212         default:
213                 return 133;
214         }
215 }
216 
217 static void intel_update_czclk(struct drm_i915_private *dev_priv)
218 {
219         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
220                 return;
221 
222         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
223                                                       CCK_CZ_CLOCK_CONTROL);
224 
225         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
226 }
227 
228 static inline u32 /* units of 100MHz */
229 intel_fdi_link_freq(struct drm_device *dev)
230 {
231         if (IS_GEN5(dev)) {
232                 struct drm_i915_private *dev_priv = dev->dev_private;
233                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
234         } else
235                 return 27;
236 }
237 
238 static const intel_limit_t intel_limits_i8xx_dac = {
239         .dot = { .min = 25000, .max = 350000 },
240         .vco = { .min = 908000, .max = 1512000 },
241         .n = { .min = 2, .max = 16 },
242         .m = { .min = 96, .max = 140 },
243         .m1 = { .min = 18, .max = 26 },
244         .m2 = { .min = 6, .max = 16 },
245         .p = { .min = 4, .max = 128 },
246         .p1 = { .min = 2, .max = 33 },
247         .p2 = { .dot_limit = 165000,
248                 .p2_slow = 4, .p2_fast = 2 },
249 };
250 
251 static const intel_limit_t intel_limits_i8xx_dvo = {
252         .dot = { .min = 25000, .max = 350000 },
253         .vco = { .min = 908000, .max = 1512000 },
254         .n = { .min = 2, .max = 16 },
255         .m = { .min = 96, .max = 140 },
256         .m1 = { .min = 18, .max = 26 },
257         .m2 = { .min = 6, .max = 16 },
258         .p = { .min = 4, .max = 128 },
259         .p1 = { .min = 2, .max = 33 },
260         .p2 = { .dot_limit = 165000,
261                 .p2_slow = 4, .p2_fast = 4 },
262 };
263 
264 static const intel_limit_t intel_limits_i8xx_lvds = {
265         .dot = { .min = 25000, .max = 350000 },
266         .vco = { .min = 908000, .max = 1512000 },
267         .n = { .min = 2, .max = 16 },
268         .m = { .min = 96, .max = 140 },
269         .m1 = { .min = 18, .max = 26 },
270         .m2 = { .min = 6, .max = 16 },
271         .p = { .min = 4, .max = 128 },
272         .p1 = { .min = 1, .max = 6 },
273         .p2 = { .dot_limit = 165000,
274                 .p2_slow = 14, .p2_fast = 7 },
275 };
276 
277 static const intel_limit_t intel_limits_i9xx_sdvo = {
278         .dot = { .min = 20000, .max = 400000 },
279         .vco = { .min = 1400000, .max = 2800000 },
280         .n = { .min = 1, .max = 6 },
281         .m = { .min = 70, .max = 120 },
282         .m1 = { .min = 8, .max = 18 },
283         .m2 = { .min = 3, .max = 7 },
284         .p = { .min = 5, .max = 80 },
285         .p1 = { .min = 1, .max = 8 },
286         .p2 = { .dot_limit = 200000,
287                 .p2_slow = 10, .p2_fast = 5 },
288 };
289 
290 static const intel_limit_t intel_limits_i9xx_lvds = {
291         .dot = { .min = 20000, .max = 400000 },
292         .vco = { .min = 1400000, .max = 2800000 },
293         .n = { .min = 1, .max = 6 },
294         .m = { .min = 70, .max = 120 },
295         .m1 = { .min = 8, .max = 18 },
296         .m2 = { .min = 3, .max = 7 },
297         .p = { .min = 7, .max = 98 },
298         .p1 = { .min = 1, .max = 8 },
299         .p2 = { .dot_limit = 112000,
300                 .p2_slow = 14, .p2_fast = 7 },
301 };
302 
303 
304 static const intel_limit_t intel_limits_g4x_sdvo = {
305         .dot = { .min = 25000, .max = 270000 },
306         .vco = { .min = 1750000, .max = 3500000},
307         .n = { .min = 1, .max = 4 },
308         .m = { .min = 104, .max = 138 },
309         .m1 = { .min = 17, .max = 23 },
310         .m2 = { .min = 5, .max = 11 },
311         .p = { .min = 10, .max = 30 },
312         .p1 = { .min = 1, .max = 3},
313         .p2 = { .dot_limit = 270000,
314                 .p2_slow = 10,
315                 .p2_fast = 10
316         },
317 };
318 
319 static const intel_limit_t intel_limits_g4x_hdmi = {
320         .dot = { .min = 22000, .max = 400000 },
321         .vco = { .min = 1750000, .max = 3500000},
322         .n = { .min = 1, .max = 4 },
323         .m = { .min = 104, .max = 138 },
324         .m1 = { .min = 16, .max = 23 },
325         .m2 = { .min = 5, .max = 11 },
326         .p = { .min = 5, .max = 80 },
327         .p1 = { .min = 1, .max = 8},
328         .p2 = { .dot_limit = 165000,
329                 .p2_slow = 10, .p2_fast = 5 },
330 };
331 
332 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
333         .dot = { .min = 20000, .max = 115000 },
334         .vco = { .min = 1750000, .max = 3500000 },
335         .n = { .min = 1, .max = 3 },
336         .m = { .min = 104, .max = 138 },
337         .m1 = { .min = 17, .max = 23 },
338         .m2 = { .min = 5, .max = 11 },
339         .p = { .min = 28, .max = 112 },
340         .p1 = { .min = 2, .max = 8 },
341         .p2 = { .dot_limit = 0,
342                 .p2_slow = 14, .p2_fast = 14
343         },
344 };
345 
346 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
347         .dot = { .min = 80000, .max = 224000 },
348         .vco = { .min = 1750000, .max = 3500000 },
349         .n = { .min = 1, .max = 3 },
350         .m = { .min = 104, .max = 138 },
351         .m1 = { .min = 17, .max = 23 },
352         .m2 = { .min = 5, .max = 11 },
353         .p = { .min = 14, .max = 42 },
354         .p1 = { .min = 2, .max = 6 },
355         .p2 = { .dot_limit = 0,
356                 .p2_slow = 7, .p2_fast = 7
357         },
358 };
359 
360 static const intel_limit_t intel_limits_pineview_sdvo = {
361         .dot = { .min = 20000, .max = 400000},
362         .vco = { .min = 1700000, .max = 3500000 },
363         /* Pineview's Ncounter is a ring counter */
364         .n = { .min = 3, .max = 6 },
365         .m = { .min = 2, .max = 256 },
366         /* Pineview only has one combined m divider, which we treat as m2. */
367         .m1 = { .min = 0, .max = 0 },
368         .m2 = { .min = 0, .max = 254 },
369         .p = { .min = 5, .max = 80 },
370         .p1 = { .min = 1, .max = 8 },
371         .p2 = { .dot_limit = 200000,
372                 .p2_slow = 10, .p2_fast = 5 },
373 };
374 
375 static const intel_limit_t intel_limits_pineview_lvds = {
376         .dot = { .min = 20000, .max = 400000 },
377         .vco = { .min = 1700000, .max = 3500000 },
378         .n = { .min = 3, .max = 6 },
379         .m = { .min = 2, .max = 256 },
380         .m1 = { .min = 0, .max = 0 },
381         .m2 = { .min = 0, .max = 254 },
382         .p = { .min = 7, .max = 112 },
383         .p1 = { .min = 1, .max = 8 },
384         .p2 = { .dot_limit = 112000,
385                 .p2_slow = 14, .p2_fast = 14 },
386 };
387 
388 /* Ironlake / Sandybridge
389  *
390  * We calculate clock using (register_value + 2) for N/M1/M2, so here
391  * the range value for them is (actual_value - 2).
392  */
393 static const intel_limit_t intel_limits_ironlake_dac = {
394         .dot = { .min = 25000, .max = 350000 },
395         .vco = { .min = 1760000, .max = 3510000 },
396         .n = { .min = 1, .max = 5 },
397         .m = { .min = 79, .max = 127 },
398         .m1 = { .min = 12, .max = 22 },
399         .m2 = { .min = 5, .max = 9 },
400         .p = { .min = 5, .max = 80 },
401         .p1 = { .min = 1, .max = 8 },
402         .p2 = { .dot_limit = 225000,
403                 .p2_slow = 10, .p2_fast = 5 },
404 };
405 
406 static const intel_limit_t intel_limits_ironlake_single_lvds = {
407         .dot = { .min = 25000, .max = 350000 },
408         .vco = { .min = 1760000, .max = 3510000 },
409         .n = { .min = 1, .max = 3 },
410         .m = { .min = 79, .max = 118 },
411         .m1 = { .min = 12, .max = 22 },
412         .m2 = { .min = 5, .max = 9 },
413         .p = { .min = 28, .max = 112 },
414         .p1 = { .min = 2, .max = 8 },
415         .p2 = { .dot_limit = 225000,
416                 .p2_slow = 14, .p2_fast = 14 },
417 };
418 
419 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
420         .dot = { .min = 25000, .max = 350000 },
421         .vco = { .min = 1760000, .max = 3510000 },
422         .n = { .min = 1, .max = 3 },
423         .m = { .min = 79, .max = 127 },
424         .m1 = { .min = 12, .max = 22 },
425         .m2 = { .min = 5, .max = 9 },
426         .p = { .min = 14, .max = 56 },
427         .p1 = { .min = 2, .max = 8 },
428         .p2 = { .dot_limit = 225000,
429                 .p2_slow = 7, .p2_fast = 7 },
430 };
431 
432 /* LVDS 100mhz refclk limits. */
433 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
434         .dot = { .min = 25000, .max = 350000 },
435         .vco = { .min = 1760000, .max = 3510000 },
436         .n = { .min = 1, .max = 2 },
437         .m = { .min = 79, .max = 126 },
438         .m1 = { .min = 12, .max = 22 },
439         .m2 = { .min = 5, .max = 9 },
440         .p = { .min = 28, .max = 112 },
441         .p1 = { .min = 2, .max = 8 },
442         .p2 = { .dot_limit = 225000,
443                 .p2_slow = 14, .p2_fast = 14 },
444 };
445 
446 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
447         .dot = { .min = 25000, .max = 350000 },
448         .vco = { .min = 1760000, .max = 3510000 },
449         .n = { .min = 1, .max = 3 },
450         .m = { .min = 79, .max = 126 },
451         .m1 = { .min = 12, .max = 22 },
452         .m2 = { .min = 5, .max = 9 },
453         .p = { .min = 14, .max = 42 },
454         .p1 = { .min = 2, .max = 6 },
455         .p2 = { .dot_limit = 225000,
456                 .p2_slow = 7, .p2_fast = 7 },
457 };
458 
459 static const intel_limit_t intel_limits_vlv = {
460          /*
461           * These are the data rate limits (measured in fast clocks)
462           * since those are the strictest limits we have. The fast
463           * clock and actual rate limits are more relaxed, so checking
464           * them would make no difference.
465           */
466         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
467         .vco = { .min = 4000000, .max = 6000000 },
468         .n = { .min = 1, .max = 7 },
469         .m1 = { .min = 2, .max = 3 },
470         .m2 = { .min = 11, .max = 156 },
471         .p1 = { .min = 2, .max = 3 },
472         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
473 };
474 
475 static const intel_limit_t intel_limits_chv = {
476         /*
477          * These are the data rate limits (measured in fast clocks)
478          * since those are the strictest limits we have.  The fast
479          * clock and actual rate limits are more relaxed, so checking
480          * them would make no difference.
481          */
482         .dot = { .min = 25000 * 5, .max = 540000 * 5},
483         .vco = { .min = 4800000, .max = 6480000 },
484         .n = { .min = 1, .max = 1 },
485         .m1 = { .min = 2, .max = 2 },
486         .m2 = { .min = 24 << 22, .max = 175 << 22 },
487         .p1 = { .min = 2, .max = 4 },
488         .p2 = { .p2_slow = 1, .p2_fast = 14 },
489 };
490 
491 static const intel_limit_t intel_limits_bxt = {
492         /* FIXME: find real dot limits */
493         .dot = { .min = 0, .max = INT_MAX },
494         .vco = { .min = 4800000, .max = 6700000 },
495         .n = { .min = 1, .max = 1 },
496         .m1 = { .min = 2, .max = 2 },
497         /* FIXME: find real m2 limits */
498         .m2 = { .min = 2 << 22, .max = 255 << 22 },
499         .p1 = { .min = 2, .max = 4 },
500         .p2 = { .p2_slow = 1, .p2_fast = 20 },
501 };
502 
503 static bool
504 needs_modeset(struct drm_crtc_state *state)
505 {
506         return drm_atomic_crtc_needs_modeset(state);
507 }
508 
509 /**
510  * Returns whether any output on the specified pipe is of the specified type
511  */
512 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
513 {
514         struct drm_device *dev = crtc->base.dev;
515         struct intel_encoder *encoder;
516 
517         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
518                 if (encoder->type == type)
519                         return true;
520 
521         return false;
522 }
523 
524 /**
525  * Returns whether any output on the specified pipe will have the specified
526  * type after a staged modeset is complete, i.e., the same as
527  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
528  * encoder->crtc.
529  */
530 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
531                                       int type)
532 {
533         struct drm_atomic_state *state = crtc_state->base.state;
534         struct drm_connector *connector;
535         struct drm_connector_state *connector_state;
536         struct intel_encoder *encoder;
537         int i, num_connectors = 0;
538 
539         for_each_connector_in_state(state, connector, connector_state, i) {
540                 if (connector_state->crtc != crtc_state->base.crtc)
541                         continue;
542 
543                 num_connectors++;
544 
545                 encoder = to_intel_encoder(connector_state->best_encoder);
546                 if (encoder->type == type)
547                         return true;
548         }
549 
550         WARN_ON(num_connectors == 0);
551 
552         return false;
553 }
554 
555 static const intel_limit_t *
556 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
557 {
558         struct drm_device *dev = crtc_state->base.crtc->dev;
559         const intel_limit_t *limit;
560 
561         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
562                 if (intel_is_dual_link_lvds(dev)) {
563                         if (refclk == 100000)
564                                 limit = &intel_limits_ironlake_dual_lvds_100m;
565                         else
566                                 limit = &intel_limits_ironlake_dual_lvds;
567                 } else {
568                         if (refclk == 100000)
569                                 limit = &intel_limits_ironlake_single_lvds_100m;
570                         else
571                                 limit = &intel_limits_ironlake_single_lvds;
572                 }
573         } else
574                 limit = &intel_limits_ironlake_dac;
575 
576         return limit;
577 }
578 
579 static const intel_limit_t *
580 intel_g4x_limit(struct intel_crtc_state *crtc_state)
581 {
582         struct drm_device *dev = crtc_state->base.crtc->dev;
583         const intel_limit_t *limit;
584 
585         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
586                 if (intel_is_dual_link_lvds(dev))
587                         limit = &intel_limits_g4x_dual_channel_lvds;
588                 else
589                         limit = &intel_limits_g4x_single_channel_lvds;
590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
591                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
592                 limit = &intel_limits_g4x_hdmi;
593         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
594                 limit = &intel_limits_g4x_sdvo;
595         } else /* The option is for other outputs */
596                 limit = &intel_limits_i9xx_sdvo;
597 
598         return limit;
599 }
600 
601 static const intel_limit_t *
602 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
603 {
604         struct drm_device *dev = crtc_state->base.crtc->dev;
605         const intel_limit_t *limit;
606 
607         if (IS_BROXTON(dev))
608                 limit = &intel_limits_bxt;
609         else if (HAS_PCH_SPLIT(dev))
610                 limit = intel_ironlake_limit(crtc_state, refclk);
611         else if (IS_G4X(dev)) {
612                 limit = intel_g4x_limit(crtc_state);
613         } else if (IS_PINEVIEW(dev)) {
614                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
615                         limit = &intel_limits_pineview_lvds;
616                 else
617                         limit = &intel_limits_pineview_sdvo;
618         } else if (IS_CHERRYVIEW(dev)) {
619                 limit = &intel_limits_chv;
620         } else if (IS_VALLEYVIEW(dev)) {
621                 limit = &intel_limits_vlv;
622         } else if (!IS_GEN2(dev)) {
623                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
624                         limit = &intel_limits_i9xx_lvds;
625                 else
626                         limit = &intel_limits_i9xx_sdvo;
627         } else {
628                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
629                         limit = &intel_limits_i8xx_lvds;
630                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
631                         limit = &intel_limits_i8xx_dvo;
632                 else
633                         limit = &intel_limits_i8xx_dac;
634         }
635         return limit;
636 }
637 
638 /*
639  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
640  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
641  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
642  * The helpers' return value is the rate of the clock that is fed to the
643  * display engine's pipe which can be the above fast dot clock rate or a
644  * divided-down version of it.
645  */
646 /* m1 is reserved as 0 in Pineview, n is a ring counter */
647 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
648 {
649         clock->m = clock->m2 + 2;
650         clock->p = clock->p1 * clock->p2;
651         if (WARN_ON(clock->n == 0 || clock->p == 0))
652                 return 0;
653         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
654         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
655 
656         return clock->dot;
657 }
658 
659 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
660 {
661         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
662 }
663 
664 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
665 {
666         clock->m = i9xx_dpll_compute_m(clock);
667         clock->p = clock->p1 * clock->p2;
668         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
669                 return 0;
670         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
671         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
672 
673         return clock->dot;
674 }
675 
676 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
677 {
678         clock->m = clock->m1 * clock->m2;
679         clock->p = clock->p1 * clock->p2;
680         if (WARN_ON(clock->n == 0 || clock->p == 0))
681                 return 0;
682         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
683         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
684 
685         return clock->dot / 5;
686 }
687 
688 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
689 {
690         clock->m = clock->m1 * clock->m2;
691         clock->p = clock->p1 * clock->p2;
692         if (WARN_ON(clock->n == 0 || clock->p == 0))
693                 return 0;
694         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
695                         clock->n << 22);
696         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
697 
698         return clock->dot / 5;
699 }
700 
701 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
702 /**
703  * Returns whether the given set of divisors are valid for a given refclk with
704  * the given connectors.
705  */
706 
707 static bool intel_PLL_is_valid(struct drm_device *dev,
708                                const intel_limit_t *limit,
709                                const intel_clock_t *clock)
710 {
711         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
712                 INTELPllInvalid("n out of range\n");
713         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
714                 INTELPllInvalid("p1 out of range\n");
715         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
716                 INTELPllInvalid("m2 out of range\n");
717         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
718                 INTELPllInvalid("m1 out of range\n");
719 
720         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
721             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
722                 if (clock->m1 <= clock->m2)
723                         INTELPllInvalid("m1 <= m2\n");
724 
725         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
726                 if (clock->p < limit->p.min || limit->p.max < clock->p)
727                         INTELPllInvalid("p out of range\n");
728                 if (clock->m < limit->m.min || limit->m.max < clock->m)
729                         INTELPllInvalid("m out of range\n");
730         }
731 
732         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
733                 INTELPllInvalid("vco out of range\n");
734         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
735          * connector, etc., rather than just a single range.
736          */
737         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
738                 INTELPllInvalid("dot out of range\n");
739 
740         return true;
741 }
742 
743 static int
744 i9xx_select_p2_div(const intel_limit_t *limit,
745                    const struct intel_crtc_state *crtc_state,
746                    int target)
747 {
748         struct drm_device *dev = crtc_state->base.crtc->dev;
749 
750         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
751                 /*
752                  * For LVDS just rely on its current settings for dual-channel.
753                  * We haven't figured out how to reliably set up different
754                  * single/dual channel state, if we even can.
755                  */
756                 if (intel_is_dual_link_lvds(dev))
757                         return limit->p2.p2_fast;
758                 else
759                         return limit->p2.p2_slow;
760         } else {
761                 if (target < limit->p2.dot_limit)
762                         return limit->p2.p2_slow;
763                 else
764                         return limit->p2.p2_fast;
765         }
766 }
767 
768 static bool
769 i9xx_find_best_dpll(const intel_limit_t *limit,
770                     struct intel_crtc_state *crtc_state,
771                     int target, int refclk, intel_clock_t *match_clock,
772                     intel_clock_t *best_clock)
773 {
774         struct drm_device *dev = crtc_state->base.crtc->dev;
775         intel_clock_t clock;
776         int err = target;
777 
778         memset(best_clock, 0, sizeof(*best_clock));
779 
780         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
781 
782         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
783              clock.m1++) {
784                 for (clock.m2 = limit->m2.min;
785                      clock.m2 <= limit->m2.max; clock.m2++) {
786                         if (clock.m2 >= clock.m1)
787                                 break;
788                         for (clock.n = limit->n.min;
789                              clock.n <= limit->n.max; clock.n++) {
790                                 for (clock.p1 = limit->p1.min;
791                                         clock.p1 <= limit->p1.max; clock.p1++) {
792                                         int this_err;
793 
794                                         i9xx_calc_dpll_params(refclk, &clock);
795                                         if (!intel_PLL_is_valid(dev, limit,
796                                                                 &clock))
797                                                 continue;
798                                         if (match_clock &&
799                                             clock.p != match_clock->p)
800                                                 continue;
801 
802                                         this_err = abs(clock.dot - target);
803                                         if (this_err < err) {
804                                                 *best_clock = clock;
805                                                 err = this_err;
806                                         }
807                                 }
808                         }
809                 }
810         }
811 
812         return (err != target);
813 }
814 
815 static bool
816 pnv_find_best_dpll(const intel_limit_t *limit,
817                    struct intel_crtc_state *crtc_state,
818                    int target, int refclk, intel_clock_t *match_clock,
819                    intel_clock_t *best_clock)
820 {
821         struct drm_device *dev = crtc_state->base.crtc->dev;
822         intel_clock_t clock;
823         int err = target;
824 
825         memset(best_clock, 0, sizeof(*best_clock));
826 
827         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
828 
829         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
830              clock.m1++) {
831                 for (clock.m2 = limit->m2.min;
832                      clock.m2 <= limit->m2.max; clock.m2++) {
833                         for (clock.n = limit->n.min;
834                              clock.n <= limit->n.max; clock.n++) {
835                                 for (clock.p1 = limit->p1.min;
836                                         clock.p1 <= limit->p1.max; clock.p1++) {
837                                         int this_err;
838 
839                                         pnv_calc_dpll_params(refclk, &clock);
840                                         if (!intel_PLL_is_valid(dev, limit,
841                                                                 &clock))
842                                                 continue;
843                                         if (match_clock &&
844                                             clock.p != match_clock->p)
845                                                 continue;
846 
847                                         this_err = abs(clock.dot - target);
848                                         if (this_err < err) {
849                                                 *best_clock = clock;
850                                                 err = this_err;
851                                         }
852                                 }
853                         }
854                 }
855         }
856 
857         return (err != target);
858 }
859 
860 static bool
861 g4x_find_best_dpll(const intel_limit_t *limit,
862                    struct intel_crtc_state *crtc_state,
863                    int target, int refclk, intel_clock_t *match_clock,
864                    intel_clock_t *best_clock)
865 {
866         struct drm_device *dev = crtc_state->base.crtc->dev;
867         intel_clock_t clock;
868         int max_n;
869         bool found = false;
870         /* approximately equals target * 0.00585 */
871         int err_most = (target >> 8) + (target >> 9);
872 
873         memset(best_clock, 0, sizeof(*best_clock));
874 
875         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
876 
877         max_n = limit->n.max;
878         /* based on hardware requirement, prefer smaller n to precision */
879         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880                 /* based on hardware requirement, prefere larger m1,m2 */
881                 for (clock.m1 = limit->m1.max;
882                      clock.m1 >= limit->m1.min; clock.m1--) {
883                         for (clock.m2 = limit->m2.max;
884                              clock.m2 >= limit->m2.min; clock.m2--) {
885                                 for (clock.p1 = limit->p1.max;
886                                      clock.p1 >= limit->p1.min; clock.p1--) {
887                                         int this_err;
888 
889                                         i9xx_calc_dpll_params(refclk, &clock);
890                                         if (!intel_PLL_is_valid(dev, limit,
891                                                                 &clock))
892                                                 continue;
893 
894                                         this_err = abs(clock.dot - target);
895                                         if (this_err < err_most) {
896                                                 *best_clock = clock;
897                                                 err_most = this_err;
898                                                 max_n = clock.n;
899                                                 found = true;
900                                         }
901                                 }
902                         }
903                 }
904         }
905         return found;
906 }
907 
908 /*
909  * Check if the calculated PLL configuration is more optimal compared to the
910  * best configuration and error found so far. Return the calculated error.
911  */
912 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
913                                const intel_clock_t *calculated_clock,
914                                const intel_clock_t *best_clock,
915                                unsigned int best_error_ppm,
916                                unsigned int *error_ppm)
917 {
918         /*
919          * For CHV ignore the error and consider only the P value.
920          * Prefer a bigger P value based on HW requirements.
921          */
922         if (IS_CHERRYVIEW(dev)) {
923                 *error_ppm = 0;
924 
925                 return calculated_clock->p > best_clock->p;
926         }
927 
928         if (WARN_ON_ONCE(!target_freq))
929                 return false;
930 
931         *error_ppm = div_u64(1000000ULL *
932                                 abs(target_freq - calculated_clock->dot),
933                              target_freq);
934         /*
935          * Prefer a better P value over a better (smaller) error if the error
936          * is small. Ensure this preference for future configurations too by
937          * setting the error to 0.
938          */
939         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
940                 *error_ppm = 0;
941 
942                 return true;
943         }
944 
945         return *error_ppm + 10 < best_error_ppm;
946 }
947 
948 static bool
949 vlv_find_best_dpll(const intel_limit_t *limit,
950                    struct intel_crtc_state *crtc_state,
951                    int target, int refclk, intel_clock_t *match_clock,
952                    intel_clock_t *best_clock)
953 {
954         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
955         struct drm_device *dev = crtc->base.dev;
956         intel_clock_t clock;
957         unsigned int bestppm = 1000000;
958         /* min update 19.2 MHz */
959         int max_n = min(limit->n.max, refclk / 19200);
960         bool found = false;
961 
962         target *= 5; /* fast clock */
963 
964         memset(best_clock, 0, sizeof(*best_clock));
965 
966         /* based on hardware requirement, prefer smaller n to precision */
967         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
968                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
969                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
970                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
971                                 clock.p = clock.p1 * clock.p2;
972                                 /* based on hardware requirement, prefer bigger m1,m2 values */
973                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
974                                         unsigned int ppm;
975 
976                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
977                                                                      refclk * clock.m1);
978 
979                                         vlv_calc_dpll_params(refclk, &clock);
980 
981                                         if (!intel_PLL_is_valid(dev, limit,
982                                                                 &clock))
983                                                 continue;
984 
985                                         if (!vlv_PLL_is_optimal(dev, target,
986                                                                 &clock,
987                                                                 best_clock,
988                                                                 bestppm, &ppm))
989                                                 continue;
990 
991                                         *best_clock = clock;
992                                         bestppm = ppm;
993                                         found = true;
994                                 }
995                         }
996                 }
997         }
998 
999         return found;
1000 }
1001 
1002 static bool
1003 chv_find_best_dpll(const intel_limit_t *limit,
1004                    struct intel_crtc_state *crtc_state,
1005                    int target, int refclk, intel_clock_t *match_clock,
1006                    intel_clock_t *best_clock)
1007 {
1008         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1009         struct drm_device *dev = crtc->base.dev;
1010         unsigned int best_error_ppm;
1011         intel_clock_t clock;
1012         uint64_t m2;
1013         int found = false;
1014 
1015         memset(best_clock, 0, sizeof(*best_clock));
1016         best_error_ppm = 1000000;
1017 
1018         /*
1019          * Based on hardware doc, the n always set to 1, and m1 always
1020          * set to 2.  If requires to support 200Mhz refclk, we need to
1021          * revisit this because n may not 1 anymore.
1022          */
1023         clock.n = 1, clock.m1 = 2;
1024         target *= 5;    /* fast clock */
1025 
1026         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1027                 for (clock.p2 = limit->p2.p2_fast;
1028                                 clock.p2 >= limit->p2.p2_slow;
1029                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1030                         unsigned int error_ppm;
1031 
1032                         clock.p = clock.p1 * clock.p2;
1033 
1034                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1035                                         clock.n) << 22, refclk * clock.m1);
1036 
1037                         if (m2 > INT_MAX/clock.m1)
1038                                 continue;
1039 
1040                         clock.m2 = m2;
1041 
1042                         chv_calc_dpll_params(refclk, &clock);
1043 
1044                         if (!intel_PLL_is_valid(dev, limit, &clock))
1045                                 continue;
1046 
1047                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1048                                                 best_error_ppm, &error_ppm))
1049                                 continue;
1050 
1051                         *best_clock = clock;
1052                         best_error_ppm = error_ppm;
1053                         found = true;
1054                 }
1055         }
1056 
1057         return found;
1058 }
1059 
1060 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1061                         intel_clock_t *best_clock)
1062 {
1063         int refclk = i9xx_get_refclk(crtc_state, 0);
1064 
1065         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1066                                   target_clock, refclk, NULL, best_clock);
1067 }
1068 
1069 bool intel_crtc_active(struct drm_crtc *crtc)
1070 {
1071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072 
1073         /* Be paranoid as we can arrive here with only partial
1074          * state retrieved from the hardware during setup.
1075          *
1076          * We can ditch the adjusted_mode.crtc_clock check as soon
1077          * as Haswell has gained clock readout/fastboot support.
1078          *
1079          * We can ditch the crtc->primary->fb check as soon as we can
1080          * properly reconstruct framebuffers.
1081          *
1082          * FIXME: The intel_crtc->active here should be switched to
1083          * crtc->state->active once we have proper CRTC states wired up
1084          * for atomic.
1085          */
1086         return intel_crtc->active && crtc->primary->state->fb &&
1087                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1088 }
1089 
1090 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1091                                              enum pipe pipe)
1092 {
1093         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1095 
1096         return intel_crtc->config->cpu_transcoder;
1097 }
1098 
1099 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1100 {
1101         struct drm_i915_private *dev_priv = dev->dev_private;
1102         i915_reg_t reg = PIPEDSL(pipe);
1103         u32 line1, line2;
1104         u32 line_mask;
1105 
1106         if (IS_GEN2(dev))
1107                 line_mask = DSL_LINEMASK_GEN2;
1108         else
1109                 line_mask = DSL_LINEMASK_GEN3;
1110 
1111         line1 = I915_READ(reg) & line_mask;
1112         msleep(5);
1113         line2 = I915_READ(reg) & line_mask;
1114 
1115         return line1 == line2;
1116 }
1117 
1118 /*
1119  * intel_wait_for_pipe_off - wait for pipe to turn off
1120  * @crtc: crtc whose pipe to wait for
1121  *
1122  * After disabling a pipe, we can't wait for vblank in the usual way,
1123  * spinning on the vblank interrupt status bit, since we won't actually
1124  * see an interrupt when the pipe is disabled.
1125  *
1126  * On Gen4 and above:
1127  *   wait for the pipe register state bit to turn off
1128  *
1129  * Otherwise:
1130  *   wait for the display line value to settle (it usually
1131  *   ends up stopping at the start of the next frame).
1132  *
1133  */
1134 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1135 {
1136         struct drm_device *dev = crtc->base.dev;
1137         struct drm_i915_private *dev_priv = dev->dev_private;
1138         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1139         enum pipe pipe = crtc->pipe;
1140 
1141         if (INTEL_INFO(dev)->gen >= 4) {
1142                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1143 
1144                 /* Wait for the Pipe State to go off */
1145                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1146                              100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         } else {
1149                 /* Wait for the display line to settle */
1150                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1151                         WARN(1, "pipe_off wait timed out\n");
1152         }
1153 }
1154 
1155 static const char *state_string(bool enabled)
1156 {
1157         return enabled ? "on" : "off";
1158 }
1159 
1160 /* Only for pre-ILK configs */
1161 void assert_pll(struct drm_i915_private *dev_priv,
1162                 enum pipe pipe, bool state)
1163 {
1164         u32 val;
1165         bool cur_state;
1166 
1167         val = I915_READ(DPLL(pipe));
1168         cur_state = !!(val & DPLL_VCO_ENABLE);
1169         I915_STATE_WARN(cur_state != state,
1170              "PLL state assertion failure (expected %s, current %s)\n",
1171              state_string(state), state_string(cur_state));
1172 }
1173 
1174 /* XXX: the dsi pll is shared between MIPI DSI ports */
1175 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1176 {
1177         u32 val;
1178         bool cur_state;
1179 
1180         mutex_lock(&dev_priv->sb_lock);
1181         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1182         mutex_unlock(&dev_priv->sb_lock);
1183 
1184         cur_state = val & DSI_PLL_VCO_EN;
1185         I915_STATE_WARN(cur_state != state,
1186              "DSI PLL state assertion failure (expected %s, current %s)\n",
1187              state_string(state), state_string(cur_state));
1188 }
1189 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1190 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1191 
1192 struct intel_shared_dpll *
1193 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1194 {
1195         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1196 
1197         if (crtc->config->shared_dpll < 0)
1198                 return NULL;
1199 
1200         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1201 }
1202 
1203 /* For ILK+ */
1204 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1205                         struct intel_shared_dpll *pll,
1206                         bool state)
1207 {
1208         bool cur_state;
1209         struct intel_dpll_hw_state hw_state;
1210 
1211         if (WARN (!pll,
1212                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1213                 return;
1214 
1215         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1216         I915_STATE_WARN(cur_state != state,
1217              "%s assertion failure (expected %s, current %s)\n",
1218              pll->name, state_string(state), state_string(cur_state));
1219 }
1220 
1221 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1222                           enum pipe pipe, bool state)
1223 {
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227 
1228         if (HAS_DDI(dev_priv->dev)) {
1229                 /* DDI does not have a specific FDI_TX register */
1230                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1231                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1232         } else {
1233                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1234                 cur_state = !!(val & FDI_TX_ENABLE);
1235         }
1236         I915_STATE_WARN(cur_state != state,
1237              "FDI TX state assertion failure (expected %s, current %s)\n",
1238              state_string(state), state_string(cur_state));
1239 }
1240 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1241 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1242 
1243 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1244                           enum pipe pipe, bool state)
1245 {
1246         u32 val;
1247         bool cur_state;
1248 
1249         val = I915_READ(FDI_RX_CTL(pipe));
1250         cur_state = !!(val & FDI_RX_ENABLE);
1251         I915_STATE_WARN(cur_state != state,
1252              "FDI RX state assertion failure (expected %s, current %s)\n",
1253              state_string(state), state_string(cur_state));
1254 }
1255 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1256 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1257 
1258 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1259                                       enum pipe pipe)
1260 {
1261         u32 val;
1262 
1263         /* ILK FDI PLL is always enabled */
1264         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1265                 return;
1266 
1267         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1268         if (HAS_DDI(dev_priv->dev))
1269                 return;
1270 
1271         val = I915_READ(FDI_TX_CTL(pipe));
1272         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1273 }
1274 
1275 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1276                        enum pipe pipe, bool state)
1277 {
1278         u32 val;
1279         bool cur_state;
1280 
1281         val = I915_READ(FDI_RX_CTL(pipe));
1282         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1283         I915_STATE_WARN(cur_state != state,
1284              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1285              state_string(state), state_string(cur_state));
1286 }
1287 
1288 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1289                            enum pipe pipe)
1290 {
1291         struct drm_device *dev = dev_priv->dev;
1292         i915_reg_t pp_reg;
1293         u32 val;
1294         enum pipe panel_pipe = PIPE_A;
1295         bool locked = true;
1296 
1297         if (WARN_ON(HAS_DDI(dev)))
1298                 return;
1299 
1300         if (HAS_PCH_SPLIT(dev)) {
1301                 u32 port_sel;
1302 
1303                 pp_reg = PCH_PP_CONTROL;
1304                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1305 
1306                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1307                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1308                         panel_pipe = PIPE_B;
1309                 /* XXX: else fix for eDP */
1310         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1311                 /* presumably write lock depends on pipe, not port select */
1312                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1313                 panel_pipe = pipe;
1314         } else {
1315                 pp_reg = PP_CONTROL;
1316                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1317                         panel_pipe = PIPE_B;
1318         }
1319 
1320         val = I915_READ(pp_reg);
1321         if (!(val & PANEL_POWER_ON) ||
1322             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1323                 locked = false;
1324 
1325         I915_STATE_WARN(panel_pipe == pipe && locked,
1326              "panel assertion failure, pipe %c regs locked\n",
1327              pipe_name(pipe));
1328 }
1329 
1330 static void assert_cursor(struct drm_i915_private *dev_priv,
1331                           enum pipe pipe, bool state)
1332 {
1333         struct drm_device *dev = dev_priv->dev;
1334         bool cur_state;
1335 
1336         if (IS_845G(dev) || IS_I865G(dev))
1337                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1338         else
1339                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1340 
1341         I915_STATE_WARN(cur_state != state,
1342              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1343              pipe_name(pipe), state_string(state), state_string(cur_state));
1344 }
1345 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1346 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1347 
1348 void assert_pipe(struct drm_i915_private *dev_priv,
1349                  enum pipe pipe, bool state)
1350 {
1351         bool cur_state;
1352         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1353                                                                       pipe);
1354         enum intel_display_power_domain power_domain;
1355 
1356         /* if we need the pipe quirk it must be always on */
1357         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1358             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1359                 state = true;
1360 
1361         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1362         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1363                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1364                 cur_state = !!(val & PIPECONF_ENABLE);
1365 
1366                 intel_display_power_put(dev_priv, power_domain);
1367         } else {
1368                 cur_state = false;
1369         }
1370 
1371         I915_STATE_WARN(cur_state != state,
1372              "pipe %c assertion failure (expected %s, current %s)\n",
1373              pipe_name(pipe), state_string(state), state_string(cur_state));
1374 }
1375 
1376 static void assert_plane(struct drm_i915_private *dev_priv,
1377                          enum plane plane, bool state)
1378 {
1379         u32 val;
1380         bool cur_state;
1381 
1382         val = I915_READ(DSPCNTR(plane));
1383         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1384         I915_STATE_WARN(cur_state != state,
1385              "plane %c assertion failure (expected %s, current %s)\n",
1386              plane_name(plane), state_string(state), state_string(cur_state));
1387 }
1388 
1389 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1390 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1391 
1392 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1393                                    enum pipe pipe)
1394 {
1395         struct drm_device *dev = dev_priv->dev;
1396         int i;
1397 
1398         /* Primary planes are fixed to pipes on gen4+ */
1399         if (INTEL_INFO(dev)->gen >= 4) {
1400                 u32 val = I915_READ(DSPCNTR(pipe));
1401                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1402                      "plane %c assertion failure, should be disabled but not\n",
1403                      plane_name(pipe));
1404                 return;
1405         }
1406 
1407         /* Need to check both planes against the pipe */
1408         for_each_pipe(dev_priv, i) {
1409                 u32 val = I915_READ(DSPCNTR(i));
1410                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1411                         DISPPLANE_SEL_PIPE_SHIFT;
1412                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1413                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1414                      plane_name(i), pipe_name(pipe));
1415         }
1416 }
1417 
1418 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1419                                     enum pipe pipe)
1420 {
1421         struct drm_device *dev = dev_priv->dev;
1422         int sprite;
1423 
1424         if (INTEL_INFO(dev)->gen >= 9) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1427                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1428                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite, pipe_name(pipe));
1430                 }
1431         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1432                 for_each_sprite(dev_priv, pipe, sprite) {
1433                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1434                         I915_STATE_WARN(val & SP_ENABLE,
1435                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1436                              sprite_name(pipe, sprite), pipe_name(pipe));
1437                 }
1438         } else if (INTEL_INFO(dev)->gen >= 7) {
1439                 u32 val = I915_READ(SPRCTL(pipe));
1440                 I915_STATE_WARN(val & SPRITE_ENABLE,
1441                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442                      plane_name(pipe), pipe_name(pipe));
1443         } else if (INTEL_INFO(dev)->gen >= 5) {
1444                 u32 val = I915_READ(DVSCNTR(pipe));
1445                 I915_STATE_WARN(val & DVS_ENABLE,
1446                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1447                      plane_name(pipe), pipe_name(pipe));
1448         }
1449 }
1450 
1451 static void assert_vblank_disabled(struct drm_crtc *crtc)
1452 {
1453         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1454                 drm_crtc_vblank_put(crtc);
1455 }
1456 
1457 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1458 {
1459         u32 val;
1460         bool enabled;
1461 
1462         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1463 
1464         val = I915_READ(PCH_DREF_CONTROL);
1465         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1466                             DREF_SUPERSPREAD_SOURCE_MASK));
1467         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1468 }
1469 
1470 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1471                                            enum pipe pipe)
1472 {
1473         u32 val;
1474         bool enabled;
1475 
1476         val = I915_READ(PCH_TRANSCONF(pipe));
1477         enabled = !!(val & TRANS_ENABLE);
1478         I915_STATE_WARN(enabled,
1479              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1480              pipe_name(pipe));
1481 }
1482 
1483 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1484                             enum pipe pipe, u32 port_sel, u32 val)
1485 {
1486         if ((val & DP_PORT_EN) == 0)
1487                 return false;
1488 
1489         if (HAS_PCH_CPT(dev_priv->dev)) {
1490                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1491                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1492                         return false;
1493         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1494                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1495                         return false;
1496         } else {
1497                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1498                         return false;
1499         }
1500         return true;
1501 }
1502 
1503 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1504                               enum pipe pipe, u32 val)
1505 {
1506         if ((val & SDVO_ENABLE) == 0)
1507                 return false;
1508 
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1511                         return false;
1512         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1513                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1514                         return false;
1515         } else {
1516                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1517                         return false;
1518         }
1519         return true;
1520 }
1521 
1522 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1523                               enum pipe pipe, u32 val)
1524 {
1525         if ((val & LVDS_PORT_EN) == 0)
1526                 return false;
1527 
1528         if (HAS_PCH_CPT(dev_priv->dev)) {
1529                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1530                         return false;
1531         } else {
1532                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1533                         return false;
1534         }
1535         return true;
1536 }
1537 
1538 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1539                               enum pipe pipe, u32 val)
1540 {
1541         if ((val & ADPA_DAC_ENABLE) == 0)
1542                 return false;
1543         if (HAS_PCH_CPT(dev_priv->dev)) {
1544                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1545                         return false;
1546         } else {
1547                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1548                         return false;
1549         }
1550         return true;
1551 }
1552 
1553 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1554                                    enum pipe pipe, i915_reg_t reg,
1555                                    u32 port_sel)
1556 {
1557         u32 val = I915_READ(reg);
1558         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1559              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1560              i915_mmio_reg_offset(reg), pipe_name(pipe));
1561 
1562         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1563              && (val & DP_PIPEB_SELECT),
1564              "IBX PCH dp port still using transcoder B\n");
1565 }
1566 
1567 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1568                                      enum pipe pipe, i915_reg_t reg)
1569 {
1570         u32 val = I915_READ(reg);
1571         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1572              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1573              i915_mmio_reg_offset(reg), pipe_name(pipe));
1574 
1575         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1576              && (val & SDVO_PIPE_B_SELECT),
1577              "IBX PCH hdmi port still using transcoder B\n");
1578 }
1579 
1580 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1581                                       enum pipe pipe)
1582 {
1583         u32 val;
1584 
1585         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1586         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1587         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1588 
1589         val = I915_READ(PCH_ADPA);
1590         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1591              "PCH VGA enabled on transcoder %c, should be disabled\n",
1592              pipe_name(pipe));
1593 
1594         val = I915_READ(PCH_LVDS);
1595         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1596              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1597              pipe_name(pipe));
1598 
1599         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1600         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1601         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1602 }
1603 
1604 static void vlv_enable_pll(struct intel_crtc *crtc,
1605                            const struct intel_crtc_state *pipe_config)
1606 {
1607         struct drm_device *dev = crtc->base.dev;
1608         struct drm_i915_private *dev_priv = dev->dev_private;
1609         i915_reg_t reg = DPLL(crtc->pipe);
1610         u32 dpll = pipe_config->dpll_hw_state.dpll;
1611 
1612         assert_pipe_disabled(dev_priv, crtc->pipe);
1613 
1614         /* PLL is protected by panel, make sure we can write it */
1615         if (IS_MOBILE(dev_priv->dev))
1616                 assert_panel_unlocked(dev_priv, crtc->pipe);
1617 
1618         I915_WRITE(reg, dpll);
1619         POSTING_READ(reg);
1620         udelay(150);
1621 
1622         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1624 
1625         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1626         POSTING_READ(DPLL_MD(crtc->pipe));
1627 
1628         /* We do this three times for luck */
1629         I915_WRITE(reg, dpll);
1630         POSTING_READ(reg);
1631         udelay(150); /* wait for warmup */
1632         I915_WRITE(reg, dpll);
1633         POSTING_READ(reg);
1634         udelay(150); /* wait for warmup */
1635         I915_WRITE(reg, dpll);
1636         POSTING_READ(reg);
1637         udelay(150); /* wait for warmup */
1638 }
1639 
1640 static void chv_enable_pll(struct intel_crtc *crtc,
1641                            const struct intel_crtc_state *pipe_config)
1642 {
1643         struct drm_device *dev = crtc->base.dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         int pipe = crtc->pipe;
1646         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1647         u32 tmp;
1648 
1649         assert_pipe_disabled(dev_priv, crtc->pipe);
1650 
1651         mutex_lock(&dev_priv->sb_lock);
1652 
1653         /* Enable back the 10bit clock to display controller */
1654         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1655         tmp |= DPIO_DCLKP_EN;
1656         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1657 
1658         mutex_unlock(&dev_priv->sb_lock);
1659 
1660         /*
1661          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1662          */
1663         udelay(1);
1664 
1665         /* Enable PLL */
1666         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1667 
1668         /* Check PLL is locked */
1669         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1670                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1671 
1672         /* not sure when this should be written */
1673         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1674         POSTING_READ(DPLL_MD(pipe));
1675 }
1676 
1677 static int intel_num_dvo_pipes(struct drm_device *dev)
1678 {
1679         struct intel_crtc *crtc;
1680         int count = 0;
1681 
1682         for_each_intel_crtc(dev, crtc)
1683                 count += crtc->base.state->active &&
1684                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1685 
1686         return count;
1687 }
1688 
1689 static void i9xx_enable_pll(struct intel_crtc *crtc)
1690 {
1691         struct drm_device *dev = crtc->base.dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         i915_reg_t reg = DPLL(crtc->pipe);
1694         u32 dpll = crtc->config->dpll_hw_state.dpll;
1695 
1696         assert_pipe_disabled(dev_priv, crtc->pipe);
1697 
1698         /* No really, not for ILK+ */
1699         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1700 
1701         /* PLL is protected by panel, make sure we can write it */
1702         if (IS_MOBILE(dev) && !IS_I830(dev))
1703                 assert_panel_unlocked(dev_priv, crtc->pipe);
1704 
1705         /* Enable DVO 2x clock on both PLLs if necessary */
1706         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1707                 /*
1708                  * It appears to be important that we don't enable this
1709                  * for the current pipe before otherwise configuring the
1710                  * PLL. No idea how this should be handled if multiple
1711                  * DVO outputs are enabled simultaneosly.
1712                  */
1713                 dpll |= DPLL_DVO_2X_MODE;
1714                 I915_WRITE(DPLL(!crtc->pipe),
1715                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1716         }
1717 
1718         /*
1719          * Apparently we need to have VGA mode enabled prior to changing
1720          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1721          * dividers, even though the register value does change.
1722          */
1723         I915_WRITE(reg, 0);
1724 
1725         I915_WRITE(reg, dpll);
1726 
1727         /* Wait for the clocks to stabilize. */
1728         POSTING_READ(reg);
1729         udelay(150);
1730 
1731         if (INTEL_INFO(dev)->gen >= 4) {
1732                 I915_WRITE(DPLL_MD(crtc->pipe),
1733                            crtc->config->dpll_hw_state.dpll_md);
1734         } else {
1735                 /* The pixel multiplier can only be updated once the
1736                  * DPLL is enabled and the clocks are stable.
1737                  *
1738                  * So write it again.
1739                  */
1740                 I915_WRITE(reg, dpll);
1741         }
1742 
1743         /* We do this three times for luck */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753 }
1754 
1755 /**
1756  * i9xx_disable_pll - disable a PLL
1757  * @dev_priv: i915 private structure
1758  * @pipe: pipe PLL to disable
1759  *
1760  * Disable the PLL for @pipe, making sure the pipe is off first.
1761  *
1762  * Note!  This is for pre-ILK only.
1763  */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766         struct drm_device *dev = crtc->base.dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         enum pipe pipe = crtc->pipe;
1769 
1770         /* Disable DVO 2x clock on both PLLs if necessary */
1771         if (IS_I830(dev) &&
1772             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773             !intel_num_dvo_pipes(dev)) {
1774                 I915_WRITE(DPLL(PIPE_B),
1775                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776                 I915_WRITE(DPLL(PIPE_A),
1777                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778         }
1779 
1780         /* Don't disable pipe or pipe PLLs if needed */
1781         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783                 return;
1784 
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787 
1788         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1789         POSTING_READ(DPLL(pipe));
1790 }
1791 
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794         u32 val;
1795 
1796         /* Make sure the pipe isn't still relying on us */
1797         assert_pipe_disabled(dev_priv, pipe);
1798 
1799         /*
1800          * Leave integrated clock source and reference clock enabled for pipe B.
1801          * The latter is needed for VGA hotplug / manual detection.
1802          */
1803         val = DPLL_VGA_MODE_DIS;
1804         if (pipe == PIPE_B)
1805                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1806         I915_WRITE(DPLL(pipe), val);
1807         POSTING_READ(DPLL(pipe));
1808 
1809 }
1810 
1811 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1814         u32 val;
1815 
1816         /* Make sure the pipe isn't still relying on us */
1817         assert_pipe_disabled(dev_priv, pipe);
1818 
1819         /* Set PLL en = 0 */
1820         val = DPLL_SSC_REF_CLK_CHV |
1821                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1822         if (pipe != PIPE_A)
1823                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824         I915_WRITE(DPLL(pipe), val);
1825         POSTING_READ(DPLL(pipe));
1826 
1827         mutex_lock(&dev_priv->sb_lock);
1828 
1829         /* Disable 10bit clock to display controller */
1830         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831         val &= ~DPIO_DCLKP_EN;
1832         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833 
1834         mutex_unlock(&dev_priv->sb_lock);
1835 }
1836 
1837 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1838                          struct intel_digital_port *dport,
1839                          unsigned int expected_mask)
1840 {
1841         u32 port_mask;
1842         i915_reg_t dpll_reg;
1843 
1844         switch (dport->port) {
1845         case PORT_B:
1846                 port_mask = DPLL_PORTB_READY_MASK;
1847                 dpll_reg = DPLL(0);
1848                 break;
1849         case PORT_C:
1850                 port_mask = DPLL_PORTC_READY_MASK;
1851                 dpll_reg = DPLL(0);
1852                 expected_mask <<= 4;
1853                 break;
1854         case PORT_D:
1855                 port_mask = DPLL_PORTD_READY_MASK;
1856                 dpll_reg = DPIO_PHY_STATUS;
1857                 break;
1858         default:
1859                 BUG();
1860         }
1861 
1862         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1863                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1864                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1865 }
1866 
1867 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1868 {
1869         struct drm_device *dev = crtc->base.dev;
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1872 
1873         if (WARN_ON(pll == NULL))
1874                 return;
1875 
1876         WARN_ON(!pll->config.crtc_mask);
1877         if (pll->active == 0) {
1878                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1879                 WARN_ON(pll->on);
1880                 assert_shared_dpll_disabled(dev_priv, pll);
1881 
1882                 pll->mode_set(dev_priv, pll);
1883         }
1884 }
1885 
1886 /**
1887  * intel_enable_shared_dpll - enable PCH PLL
1888  * @dev_priv: i915 private structure
1889  * @pipe: pipe PLL to enable
1890  *
1891  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1892  * drives the transcoder clock.
1893  */
1894 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1895 {
1896         struct drm_device *dev = crtc->base.dev;
1897         struct drm_i915_private *dev_priv = dev->dev_private;
1898         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1899 
1900         if (WARN_ON(pll == NULL))
1901                 return;
1902 
1903         if (WARN_ON(pll->config.crtc_mask == 0))
1904                 return;
1905 
1906         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1907                       pll->name, pll->active, pll->on,
1908                       crtc->base.base.id);
1909 
1910         if (pll->active++) {
1911                 WARN_ON(!pll->on);
1912                 assert_shared_dpll_enabled(dev_priv, pll);
1913                 return;
1914         }
1915         WARN_ON(pll->on);
1916 
1917         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1918 
1919         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1920         pll->enable(dev_priv, pll);
1921         pll->on = true;
1922 }
1923 
1924 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1925 {
1926         struct drm_device *dev = crtc->base.dev;
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1929 
1930         /* PCH only available on ILK+ */
1931         if (INTEL_INFO(dev)->gen < 5)
1932                 return;
1933 
1934         if (pll == NULL)
1935                 return;
1936 
1937         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1938                 return;
1939 
1940         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1941                       pll->name, pll->active, pll->on,
1942                       crtc->base.base.id);
1943 
1944         if (WARN_ON(pll->active == 0)) {
1945                 assert_shared_dpll_disabled(dev_priv, pll);
1946                 return;
1947         }
1948 
1949         assert_shared_dpll_enabled(dev_priv, pll);
1950         WARN_ON(!pll->on);
1951         if (--pll->active)
1952                 return;
1953 
1954         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1955         pll->disable(dev_priv, pll);
1956         pll->on = false;
1957 
1958         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1959 }
1960 
1961 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1962                                            enum pipe pipe)
1963 {
1964         struct drm_device *dev = dev_priv->dev;
1965         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1967         i915_reg_t reg;
1968         uint32_t val, pipeconf_val;
1969 
1970         /* PCH only available on ILK+ */
1971         BUG_ON(!HAS_PCH_SPLIT(dev));
1972 
1973         /* Make sure PCH DPLL is enabled */
1974         assert_shared_dpll_enabled(dev_priv,
1975                                    intel_crtc_to_shared_dpll(intel_crtc));
1976 
1977         /* FDI must be feeding us bits for PCH ports */
1978         assert_fdi_tx_enabled(dev_priv, pipe);
1979         assert_fdi_rx_enabled(dev_priv, pipe);
1980 
1981         if (HAS_PCH_CPT(dev)) {
1982                 /* Workaround: Set the timing override bit before enabling the
1983                  * pch transcoder. */
1984                 reg = TRANS_CHICKEN2(pipe);
1985                 val = I915_READ(reg);
1986                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1987                 I915_WRITE(reg, val);
1988         }
1989 
1990         reg = PCH_TRANSCONF(pipe);
1991         val = I915_READ(reg);
1992         pipeconf_val = I915_READ(PIPECONF(pipe));
1993 
1994         if (HAS_PCH_IBX(dev_priv->dev)) {
1995                 /*
1996                  * Make the BPC in transcoder be consistent with
1997                  * that in pipeconf reg. For HDMI we must use 8bpc
1998                  * here for both 8bpc and 12bpc.
1999                  */
2000                 val &= ~PIPECONF_BPC_MASK;
2001                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2002                         val |= PIPECONF_8BPC;
2003                 else
2004                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2005         }
2006 
2007         val &= ~TRANS_INTERLACE_MASK;
2008         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2009                 if (HAS_PCH_IBX(dev_priv->dev) &&
2010                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2011                         val |= TRANS_LEGACY_INTERLACED_ILK;
2012                 else
2013                         val |= TRANS_INTERLACED;
2014         else
2015                 val |= TRANS_PROGRESSIVE;
2016 
2017         I915_WRITE(reg, val | TRANS_ENABLE);
2018         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2019                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2020 }
2021 
2022 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2023                                       enum transcoder cpu_transcoder)
2024 {
2025         u32 val, pipeconf_val;
2026 
2027         /* PCH only available on ILK+ */
2028         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2029 
2030         /* FDI must be feeding us bits for PCH ports */
2031         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2032         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2033 
2034         /* Workaround: set timing override bit. */
2035         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2036         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2037         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2038 
2039         val = TRANS_ENABLE;
2040         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2041 
2042         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2043             PIPECONF_INTERLACED_ILK)
2044                 val |= TRANS_INTERLACED;
2045         else
2046                 val |= TRANS_PROGRESSIVE;
2047 
2048         I915_WRITE(LPT_TRANSCONF, val);
2049         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2050                 DRM_ERROR("Failed to enable PCH transcoder\n");
2051 }
2052 
2053 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2054                                             enum pipe pipe)
2055 {
2056         struct drm_device *dev = dev_priv->dev;
2057         i915_reg_t reg;
2058         uint32_t val;
2059 
2060         /* FDI relies on the transcoder */
2061         assert_fdi_tx_disabled(dev_priv, pipe);
2062         assert_fdi_rx_disabled(dev_priv, pipe);
2063 
2064         /* Ports must be off as well */
2065         assert_pch_ports_disabled(dev_priv, pipe);
2066 
2067         reg = PCH_TRANSCONF(pipe);
2068         val = I915_READ(reg);
2069         val &= ~TRANS_ENABLE;
2070         I915_WRITE(reg, val);
2071         /* wait for PCH transcoder off, transcoder state */
2072         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2073                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2074 
2075         if (HAS_PCH_CPT(dev)) {
2076                 /* Workaround: Clear the timing override chicken bit again. */
2077                 reg = TRANS_CHICKEN2(pipe);
2078                 val = I915_READ(reg);
2079                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080                 I915_WRITE(reg, val);
2081         }
2082 }
2083 
2084 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2085 {
2086         u32 val;
2087 
2088         val = I915_READ(LPT_TRANSCONF);
2089         val &= ~TRANS_ENABLE;
2090         I915_WRITE(LPT_TRANSCONF, val);
2091         /* wait for PCH transcoder off, transcoder state */
2092         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2093                 DRM_ERROR("Failed to disable PCH transcoder\n");
2094 
2095         /* Workaround: clear timing override bit. */
2096         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2097         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2098         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2099 }
2100 
2101 /**
2102  * intel_enable_pipe - enable a pipe, asserting requirements
2103  * @crtc: crtc responsible for the pipe
2104  *
2105  * Enable @crtc's pipe, making sure that various hardware specific requirements
2106  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2107  */
2108 static void intel_enable_pipe(struct intel_crtc *crtc)
2109 {
2110         struct drm_device *dev = crtc->base.dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         enum pipe pipe = crtc->pipe;
2113         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2114         enum pipe pch_transcoder;
2115         i915_reg_t reg;
2116         u32 val;
2117 
2118         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2119 
2120         assert_planes_disabled(dev_priv, pipe);
2121         assert_cursor_disabled(dev_priv, pipe);
2122         assert_sprites_disabled(dev_priv, pipe);
2123 
2124         if (HAS_PCH_LPT(dev_priv->dev))
2125                 pch_transcoder = TRANSCODER_A;
2126         else
2127                 pch_transcoder = pipe;
2128 
2129         /*
2130          * A pipe without a PLL won't actually be able to drive bits from
2131          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2132          * need the check.
2133          */
2134         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135                 if (crtc->config->has_dsi_encoder)
2136                         assert_dsi_pll_enabled(dev_priv);
2137                 else
2138                         assert_pll_enabled(dev_priv, pipe);
2139         else {
2140                 if (crtc->config->has_pch_encoder) {
2141                         /* if driving the PCH, we need FDI enabled */
2142                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143                         assert_fdi_tx_pll_enabled(dev_priv,
2144                                                   (enum pipe) cpu_transcoder);
2145                 }
2146                 /* FIXME: assert CPU port conditions for SNB+ */
2147         }
2148 
2149         reg = PIPECONF(cpu_transcoder);
2150         val = I915_READ(reg);
2151         if (val & PIPECONF_ENABLE) {
2152                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154                 return;
2155         }
2156 
2157         I915_WRITE(reg, val | PIPECONF_ENABLE);
2158         POSTING_READ(reg);
2159 }
2160 
2161 /**
2162  * intel_disable_pipe - disable a pipe, asserting requirements
2163  * @crtc: crtc whose pipes is to be disabled
2164  *
2165  * Disable the pipe of @crtc, making sure that various hardware
2166  * specific requirements are met, if applicable, e.g. plane
2167  * disabled, panel fitter off, etc.
2168  *
2169  * Will wait until the pipe has shut down before returning.
2170  */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175         enum pipe pipe = crtc->pipe;
2176         i915_reg_t reg;
2177         u32 val;
2178 
2179         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180 
2181         /*
2182          * Make sure planes won't keep trying to pump pixels to us,
2183          * or we might hang the display.
2184          */
2185         assert_planes_disabled(dev_priv, pipe);
2186         assert_cursor_disabled(dev_priv, pipe);
2187         assert_sprites_disabled(dev_priv, pipe);
2188 
2189         reg = PIPECONF(cpu_transcoder);
2190         val = I915_READ(reg);
2191         if ((val & PIPECONF_ENABLE) == 0)
2192                 return;
2193 
2194         /*
2195          * Double wide has implications for planes
2196          * so best keep it disabled when not needed.
2197          */
2198         if (crtc->config->double_wide)
2199                 val &= ~PIPECONF_DOUBLE_WIDE;
2200 
2201         /* Don't disable pipe or pipe PLLs if needed */
2202         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204                 val &= ~PIPECONF_ENABLE;
2205 
2206         I915_WRITE(reg, val);
2207         if ((val & PIPECONF_ENABLE) == 0)
2208                 intel_wait_for_pipe_off(crtc);
2209 }
2210 
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215                 return true;
2216 #endif
2217         return false;
2218 }
2219 
2220 unsigned int
2221 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2222                   uint64_t fb_format_modifier, unsigned int plane)
2223 {
2224         unsigned int tile_height;
2225         uint32_t pixel_bytes;
2226 
2227         switch (fb_format_modifier) {
2228         case DRM_FORMAT_MOD_NONE:
2229                 tile_height = 1;
2230                 break;
2231         case I915_FORMAT_MOD_X_TILED:
2232                 tile_height = IS_GEN2(dev) ? 16 : 8;
2233                 break;
2234         case I915_FORMAT_MOD_Y_TILED:
2235                 tile_height = 32;
2236                 break;
2237         case I915_FORMAT_MOD_Yf_TILED:
2238                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2239                 switch (pixel_bytes) {
2240                 default:
2241                 case 1:
2242                         tile_height = 64;
2243                         break;
2244                 case 2:
2245                 case 4:
2246                         tile_height = 32;
2247                         break;
2248                 case 8:
2249                         tile_height = 16;
2250                         break;
2251                 case 16:
2252                         WARN_ONCE(1,
2253                                   "128-bit pixels are not supported for display!");
2254                         tile_height = 16;
2255                         break;
2256                 }
2257                 break;
2258         default:
2259                 MISSING_CASE(fb_format_modifier);
2260                 tile_height = 1;
2261                 break;
2262         }
2263 
2264         return tile_height;
2265 }
2266 
2267 unsigned int
2268 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2269                       uint32_t pixel_format, uint64_t fb_format_modifier)
2270 {
2271         return ALIGN(height, intel_tile_height(dev, pixel_format,
2272                                                fb_format_modifier, 0));
2273 }
2274 
2275 static void
2276 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2277                         const struct drm_plane_state *plane_state)
2278 {
2279         struct intel_rotation_info *info = &view->params.rotation_info;
2280         unsigned int tile_height, tile_pitch;
2281 
2282         *view = i915_ggtt_view_normal;
2283 
2284         if (!plane_state)
2285                 return;
2286 
2287         if (!intel_rotation_90_or_270(plane_state->rotation))
2288                 return;
2289 
2290         *view = i915_ggtt_view_rotated;
2291 
2292         info->height = fb->height;
2293         info->pixel_format = fb->pixel_format;
2294         info->pitch = fb->pitches[0];
2295         info->uv_offset = fb->offsets[1];
2296         info->fb_modifier = fb->modifier[0];
2297 
2298         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2299                                         fb->modifier[0], 0);
2300         tile_pitch = PAGE_SIZE / tile_height;
2301         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2302         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2303         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2304 
2305         if (info->pixel_format == DRM_FORMAT_NV12) {
2306                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2307                                                 fb->modifier[0], 1);
2308                 tile_pitch = PAGE_SIZE / tile_height;
2309                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2310                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2311                                                      tile_height);
2312                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2313                                 PAGE_SIZE;
2314         }
2315 }
2316 
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2318 {
2319         if (INTEL_INFO(dev_priv)->gen >= 9)
2320                 return 256 * 1024;
2321         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2323                 return 128 * 1024;
2324         else if (INTEL_INFO(dev_priv)->gen >= 4)
2325                 return 4 * 1024;
2326         else
2327                 return 0;
2328 }
2329 
2330 int
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332                            struct drm_framebuffer *fb,
2333                            const struct drm_plane_state *plane_state)
2334 {
2335         struct drm_device *dev = fb->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338         struct i915_ggtt_view view;
2339         u32 alignment;
2340         int ret;
2341 
2342         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343 
2344         switch (fb->modifier[0]) {
2345         case DRM_FORMAT_MOD_NONE:
2346                 alignment = intel_linear_alignment(dev_priv);
2347                 break;
2348         case I915_FORMAT_MOD_X_TILED:
2349                 if (INTEL_INFO(dev)->gen >= 9)
2350                         alignment = 256 * 1024;
2351                 else {
2352                         /* pin() will align the object as required by fence */
2353                         alignment = 0;
2354                 }
2355                 break;
2356         case I915_FORMAT_MOD_Y_TILED:
2357         case I915_FORMAT_MOD_Yf_TILED:
2358                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2359                           "Y tiling bo slipped through, driver bug!\n"))
2360                         return -EINVAL;
2361                 alignment = 1 * 1024 * 1024;
2362                 break;
2363         default:
2364                 MISSING_CASE(fb->modifier[0]);
2365                 return -EINVAL;
2366         }
2367 
2368         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2369 
2370         /* Note that the w/a also requires 64 PTE of padding following the
2371          * bo. We currently fill all unused PTE with the shadow page and so
2372          * we should always have valid PTE following the scanout preventing
2373          * the VT-d warning.
2374          */
2375         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2376                 alignment = 256 * 1024;
2377 
2378         /*
2379          * Global gtt pte registers are special registers which actually forward
2380          * writes to a chunk of system memory. Which means that there is no risk
2381          * that the register values disappear as soon as we call
2382          * intel_runtime_pm_put(), so it is correct to wrap only the
2383          * pin/unpin/fence and not more.
2384          */
2385         intel_runtime_pm_get(dev_priv);
2386 
2387         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2388                                                    &view);
2389         if (ret)
2390                 goto err_pm;
2391 
2392         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393          * fence, whereas 965+ only requires a fence if using
2394          * framebuffer compression.  For simplicity, we always install
2395          * a fence as the cost is not that onerous.
2396          */
2397         if (view.type == I915_GGTT_VIEW_NORMAL) {
2398                 ret = i915_gem_object_get_fence(obj);
2399                 if (ret == -EDEADLK) {
2400                         /*
2401                          * -EDEADLK means there are no free fences
2402                          * no pending flips.
2403                          *
2404                          * This is propagated to atomic, but it uses
2405                          * -EDEADLK to force a locking recovery, so
2406                          * change the returned error to -EBUSY.
2407                          */
2408                         ret = -EBUSY;
2409                         goto err_unpin;
2410                 } else if (ret)
2411                         goto err_unpin;
2412 
2413                 i915_gem_object_pin_fence(obj);
2414         }
2415 
2416         intel_runtime_pm_put(dev_priv);
2417         return 0;
2418 
2419 err_unpin:
2420         i915_gem_object_unpin_from_display_plane(obj, &view);
2421 err_pm:
2422         intel_runtime_pm_put(dev_priv);
2423         return ret;
2424 }
2425 
2426 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2427                                const struct drm_plane_state *plane_state)
2428 {
2429         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2430         struct i915_ggtt_view view;
2431 
2432         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433 
2434         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435 
2436         if (view.type == I915_GGTT_VIEW_NORMAL)
2437                 i915_gem_object_unpin_fence(obj);
2438 
2439         i915_gem_object_unpin_from_display_plane(obj, &view);
2440 }
2441 
2442 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2443  * is assumed to be a power-of-two. */
2444 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2445                                              int *x, int *y,
2446                                              unsigned int tiling_mode,
2447                                              unsigned int cpp,
2448                                              unsigned int pitch)
2449 {
2450         if (tiling_mode != I915_TILING_NONE) {
2451                 unsigned int tile_rows, tiles;
2452 
2453                 tile_rows = *y / 8;
2454                 *y %= 8;
2455 
2456                 tiles = *x / (512/cpp);
2457                 *x %= 512/cpp;
2458 
2459                 return tile_rows * pitch * 8 + tiles * 4096;
2460         } else {
2461                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2462                 unsigned int offset;
2463 
2464                 offset = *y * pitch + *x * cpp;
2465                 *y = (offset & alignment) / pitch;
2466                 *x = ((offset & alignment) - *y * pitch) / cpp;
2467                 return offset & ~alignment;
2468         }
2469 }
2470 
2471 static int i9xx_format_to_fourcc(int format)
2472 {
2473         switch (format) {
2474         case DISPPLANE_8BPP:
2475                 return DRM_FORMAT_C8;
2476         case DISPPLANE_BGRX555:
2477                 return DRM_FORMAT_XRGB1555;
2478         case DISPPLANE_BGRX565:
2479                 return DRM_FORMAT_RGB565;
2480         default:
2481         case DISPPLANE_BGRX888:
2482                 return DRM_FORMAT_XRGB8888;
2483         case DISPPLANE_RGBX888:
2484                 return DRM_FORMAT_XBGR8888;
2485         case DISPPLANE_BGRX101010:
2486                 return DRM_FORMAT_XRGB2101010;
2487         case DISPPLANE_RGBX101010:
2488                 return DRM_FORMAT_XBGR2101010;
2489         }
2490 }
2491 
2492 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493 {
2494         switch (format) {
2495         case PLANE_CTL_FORMAT_RGB_565:
2496                 return DRM_FORMAT_RGB565;
2497         default:
2498         case PLANE_CTL_FORMAT_XRGB_8888:
2499                 if (rgb_order) {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ABGR8888;
2502                         else
2503                                 return DRM_FORMAT_XBGR8888;
2504                 } else {
2505                         if (alpha)
2506                                 return DRM_FORMAT_ARGB8888;
2507                         else
2508                                 return DRM_FORMAT_XRGB8888;
2509                 }
2510         case PLANE_CTL_FORMAT_XRGB_2101010:
2511                 if (rgb_order)
2512                         return DRM_FORMAT_XBGR2101010;
2513                 else
2514                         return DRM_FORMAT_XRGB2101010;
2515         }
2516 }
2517 
2518 static bool
2519 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520                               struct intel_initial_plane_config *plane_config)
2521 {
2522         struct drm_device *dev = crtc->base.dev;
2523         struct drm_i915_private *dev_priv = to_i915(dev);
2524         struct drm_i915_gem_object *obj = NULL;
2525         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526         struct drm_framebuffer *fb = &plane_config->fb->base;
2527         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529                                     PAGE_SIZE);
2530 
2531         size_aligned -= base_aligned;
2532 
2533         if (plane_config->size == 0)
2534                 return false;
2535 
2536         /* If the FB is too big, just don't use it since fbdev is not very
2537          * important and we should probably use that space with FBC or other
2538          * features. */
2539         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2540                 return false;
2541 
2542         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2543                                                              base_aligned,
2544                                                              base_aligned,
2545                                                              size_aligned);
2546         if (!obj)
2547                 return false;
2548 
2549         obj->tiling_mode = plane_config->tiling;
2550         if (obj->tiling_mode == I915_TILING_X)
2551                 obj->stride = fb->pitches[0];
2552 
2553         mode_cmd.pixel_format = fb->pixel_format;
2554         mode_cmd.width = fb->width;
2555         mode_cmd.height = fb->height;
2556         mode_cmd.pitches[0] = fb->pitches[0];
2557         mode_cmd.modifier[0] = fb->modifier[0];
2558         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2559 
2560         mutex_lock(&dev->struct_mutex);
2561         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2562                                    &mode_cmd, obj)) {
2563                 DRM_DEBUG_KMS("intel fb init failed\n");
2564                 goto out_unref_obj;
2565         }
2566         mutex_unlock(&dev->struct_mutex);
2567 
2568         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2569         return true;
2570 
2571 out_unref_obj:
2572         drm_gem_object_unreference(&obj->base);
2573         mutex_unlock(&dev->struct_mutex);
2574         return false;
2575 }
2576 
2577 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2578 static void
2579 update_state_fb(struct drm_plane *plane)
2580 {
2581         if (plane->fb == plane->state->fb)
2582                 return;
2583 
2584         if (plane->state->fb)
2585                 drm_framebuffer_unreference(plane->state->fb);
2586         plane->state->fb = plane->fb;
2587         if (plane->state->fb)
2588                 drm_framebuffer_reference(plane->state->fb);
2589 }
2590 
2591 static void
2592 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2593                              struct intel_initial_plane_config *plane_config)
2594 {
2595         struct drm_device *dev = intel_crtc->base.dev;
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct drm_crtc *c;
2598         struct intel_crtc *i;
2599         struct drm_i915_gem_object *obj;
2600         struct drm_plane *primary = intel_crtc->base.primary;
2601         struct drm_plane_state *plane_state = primary->state;
2602         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2603         struct intel_plane *intel_plane = to_intel_plane(primary);
2604         struct drm_framebuffer *fb;
2605 
2606         if (!plane_config->fb)
2607                 return;
2608 
2609         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2610                 fb = &plane_config->fb->base;
2611                 goto valid_fb;
2612         }
2613 
2614         kfree(plane_config->fb);
2615 
2616         /*
2617          * Failed to alloc the obj, check to see if we should share
2618          * an fb with another CRTC instead
2619          */
2620         for_each_crtc(dev, c) {
2621                 i = to_intel_crtc(c);
2622 
2623                 if (c == &intel_crtc->base)
2624                         continue;
2625 
2626                 if (!i->active)
2627                         continue;
2628 
2629                 fb = c->primary->fb;
2630                 if (!fb)
2631                         continue;
2632 
2633                 obj = intel_fb_obj(fb);
2634                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2635                         drm_framebuffer_reference(fb);
2636                         goto valid_fb;
2637                 }
2638         }
2639 
2640         /*
2641          * We've failed to reconstruct the BIOS FB.  Current display state
2642          * indicates that the primary plane is visible, but has a NULL FB,
2643          * which will lead to problems later if we don't fix it up.  The
2644          * simplest solution is to just disable the primary plane now and
2645          * pretend the BIOS never had it enabled.
2646          */
2647         to_intel_plane_state(plane_state)->visible = false;
2648         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2649         intel_pre_disable_primary(&intel_crtc->base);
2650         intel_plane->disable_plane(primary, &intel_crtc->base);
2651 
2652         return;
2653 
2654 valid_fb:
2655         plane_state->src_x = 0;
2656         plane_state->src_y = 0;
2657         plane_state->src_w = fb->width << 16;
2658         plane_state->src_h = fb->height << 16;
2659 
2660         plane_state->crtc_x = 0;
2661         plane_state->crtc_y = 0;
2662         plane_state->crtc_w = fb->width;
2663         plane_state->crtc_h = fb->height;
2664 
2665         obj = intel_fb_obj(fb);
2666         if (obj->tiling_mode != I915_TILING_NONE)
2667                 dev_priv->preserve_bios_swizzle = true;
2668 
2669         drm_framebuffer_reference(fb);
2670         primary->fb = primary->state->fb = fb;
2671         primary->crtc = primary->state->crtc = &intel_crtc->base;
2672         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2673         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2674 }
2675 
2676 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2677                                       struct drm_framebuffer *fb,
2678                                       int x, int y)
2679 {
2680         struct drm_device *dev = crtc->dev;
2681         struct drm_i915_private *dev_priv = dev->dev_private;
2682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2683         struct drm_plane *primary = crtc->primary;
2684         bool visible = to_intel_plane_state(primary->state)->visible;
2685         struct drm_i915_gem_object *obj;
2686         int plane = intel_crtc->plane;
2687         unsigned long linear_offset;
2688         u32 dspcntr;
2689         i915_reg_t reg = DSPCNTR(plane);
2690         int pixel_size;
2691 
2692         if (!visible || !fb) {
2693                 I915_WRITE(reg, 0);
2694                 if (INTEL_INFO(dev)->gen >= 4)
2695                         I915_WRITE(DSPSURF(plane), 0);
2696                 else
2697                         I915_WRITE(DSPADDR(plane), 0);
2698                 POSTING_READ(reg);
2699                 return;
2700         }
2701 
2702         obj = intel_fb_obj(fb);
2703         if (WARN_ON(obj == NULL))
2704                 return;
2705 
2706         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2707 
2708         dspcntr = DISPPLANE_GAMMA_ENABLE;
2709 
2710         dspcntr |= DISPLAY_PLANE_ENABLE;
2711 
2712         if (INTEL_INFO(dev)->gen < 4) {
2713                 if (intel_crtc->pipe == PIPE_B)
2714                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2715 
2716                 /* pipesrc and dspsize control the size that is scaled from,
2717                  * which should always be the user's requested size.
2718                  */
2719                 I915_WRITE(DSPSIZE(plane),
2720                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2721                            (intel_crtc->config->pipe_src_w - 1));
2722                 I915_WRITE(DSPPOS(plane), 0);
2723         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2724                 I915_WRITE(PRIMSIZE(plane),
2725                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2726                            (intel_crtc->config->pipe_src_w - 1));
2727                 I915_WRITE(PRIMPOS(plane), 0);
2728                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2729         }
2730 
2731         switch (fb->pixel_format) {
2732         case DRM_FORMAT_C8:
2733                 dspcntr |= DISPPLANE_8BPP;
2734                 break;
2735         case DRM_FORMAT_XRGB1555:
2736                 dspcntr |= DISPPLANE_BGRX555;
2737                 break;
2738         case DRM_FORMAT_RGB565:
2739                 dspcntr |= DISPPLANE_BGRX565;
2740                 break;
2741         case DRM_FORMAT_XRGB8888:
2742                 dspcntr |= DISPPLANE_BGRX888;
2743                 break;
2744         case DRM_FORMAT_XBGR8888:
2745                 dspcntr |= DISPPLANE_RGBX888;
2746                 break;
2747         case DRM_FORMAT_XRGB2101010:
2748                 dspcntr |= DISPPLANE_BGRX101010;
2749                 break;
2750         case DRM_FORMAT_XBGR2101010:
2751                 dspcntr |= DISPPLANE_RGBX101010;
2752                 break;
2753         default:
2754                 BUG();
2755         }
2756 
2757         if (INTEL_INFO(dev)->gen >= 4 &&
2758             obj->tiling_mode != I915_TILING_NONE)
2759                 dspcntr |= DISPPLANE_TILED;
2760 
2761         if (IS_G4X(dev))
2762                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2763 
2764         linear_offset = y * fb->pitches[0] + x * pixel_size;
2765 
2766         if (INTEL_INFO(dev)->gen >= 4) {
2767                 intel_crtc->dspaddr_offset =
2768                         intel_gen4_compute_page_offset(dev_priv,
2769                                                        &x, &y, obj->tiling_mode,
2770                                                        pixel_size,
2771                                                        fb->pitches[0]);
2772                 linear_offset -= intel_crtc->dspaddr_offset;
2773         } else {
2774                 intel_crtc->dspaddr_offset = linear_offset;
2775         }
2776 
2777         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2778                 dspcntr |= DISPPLANE_ROTATE_180;
2779 
2780                 x += (intel_crtc->config->pipe_src_w - 1);
2781                 y += (intel_crtc->config->pipe_src_h - 1);
2782 
2783                 /* Finding the last pixel of the last line of the display
2784                 data and adding to linear_offset*/
2785                 linear_offset +=
2786                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2787                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2788         }
2789 
2790         intel_crtc->adjusted_x = x;
2791         intel_crtc->adjusted_y = y;
2792 
2793         I915_WRITE(reg, dspcntr);
2794 
2795         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2796         if (INTEL_INFO(dev)->gen >= 4) {
2797                 I915_WRITE(DSPSURF(plane),
2798                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2799                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2800                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2801         } else
2802                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2803         POSTING_READ(reg);
2804 }
2805 
2806 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2807                                           struct drm_framebuffer *fb,
2808                                           int x, int y)
2809 {
2810         struct drm_device *dev = crtc->dev;
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2813         struct drm_plane *primary = crtc->primary;
2814         bool visible = to_intel_plane_state(primary->state)->visible;
2815         struct drm_i915_gem_object *obj;
2816         int plane = intel_crtc->plane;
2817         unsigned long linear_offset;
2818         u32 dspcntr;
2819         i915_reg_t reg = DSPCNTR(plane);
2820         int pixel_size;
2821 
2822         if (!visible || !fb) {
2823                 I915_WRITE(reg, 0);
2824                 I915_WRITE(DSPSURF(plane), 0);
2825                 POSTING_READ(reg);
2826                 return;
2827         }
2828 
2829         obj = intel_fb_obj(fb);
2830         if (WARN_ON(obj == NULL))
2831                 return;
2832 
2833         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2834 
2835         dspcntr = DISPPLANE_GAMMA_ENABLE;
2836 
2837         dspcntr |= DISPLAY_PLANE_ENABLE;
2838 
2839         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2840                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2841 
2842         switch (fb->pixel_format) {
2843         case DRM_FORMAT_C8:
2844                 dspcntr |= DISPPLANE_8BPP;
2845                 break;
2846         case DRM_FORMAT_RGB565:
2847                 dspcntr |= DISPPLANE_BGRX565;
2848                 break;
2849         case DRM_FORMAT_XRGB8888:
2850                 dspcntr |= DISPPLANE_BGRX888;
2851                 break;
2852         case DRM_FORMAT_XBGR8888:
2853                 dspcntr |= DISPPLANE_RGBX888;
2854                 break;
2855         case DRM_FORMAT_XRGB2101010:
2856                 dspcntr |= DISPPLANE_BGRX101010;
2857                 break;
2858         case DRM_FORMAT_XBGR2101010:
2859                 dspcntr |= DISPPLANE_RGBX101010;
2860                 break;
2861         default:
2862                 BUG();
2863         }
2864 
2865         if (obj->tiling_mode != I915_TILING_NONE)
2866                 dspcntr |= DISPPLANE_TILED;
2867 
2868         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2869                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2870 
2871         linear_offset = y * fb->pitches[0] + x * pixel_size;
2872         intel_crtc->dspaddr_offset =
2873                 intel_gen4_compute_page_offset(dev_priv,
2874                                                &x, &y, obj->tiling_mode,
2875                                                pixel_size,
2876                                                fb->pitches[0]);
2877         linear_offset -= intel_crtc->dspaddr_offset;
2878         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2879                 dspcntr |= DISPPLANE_ROTATE_180;
2880 
2881                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2882                         x += (intel_crtc->config->pipe_src_w - 1);
2883                         y += (intel_crtc->config->pipe_src_h - 1);
2884 
2885                         /* Finding the last pixel of the last line of the display
2886                         data and adding to linear_offset*/
2887                         linear_offset +=
2888                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2889                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2890                 }
2891         }
2892 
2893         intel_crtc->adjusted_x = x;
2894         intel_crtc->adjusted_y = y;
2895 
2896         I915_WRITE(reg, dspcntr);
2897 
2898         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2899         I915_WRITE(DSPSURF(plane),
2900                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2901         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2902                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2903         } else {
2904                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2905                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2906         }
2907         POSTING_READ(reg);
2908 }
2909 
2910 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2911                               uint32_t pixel_format)
2912 {
2913         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2914 
2915         /*
2916          * The stride is either expressed as a multiple of 64 bytes
2917          * chunks for linear buffers or in number of tiles for tiled
2918          * buffers.
2919          */
2920         switch (fb_modifier) {
2921         case DRM_FORMAT_MOD_NONE:
2922                 return 64;
2923         case I915_FORMAT_MOD_X_TILED:
2924                 if (INTEL_INFO(dev)->gen == 2)
2925                         return 128;
2926                 return 512;
2927         case I915_FORMAT_MOD_Y_TILED:
2928                 /* No need to check for old gens and Y tiling since this is
2929                  * about the display engine and those will be blocked before
2930                  * we get here.
2931                  */
2932                 return 128;
2933         case I915_FORMAT_MOD_Yf_TILED:
2934                 if (bits_per_pixel == 8)
2935                         return 64;
2936                 else
2937                         return 128;
2938         default:
2939                 MISSING_CASE(fb_modifier);
2940                 return 64;
2941         }
2942 }
2943 
2944 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2945                            struct drm_i915_gem_object *obj,
2946                            unsigned int plane)
2947 {
2948         struct i915_ggtt_view view;
2949         struct i915_vma *vma;
2950         u64 offset;
2951 
2952         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2953                                 intel_plane->base.state);
2954 
2955         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2956         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2957                 view.type))
2958                 return -1;
2959 
2960         offset = vma->node.start;
2961 
2962         if (plane == 1) {
2963                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2964                           PAGE_SIZE;
2965         }
2966 
2967         WARN_ON(upper_32_bits(offset));
2968 
2969         return lower_32_bits(offset);
2970 }
2971 
2972 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2973 {
2974         struct drm_device *dev = intel_crtc->base.dev;
2975         struct drm_i915_private *dev_priv = dev->dev_private;
2976 
2977         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2978         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2979         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2980 }
2981 
2982 /*
2983  * This function detaches (aka. unbinds) unused scalers in hardware
2984  */
2985 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2986 {
2987         struct intel_crtc_scaler_state *scaler_state;
2988         int i;
2989 
2990         scaler_state = &intel_crtc->config->scaler_state;
2991 
2992         /* loop through and disable scalers that aren't in use */
2993         for (i = 0; i < intel_crtc->num_scalers; i++) {
2994                 if (!scaler_state->scalers[i].in_use)
2995                         skl_detach_scaler(intel_crtc, i);
2996         }
2997 }
2998 
2999 u32 skl_plane_ctl_format(uint32_t pixel_format)
3000 {
3001         switch (pixel_format) {
3002         case DRM_FORMAT_C8:
3003                 return PLANE_CTL_FORMAT_INDEXED;
3004         case DRM_FORMAT_RGB565:
3005                 return PLANE_CTL_FORMAT_RGB_565;
3006         case DRM_FORMAT_XBGR8888:
3007                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3008         case DRM_FORMAT_XRGB8888:
3009                 return PLANE_CTL_FORMAT_XRGB_8888;
3010         /*
3011          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3012          * to be already pre-multiplied. We need to add a knob (or a different
3013          * DRM_FORMAT) for user-space to configure that.
3014          */
3015         case DRM_FORMAT_ABGR8888:
3016                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3017                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3018         case DRM_FORMAT_ARGB8888:
3019                 return PLANE_CTL_FORMAT_XRGB_8888 |
3020                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3021         case DRM_FORMAT_XRGB2101010:
3022                 return PLANE_CTL_FORMAT_XRGB_2101010;
3023         case DRM_FORMAT_XBGR2101010:
3024                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3025         case DRM_FORMAT_YUYV:
3026                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3027         case DRM_FORMAT_YVYU:
3028                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3029         case DRM_FORMAT_UYVY:
3030                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3031         case DRM_FORMAT_VYUY:
3032                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3033         default:
3034                 MISSING_CASE(pixel_format);
3035         }
3036 
3037         return 0;
3038 }
3039 
3040 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3041 {
3042         switch (fb_modifier) {
3043         case DRM_FORMAT_MOD_NONE:
3044                 break;
3045         case I915_FORMAT_MOD_X_TILED:
3046                 return PLANE_CTL_TILED_X;
3047         case I915_FORMAT_MOD_Y_TILED:
3048                 return PLANE_CTL_TILED_Y;
3049         case I915_FORMAT_MOD_Yf_TILED:
3050                 return PLANE_CTL_TILED_YF;
3051         default:
3052                 MISSING_CASE(fb_modifier);
3053         }
3054 
3055         return 0;
3056 }
3057 
3058 u32 skl_plane_ctl_rotation(unsigned int rotation)
3059 {
3060         switch (rotation) {
3061         case BIT(DRM_ROTATE_0):
3062                 break;
3063         /*
3064          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3065          * while i915 HW rotation is clockwise, thats why this swapping.
3066          */
3067         case BIT(DRM_ROTATE_90):
3068                 return PLANE_CTL_ROTATE_270;
3069         case BIT(DRM_ROTATE_180):
3070                 return PLANE_CTL_ROTATE_180;
3071         case BIT(DRM_ROTATE_270):
3072                 return PLANE_CTL_ROTATE_90;
3073         default:
3074                 MISSING_CASE(rotation);
3075         }
3076 
3077         return 0;
3078 }
3079 
3080 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3081                                          struct drm_framebuffer *fb,
3082                                          int x, int y)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         struct drm_plane *plane = crtc->primary;
3088         bool visible = to_intel_plane_state(plane->state)->visible;
3089         struct drm_i915_gem_object *obj;
3090         int pipe = intel_crtc->pipe;
3091         u32 plane_ctl, stride_div, stride;
3092         u32 tile_height, plane_offset, plane_size;
3093         unsigned int rotation;
3094         int x_offset, y_offset;
3095         u32 surf_addr;
3096         struct intel_crtc_state *crtc_state = intel_crtc->config;
3097         struct intel_plane_state *plane_state;
3098         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3099         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3100         int scaler_id = -1;
3101 
3102         plane_state = to_intel_plane_state(plane->state);
3103 
3104         if (!visible || !fb) {
3105                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3106                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3107                 POSTING_READ(PLANE_CTL(pipe, 0));
3108                 return;
3109         }
3110 
3111         plane_ctl = PLANE_CTL_ENABLE |
3112                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3113                     PLANE_CTL_PIPE_CSC_ENABLE;
3114 
3115         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3116         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3117         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3118 
3119         rotation = plane->state->rotation;
3120         plane_ctl |= skl_plane_ctl_rotation(rotation);
3121 
3122         obj = intel_fb_obj(fb);
3123         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3124                                                fb->pixel_format);
3125         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3126 
3127         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3128 
3129         scaler_id = plane_state->scaler_id;
3130         src_x = plane_state->src.x1 >> 16;
3131         src_y = plane_state->src.y1 >> 16;
3132         src_w = drm_rect_width(&plane_state->src) >> 16;
3133         src_h = drm_rect_height(&plane_state->src) >> 16;
3134         dst_x = plane_state->dst.x1;
3135         dst_y = plane_state->dst.y1;
3136         dst_w = drm_rect_width(&plane_state->dst);
3137         dst_h = drm_rect_height(&plane_state->dst);
3138 
3139         WARN_ON(x != src_x || y != src_y);
3140 
3141         if (intel_rotation_90_or_270(rotation)) {
3142                 /* stride = Surface height in tiles */
3143                 tile_height = intel_tile_height(dev, fb->pixel_format,
3144                                                 fb->modifier[0], 0);
3145                 stride = DIV_ROUND_UP(fb->height, tile_height);
3146                 x_offset = stride * tile_height - y - src_h;
3147                 y_offset = x;
3148                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3149         } else {
3150                 stride = fb->pitches[0] / stride_div;
3151                 x_offset = x;
3152                 y_offset = y;
3153                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3154         }
3155         plane_offset = y_offset << 16 | x_offset;
3156 
3157         intel_crtc->adjusted_x = x_offset;
3158         intel_crtc->adjusted_y = y_offset;
3159 
3160         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3161         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3162         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3163         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3164 
3165         if (scaler_id >= 0) {
3166                 uint32_t ps_ctrl = 0;
3167 
3168                 WARN_ON(!dst_w || !dst_h);
3169                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3170                         crtc_state->scaler_state.scalers[scaler_id].mode;
3171                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3172                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3173                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3174                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3175                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3176         } else {
3177                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3178         }
3179 
3180         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3181 
3182         POSTING_READ(PLANE_SURF(pipe, 0));
3183 }
3184 
3185 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3186 static int
3187 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3188                            int x, int y, enum mode_set_atomic state)
3189 {
3190         struct drm_device *dev = crtc->dev;
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192 
3193         if (dev_priv->fbc.deactivate)
3194                 dev_priv->fbc.deactivate(dev_priv);
3195 
3196         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3197 
3198         return 0;
3199 }
3200 
3201 static void intel_complete_page_flips(struct drm_device *dev)
3202 {
3203         struct drm_crtc *crtc;
3204 
3205         for_each_crtc(dev, crtc) {
3206                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207                 enum plane plane = intel_crtc->plane;
3208 
3209                 intel_prepare_page_flip(dev, plane);
3210                 intel_finish_page_flip_plane(dev, plane);
3211         }
3212 }
3213 
3214 static void intel_update_primary_planes(struct drm_device *dev)
3215 {
3216         struct drm_crtc *crtc;
3217 
3218         for_each_crtc(dev, crtc) {
3219                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3220                 struct intel_plane_state *plane_state;
3221 
3222                 drm_modeset_lock_crtc(crtc, &plane->base);
3223                 plane_state = to_intel_plane_state(plane->base.state);
3224 
3225                 if (crtc->state->active && plane_state->base.fb)
3226                         plane->commit_plane(&plane->base, plane_state);
3227 
3228                 drm_modeset_unlock_crtc(crtc);
3229         }
3230 }
3231 
3232 void intel_prepare_reset(struct drm_device *dev)
3233 {
3234         /* no reset support for gen2 */
3235         if (IS_GEN2(dev))
3236                 return;
3237 
3238         /* reset doesn't touch the display */
3239         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3240                 return;
3241 
3242         drm_modeset_lock_all(dev);
3243         /*
3244          * Disabling the crtcs gracefully seems nicer. Also the
3245          * g33 docs say we should at least disable all the planes.
3246          */
3247         intel_display_suspend(dev);
3248 }
3249 
3250 void intel_finish_reset(struct drm_device *dev)
3251 {
3252         struct drm_i915_private *dev_priv = to_i915(dev);
3253 
3254         /*
3255          * Flips in the rings will be nuked by the reset,
3256          * so complete all pending flips so that user space
3257          * will get its events and not get stuck.
3258          */
3259         intel_complete_page_flips(dev);
3260 
3261         /* no reset support for gen2 */
3262         if (IS_GEN2(dev))
3263                 return;
3264 
3265         /* reset doesn't touch the display */
3266         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3267                 /*
3268                  * Flips in the rings have been nuked by the reset,
3269                  * so update the base address of all primary
3270                  * planes to the the last fb to make sure we're
3271                  * showing the correct fb after a reset.
3272                  *
3273                  * FIXME: Atomic will make this obsolete since we won't schedule
3274                  * CS-based flips (which might get lost in gpu resets) any more.
3275                  */
3276                 intel_update_primary_planes(dev);
3277                 return;
3278         }
3279 
3280         /*
3281          * The display has been reset as well,
3282          * so need a full re-initialization.
3283          */
3284         intel_runtime_pm_disable_interrupts(dev_priv);
3285         intel_runtime_pm_enable_interrupts(dev_priv);
3286 
3287         intel_modeset_init_hw(dev);
3288 
3289         spin_lock_irq(&dev_priv->irq_lock);
3290         if (dev_priv->display.hpd_irq_setup)
3291                 dev_priv->display.hpd_irq_setup(dev);
3292         spin_unlock_irq(&dev_priv->irq_lock);
3293 
3294         intel_display_resume(dev);
3295 
3296         intel_hpd_init(dev_priv);
3297 
3298         drm_modeset_unlock_all(dev);
3299 }
3300 
3301 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         bool pending;
3307 
3308         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3309             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3310                 return false;
3311 
3312         spin_lock_irq(&dev->event_lock);
3313         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3314         spin_unlock_irq(&dev->event_lock);
3315 
3316         return pending;
3317 }
3318 
3319 static void intel_update_pipe_config(struct intel_crtc *crtc,
3320                                      struct intel_crtc_state *old_crtc_state)
3321 {
3322         struct drm_device *dev = crtc->base.dev;
3323         struct drm_i915_private *dev_priv = dev->dev_private;
3324         struct intel_crtc_state *pipe_config =
3325                 to_intel_crtc_state(crtc->base.state);
3326 
3327         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3328         crtc->base.mode = crtc->base.state->mode;
3329 
3330         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3331                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3332                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3333 
3334         if (HAS_DDI(dev))
3335                 intel_set_pipe_csc(&crtc->base);
3336 
3337         /*
3338          * Update pipe size and adjust fitter if needed: the reason for this is
3339          * that in compute_mode_changes we check the native mode (not the pfit
3340          * mode) to see if we can flip rather than do a full mode set. In the
3341          * fastboot case, we'll flip, but if we don't update the pipesrc and
3342          * pfit state, we'll end up with a big fb scanned out into the wrong
3343          * sized surface.
3344          */
3345 
3346         I915_WRITE(PIPESRC(crtc->pipe),
3347                    ((pipe_config->pipe_src_w - 1) << 16) |
3348                    (pipe_config->pipe_src_h - 1));
3349 
3350         /* on skylake this is done by detaching scalers */
3351         if (INTEL_INFO(dev)->gen >= 9) {
3352                 skl_detach_scalers(crtc);
3353 
3354                 if (pipe_config->pch_pfit.enabled)
3355                         skylake_pfit_enable(crtc);
3356         } else if (HAS_PCH_SPLIT(dev)) {
3357                 if (pipe_config->pch_pfit.enabled)
3358                         ironlake_pfit_enable(crtc);
3359                 else if (old_crtc_state->pch_pfit.enabled)
3360                         ironlake_pfit_disable(crtc, true);
3361         }
3362 }
3363 
3364 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365 {
3366         struct drm_device *dev = crtc->dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369         int pipe = intel_crtc->pipe;
3370         i915_reg_t reg;
3371         u32 temp;
3372 
3373         /* enable normal train */
3374         reg = FDI_TX_CTL(pipe);
3375         temp = I915_READ(reg);
3376         if (IS_IVYBRIDGE(dev)) {
3377                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3378                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3379         } else {
3380                 temp &= ~FDI_LINK_TRAIN_NONE;
3381                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3382         }
3383         I915_WRITE(reg, temp);
3384 
3385         reg = FDI_RX_CTL(pipe);
3386         temp = I915_READ(reg);
3387         if (HAS_PCH_CPT(dev)) {
3388                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3390         } else {
3391                 temp &= ~FDI_LINK_TRAIN_NONE;
3392                 temp |= FDI_LINK_TRAIN_NONE;
3393         }
3394         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3395 
3396         /* wait one idle pattern time */
3397         POSTING_READ(reg);
3398         udelay(1000);
3399 
3400         /* IVB wants error correction enabled */
3401         if (IS_IVYBRIDGE(dev))
3402                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3403                            FDI_FE_ERRC_ENABLE);
3404 }
3405 
3406 /* The FDI link training functions for ILK/Ibexpeak. */
3407 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3408 {
3409         struct drm_device *dev = crtc->dev;
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3412         int pipe = intel_crtc->pipe;
3413         i915_reg_t reg;
3414         u32 temp, tries;
3415 
3416         /* FDI needs bits from pipe first */
3417         assert_pipe_enabled(dev_priv, pipe);
3418 
3419         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3420            for train result */
3421         reg = FDI_RX_IMR(pipe);
3422         temp = I915_READ(reg);
3423         temp &= ~FDI_RX_SYMBOL_LOCK;
3424         temp &= ~FDI_RX_BIT_LOCK;
3425         I915_WRITE(reg, temp);
3426         I915_READ(reg);
3427         udelay(150);
3428 
3429         /* enable CPU FDI TX and PCH FDI RX */
3430         reg = FDI_TX_CTL(pipe);
3431         temp = I915_READ(reg);
3432         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3433         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3434         temp &= ~FDI_LINK_TRAIN_NONE;
3435         temp |= FDI_LINK_TRAIN_PATTERN_1;
3436         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3437 
3438         reg = FDI_RX_CTL(pipe);
3439         temp = I915_READ(reg);
3440         temp &= ~FDI_LINK_TRAIN_NONE;
3441         temp |= FDI_LINK_TRAIN_PATTERN_1;
3442         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3443 
3444         POSTING_READ(reg);
3445         udelay(150);
3446 
3447         /* Ironlake workaround, enable clock pointer after FDI enable*/
3448         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3449         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3450                    FDI_RX_PHASE_SYNC_POINTER_EN);
3451 
3452         reg = FDI_RX_IIR(pipe);
3453         for (tries = 0; tries < 5; tries++) {
3454                 temp = I915_READ(reg);
3455                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3456 
3457                 if ((temp & FDI_RX_BIT_LOCK)) {
3458                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3459                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3460                         break;
3461                 }
3462         }
3463         if (tries == 5)
3464                 DRM_ERROR("FDI train 1 fail!\n");
3465 
3466         /* Train 2 */
3467         reg = FDI_TX_CTL(pipe);
3468         temp = I915_READ(reg);
3469         temp &= ~FDI_LINK_TRAIN_NONE;
3470         temp |= FDI_LINK_TRAIN_PATTERN_2;
3471         I915_WRITE(reg, temp);
3472 
3473         reg = FDI_RX_CTL(pipe);
3474         temp = I915_READ(reg);
3475         temp &= ~FDI_LINK_TRAIN_NONE;
3476         temp |= FDI_LINK_TRAIN_PATTERN_2;
3477         I915_WRITE(reg, temp);
3478 
3479         POSTING_READ(reg);
3480         udelay(150);
3481 
3482         reg = FDI_RX_IIR(pipe);
3483         for (tries = 0; tries < 5; tries++) {
3484                 temp = I915_READ(reg);
3485                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3486 
3487                 if (temp & FDI_RX_SYMBOL_LOCK) {
3488                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3489                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3490                         break;
3491                 }
3492         }
3493         if (tries == 5)
3494                 DRM_ERROR("FDI train 2 fail!\n");
3495 
3496         DRM_DEBUG_KMS("FDI train done\n");
3497 
3498 }
3499 
3500 static const int snb_b_fdi_train_param[] = {
3501         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3502         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3503         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3504         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3505 };
3506 
3507 /* The FDI link training functions for SNB/Cougarpoint. */
3508 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3509 {
3510         struct drm_device *dev = crtc->dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513         int pipe = intel_crtc->pipe;
3514         i915_reg_t reg;
3515         u32 temp, i, retry;
3516 
3517         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3518            for train result */
3519         reg = FDI_RX_IMR(pipe);
3520         temp = I915_READ(reg);
3521         temp &= ~FDI_RX_SYMBOL_LOCK;
3522         temp &= ~FDI_RX_BIT_LOCK;
3523         I915_WRITE(reg, temp);
3524 
3525         POSTING_READ(reg);
3526         udelay(150);
3527 
3528         /* enable CPU FDI TX and PCH FDI RX */
3529         reg = FDI_TX_CTL(pipe);
3530         temp = I915_READ(reg);
3531         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3532         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3533         temp &= ~FDI_LINK_TRAIN_NONE;
3534         temp |= FDI_LINK_TRAIN_PATTERN_1;
3535         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3536         /* SNB-B */
3537         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3538         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3539 
3540         I915_WRITE(FDI_RX_MISC(pipe),
3541                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3542 
3543         reg = FDI_RX_CTL(pipe);
3544         temp = I915_READ(reg);
3545         if (HAS_PCH_CPT(dev)) {
3546                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3547                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3548         } else {
3549                 temp &= ~FDI_LINK_TRAIN_NONE;
3550                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3551         }
3552         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3553 
3554         POSTING_READ(reg);
3555         udelay(150);
3556 
3557         for (i = 0; i < 4; i++) {
3558                 reg = FDI_TX_CTL(pipe);
3559                 temp = I915_READ(reg);
3560                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561                 temp |= snb_b_fdi_train_param[i];
3562                 I915_WRITE(reg, temp);
3563 
3564                 POSTING_READ(reg);
3565                 udelay(500);
3566 
3567                 for (retry = 0; retry < 5; retry++) {
3568                         reg = FDI_RX_IIR(pipe);
3569                         temp = I915_READ(reg);
3570                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3571                         if (temp & FDI_RX_BIT_LOCK) {
3572                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3573                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3574                                 break;
3575                         }
3576                         udelay(50);
3577                 }
3578                 if (retry < 5)
3579                         break;
3580         }
3581         if (i == 4)
3582                 DRM_ERROR("FDI train 1 fail!\n");
3583 
3584         /* Train 2 */
3585         reg = FDI_TX_CTL(pipe);
3586         temp = I915_READ(reg);
3587         temp &= ~FDI_LINK_TRAIN_NONE;
3588         temp |= FDI_LINK_TRAIN_PATTERN_2;
3589         if (IS_GEN6(dev)) {
3590                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3591                 /* SNB-B */
3592                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3593         }
3594         I915_WRITE(reg, temp);
3595 
3596         reg = FDI_RX_CTL(pipe);
3597         temp = I915_READ(reg);
3598         if (HAS_PCH_CPT(dev)) {
3599                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3600                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3601         } else {
3602                 temp &= ~FDI_LINK_TRAIN_NONE;
3603                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3604         }
3605         I915_WRITE(reg, temp);
3606 
3607         POSTING_READ(reg);
3608         udelay(150);
3609 
3610         for (i = 0; i < 4; i++) {
3611                 reg = FDI_TX_CTL(pipe);
3612                 temp = I915_READ(reg);
3613                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3614                 temp |= snb_b_fdi_train_param[i];
3615                 I915_WRITE(reg, temp);
3616 
3617                 POSTING_READ(reg);
3618                 udelay(500);
3619 
3620                 for (retry = 0; retry < 5; retry++) {
3621                         reg = FDI_RX_IIR(pipe);
3622                         temp = I915_READ(reg);
3623                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3624                         if (temp & FDI_RX_SYMBOL_LOCK) {
3625                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3626                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3627                                 break;
3628                         }
3629                         udelay(50);
3630                 }
3631                 if (retry < 5)
3632                         break;
3633         }
3634         if (i == 4)
3635                 DRM_ERROR("FDI train 2 fail!\n");
3636 
3637         DRM_DEBUG_KMS("FDI train done.\n");
3638 }
3639 
3640 /* Manual link training for Ivy Bridge A0 parts */
3641 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3642 {
3643         struct drm_device *dev = crtc->dev;
3644         struct drm_i915_private *dev_priv = dev->dev_private;
3645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646         int pipe = intel_crtc->pipe;
3647         i915_reg_t reg;
3648         u32 temp, i, j;
3649 
3650         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3651            for train result */
3652         reg = FDI_RX_IMR(pipe);
3653         temp = I915_READ(reg);
3654         temp &= ~FDI_RX_SYMBOL_LOCK;
3655         temp &= ~FDI_RX_BIT_LOCK;
3656         I915_WRITE(reg, temp);
3657 
3658         POSTING_READ(reg);
3659         udelay(150);
3660 
3661         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3662                       I915_READ(FDI_RX_IIR(pipe)));
3663 
3664         /* Try each vswing and preemphasis setting twice before moving on */
3665         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3666                 /* disable first in case we need to retry */
3667                 reg = FDI_TX_CTL(pipe);
3668                 temp = I915_READ(reg);
3669                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3670                 temp &= ~FDI_TX_ENABLE;
3671                 I915_WRITE(reg, temp);
3672 
3673                 reg = FDI_RX_CTL(pipe);
3674                 temp = I915_READ(reg);
3675                 temp &= ~FDI_LINK_TRAIN_AUTO;
3676                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3677                 temp &= ~FDI_RX_ENABLE;
3678                 I915_WRITE(reg, temp);
3679 
3680                 /* enable CPU FDI TX and PCH FDI RX */
3681                 reg = FDI_TX_CTL(pipe);
3682                 temp = I915_READ(reg);
3683                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3684                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3685                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3686                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3687                 temp |= snb_b_fdi_train_param[j/2];
3688                 temp |= FDI_COMPOSITE_SYNC;
3689                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3690 
3691                 I915_WRITE(FDI_RX_MISC(pipe),
3692                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3693 
3694                 reg = FDI_RX_CTL(pipe);
3695                 temp = I915_READ(reg);
3696                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3697                 temp |= FDI_COMPOSITE_SYNC;
3698                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3699 
3700                 POSTING_READ(reg);
3701                 udelay(1); /* should be 0.5us */
3702 
3703                 for (i = 0; i < 4; i++) {
3704                         reg = FDI_RX_IIR(pipe);
3705                         temp = I915_READ(reg);
3706                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3707 
3708                         if (temp & FDI_RX_BIT_LOCK ||
3709                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3710                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3711                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3712                                               i);
3713                                 break;
3714                         }
3715                         udelay(1); /* should be 0.5us */
3716                 }
3717                 if (i == 4) {
3718                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3719                         continue;
3720                 }
3721 
3722                 /* Train 2 */
3723                 reg = FDI_TX_CTL(pipe);
3724                 temp = I915_READ(reg);
3725                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3726                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3727                 I915_WRITE(reg, temp);
3728 
3729                 reg = FDI_RX_CTL(pipe);
3730                 temp = I915_READ(reg);
3731                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3732                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3733                 I915_WRITE(reg, temp);
3734 
3735                 POSTING_READ(reg);
3736                 udelay(2); /* should be 1.5us */
3737 
3738                 for (i = 0; i < 4; i++) {
3739                         reg = FDI_RX_IIR(pipe);
3740                         temp = I915_READ(reg);
3741                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3742 
3743                         if (temp & FDI_RX_SYMBOL_LOCK ||
3744                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3745                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3746                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3747                                               i);
3748                                 goto train_done;
3749                         }
3750                         udelay(2); /* should be 1.5us */
3751                 }
3752                 if (i == 4)
3753                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3754         }
3755 
3756 train_done:
3757         DRM_DEBUG_KMS("FDI train done.\n");
3758 }
3759 
3760 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3761 {
3762         struct drm_device *dev = intel_crtc->base.dev;
3763         struct drm_i915_private *dev_priv = dev->dev_private;
3764         int pipe = intel_crtc->pipe;
3765         i915_reg_t reg;
3766         u32 temp;
3767 
3768         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3769         reg = FDI_RX_CTL(pipe);
3770         temp = I915_READ(reg);
3771         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3772         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3773         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3774         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3775 
3776         POSTING_READ(reg);
3777         udelay(200);
3778 
3779         /* Switch from Rawclk to PCDclk */
3780         temp = I915_READ(reg);
3781         I915_WRITE(reg, temp | FDI_PCDCLK);
3782 
3783         POSTING_READ(reg);
3784         udelay(200);
3785 
3786         /* Enable CPU FDI TX PLL, always on for Ironlake */
3787         reg = FDI_TX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3790                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3791 
3792                 POSTING_READ(reg);
3793                 udelay(100);
3794         }
3795 }
3796 
3797 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3798 {
3799         struct drm_device *dev = intel_crtc->base.dev;
3800         struct drm_i915_private *dev_priv = dev->dev_private;
3801         int pipe = intel_crtc->pipe;
3802         i915_reg_t reg;
3803         u32 temp;
3804 
3805         /* Switch from PCDclk to Rawclk */
3806         reg = FDI_RX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3809 
3810         /* Disable CPU FDI TX PLL */
3811         reg = FDI_TX_CTL(pipe);
3812         temp = I915_READ(reg);
3813         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3814 
3815         POSTING_READ(reg);
3816         udelay(100);
3817 
3818         reg = FDI_RX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3821 
3822         /* Wait for the clocks to turn off. */
3823         POSTING_READ(reg);
3824         udelay(100);
3825 }
3826 
3827 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3828 {
3829         struct drm_device *dev = crtc->dev;
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832         int pipe = intel_crtc->pipe;
3833         i915_reg_t reg;
3834         u32 temp;
3835 
3836         /* disable CPU FDI tx and PCH FDI rx */
3837         reg = FDI_TX_CTL(pipe);
3838         temp = I915_READ(reg);
3839         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3840         POSTING_READ(reg);
3841 
3842         reg = FDI_RX_CTL(pipe);
3843         temp = I915_READ(reg);
3844         temp &= ~(0x7 << 16);
3845         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3846         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3847 
3848         POSTING_READ(reg);
3849         udelay(100);
3850 
3851         /* Ironlake workaround, disable clock pointer after downing FDI */
3852         if (HAS_PCH_IBX(dev))
3853                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3854 
3855         /* still set train pattern 1 */
3856         reg = FDI_TX_CTL(pipe);
3857         temp = I915_READ(reg);
3858         temp &= ~FDI_LINK_TRAIN_NONE;
3859         temp |= FDI_LINK_TRAIN_PATTERN_1;
3860         I915_WRITE(reg, temp);
3861 
3862         reg = FDI_RX_CTL(pipe);
3863         temp = I915_READ(reg);
3864         if (HAS_PCH_CPT(dev)) {
3865                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3866                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3867         } else {
3868                 temp &= ~FDI_LINK_TRAIN_NONE;
3869                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3870         }
3871         /* BPC in FDI rx is consistent with that in PIPECONF */
3872         temp &= ~(0x07 << 16);
3873         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3874         I915_WRITE(reg, temp);
3875 
3876         POSTING_READ(reg);
3877         udelay(100);
3878 }
3879 
3880 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3881 {
3882         struct intel_crtc *crtc;
3883 
3884         /* Note that we don't need to be called with mode_config.lock here
3885          * as our list of CRTC objects is static for the lifetime of the
3886          * device and so cannot disappear as we iterate. Similarly, we can
3887          * happily treat the predicates as racy, atomic checks as userspace
3888          * cannot claim and pin a new fb without at least acquring the
3889          * struct_mutex and so serialising with us.
3890          */
3891         for_each_intel_crtc(dev, crtc) {
3892                 if (atomic_read(&crtc->unpin_work_count) == 0)
3893                         continue;
3894 
3895                 if (crtc->unpin_work)
3896                         intel_wait_for_vblank(dev, crtc->pipe);
3897 
3898                 return true;
3899         }
3900 
3901         return false;
3902 }
3903 
3904 static void page_flip_completed(struct intel_crtc *intel_crtc)
3905 {
3906         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3907         struct intel_unpin_work *work = intel_crtc->unpin_work;
3908 
3909         /* ensure that the unpin work is consistent wrt ->pending. */
3910         smp_rmb();
3911         intel_crtc->unpin_work = NULL;
3912 
3913         if (work->event)
3914                 drm_send_vblank_event(intel_crtc->base.dev,
3915                                       intel_crtc->pipe,
3916                                       work->event);
3917 
3918         drm_crtc_vblank_put(&intel_crtc->base);
3919 
3920         wake_up_all(&dev_priv->pending_flip_queue);
3921         queue_work(dev_priv->wq, &work->work);
3922 
3923         trace_i915_flip_complete(intel_crtc->plane,
3924                                  work->pending_flip_obj);
3925 }
3926 
3927 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3928 {
3929         struct drm_device *dev = crtc->dev;
3930         struct drm_i915_private *dev_priv = dev->dev_private;
3931         long ret;
3932 
3933         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3934 
3935         ret = wait_event_interruptible_timeout(
3936                                         dev_priv->pending_flip_queue,
3937                                         !intel_crtc_has_pending_flip(crtc),
3938                                         60*HZ);
3939 
3940         if (ret < 0)
3941                 return ret;
3942 
3943         if (ret == 0) {
3944                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3945 
3946                 spin_lock_irq(&dev->event_lock);
3947                 if (intel_crtc->unpin_work) {
3948                         WARN_ONCE(1, "Removing stuck page flip\n");
3949                         page_flip_completed(intel_crtc);
3950                 }
3951                 spin_unlock_irq(&dev->event_lock);
3952         }
3953 
3954         return 0;
3955 }
3956 
3957 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3958 {
3959         u32 temp;
3960 
3961         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962 
3963         mutex_lock(&dev_priv->sb_lock);
3964 
3965         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3966         temp |= SBI_SSCCTL_DISABLE;
3967         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3968 
3969         mutex_unlock(&dev_priv->sb_lock);
3970 }
3971 
3972 /* Program iCLKIP clock to the desired frequency */
3973 static void lpt_program_iclkip(struct drm_crtc *crtc)
3974 {
3975         struct drm_device *dev = crtc->dev;
3976         struct drm_i915_private *dev_priv = dev->dev_private;
3977         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3978         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3979         u32 temp;
3980 
3981         lpt_disable_iclkip(dev_priv);
3982 
3983         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3984         if (clock == 20000) {
3985                 auxdiv = 1;
3986                 divsel = 0x41;
3987                 phaseinc = 0x20;
3988         } else {
3989                 /* The iCLK virtual clock root frequency is in MHz,
3990                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3991                  * divisors, it is necessary to divide one by another, so we
3992                  * convert the virtual clock precision to KHz here for higher
3993                  * precision.
3994                  */
3995                 u32 iclk_virtual_root_freq = 172800 * 1000;
3996                 u32 iclk_pi_range = 64;
3997                 u32 desired_divisor, msb_divisor_value, pi_value;
3998 
3999                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
4000                 msb_divisor_value = desired_divisor / iclk_pi_range;
4001                 pi_value = desired_divisor % iclk_pi_range;
4002 
4003                 auxdiv = 0;
4004                 divsel = msb_divisor_value - 2;
4005                 phaseinc = pi_value;
4006         }
4007 
4008         /* This should not happen with any sane values */
4009         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4010                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4011         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4012                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4013 
4014         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4015                         clock,
4016                         auxdiv,
4017                         divsel,
4018                         phasedir,
4019                         phaseinc);
4020 
4021         mutex_lock(&dev_priv->sb_lock);
4022 
4023         /* Program SSCDIVINTPHASE6 */
4024         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4025         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4026         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4027         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4028         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4029         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4030         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4031         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4032 
4033         /* Program SSCAUXDIV */
4034         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4035         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4036         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4037         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4038 
4039         /* Enable modulator and associated divider */
4040         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4041         temp &= ~SBI_SSCCTL_DISABLE;
4042         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4043 
4044         mutex_unlock(&dev_priv->sb_lock);
4045 
4046         /* Wait for initialization time */
4047         udelay(24);
4048 
4049         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4050 }
4051 
4052 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4053                                                 enum pipe pch_transcoder)
4054 {
4055         struct drm_device *dev = crtc->base.dev;
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4058 
4059         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4060                    I915_READ(HTOTAL(cpu_transcoder)));
4061         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4062                    I915_READ(HBLANK(cpu_transcoder)));
4063         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4064                    I915_READ(HSYNC(cpu_transcoder)));
4065 
4066         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4067                    I915_READ(VTOTAL(cpu_transcoder)));
4068         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4069                    I915_READ(VBLANK(cpu_transcoder)));
4070         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4071                    I915_READ(VSYNC(cpu_transcoder)));
4072         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4073                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4074 }
4075 
4076 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4077 {
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         uint32_t temp;
4080 
4081         temp = I915_READ(SOUTH_CHICKEN1);
4082         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4083                 return;
4084 
4085         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4086         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4087 
4088         temp &= ~FDI_BC_BIFURCATION_SELECT;
4089         if (enable)
4090                 temp |= FDI_BC_BIFURCATION_SELECT;
4091 
4092         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4093         I915_WRITE(SOUTH_CHICKEN1, temp);
4094         POSTING_READ(SOUTH_CHICKEN1);
4095 }
4096 
4097 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4098 {
4099         struct drm_device *dev = intel_crtc->base.dev;
4100 
4101         switch (intel_crtc->pipe) {
4102         case PIPE_A:
4103                 break;
4104         case PIPE_B:
4105                 if (intel_crtc->config->fdi_lanes > 2)
4106                         cpt_set_fdi_bc_bifurcation(dev, false);
4107                 else
4108                         cpt_set_fdi_bc_bifurcation(dev, true);
4109 
4110                 break;
4111         case PIPE_C:
4112                 cpt_set_fdi_bc_bifurcation(dev, true);
4113 
4114                 break;
4115         default:
4116                 BUG();
4117         }
4118 }
4119 
4120 /* Return which DP Port should be selected for Transcoder DP control */
4121 static enum port
4122 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4123 {
4124         struct drm_device *dev = crtc->dev;
4125         struct intel_encoder *encoder;
4126 
4127         for_each_encoder_on_crtc(dev, crtc, encoder) {
4128                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4129                     encoder->type == INTEL_OUTPUT_EDP)
4130                         return enc_to_dig_port(&encoder->base)->port;
4131         }
4132 
4133         return -1;
4134 }
4135 
4136 /*
4137  * Enable PCH resources required for PCH ports:
4138  *   - PCH PLLs
4139  *   - FDI training & RX/TX
4140  *   - update transcoder timings
4141  *   - DP transcoding bits
4142  *   - transcoder
4143  */
4144 static void ironlake_pch_enable(struct drm_crtc *crtc)
4145 {
4146         struct drm_device *dev = crtc->dev;
4147         struct drm_i915_private *dev_priv = dev->dev_private;
4148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4149         int pipe = intel_crtc->pipe;
4150         u32 temp;
4151 
4152         assert_pch_transcoder_disabled(dev_priv, pipe);
4153 
4154         if (IS_IVYBRIDGE(dev))
4155                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4156 
4157         /* Write the TU size bits before fdi link training, so that error
4158          * detection works. */
4159         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4160                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4161 
4162         /*
4163          * Sometimes spurious CPU pipe underruns happen during FDI
4164          * training, at least with VGA+HDMI cloning. Suppress them.
4165          */
4166         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4167 
4168         /* For PCH output, training FDI link */
4169         dev_priv->display.fdi_link_train(crtc);
4170 
4171         /* We need to program the right clock selection before writing the pixel
4172          * mutliplier into the DPLL. */
4173         if (HAS_PCH_CPT(dev)) {
4174                 u32 sel;
4175 
4176                 temp = I915_READ(PCH_DPLL_SEL);
4177                 temp |= TRANS_DPLL_ENABLE(pipe);
4178                 sel = TRANS_DPLLB_SEL(pipe);
4179                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4180                         temp |= sel;
4181                 else
4182                         temp &= ~sel;
4183                 I915_WRITE(PCH_DPLL_SEL, temp);
4184         }
4185 
4186         /* XXX: pch pll's can be enabled any time before we enable the PCH
4187          * transcoder, and we actually should do this to not upset any PCH
4188          * transcoder that already use the clock when we share it.
4189          *
4190          * Note that enable_shared_dpll tries to do the right thing, but
4191          * get_shared_dpll unconditionally resets the pll - we need that to have
4192          * the right LVDS enable sequence. */
4193         intel_enable_shared_dpll(intel_crtc);
4194 
4195         /* set transcoder timing, panel must allow it */
4196         assert_panel_unlocked(dev_priv, pipe);
4197         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4198 
4199         intel_fdi_normal_train(crtc);
4200 
4201         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4202 
4203         /* For PCH DP, enable TRANS_DP_CTL */
4204         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4205                 const struct drm_display_mode *adjusted_mode =
4206                         &intel_crtc->config->base.adjusted_mode;
4207                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4208                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4209                 temp = I915_READ(reg);
4210                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4211                           TRANS_DP_SYNC_MASK |
4212                           TRANS_DP_BPC_MASK);
4213                 temp |= TRANS_DP_OUTPUT_ENABLE;
4214                 temp |= bpc << 9; /* same format but at 11:9 */
4215 
4216                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4217                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4218                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4219                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4220 
4221                 switch (intel_trans_dp_port_sel(crtc)) {
4222                 case PORT_B:
4223                         temp |= TRANS_DP_PORT_SEL_B;
4224                         break;
4225                 case PORT_C:
4226                         temp |= TRANS_DP_PORT_SEL_C;
4227                         break;
4228                 case PORT_D:
4229                         temp |= TRANS_DP_PORT_SEL_D;
4230                         break;
4231                 default:
4232                         BUG();
4233                 }
4234 
4235                 I915_WRITE(reg, temp);
4236         }
4237 
4238         ironlake_enable_pch_transcoder(dev_priv, pipe);
4239 }
4240 
4241 static void lpt_pch_enable(struct drm_crtc *crtc)
4242 {
4243         struct drm_device *dev = crtc->dev;
4244         struct drm_i915_private *dev_priv = dev->dev_private;
4245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4246         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4247 
4248         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4249 
4250         lpt_program_iclkip(crtc);
4251 
4252         /* Set transcoder timing. */
4253         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4254 
4255         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4256 }
4257 
4258 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4259                                                 struct intel_crtc_state *crtc_state)
4260 {
4261         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4262         struct intel_shared_dpll *pll;
4263         struct intel_shared_dpll_config *shared_dpll;
4264         enum intel_dpll_id i;
4265         int max = dev_priv->num_shared_dpll;
4266 
4267         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4268 
4269         if (HAS_PCH_IBX(dev_priv->dev)) {
4270                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4271                 i = (enum intel_dpll_id) crtc->pipe;
4272                 pll = &dev_priv->shared_dplls[i];
4273 
4274                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4275                               crtc->base.base.id, pll->name);
4276 
4277                 WARN_ON(shared_dpll[i].crtc_mask);
4278 
4279                 goto found;
4280         }
4281 
4282         if (IS_BROXTON(dev_priv->dev)) {
4283                 /* PLL is attached to port in bxt */
4284                 struct intel_encoder *encoder;
4285                 struct intel_digital_port *intel_dig_port;
4286 
4287                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4288                 if (WARN_ON(!encoder))
4289                         return NULL;
4290 
4291                 intel_dig_port = enc_to_dig_port(&encoder->base);
4292                 /* 1:1 mapping between ports and PLLs */
4293                 i = (enum intel_dpll_id)intel_dig_port->port;
4294                 pll = &dev_priv->shared_dplls[i];
4295                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4296                         crtc->base.base.id, pll->name);
4297                 WARN_ON(shared_dpll[i].crtc_mask);
4298 
4299                 goto found;
4300         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4301                 /* Do not consider SPLL */
4302                 max = 2;
4303 
4304         for (i = 0; i < max; i++) {
4305                 pll = &dev_priv->shared_dplls[i];
4306 
4307                 /* Only want to check enabled timings first */
4308                 if (shared_dpll[i].crtc_mask == 0)
4309                         continue;
4310 
4311                 if (memcmp(&crtc_state->dpll_hw_state,
4312                            &shared_dpll[i].hw_state,
4313                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4314                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4315                                       crtc->base.base.id, pll->name,
4316                                       shared_dpll[i].crtc_mask,
4317                                       pll->active);
4318                         goto found;
4319                 }
4320         }
4321 
4322         /* Ok no matching timings, maybe there's a free one? */
4323         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4324                 pll = &dev_priv->shared_dplls[i];
4325                 if (shared_dpll[i].crtc_mask == 0) {
4326                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4327                                       crtc->base.base.id, pll->name);
4328                         goto found;
4329                 }
4330         }
4331 
4332         return NULL;
4333 
4334 found:
4335         if (shared_dpll[i].crtc_mask == 0)
4336                 shared_dpll[i].hw_state =
4337                         crtc_state->dpll_hw_state;
4338 
4339         crtc_state->shared_dpll = i;
4340         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4341                          pipe_name(crtc->pipe));
4342 
4343         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4344 
4345         return pll;
4346 }
4347 
4348 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4349 {
4350         struct drm_i915_private *dev_priv = to_i915(state->dev);
4351         struct intel_shared_dpll_config *shared_dpll;
4352         struct intel_shared_dpll *pll;
4353         enum intel_dpll_id i;
4354 
4355         if (!to_intel_atomic_state(state)->dpll_set)
4356                 return;
4357 
4358         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4359         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4360                 pll = &dev_priv->shared_dplls[i];
4361                 pll->config = shared_dpll[i];
4362         }
4363 }
4364 
4365 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4366 {
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         i915_reg_t dslreg = PIPEDSL(pipe);
4369         u32 temp;
4370 
4371         temp = I915_READ(dslreg);
4372         udelay(500);
4373         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4374                 if (wait_for(I915_READ(dslreg) != temp, 5))
4375                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4376         }
4377 }
4378 
4379 static int
4380 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4381                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4382                   int src_w, int src_h, int dst_w, int dst_h)
4383 {
4384         struct intel_crtc_scaler_state *scaler_state =
4385                 &crtc_state->scaler_state;
4386         struct intel_crtc *intel_crtc =
4387                 to_intel_crtc(crtc_state->base.crtc);
4388         int need_scaling;
4389 
4390         need_scaling = intel_rotation_90_or_270(rotation) ?
4391                 (src_h != dst_w || src_w != dst_h):
4392                 (src_w != dst_w || src_h != dst_h);
4393 
4394         /*
4395          * if plane is being disabled or scaler is no more required or force detach
4396          *  - free scaler binded to this plane/crtc
4397          *  - in order to do this, update crtc->scaler_usage
4398          *
4399          * Here scaler state in crtc_state is set free so that
4400          * scaler can be assigned to other user. Actual register
4401          * update to free the scaler is done in plane/panel-fit programming.
4402          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4403          */
4404         if (force_detach || !need_scaling) {
4405                 if (*scaler_id >= 0) {
4406                         scaler_state->scaler_users &= ~(1 << scaler_user);
4407                         scaler_state->scalers[*scaler_id].in_use = 0;
4408 
4409                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4410                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4411                                 intel_crtc->pipe, scaler_user, *scaler_id,
4412                                 scaler_state->scaler_users);
4413                         *scaler_id = -1;
4414                 }
4415                 return 0;
4416         }
4417 
4418         /* range checks */
4419         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4420                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4421 
4422                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4423                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4424                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4425                         "size is out of scaler range\n",
4426                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4427                 return -EINVAL;
4428         }
4429 
4430         /* mark this plane as a scaler user in crtc_state */
4431         scaler_state->scaler_users |= (1 << scaler_user);
4432         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4433                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4434                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4435                 scaler_state->scaler_users);
4436 
4437         return 0;
4438 }
4439 
4440 /**
4441  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4442  *
4443  * @state: crtc's scaler state
4444  *
4445  * Return
4446  *     0 - scaler_usage updated successfully
4447  *    error - requested scaling cannot be supported or other error condition
4448  */
4449 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4450 {
4451         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4452         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4453 
4454         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4455                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4456 
4457         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4458                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4459                 state->pipe_src_w, state->pipe_src_h,
4460                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4461 }
4462 
4463 /**
4464  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4465  *
4466  * @state: crtc's scaler state
4467  * @plane_state: atomic plane state to update
4468  *
4469  * Return
4470  *     0 - scaler_usage updated successfully
4471  *    error - requested scaling cannot be supported or other error condition
4472  */
4473 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4474                                    struct intel_plane_state *plane_state)
4475 {
4476 
4477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4478         struct intel_plane *intel_plane =
4479                 to_intel_plane(plane_state->base.plane);
4480         struct drm_framebuffer *fb = plane_state->base.fb;
4481         int ret;
4482 
4483         bool force_detach = !fb || !plane_state->visible;
4484 
4485         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4486                       intel_plane->base.base.id, intel_crtc->pipe,
4487                       drm_plane_index(&intel_plane->base));
4488 
4489         ret = skl_update_scaler(crtc_state, force_detach,
4490                                 drm_plane_index(&intel_plane->base),
4491                                 &plane_state->scaler_id,
4492                                 plane_state->base.rotation,
4493                                 drm_rect_width(&plane_state->src) >> 16,
4494                                 drm_rect_height(&plane_state->src) >> 16,
4495                                 drm_rect_width(&plane_state->dst),
4496                                 drm_rect_height(&plane_state->dst));
4497 
4498         if (ret || plane_state->scaler_id < 0)
4499                 return ret;
4500 
4501         /* check colorkey */
4502         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4503                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4504                               intel_plane->base.base.id);
4505                 return -EINVAL;
4506         }
4507 
4508         /* Check src format */
4509         switch (fb->pixel_format) {
4510         case DRM_FORMAT_RGB565:
4511         case DRM_FORMAT_XBGR8888:
4512         case DRM_FORMAT_XRGB8888:
4513         case DRM_FORMAT_ABGR8888:
4514         case DRM_FORMAT_ARGB8888:
4515         case DRM_FORMAT_XRGB2101010:
4516         case DRM_FORMAT_XBGR2101010:
4517         case DRM_FORMAT_YUYV:
4518         case DRM_FORMAT_YVYU:
4519         case DRM_FORMAT_UYVY:
4520         case DRM_FORMAT_VYUY:
4521                 break;
4522         default:
4523                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4524                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4525                 return -EINVAL;
4526         }
4527 
4528         return 0;
4529 }
4530 
4531 static void skylake_scaler_disable(struct intel_crtc *crtc)
4532 {
4533         int i;
4534 
4535         for (i = 0; i < crtc->num_scalers; i++)
4536                 skl_detach_scaler(crtc, i);
4537 }
4538 
4539 static void skylake_pfit_enable(struct intel_crtc *crtc)
4540 {
4541         struct drm_device *dev = crtc->base.dev;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         int pipe = crtc->pipe;
4544         struct intel_crtc_scaler_state *scaler_state =
4545                 &crtc->config->scaler_state;
4546 
4547         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4548 
4549         if (crtc->config->pch_pfit.enabled) {
4550                 int id;
4551 
4552                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4553                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4554                         return;
4555                 }
4556 
4557                 id = scaler_state->scaler_id;
4558                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4559                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4560                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4561                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4562 
4563                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4564         }
4565 }
4566 
4567 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4568 {
4569         struct drm_device *dev = crtc->base.dev;
4570         struct drm_i915_private *dev_priv = dev->dev_private;
4571         int pipe = crtc->pipe;
4572 
4573         if (crtc->config->pch_pfit.enabled) {
4574                 /* Force use of hard-coded filter coefficients
4575                  * as some pre-programmed values are broken,
4576                  * e.g. x201.
4577                  */
4578                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4579                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4580                                                  PF_PIPE_SEL_IVB(pipe));
4581                 else
4582                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4583                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4584                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4585         }
4586 }
4587 
4588 void hsw_enable_ips(struct intel_crtc *crtc)
4589 {
4590         struct drm_device *dev = crtc->base.dev;
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592 
4593         if (!crtc->config->ips_enabled)
4594                 return;
4595 
4596         /* We can only enable IPS after we enable a plane and wait for a vblank */
4597         intel_wait_for_vblank(dev, crtc->pipe);
4598 
4599         assert_plane_enabled(dev_priv, crtc->plane);
4600         if (IS_BROADWELL(dev)) {
4601                 mutex_lock(&dev_priv->rps.hw_lock);
4602                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4603                 mutex_unlock(&dev_priv->rps.hw_lock);
4604                 /* Quoting Art Runyan: "its not safe to expect any particular
4605                  * value in IPS_CTL bit 31 after enabling IPS through the
4606                  * mailbox." Moreover, the mailbox may return a bogus state,
4607                  * so we need to just enable it and continue on.
4608                  */
4609         } else {
4610                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4611                 /* The bit only becomes 1 in the next vblank, so this wait here
4612                  * is essentially intel_wait_for_vblank. If we don't have this
4613                  * and don't wait for vblanks until the end of crtc_enable, then
4614                  * the HW state readout code will complain that the expected
4615                  * IPS_CTL value is not the one we read. */
4616                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4617                         DRM_ERROR("Timed out waiting for IPS enable\n");
4618         }
4619 }
4620 
4621 void hsw_disable_ips(struct intel_crtc *crtc)
4622 {
4623         struct drm_device *dev = crtc->base.dev;
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625 
4626         if (!crtc->config->ips_enabled)
4627                 return;
4628 
4629         assert_plane_enabled(dev_priv, crtc->plane);
4630         if (IS_BROADWELL(dev)) {
4631                 mutex_lock(&dev_priv->rps.hw_lock);
4632                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4633                 mutex_unlock(&dev_priv->rps.hw_lock);
4634                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4635                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4636                         DRM_ERROR("Timed out waiting for IPS disable\n");
4637         } else {
4638                 I915_WRITE(IPS_CTL, 0);
4639                 POSTING_READ(IPS_CTL);
4640         }
4641 
4642         /* We need to wait for a vblank before we can disable the plane. */
4643         intel_wait_for_vblank(dev, crtc->pipe);
4644 }
4645 
4646 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4647 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4648 {
4649         struct drm_device *dev = crtc->dev;
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4652         enum pipe pipe = intel_crtc->pipe;
4653         int i;
4654         bool reenable_ips = false;
4655 
4656         /* The clocks have to be on to load the palette. */
4657         if (!crtc->state->active)
4658                 return;
4659 
4660         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4661                 if (intel_crtc->config->has_dsi_encoder)
4662                         assert_dsi_pll_enabled(dev_priv);
4663                 else
4664                         assert_pll_enabled(dev_priv, pipe);
4665         }
4666 
4667         /* Workaround : Do not read or write the pipe palette/gamma data while
4668          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4669          */
4670         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4671             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4672              GAMMA_MODE_MODE_SPLIT)) {
4673                 hsw_disable_ips(intel_crtc);
4674                 reenable_ips = true;
4675         }
4676 
4677         for (i = 0; i < 256; i++) {
4678                 i915_reg_t palreg;
4679 
4680                 if (HAS_GMCH_DISPLAY(dev))
4681                         palreg = PALETTE(pipe, i);
4682                 else
4683                         palreg = LGC_PALETTE(pipe, i);
4684 
4685                 I915_WRITE(palreg,
4686                            (intel_crtc->lut_r[i] << 16) |
4687                            (intel_crtc->lut_g[i] << 8) |
4688                            intel_crtc->lut_b[i]);
4689         }
4690 
4691         if (reenable_ips)
4692                 hsw_enable_ips(intel_crtc);
4693 }
4694 
4695 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4696 {
4697         if (intel_crtc->overlay) {
4698                 struct drm_device *dev = intel_crtc->base.dev;
4699                 struct drm_i915_private *dev_priv = dev->dev_private;
4700 
4701                 mutex_lock(&dev->struct_mutex);
4702                 dev_priv->mm.interruptible = false;
4703                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4704                 dev_priv->mm.interruptible = true;
4705                 mutex_unlock(&dev->struct_mutex);
4706         }
4707 
4708         /* Let userspace switch the overlay on again. In most cases userspace
4709          * has to recompute where to put it anyway.
4710          */
4711 }
4712 
4713 /**
4714  * intel_post_enable_primary - Perform operations after enabling primary plane
4715  * @crtc: the CRTC whose primary plane was just enabled
4716  *
4717  * Performs potentially sleeping operations that must be done after the primary
4718  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4719  * called due to an explicit primary plane update, or due to an implicit
4720  * re-enable that is caused when a sprite plane is updated to no longer
4721  * completely hide the primary plane.
4722  */
4723 static void
4724 intel_post_enable_primary(struct drm_crtc *crtc)
4725 {
4726         struct drm_device *dev = crtc->dev;
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729         int pipe = intel_crtc->pipe;
4730 
4731         /*
4732          * FIXME IPS should be fine as long as one plane is
4733          * enabled, but in practice it seems to have problems
4734          * when going from primary only to sprite only and vice
4735          * versa.
4736          */
4737         hsw_enable_ips(intel_crtc);
4738 
4739         /*
4740          * Gen2 reports pipe underruns whenever all planes are disabled.
4741          * So don't enable underrun reporting before at least some planes
4742          * are enabled.
4743          * FIXME: Need to fix the logic to work when we turn off all planes
4744          * but leave the pipe running.
4745          */
4746         if (IS_GEN2(dev))
4747                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4748 
4749         /* Underruns don't always raise interrupts, so check manually. */
4750         intel_check_cpu_fifo_underruns(dev_priv);
4751         intel_check_pch_fifo_underruns(dev_priv);
4752 }
4753 
4754 /**
4755  * intel_pre_disable_primary - Perform operations before disabling primary plane
4756  * @crtc: the CRTC whose primary plane is to be disabled
4757  *
4758  * Performs potentially sleeping operations that must be done before the
4759  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4760  * be called due to an explicit primary plane update, or due to an implicit
4761  * disable that is caused when a sprite plane completely hides the primary
4762  * plane.
4763  */
4764 static void
4765 intel_pre_disable_primary(struct drm_crtc *crtc)
4766 {
4767         struct drm_device *dev = crtc->dev;
4768         struct drm_i915_private *dev_priv = dev->dev_private;
4769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770         int pipe = intel_crtc->pipe;
4771 
4772         /*
4773          * Gen2 reports pipe underruns whenever all planes are disabled.
4774          * So diasble underrun reporting before all the planes get disabled.
4775          * FIXME: Need to fix the logic to work when we turn off all planes
4776          * but leave the pipe running.
4777          */
4778         if (IS_GEN2(dev))
4779                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4780 
4781         /*
4782          * Vblank time updates from the shadow to live plane control register
4783          * are blocked if the memory self-refresh mode is active at that
4784          * moment. So to make sure the plane gets truly disabled, disable
4785          * first the self-refresh mode. The self-refresh enable bit in turn
4786          * will be checked/applied by the HW only at the next frame start
4787          * event which is after the vblank start event, so we need to have a
4788          * wait-for-vblank between disabling the plane and the pipe.
4789          */
4790         if (HAS_GMCH_DISPLAY(dev)) {
4791                 intel_set_memory_cxsr(dev_priv, false);
4792                 dev_priv->wm.vlv.cxsr = false;
4793                 intel_wait_for_vblank(dev, pipe);
4794         }
4795 
4796         /*
4797          * FIXME IPS should be fine as long as one plane is
4798          * enabled, but in practice it seems to have problems
4799          * when going from primary only to sprite only and vice
4800          * versa.
4801          */
4802         hsw_disable_ips(intel_crtc);
4803 }
4804 
4805 static void intel_post_plane_update(struct intel_crtc *crtc)
4806 {
4807         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4808         struct intel_crtc_state *pipe_config =
4809                 to_intel_crtc_state(crtc->base.state);
4810         struct drm_device *dev = crtc->base.dev;
4811 
4812         if (atomic->wait_vblank)
4813                 intel_wait_for_vblank(dev, crtc->pipe);
4814 
4815         intel_frontbuffer_flip(dev, atomic->fb_bits);
4816 
4817         crtc->wm.cxsr_allowed = true;
4818 
4819         if (pipe_config->wm_changed && pipe_config->base.active)
4820                 intel_update_watermarks(&crtc->base);
4821 
4822         if (atomic->update_fbc)
4823                 intel_fbc_update(crtc);
4824 
4825         if (atomic->post_enable_primary)
4826                 intel_post_enable_primary(&crtc->base);
4827 
4828         memset(atomic, 0, sizeof(*atomic));
4829 }
4830 
4831 static void intel_pre_plane_update(struct intel_crtc *crtc)
4832 {
4833         struct drm_device *dev = crtc->base.dev;
4834         struct drm_i915_private *dev_priv = dev->dev_private;
4835         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4836         struct intel_crtc_state *pipe_config =
4837                 to_intel_crtc_state(crtc->base.state);
4838 
4839         if (atomic->disable_fbc)
4840                 intel_fbc_deactivate(crtc);
4841 
4842         if (crtc->atomic.disable_ips)
4843                 hsw_disable_ips(crtc);
4844 
4845         if (atomic->pre_disable_primary)
4846                 intel_pre_disable_primary(&crtc->base);
4847 
4848         if (pipe_config->disable_cxsr) {
4849                 crtc->wm.cxsr_allowed = false;
4850                 intel_set_memory_cxsr(dev_priv, false);
4851         }
4852 
4853         if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4854                 intel_update_watermarks(&crtc->base);
4855 }
4856 
4857 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4858 {
4859         struct drm_device *dev = crtc->dev;
4860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4861         struct drm_plane *p;
4862         int pipe = intel_crtc->pipe;
4863 
4864         intel_crtc_dpms_overlay_disable(intel_crtc);
4865 
4866         drm_for_each_plane_mask(p, dev, plane_mask)
4867                 to_intel_plane(p)->disable_plane(p, crtc);
4868 
4869         /*
4870          * FIXME: Once we grow proper nuclear flip support out of this we need
4871          * to compute the mask of flip planes precisely. For the time being
4872          * consider this a flip to a NULL plane.
4873          */
4874         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4875 }
4876 
4877 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4878 {
4879         struct drm_device *dev = crtc->dev;
4880         struct drm_i915_private *dev_priv = dev->dev_private;
4881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882         struct intel_encoder *encoder;
4883         int pipe = intel_crtc->pipe;
4884 
4885         if (WARN_ON(intel_crtc->active))
4886                 return;
4887 
4888         if (intel_crtc->config->has_pch_encoder)
4889                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4890 
4891         if (intel_crtc->config->has_pch_encoder)
4892                 intel_prepare_shared_dpll(intel_crtc);
4893 
4894         if (intel_crtc->config->has_dp_encoder)
4895                 intel_dp_set_m_n(intel_crtc, M1_N1);
4896 
4897         intel_set_pipe_timings(intel_crtc);
4898 
4899         if (intel_crtc->config->has_pch_encoder) {
4900                 intel_cpu_transcoder_set_m_n(intel_crtc,
4901                                      &intel_crtc->config->fdi_m_n, NULL);
4902         }
4903 
4904         ironlake_set_pipeconf(crtc);
4905 
4906         intel_crtc->active = true;
4907 
4908         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4909 
4910         for_each_encoder_on_crtc(dev, crtc, encoder)
4911                 if (encoder->pre_enable)
4912                         encoder->pre_enable(encoder);
4913 
4914         if (intel_crtc->config->has_pch_encoder) {
4915                 /* Note: FDI PLL enabling _must_ be done before we enable the
4916                  * cpu pipes, hence this is separate from all the other fdi/pch
4917                  * enabling. */
4918                 ironlake_fdi_pll_enable(intel_crtc);
4919         } else {
4920                 assert_fdi_tx_disabled(dev_priv, pipe);
4921                 assert_fdi_rx_disabled(dev_priv, pipe);
4922         }
4923 
4924         ironlake_pfit_enable(intel_crtc);
4925 
4926         /*
4927          * On ILK+ LUT must be loaded before the pipe is running but with
4928          * clocks enabled
4929          */
4930         intel_crtc_load_lut(crtc);
4931 
4932         intel_update_watermarks(crtc);
4933         intel_enable_pipe(intel_crtc);
4934 
4935         if (intel_crtc->config->has_pch_encoder)
4936                 ironlake_pch_enable(crtc);
4937 
4938         assert_vblank_disabled(crtc);
4939         drm_crtc_vblank_on(crtc);
4940 
4941         for_each_encoder_on_crtc(dev, crtc, encoder)
4942                 encoder->enable(encoder);
4943 
4944         if (HAS_PCH_CPT(dev))
4945                 cpt_verify_modeset(dev, intel_crtc->pipe);
4946 
4947         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4948         if (intel_crtc->config->has_pch_encoder)
4949                 intel_wait_for_vblank(dev, pipe);
4950         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4951 
4952         intel_fbc_enable(intel_crtc);
4953 }
4954 
4955 /* IPS only exists on ULT machines and is tied to pipe A. */
4956 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4957 {
4958         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4959 }
4960 
4961 static void haswell_crtc_enable(struct drm_crtc *crtc)
4962 {
4963         struct drm_device *dev = crtc->dev;
4964         struct drm_i915_private *dev_priv = dev->dev_private;
4965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966         struct intel_encoder *encoder;
4967         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4968         struct intel_crtc_state *pipe_config =
4969                 to_intel_crtc_state(crtc->state);
4970 
4971         if (WARN_ON(intel_crtc->active))
4972                 return;
4973 
4974         if (intel_crtc->config->has_pch_encoder)
4975                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4976                                                       false);
4977 
4978         if (intel_crtc_to_shared_dpll(intel_crtc))
4979                 intel_enable_shared_dpll(intel_crtc);
4980 
4981         if (intel_crtc->config->has_dp_encoder)
4982                 intel_dp_set_m_n(intel_crtc, M1_N1);
4983 
4984         intel_set_pipe_timings(intel_crtc);
4985 
4986         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4987                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4988                            intel_crtc->config->pixel_multiplier - 1);
4989         }
4990 
4991         if (intel_crtc->config->has_pch_encoder) {
4992                 intel_cpu_transcoder_set_m_n(intel_crtc,
4993                                      &intel_crtc->config->fdi_m_n, NULL);
4994         }
4995 
4996         haswell_set_pipeconf(crtc);
4997 
4998         intel_set_pipe_csc(crtc);
4999 
5000         intel_crtc->active = true;
5001 
5002         if (intel_crtc->config->has_pch_encoder)
5003                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5004         else
5005                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5006 
5007         for_each_encoder_on_crtc(dev, crtc, encoder) {
5008                 if (encoder->pre_enable)
5009                         encoder->pre_enable(encoder);
5010         }
5011 
5012         if (intel_crtc->config->has_pch_encoder)
5013                 dev_priv->display.fdi_link_train(crtc);
5014 
5015         if (!intel_crtc->config->has_dsi_encoder)
5016                 intel_ddi_enable_pipe_clock(intel_crtc);
5017 
5018         if (INTEL_INFO(dev)->gen >= 9)
5019                 skylake_pfit_enable(intel_crtc);
5020         else
5021                 ironlake_pfit_enable(intel_crtc);
5022 
5023         /*
5024          * On ILK+ LUT must be loaded before the pipe is running but with
5025          * clocks enabled
5026          */
5027         intel_crtc_load_lut(crtc);
5028 
5029         intel_ddi_set_pipe_settings(crtc);
5030         if (!intel_crtc->config->has_dsi_encoder)
5031                 intel_ddi_enable_transcoder_func(crtc);
5032 
5033         intel_update_watermarks(crtc);
5034         intel_enable_pipe(intel_crtc);
5035 
5036         if (intel_crtc->config->has_pch_encoder)
5037                 lpt_pch_enable(crtc);
5038 
5039         if (intel_crtc->config->dp_encoder_is_mst)
5040                 intel_ddi_set_vc_payload_alloc(crtc, true);
5041 
5042         assert_vblank_disabled(crtc);
5043         drm_crtc_vblank_on(crtc);
5044 
5045         for_each_encoder_on_crtc(dev, crtc, encoder) {
5046                 encoder->enable(encoder);
5047                 intel_opregion_notify_encoder(encoder, true);
5048         }
5049 
5050         if (intel_crtc->config->has_pch_encoder) {
5051                 intel_wait_for_vblank(dev, pipe);
5052                 intel_wait_for_vblank(dev, pipe);
5053                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5054                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5055                                                       true);
5056         }
5057 
5058         /* If we change the relative order between pipe/planes enabling, we need
5059          * to change the workaround. */
5060         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5061         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5062                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5063                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5064         }
5065 
5066         intel_fbc_enable(intel_crtc);
5067 }
5068 
5069 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5070 {
5071         struct drm_device *dev = crtc->base.dev;
5072         struct drm_i915_private *dev_priv = dev->dev_private;
5073         int pipe = crtc->pipe;
5074 
5075         /* To avoid upsetting the power well on haswell only disable the pfit if
5076          * it's in use. The hw state code will make sure we get this right. */
5077         if (force || crtc->config->pch_pfit.enabled) {
5078                 I915_WRITE(PF_CTL(pipe), 0);
5079                 I915_WRITE(PF_WIN_POS(pipe), 0);
5080                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5081         }
5082 }
5083 
5084 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5085 {
5086         struct drm_device *dev = crtc->dev;
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089         struct intel_encoder *encoder;
5090         int pipe = intel_crtc->pipe;
5091 
5092         if (intel_crtc->config->has_pch_encoder)
5093                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5094 
5095         for_each_encoder_on_crtc(dev, crtc, encoder)
5096                 encoder->disable(encoder);
5097 
5098         drm_crtc_vblank_off(crtc);
5099         assert_vblank_disabled(crtc);
5100 
5101         /*
5102          * Sometimes spurious CPU pipe underruns happen when the
5103          * pipe is already disabled, but FDI RX/TX is still enabled.
5104          * Happens at least with VGA+HDMI cloning. Suppress them.
5105          */
5106         if (intel_crtc->config->has_pch_encoder)
5107                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5108 
5109         intel_disable_pipe(intel_crtc);
5110 
5111         ironlake_pfit_disable(intel_crtc, false);
5112 
5113         if (intel_crtc->config->has_pch_encoder) {
5114                 ironlake_fdi_disable(crtc);
5115                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5116         }
5117 
5118         for_each_encoder_on_crtc(dev, crtc, encoder)
5119                 if (encoder->post_disable)
5120                         encoder->post_disable(encoder);
5121 
5122         if (intel_crtc->config->has_pch_encoder) {
5123                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5124 
5125                 if (HAS_PCH_CPT(dev)) {
5126                         i915_reg_t reg;
5127                         u32 temp;
5128 
5129                         /* disable TRANS_DP_CTL */
5130                         reg = TRANS_DP_CTL(pipe);
5131                         temp = I915_READ(reg);
5132                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5133                                   TRANS_DP_PORT_SEL_MASK);
5134                         temp |= TRANS_DP_PORT_SEL_NONE;
5135                         I915_WRITE(reg, temp);
5136 
5137                         /* disable DPLL_SEL */
5138                         temp = I915_READ(PCH_DPLL_SEL);
5139                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5140                         I915_WRITE(PCH_DPLL_SEL, temp);
5141                 }
5142 
5143                 ironlake_fdi_pll_disable(intel_crtc);
5144         }
5145 
5146         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5147 
5148         intel_fbc_disable_crtc(intel_crtc);
5149 }
5150 
5151 static void haswell_crtc_disable(struct drm_crtc *crtc)
5152 {
5153         struct drm_device *dev = crtc->dev;
5154         struct drm_i915_private *dev_priv = dev->dev_private;
5155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156         struct intel_encoder *encoder;
5157         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5158 
5159         if (intel_crtc->config->has_pch_encoder)
5160                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5161                                                       false);
5162 
5163         for_each_encoder_on_crtc(dev, crtc, encoder) {
5164                 intel_opregion_notify_encoder(encoder, false);
5165                 encoder->disable(encoder);
5166         }
5167 
5168         drm_crtc_vblank_off(crtc);
5169         assert_vblank_disabled(crtc);
5170 
5171         intel_disable_pipe(intel_crtc);
5172 
5173         if (intel_crtc->config->dp_encoder_is_mst)
5174                 intel_ddi_set_vc_payload_alloc(crtc, false);
5175 
5176         if (!intel_crtc->config->has_dsi_encoder)
5177                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5178 
5179         if (INTEL_INFO(dev)->gen >= 9)
5180                 skylake_scaler_disable(intel_crtc);
5181         else
5182                 ironlake_pfit_disable(intel_crtc, false);
5183 
5184         if (!intel_crtc->config->has_dsi_encoder)
5185                 intel_ddi_disable_pipe_clock(intel_crtc);
5186 
5187         for_each_encoder_on_crtc(dev, crtc, encoder)
5188                 if (encoder->post_disable)
5189                         encoder->post_disable(encoder);
5190 
5191         if (intel_crtc->config->has_pch_encoder) {
5192                 lpt_disable_pch_transcoder(dev_priv);
5193                 lpt_disable_iclkip(dev_priv);
5194                 intel_ddi_fdi_disable(crtc);
5195 
5196                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5197                                                       true);
5198         }
5199 
5200         intel_fbc_disable_crtc(intel_crtc);
5201 }
5202 
5203 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5204 {
5205         struct drm_device *dev = crtc->base.dev;
5206         struct drm_i915_private *dev_priv = dev->dev_private;
5207         struct intel_crtc_state *pipe_config = crtc->config;
5208 
5209         if (!pipe_config->gmch_pfit.control)
5210                 return;
5211 
5212         /*
5213          * The panel fitter should only be adjusted whilst the pipe is disabled,
5214          * according to register description and PRM.
5215          */
5216         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5217         assert_pipe_disabled(dev_priv, crtc->pipe);
5218 
5219         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5220         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5221 
5222         /* Border color in case we don't scale up to the full screen. Black by
5223          * default, change to something else for debugging. */
5224         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5225 }
5226 
5227 static enum intel_display_power_domain port_to_power_domain(enum port port)
5228 {
5229         switch (port) {
5230         case PORT_A:
5231                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5232         case PORT_B:
5233                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5234         case PORT_C:
5235                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5236         case PORT_D:
5237                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5238         case PORT_E:
5239                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5240         default:
5241                 MISSING_CASE(port);
5242                 return POWER_DOMAIN_PORT_OTHER;
5243         }
5244 }
5245 
5246 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5247 {
5248         switch (port) {
5249         case PORT_A:
5250                 return POWER_DOMAIN_AUX_A;
5251         case PORT_B:
5252                 return POWER_DOMAIN_AUX_B;
5253         case PORT_C:
5254                 return POWER_DOMAIN_AUX_C;
5255         case PORT_D:
5256                 return POWER_DOMAIN_AUX_D;
5257         case PORT_E:
5258                 /* FIXME: Check VBT for actual wiring of PORT E */
5259                 return POWER_DOMAIN_AUX_D;
5260         default:
5261                 MISSING_CASE(port);
5262                 return POWER_DOMAIN_AUX_A;
5263         }
5264 }
5265 
5266 enum intel_display_power_domain
5267 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5268 {
5269         struct drm_device *dev = intel_encoder->base.dev;
5270         struct intel_digital_port *intel_dig_port;
5271 
5272         switch (intel_encoder->type) {
5273         case INTEL_OUTPUT_UNKNOWN:
5274                 /* Only DDI platforms should ever use this output type */
5275                 WARN_ON_ONCE(!HAS_DDI(dev));
5276         case INTEL_OUTPUT_DISPLAYPORT:
5277         case INTEL_OUTPUT_HDMI:
5278         case INTEL_OUTPUT_EDP:
5279                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5280                 return port_to_power_domain(intel_dig_port->port);
5281         case INTEL_OUTPUT_DP_MST:
5282                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5283                 return port_to_power_domain(intel_dig_port->port);
5284         case INTEL_OUTPUT_ANALOG:
5285                 return POWER_DOMAIN_PORT_CRT;
5286         case INTEL_OUTPUT_DSI:
5287                 return POWER_DOMAIN_PORT_DSI;
5288         default:
5289                 return POWER_DOMAIN_PORT_OTHER;
5290         }
5291 }
5292 
5293 enum intel_display_power_domain
5294 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5295 {
5296         struct drm_device *dev = intel_encoder->base.dev;
5297         struct intel_digital_port *intel_dig_port;
5298 
5299         switch (intel_encoder->type) {
5300         case INTEL_OUTPUT_UNKNOWN:
5301         case INTEL_OUTPUT_HDMI:
5302                 /*
5303                  * Only DDI platforms should ever use these output types.
5304                  * We can get here after the HDMI detect code has already set
5305                  * the type of the shared encoder. Since we can't be sure
5306                  * what's the status of the given connectors, play safe and
5307                  * run the DP detection too.
5308                  */
5309                 WARN_ON_ONCE(!HAS_DDI(dev));
5310         case INTEL_OUTPUT_DISPLAYPORT:
5311         case INTEL_OUTPUT_EDP:
5312                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5313                 return port_to_aux_power_domain(intel_dig_port->port);
5314         case INTEL_OUTPUT_DP_MST:
5315                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5316                 return port_to_aux_power_domain(intel_dig_port->port);
5317         default:
5318                 MISSING_CASE(intel_encoder->type);
5319                 return POWER_DOMAIN_AUX_A;
5320         }
5321 }
5322 
5323 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5324 {
5325         struct drm_device *dev = crtc->dev;
5326         struct intel_encoder *intel_encoder;
5327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328         enum pipe pipe = intel_crtc->pipe;
5329         unsigned long mask;
5330         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5331 
5332         if (!crtc->state->active)
5333                 return 0;
5334 
5335         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5336         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5337         if (intel_crtc->config->pch_pfit.enabled ||
5338             intel_crtc->config->pch_pfit.force_thru)
5339                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5340 
5341         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5342                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5343 
5344         return mask;
5345 }
5346 
5347 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5348 {
5349         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5351         enum intel_display_power_domain domain;
5352         unsigned long domains, new_domains, old_domains;
5353 
5354         old_domains = intel_crtc->enabled_power_domains;
5355         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5356 
5357         domains = new_domains & ~old_domains;
5358 
5359         for_each_power_domain(domain, domains)
5360                 intel_display_power_get(dev_priv, domain);
5361 
5362         return old_domains & ~new_domains;
5363 }
5364 
5365 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5366                                       unsigned long domains)
5367 {
5368         enum intel_display_power_domain domain;
5369 
5370         for_each_power_domain(domain, domains)
5371                 intel_display_power_put(dev_priv, domain);
5372 }
5373 
5374 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5375 {
5376         struct drm_device *dev = state->dev;
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         unsigned long put_domains[I915_MAX_PIPES] = {};
5379         struct drm_crtc_state *crtc_state;
5380         struct drm_crtc *crtc;
5381         int i;
5382 
5383         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5384                 if (needs_modeset(crtc->state))
5385                         put_domains[to_intel_crtc(crtc)->pipe] =
5386                                 modeset_get_crtc_power_domains(crtc);
5387         }
5388 
5389         if (dev_priv->display.modeset_commit_cdclk) {
5390                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5391 
5392                 if (cdclk != dev_priv->cdclk_freq &&
5393                     !WARN_ON(!state->allow_modeset))
5394                         dev_priv->display.modeset_commit_cdclk(state);
5395         }
5396 
5397         for (i = 0; i < I915_MAX_PIPES; i++)
5398                 if (put_domains[i])
5399                         modeset_put_power_domains(dev_priv, put_domains[i]);
5400 }
5401 
5402 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5403 {
5404         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5405 
5406         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5407             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5408                 return max_cdclk_freq;
5409         else if (IS_CHERRYVIEW(dev_priv))
5410                 return max_cdclk_freq*95/100;
5411         else if (INTEL_INFO(dev_priv)->gen < 4)
5412                 return 2*max_cdclk_freq*90/100;
5413         else
5414                 return max_cdclk_freq*90/100;
5415 }
5416 
5417 static void intel_update_max_cdclk(struct drm_device *dev)
5418 {
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420 
5421         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5422                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5423 
5424                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5425                         dev_priv->max_cdclk_freq = 675000;
5426                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5427                         dev_priv->max_cdclk_freq = 540000;
5428                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5429                         dev_priv->max_cdclk_freq = 450000;
5430                 else
5431                         dev_priv->max_cdclk_freq = 337500;
5432         } else if (IS_BROADWELL(dev))  {
5433                 /*
5434                  * FIXME with extra cooling we can allow
5435                  * 540 MHz for ULX and 675 Mhz for ULT.
5436                  * How can we know if extra cooling is
5437                  * available? PCI ID, VTB, something else?
5438                  */
5439                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5440                         dev_priv->max_cdclk_freq = 450000;
5441                 else if (IS_BDW_ULX(dev))
5442                         dev_priv->max_cdclk_freq = 450000;
5443                 else if (IS_BDW_ULT(dev))
5444                         dev_priv->max_cdclk_freq = 540000;
5445                 else
5446                         dev_priv->max_cdclk_freq = 675000;
5447         } else if (IS_CHERRYVIEW(dev)) {
5448                 dev_priv->max_cdclk_freq = 320000;
5449         } else if (IS_VALLEYVIEW(dev)) {
5450                 dev_priv->max_cdclk_freq = 400000;
5451         } else {
5452                 /* otherwise assume cdclk is fixed */
5453                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5454         }
5455 
5456         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5457 
5458         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5459                          dev_priv->max_cdclk_freq);
5460 
5461         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5462                          dev_priv->max_dotclk_freq);
5463 }
5464 
5465 static void intel_update_cdclk(struct drm_device *dev)
5466 {
5467         struct drm_i915_private *dev_priv = dev->dev_private;
5468 
5469         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5470         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5471                          dev_priv->cdclk_freq);
5472 
5473         /*
5474          * Program the gmbus_freq based on the cdclk frequency.
5475          * BSpec erroneously claims we should aim for 4MHz, but
5476          * in fact 1MHz is the correct frequency.
5477          */
5478         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5479                 /*
5480                  * Program the gmbus_freq based on the cdclk frequency.
5481                  * BSpec erroneously claims we should aim for 4MHz, but
5482                  * in fact 1MHz is the correct frequency.
5483                  */
5484                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5485         }
5486 
5487         if (dev_priv->max_cdclk_freq == 0)
5488                 intel_update_max_cdclk(dev);
5489 }
5490 
5491 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5492 {
5493         struct drm_i915_private *dev_priv = dev->dev_private;
5494         uint32_t divider;
5495         uint32_t ratio;
5496         uint32_t current_freq;
5497         int ret;
5498 
5499         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5500         switch (frequency) {
5501         case 144000:
5502                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5503                 ratio = BXT_DE_PLL_RATIO(60);
5504                 break;
5505         case 288000:
5506                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5507                 ratio = BXT_DE_PLL_RATIO(60);
5508                 break;
5509         case 384000:
5510                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5511                 ratio = BXT_DE_PLL_RATIO(60);
5512                 break;
5513         case 576000:
5514                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5515                 ratio = BXT_DE_PLL_RATIO(60);
5516                 break;
5517         case 624000:
5518                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5519                 ratio = BXT_DE_PLL_RATIO(65);
5520                 break;
5521         case 19200:
5522                 /*
5523                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5524                  * to suppress GCC warning.
5525                  */
5526                 ratio = 0;
5527                 divider = 0;
5528                 break;
5529         default:
5530                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5531 
5532                 return;
5533         }
5534 
5535         mutex_lock(&dev_priv->rps.hw_lock);
5536         /* Inform power controller of upcoming frequency change */
5537         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5538                                       0x80000000);
5539         mutex_unlock(&dev_priv->rps.hw_lock);
5540 
5541         if (ret) {
5542                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5543                           ret, frequency);
5544                 return;
5545         }
5546 
5547         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5548         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5549         current_freq = current_freq * 500 + 1000;
5550 
5551         /*
5552          * DE PLL has to be disabled when
5553          * - setting to 19.2MHz (bypass, PLL isn't used)
5554          * - before setting to 624MHz (PLL needs toggling)
5555          * - before setting to any frequency from 624MHz (PLL needs toggling)
5556          */
5557         if (frequency == 19200 || frequency == 624000 ||
5558             current_freq == 624000) {
5559                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5560                 /* Timeout 200us */
5561                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5562                              1))
5563                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5564         }
5565 
5566         if (frequency != 19200) {
5567                 uint32_t val;
5568 
5569                 val = I915_READ(BXT_DE_PLL_CTL);
5570                 val &= ~BXT_DE_PLL_RATIO_MASK;
5571                 val |= ratio;
5572                 I915_WRITE(BXT_DE_PLL_CTL, val);
5573 
5574                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5575                 /* Timeout 200us */
5576                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5577                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5578 
5579                 val = I915_READ(CDCLK_CTL);
5580                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5581                 val |= divider;
5582                 /*
5583                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5584                  * enable otherwise.
5585                  */
5586                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5587                 if (frequency >= 500000)
5588                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5589 
5590                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5591                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5592                 val |= (frequency - 1000) / 500;
5593                 I915_WRITE(CDCLK_CTL, val);
5594         }
5595 
5596         mutex_lock(&dev_priv->rps.hw_lock);
5597         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5598                                       DIV_ROUND_UP(frequency, 25000));
5599         mutex_unlock(&dev_priv->rps.hw_lock);
5600 
5601         if (ret) {
5602                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5603                           ret, frequency);
5604                 return;
5605         }
5606 
5607         intel_update_cdclk(dev);
5608 }
5609 
5610 void broxton_init_cdclk(struct drm_device *dev)
5611 {
5612         struct drm_i915_private *dev_priv = dev->dev_private;
5613         uint32_t val;
5614 
5615         /*
5616          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5617          * or else the reset will hang because there is no PCH to respond.
5618          * Move the handshake programming to initialization sequence.
5619          * Previously was left up to BIOS.
5620          */
5621         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5622         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5623         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5624 
5625         /* Enable PG1 for cdclk */
5626         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5627 
5628         /* check if cd clock is enabled */
5629         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5630                 DRM_DEBUG_KMS("Display already initialized\n");
5631                 return;
5632         }
5633 
5634         /*
5635          * FIXME:
5636          * - The initial CDCLK needs to be read from VBT.
5637          *   Need to make this change after VBT has changes for BXT.
5638          * - check if setting the max (or any) cdclk freq is really necessary
5639          *   here, it belongs to modeset time
5640          */
5641         broxton_set_cdclk(dev, 624000);
5642 
5643         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5644         POSTING_READ(DBUF_CTL);
5645 
5646         udelay(10);
5647 
5648         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5649                 DRM_ERROR("DBuf power enable timeout!\n");
5650 }
5651 
5652 void broxton_uninit_cdclk(struct drm_device *dev)
5653 {
5654         struct drm_i915_private *dev_priv = dev->dev_private;
5655 
5656         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5657         POSTING_READ(DBUF_CTL);
5658 
5659         udelay(10);
5660 
5661         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5662                 DRM_ERROR("DBuf power disable timeout!\n");
5663 
5664         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5665         broxton_set_cdclk(dev, 19200);
5666 
5667         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5668 }
5669 
5670 static const struct skl_cdclk_entry {
5671         unsigned int freq;
5672         unsigned int vco;
5673 } skl_cdclk_frequencies[] = {
5674         { .freq = 308570, .vco = 8640 },
5675         { .freq = 337500, .vco = 8100 },
5676         { .freq = 432000, .vco = 8640 },
5677         { .freq = 450000, .vco = 8100 },
5678         { .freq = 540000, .vco = 8100 },
5679         { .freq = 617140, .vco = 8640 },
5680         { .freq = 675000, .vco = 8100 },
5681 };
5682 
5683 static unsigned int skl_cdclk_decimal(unsigned int freq)
5684 {
5685         return (freq - 1000) / 500;
5686 }
5687 
5688 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5689 {
5690         unsigned int i;
5691 
5692         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5693                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5694 
5695                 if (e->freq == freq)
5696                         return e->vco;
5697         }
5698 
5699         return 8100;
5700 }
5701 
5702 static void
5703 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5704 {
5705         unsigned int min_freq;
5706         u32 val;
5707 
5708         /* select the minimum CDCLK before enabling DPLL 0 */
5709         val = I915_READ(CDCLK_CTL);
5710         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5711         val |= CDCLK_FREQ_337_308;
5712 
5713         if (required_vco == 8640)
5714                 min_freq = 308570;
5715         else
5716                 min_freq = 337500;
5717 
5718         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5719 
5720         I915_WRITE(CDCLK_CTL, val);
5721         POSTING_READ(CDCLK_CTL);
5722 
5723         /*
5724          * We always enable DPLL0 with the lowest link rate possible, but still
5725          * taking into account the VCO required to operate the eDP panel at the
5726          * desired frequency. The usual DP link rates operate with a VCO of
5727          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5728          * The modeset code is responsible for the selection of the exact link
5729          * rate later on, with the constraint of choosing a frequency that
5730          * works with required_vco.
5731          */
5732         val = I915_READ(DPLL_CTRL1);
5733 
5734         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5735                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5736         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5737         if (required_vco == 8640)
5738                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5739                                             SKL_DPLL0);
5740         else
5741                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5742                                             SKL_DPLL0);
5743 
5744         I915_WRITE(DPLL_CTRL1, val);
5745         POSTING_READ(DPLL_CTRL1);
5746 
5747         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5748 
5749         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5750                 DRM_ERROR("DPLL0 not locked\n");
5751 }
5752 
5753 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5754 {
5755         int ret;
5756         u32 val;
5757 
5758         /* inform PCU we want to change CDCLK */
5759         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5760         mutex_lock(&dev_priv->rps.hw_lock);
5761         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5762         mutex_unlock(&dev_priv->rps.hw_lock);
5763 
5764         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5765 }
5766 
5767 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5768 {
5769         unsigned int i;
5770 
5771         for (i = 0; i < 15; i++) {
5772                 if (skl_cdclk_pcu_ready(dev_priv))
5773                         return true;
5774                 udelay(10);
5775         }
5776 
5777         return false;
5778 }
5779 
5780 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5781 {
5782         struct drm_device *dev = dev_priv->dev;
5783         u32 freq_select, pcu_ack;
5784 
5785         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5786 
5787         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5788                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5789                 return;
5790         }
5791 
5792         /* set CDCLK_CTL */
5793         switch(freq) {
5794         case 450000:
5795         case 432000:
5796                 freq_select = CDCLK_FREQ_450_432;
5797                 pcu_ack = 1;
5798                 break;
5799         case 540000:
5800                 freq_select = CDCLK_FREQ_540;
5801                 pcu_ack = 2;
5802                 break;
5803         case 308570:
5804         case 337500:
5805         default:
5806                 freq_select = CDCLK_FREQ_337_308;
5807                 pcu_ack = 0;
5808                 break;
5809         case 617140:
5810         case 675000:
5811                 freq_select = CDCLK_FREQ_675_617;
5812                 pcu_ack = 3;
5813                 break;
5814         }
5815 
5816         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5817         POSTING_READ(CDCLK_CTL);
5818 
5819         /* inform PCU of the change */
5820         mutex_lock(&dev_priv->rps.hw_lock);
5821         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5822         mutex_unlock(&dev_priv->rps.hw_lock);
5823 
5824         intel_update_cdclk(dev);
5825 }
5826 
5827 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5828 {
5829         /* disable DBUF power */
5830         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5831         POSTING_READ(DBUF_CTL);
5832 
5833         udelay(10);
5834 
5835         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5836                 DRM_ERROR("DBuf power disable timeout\n");
5837 
5838         /* disable DPLL0 */
5839         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5840         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5841                 DRM_ERROR("Couldn't disable DPLL0\n");
5842 }
5843 
5844 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5845 {
5846         unsigned int required_vco;
5847 
5848         /* DPLL0 not enabled (happens on early BIOS versions) */
5849         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5850                 /* enable DPLL0 */
5851                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5852                 skl_dpll0_enable(dev_priv, required_vco);
5853         }
5854 
5855         /* set CDCLK to the frequency the BIOS chose */
5856         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5857 
5858         /* enable DBUF power */
5859         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5860         POSTING_READ(DBUF_CTL);
5861 
5862         udelay(10);
5863 
5864         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5865                 DRM_ERROR("DBuf power enable timeout\n");
5866 }
5867 
5868 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5869 {
5870         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5871         uint32_t cdctl = I915_READ(CDCLK_CTL);
5872         int freq = dev_priv->skl_boot_cdclk;
5873 
5874         /*
5875          * check if the pre-os intialized the display
5876          * There is SWF18 scratchpad register defined which is set by the
5877          * pre-os which can be used by the OS drivers to check the status
5878          */
5879         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5880                 goto sanitize;
5881 
5882         /* Is PLL enabled and locked ? */
5883         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5884                 goto sanitize;
5885 
5886         /* DPLL okay; verify the cdclock
5887          *
5888          * Noticed in some instances that the freq selection is correct but
5889          * decimal part is programmed wrong from BIOS where pre-os does not
5890          * enable display. Verify the same as well.
5891          */
5892         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5893                 /* All well; nothing to sanitize */
5894                 return false;
5895 sanitize:
5896         /*
5897          * As of now initialize with max cdclk till
5898          * we get dynamic cdclk support
5899          * */
5900         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5901         skl_init_cdclk(dev_priv);
5902 
5903         /* we did have to sanitize */
5904         return true;
5905 }
5906 
5907 /* Adjust CDclk dividers to allow high res or save power if possible */
5908 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5909 {
5910         struct drm_i915_private *dev_priv = dev->dev_private;
5911         u32 val, cmd;
5912 
5913         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5914                                         != dev_priv->cdclk_freq);
5915 
5916         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5917                 cmd = 2;
5918         else if (cdclk == 266667)
5919                 cmd = 1;
5920         else
5921                 cmd = 0;
5922 
5923         mutex_lock(&dev_priv->rps.hw_lock);
5924         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5925         val &= ~DSPFREQGUAR_MASK;
5926         val |= (cmd << DSPFREQGUAR_SHIFT);
5927         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5928         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5929                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5930                      50)) {
5931                 DRM_ERROR("timed out waiting for CDclk change\n");
5932         }
5933         mutex_unlock(&dev_priv->rps.hw_lock);
5934 
5935         mutex_lock(&dev_priv->sb_lock);
5936 
5937         if (cdclk == 400000) {
5938                 u32 divider;
5939 
5940                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5941 
5942                 /* adjust cdclk divider */
5943                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5944                 val &= ~CCK_FREQUENCY_VALUES;
5945                 val |= divider;
5946                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5947 
5948                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5949                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5950                              50))
5951                         DRM_ERROR("timed out waiting for CDclk change\n");
5952         }
5953 
5954         /* adjust self-refresh exit latency value */
5955         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5956         val &= ~0x7f;
5957 
5958         /*
5959          * For high bandwidth configs, we set a higher latency in the bunit
5960          * so that the core display fetch happens in time to avoid underruns.
5961          */
5962         if (cdclk == 400000)
5963                 val |= 4500 / 250; /* 4.5 usec */
5964         else
5965                 val |= 3000 / 250; /* 3.0 usec */
5966         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5967 
5968         mutex_unlock(&dev_priv->sb_lock);
5969 
5970         intel_update_cdclk(dev);
5971 }
5972 
5973 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5974 {
5975         struct drm_i915_private *dev_priv = dev->dev_private;
5976         u32 val, cmd;
5977 
5978         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5979                                                 != dev_priv->cdclk_freq);
5980 
5981         switch (cdclk) {
5982         case 333333:
5983         case 320000:
5984         case 266667:
5985         case 200000:
5986                 break;
5987         default:
5988                 MISSING_CASE(cdclk);
5989                 return;
5990         }
5991 
5992         /*
5993          * Specs are full of misinformation, but testing on actual
5994          * hardware has shown that we just need to write the desired
5995          * CCK divider into the Punit register.
5996          */
5997         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5998 
5999         mutex_lock(&dev_priv->rps.hw_lock);
6000         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6001         val &= ~DSPFREQGUAR_MASK_CHV;
6002         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6003         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6004         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6005                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6006                      50)) {
6007                 DRM_ERROR("timed out waiting for CDclk change\n");
6008         }
6009         mutex_unlock(&dev_priv->rps.hw_lock);
6010 
6011         intel_update_cdclk(dev);
6012 }
6013 
6014 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6015                                  int max_pixclk)
6016 {
6017         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6018         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6019 
6020         /*
6021          * Really only a few cases to deal with, as only 4 CDclks are supported:
6022          *   200MHz
6023          *   267MHz
6024          *   320/333MHz (depends on HPLL freq)
6025          *   400MHz (VLV only)
6026          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6027          * of the lower bin and adjust if needed.
6028          *
6029          * We seem to get an unstable or solid color picture at 200MHz.
6030          * Not sure what's wrong. For now use 200MHz only when all pipes
6031          * are off.
6032          */
6033         if (!IS_CHERRYVIEW(dev_priv) &&
6034             max_pixclk > freq_320*limit/100)
6035                 return 400000;
6036         else if (max_pixclk > 266667*limit/100)
6037                 return freq_320;
6038         else if (max_pixclk > 0)
6039                 return 266667;
6040         else
6041                 return 200000;
6042 }
6043 
6044 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6045                               int max_pixclk)
6046 {
6047         /*
6048          * FIXME:
6049          * - remove the guardband, it's not needed on BXT
6050          * - set 19.2MHz bypass frequency if there are no active pipes
6051          */
6052         if (max_pixclk > 576000*9/10)
6053                 return 624000;
6054         else if (max_pixclk > 384000*9/10)
6055                 return 576000;
6056         else if (max_pixclk > 288000*9/10)
6057                 return 384000;
6058         else if (max_pixclk > 144000*9/10)
6059                 return 288000;
6060         else
6061                 return 144000;
6062 }
6063 
6064 /* Compute the max pixel clock for new configuration. Uses atomic state if
6065  * that's non-NULL, look at current state otherwise. */
6066 static int intel_mode_max_pixclk(struct drm_device *dev,
6067                                  struct drm_atomic_state *state)
6068 {
6069         struct intel_crtc *intel_crtc;
6070         struct intel_crtc_state *crtc_state;
6071         int max_pixclk = 0;
6072 
6073         for_each_intel_crtc(dev, intel_crtc) {
6074                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6075                 if (IS_ERR(crtc_state))
6076                         return PTR_ERR(crtc_state);
6077 
6078                 if (!crtc_state->base.enable)
6079                         continue;
6080 
6081                 max_pixclk = max(max_pixclk,
6082                                  crtc_state->base.adjusted_mode.crtc_clock);
6083         }
6084 
6085         return max_pixclk;
6086 }
6087 
6088 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6089 {
6090         struct drm_device *dev = state->dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         int max_pixclk = intel_mode_max_pixclk(dev, state);
6093 
6094         if (max_pixclk < 0)
6095                 return max_pixclk;
6096 
6097         to_intel_atomic_state(state)->cdclk =
6098                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6099 
6100         return 0;
6101 }
6102 
6103 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6104 {
6105         struct drm_device *dev = state->dev;
6106         struct drm_i915_private *dev_priv = dev->dev_private;
6107         int max_pixclk = intel_mode_max_pixclk(dev, state);
6108 
6109         if (max_pixclk < 0)
6110                 return max_pixclk;
6111 
6112         to_intel_atomic_state(state)->cdclk =
6113                 broxton_calc_cdclk(dev_priv, max_pixclk);
6114 
6115         return 0;
6116 }
6117 
6118 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6119 {
6120         unsigned int credits, default_credits;
6121 
6122         if (IS_CHERRYVIEW(dev_priv))
6123                 default_credits = PFI_CREDIT(12);
6124         else
6125                 default_credits = PFI_CREDIT(8);
6126 
6127         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6128                 /* CHV suggested value is 31 or 63 */
6129                 if (IS_CHERRYVIEW(dev_priv))
6130                         credits = PFI_CREDIT_63;
6131                 else
6132                         credits = PFI_CREDIT(15);
6133         } else {
6134                 credits = default_credits;
6135         }
6136 
6137         /*
6138          * WA - write default credits before re-programming
6139          * FIXME: should we also set the resend bit here?
6140          */
6141         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6142                    default_credits);
6143 
6144         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6145                    credits | PFI_CREDIT_RESEND);
6146 
6147         /*
6148          * FIXME is this guaranteed to clear
6149          * immediately or should we poll for it?
6150          */
6151         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6152 }
6153 
6154 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6155 {
6156         struct drm_device *dev = old_state->dev;
6157         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159 
6160         /*
6161          * FIXME: We can end up here with all power domains off, yet
6162          * with a CDCLK frequency other than the minimum. To account
6163          * for this take the PIPE-A power domain, which covers the HW
6164          * blocks needed for the following programming. This can be
6165          * removed once it's guaranteed that we get here either with
6166          * the minimum CDCLK set, or the required power domains
6167          * enabled.
6168          */
6169         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6170 
6171         if (IS_CHERRYVIEW(dev))
6172                 cherryview_set_cdclk(dev, req_cdclk);
6173         else
6174                 valleyview_set_cdclk(dev, req_cdclk);
6175 
6176         vlv_program_pfi_credits(dev_priv);
6177 
6178         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6179 }
6180 
6181 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6182 {
6183         struct drm_device *dev = crtc->dev;
6184         struct drm_i915_private *dev_priv = to_i915(dev);
6185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6186         struct intel_encoder *encoder;
6187         int pipe = intel_crtc->pipe;
6188 
6189         if (WARN_ON(intel_crtc->active))
6190                 return;
6191 
6192         if (intel_crtc->config->has_dp_encoder)
6193                 intel_dp_set_m_n(intel_crtc, M1_N1);
6194 
6195         intel_set_pipe_timings(intel_crtc);
6196 
6197         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6198                 struct drm_i915_private *dev_priv = dev->dev_private;
6199 
6200                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6201                 I915_WRITE(CHV_CANVAS(pipe), 0);
6202         }
6203 
6204         i9xx_set_pipeconf(intel_crtc);
6205 
6206         intel_crtc->active = true;
6207 
6208         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6209 
6210         for_each_encoder_on_crtc(dev, crtc, encoder)
6211                 if (encoder->pre_pll_enable)
6212                         encoder->pre_pll_enable(encoder);
6213 
6214         if (!intel_crtc->config->has_dsi_encoder) {
6215                 if (IS_CHERRYVIEW(dev)) {
6216                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6217                         chv_enable_pll(intel_crtc, intel_crtc->config);
6218                 } else {
6219                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6220                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6221                 }
6222         }
6223 
6224         for_each_encoder_on_crtc(dev, crtc, encoder)
6225                 if (encoder->pre_enable)
6226                         encoder->pre_enable(encoder);
6227 
6228         i9xx_pfit_enable(intel_crtc);
6229 
6230         intel_crtc_load_lut(crtc);
6231 
6232         intel_enable_pipe(intel_crtc);
6233 
6234         assert_vblank_disabled(crtc);
6235         drm_crtc_vblank_on(crtc);
6236 
6237         for_each_encoder_on_crtc(dev, crtc, encoder)
6238                 encoder->enable(encoder);
6239 }
6240 
6241 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6242 {
6243         struct drm_device *dev = crtc->base.dev;
6244         struct drm_i915_private *dev_priv = dev->dev_private;
6245 
6246         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6247         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6248 }
6249 
6250 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6251 {
6252         struct drm_device *dev = crtc->dev;
6253         struct drm_i915_private *dev_priv = to_i915(dev);
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255         struct intel_encoder *encoder;
6256         int pipe = intel_crtc->pipe;
6257 
6258         if (WARN_ON(intel_crtc->active))
6259                 return;
6260 
6261         i9xx_set_pll_dividers(intel_crtc);
6262 
6263         if (intel_crtc->config->has_dp_encoder)
6264                 intel_dp_set_m_n(intel_crtc, M1_N1);
6265 
6266         intel_set_pipe_timings(intel_crtc);
6267 
6268         i9xx_set_pipeconf(intel_crtc);
6269 
6270         intel_crtc->active = true;
6271 
6272         if (!IS_GEN2(dev))
6273                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6274 
6275         for_each_encoder_on_crtc(dev, crtc, encoder)
6276                 if (encoder->pre_enable)
6277                         encoder->pre_enable(encoder);
6278 
6279         i9xx_enable_pll(intel_crtc);
6280 
6281         i9xx_pfit_enable(intel_crtc);
6282 
6283         intel_crtc_load_lut(crtc);
6284 
6285         intel_update_watermarks(crtc);
6286         intel_enable_pipe(intel_crtc);
6287 
6288         assert_vblank_disabled(crtc);
6289         drm_crtc_vblank_on(crtc);
6290 
6291         for_each_encoder_on_crtc(dev, crtc, encoder)
6292                 encoder->enable(encoder);
6293 
6294         intel_fbc_enable(intel_crtc);
6295 }
6296 
6297 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6298 {
6299         struct drm_device *dev = crtc->base.dev;
6300         struct drm_i915_private *dev_priv = dev->dev_private;
6301 
6302         if (!crtc->config->gmch_pfit.control)
6303                 return;
6304 
6305         assert_pipe_disabled(dev_priv, crtc->pipe);
6306 
6307         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6308                          I915_READ(PFIT_CONTROL));
6309         I915_WRITE(PFIT_CONTROL, 0);
6310 }
6311 
6312 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6313 {
6314         struct drm_device *dev = crtc->dev;
6315         struct drm_i915_private *dev_priv = dev->dev_private;
6316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317         struct intel_encoder *encoder;
6318         int pipe = intel_crtc->pipe;
6319 
6320         /*
6321          * On gen2 planes are double buffered but the pipe isn't, so we must
6322          * wait for planes to fully turn off before disabling the pipe.
6323          * We also need to wait on all gmch platforms because of the
6324          * self-refresh mode constraint explained above.
6325          */
6326         intel_wait_for_vblank(dev, pipe);
6327 
6328         for_each_encoder_on_crtc(dev, crtc, encoder)
6329                 encoder->disable(encoder);
6330 
6331         drm_crtc_vblank_off(crtc);
6332         assert_vblank_disabled(crtc);
6333 
6334         intel_disable_pipe(intel_crtc);
6335 
6336         i9xx_pfit_disable(intel_crtc);
6337 
6338         for_each_encoder_on_crtc(dev, crtc, encoder)
6339                 if (encoder->post_disable)
6340                         encoder->post_disable(encoder);
6341 
6342         if (!intel_crtc->config->has_dsi_encoder) {
6343                 if (IS_CHERRYVIEW(dev))
6344                         chv_disable_pll(dev_priv, pipe);
6345                 else if (IS_VALLEYVIEW(dev))
6346                         vlv_disable_pll(dev_priv, pipe);
6347                 else
6348                         i9xx_disable_pll(intel_crtc);
6349         }
6350 
6351         for_each_encoder_on_crtc(dev, crtc, encoder)
6352                 if (encoder->post_pll_disable)
6353                         encoder->post_pll_disable(encoder);
6354 
6355         if (!IS_GEN2(dev))
6356                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6357 
6358         intel_fbc_disable_crtc(intel_crtc);
6359 }
6360 
6361 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6362 {
6363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6365         enum intel_display_power_domain domain;
6366         unsigned long domains;
6367 
6368         if (!intel_crtc->active)
6369                 return;
6370 
6371         if (to_intel_plane_state(crtc->primary->state)->visible) {
6372                 WARN_ON(intel_crtc->unpin_work);
6373 
6374                 intel_pre_disable_primary(crtc);
6375 
6376                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6377                 to_intel_plane_state(crtc->primary->state)->visible = false;
6378         }
6379 
6380         dev_priv->display.crtc_disable(crtc);
6381         intel_crtc->active = false;
6382         intel_update_watermarks(crtc);
6383         intel_disable_shared_dpll(intel_crtc);
6384 
6385         domains = intel_crtc->enabled_power_domains;
6386         for_each_power_domain(domain, domains)
6387                 intel_display_power_put(dev_priv, domain);
6388         intel_crtc->enabled_power_domains = 0;
6389 }
6390 
6391 /*
6392  * turn all crtc's off, but do not adjust state
6393  * This has to be paired with a call to intel_modeset_setup_hw_state.
6394  */
6395 int intel_display_suspend(struct drm_device *dev)
6396 {
6397         struct drm_mode_config *config = &dev->mode_config;
6398         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6399         struct drm_atomic_state *state;
6400         struct drm_crtc *crtc;
6401         unsigned crtc_mask = 0;
6402         int ret = 0;
6403 
6404         if (WARN_ON(!ctx))
6405                 return 0;
6406 
6407         lockdep_assert_held(&ctx->ww_ctx);
6408         state = drm_atomic_state_alloc(dev);
6409         if (WARN_ON(!state))
6410                 return -ENOMEM;
6411 
6412         state->acquire_ctx = ctx;
6413         state->allow_modeset = true;
6414 
6415         for_each_crtc(dev, crtc) {
6416                 struct drm_crtc_state *crtc_state =
6417                         drm_atomic_get_crtc_state(state, crtc);
6418 
6419                 ret = PTR_ERR_OR_ZERO(crtc_state);
6420                 if (ret)
6421                         goto free;
6422 
6423                 if (!crtc_state->active)
6424                         continue;
6425 
6426                 crtc_state->active = false;
6427                 crtc_mask |= 1 << drm_crtc_index(crtc);
6428         }
6429 
6430         if (crtc_mask) {
6431                 ret = drm_atomic_commit(state);
6432 
6433                 if (!ret) {
6434                         for_each_crtc(dev, crtc)
6435                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6436                                         crtc->state->active = true;
6437 
6438                         return ret;
6439                 }
6440         }
6441 
6442 free:
6443         if (ret)
6444                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6445         drm_atomic_state_free(state);
6446         return ret;
6447 }
6448 
6449 void intel_encoder_destroy(struct drm_encoder *encoder)
6450 {
6451         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6452 
6453         drm_encoder_cleanup(encoder);
6454         kfree(intel_encoder);
6455 }
6456 
6457 /* Cross check the actual hw state with our own modeset state tracking (and it's
6458  * internal consistency). */
6459 static void intel_connector_check_state(struct intel_connector *connector)
6460 {
6461         struct drm_crtc *crtc = connector->base.state->crtc;
6462 
6463         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6464                       connector->base.base.id,
6465                       connector->base.name);
6466 
6467         if (connector->get_hw_state(connector)) {
6468                 struct intel_encoder *encoder = connector->encoder;
6469                 struct drm_connector_state *conn_state = connector->base.state;
6470 
6471                 I915_STATE_WARN(!crtc,