Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/gpu/drm/i915/intel_display.c

  1 /*
  2  * Copyright © 2006-2007 Intel Corporation
  3  *
  4  * Permission is hereby granted, free of charge, to any person obtaining a
  5  * copy of this software and associated documentation files (the "Software"),
  6  * to deal in the Software without restriction, including without limitation
  7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8  * and/or sell copies of the Software, and to permit persons to whom the
  9  * Software is furnished to do so, subject to the following conditions:
 10  *
 11  * The above copyright notice and this permission notice (including the next
 12  * paragraph) shall be included in all copies or substantial portions of the
 13  * Software.
 14  *
 15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 21  * DEALINGS IN THE SOFTWARE.
 22  *
 23  * Authors:
 24  *      Eric Anholt <eric@anholt.net>
 25  */
 26 
 27 #include <linux/dmi.h>
 28 #include <linux/module.h>
 29 #include <linux/input.h>
 30 #include <linux/i2c.h>
 31 #include <linux/kernel.h>
 32 #include <linux/slab.h>
 33 #include <linux/vgaarb.h>
 34 #include <drm/drm_edid.h>
 35 #include <drm/drmP.h>
 36 #include "intel_drv.h"
 37 #include <drm/i915_drm.h>
 38 #include "i915_drv.h"
 39 #include "i915_trace.h"
 40 #include <drm/drm_dp_helper.h>
 41 #include <drm/drm_crtc_helper.h>
 42 #include <linux/dma_remapping.h>
 43 
 44 static void intel_increase_pllclock(struct drm_crtc *crtc);
 45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 46 
 47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 48                                 struct intel_crtc_config *pipe_config);
 49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 50                                    struct intel_crtc_config *pipe_config);
 51 
 52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
 53                           int x, int y, struct drm_framebuffer *old_fb);
 54 static int intel_framebuffer_init(struct drm_device *dev,
 55                                   struct intel_framebuffer *ifb,
 56                                   struct drm_mode_fb_cmd2 *mode_cmd,
 57                                   struct drm_i915_gem_object *obj);
 58 
 59 typedef struct {
 60         int     min, max;
 61 } intel_range_t;
 62 
 63 typedef struct {
 64         int     dot_limit;
 65         int     p2_slow, p2_fast;
 66 } intel_p2_t;
 67 
 68 typedef struct intel_limit intel_limit_t;
 69 struct intel_limit {
 70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 71         intel_p2_t          p2;
 72 };
 73 
 74 int
 75 intel_pch_rawclk(struct drm_device *dev)
 76 {
 77         struct drm_i915_private *dev_priv = dev->dev_private;
 78 
 79         WARN_ON(!HAS_PCH_SPLIT(dev));
 80 
 81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 82 }
 83 
 84 static inline u32 /* units of 100MHz */
 85 intel_fdi_link_freq(struct drm_device *dev)
 86 {
 87         if (IS_GEN5(dev)) {
 88                 struct drm_i915_private *dev_priv = dev->dev_private;
 89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 90         } else
 91                 return 27;
 92 }
 93 
 94 static const intel_limit_t intel_limits_i8xx_dac = {
 95         .dot = { .min = 25000, .max = 350000 },
 96         .vco = { .min = 908000, .max = 1512000 },
 97         .n = { .min = 2, .max = 16 },
 98         .m = { .min = 96, .max = 140 },
 99         .m1 = { .min = 18, .max = 26 },
100         .m2 = { .min = 6, .max = 16 },
101         .p = { .min = 4, .max = 128 },
102         .p1 = { .min = 2, .max = 33 },
103         .p2 = { .dot_limit = 165000,
104                 .p2_slow = 4, .p2_fast = 2 },
105 };
106 
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108         .dot = { .min = 25000, .max = 350000 },
109         .vco = { .min = 908000, .max = 1512000 },
110         .n = { .min = 2, .max = 16 },
111         .m = { .min = 96, .max = 140 },
112         .m1 = { .min = 18, .max = 26 },
113         .m2 = { .min = 6, .max = 16 },
114         .p = { .min = 4, .max = 128 },
115         .p1 = { .min = 2, .max = 33 },
116         .p2 = { .dot_limit = 165000,
117                 .p2_slow = 4, .p2_fast = 4 },
118 };
119 
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121         .dot = { .min = 25000, .max = 350000 },
122         .vco = { .min = 908000, .max = 1512000 },
123         .n = { .min = 2, .max = 16 },
124         .m = { .min = 96, .max = 140 },
125         .m1 = { .min = 18, .max = 26 },
126         .m2 = { .min = 6, .max = 16 },
127         .p = { .min = 4, .max = 128 },
128         .p1 = { .min = 1, .max = 6 },
129         .p2 = { .dot_limit = 165000,
130                 .p2_slow = 14, .p2_fast = 7 },
131 };
132 
133 static const intel_limit_t intel_limits_i9xx_sdvo = {
134         .dot = { .min = 20000, .max = 400000 },
135         .vco = { .min = 1400000, .max = 2800000 },
136         .n = { .min = 1, .max = 6 },
137         .m = { .min = 70, .max = 120 },
138         .m1 = { .min = 8, .max = 18 },
139         .m2 = { .min = 3, .max = 7 },
140         .p = { .min = 5, .max = 80 },
141         .p1 = { .min = 1, .max = 8 },
142         .p2 = { .dot_limit = 200000,
143                 .p2_slow = 10, .p2_fast = 5 },
144 };
145 
146 static const intel_limit_t intel_limits_i9xx_lvds = {
147         .dot = { .min = 20000, .max = 400000 },
148         .vco = { .min = 1400000, .max = 2800000 },
149         .n = { .min = 1, .max = 6 },
150         .m = { .min = 70, .max = 120 },
151         .m1 = { .min = 8, .max = 18 },
152         .m2 = { .min = 3, .max = 7 },
153         .p = { .min = 7, .max = 98 },
154         .p1 = { .min = 1, .max = 8 },
155         .p2 = { .dot_limit = 112000,
156                 .p2_slow = 14, .p2_fast = 7 },
157 };
158 
159 
160 static const intel_limit_t intel_limits_g4x_sdvo = {
161         .dot = { .min = 25000, .max = 270000 },
162         .vco = { .min = 1750000, .max = 3500000},
163         .n = { .min = 1, .max = 4 },
164         .m = { .min = 104, .max = 138 },
165         .m1 = { .min = 17, .max = 23 },
166         .m2 = { .min = 5, .max = 11 },
167         .p = { .min = 10, .max = 30 },
168         .p1 = { .min = 1, .max = 3},
169         .p2 = { .dot_limit = 270000,
170                 .p2_slow = 10,
171                 .p2_fast = 10
172         },
173 };
174 
175 static const intel_limit_t intel_limits_g4x_hdmi = {
176         .dot = { .min = 22000, .max = 400000 },
177         .vco = { .min = 1750000, .max = 3500000},
178         .n = { .min = 1, .max = 4 },
179         .m = { .min = 104, .max = 138 },
180         .m1 = { .min = 16, .max = 23 },
181         .m2 = { .min = 5, .max = 11 },
182         .p = { .min = 5, .max = 80 },
183         .p1 = { .min = 1, .max = 8},
184         .p2 = { .dot_limit = 165000,
185                 .p2_slow = 10, .p2_fast = 5 },
186 };
187 
188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
189         .dot = { .min = 20000, .max = 115000 },
190         .vco = { .min = 1750000, .max = 3500000 },
191         .n = { .min = 1, .max = 3 },
192         .m = { .min = 104, .max = 138 },
193         .m1 = { .min = 17, .max = 23 },
194         .m2 = { .min = 5, .max = 11 },
195         .p = { .min = 28, .max = 112 },
196         .p1 = { .min = 2, .max = 8 },
197         .p2 = { .dot_limit = 0,
198                 .p2_slow = 14, .p2_fast = 14
199         },
200 };
201 
202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
203         .dot = { .min = 80000, .max = 224000 },
204         .vco = { .min = 1750000, .max = 3500000 },
205         .n = { .min = 1, .max = 3 },
206         .m = { .min = 104, .max = 138 },
207         .m1 = { .min = 17, .max = 23 },
208         .m2 = { .min = 5, .max = 11 },
209         .p = { .min = 14, .max = 42 },
210         .p1 = { .min = 2, .max = 6 },
211         .p2 = { .dot_limit = 0,
212                 .p2_slow = 7, .p2_fast = 7
213         },
214 };
215 
216 static const intel_limit_t intel_limits_pineview_sdvo = {
217         .dot = { .min = 20000, .max = 400000},
218         .vco = { .min = 1700000, .max = 3500000 },
219         /* Pineview's Ncounter is a ring counter */
220         .n = { .min = 3, .max = 6 },
221         .m = { .min = 2, .max = 256 },
222         /* Pineview only has one combined m divider, which we treat as m2. */
223         .m1 = { .min = 0, .max = 0 },
224         .m2 = { .min = 0, .max = 254 },
225         .p = { .min = 5, .max = 80 },
226         .p1 = { .min = 1, .max = 8 },
227         .p2 = { .dot_limit = 200000,
228                 .p2_slow = 10, .p2_fast = 5 },
229 };
230 
231 static const intel_limit_t intel_limits_pineview_lvds = {
232         .dot = { .min = 20000, .max = 400000 },
233         .vco = { .min = 1700000, .max = 3500000 },
234         .n = { .min = 3, .max = 6 },
235         .m = { .min = 2, .max = 256 },
236         .m1 = { .min = 0, .max = 0 },
237         .m2 = { .min = 0, .max = 254 },
238         .p = { .min = 7, .max = 112 },
239         .p1 = { .min = 1, .max = 8 },
240         .p2 = { .dot_limit = 112000,
241                 .p2_slow = 14, .p2_fast = 14 },
242 };
243 
244 /* Ironlake / Sandybridge
245  *
246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
247  * the range value for them is (actual_value - 2).
248  */
249 static const intel_limit_t intel_limits_ironlake_dac = {
250         .dot = { .min = 25000, .max = 350000 },
251         .vco = { .min = 1760000, .max = 3510000 },
252         .n = { .min = 1, .max = 5 },
253         .m = { .min = 79, .max = 127 },
254         .m1 = { .min = 12, .max = 22 },
255         .m2 = { .min = 5, .max = 9 },
256         .p = { .min = 5, .max = 80 },
257         .p1 = { .min = 1, .max = 8 },
258         .p2 = { .dot_limit = 225000,
259                 .p2_slow = 10, .p2_fast = 5 },
260 };
261 
262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
263         .dot = { .min = 25000, .max = 350000 },
264         .vco = { .min = 1760000, .max = 3510000 },
265         .n = { .min = 1, .max = 3 },
266         .m = { .min = 79, .max = 118 },
267         .m1 = { .min = 12, .max = 22 },
268         .m2 = { .min = 5, .max = 9 },
269         .p = { .min = 28, .max = 112 },
270         .p1 = { .min = 2, .max = 8 },
271         .p2 = { .dot_limit = 225000,
272                 .p2_slow = 14, .p2_fast = 14 },
273 };
274 
275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
276         .dot = { .min = 25000, .max = 350000 },
277         .vco = { .min = 1760000, .max = 3510000 },
278         .n = { .min = 1, .max = 3 },
279         .m = { .min = 79, .max = 127 },
280         .m1 = { .min = 12, .max = 22 },
281         .m2 = { .min = 5, .max = 9 },
282         .p = { .min = 14, .max = 56 },
283         .p1 = { .min = 2, .max = 8 },
284         .p2 = { .dot_limit = 225000,
285                 .p2_slow = 7, .p2_fast = 7 },
286 };
287 
288 /* LVDS 100mhz refclk limits. */
289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
290         .dot = { .min = 25000, .max = 350000 },
291         .vco = { .min = 1760000, .max = 3510000 },
292         .n = { .min = 1, .max = 2 },
293         .m = { .min = 79, .max = 126 },
294         .m1 = { .min = 12, .max = 22 },
295         .m2 = { .min = 5, .max = 9 },
296         .p = { .min = 28, .max = 112 },
297         .p1 = { .min = 2, .max = 8 },
298         .p2 = { .dot_limit = 225000,
299                 .p2_slow = 14, .p2_fast = 14 },
300 };
301 
302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
303         .dot = { .min = 25000, .max = 350000 },
304         .vco = { .min = 1760000, .max = 3510000 },
305         .n = { .min = 1, .max = 3 },
306         .m = { .min = 79, .max = 126 },
307         .m1 = { .min = 12, .max = 22 },
308         .m2 = { .min = 5, .max = 9 },
309         .p = { .min = 14, .max = 42 },
310         .p1 = { .min = 2, .max = 6 },
311         .p2 = { .dot_limit = 225000,
312                 .p2_slow = 7, .p2_fast = 7 },
313 };
314 
315 static const intel_limit_t intel_limits_vlv = {
316          /*
317           * These are the data rate limits (measured in fast clocks)
318           * since those are the strictest limits we have. The fast
319           * clock and actual rate limits are more relaxed, so checking
320           * them would make no difference.
321           */
322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
323         .vco = { .min = 4000000, .max = 6000000 },
324         .n = { .min = 1, .max = 7 },
325         .m1 = { .min = 2, .max = 3 },
326         .m2 = { .min = 11, .max = 156 },
327         .p1 = { .min = 2, .max = 3 },
328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
329 };
330 
331 static void vlv_clock(int refclk, intel_clock_t *clock)
332 {
333         clock->m = clock->m1 * clock->m2;
334         clock->p = clock->p1 * clock->p2;
335         if (WARN_ON(clock->n == 0 || clock->p == 0))
336                 return;
337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 }
340 
341 /**
342  * Returns whether any output on the specified pipe is of the specified type
343  */
344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
345 {
346         struct drm_device *dev = crtc->dev;
347         struct intel_encoder *encoder;
348 
349         for_each_encoder_on_crtc(dev, crtc, encoder)
350                 if (encoder->type == type)
351                         return true;
352 
353         return false;
354 }
355 
356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
357                                                 int refclk)
358 {
359         struct drm_device *dev = crtc->dev;
360         const intel_limit_t *limit;
361 
362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
363                 if (intel_is_dual_link_lvds(dev)) {
364                         if (refclk == 100000)
365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
366                         else
367                                 limit = &intel_limits_ironlake_dual_lvds;
368                 } else {
369                         if (refclk == 100000)
370                                 limit = &intel_limits_ironlake_single_lvds_100m;
371                         else
372                                 limit = &intel_limits_ironlake_single_lvds;
373                 }
374         } else
375                 limit = &intel_limits_ironlake_dac;
376 
377         return limit;
378 }
379 
380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 {
382         struct drm_device *dev = crtc->dev;
383         const intel_limit_t *limit;
384 
385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
386                 if (intel_is_dual_link_lvds(dev))
387                         limit = &intel_limits_g4x_dual_channel_lvds;
388                 else
389                         limit = &intel_limits_g4x_single_channel_lvds;
390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
392                 limit = &intel_limits_g4x_hdmi;
393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
394                 limit = &intel_limits_g4x_sdvo;
395         } else /* The option is for other outputs */
396                 limit = &intel_limits_i9xx_sdvo;
397 
398         return limit;
399 }
400 
401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 {
403         struct drm_device *dev = crtc->dev;
404         const intel_limit_t *limit;
405 
406         if (HAS_PCH_SPLIT(dev))
407                 limit = intel_ironlake_limit(crtc, refclk);
408         else if (IS_G4X(dev)) {
409                 limit = intel_g4x_limit(crtc);
410         } else if (IS_PINEVIEW(dev)) {
411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412                         limit = &intel_limits_pineview_lvds;
413                 else
414                         limit = &intel_limits_pineview_sdvo;
415         } else if (IS_VALLEYVIEW(dev)) {
416                 limit = &intel_limits_vlv;
417         } else if (!IS_GEN2(dev)) {
418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419                         limit = &intel_limits_i9xx_lvds;
420                 else
421                         limit = &intel_limits_i9xx_sdvo;
422         } else {
423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
424                         limit = &intel_limits_i8xx_lvds;
425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
426                         limit = &intel_limits_i8xx_dvo;
427                 else
428                         limit = &intel_limits_i8xx_dac;
429         }
430         return limit;
431 }
432 
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk, intel_clock_t *clock)
435 {
436         clock->m = clock->m2 + 2;
437         clock->p = clock->p1 * clock->p2;
438         if (WARN_ON(clock->n == 0 || clock->p == 0))
439                 return;
440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
442 }
443 
444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
445 {
446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
447 }
448 
449 static void i9xx_clock(int refclk, intel_clock_t *clock)
450 {
451         clock->m = i9xx_dpll_compute_m(clock);
452         clock->p = clock->p1 * clock->p2;
453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
454                 return;
455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
457 }
458 
459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
460 /**
461  * Returns whether the given set of divisors are valid for a given refclk with
462  * the given connectors.
463  */
464 
465 static bool intel_PLL_is_valid(struct drm_device *dev,
466                                const intel_limit_t *limit,
467                                const intel_clock_t *clock)
468 {
469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
470                 INTELPllInvalid("n out of range\n");
471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
472                 INTELPllInvalid("p1 out of range\n");
473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
474                 INTELPllInvalid("m2 out of range\n");
475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
476                 INTELPllInvalid("m1 out of range\n");
477 
478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
479                 if (clock->m1 <= clock->m2)
480                         INTELPllInvalid("m1 <= m2\n");
481 
482         if (!IS_VALLEYVIEW(dev)) {
483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
484                         INTELPllInvalid("p out of range\n");
485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
486                         INTELPllInvalid("m out of range\n");
487         }
488 
489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
490                 INTELPllInvalid("vco out of range\n");
491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
492          * connector, etc., rather than just a single range.
493          */
494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
495                 INTELPllInvalid("dot out of range\n");
496 
497         return true;
498 }
499 
500 static bool
501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
502                     int target, int refclk, intel_clock_t *match_clock,
503                     intel_clock_t *best_clock)
504 {
505         struct drm_device *dev = crtc->dev;
506         intel_clock_t clock;
507         int err = target;
508 
509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
510                 /*
511                  * For LVDS just rely on its current settings for dual-channel.
512                  * We haven't figured out how to reliably set up different
513                  * single/dual channel state, if we even can.
514                  */
515                 if (intel_is_dual_link_lvds(dev))
516                         clock.p2 = limit->p2.p2_fast;
517                 else
518                         clock.p2 = limit->p2.p2_slow;
519         } else {
520                 if (target < limit->p2.dot_limit)
521                         clock.p2 = limit->p2.p2_slow;
522                 else
523                         clock.p2 = limit->p2.p2_fast;
524         }
525 
526         memset(best_clock, 0, sizeof(*best_clock));
527 
528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
529              clock.m1++) {
530                 for (clock.m2 = limit->m2.min;
531                      clock.m2 <= limit->m2.max; clock.m2++) {
532                         if (clock.m2 >= clock.m1)
533                                 break;
534                         for (clock.n = limit->n.min;
535                              clock.n <= limit->n.max; clock.n++) {
536                                 for (clock.p1 = limit->p1.min;
537                                         clock.p1 <= limit->p1.max; clock.p1++) {
538                                         int this_err;
539 
540                                         i9xx_clock(refclk, &clock);
541                                         if (!intel_PLL_is_valid(dev, limit,
542                                                                 &clock))
543                                                 continue;
544                                         if (match_clock &&
545                                             clock.p != match_clock->p)
546                                                 continue;
547 
548                                         this_err = abs(clock.dot - target);
549                                         if (this_err < err) {
550                                                 *best_clock = clock;
551                                                 err = this_err;
552                                         }
553                                 }
554                         }
555                 }
556         }
557 
558         return (err != target);
559 }
560 
561 static bool
562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
563                    int target, int refclk, intel_clock_t *match_clock,
564                    intel_clock_t *best_clock)
565 {
566         struct drm_device *dev = crtc->dev;
567         intel_clock_t clock;
568         int err = target;
569 
570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
571                 /*
572                  * For LVDS just rely on its current settings for dual-channel.
573                  * We haven't figured out how to reliably set up different
574                  * single/dual channel state, if we even can.
575                  */
576                 if (intel_is_dual_link_lvds(dev))
577                         clock.p2 = limit->p2.p2_fast;
578                 else
579                         clock.p2 = limit->p2.p2_slow;
580         } else {
581                 if (target < limit->p2.dot_limit)
582                         clock.p2 = limit->p2.p2_slow;
583                 else
584                         clock.p2 = limit->p2.p2_fast;
585         }
586 
587         memset(best_clock, 0, sizeof(*best_clock));
588 
589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
590              clock.m1++) {
591                 for (clock.m2 = limit->m2.min;
592                      clock.m2 <= limit->m2.max; clock.m2++) {
593                         for (clock.n = limit->n.min;
594                              clock.n <= limit->n.max; clock.n++) {
595                                 for (clock.p1 = limit->p1.min;
596                                         clock.p1 <= limit->p1.max; clock.p1++) {
597                                         int this_err;
598 
599                                         pineview_clock(refclk, &clock);
600                                         if (!intel_PLL_is_valid(dev, limit,
601                                                                 &clock))
602                                                 continue;
603                                         if (match_clock &&
604                                             clock.p != match_clock->p)
605                                                 continue;
606 
607                                         this_err = abs(clock.dot - target);
608                                         if (this_err < err) {
609                                                 *best_clock = clock;
610                                                 err = this_err;
611                                         }
612                                 }
613                         }
614                 }
615         }
616 
617         return (err != target);
618 }
619 
620 static bool
621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
622                    int target, int refclk, intel_clock_t *match_clock,
623                    intel_clock_t *best_clock)
624 {
625         struct drm_device *dev = crtc->dev;
626         intel_clock_t clock;
627         int max_n;
628         bool found;
629         /* approximately equals target * 0.00585 */
630         int err_most = (target >> 8) + (target >> 9);
631         found = false;
632 
633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
634                 if (intel_is_dual_link_lvds(dev))
635                         clock.p2 = limit->p2.p2_fast;
636                 else
637                         clock.p2 = limit->p2.p2_slow;
638         } else {
639                 if (target < limit->p2.dot_limit)
640                         clock.p2 = limit->p2.p2_slow;
641                 else
642                         clock.p2 = limit->p2.p2_fast;
643         }
644 
645         memset(best_clock, 0, sizeof(*best_clock));
646         max_n = limit->n.max;
647         /* based on hardware requirement, prefer smaller n to precision */
648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
649                 /* based on hardware requirement, prefere larger m1,m2 */
650                 for (clock.m1 = limit->m1.max;
651                      clock.m1 >= limit->m1.min; clock.m1--) {
652                         for (clock.m2 = limit->m2.max;
653                              clock.m2 >= limit->m2.min; clock.m2--) {
654                                 for (clock.p1 = limit->p1.max;
655                                      clock.p1 >= limit->p1.min; clock.p1--) {
656                                         int this_err;
657 
658                                         i9xx_clock(refclk, &clock);
659                                         if (!intel_PLL_is_valid(dev, limit,
660                                                                 &clock))
661                                                 continue;
662 
663                                         this_err = abs(clock.dot - target);
664                                         if (this_err < err_most) {
665                                                 *best_clock = clock;
666                                                 err_most = this_err;
667                                                 max_n = clock.n;
668                                                 found = true;
669                                         }
670                                 }
671                         }
672                 }
673         }
674         return found;
675 }
676 
677 static bool
678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
679                    int target, int refclk, intel_clock_t *match_clock,
680                    intel_clock_t *best_clock)
681 {
682         struct drm_device *dev = crtc->dev;
683         intel_clock_t clock;
684         unsigned int bestppm = 1000000;
685         /* min update 19.2 MHz */
686         int max_n = min(limit->n.max, refclk / 19200);
687         bool found = false;
688 
689         target *= 5; /* fast clock */
690 
691         memset(best_clock, 0, sizeof(*best_clock));
692 
693         /* based on hardware requirement, prefer smaller n to precision */
694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
698                                 clock.p = clock.p1 * clock.p2;
699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
701                                         unsigned int ppm, diff;
702 
703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
704                                                                      refclk * clock.m1);
705 
706                                         vlv_clock(refclk, &clock);
707 
708                                         if (!intel_PLL_is_valid(dev, limit,
709                                                                 &clock))
710                                                 continue;
711 
712                                         diff = abs(clock.dot - target);
713                                         ppm = div_u64(1000000ULL * diff, target);
714 
715                                         if (ppm < 100 && clock.p > best_clock->p) {
716                                                 bestppm = 0;
717                                                 *best_clock = clock;
718                                                 found = true;
719                                         }
720 
721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
722                                                 bestppm = ppm;
723                                                 *best_clock = clock;
724                                                 found = true;
725                                         }
726                                 }
727                         }
728                 }
729         }
730 
731         return found;
732 }
733 
734 bool intel_crtc_active(struct drm_crtc *crtc)
735 {
736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737 
738         /* Be paranoid as we can arrive here with only partial
739          * state retrieved from the hardware during setup.
740          *
741          * We can ditch the adjusted_mode.crtc_clock check as soon
742          * as Haswell has gained clock readout/fastboot support.
743          *
744          * We can ditch the crtc->primary->fb check as soon as we can
745          * properly reconstruct framebuffers.
746          */
747         return intel_crtc->active && crtc->primary->fb &&
748                 intel_crtc->config.adjusted_mode.crtc_clock;
749 }
750 
751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
752                                              enum pipe pipe)
753 {
754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756 
757         return intel_crtc->config.cpu_transcoder;
758 }
759 
760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762         struct drm_i915_private *dev_priv = dev->dev_private;
763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
764 
765         frame = I915_READ(frame_reg);
766 
767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
768                 DRM_DEBUG_KMS("vblank wait timed out\n");
769 }
770 
771 /**
772  * intel_wait_for_vblank - wait for vblank on a given pipe
773  * @dev: drm device
774  * @pipe: pipe to wait for
775  *
776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
777  * mode setting code.
778  */
779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
780 {
781         struct drm_i915_private *dev_priv = dev->dev_private;
782         int pipestat_reg = PIPESTAT(pipe);
783 
784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785                 g4x_wait_for_vblank(dev, pipe);
786                 return;
787         }
788 
789         /* Clear existing vblank status. Note this will clear any other
790          * sticky status fields as well.
791          *
792          * This races with i915_driver_irq_handler() with the result
793          * that either function could miss a vblank event.  Here it is not
794          * fatal, as we will either wait upon the next vblank interrupt or
795          * timeout.  Generally speaking intel_wait_for_vblank() is only
796          * called during modeset at which time the GPU should be idle and
797          * should *not* be performing page flips and thus not waiting on
798          * vblanks...
799          * Currently, the result of us stealing a vblank from the irq
800          * handler is that a single frame will be skipped during swapbuffers.
801          */
802         I915_WRITE(pipestat_reg,
803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
804 
805         /* Wait for vblank interrupt bit to set */
806         if (wait_for(I915_READ(pipestat_reg) &
807                      PIPE_VBLANK_INTERRUPT_STATUS,
808                      50))
809                 DRM_DEBUG_KMS("vblank wait timed out\n");
810 }
811 
812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
813 {
814         struct drm_i915_private *dev_priv = dev->dev_private;
815         u32 reg = PIPEDSL(pipe);
816         u32 line1, line2;
817         u32 line_mask;
818 
819         if (IS_GEN2(dev))
820                 line_mask = DSL_LINEMASK_GEN2;
821         else
822                 line_mask = DSL_LINEMASK_GEN3;
823 
824         line1 = I915_READ(reg) & line_mask;
825         mdelay(5);
826         line2 = I915_READ(reg) & line_mask;
827 
828         return line1 == line2;
829 }
830 
831 /*
832  * intel_wait_for_pipe_off - wait for pipe to turn off
833  * @dev: drm device
834  * @pipe: pipe to wait for
835  *
836  * After disabling a pipe, we can't wait for vblank in the usual way,
837  * spinning on the vblank interrupt status bit, since we won't actually
838  * see an interrupt when the pipe is disabled.
839  *
840  * On Gen4 and above:
841  *   wait for the pipe register state bit to turn off
842  *
843  * Otherwise:
844  *   wait for the display line value to settle (it usually
845  *   ends up stopping at the start of the next frame).
846  *
847  */
848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
849 {
850         struct drm_i915_private *dev_priv = dev->dev_private;
851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
852                                                                       pipe);
853 
854         if (INTEL_INFO(dev)->gen >= 4) {
855                 int reg = PIPECONF(cpu_transcoder);
856 
857                 /* Wait for the Pipe State to go off */
858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
859                              100))
860                         WARN(1, "pipe_off wait timed out\n");
861         } else {
862                 /* Wait for the display line to settle */
863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
864                         WARN(1, "pipe_off wait timed out\n");
865         }
866 }
867 
868 /*
869  * ibx_digital_port_connected - is the specified port connected?
870  * @dev_priv: i915 private structure
871  * @port: the port to test
872  *
873  * Returns true if @port is connected, false otherwise.
874  */
875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
876                                 struct intel_digital_port *port)
877 {
878         u32 bit;
879 
880         if (HAS_PCH_IBX(dev_priv->dev)) {
881                 switch(port->port) {
882                 case PORT_B:
883                         bit = SDE_PORTB_HOTPLUG;
884                         break;
885                 case PORT_C:
886                         bit = SDE_PORTC_HOTPLUG;
887                         break;
888                 case PORT_D:
889                         bit = SDE_PORTD_HOTPLUG;
890                         break;
891                 default:
892                         return true;
893                 }
894         } else {
895                 switch(port->port) {
896                 case PORT_B:
897                         bit = SDE_PORTB_HOTPLUG_CPT;
898                         break;
899                 case PORT_C:
900                         bit = SDE_PORTC_HOTPLUG_CPT;
901                         break;
902                 case PORT_D:
903                         bit = SDE_PORTD_HOTPLUG_CPT;
904                         break;
905                 default:
906                         return true;
907                 }
908         }
909 
910         return I915_READ(SDEISR) & bit;
911 }
912 
913 static const char *state_string(bool enabled)
914 {
915         return enabled ? "on" : "off";
916 }
917 
918 /* Only for pre-ILK configs */
919 void assert_pll(struct drm_i915_private *dev_priv,
920                 enum pipe pipe, bool state)
921 {
922         int reg;
923         u32 val;
924         bool cur_state;
925 
926         reg = DPLL(pipe);
927         val = I915_READ(reg);
928         cur_state = !!(val & DPLL_VCO_ENABLE);
929         WARN(cur_state != state,
930              "PLL state assertion failure (expected %s, current %s)\n",
931              state_string(state), state_string(cur_state));
932 }
933 
934 /* XXX: the dsi pll is shared between MIPI DSI ports */
935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
936 {
937         u32 val;
938         bool cur_state;
939 
940         mutex_lock(&dev_priv->dpio_lock);
941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
942         mutex_unlock(&dev_priv->dpio_lock);
943 
944         cur_state = val & DSI_PLL_VCO_EN;
945         WARN(cur_state != state,
946              "DSI PLL state assertion failure (expected %s, current %s)\n",
947              state_string(state), state_string(cur_state));
948 }
949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
951 
952 struct intel_shared_dpll *
953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
954 {
955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
956 
957         if (crtc->config.shared_dpll < 0)
958                 return NULL;
959 
960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 }
962 
963 /* For ILK+ */
964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
965                         struct intel_shared_dpll *pll,
966                         bool state)
967 {
968         bool cur_state;
969         struct intel_dpll_hw_state hw_state;
970 
971         if (HAS_PCH_LPT(dev_priv->dev)) {
972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
973                 return;
974         }
975 
976         if (WARN (!pll,
977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
978                 return;
979 
980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
981         WARN(cur_state != state,
982              "%s assertion failure (expected %s, current %s)\n",
983              pll->name, state_string(state), state_string(cur_state));
984 }
985 
986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
987                           enum pipe pipe, bool state)
988 {
989         int reg;
990         u32 val;
991         bool cur_state;
992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
993                                                                       pipe);
994 
995         if (HAS_DDI(dev_priv->dev)) {
996                 /* DDI does not have a specific FDI_TX register */
997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
998                 val = I915_READ(reg);
999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011 
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018 
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028 
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034 
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038 
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042 
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047 
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054 
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062 
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070 
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078 
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083 
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086 
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091 
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097 
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104 
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111 
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120 
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124 
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133 
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138 
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145 
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153 
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156 
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164 
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174 
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186 
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193 
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216 
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221 
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223 
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229 
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236 
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244 
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250 
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262 
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268 
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278 
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284 
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294 
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309 
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317 
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322 
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330 
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335 
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341 
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345 
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351 
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357 
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362 
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366 
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369 
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372 
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376 
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379 
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387 
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400 
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407 
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409 
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412 
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416 
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420 
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423 
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426 
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438 
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445 
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447 
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450 
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454 
1455         I915_WRITE(reg, dpll);
1456 
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460 
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472 
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484 
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499 
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502 
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506 
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510 
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513 
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523 
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528 
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539 
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544 
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558 
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563 
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566 
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570 
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577 
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582 
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588 
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593 
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596 
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600 
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605 
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610 
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615 
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623 
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626 
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630 
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634 
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643 
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647 
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656 
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666 
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671 
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676 
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679 
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683 
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688 
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691 
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697 
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702 
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708 
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712 
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715 
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723 
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732 
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736 
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743 
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749 
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767 
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771 
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776 
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796 
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804 
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807 
1808         /*
1809          * There's no guarantee the pipe will really start running now. It
1810          * depends on the Gen, the output type and the relative order between
1811          * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812          * necessary.
1813          * TODO: audit the previous gens.
1814          */
1815         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816                 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818 
1819 /**
1820  * intel_disable_pipe - disable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to disable
1823  *
1824  * Disable @pipe, making sure that various hardware specific requirements
1825  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826  *
1827  * @pipe should be %PIPE_A or %PIPE_B.
1828  *
1829  * Will wait until the pipe has shut down before returning.
1830  */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832                                enum pipe pipe)
1833 {
1834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835                                                                       pipe);
1836         int reg;
1837         u32 val;
1838 
1839         /*
1840          * Make sure planes won't keep trying to pump pixels to us,
1841          * or we might hang the display.
1842          */
1843         assert_planes_disabled(dev_priv, pipe);
1844         assert_cursor_disabled(dev_priv, pipe);
1845         assert_sprites_disabled(dev_priv, pipe);
1846 
1847         /* Don't disable pipe A or pipe A PLLs if needed */
1848         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849                 return;
1850 
1851         reg = PIPECONF(cpu_transcoder);
1852         val = I915_READ(reg);
1853         if ((val & PIPECONF_ENABLE) == 0)
1854                 return;
1855 
1856         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859 
1860 /*
1861  * Plane regs are double buffered, going from enabled->disabled needs a
1862  * trigger in order to latch.  The display address reg provides this.
1863  */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865                                enum plane plane)
1866 {
1867         struct drm_device *dev = dev_priv->dev;
1868         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869 
1870         I915_WRITE(reg, I915_READ(reg));
1871         POSTING_READ(reg);
1872 }
1873 
1874 /**
1875  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1876  * @dev_priv: i915 private structure
1877  * @plane: plane to enable
1878  * @pipe: pipe being fed
1879  *
1880  * Enable @plane on @pipe, making sure that @pipe is running first.
1881  */
1882 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1883                                           enum plane plane, enum pipe pipe)
1884 {
1885         struct intel_crtc *intel_crtc =
1886                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887         int reg;
1888         u32 val;
1889 
1890         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891         assert_pipe_enabled(dev_priv, pipe);
1892 
1893         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894 
1895         intel_crtc->primary_enabled = true;
1896 
1897         reg = DSPCNTR(plane);
1898         val = I915_READ(reg);
1899         if (val & DISPLAY_PLANE_ENABLE)
1900                 return;
1901 
1902         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903         intel_flush_primary_plane(dev_priv, plane);
1904         intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906 
1907 /**
1908  * intel_disable_primary_hw_plane - disable the primary hardware plane
1909  * @dev_priv: i915 private structure
1910  * @plane: plane to disable
1911  * @pipe: pipe consuming the data
1912  *
1913  * Disable @plane; should be an independent operation.
1914  */
1915 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1916                                            enum plane plane, enum pipe pipe)
1917 {
1918         struct intel_crtc *intel_crtc =
1919                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920         int reg;
1921         u32 val;
1922 
1923         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924 
1925         intel_crtc->primary_enabled = false;
1926 
1927         reg = DSPCNTR(plane);
1928         val = I915_READ(reg);
1929         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930                 return;
1931 
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_primary_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936 
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941                 return true;
1942 #endif
1943         return false;
1944 }
1945 
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948         int tile_height;
1949 
1950         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951         return ALIGN(height, tile_height);
1952 }
1953 
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956                            struct drm_i915_gem_object *obj,
1957                            struct intel_ring_buffer *pipelined)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         u32 alignment;
1961         int ret;
1962 
1963         switch (obj->tiling_mode) {
1964         case I915_TILING_NONE:
1965                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966                         alignment = 128 * 1024;
1967                 else if (INTEL_INFO(dev)->gen >= 4)
1968                         alignment = 4 * 1024;
1969                 else
1970                         alignment = 64 * 1024;
1971                 break;
1972         case I915_TILING_X:
1973                 /* pin() will align the object as required by fence */
1974                 alignment = 0;
1975                 break;
1976         case I915_TILING_Y:
1977                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978                 return -EINVAL;
1979         default:
1980                 BUG();
1981         }
1982 
1983         /* Note that the w/a also requires 64 PTE of padding following the
1984          * bo. We currently fill all unused PTE with the shadow page and so
1985          * we should always have valid PTE following the scanout preventing
1986          * the VT-d warning.
1987          */
1988         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989                 alignment = 256 * 1024;
1990 
1991         dev_priv->mm.interruptible = false;
1992         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993         if (ret)
1994                 goto err_interruptible;
1995 
1996         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997          * fence, whereas 965+ only requires a fence if using
1998          * framebuffer compression.  For simplicity, we always install
1999          * a fence as the cost is not that onerous.
2000          */
2001         ret = i915_gem_object_get_fence(obj);
2002         if (ret)
2003                 goto err_unpin;
2004 
2005         i915_gem_object_pin_fence(obj);
2006 
2007         dev_priv->mm.interruptible = true;
2008         return 0;
2009 
2010 err_unpin:
2011         i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013         dev_priv->mm.interruptible = true;
2014         return ret;
2015 }
2016 
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019         i915_gem_object_unpin_fence(obj);
2020         i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022 
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024  * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026                                              unsigned int tiling_mode,
2027                                              unsigned int cpp,
2028                                              unsigned int pitch)
2029 {
2030         if (tiling_mode != I915_TILING_NONE) {
2031                 unsigned int tile_rows, tiles;
2032 
2033                 tile_rows = *y / 8;
2034                 *y %= 8;
2035 
2036                 tiles = *x / (512/cpp);
2037                 *x %= 512/cpp;
2038 
2039                 return tile_rows * pitch * 8 + tiles * 4096;
2040         } else {
2041                 unsigned int offset;
2042 
2043                 offset = *y * pitch + *x * cpp;
2044                 *y = 0;
2045                 *x = (offset & 4095) / cpp;
2046                 return offset & -4096;
2047         }
2048 }
2049 
2050 int intel_format_to_fourcc(int format)
2051 {
2052         switch (format) {
2053         case DISPPLANE_8BPP:
2054                 return DRM_FORMAT_C8;
2055         case DISPPLANE_BGRX555:
2056                 return DRM_FORMAT_XRGB1555;
2057         case DISPPLANE_BGRX565:
2058                 return DRM_FORMAT_RGB565;
2059         default:
2060         case DISPPLANE_BGRX888:
2061                 return DRM_FORMAT_XRGB8888;
2062         case DISPPLANE_RGBX888:
2063                 return DRM_FORMAT_XBGR8888;
2064         case DISPPLANE_BGRX101010:
2065                 return DRM_FORMAT_XRGB2101010;
2066         case DISPPLANE_RGBX101010:
2067                 return DRM_FORMAT_XBGR2101010;
2068         }
2069 }
2070 
2071 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2072                                   struct intel_plane_config *plane_config)
2073 {
2074         struct drm_device *dev = crtc->base.dev;
2075         struct drm_i915_gem_object *obj = NULL;
2076         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2077         u32 base = plane_config->base;
2078 
2079         if (plane_config->size == 0)
2080                 return false;
2081 
2082         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2083                                                              plane_config->size);
2084         if (!obj)
2085                 return false;
2086 
2087         if (plane_config->tiled) {
2088                 obj->tiling_mode = I915_TILING_X;
2089                 obj->stride = crtc->base.primary->fb->pitches[0];
2090         }
2091 
2092         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2093         mode_cmd.width = crtc->base.primary->fb->width;
2094         mode_cmd.height = crtc->base.primary->fb->height;
2095         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2096 
2097         mutex_lock(&dev->struct_mutex);
2098 
2099         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2100                                    &mode_cmd, obj)) {
2101                 DRM_DEBUG_KMS("intel fb init failed\n");
2102                 goto out_unref_obj;
2103         }
2104 
2105         mutex_unlock(&dev->struct_mutex);
2106 
2107         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2108         return true;
2109 
2110 out_unref_obj:
2111         drm_gem_object_unreference(&obj->base);
2112         mutex_unlock(&dev->struct_mutex);
2113         return false;
2114 }
2115 
2116 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2117                                  struct intel_plane_config *plane_config)
2118 {
2119         struct drm_device *dev = intel_crtc->base.dev;
2120         struct drm_crtc *c;
2121         struct intel_crtc *i;
2122         struct intel_framebuffer *fb;
2123 
2124         if (!intel_crtc->base.primary->fb)
2125                 return;
2126 
2127         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2128                 return;
2129 
2130         kfree(intel_crtc->base.primary->fb);
2131         intel_crtc->base.primary->fb = NULL;
2132 
2133         /*
2134          * Failed to alloc the obj, check to see if we should share
2135          * an fb with another CRTC instead
2136          */
2137         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2138                 i = to_intel_crtc(c);
2139 
2140                 if (c == &intel_crtc->base)
2141                         continue;
2142 
2143                 if (!i->active || !c->primary->fb)
2144                         continue;
2145 
2146                 fb = to_intel_framebuffer(c->primary->fb);
2147                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2148                         drm_framebuffer_reference(c->primary->fb);
2149                         intel_crtc->base.primary->fb = c->primary->fb;
2150                         break;
2151                 }
2152         }
2153 }
2154 
2155 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2156                                      struct drm_framebuffer *fb,
2157                                      int x, int y)
2158 {
2159         struct drm_device *dev = crtc->dev;
2160         struct drm_i915_private *dev_priv = dev->dev_private;
2161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162         struct intel_framebuffer *intel_fb;
2163         struct drm_i915_gem_object *obj;
2164         int plane = intel_crtc->plane;
2165         unsigned long linear_offset;
2166         u32 dspcntr;
2167         u32 reg;
2168 
2169         switch (plane) {
2170         case 0:
2171         case 1:
2172                 break;
2173         default:
2174                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2175                 return -EINVAL;
2176         }
2177 
2178         intel_fb = to_intel_framebuffer(fb);
2179         obj = intel_fb->obj;
2180 
2181         reg = DSPCNTR(plane);
2182         dspcntr = I915_READ(reg);
2183         /* Mask out pixel format bits in case we change it */
2184         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2185         switch (fb->pixel_format) {
2186         case DRM_FORMAT_C8:
2187                 dspcntr |= DISPPLANE_8BPP;
2188                 break;
2189         case DRM_FORMAT_XRGB1555:
2190         case DRM_FORMAT_ARGB1555:
2191                 dspcntr |= DISPPLANE_BGRX555;
2192                 break;
2193         case DRM_FORMAT_RGB565:
2194                 dspcntr |= DISPPLANE_BGRX565;
2195                 break;
2196         case DRM_FORMAT_XRGB8888:
2197         case DRM_FORMAT_ARGB8888:
2198                 dspcntr |= DISPPLANE_BGRX888;
2199                 break;
2200         case DRM_FORMAT_XBGR8888:
2201         case DRM_FORMAT_ABGR8888:
2202                 dspcntr |= DISPPLANE_RGBX888;
2203                 break;
2204         case DRM_FORMAT_XRGB2101010:
2205         case DRM_FORMAT_ARGB2101010:
2206                 dspcntr |= DISPPLANE_BGRX101010;
2207                 break;
2208         case DRM_FORMAT_XBGR2101010:
2209         case DRM_FORMAT_ABGR2101010:
2210                 dspcntr |= DISPPLANE_RGBX101010;
2211                 break;
2212         default:
2213                 BUG();
2214         }
2215 
2216         if (INTEL_INFO(dev)->gen >= 4) {
2217                 if (obj->tiling_mode != I915_TILING_NONE)
2218                         dspcntr |= DISPPLANE_TILED;
2219                 else
2220                         dspcntr &= ~DISPPLANE_TILED;
2221         }
2222 
2223         if (IS_G4X(dev))
2224                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2225 
2226         I915_WRITE(reg, dspcntr);
2227 
2228         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2229 
2230         if (INTEL_INFO(dev)->gen >= 4) {
2231                 intel_crtc->dspaddr_offset =
2232                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2233                                                        fb->bits_per_pixel / 8,
2234                                                        fb->pitches[0]);
2235                 linear_offset -= intel_crtc->dspaddr_offset;
2236         } else {
2237                 intel_crtc->dspaddr_offset = linear_offset;
2238         }
2239 
2240         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2241                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2242                       fb->pitches[0]);
2243         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2244         if (INTEL_INFO(dev)->gen >= 4) {
2245                 I915_WRITE(DSPSURF(plane),
2246                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2247                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2248                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2249         } else
2250                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2251         POSTING_READ(reg);
2252 
2253         return 0;
2254 }
2255 
2256 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2257                                          struct drm_framebuffer *fb,
2258                                          int x, int y)
2259 {
2260         struct drm_device *dev = crtc->dev;
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263         struct intel_framebuffer *intel_fb;
2264         struct drm_i915_gem_object *obj;
2265         int plane = intel_crtc->plane;
2266         unsigned long linear_offset;
2267         u32 dspcntr;
2268         u32 reg;
2269 
2270         switch (plane) {
2271         case 0:
2272         case 1:
2273         case 2:
2274                 break;
2275         default:
2276                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2277                 return -EINVAL;
2278         }
2279 
2280         intel_fb = to_intel_framebuffer(fb);
2281         obj = intel_fb->obj;
2282 
2283         reg = DSPCNTR(plane);
2284         dspcntr = I915_READ(reg);
2285         /* Mask out pixel format bits in case we change it */
2286         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2287         switch (fb->pixel_format) {
2288         case DRM_FORMAT_C8:
2289                 dspcntr |= DISPPLANE_8BPP;
2290                 break;
2291         case DRM_FORMAT_RGB565:
2292                 dspcntr |= DISPPLANE_BGRX565;
2293                 break;
2294         case DRM_FORMAT_XRGB8888:
2295         case DRM_FORMAT_ARGB8888:
2296                 dspcntr |= DISPPLANE_BGRX888;
2297                 break;
2298         case DRM_FORMAT_XBGR8888:
2299         case DRM_FORMAT_ABGR8888:
2300                 dspcntr |= DISPPLANE_RGBX888;
2301                 break;
2302         case DRM_FORMAT_XRGB2101010:
2303         case DRM_FORMAT_ARGB2101010:
2304                 dspcntr |= DISPPLANE_BGRX101010;
2305                 break;
2306         case DRM_FORMAT_XBGR2101010:
2307         case DRM_FORMAT_ABGR2101010:
2308                 dspcntr |= DISPPLANE_RGBX101010;
2309                 break;
2310         default:
2311                 BUG();
2312         }
2313 
2314         if (obj->tiling_mode != I915_TILING_NONE)
2315                 dspcntr |= DISPPLANE_TILED;
2316         else
2317                 dspcntr &= ~DISPPLANE_TILED;
2318 
2319         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2320                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2321         else
2322                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2323 
2324         I915_WRITE(reg, dspcntr);
2325 
2326         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327         intel_crtc->dspaddr_offset =
2328                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2329                                                fb->bits_per_pixel / 8,
2330                                                fb->pitches[0]);
2331         linear_offset -= intel_crtc->dspaddr_offset;
2332 
2333         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2334                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2335                       fb->pitches[0]);
2336         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2337         I915_WRITE(DSPSURF(plane),
2338                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2339         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2340                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2341         } else {
2342                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2343                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2344         }
2345         POSTING_READ(reg);
2346 
2347         return 0;
2348 }
2349 
2350 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2351 static int
2352 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2353                            int x, int y, enum mode_set_atomic state)
2354 {
2355         struct drm_device *dev = crtc->dev;
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357 
2358         if (dev_priv->display.disable_fbc)
2359                 dev_priv->display.disable_fbc(dev);
2360         intel_increase_pllclock(crtc);
2361 
2362         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2363 }
2364 
2365 void intel_display_handle_reset(struct drm_device *dev)
2366 {
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         struct drm_crtc *crtc;
2369 
2370         /*
2371          * Flips in the rings have been nuked by the reset,
2372          * so complete all pending flips so that user space
2373          * will get its events and not get stuck.
2374          *
2375          * Also update the base address of all primary
2376          * planes to the the last fb to make sure we're
2377          * showing the correct fb after a reset.
2378          *
2379          * Need to make two loops over the crtcs so that we
2380          * don't try to grab a crtc mutex before the
2381          * pending_flip_queue really got woken up.
2382          */
2383 
2384         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2385                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386                 enum plane plane = intel_crtc->plane;
2387 
2388                 intel_prepare_page_flip(dev, plane);
2389                 intel_finish_page_flip_plane(dev, plane);
2390         }
2391 
2392         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2393                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394 
2395                 mutex_lock(&crtc->mutex);
2396                 /*
2397                  * FIXME: Once we have proper support for primary planes (and
2398                  * disabling them without disabling the entire crtc) allow again
2399                  * a NULL crtc->primary->fb.
2400                  */
2401                 if (intel_crtc->active && crtc->primary->fb)
2402                         dev_priv->display.update_primary_plane(crtc,
2403                                                                crtc->primary->fb,
2404                                                                crtc->x,
2405                                                                crtc->y);
2406                 mutex_unlock(&crtc->mutex);
2407         }
2408 }
2409 
2410 static int
2411 intel_finish_fb(struct drm_framebuffer *old_fb)
2412 {
2413         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2414         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2415         bool was_interruptible = dev_priv->mm.interruptible;
2416         int ret;
2417 
2418         /* Big Hammer, we also need to ensure that any pending
2419          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2420          * current scanout is retired before unpinning the old
2421          * framebuffer.
2422          *
2423          * This should only fail upon a hung GPU, in which case we
2424          * can safely continue.
2425          */
2426         dev_priv->mm.interruptible = false;
2427         ret = i915_gem_object_finish_gpu(obj);
2428         dev_priv->mm.interruptible = was_interruptible;
2429 
2430         return ret;
2431 }
2432 
2433 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2434 {
2435         struct drm_device *dev = crtc->dev;
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2438         unsigned long flags;
2439         bool pending;
2440 
2441         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2442             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2443                 return false;
2444 
2445         spin_lock_irqsave(&dev->event_lock, flags);
2446         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2447         spin_unlock_irqrestore(&dev->event_lock, flags);
2448 
2449         return pending;
2450 }
2451 
2452 static int
2453 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2454                     struct drm_framebuffer *fb)
2455 {
2456         struct drm_device *dev = crtc->dev;
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2459         struct drm_framebuffer *old_fb;
2460         int ret;
2461 
2462         if (intel_crtc_has_pending_flip(crtc)) {
2463                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2464                 return -EBUSY;
2465         }
2466 
2467         /* no fb bound */
2468         if (!fb) {
2469                 DRM_ERROR("No FB bound\n");
2470                 return 0;
2471         }
2472 
2473         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2474                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2475                           plane_name(intel_crtc->plane),
2476                           INTEL_INFO(dev)->num_pipes);
2477                 return -EINVAL;
2478         }
2479 
2480         mutex_lock(&dev->struct_mutex);
2481         ret = intel_pin_and_fence_fb_obj(dev,
2482                                          to_intel_framebuffer(fb)->obj,
2483                                          NULL);
2484         mutex_unlock(&dev->struct_mutex);
2485         if (ret != 0) {
2486                 DRM_ERROR("pin & fence failed\n");
2487                 return ret;
2488         }
2489 
2490         /*
2491          * Update pipe size and adjust fitter if needed: the reason for this is
2492          * that in compute_mode_changes we check the native mode (not the pfit
2493          * mode) to see if we can flip rather than do a full mode set. In the
2494          * fastboot case, we'll flip, but if we don't update the pipesrc and
2495          * pfit state, we'll end up with a big fb scanned out into the wrong
2496          * sized surface.
2497          *
2498          * To fix this properly, we need to hoist the checks up into
2499          * compute_mode_changes (or above), check the actual pfit state and
2500          * whether the platform allows pfit disable with pipe active, and only
2501          * then update the pipesrc and pfit state, even on the flip path.
2502          */
2503         if (i915.fastboot) {
2504                 const struct drm_display_mode *adjusted_mode =
2505                         &intel_crtc->config.adjusted_mode;
2506 
2507                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2508                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2509                            (adjusted_mode->crtc_vdisplay - 1));
2510                 if (!intel_crtc->config.pch_pfit.enabled &&
2511                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2512                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2513                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2514                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2515                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2516                 }
2517                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2518                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2519         }
2520 
2521         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522         if (ret) {
2523                 mutex_lock(&dev->struct_mutex);
2524                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2525                 mutex_unlock(&dev->struct_mutex);
2526                 DRM_ERROR("failed to update base address\n");
2527                 return ret;
2528         }
2529 
2530         old_fb = crtc->primary->fb;
2531         crtc->primary->fb = fb;
2532         crtc->x = x;
2533         crtc->y = y;
2534 
2535         if (old_fb) {
2536                 if (intel_crtc->active && old_fb != fb)
2537                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2538                 mutex_lock(&dev->struct_mutex);
2539                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2540                 mutex_unlock(&dev->struct_mutex);
2541         }
2542 
2543         mutex_lock(&dev->struct_mutex);
2544         intel_update_fbc(dev);
2545         intel_edp_psr_update(dev);
2546         mutex_unlock(&dev->struct_mutex);
2547 
2548         return 0;
2549 }
2550 
2551 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2552 {
2553         struct drm_device *dev = crtc->dev;
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556         int pipe = intel_crtc->pipe;
2557         u32 reg, temp;
2558 
2559         /* enable normal train */
2560         reg = FDI_TX_CTL(pipe);
2561         temp = I915_READ(reg);
2562         if (IS_IVYBRIDGE(dev)) {
2563                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2564                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2565         } else {
2566                 temp &= ~FDI_LINK_TRAIN_NONE;
2567                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2568         }
2569         I915_WRITE(reg, temp);
2570 
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         if (HAS_PCH_CPT(dev)) {
2574                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2576         } else {
2577                 temp &= ~FDI_LINK_TRAIN_NONE;
2578                 temp |= FDI_LINK_TRAIN_NONE;
2579         }
2580         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2581 
2582         /* wait one idle pattern time */
2583         POSTING_READ(reg);
2584         udelay(1000);
2585 
2586         /* IVB wants error correction enabled */
2587         if (IS_IVYBRIDGE(dev))
2588                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2589                            FDI_FE_ERRC_ENABLE);
2590 }
2591 
2592 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2593 {
2594         return crtc->base.enabled && crtc->active &&
2595                 crtc->config.has_pch_encoder;
2596 }
2597 
2598 static void ivb_modeset_global_resources(struct drm_device *dev)
2599 {
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_crtc *pipe_B_crtc =
2602                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2603         struct intel_crtc *pipe_C_crtc =
2604                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2605         uint32_t temp;
2606 
2607         /*
2608          * When everything is off disable fdi C so that we could enable fdi B
2609          * with all lanes. Note that we don't care about enabled pipes without
2610          * an enabled pch encoder.
2611          */
2612         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2613             !pipe_has_enabled_pch(pipe_C_crtc)) {
2614                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2615                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2616 
2617                 temp = I915_READ(SOUTH_CHICKEN1);
2618                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2619                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2620                 I915_WRITE(SOUTH_CHICKEN1, temp);
2621         }
2622 }
2623 
2624 /* The FDI link training functions for ILK/Ibexpeak. */
2625 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2626 {
2627         struct drm_device *dev = crtc->dev;
2628         struct drm_i915_private *dev_priv = dev->dev_private;
2629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2630         int pipe = intel_crtc->pipe;
2631         int plane = intel_crtc->plane;
2632         u32 reg, temp, tries;
2633 
2634         /* FDI needs bits from pipe & plane first */
2635         assert_pipe_enabled(dev_priv, pipe);
2636         assert_plane_enabled(dev_priv, plane);
2637 
2638         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639            for train result */
2640         reg = FDI_RX_IMR(pipe);
2641         temp = I915_READ(reg);
2642         temp &= ~FDI_RX_SYMBOL_LOCK;
2643         temp &= ~FDI_RX_BIT_LOCK;
2644         I915_WRITE(reg, temp);
2645         I915_READ(reg);
2646         udelay(150);
2647 
2648         /* enable CPU FDI TX and PCH FDI RX */
2649         reg = FDI_TX_CTL(pipe);
2650         temp = I915_READ(reg);
2651         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2652         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2653         temp &= ~FDI_LINK_TRAIN_NONE;
2654         temp |= FDI_LINK_TRAIN_PATTERN_1;
2655         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2656 
2657         reg = FDI_RX_CTL(pipe);
2658         temp = I915_READ(reg);
2659         temp &= ~FDI_LINK_TRAIN_NONE;
2660         temp |= FDI_LINK_TRAIN_PATTERN_1;
2661         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2662 
2663         POSTING_READ(reg);
2664         udelay(150);
2665 
2666         /* Ironlake workaround, enable clock pointer after FDI enable*/
2667         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2668         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2669                    FDI_RX_PHASE_SYNC_POINTER_EN);
2670 
2671         reg = FDI_RX_IIR(pipe);
2672         for (tries = 0; tries < 5; tries++) {
2673                 temp = I915_READ(reg);
2674                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675 
2676                 if ((temp & FDI_RX_BIT_LOCK)) {
2677                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2678                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2679                         break;
2680                 }
2681         }
2682         if (tries == 5)
2683                 DRM_ERROR("FDI train 1 fail!\n");
2684 
2685         /* Train 2 */
2686         reg = FDI_TX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_LINK_TRAIN_NONE;
2689         temp |= FDI_LINK_TRAIN_PATTERN_2;
2690         I915_WRITE(reg, temp);
2691 
2692         reg = FDI_RX_CTL(pipe);
2693         temp = I915_READ(reg);
2694         temp &= ~FDI_LINK_TRAIN_NONE;
2695         temp |= FDI_LINK_TRAIN_PATTERN_2;
2696         I915_WRITE(reg, temp);
2697 
2698         POSTING_READ(reg);
2699         udelay(150);
2700 
2701         reg = FDI_RX_IIR(pipe);
2702         for (tries = 0; tries < 5; tries++) {
2703                 temp = I915_READ(reg);
2704                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705 
2706                 if (temp & FDI_RX_SYMBOL_LOCK) {
2707                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2709                         break;
2710                 }
2711         }
2712         if (tries == 5)
2713                 DRM_ERROR("FDI train 2 fail!\n");
2714 
2715         DRM_DEBUG_KMS("FDI train done\n");
2716 
2717 }
2718 
2719 static const int snb_b_fdi_train_param[] = {
2720         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2721         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2722         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2723         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2724 };
2725 
2726 /* The FDI link training functions for SNB/Cougarpoint. */
2727 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2728 {
2729         struct drm_device *dev = crtc->dev;
2730         struct drm_i915_private *dev_priv = dev->dev_private;
2731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2732         int pipe = intel_crtc->pipe;
2733         u32 reg, temp, i, retry;
2734 
2735         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2736            for train result */
2737         reg = FDI_RX_IMR(pipe);
2738         temp = I915_READ(reg);
2739         temp &= ~FDI_RX_SYMBOL_LOCK;
2740         temp &= ~FDI_RX_BIT_LOCK;
2741         I915_WRITE(reg, temp);
2742 
2743         POSTING_READ(reg);
2744         udelay(150);
2745 
2746         /* enable CPU FDI TX and PCH FDI RX */
2747         reg = FDI_TX_CTL(pipe);
2748         temp = I915_READ(reg);
2749         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2750         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2751         temp &= ~FDI_LINK_TRAIN_NONE;
2752         temp |= FDI_LINK_TRAIN_PATTERN_1;
2753         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2754         /* SNB-B */
2755         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2756         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2757 
2758         I915_WRITE(FDI_RX_MISC(pipe),
2759                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2760 
2761         reg = FDI_RX_CTL(pipe);
2762         temp = I915_READ(reg);
2763         if (HAS_PCH_CPT(dev)) {
2764                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2765                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2766         } else {
2767                 temp &= ~FDI_LINK_TRAIN_NONE;
2768                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2769         }
2770         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2771 
2772         POSTING_READ(reg);
2773         udelay(150);
2774 
2775         for (i = 0; i < 4; i++) {
2776                 reg = FDI_TX_CTL(pipe);
2777                 temp = I915_READ(reg);
2778                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779                 temp |= snb_b_fdi_train_param[i];
2780                 I915_WRITE(reg, temp);
2781 
2782                 POSTING_READ(reg);
2783                 udelay(500);
2784 
2785                 for (retry = 0; retry < 5; retry++) {
2786                         reg = FDI_RX_IIR(pipe);
2787                         temp = I915_READ(reg);
2788                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789                         if (temp & FDI_RX_BIT_LOCK) {
2790                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2792                                 break;
2793                         }
2794                         udelay(50);
2795                 }
2796                 if (retry < 5)
2797                         break;
2798         }
2799         if (i == 4)
2800                 DRM_ERROR("FDI train 1 fail!\n");
2801 
2802         /* Train 2 */
2803         reg = FDI_TX_CTL(pipe);
2804         temp = I915_READ(reg);
2805         temp &= ~FDI_LINK_TRAIN_NONE;
2806         temp |= FDI_LINK_TRAIN_PATTERN_2;
2807         if (IS_GEN6(dev)) {
2808                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2809                 /* SNB-B */
2810                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2811         }
2812         I915_WRITE(reg, temp);
2813 
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         if (HAS_PCH_CPT(dev)) {
2817                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2818                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2819         } else {
2820                 temp &= ~FDI_LINK_TRAIN_NONE;
2821                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2822         }
2823         I915_WRITE(reg, temp);
2824 
2825         POSTING_READ(reg);
2826         udelay(150);
2827 
2828         for (i = 0; i < 4; i++) {
2829                 reg = FDI_TX_CTL(pipe);
2830                 temp = I915_READ(reg);
2831                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2832                 temp |= snb_b_fdi_train_param[i];
2833                 I915_WRITE(reg, temp);
2834 
2835                 POSTING_READ(reg);
2836                 udelay(500);
2837 
2838                 for (retry = 0; retry < 5; retry++) {
2839                         reg = FDI_RX_IIR(pipe);
2840                         temp = I915_READ(reg);
2841                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2842                         if (temp & FDI_RX_SYMBOL_LOCK) {
2843                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2844                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2845                                 break;
2846                         }
2847                         udelay(50);
2848                 }
2849                 if (retry < 5)
2850                         break;
2851         }
2852         if (i == 4)
2853                 DRM_ERROR("FDI train 2 fail!\n");
2854 
2855         DRM_DEBUG_KMS("FDI train done.\n");
2856 }
2857 
2858 /* Manual link training for Ivy Bridge A0 parts */
2859 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2860 {
2861         struct drm_device *dev = crtc->dev;
2862         struct drm_i915_private *dev_priv = dev->dev_private;
2863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864         int pipe = intel_crtc->pipe;
2865         u32 reg, temp, i, j;
2866 
2867         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2868            for train result */
2869         reg = FDI_RX_IMR(pipe);
2870         temp = I915_READ(reg);
2871         temp &= ~FDI_RX_SYMBOL_LOCK;
2872         temp &= ~FDI_RX_BIT_LOCK;
2873         I915_WRITE(reg, temp);
2874 
2875         POSTING_READ(reg);
2876         udelay(150);
2877 
2878         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2879                       I915_READ(FDI_RX_IIR(pipe)));
2880 
2881         /* Try each vswing and preemphasis setting twice before moving on */
2882         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2883                 /* disable first in case we need to retry */
2884                 reg = FDI_TX_CTL(pipe);
2885                 temp = I915_READ(reg);
2886                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2887                 temp &= ~FDI_TX_ENABLE;
2888                 I915_WRITE(reg, temp);
2889 
2890                 reg = FDI_RX_CTL(pipe);
2891                 temp = I915_READ(reg);
2892                 temp &= ~FDI_LINK_TRAIN_AUTO;
2893                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2894                 temp &= ~FDI_RX_ENABLE;
2895                 I915_WRITE(reg, temp);
2896 
2897                 /* enable CPU FDI TX and PCH FDI RX */
2898                 reg = FDI_TX_CTL(pipe);
2899                 temp = I915_READ(reg);
2900                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2901                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2902                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2903                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2904                 temp |= snb_b_fdi_train_param[j/2];
2905                 temp |= FDI_COMPOSITE_SYNC;
2906                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2907 
2908                 I915_WRITE(FDI_RX_MISC(pipe),
2909                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2910 
2911                 reg = FDI_RX_CTL(pipe);
2912                 temp = I915_READ(reg);
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914                 temp |= FDI_COMPOSITE_SYNC;
2915                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2916 
2917                 POSTING_READ(reg);
2918                 udelay(1); /* should be 0.5us */
2919 
2920                 for (i = 0; i < 4; i++) {
2921                         reg = FDI_RX_IIR(pipe);
2922                         temp = I915_READ(reg);
2923                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2924 
2925                         if (temp & FDI_RX_BIT_LOCK ||
2926                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2927                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2928                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2929                                               i);
2930                                 break;
2931                         }
2932                         udelay(1); /* should be 0.5us */
2933                 }
2934                 if (i == 4) {
2935                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2936                         continue;
2937                 }
2938 
2939                 /* Train 2 */
2940                 reg = FDI_TX_CTL(pipe);
2941                 temp = I915_READ(reg);
2942                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2943                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2944                 I915_WRITE(reg, temp);
2945 
2946                 reg = FDI_RX_CTL(pipe);
2947                 temp = I915_READ(reg);
2948                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2950                 I915_WRITE(reg, temp);
2951 
2952                 POSTING_READ(reg);
2953                 udelay(2); /* should be 1.5us */
2954 
2955                 for (i = 0; i < 4; i++) {
2956                         reg = FDI_RX_IIR(pipe);
2957                         temp = I915_READ(reg);
2958                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2959 
2960                         if (temp & FDI_RX_SYMBOL_LOCK ||
2961                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2962                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2963                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2964                                               i);
2965                                 goto train_done;
2966                         }
2967                         udelay(2); /* should be 1.5us */
2968                 }
2969                 if (i == 4)
2970                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2971         }
2972 
2973 train_done:
2974         DRM_DEBUG_KMS("FDI train done.\n");
2975 }
2976 
2977 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2978 {
2979         struct drm_device *dev = intel_crtc->base.dev;
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         int pipe = intel_crtc->pipe;
2982         u32 reg, temp;
2983 
2984 
2985         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2986         reg = FDI_RX_CTL(pipe);
2987         temp = I915_READ(reg);
2988         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2989         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2990         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2991         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2992 
2993         POSTING_READ(reg);
2994         udelay(200);
2995 
2996         /* Switch from Rawclk to PCDclk */
2997         temp = I915_READ(reg);
2998         I915_WRITE(reg, temp | FDI_PCDCLK);
2999 
3000         POSTING_READ(reg);
3001         udelay(200);
3002 
3003         /* Enable CPU FDI TX PLL, always on for Ironlake */
3004         reg = FDI_TX_CTL(pipe);
3005         temp = I915_READ(reg);
3006         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3007                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3008 
3009                 POSTING_READ(reg);
3010                 udelay(100);
3011         }
3012 }
3013 
3014 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3015 {
3016         struct drm_device *dev = intel_crtc->base.dev;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         int pipe = intel_crtc->pipe;
3019         u32 reg, temp;
3020 
3021         /* Switch from PCDclk to Rawclk */
3022         reg = FDI_RX_CTL(pipe);
3023         temp = I915_READ(reg);
3024         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3025 
3026         /* Disable CPU FDI TX PLL */
3027         reg = FDI_TX_CTL(pipe);
3028         temp = I915_READ(reg);
3029         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3030 
3031         POSTING_READ(reg);
3032         udelay(100);
3033 
3034         reg = FDI_RX_CTL(pipe);
3035         temp = I915_READ(reg);
3036         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3037 
3038         /* Wait for the clocks to turn off. */
3039         POSTING_READ(reg);
3040         udelay(100);
3041 }
3042 
3043 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3044 {
3045         struct drm_device *dev = crtc->dev;
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048         int pipe = intel_crtc->pipe;
3049         u32 reg, temp;
3050 
3051         /* disable CPU FDI tx and PCH FDI rx */
3052         reg = FDI_TX_CTL(pipe);
3053         temp = I915_READ(reg);
3054         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3055         POSTING_READ(reg);
3056 
3057         reg = FDI_RX_CTL(pipe);
3058         temp = I915_READ(reg);
3059         temp &= ~(0x7 << 16);
3060         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3061         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3062 
3063         POSTING_READ(reg);
3064         udelay(100);
3065 
3066         /* Ironlake workaround, disable clock pointer after downing FDI */
3067         if (HAS_PCH_IBX(dev)) {
3068                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3069         }
3070 
3071         /* still set train pattern 1 */
3072         reg = FDI_TX_CTL(pipe);
3073         temp = I915_READ(reg);
3074         temp &= ~FDI_LINK_TRAIN_NONE;
3075         temp |= FDI_LINK_TRAIN_PATTERN_1;
3076         I915_WRITE(reg, temp);
3077 
3078         reg = FDI_RX_CTL(pipe);
3079         temp = I915_READ(reg);
3080         if (HAS_PCH_CPT(dev)) {
3081                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3082                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3083         } else {
3084                 temp &= ~FDI_LINK_TRAIN_NONE;
3085                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3086         }
3087         /* BPC in FDI rx is consistent with that in PIPECONF */
3088         temp &= ~(0x07 << 16);
3089         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3090         I915_WRITE(reg, temp);
3091 
3092         POSTING_READ(reg);
3093         udelay(100);
3094 }
3095 
3096 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3097 {
3098         struct intel_crtc *crtc;
3099 
3100         /* Note that we don't need to be called with mode_config.lock here
3101          * as our list of CRTC objects is static for the lifetime of the
3102          * device and so cannot disappear as we iterate. Similarly, we can
3103          * happily treat the predicates as racy, atomic checks as userspace
3104          * cannot claim and pin a new fb without at least acquring the
3105          * struct_mutex and so serialising with us.
3106          */
3107         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3108                 if (atomic_read(&crtc->unpin_work_count) == 0)
3109                         continue;
3110 
3111                 if (crtc->unpin_work)
3112                         intel_wait_for_vblank(dev, crtc->pipe);
3113 
3114                 return true;
3115         }
3116 
3117         return false;
3118 }
3119 
3120 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124 
3125         if (crtc->primary->fb == NULL)
3126                 return;
3127 
3128         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3129 
3130         wait_event(dev_priv->pending_flip_queue,
3131                    !intel_crtc_has_pending_flip(crtc));
3132 
3133         mutex_lock(&dev->struct_mutex);
3134         intel_finish_fb(crtc->primary->fb);
3135         mutex_unlock(&dev->struct_mutex);
3136 }
3137 
3138 /* Program iCLKIP clock to the desired frequency */
3139 static void lpt_program_iclkip(struct drm_crtc *crtc)
3140 {
3141         struct drm_device *dev = crtc->dev;
3142         struct drm_i915_private *dev_priv = dev->dev_private;
3143         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3144         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3145         u32 temp;
3146 
3147         mutex_lock(&dev_priv->dpio_lock);
3148 
3149         /* It is necessary to ungate the pixclk gate prior to programming
3150          * the divisors, and gate it back when it is done.
3151          */
3152         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3153 
3154         /* Disable SSCCTL */
3155         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3156                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3157                                 SBI_SSCCTL_DISABLE,
3158                         SBI_ICLK);
3159 
3160         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3161         if (clock == 20000) {
3162                 auxdiv = 1;
3163                 divsel = 0x41;
3164                 phaseinc = 0x20;
3165         } else {
3166                 /* The iCLK virtual clock root frequency is in MHz,
3167                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3168                  * divisors, it is necessary to divide one by another, so we
3169                  * convert the virtual clock precision to KHz here for higher
3170                  * precision.
3171                  */
3172                 u32 iclk_virtual_root_freq = 172800 * 1000;
3173                 u32 iclk_pi_range = 64;
3174                 u32 desired_divisor, msb_divisor_value, pi_value;
3175 
3176                 desired_divisor = (iclk_virtual_root_freq / clock);
3177                 msb_divisor_value = desired_divisor / iclk_pi_range;
3178                 pi_value = desired_divisor % iclk_pi_range;
3179 
3180                 auxdiv = 0;
3181                 divsel = msb_divisor_value - 2;
3182                 phaseinc = pi_value;
3183         }
3184 
3185         /* This should not happen with any sane values */
3186         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3187                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3188         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3189                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3190 
3191         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3192                         clock,
3193                         auxdiv,
3194                         divsel,
3195                         phasedir,
3196                         phaseinc);
3197 
3198         /* Program SSCDIVINTPHASE6 */
3199         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3200         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3201         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3202         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3203         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3204         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3205         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3206         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3207 
3208         /* Program SSCAUXDIV */
3209         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3210         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3211         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3212         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3213 
3214         /* Enable modulator and associated divider */
3215         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3216         temp &= ~SBI_SSCCTL_DISABLE;
3217         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3218 
3219         /* Wait for initialization time */
3220         udelay(24);
3221 
3222         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3223 
3224         mutex_unlock(&dev_priv->dpio_lock);
3225 }
3226 
3227 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3228                                                 enum pipe pch_transcoder)
3229 {
3230         struct drm_device *dev = crtc->base.dev;
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3233 
3234         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3235                    I915_READ(HTOTAL(cpu_transcoder)));
3236         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3237                    I915_READ(HBLANK(cpu_transcoder)));
3238         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3239                    I915_READ(HSYNC(cpu_transcoder)));
3240 
3241         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3242                    I915_READ(VTOTAL(cpu_transcoder)));
3243         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3244                    I915_READ(VBLANK(cpu_transcoder)));
3245         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3246                    I915_READ(VSYNC(cpu_transcoder)));
3247         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3248                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3249 }
3250 
3251 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3252 {
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         uint32_t temp;
3255 
3256         temp = I915_READ(SOUTH_CHICKEN1);
3257         if (temp & FDI_BC_BIFURCATION_SELECT)
3258                 return;
3259 
3260         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3261         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3262 
3263         temp |= FDI_BC_BIFURCATION_SELECT;
3264         DRM_DEBUG_KMS("enabling fdi C rx\n");
3265         I915_WRITE(SOUTH_CHICKEN1, temp);
3266         POSTING_READ(SOUTH_CHICKEN1);
3267 }
3268 
3269 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3270 {
3271         struct drm_device *dev = intel_crtc->base.dev;
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273 
3274         switch (intel_crtc->pipe) {
3275         case PIPE_A:
3276                 break;
3277         case PIPE_B:
3278                 if (intel_crtc->config.fdi_lanes > 2)
3279                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3280                 else
3281                         cpt_enable_fdi_bc_bifurcation(dev);
3282 
3283                 break;
3284         case PIPE_C:
3285                 cpt_enable_fdi_bc_bifurcation(dev);
3286 
3287                 break;
3288         default:
3289                 BUG();
3290         }
3291 }
3292 
3293 /*
3294  * Enable PCH resources required for PCH ports:
3295  *   - PCH PLLs
3296  *   - FDI training & RX/TX
3297  *   - update transcoder timings
3298  *   - DP transcoding bits
3299  *   - transcoder
3300  */
3301 static void ironlake_pch_enable(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         int pipe = intel_crtc->pipe;
3307         u32 reg, temp;
3308 
3309         assert_pch_transcoder_disabled(dev_priv, pipe);
3310 
3311         if (IS_IVYBRIDGE(dev))
3312                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3313 
3314         /* Write the TU size bits before fdi link training, so that error
3315          * detection works. */
3316         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3317                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3318 
3319         /* For PCH output, training FDI link */
3320         dev_priv->display.fdi_link_train(crtc);
3321 
3322         /* We need to program the right clock selection before writing the pixel
3323          * mutliplier into the DPLL. */
3324         if (HAS_PCH_CPT(dev)) {
3325                 u32 sel;
3326 
3327                 temp = I915_READ(PCH_DPLL_SEL);
3328                 temp |= TRANS_DPLL_ENABLE(pipe);
3329                 sel = TRANS_DPLLB_SEL(pipe);
3330                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3331                         temp |= sel;
3332                 else
3333                         temp &= ~sel;
3334                 I915_WRITE(PCH_DPLL_SEL, temp);
3335         }
3336 
3337         /* XXX: pch pll's can be enabled any time before we enable the PCH
3338          * transcoder, and we actually should do this to not upset any PCH
3339          * transcoder that already use the clock when we share it.
3340          *
3341          * Note that enable_shared_dpll tries to do the right thing, but
3342          * get_shared_dpll unconditionally resets the pll - we need that to have
3343          * the right LVDS enable sequence. */
3344         ironlake_enable_shared_dpll(intel_crtc);
3345 
3346         /* set transcoder timing, panel must allow it */
3347         assert_panel_unlocked(dev_priv, pipe);
3348         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3349 
3350         intel_fdi_normal_train(crtc);
3351 
3352         /* For PCH DP, enable TRANS_DP_CTL */
3353         if (HAS_PCH_CPT(dev) &&
3354             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3355              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3356                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3357                 reg = TRANS_DP_CTL(pipe);
3358                 temp = I915_READ(reg);
3359                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3360                           TRANS_DP_SYNC_MASK |
3361                           TRANS_DP_BPC_MASK);
3362                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3363                          TRANS_DP_ENH_FRAMING);
3364                 temp |= bpc << 9; /* same format but at 11:9 */
3365 
3366                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3367                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3368                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3369                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3370 
3371                 switch (intel_trans_dp_port_sel(crtc)) {
3372                 case PCH_DP_B:
3373                         temp |= TRANS_DP_PORT_SEL_B;
3374                         break;
3375                 case PCH_DP_C:
3376                         temp |= TRANS_DP_PORT_SEL_C;
3377                         break;
3378                 case PCH_DP_D:
3379                         temp |= TRANS_DP_PORT_SEL_D;
3380                         break;
3381                 default:
3382                         BUG();
3383                 }
3384 
3385                 I915_WRITE(reg, temp);
3386         }
3387 
3388         ironlake_enable_pch_transcoder(dev_priv, pipe);
3389 }
3390 
3391 static void lpt_pch_enable(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3397 
3398         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3399 
3400         lpt_program_iclkip(crtc);
3401 
3402         /* Set transcoder timing. */
3403         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3404 
3405         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3406 }
3407 
3408 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3409 {
3410         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3411 
3412         if (pll == NULL)
3413                 return;
3414 
3415         if (pll->refcount == 0) {
3416                 WARN(1, "bad %s refcount\n", pll->name);
3417                 return;
3418         }
3419 
3420         if (--pll->refcount == 0) {
3421                 WARN_ON(pll->on);
3422                 WARN_ON(pll->active);
3423         }
3424 
3425         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3426 }
3427 
3428 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3429 {
3430         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3431         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3432         enum intel_dpll_id i;
3433 
3434         if (pll) {
3435                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3436                               crtc->base.base.id, pll->name);
3437                 intel_put_shared_dpll(crtc);
3438         }
3439 
3440         if (HAS_PCH_IBX(dev_priv->dev)) {
3441                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3442                 i = (enum intel_dpll_id) crtc->pipe;
3443                 pll = &dev_priv->shared_dplls[i];
3444 
3445                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3446                               crtc->base.base.id, pll->name);
3447 
3448                 goto found;
3449         }
3450 
3451         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3452                 pll = &dev_priv->shared_dplls[i];
3453 
3454                 /* Only want to check enabled timings first */
3455                 if (pll->refcount == 0)
3456                         continue;
3457 
3458                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3459                            sizeof(pll->hw_state)) == 0) {
3460                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3461                                       crtc->base.base.id,
3462                                       pll->name, pll->refcount, pll->active);
3463 
3464                         goto found;
3465                 }
3466         }
3467 
3468         /* Ok no matching timings, maybe there's a free one? */
3469         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3470                 pll = &dev_priv->shared_dplls[i];
3471                 if (pll->refcount == 0) {
3472                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3473                                       crtc->base.base.id, pll->name);
3474                         goto found;
3475                 }
3476         }
3477 
3478         return NULL;
3479 
3480 found:
3481         crtc->config.shared_dpll = i;
3482         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3483                          pipe_name(crtc->pipe));
3484 
3485         if (pll->active == 0) {
3486                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3487                        sizeof(pll->hw_state));
3488 
3489                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3490                 WARN_ON(pll->on);
3491                 assert_shared_dpll_disabled(dev_priv, pll);
3492 
3493                 pll->mode_set(dev_priv, pll);
3494         }
3495         pll->refcount++;
3496 
3497         return pll;
3498 }
3499 
3500 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3501 {
3502         struct drm_i915_private *dev_priv = dev->dev_private;
3503         int dslreg = PIPEDSL(pipe);
3504         u32 temp;
3505 
3506         temp = I915_READ(dslreg);
3507         udelay(500);
3508         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3509                 if (wait_for(I915_READ(dslreg) != temp, 5))
3510                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3511         }
3512 }
3513 
3514 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->base.dev;
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518         int pipe = crtc->pipe;
3519 
3520         if (crtc->config.pch_pfit.enabled) {
3521                 /* Force use of hard-coded filter coefficients
3522                  * as some pre-programmed values are broken,
3523                  * e.g. x201.
3524                  */
3525                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3526                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3527                                                  PF_PIPE_SEL_IVB(pipe));
3528                 else
3529                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3530                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3531                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3532         }
3533 }
3534 
3535 static void intel_enable_planes(struct drm_crtc *crtc)
3536 {
3537         struct drm_device *dev = crtc->dev;
3538         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3539         struct drm_plane *plane;
3540         struct intel_plane *intel_plane;
3541 
3542         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3543                 intel_plane = to_intel_plane(plane);
3544                 if (intel_plane->pipe == pipe)
3545                         intel_plane_restore(&intel_plane->base);
3546         }
3547 }
3548 
3549 static void intel_disable_planes(struct drm_crtc *crtc)
3550 {
3551         struct drm_device *dev = crtc->dev;
3552         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3553         struct drm_plane *plane;
3554         struct intel_plane *intel_plane;
3555 
3556         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3557                 intel_plane = to_intel_plane(plane);
3558                 if (intel_plane->pipe == pipe)
3559                         intel_plane_disable(&intel_plane->base);
3560         }
3561 }
3562 
3563 void hsw_enable_ips(struct intel_crtc *crtc)
3564 {
3565         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3566 
3567         if (!crtc->config.ips_enabled)
3568                 return;
3569 
3570         /* We can only enable IPS after we enable a plane and wait for a vblank.
3571          * We guarantee that the plane is enabled by calling intel_enable_ips
3572          * only after intel_enable_plane. And intel_enable_plane already waits
3573          * for a vblank, so all we need to do here is to enable the IPS bit. */
3574         assert_plane_enabled(dev_priv, crtc->plane);
3575         if (IS_BROADWELL(crtc->base.dev)) {
3576                 mutex_lock(&dev_priv->rps.hw_lock);
3577                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3578                 mutex_unlock(&dev_priv->rps.hw_lock);
3579                 /* Quoting Art Runyan: "its not safe to expect any particular
3580                  * value in IPS_CTL bit 31 after enabling IPS through the
3581                  * mailbox." Moreover, the mailbox may return a bogus state,
3582                  * so we need to just enable it and continue on.
3583                  */
3584         } else {
3585                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3586                 /* The bit only becomes 1 in the next vblank, so this wait here
3587                  * is essentially intel_wait_for_vblank. If we don't have this
3588                  * and don't wait for vblanks until the end of crtc_enable, then
3589                  * the HW state readout code will complain that the expected
3590                  * IPS_CTL value is not the one we read. */
3591                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3592                         DRM_ERROR("Timed out waiting for IPS enable\n");
3593         }
3594 }
3595 
3596 void hsw_disable_ips(struct intel_crtc *crtc)
3597 {
3598         struct drm_device *dev = crtc->base.dev;
3599         struct drm_i915_private *dev_priv = dev->dev_private;
3600 
3601         if (!crtc->config.ips_enabled)
3602                 return;
3603 
3604         assert_plane_enabled(dev_priv, crtc->plane);
3605         if (IS_BROADWELL(crtc->base.dev)) {
3606                 mutex_lock(&dev_priv->rps.hw_lock);
3607                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3608                 mutex_unlock(&dev_priv->rps.hw_lock);
3609         } else {
3610                 I915_WRITE(IPS_CTL, 0);
3611                 POSTING_READ(IPS_CTL);
3612         }
3613 
3614         /* We need to wait for a vblank before we can disable the plane. */
3615         intel_wait_for_vblank(dev, crtc->pipe);
3616 }
3617 
3618 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3619 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3620 {
3621         struct drm_device *dev = crtc->dev;
3622         struct drm_i915_private *dev_priv = dev->dev_private;
3623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624         enum pipe pipe = intel_crtc->pipe;
3625         int palreg = PALETTE(pipe);
3626         int i;
3627         bool reenable_ips = false;
3628 
3629         /* The clocks have to be on to load the palette. */
3630         if (!crtc->enabled || !intel_crtc->active)
3631                 return;
3632 
3633         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3634                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3635                         assert_dsi_pll_enabled(dev_priv);
3636                 else
3637                         assert_pll_enabled(dev_priv, pipe);
3638         }
3639 
3640         /* use legacy palette for Ironlake */
3641         if (HAS_PCH_SPLIT(dev))
3642                 palreg = LGC_PALETTE(pipe);
3643 
3644         /* Workaround : Do not read or write the pipe palette/gamma data while
3645          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3646          */
3647         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3648             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3649              GAMMA_MODE_MODE_SPLIT)) {
3650                 hsw_disable_ips(intel_crtc);
3651                 reenable_ips = true;
3652         }
3653 
3654         for (i = 0; i < 256; i++) {
3655                 I915_WRITE(palreg + 4 * i,
3656                            (intel_crtc->lut_r[i] << 16) |
3657                            (intel_crtc->lut_g[i] << 8) |
3658                            intel_crtc->lut_b[i]);
3659         }
3660 
3661         if (reenable_ips)
3662                 hsw_enable_ips(intel_crtc);
3663 }
3664 
3665 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3666 {
3667         struct drm_device *dev = crtc->dev;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670         struct intel_encoder *encoder;
3671         int pipe = intel_crtc->pipe;
3672         int plane = intel_crtc->plane;
3673 
3674         WARN_ON(!crtc->enabled);
3675 
3676         if (intel_crtc->active)
3677                 return;
3678 
3679         intel_crtc->active = true;
3680 
3681         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3682         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3683 
3684         for_each_encoder_on_crtc(dev, crtc, encoder)
3685                 if (encoder->pre_enable)
3686                         encoder->pre_enable(encoder);
3687 
3688         if (intel_crtc->config.has_pch_encoder) {
3689                 /* Note: FDI PLL enabling _must_ be done before we enable the
3690                  * cpu pipes, hence this is separate from all the other fdi/pch
3691                  * enabling. */
3692                 ironlake_fdi_pll_enable(intel_crtc);
3693         } else {
3694                 assert_fdi_tx_disabled(dev_priv, pipe);
3695                 assert_fdi_rx_disabled(dev_priv, pipe);
3696         }
3697 
3698         ironlake_pfit_enable(intel_crtc);
3699 
3700         /*
3701          * On ILK+ LUT must be loaded before the pipe is running but with
3702          * clocks enabled
3703          */
3704         intel_crtc_load_lut(crtc);
3705 
3706         intel_update_watermarks(crtc);
3707         intel_enable_pipe(intel_crtc);
3708         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3709         intel_enable_planes(crtc);
3710         intel_crtc_update_cursor(crtc, true);
3711 
3712         if (intel_crtc->config.has_pch_encoder)
3713                 ironlake_pch_enable(crtc);
3714 
3715         mutex_lock(&dev->struct_mutex);
3716         intel_update_fbc(dev);
3717         mutex_unlock(&dev->struct_mutex);
3718 
3719         for_each_encoder_on_crtc(dev, crtc, encoder)
3720                 encoder->enable(encoder);
3721 
3722         if (HAS_PCH_CPT(dev))
3723                 cpt_verify_modeset(dev, intel_crtc->pipe);
3724 
3725         /*
3726          * There seems to be a race in PCH platform hw (at least on some
3727          * outputs) where an enabled pipe still completes any pageflip right
3728          * away (as if the pipe is off) instead of waiting for vblank. As soon
3729          * as the first vblank happend, everything works as expected. Hence just
3730          * wait for one vblank before returning to avoid strange things
3731          * happening.
3732          */
3733         intel_wait_for_vblank(dev, intel_crtc->pipe);
3734 }
3735 
3736 /* IPS only exists on ULT machines and is tied to pipe A. */
3737 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3738 {
3739         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3740 }
3741 
3742 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3743 {
3744         struct drm_device *dev = crtc->dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747         int pipe = intel_crtc->pipe;
3748         int plane = intel_crtc->plane;
3749 
3750         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3751         intel_enable_planes(crtc);
3752         intel_crtc_update_cursor(crtc, true);
3753 
3754         hsw_enable_ips(intel_crtc);
3755 
3756         mutex_lock(&dev->struct_mutex);
3757         intel_update_fbc(dev);
3758         mutex_unlock(&dev->struct_mutex);
3759 }
3760 
3761 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3762 {
3763         struct drm_device *dev = crtc->dev;
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766         int pipe = intel_crtc->pipe;
3767         int plane = intel_crtc->plane;
3768 
3769         intel_crtc_wait_for_pending_flips(crtc);
3770         drm_vblank_off(dev, pipe);
3771 
3772         /* FBC must be disabled before disabling the plane on HSW. */
3773         if (dev_priv->fbc.plane == plane)
3774                 intel_disable_fbc(dev);
3775 
3776         hsw_disable_ips(intel_crtc);
3777 
3778         intel_crtc_update_cursor(crtc, false);
3779         intel_disable_planes(crtc);
3780         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3781 }
3782 
3783 /*
3784  * This implements the workaround described in the "notes" section of the mode
3785  * set sequence documentation. When going from no pipes or single pipe to
3786  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3787  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3788  */
3789 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3790 {
3791         struct drm_device *dev = crtc->base.dev;
3792         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3793 
3794         /* We want to get the other_active_crtc only if there's only 1 other
3795          * active crtc. */
3796         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3797                 if (!crtc_it->active || crtc_it == crtc)
3798                         continue;
3799 
3800                 if (other_active_crtc)
3801                         return;
3802 
3803                 other_active_crtc = crtc_it;
3804         }
3805         if (!other_active_crtc)
3806                 return;
3807 
3808         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3809         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3810 }
3811 
3812 static void haswell_crtc_enable(struct drm_crtc *crtc)
3813 {
3814         struct drm_device *dev = crtc->dev;
3815         struct drm_i915_private *dev_priv = dev->dev_private;
3816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3817         struct intel_encoder *encoder;
3818         int pipe = intel_crtc->pipe;
3819 
3820         WARN_ON(!crtc->enabled);
3821 
3822         if (intel_crtc->active)
3823                 return;
3824 
3825         intel_crtc->active = true;
3826 
3827         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3828         if (intel_crtc->config.has_pch_encoder)
3829                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3830 
3831         if (intel_crtc->config.has_pch_encoder)
3832                 dev_priv->display.fdi_link_train(crtc);
3833 
3834         for_each_encoder_on_crtc(dev, crtc, encoder)
3835                 if (encoder->pre_enable)
3836                         encoder->pre_enable(encoder);
3837 
3838         intel_ddi_enable_pipe_clock(intel_crtc);
3839 
3840         ironlake_pfit_enable(intel_crtc);
3841 
3842         /*
3843          * On ILK+ LUT must be loaded before the pipe is running but with
3844          * clocks enabled
3845          */
3846         intel_crtc_load_lut(crtc);
3847 
3848         intel_ddi_set_pipe_settings(crtc);
3849         intel_ddi_enable_transcoder_func(crtc);
3850 
3851         intel_update_watermarks(crtc);
3852         intel_enable_pipe(intel_crtc);
3853 
3854         if (intel_crtc->config.has_pch_encoder)
3855                 lpt_pch_enable(crtc);
3856 
3857         for_each_encoder_on_crtc(dev, crtc, encoder) {
3858                 encoder->enable(encoder);
3859                 intel_opregion_notify_encoder(encoder, true);
3860         }
3861 
3862         /* If we change the relative order between pipe/planes enabling, we need
3863          * to change the workaround. */
3864         haswell_mode_set_planes_workaround(intel_crtc);
3865         haswell_crtc_enable_planes(crtc);
3866 }
3867 
3868 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3869 {
3870         struct drm_device *dev = crtc->base.dev;
3871         struct drm_i915_private *dev_priv = dev->dev_private;
3872         int pipe = crtc->pipe;
3873 
3874         /* To avoid upsetting the power well on haswell only disable the pfit if
3875          * it's in use. The hw state code will make sure we get this right. */
3876         if (crtc->config.pch_pfit.enabled) {
3877                 I915_WRITE(PF_CTL(pipe), 0);
3878                 I915_WRITE(PF_WIN_POS(pipe), 0);
3879                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3880         }
3881 }
3882 
3883 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3884 {
3885         struct drm_device *dev = crtc->dev;
3886         struct drm_i915_private *dev_priv = dev->dev_private;
3887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3888         struct intel_encoder *encoder;
3889         int pipe = intel_crtc->pipe;
3890         int plane = intel_crtc->plane;
3891         u32 reg, temp;
3892 
3893 
3894         if (!intel_crtc->active)
3895                 return;
3896 
3897         for_each_encoder_on_crtc(dev, crtc, encoder)
3898                 encoder->disable(encoder);
3899 
3900         intel_crtc_wait_for_pending_flips(crtc);
3901         drm_vblank_off(dev, pipe);
3902 
3903         if (dev_priv->fbc.plane == plane)
3904                 intel_disable_fbc(dev);
3905 
3906         intel_crtc_update_cursor(crtc, false);
3907         intel_disable_planes(crtc);
3908         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3909 
3910         if (intel_crtc->config.has_pch_encoder)
3911                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3912 
3913         intel_disable_pipe(dev_priv, pipe);
3914 
3915         ironlake_pfit_disable(intel_crtc);
3916 
3917         for_each_encoder_on_crtc(dev, crtc, encoder)
3918                 if (encoder->post_disable)
3919                         encoder->post_disable(encoder);
3920 
3921         if (intel_crtc->config.has_pch_encoder) {
3922                 ironlake_fdi_disable(crtc);
3923 
3924                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3925                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3926 
3927                 if (HAS_PCH_CPT(dev)) {
3928                         /* disable TRANS_DP_CTL */
3929                         reg = TRANS_DP_CTL(pipe);
3930                         temp = I915_READ(reg);
3931                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3932                                   TRANS_DP_PORT_SEL_MASK);
3933                         temp |= TRANS_DP_PORT_SEL_NONE;
3934                         I915_WRITE(reg, temp);
3935 
3936                         /* disable DPLL_SEL */
3937                         temp = I915_READ(PCH_DPLL_SEL);
3938                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3939                         I915_WRITE(PCH_DPLL_SEL, temp);
3940                 }
3941 
3942                 /* disable PCH DPLL */
3943                 intel_disable_shared_dpll(intel_crtc);
3944 
3945                 ironlake_fdi_pll_disable(intel_crtc);
3946         }
3947 
3948         intel_crtc->active = false;
3949         intel_update_watermarks(crtc);
3950 
3951         mutex_lock(&dev->struct_mutex);
3952         intel_update_fbc(dev);
3953         mutex_unlock(&dev->struct_mutex);
3954 }
3955 
3956 static void haswell_crtc_disable(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         struct intel_encoder *encoder;
3962         int pipe = intel_crtc->pipe;
3963         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3964 
3965         if (!intel_crtc->active)
3966                 return;
3967 
3968         haswell_crtc_disable_planes(crtc);
3969 
3970         for_each_encoder_on_crtc(dev, crtc, encoder) {
3971                 intel_opregion_notify_encoder(encoder, false);
3972                 encoder->disable(encoder);
3973         }
3974 
3975         if (intel_crtc->config.has_pch_encoder)
3976                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3977         intel_disable_pipe(dev_priv, pipe);
3978 
3979         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3980 
3981         ironlake_pfit_disable(intel_crtc);
3982 
3983         intel_ddi_disable_pipe_clock(intel_crtc);
3984 
3985         for_each_encoder_on_crtc(dev, crtc, encoder)
3986                 if (encoder->post_disable)
3987                         encoder->post_disable(encoder);
3988 
3989         if (intel_crtc->config.has_pch_encoder) {
3990                 lpt_disable_pch_transcoder(dev_priv);
3991                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3992                 intel_ddi_fdi_disable(crtc);
3993         }
3994 
3995         intel_crtc->active = false;
3996         intel_update_watermarks(crtc);
3997 
3998         mutex_lock(&dev->struct_mutex);
3999         intel_update_fbc(dev);
4000         mutex_unlock(&dev->struct_mutex);
4001 }
4002 
4003 static void ironlake_crtc_off(struct drm_crtc *crtc)
4004 {
4005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4006         intel_put_shared_dpll(intel_crtc);
4007 }
4008 
4009 static void haswell_crtc_off(struct drm_crtc *crtc)
4010 {
4011         intel_ddi_put_crtc_pll(crtc);
4012 }
4013 
4014 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4015 {
4016         if (!enable && intel_crtc->overlay) {
4017                 struct drm_device *dev = intel_crtc->base.dev;
4018                 struct drm_i915_private *dev_priv = dev->dev_private;
4019 
4020                 mutex_lock(&dev->struct_mutex);
4021                 dev_priv->mm.interruptible = false;
4022                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4023                 dev_priv->mm.interruptible = true;
4024                 mutex_unlock(&dev->struct_mutex);
4025         }
4026 
4027         /* Let userspace switch the overlay on again. In most cases userspace
4028          * has to recompute where to put it anyway.
4029          */
4030 }
4031 
4032 /**
4033  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
4034  * cursor plane briefly if not already running after enabling the display
4035  * plane.
4036  * This workaround avoids occasional blank screens when self refresh is
4037  * enabled.
4038  */
4039 static void
4040 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
4041 {
4042         u32 cntl = I915_READ(CURCNTR(pipe));
4043 
4044         if ((cntl & CURSOR_MODE) == 0) {
4045                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4046 
4047                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4048                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4049                 intel_wait_for_vblank(dev_priv->dev, pipe);
4050                 I915_WRITE(CURCNTR(pipe), cntl);
4051                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4052                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4053         }
4054 }
4055 
4056 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4057 {
4058         struct drm_device *dev = crtc->base.dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         struct intel_crtc_config *pipe_config = &crtc->config;
4061 
4062         if (!crtc->config.gmch_pfit.control)
4063                 return;
4064 
4065         /*
4066          * The panel fitter should only be adjusted whilst the pipe is disabled,
4067          * according to register description and PRM.
4068          */
4069         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4070         assert_pipe_disabled(dev_priv, crtc->pipe);
4071 
4072         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4073         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4074 
4075         /* Border color in case we don't scale up to the full screen. Black by
4076          * default, change to something else for debugging. */
4077         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4078 }
4079 
4080 #define for_each_power_domain(domain, mask)                             \
4081         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4082                 if ((1 << (domain)) & (mask))
4083 
4084 enum intel_display_power_domain
4085 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4086 {
4087         struct drm_device *dev = intel_encoder->base.dev;
4088         struct intel_digital_port *intel_dig_port;
4089 
4090         switch (intel_encoder->type) {
4091         case INTEL_OUTPUT_UNKNOWN:
4092                 /* Only DDI platforms should ever use this output type */
4093                 WARN_ON_ONCE(!HAS_DDI(dev));
4094         case INTEL_OUTPUT_DISPLAYPORT:
4095         case INTEL_OUTPUT_HDMI:
4096         case INTEL_OUTPUT_EDP:
4097                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4098                 switch (intel_dig_port->port) {
4099                 case PORT_A:
4100                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4101                 case PORT_B:
4102                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4103                 case PORT_C:
4104                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4105                 case PORT_D:
4106                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4107                 default:
4108                         WARN_ON_ONCE(1);
4109                         return POWER_DOMAIN_PORT_OTHER;
4110                 }
4111         case INTEL_OUTPUT_ANALOG:
4112                 return POWER_DOMAIN_PORT_CRT;
4113         case INTEL_OUTPUT_DSI:
4114                 return POWER_DOMAIN_PORT_DSI;
4115         default:
4116                 return POWER_DOMAIN_PORT_OTHER;
4117         }
4118 }
4119 
4120 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4121 {
4122         struct drm_device *dev = crtc->dev;
4123         struct intel_encoder *intel_encoder;
4124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4125         enum pipe pipe = intel_crtc->pipe;
4126         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4127         unsigned long mask;
4128         enum transcoder transcoder;
4129 
4130         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4131 
4132         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4133         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4134         if (pfit_enabled)
4135                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4136 
4137         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4138                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4139 
4140         return mask;
4141 }
4142 
4143 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4144                                   bool enable)
4145 {
4146         if (dev_priv->power_domains.init_power_on == enable)
4147                 return;
4148 
4149         if (enable)
4150                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4151         else
4152                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4153 
4154         dev_priv->power_domains.init_power_on = enable;
4155 }
4156 
4157 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4158 {
4159         struct drm_i915_private *dev_priv = dev->dev_private;
4160         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4161         struct intel_crtc *crtc;
4162 
4163         /*
4164          * First get all needed power domains, then put all unneeded, to avoid
4165          * any unnecessary toggling of the power wells.
4166          */
4167         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4168                 enum intel_display_power_domain domain;
4169 
4170                 if (!crtc->base.enabled)
4171                         continue;
4172 
4173                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4174 
4175                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4176                         intel_display_power_get(dev_priv, domain);
4177         }
4178 
4179         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4180                 enum intel_display_power_domain domain;
4181 
4182                 for_each_power_domain(domain, crtc->enabled_power_domains)
4183                         intel_display_power_put(dev_priv, domain);
4184 
4185                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4186         }
4187 
4188         intel_display_set_init_power(dev_priv, false);
4189 }
4190 
4191 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4192 {
4193         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4194 
4195         /* Obtain SKU information */
4196         mutex_lock(&dev_priv->dpio_lock);
4197         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4198                 CCK_FUSE_HPLL_FREQ_MASK;
4199         mutex_unlock(&dev_priv->dpio_lock);
4200 
4201         return vco_freq[hpll_freq];
4202 }
4203 
4204 /* Adjust CDclk dividers to allow high res or save power if possible */
4205 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4206 {
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         u32 val, cmd;
4209 
4210         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4211                 cmd = 2;
4212         else if (cdclk == 266)
4213                 cmd = 1;
4214         else
4215                 cmd = 0;
4216 
4217         mutex_lock(&dev_priv->rps.hw_lock);
4218         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4219         val &= ~DSPFREQGUAR_MASK;
4220         val |= (cmd << DSPFREQGUAR_SHIFT);
4221         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4222         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4223                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4224                      50)) {
4225                 DRM_ERROR("timed out waiting for CDclk change\n");
4226         }
4227         mutex_unlock(&dev_priv->rps.hw_lock);
4228 
4229         if (cdclk == 400) {
4230                 u32 divider, vco;
4231 
4232                 vco = valleyview_get_vco(dev_priv);
4233                 divider = ((vco << 1) / cdclk) - 1;
4234 
4235                 mutex_lock(&dev_priv->dpio_lock);
4236                 /* adjust cdclk divider */
4237                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4238                 val &= ~0xf;
4239                 val |= divider;
4240                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4241                 mutex_unlock(&dev_priv->dpio_lock);
4242         }
4243 
4244         mutex_lock(&dev_priv->dpio_lock);
4245         /* adjust self-refresh exit latency value */
4246         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4247         val &= ~0x7f;
4248 
4249         /*
4250          * For high bandwidth configs, we set a higher latency in the bunit
4251          * so that the core display fetch happens in time to avoid underruns.
4252          */
4253         if (cdclk == 400)
4254                 val |= 4500 / 250; /* 4.5 usec */
4255         else
4256                 val |= 3000 / 250; /* 3.0 usec */
4257         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4258         mutex_unlock(&dev_priv->dpio_lock);
4259 
4260         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4261         intel_i2c_reset(dev);
4262 }
4263 
4264 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4265 {
4266         int cur_cdclk, vco;
4267         int divider;
4268 
4269         vco = valleyview_get_vco(dev_priv);
4270 
4271         mutex_lock(&dev_priv->dpio_lock);
4272         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4273         mutex_unlock(&dev_priv->dpio_lock);
4274 
4275         divider &= 0xf;
4276 
4277         cur_cdclk = (vco << 1) / (divider + 1);
4278 
4279         return cur_cdclk;
4280 }
4281 
4282 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4283                                  int max_pixclk)
4284 {
4285         int cur_cdclk;
4286 
4287         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4288 
4289         /*
4290          * Really only a few cases to deal with, as only 4 CDclks are supported:
4291          *   200MHz
4292          *   267MHz
4293          *   320MHz
4294          *   400MHz
4295          * So we check to see whether we're above 90% of the lower bin and
4296          * adjust if needed.
4297          */
4298         if (max_pixclk > 288000) {
4299                 return 400;
4300         } else if (max_pixclk > 240000) {
4301                 return 320;
4302         } else
4303                 return 266;
4304         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4305 }
4306 
4307 /* compute the max pixel clock for new configuration */
4308 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4309 {
4310         struct drm_device *dev = dev_priv->dev;
4311         struct intel_crtc *intel_crtc;
4312         int max_pixclk = 0;
4313 
4314         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4315                             base.head) {
4316                 if (intel_crtc->new_enabled)
4317                         max_pixclk = max(max_pixclk,
4318                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4319         }
4320 
4321         return max_pixclk;
4322 }
4323 
4324 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4325                                             unsigned *prepare_pipes)
4326 {
4327         struct drm_i915_private *dev_priv = dev->dev_private;
4328         struct intel_crtc *intel_crtc;
4329         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4330         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4331 
4332         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4333                 return;
4334 
4335         /* disable/enable all currently active pipes while we change cdclk */
4336         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4337                             base.head)
4338                 if (intel_crtc->base.enabled)
4339                         *prepare_pipes |= (1 << intel_crtc->pipe);
4340 }
4341 
4342 static void valleyview_modeset_global_resources(struct drm_device *dev)
4343 {
4344         struct drm_i915_private *dev_priv = dev->dev_private;
4345         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4346         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4347         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4348 
4349         if (req_cdclk != cur_cdclk)
4350                 valleyview_set_cdclk(dev, req_cdclk);
4351         modeset_update_crtc_power_domains(dev);
4352 }
4353 
4354 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4355 {
4356         struct drm_device *dev = crtc->dev;
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4359         struct intel_encoder *encoder;
4360         int pipe = intel_crtc->pipe;
4361         int plane = intel_crtc->plane;
4362         bool is_dsi;
4363 
4364         WARN_ON(!crtc->enabled);
4365 
4366         if (intel_crtc->active)
4367                 return;
4368 
4369         intel_crtc->active = true;
4370 
4371         for_each_encoder_on_crtc(dev, crtc, encoder)
4372                 if (encoder->pre_pll_enable)
4373                         encoder->pre_pll_enable(encoder);
4374 
4375         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4376 
4377         if (!is_dsi)
4378                 vlv_enable_pll(intel_crtc);
4379 
4380         for_each_encoder_on_crtc(dev, crtc, encoder)
4381                 if (encoder->pre_enable)
4382                         encoder->pre_enable(encoder);
4383 
4384         i9xx_pfit_enable(intel_crtc);
4385 
4386         intel_crtc_load_lut(crtc);
4387 
4388         intel_update_watermarks(crtc);
4389         intel_enable_pipe(intel_crtc);
4390         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4391         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4392         intel_enable_planes(crtc);
4393         intel_crtc_update_cursor(crtc, true);
4394 
4395         intel_update_fbc(dev);
4396 
4397         for_each_encoder_on_crtc(dev, crtc, encoder)
4398                 encoder->enable(encoder);
4399 }
4400 
4401 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4402 {
4403         struct drm_device *dev = crtc->dev;
4404         struct drm_i915_private *dev_priv = dev->dev_private;
4405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4406         struct intel_encoder *encoder;
4407         int pipe = intel_crtc->pipe;
4408         int plane = intel_crtc->plane;
4409 
4410         WARN_ON(!crtc->enabled);
4411 
4412         if (intel_crtc->active)
4413                 return;
4414 
4415         intel_crtc->active = true;
4416 
4417         for_each_encoder_on_crtc(dev, crtc, encoder)
4418                 if (encoder->pre_enable)
4419                         encoder->pre_enable(encoder);
4420 
4421         i9xx_enable_pll(intel_crtc);
4422 
4423         i9xx_pfit_enable(intel_crtc);
4424 
4425         intel_crtc_load_lut(crtc);
4426 
4427         intel_update_watermarks(crtc);
4428         intel_enable_pipe(intel_crtc);
4429         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4430         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4431         intel_enable_planes(crtc);
4432         /* The fixup needs to happen before cursor is enabled */
4433         if (IS_G4X(dev))
4434                 g4x_fixup_plane(dev_priv, pipe);
4435         intel_crtc_update_cursor(crtc, true);
4436 
4437         /* Give the overlay scaler a chance to enable if it's on this pipe */
4438         intel_crtc_dpms_overlay(intel_crtc, true);
4439 
4440         intel_update_fbc(dev);
4441 
4442         for_each_encoder_on_crtc(dev, crtc, encoder)
4443                 encoder->enable(encoder);
4444 }
4445 
4446 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4447 {
4448         struct drm_device *dev = crtc->base.dev;
4449         struct drm_i915_private *dev_priv = dev->dev_private;
4450 
4451         if (!crtc->config.gmch_pfit.control)
4452                 return;
4453 
4454         assert_pipe_disabled(dev_priv, crtc->pipe);
4455 
4456         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4457                          I915_READ(PFIT_CONTROL));
4458         I915_WRITE(PFIT_CONTROL, 0);
4459 }
4460 
4461 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4462 {
4463         struct drm_device *dev = crtc->dev;
4464         struct drm_i915_private *dev_priv = dev->dev_private;
4465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4466         struct intel_encoder *encoder;
4467         int pipe = intel_crtc->pipe;
4468         int plane = intel_crtc->plane;
4469 
4470         if (!intel_crtc->active)
4471                 return;
4472 
4473         for_each_encoder_on_crtc(dev, crtc, encoder)
4474                 encoder->disable(encoder);
4475 
4476         /* Give the overlay scaler a chance to disable if it's on this pipe */
4477         intel_crtc_wait_for_pending_flips(crtc);
4478         drm_vblank_off(dev, pipe);
4479 
4480         if (dev_priv->fbc.plane == plane)
4481                 intel_disable_fbc(dev);
4482 
4483         intel_crtc_dpms_overlay(intel_crtc, false);
4484         intel_crtc_update_cursor(crtc, false);
4485         intel_disable_planes(crtc);
4486         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4487 
4488         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4489         intel_disable_pipe(dev_priv, pipe);
4490 
4491         i9xx_pfit_disable(intel_crtc);
4492 
4493         for_each_encoder_on_crtc(dev, crtc, encoder)
4494                 if (encoder->post_disable)
4495                         encoder->post_disable(encoder);
4496 
4497         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4498                 vlv_disable_pll(dev_priv, pipe);
4499         else if (!IS_VALLEYVIEW(dev))
4500                 i9xx_disable_pll(dev_priv, pipe);
4501 
4502         intel_crtc->active = false;
4503         intel_update_watermarks(crtc);
4504 
4505         intel_update_fbc(dev);
4506 }
4507 
4508 static void i9xx_crtc_off(struct drm_crtc *crtc)
4509 {
4510 }
4511 
4512 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4513                                     bool enabled)
4514 {
4515         struct drm_device *dev = crtc->dev;
4516         struct drm_i915_master_private *master_priv;
4517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518         int pipe = intel_crtc->pipe;
4519 
4520         if (!dev->primary->master)
4521                 return;
4522 
4523         master_priv = dev->primary->master->driver_priv;
4524         if (!master_priv->sarea_priv)
4525                 return;
4526 
4527         switch (pipe) {
4528         case 0:
4529                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4530                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4531                 break;
4532         case 1:
4533                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4534                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4535                 break;
4536         default:
4537                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4538                 break;
4539         }
4540 }
4541 
4542 /**
4543  * Sets the power management mode of the pipe and plane.
4544  */
4545 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4546 {
4547         struct drm_device *dev = crtc->dev;
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         struct intel_encoder *intel_encoder;
4550         bool enable = false;
4551 
4552         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4553                 enable |= intel_encoder->connectors_active;
4554 
4555         if (enable)
4556                 dev_priv->display.crtc_enable(crtc);
4557         else
4558                 dev_priv->display.crtc_disable(crtc);
4559 
4560         intel_crtc_update_sarea(crtc, enable);
4561 }
4562 
4563 static void intel_crtc_disable(struct drm_crtc *crtc)
4564 {
4565         struct drm_device *dev = crtc->dev;
4566         struct drm_connector *connector;
4567         struct drm_i915_private *dev_priv = dev->dev_private;
4568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4569 
4570         /* crtc should still be enabled when we disable it. */
4571         WARN_ON(!crtc->enabled);
4572 
4573         dev_priv->display.crtc_disable(crtc);
4574         intel_crtc->eld_vld = false;
4575         intel_crtc_update_sarea(crtc, false);
4576         dev_priv->display.off(crtc);
4577 
4578         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4579         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4580         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4581 
4582         if (crtc->primary->fb) {
4583                 mutex_lock(&dev->struct_mutex);
4584                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4585                 mutex_unlock(&dev->struct_mutex);
4586                 crtc->primary->fb = NULL;
4587         }
4588 
4589         /* Update computed state. */
4590         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4591                 if (!connector->encoder || !connector->encoder->crtc)
4592                         continue;
4593 
4594                 if (connector->encoder->crtc != crtc)
4595                         continue;
4596 
4597                 connector->dpms = DRM_MODE_DPMS_OFF;
4598                 to_intel_encoder(connector->encoder)->connectors_active = false;
4599         }
4600 }
4601 
4602 void intel_encoder_destroy(struct drm_encoder *encoder)
4603 {
4604         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4605 
4606         drm_encoder_cleanup(encoder);
4607         kfree(intel_encoder);
4608 }
4609 
4610 /* Simple dpms helper for encoders with just one connector, no cloning and only
4611  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4612  * state of the entire output pipe. */
4613 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4614 {
4615         if (mode == DRM_MODE_DPMS_ON) {
4616                 encoder->connectors_active = true;
4617 
4618                 intel_crtc_update_dpms(encoder->base.crtc);
4619         } else {
4620                 encoder->connectors_active = false;
4621 
4622                 intel_crtc_update_dpms(encoder->base.crtc);
4623         }
4624 }
4625 
4626 /* Cross check the actual hw state with our own modeset state tracking (and it's
4627  * internal consistency). */
4628 static void intel_connector_check_state(struct intel_connector *connector)
4629 {
4630         if (connector->get_hw_state(connector)) {
4631                 struct intel_encoder *encoder = connector->encoder;
4632                 struct drm_crtc *crtc;
4633                 bool encoder_enabled;
4634                 enum pipe pipe;
4635 
4636                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4637                               connector->base.base.id,
4638                               drm_get_connector_name(&connector->base));
4639 
4640                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4641                      "wrong connector dpms state\n");
4642                 WARN(connector->base.encoder != &encoder->base,
4643                      "active connector not linked to encoder\n");
4644                 WARN(!encoder->connectors_active,
4645                      "encoder->connectors_active not set\n");
4646 
4647                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4648                 WARN(!encoder_enabled, "encoder not enabled\n");
4649                 if (WARN_ON(!encoder->base.crtc))
4650                         return;
4651 
4652                 crtc = encoder->base.crtc;
4653 
4654                 WARN(!crtc->enabled, "crtc not enabled\n");
4655                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4656                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4657                      "encoder active on the wrong pipe\n");
4658         }
4659 }
4660 
4661 /* Even simpler default implementation, if there's really no special case to
4662  * consider. */
4663 void intel_connector_dpms(struct drm_connector *connector, int mode)
4664 {
4665         /* All the simple cases only support two dpms states. */
4666         if (mode != DRM_MODE_DPMS_ON)
4667                 mode = DRM_MODE_DPMS_OFF;
4668 
4669         if (mode == connector->dpms)
4670                 return;
4671 
4672         connector->dpms = mode;
4673 
4674         /* Only need to change hw state when actually enabled */
4675         if (connector->encoder)
4676                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4677 
4678         intel_modeset_check_state(connector->dev);
4679 }
4680 
4681 /* Simple connector->get_hw_state implementation for encoders that support only
4682  * one connector and no cloning and hence the encoder state determines the state
4683  * of the connector. */
4684 bool intel_connector_get_hw_state(struct intel_connector *connector)
4685 {
4686         enum pipe pipe = 0;
4687         struct intel_encoder *encoder = connector->encoder;
4688 
4689         return encoder->get_hw_state(encoder, &pipe);
4690 }
4691 
4692 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4693                                      struct intel_crtc_config *pipe_config)
4694 {
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         struct intel_crtc *pipe_B_crtc =
4697                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4698 
4699         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4700                       pipe_name(pipe), pipe_config->fdi_lanes);
4701         if (pipe_config->fdi_lanes > 4) {
4702                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4703                               pipe_name(pipe), pipe_config->fdi_lanes);
4704                 return false;
4705         }
4706 
4707         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4708                 if (pipe_config->fdi_lanes > 2) {
4709                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4710                                       pipe_config->fdi_lanes);
4711                         return false;
4712                 } else {
4713                         return true;
4714                 }
4715         }
4716 
4717         if (INTEL_INFO(dev)->num_pipes == 2)
4718                 return true;
4719 
4720         /* Ivybridge 3 pipe is really complicated */
4721         switch (pipe) {
4722         case PIPE_A:
4723                 return true;
4724         case PIPE_B:
4725                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4726                     pipe_config->fdi_lanes > 2) {
4727                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4728                                       pipe_name(pipe), pipe_config->fdi_lanes);
4729                         return false;
4730                 }
4731                 return true;
4732         case PIPE_C:
4733                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4734                     pipe_B_crtc->config.fdi_lanes <= 2) {
4735                         if (pipe_config->fdi_lanes > 2) {
4736                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4737                                               pipe_name(pipe), pipe_config->fdi_lanes);
4738                                 return false;
4739                         }
4740                 } else {
4741                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4742                         return false;
4743                 }
4744                 return true;
4745         default:
4746                 BUG();
4747         }
4748 }
4749 
4750 #define RETRY 1
4751 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4752                                        struct intel_crtc_config *pipe_config)
4753 {
4754         struct drm_device *dev = intel_crtc->base.dev;
4755         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4756         int lane, link_bw, fdi_dotclock;
4757         bool setup_ok, needs_recompute = false;
4758 
4759 retry:
4760         /* FDI is a binary signal running at ~2.7GHz, encoding
4761          * each output octet as 10 bits. The actual frequency
4762          * is stored as a divider into a 100MHz clock, and the
4763          * mode pixel clock is stored in units of 1KHz.
4764          * Hence the bw of each lane in terms of the mode signal
4765          * is:
4766          */
4767         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4768 
4769         fdi_dotclock = adjusted_mode->crtc_clock;
4770 
4771         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4772                                            pipe_config->pipe_bpp);
4773 
4774         pipe_config->fdi_lanes = lane;
4775 
4776         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4777                                link_bw, &pipe_config->fdi_m_n);
4778 
4779         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4780                                             intel_crtc->pipe, pipe_config);
4781         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4782                 pipe_config->pipe_bpp -= 2*3;
4783                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4784                               pipe_config->pipe_bpp);
4785                 needs_recompute = true;
4786                 pipe_config->bw_constrained = true;
4787 
4788                 goto retry;
4789         }
4790 
4791         if (needs_recompute)
4792                 return RETRY;
4793 
4794         return setup_ok ? 0 : -EINVAL;
4795 }
4796 
4797 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4798                                    struct intel_crtc_config *pipe_config)
4799 {
4800         pipe_config->ips_enabled = i915.enable_ips &&
4801                                    hsw_crtc_supports_ips(crtc) &&
4802                                    pipe_config->pipe_bpp <= 24;
4803 }
4804 
4805 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4806                                      struct intel_crtc_config *pipe_config)
4807 {
4808         struct drm_device *dev = crtc->base.dev;
4809         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4810 
4811         /* FIXME should check pixel clock limits on all platforms */
4812         if (INTEL_INFO(dev)->gen < 4) {
4813                 struct drm_i915_private *dev_priv = dev->dev_private;
4814                 int clock_limit =
4815                         dev_priv->display.get_display_clock_speed(dev);
4816 
4817                 /*
4818                  * Enable pixel doubling when the dot clock
4819                  * is > 90% of the (display) core speed.
4820                  *
4821                  * GDG double wide on either pipe,
4822                  * otherwise pipe A only.
4823                  */
4824                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4825                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4826                         clock_limit *= 2;
4827                         pipe_config->double_wide = true;
4828                 }
4829 
4830                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4831                         return -EINVAL;
4832         }
4833 
4834         /*
4835          * Pipe horizontal size must be even in:
4836          * - DVO ganged mode
4837          * - LVDS dual channel mode
4838          * - Double wide pipe
4839          */
4840         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4841              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4842                 pipe_config->pipe_src_w &= ~1;
4843 
4844         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4845          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4846          */
4847         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4848                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4849                 return -EINVAL;
4850 
4851         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4852                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4853         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4854                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4855                  * for lvds. */
4856                 pipe_config->pipe_bpp = 8*3;
4857         }
4858 
4859         if (HAS_IPS(dev))
4860                 hsw_compute_ips_config(crtc, pipe_config);
4861 
4862         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4863          * clock survives for now. */
4864         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4865                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4866 
4867         if (pipe_config->has_pch_encoder)
4868                 return ironlake_fdi_compute_config(crtc, pipe_config);
4869 
4870         return 0;
4871 }
4872 
4873 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4874 {
4875         return 400000; /* FIXME */
4876 }
4877 
4878 static int i945_get_display_clock_speed(struct drm_device *dev)
4879 {
4880         return 400000;
4881 }
4882 
4883 static int i915_get_display_clock_speed(struct drm_device *dev)
4884 {
4885         return 333000;
4886 }
4887 
4888 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4889 {
4890         return 200000;
4891 }
4892 
4893 static int pnv_get_display_clock_speed(struct drm_device *dev)
4894 {
4895         u16 gcfgc = 0;
4896 
4897         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4898 
4899         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4900         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4901                 return 267000;
4902         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4903                 return 333000;
4904         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4905                 return 444000;
4906         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4907                 return 200000;
4908         default:
4909                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4910         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4911                 return 133000;
4912         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4913                 return 167000;
4914         }
4915 }
4916 
4917 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4918 {
4919         u16 gcfgc = 0;
4920 
4921         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4922 
4923         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4924                 return 133000;
4925         else {
4926                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4927                 case GC_DISPLAY_CLOCK_333_MHZ:
4928                         return 333000;
4929                 default:
4930                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4931                         return 190000;
4932                 }
4933         }
4934 }
4935 
4936 static int i865_get_display_clock_speed(struct drm_device *dev)
4937 {
4938         return 266000;
4939 }
4940 
4941 static int i855_get_display_clock_speed(struct drm_device *dev)
4942 {
4943         u16 hpllcc = 0;
4944         /* Assume that the hardware is in the high speed state.  This
4945          * should be the default.
4946          */
4947         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4948         case GC_CLOCK_133_200:
4949         case GC_CLOCK_100_200:
4950                 return 200000;
4951         case GC_CLOCK_166_250:
4952                 return 250000;
4953         case GC_CLOCK_100_133:
4954                 return 133000;
4955         }
4956 
4957         /* Shouldn't happen */
4958         return 0;
4959 }
4960 
4961 static int i830_get_display_clock_speed(struct drm_device *dev)
4962 {
4963         return 133000;
4964 }
4965 
4966 static void
4967 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4968 {
4969         while (*num > DATA_LINK_M_N_MASK ||
4970                *den > DATA_LINK_M_N_MASK) {
4971                 *num >>= 1;
4972                 *den >>= 1;
4973         }
4974 }
4975 
4976 static void compute_m_n(unsigned int m, unsigned int n,
4977                         uint32_t *ret_m, uint32_t *ret_n)
4978 {
4979         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4980         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4981         intel_reduce_m_n_ratio(ret_m, ret_n);
4982 }
4983 
4984 void
4985 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4986                        int pixel_clock, int link_clock,
4987                        struct intel_link_m_n *m_n)
4988 {
4989         m_n->tu = 64;
4990 
4991         compute_m_n(bits_per_pixel * pixel_clock,
4992                     link_clock * nlanes * 8,
4993                     &m_n->gmch_m, &m_n->gmch_n);
4994 
4995         compute_m_n(pixel_clock, link_clock,
4996                     &m_n->link_m, &m_n->link_n);
4997 }
4998 
4999 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5000 {
5001         if (i915.panel_use_ssc >= 0)
5002                 return i915.panel_use_ssc != 0;
5003         return dev_priv->vbt.lvds_use_ssc
5004                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5005 }
5006 
5007 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5008 {
5009         struct drm_device *dev = crtc->dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         int refclk;
5012 
5013         if (IS_VALLEYVIEW(dev)) {
5014                 refclk = 100000;
5015         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5016             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5017                 refclk = dev_priv->vbt.lvds_ssc_freq;
5018                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5019         } else if (!IS_GEN2(dev)) {
5020                 refclk = 96000;
5021         } else {
5022                 refclk = 48000;
5023         }
5024 
5025         return refclk;
5026 }
5027 
5028 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5029 {
5030         return (1 << dpll->n) << 16 | dpll->m2;
5031 }
5032 
5033 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5034 {
5035         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5036 }
5037 
5038 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5039                                      intel_clock_t *reduced_clock)
5040 {
5041         struct drm_device *dev = crtc->base.dev;
5042         struct drm_i915_private *dev_priv = dev->dev_private;
5043         int pipe = crtc->pipe;
5044         u32 fp, fp2 = 0;
5045 
5046         if (IS_PINEVIEW(dev)) {
5047                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5048                 if (reduced_clock)
5049                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5050         } else {
5051                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5052                 if (reduced_clock)
5053                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5054         }
5055 
5056         I915_WRITE(FP0(pipe), fp);
5057         crtc->config.dpll_hw_state.fp0 = fp;
5058 
5059         crtc->lowfreq_avail = false;
5060         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5061             reduced_clock && i915.powersave) {
5062                 I915_WRITE(FP1(pipe), fp2);
5063                 crtc->config.dpll_hw_state.fp1 = fp2;
5064                 crtc->lowfreq_avail = true;
5065         } else {
5066                 I915_WRITE(FP1(pipe), fp);
5067                 crtc->config.dpll_hw_state.fp1 = fp;
5068         }
5069 }
5070 
5071 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5072                 pipe)
5073 {
5074         u32 reg_val;
5075 
5076         /*
5077          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5078          * and set it to a reasonable value instead.
5079          */
5080         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5081         reg_val &= 0xffffff00;
5082         reg_val |= 0x00000030;
5083         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5084 
5085         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5086         reg_val &= 0x8cffffff;
5087         reg_val = 0x8c000000;
5088         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5089 
5090         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5091         reg_val &= 0xffffff00;
5092         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5093 
5094         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5095         reg_val &= 0x00ffffff;
5096         reg_val |= 0xb0000000;
5097         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5098 }
5099 
5100 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5101                                          struct intel_link_m_n *m_n)
5102 {
5103         struct drm_device *dev = crtc->base.dev;
5104         struct drm_i915_private *dev_priv = dev->dev_private;
5105         int pipe = crtc->pipe;
5106 
5107         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5108         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5109         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5110         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5111 }
5112 
5113 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5114                                          struct intel_link_m_n *m_n)
5115 {
5116         struct drm_device *dev = crtc->base.dev;
5117         struct drm_i915_private *dev_priv = dev->dev_private;
5118         int pipe = crtc->pipe;
5119         enum transcoder transcoder = crtc->config.cpu_transcoder;
5120 
5121         if (INTEL_INFO(dev)->gen >= 5) {
5122                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5123                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5124                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5125                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5126         } else {
5127                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5128                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5129                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5130                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5131         }
5132 }
5133 
5134 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5135 {
5136         if (crtc->config.has_pch_encoder)
5137                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5138         else
5139                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5140 }
5141 
5142 static void vlv_update_pll(struct intel_crtc *crtc)
5143 {
5144         struct drm_device *dev = crtc->base.dev;
5145         struct drm_i915_private *dev_priv = dev->dev_private;
5146         int pipe = crtc->pipe;
5147         u32 dpll, mdiv;
5148         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5149         u32 coreclk, reg_val, dpll_md;
5150 
5151         mutex_lock(&dev_priv->dpio_lock);
5152 
5153         bestn = crtc->config.dpll.n;
5154         bestm1 = crtc->config.dpll.m1;
5155         bestm2 = crtc->config.dpll.m2;
5156         bestp1 = crtc->config.dpll.p1;
5157         bestp2 = crtc->config.dpll.p2;
5158 
5159         /* See eDP HDMI DPIO driver vbios notes doc */
5160 
5161         /* PLL B needs special handling */
5162         if (pipe)
5163                 vlv_pllb_recal_opamp(dev_priv, pipe);
5164 
5165         /* Set up Tx target for periodic Rcomp update */
5166         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5167 
5168         /* Disable target IRef on PLL */
5169         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5170         reg_val &= 0x00ffffff;
5171         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5172 
5173         /* Disable fast lock */
5174         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5175 
5176         /* Set idtafcrecal before PLL is enabled */
5177         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5178         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5179         mdiv |= ((bestn << DPIO_N_SHIFT));
5180         mdiv |= (1 << DPIO_K_SHIFT);
5181 
5182         /*
5183          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5184          * but we don't support that).
5185          * Note: don't use the DAC post divider as it seems unstable.
5186          */
5187         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5188         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5189 
5190         mdiv |= DPIO_ENABLE_CALIBRATION;
5191         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5192 
5193         /* Set HBR and RBR LPF coefficients */
5194         if (crtc->config.port_clock == 162000 ||
5195             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5196             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5197                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5198                                  0x009f0003);
5199         else
5200                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5201                                  0x00d0000f);
5202 
5203         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5204             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5205                 /* Use SSC source */
5206                 if (!pipe)
5207                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5208                                          0x0df40000);
5209                 else
5210                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5211                                          0x0df70000);
5212         } else { /* HDMI or VGA */
5213                 /* Use bend source */
5214                 if (!pipe)
5215                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5216                                          0x0df70000);
5217                 else
5218                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5219                                          0x0df40000);
5220         }
5221 
5222         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5223         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5224         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5225             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5226                 coreclk |= 0x01000000;
5227         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5228 
5229         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5230 
5231         /*
5232          * Enable DPIO clock input. We should never disable the reference
5233          * clock for pipe B, since VGA hotplug / manual detection depends
5234          * on it.
5235          */
5236         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5237                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5238         /* We should never disable this, set it here for state tracking */
5239         if (pipe == PIPE_B)
5240                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5241         dpll |= DPLL_VCO_ENABLE;
5242         crtc->config.dpll_hw_state.dpll = dpll;
5243 
5244         dpll_md = (crtc->config.pixel_multiplier - 1)
5245                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5246         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5247 
5248         if (crtc->config.has_dp_encoder)
5249                 intel_dp_set_m_n(crtc);
5250 
5251         mutex_unlock(&dev_priv->dpio_lock);
5252 }
5253 
5254 static void i9xx_update_pll(struct intel_crtc *crtc,
5255                             intel_clock_t *reduced_clock,
5256                             int num_connectors)
5257 {
5258         struct drm_device *dev = crtc->base.dev;
5259         struct drm_i915_private *dev_priv = dev->dev_private;
5260         u32 dpll;
5261         bool is_sdvo;
5262         struct dpll *clock = &crtc->config.dpll;
5263 
5264         i9xx_update_pll_dividers(crtc, reduced_clock);
5265 
5266         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5267                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5268 
5269         dpll = DPLL_VGA_MODE_DIS;
5270 
5271         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5272                 dpll |= DPLLB_MODE_LVDS;
5273         else
5274                 dpll |= DPLLB_MODE_DAC_SERIAL;
5275 
5276         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5277                 dpll |= (crtc->config.pixel_multiplier - 1)
5278                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5279         }
5280 
5281         if (is_sdvo)
5282                 dpll |= DPLL_SDVO_HIGH_SPEED;
5283 
5284         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5285                 dpll |= DPLL_SDVO_HIGH_SPEED;
5286 
5287         /* compute bitmask from p1 value */
5288         if (IS_PINEVIEW(dev))
5289                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5290         else {
5291                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5292                 if (IS_G4X(dev) && reduced_clock)
5293                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5294         }
5295         switch (clock->p2) {
5296         case 5:
5297                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5298                 break;
5299         case 7:
5300                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5301                 break;
5302         case 10:
5303                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5304                 break;
5305         case 14:
5306                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5307                 break;
5308         }
5309         if (INTEL_INFO(dev)->gen >= 4)
5310                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5311 
5312         if (crtc->config.sdvo_tv_clock)
5313                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5314         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5315                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5316                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5317         else
5318                 dpll |= PLL_REF_INPUT_DREFCLK;
5319 
5320         dpll |= DPLL_VCO_ENABLE;
5321         crtc->config.dpll_hw_state.dpll = dpll;
5322 
5323         if (INTEL_INFO(dev)->gen >= 4) {
5324                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5325                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5326                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5327         }
5328 
5329         if (crtc->config.has_dp_encoder)
5330                 intel_dp_set_m_n(crtc);
5331 }
5332 
5333 static void i8xx_update_pll(struct intel_crtc *crtc,
5334                             intel_clock_t *reduced_clock,
5335                             int num_connectors)
5336 {
5337         struct drm_device *dev = crtc->base.dev;
5338         struct drm_i915_private *dev_priv = dev->dev_private;
5339         u32 dpll;
5340         struct dpll *clock = &crtc->config.dpll;
5341 
5342         i9xx_update_pll_dividers(crtc, reduced_clock);
5343 
5344         dpll = DPLL_VGA_MODE_DIS;
5345 
5346         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5347                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5348         } else {
5349                 if (clock->p1 == 2)
5350                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5351                 else
5352                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5353                 if (clock->p2 == 4)
5354                         dpll |= PLL_P2_DIVIDE_BY_4;
5355         }
5356 
5357         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5358                 dpll |= DPLL_DVO_2X_MODE;
5359 
5360         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5361                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5362                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5363         else
5364                 dpll |= PLL_REF_INPUT_DREFCLK;
5365 
5366         dpll |= DPLL_VCO_ENABLE;
5367         crtc->config.dpll_hw_state.dpll = dpll;
5368 }
5369 
5370 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5371 {
5372         struct drm_device *dev = intel_crtc->base.dev;
5373         struct drm_i915_private *dev_priv = dev->dev_private;
5374         enum pipe pipe = intel_crtc->pipe;
5375         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5376         struct drm_display_mode *adjusted_mode =
5377                 &intel_crtc->config.adjusted_mode;
5378         uint32_t crtc_vtotal, crtc_vblank_end;
5379         int vsyncshift = 0;
5380 
5381         /* We need to be careful not to changed the adjusted mode, for otherwise
5382          * the hw state checker will get angry at the mismatch. */
5383         crtc_vtotal = adjusted_mode->crtc_vtotal;
5384         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5385 
5386         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5387                 /* the chip adds 2 halflines automatically */
5388                 crtc_vtotal -= 1;
5389                 crtc_vblank_end -= 1;
5390 
5391                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5392                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5393                 else
5394                         vsyncshift = adjusted_mode->crtc_hsync_start -
5395                                 adjusted_mode->crtc_htotal / 2;
5396                 if (vsyncshift < 0)
5397                         vsyncshift += adjusted_mode->crtc_htotal;
5398         }
5399 
5400         if (INTEL_INFO(dev)->gen > 3)
5401                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5402 
5403         I915_WRITE(HTOTAL(cpu_transcoder),
5404                    (adjusted_mode->crtc_hdisplay - 1) |
5405                    ((adjusted_mode->crtc_htotal - 1) << 16));
5406         I915_WRITE(HBLANK(cpu_transcoder),
5407                    (adjusted_mode->crtc_hblank_start - 1) |
5408                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5409         I915_WRITE(HSYNC(cpu_transcoder),
5410                    (adjusted_mode->crtc_hsync_start - 1) |
5411                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5412 
5413         I915_WRITE(VTOTAL(cpu_transcoder),
5414                    (adjusted_mode->crtc_vdisplay - 1) |
5415                    ((crtc_vtotal - 1) << 16));
5416         I915_WRITE(VBLANK(cpu_transcoder),
5417                    (adjusted_mode->crtc_vblank_start - 1) |
5418                    ((crtc_vblank_end - 1) << 16));
5419         I915_WRITE(VSYNC(cpu_transcoder),
5420                    (adjusted_mode->crtc_vsync_start - 1) |
5421                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5422 
5423         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5424          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5425          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5426          * bits. */
5427         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5428             (pipe == PIPE_B || pipe == PIPE_C))
5429                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5430 
5431         /* pipesrc controls the size that is scaled from, which should
5432          * always be the user's requested size.
5433          */
5434         I915_WRITE(PIPESRC(pipe),
5435                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5436                    (intel_crtc->config.pipe_src_h - 1));
5437 }
5438 
5439 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5440                                    struct intel_crtc_config *pipe_config)
5441 {
5442         struct drm_device *dev = crtc->base.dev;
5443         struct drm_i915_private *dev_priv = dev->dev_private;
5444         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5445         uint32_t tmp;
5446 
5447         tmp = I915_READ(HTOTAL(cpu_transcoder));
5448         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5449         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5450         tmp = I915_READ(HBLANK(cpu_transcoder));
5451         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5452         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5453         tmp = I915_READ(HSYNC(cpu_transcoder));
5454         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5455         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5456 
5457         tmp = I915_READ(VTOTAL(cpu_transcoder));
5458         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5459         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5460         tmp = I915_READ(VBLANK(cpu_transcoder));
5461         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5462         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5463         tmp = I915_READ(VSYNC(cpu_transcoder));
5464         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5465         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5466 
5467         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5468                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5469                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5470                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5471         }
5472 
5473         tmp = I915_READ(PIPESRC(crtc->pipe));
5474         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5475         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5476 
5477         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5478         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5479 }
5480 
5481 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5482                                  struct intel_crtc_config *pipe_config)
5483 {
5484         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5485         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5486         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5487         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5488 
5489         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5490         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5491         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5492         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5493 
5494         mode->flags = pipe_config->adjusted_mode.flags;
5495 
5496         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5497         mode->flags |= pipe_config->adjusted_mode.flags;
5498 }
5499 
5500 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5501 {
5502         struct drm_device *dev = intel_crtc->base.dev;
5503         struct drm_i915_private *dev_priv = dev->dev_private;
5504         uint32_t pipeconf;
5505 
5506         pipeconf = 0;
5507 
5508         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5509             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5510                 pipeconf |= PIPECONF_ENABLE;
5511 
5512         if (intel_crtc->config.double_wide)
5513                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5514 
5515         /* only g4x and later have fancy bpc/dither controls */
5516         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5517                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5518                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5519                         pipeconf |= PIPECONF_DITHER_EN |
5520                                     PIPECONF_DITHER_TYPE_SP;
5521 
5522                 switch (intel_crtc->config.pipe_bpp) {
5523                 case 18:
5524                         pipeconf |= PIPECONF_6BPC;
5525                         break;
5526                 case 24:
5527                         pipeconf |= PIPECONF_8BPC;
5528                         break;
5529                 case 30:
5530                         pipeconf |= PIPECONF_10BPC;
5531                         break;
5532                 default:
5533                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5534                         BUG();
5535                 }
5536         }
5537 
5538         if (HAS_PIPE_CXSR(dev)) {
5539                 if (intel_crtc->lowfreq_avail) {
5540                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5541                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5542                 } else {
5543                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5544                 }
5545         }
5546 
5547         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5548                 if (INTEL_INFO(dev)->gen < 4 ||
5549                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5550                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5551                 else
5552                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5553         } else
5554                 pipeconf |= PIPECONF_PROGRESSIVE;
5555 
5556         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5557                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5558 
5559         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5560         POSTING_READ(PIPECONF(intel_crtc->pipe));
5561 }
5562 
5563 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5564                               int x, int y,
5565                               struct drm_framebuffer *fb)
5566 {
5567         struct drm_device *dev = crtc->dev;
5568         struct drm_i915_private *dev_priv = dev->dev_private;
5569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5570         int pipe = intel_crtc->pipe;
5571         int plane = intel_crtc->plane;
5572         int refclk, num_connectors = 0;
5573         intel_clock_t clock, reduced_clock;
5574         u32 dspcntr;
5575         bool ok, has_reduced_clock = false;
5576         bool is_lvds = false, is_dsi = false;
5577         struct intel_encoder *encoder;
5578         const intel_limit_t *limit;
5579         int ret;
5580 
5581         for_each_encoder_on_crtc(dev, crtc, encoder) {
5582                 switch (encoder->type) {
5583                 case INTEL_OUTPUT_LVDS:
5584                         is_lvds = true;
5585                         break;
5586                 case INTEL_OUTPUT_DSI:
5587                         is_dsi = true;
5588                         break;
5589                 }
5590 
5591                 num_connectors++;
5592         }
5593 
5594         if (is_dsi)
5595                 goto skip_dpll;
5596 
5597         if (!intel_crtc->config.clock_set) {
5598                 refclk = i9xx_get_refclk(crtc, num_connectors);
5599 
5600                 /*
5601                  * Returns a set of divisors for the desired target clock with
5602                  * the given refclk, or FALSE.  The returned values represent
5603                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5604                  * 2) / p1 / p2.
5605                  */
5606                 limit = intel_limit(crtc, refclk);
5607                 ok = dev_priv->display.find_dpll(limit, crtc,
5608                                                  intel_crtc->config.port_clock,
5609                                                  refclk, NULL, &clock);
5610                 if (!ok) {
5611                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5612                         return -EINVAL;
5613                 }
5614 
5615                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5616                         /*
5617                          * Ensure we match the reduced clock's P to the target
5618                          * clock.  If the clocks don't match, we can't switch
5619                          * the display clock by using the FP0/FP1. In such case
5620                          * we will disable the LVDS downclock feature.
5621                          */
5622                         has_reduced_clock =
5623                                 dev_priv->display.find_dpll(limit, crtc,
5624                                                             dev_priv->lvds_downclock,
5625                                                             refclk, &clock,
5626                                                             &reduced_clock);
5627                 }
5628                 /* Compat-code for transition, will disappear. */
5629                 intel_crtc->config.dpll.n = clock.n;
5630                 intel_crtc->config.dpll.m1 = clock.m1;
5631                 intel_crtc->config.dpll.m2 = clock.m2;
5632                 intel_crtc->config.dpll.p1 = clock.p1;
5633                 intel_crtc->config.dpll.p2 = clock.p2;
5634         }
5635 
5636         if (IS_GEN2(dev)) {
5637                 i8xx_update_pll(intel_crtc,
5638                                 has_reduced_clock ? &reduced_clock : NULL,
5639                                 num_connectors);
5640         } else if (IS_VALLEYVIEW(dev)) {
5641                 vlv_update_pll(intel_crtc);
5642         } else {
5643                 i9xx_update_pll(intel_crtc,
5644                                 has_reduced_clock ? &reduced_clock : NULL,
5645                                 num_connectors);
5646         }
5647 
5648 skip_dpll:
5649         /* Set up the display plane register */
5650         dspcntr = DISPPLANE_GAMMA_ENABLE;
5651 
5652         if (!IS_VALLEYVIEW(dev)) {
5653                 if (pipe == 0)
5654                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5655                 else
5656                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5657         }
5658 
5659         intel_set_pipe_timings(intel_crtc);
5660 
5661         /* pipesrc and dspsize control the size that is scaled from,
5662          * which should always be the user's requested size.
5663          */
5664         I915_WRITE(DSPSIZE(plane),
5665                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5666                    (intel_crtc->config.pipe_src_w - 1));
5667         I915_WRITE(DSPPOS(plane), 0);
5668 
5669         i9xx_set_pipeconf(intel_crtc);
5670 
5671         I915_WRITE(DSPCNTR(plane), dspcntr);
5672         POSTING_READ(DSPCNTR(plane));
5673 
5674         ret = intel_pipe_set_base(crtc, x, y, fb);
5675 
5676         return ret;
5677 }
5678 
5679 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5680                                  struct intel_crtc_config *pipe_config)
5681 {
5682         struct drm_device *dev = crtc->base.dev;
5683         struct drm_i915_private *dev_priv = dev->dev_private;
5684         uint32_t tmp;
5685 
5686         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5687                 return;
5688 
5689         tmp = I915_READ(PFIT_CONTROL);
5690         if (!(tmp & PFIT_ENABLE))
5691                 return;
5692 
5693         /* Check whether the pfit is attached to our pipe. */
5694         if (INTEL_INFO(dev)->gen < 4) {
5695                 if (crtc->pipe != PIPE_B)
5696                         return;
5697         } else {
5698                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5699                         return;
5700         }
5701 
5702         pipe_config->gmch_pfit.control = tmp;
5703         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5704         if (INTEL_INFO(dev)->gen < 5)
5705                 pipe_config->gmch_pfit.lvds_border_bits =
5706                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5707 }
5708 
5709 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5710                                struct intel_crtc_config *pipe_config)
5711 {
5712         struct drm_device *dev = crtc->base.dev;
5713         struct drm_i915_private *dev_priv = dev->dev_private;
5714         int pipe = pipe_config->cpu_transcoder;
5715         intel_clock_t clock;
5716         u32 mdiv;
5717         int refclk = 100000;
5718 
5719         mutex_lock(&dev_priv->dpio_lock);
5720         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5721         mutex_unlock(&dev_priv->dpio_lock);
5722 
5723         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5724         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5725         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5726         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5727         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5728 
5729         vlv_clock(refclk, &clock);
5730 
5731         /* clock.dot is the fast clock */
5732         pipe_config->port_clock = clock.dot / 5;
5733 }
5734 
5735 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5736                                   struct intel_plane_config *plane_config)
5737 {
5738         struct drm_device *dev = crtc->base.dev;
5739         struct drm_i915_private *dev_priv = dev->dev_private;
5740         u32 val, base, offset;
5741         int pipe = crtc->pipe, plane = crtc->plane;
5742         int fourcc, pixel_format;
5743         int aligned_height;
5744 
5745         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5746         if (!crtc->base.primary->fb) {
5747                 DRM_DEBUG_KMS("failed to alloc fb\n");
5748                 return;
5749         }
5750 
5751         val = I915_READ(DSPCNTR(plane));
5752 
5753         if (INTEL_INFO(dev)->gen >= 4)
5754                 if (val & DISPPLANE_TILED)
5755                         plane_config->tiled = true;
5756 
5757         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5758         fourcc = intel_format_to_fourcc(pixel_format);
5759         crtc->base.primary->fb->pixel_format = fourcc;
5760         crtc->base.primary->fb->bits_per_pixel =
5761                 drm_format_plane_cpp(fourcc, 0) * 8;
5762 
5763         if (INTEL_INFO(dev)->gen >= 4) {
5764                 if (plane_config->tiled)
5765                         offset = I915_READ(DSPTILEOFF(plane));
5766                 else
5767                         offset = I915_READ(DSPLINOFF(plane));
5768                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5769         } else {
5770                 base = I915_READ(DSPADDR(plane));
5771         }
5772         plane_config->base = base;
5773 
5774         val = I915_READ(PIPESRC(pipe));
5775         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5776         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5777 
5778         val = I915_READ(DSPSTRIDE(pipe));
5779         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5780 
5781         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5782                                             plane_config->tiled);
5783 
5784         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5785                                    aligned_height, PAGE_SIZE);
5786 
5787         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5788                       pipe, plane, crtc->base.primary->fb->width,
5789                       crtc->base.primary->fb->height,
5790                       crtc->base.primary->fb->bits_per_pixel, base,
5791                       crtc->base.primary->fb->pitches[0],
5792                       plane_config->size);
5793 
5794 }
5795 
5796 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5797                                  struct intel_crtc_config *pipe_config)
5798 {
5799         struct drm_device *dev = crtc->base.dev;
5800         struct drm_i915_private *dev_priv = dev->dev_private;
5801         uint32_t tmp;
5802 
5803         if (!intel_display_power_enabled(dev_priv,
5804                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5805                 return false;
5806 
5807         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5808         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5809 
5810         tmp = I915_READ(PIPECONF(crtc->pipe));
5811         if (!(tmp & PIPECONF_ENABLE))
5812                 return false;
5813 
5814         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5815                 switch (tmp & PIPECONF_BPC_MASK) {
5816                 case PIPECONF_6BPC:
5817                         pipe_config->pipe_bpp = 18;
5818                         break;
5819                 case PIPECONF_8BPC:
5820                         pipe_config->pipe_bpp = 24;
5821                         break;
5822                 case PIPECONF_10BPC:
5823                         pipe_config->pipe_bpp = 30;
5824                         break;
5825                 default:
5826                         break;
5827                 }
5828         }
5829 
5830         if (INTEL_INFO(dev)->gen < 4)
5831                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5832 
5833         intel_get_pipe_timings(crtc, pipe_config);
5834 
5835         i9xx_get_pfit_config(crtc, pipe_config);
5836 
5837         if (INTEL_INFO(dev)->gen >= 4) {
5838                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5839                 pipe_config->pixel_multiplier =
5840                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5841                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5842                 pipe_config->dpll_hw_state.dpll_md = tmp;
5843         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5844                 tmp = I915_READ(DPLL(crtc->pipe));
5845                 pipe_config->pixel_multiplier =
5846                         ((tmp & SDVO_MULTIPLIER_MASK)
5847                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5848         } else {
5849                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5850                  * port and will be fixed up in the encoder->get_config
5851                  * function. */
5852                 pipe_config->pixel_multiplier = 1;
5853         }
5854         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5855         if (!IS_VALLEYVIEW(dev)) {
5856                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5857                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5858         } else {
5859                 /* Mask out read-only status bits. */
5860                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5861                                                      DPLL_PORTC_READY_MASK |
5862                                                      DPLL_PORTB_READY_MASK);
5863         }
5864 
5865         if (IS_VALLEYVIEW(dev))
5866                 vlv_crtc_clock_get(crtc, pipe_config);
5867         else
5868                 i9xx_crtc_clock_get(crtc, pipe_config);
5869 
5870         return true;
5871 }
5872 
5873 static void ironlake_init_pch_refclk(struct drm_device *dev)
5874 {
5875         struct drm_i915_private *dev_priv = dev->dev_private;
5876         struct drm_mode_config *mode_config = &dev->mode_config;
5877         struct intel_encoder *encoder;
5878         u32 val, final;
5879         bool has_lvds = false;
5880         bool has_cpu_edp = false;
5881         bool has_panel = false;
5882         bool has_ck505 = false;
5883         bool can_ssc = false;
5884 
5885         /* We need to take the global config into account */
5886         list_for_each_entry(encoder, &mode_config->encoder_list,
5887                             base.head) {
5888                 switch (encoder->type) {
5889                 case INTEL_OUTPUT_LVDS:
5890                         has_panel = true;
5891                         has_lvds = true;
5892                         break;
5893                 case INTEL_OUTPUT_EDP:
5894                         has_panel = true;
5895                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5896                                 has_cpu_edp = true;
5897                         break;
5898                 }
5899         }
5900 
5901         if (HAS_PCH_IBX(dev)) {
5902                 has_ck505 = dev_priv->vbt.display_clock_mode;
5903                 can_ssc = has_ck505;
5904         } else {
5905                 has_ck505 = false;
5906                 can_ssc = true;
5907         }
5908 
5909         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5910                       has_panel, has_lvds, has_ck505);
5911 
5912         /* Ironlake: try to setup display ref clock before DPLL
5913          * enabling. This is only under driver's control after
5914          * PCH B stepping, previous chipset stepping should be
5915          * ignoring this setting.
5916          */
5917         val = I915_READ(PCH_DREF_CONTROL);
5918 
5919         /* As we must carefully and slowly disable/enable each source in turn,
5920          * compute the final state we want first and check if we need to
5921          * make any changes at all.
5922          */
5923         final = val;
5924         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5925         if (has_ck505)
5926                 final |= DREF_NONSPREAD_CK505_ENABLE;
5927         else
5928                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5929 
5930         final &= ~DREF_SSC_SOURCE_MASK;
5931         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5932         final &= ~DREF_SSC1_ENABLE;
5933 
5934         if (has_panel) {
5935                 final |= DREF_SSC_SOURCE_ENABLE;
5936 
5937                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5938                         final |= DREF_SSC1_ENABLE;
5939 
5940                 if (has_cpu_edp) {
5941                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5942                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5943                         else
5944                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5945                 } else
5946                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5947         } else {
5948                 final |= DREF_SSC_SOURCE_DISABLE;
5949                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5950         }
5951 
5952         if (final == val)
5953                 return;
5954 
5955         /* Always enable nonspread source */
5956         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5957 
5958         if (has_ck505)
5959                 val |= DREF_NONSPREAD_CK505_ENABLE;
5960         else
5961                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5962 
5963         if (has_panel) {
5964                 val &= ~DREF_SSC_SOURCE_MASK;
5965                 val |= DREF_SSC_SOURCE_ENABLE;
5966 
5967                 /* SSC must be turned on before enabling the CPU output  */
5968                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5969                         DRM_DEBUG_KMS("Using SSC on panel\n");
5970                         val |= DREF_SSC1_ENABLE;
5971                 } else
5972                         val &= ~DREF_SSC1_ENABLE;
5973 
5974                 /* Get SSC going before enabling the outputs */
5975                 I915_WRITE(PCH_DREF_CONTROL, val);
5976                 POSTING_READ(PCH_DREF_CONTROL);
5977                 udelay(200);
5978 
5979                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5980 
5981                 /* Enable CPU source on CPU attached eDP */
5982                 if (has_cpu_edp) {
5983                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5984                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5985                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5986                         }
5987                         else
5988                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5989                 } else
5990                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5991 
5992                 I915_WRITE(PCH_DREF_CONTROL, val);
5993                 POSTING_READ(PCH_DREF_CONTROL);
5994                 udelay(200);
5995         } else {
5996                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5997 
5998                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5999 
6000                 /* Turn off CPU output */
6001                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6002 
6003                 I915_WRITE(PCH_DREF_CONTROL, val);
6004                 POSTING_READ(PCH_DREF_CONTROL);
6005                 udelay(200);
6006 
6007                 /* Turn off the SSC source */
6008                 val &= ~DREF_SSC_SOURCE_MASK;
6009                 val |= DREF_SSC_SOURCE_DISABLE;
6010 
6011                 /* Turn off SSC1 */
6012                 val &= ~DREF_SSC1_ENABLE;
6013 
6014                 I915_WRITE(PCH_DREF_CONTROL, val);
6015                 POSTING_READ(PCH_DREF_CONTROL);
6016                 udelay(200);
6017         }
6018 
6019         BUG_ON(val != final);
6020 }
6021 
6022 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6023 {
6024         uint32_t tmp;
6025 
6026         tmp = I915_READ(SOUTH_CHICKEN2);
6027         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6028         I915_WRITE(SOUTH_CHICKEN2, tmp);
6029 
6030         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6031                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6032                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6033 
6034         tmp = I915_READ(SOUTH_CHICKEN2);
6035         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6036         I915_WRITE(SOUTH_CHICKEN2, tmp);
6037 
6038         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6039                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6040                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6041 }
6042 
6043 /* WaMPhyProgramming:hsw */
6044 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6045 {
6046         uint32_t tmp;
6047 
6048         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6049         tmp &= ~(0xFF << 24);
6050         tmp |= (0x12 << 24);
6051         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6052 
6053         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6054         tmp |= (1 << 11);
6055         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6056 
6057         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6058         tmp |= (1 << 11);
6059         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6060 
6061         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6062         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6063         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6064 
6065         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6066         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6067         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6068 
6069         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6070         tmp &= ~(7 << 13);
6071         tmp |= (5 << 13);
6072         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6073 
6074         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6075         tmp &= ~(7 << 13);
6076         tmp |= (5 << 13);
6077         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6078 
6079         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6080         tmp &= ~0xFF;
6081         tmp |= 0x1C;
6082         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6083 
6084         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6085         tmp &= ~0xFF;
6086         tmp |= 0x1C;
6087         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6088 
6089         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6090         tmp &= ~(0xFF << 16);
6091         tmp |= (0x1C << 16);
6092         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6093 
6094         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6095         tmp &= ~(0xFF << 16);
6096         tmp |= (0x1C << 16);
6097         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6098 
6099         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6100         tmp |= (1 << 27);
6101         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6102 
6103         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6104         tmp |= (1 << 27);
6105         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6106 
6107         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6108         tmp &= ~(0xF << 28);
6109         tmp |= (4 << 28);
6110         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6111 
6112         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6113         tmp &= ~(0xF << 28);
6114         tmp |= (4 << 28);
6115         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6116 }
6117 
6118 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6119  * Programming" based on the parameters passed:
6120  * - Sequence to enable CLKOUT_DP
6121  * - Sequence to enable CLKOUT_DP without spread
6122  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6123  */
6124 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6125                                  bool with_fdi)
6126 {
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128         uint32_t reg, tmp;
6129 
6130         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6131                 with_spread = true;
6132         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6133                  with_fdi, "LP PCH doesn't have FDI\n"))
6134                 with_fdi = false;
6135 
6136         mutex_lock(&dev_priv->dpio_lock);
6137 
6138         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6139         tmp &= ~SBI_SSCCTL_DISABLE;
6140         tmp |= SBI_SSCCTL_PATHALT;
6141         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6142 
6143         udelay(24);
6144 
6145         if (with_spread) {
6146                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6147                 tmp &= ~SBI_SSCCTL_PATHALT;
6148                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6149 
6150                 if (with_fdi) {
6151                         lpt_reset_fdi_mphy(dev_priv);
6152                         lpt_program_fdi_mphy(dev_priv);
6153                 }
6154         }
6155 
6156         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6157                SBI_GEN0 : SBI_DBUFF0;
6158         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6159         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6160         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6161 
6162         mutex_unlock(&dev_priv->dpio_lock);
6163 }
6164 
6165 /* Sequence to disable CLKOUT_DP */
6166 static void lpt_disable_clkout_dp(struct drm_device *dev)
6167 {
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169         uint32_t reg, tmp;
6170 
6171         mutex_lock(&dev_priv->dpio_lock);
6172 
6173         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6174                SBI_GEN0 : SBI_DBUFF0;
6175         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6176         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6177         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6178 
6179         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6180         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6181                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6182                         tmp |= SBI_SSCCTL_PATHALT;
6183                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6184                         udelay(32);
6185                 }
6186                 tmp |= SBI_SSCCTL_DISABLE;
6187                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6188         }
6189 
6190         mutex_unlock(&dev_priv->dpio_lock);
6191 }
6192 
6193 static void lpt_init_pch_refclk(struct drm_device *dev)
6194 {
6195         struct drm_mode_config *mode_config = &dev->mode_config;
6196         struct intel_encoder *encoder;
6197         bool has_vga = false;
6198 
6199         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6200                 switch (encoder->type) {
6201                 case INTEL_OUTPUT_ANALOG:
6202                         has_vga = true;
6203                         break;
6204                 }
6205         }
6206 
6207         if (has_vga)
6208                 lpt_enable_clkout_dp(dev, true, true);
6209         else
6210                 lpt_disable_clkout_dp(dev);
6211 }
6212 
6213 /*
6214  * Initialize reference clocks when the driver loads
6215  */
6216 void intel_init_pch_refclk(struct drm_device *dev)
6217 {
6218         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6219                 ironlake_init_pch_refclk(dev);
6220         else if (HAS_PCH_LPT(dev))
6221                 lpt_init_pch_refclk(dev);
6222 }
6223 
6224 static int ironlake_get_refclk(struct drm_crtc *crtc)
6225 {
6226         struct drm_device *dev = crtc->dev;
6227         struct drm_i915_private *dev_priv = dev->dev_private;
6228         struct intel_encoder *encoder;
6229         int num_connectors = 0;
6230         bool is_lvds = false;
6231 
6232         for_each_encoder_on_crtc(dev, crtc, encoder) {
6233                 switch (encoder->type) {
6234                 case INTEL_OUTPUT_LVDS:
6235                         is_lvds = true;
6236                         break;
6237                 }
6238                 num_connectors++;
6239         }
6240 
6241         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6242                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6243                               dev_priv->vbt.lvds_ssc_freq);
6244                 return dev_priv->vbt.lvds_ssc_freq;
6245         }
6246 
6247         return 120000;
6248 }
6249 
6250 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6251 {
6252         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254         int pipe = intel_crtc->pipe;
6255         uint32_t val;
6256 
6257         val = 0;
6258 
6259         switch (intel_crtc->config.pipe_bpp) {
6260         case 18:
6261                 val |= PIPECONF_6BPC;
6262                 break;
6263         case 24:
6264                 val |= PIPECONF_8BPC;
6265                 break;
6266         case 30:
6267                 val |= PIPECONF_10BPC;
6268                 break;
6269         case 36:
6270                 val |= PIPECONF_12BPC;
6271                 break;
6272         default:
6273                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6274                 BUG();
6275         }
6276 
6277         if (intel_crtc->config.dither)
6278                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6279 
6280         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6281                 val |= PIPECONF_INTERLACED_ILK;
6282         else
6283                 val |= PIPECONF_PROGRESSIVE;
6284 
6285         if (intel_crtc->config.limited_color_range)
6286                 val |= PIPECONF_COLOR_RANGE_SELECT;
6287 
6288         I915_WRITE(PIPECONF(pipe), val);
6289         POSTING_READ(PIPECONF(pipe));
6290 }
6291 
6292 /*
6293  * Set up the pipe CSC unit.
6294  *
6295  * Currently only full range RGB to limited range RGB conversion
6296  * is supported, but eventually this should handle various
6297  * RGB<->YCbCr scenarios as well.
6298  */
6299 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6300 {
6301         struct drm_device *dev = crtc->dev;
6302         struct drm_i915_private *dev_priv = dev->dev_private;
6303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304         int pipe = intel_crtc->pipe;
6305         uint16_t coeff = 0x7800; /* 1.0 */
6306 
6307         /*
6308          * TODO: Check what kind of values actually come out of the pipe
6309          * with these coeff/postoff values and adjust to get the best
6310          * accuracy. Perhaps we even need to take the bpc value into
6311          * consideration.
6312          */
6313 
6314         if (intel_crtc->config.limited_color_range)
6315                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6316 
6317         /*
6318          * GY/GU and RY/RU should be the other way around according
6319          * to BSpec, but reality doesn't agree. Just set them up in
6320          * a way that results in the correct picture.
6321          */
6322         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6323         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6324 
6325         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6326         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6327 
6328         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6329         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6330 
6331         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6332         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6333         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6334 
6335         if (INTEL_INFO(dev)->gen > 6) {
6336                 uint16_t postoff = 0;
6337 
6338                 if (intel_crtc->config.limited_color_range)
6339                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6340 
6341                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6342                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6343                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6344 
6345                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6346         } else {
6347                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6348 
6349                 if (intel_crtc->config.limited_color_range)
6350                         mode |= CSC_BLACK_SCREEN_OFFSET;
6351 
6352                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6353         }
6354 }
6355 
6356 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6357 {
6358         struct drm_device *dev = crtc->dev;
6359         struct drm_i915_private *dev_priv = dev->dev_private;
6360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361         enum pipe pipe = intel_crtc->pipe;
6362         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6363         uint32_t val;
6364 
6365         val = 0;
6366 
6367         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6368                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6369 
6370         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6371                 val |= PIPECONF_INTERLACED_ILK;
6372         else
6373                 val |= PIPECONF_PROGRESSIVE;
6374 
6375         I915_WRITE(PIPECONF(cpu_transcoder), val);
6376         POSTING_READ(PIPECONF(cpu_transcoder));
6377 
6378         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6379         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6380 
6381         if (IS_BROADWELL(dev)) {
6382                 val = 0;
6383 
6384                 switch (intel_crtc->config.pipe_bpp) {
6385                 case 18:
6386                         val |= PIPEMISC_DITHER_6_BPC;
6387                         break;
6388                 case 24:
6389                         val |= PIPEMISC_DITHER_8_BPC;
6390                         break;
6391                 case 30:
6392                         val |= PIPEMISC_DITHER_10_BPC;
6393                         break;
6394                 case 36:
6395                         val |= PIPEMISC_DITHER_12_BPC;
6396                         break;
6397                 default:
6398                         /* Case prevented by pipe_config_set_bpp. */
6399                         BUG();
6400                 }
6401 
6402                 if (intel_crtc->config.dither)
6403                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6404 
6405                 I915_WRITE(PIPEMISC(pipe), val);
6406         }
6407 }
6408 
6409 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6410                                     intel_clock_t *clock,
6411                                     bool *has_reduced_clock,
6412                                     intel_clock_t *reduced_clock)
6413 {
6414         struct drm_device *dev = crtc->dev;
6415         struct drm_i915_private *dev_priv = dev->dev_private;
6416         struct intel_encoder *intel_encoder;
6417         int refclk;
6418         const intel_limit_t *limit;
6419         bool ret, is_lvds = false;
6420 
6421         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6422                 switch (intel_encoder->type) {
6423                 case INTEL_OUTPUT_LVDS:
6424                         is_lvds = true;
6425                         break;
6426                 }
6427         }
6428 
6429         refclk = ironlake_get_refclk(crtc);
6430