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Linux/drivers/gpu/drm/exynos/exynos_drm_gsc.c

  1 /*
  2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3  * Authors:
  4  *      Eunchul Kim <chulspro.kim@samsung.com>
  5  *      Jinyoung Jeon <jy0.jeon@samsung.com>
  6  *      Sangmin Lee <lsmin.lee@samsung.com>
  7  *
  8  * This program is free software; you can redistribute  it and/or modify it
  9  * under  the terms of  the GNU General  Public License as published by the
 10  * Free Software Foundation;  either version 2 of the  License, or (at your
 11  * option) any later version.
 12  *
 13  */
 14 #include <linux/kernel.h>
 15 #include <linux/platform_device.h>
 16 #include <linux/clk.h>
 17 #include <linux/pm_runtime.h>
 18 #include <plat/map-base.h>
 19 
 20 #include <drm/drmP.h>
 21 #include <drm/exynos_drm.h>
 22 #include "regs-gsc.h"
 23 #include "exynos_drm_drv.h"
 24 #include "exynos_drm_ipp.h"
 25 #include "exynos_drm_gsc.h"
 26 
 27 /*
 28  * GSC stands for General SCaler and
 29  * supports image scaler/rotator and input/output DMA operations.
 30  * input DMA reads image data from the memory.
 31  * output DMA writes image data to memory.
 32  * GSC supports image rotation and image effect functions.
 33  *
 34  * M2M operation : supports crop/scale/rotation/csc so on.
 35  * Memory ----> GSC H/W ----> Memory.
 36  * Writeback operation : supports cloned screen with FIMD.
 37  * FIMD ----> GSC H/W ----> Memory.
 38  * Output operation : supports direct display using local path.
 39  * Memory ----> GSC H/W ----> FIMD, Mixer.
 40  */
 41 
 42 /*
 43  * TODO
 44  * 1. check suspend/resume api if needed.
 45  * 2. need to check use case platform_device_id.
 46  * 3. check src/dst size with, height.
 47  * 4. added check_prepare api for right register.
 48  * 5. need to add supported list in prop_list.
 49  * 6. check prescaler/scaler optimization.
 50  */
 51 
 52 #define GSC_MAX_DEVS    4
 53 #define GSC_MAX_SRC             4
 54 #define GSC_MAX_DST             16
 55 #define GSC_RESET_TIMEOUT       50
 56 #define GSC_BUF_STOP    1
 57 #define GSC_BUF_START   2
 58 #define GSC_REG_SZ              16
 59 #define GSC_WIDTH_ITU_709       1280
 60 #define GSC_SC_UP_MAX_RATIO             65536
 61 #define GSC_SC_DOWN_RATIO_7_8           74898
 62 #define GSC_SC_DOWN_RATIO_6_8           87381
 63 #define GSC_SC_DOWN_RATIO_5_8           104857
 64 #define GSC_SC_DOWN_RATIO_4_8           131072
 65 #define GSC_SC_DOWN_RATIO_3_8           174762
 66 #define GSC_SC_DOWN_RATIO_2_8           262144
 67 #define GSC_REFRESH_MIN 12
 68 #define GSC_REFRESH_MAX 60
 69 #define GSC_CROP_MAX    8192
 70 #define GSC_CROP_MIN    32
 71 #define GSC_SCALE_MAX   4224
 72 #define GSC_SCALE_MIN   32
 73 #define GSC_COEF_RATIO  7
 74 #define GSC_COEF_PHASE  9
 75 #define GSC_COEF_ATTR   16
 76 #define GSC_COEF_H_8T   8
 77 #define GSC_COEF_V_4T   4
 78 #define GSC_COEF_DEPTH  3
 79 
 80 #define get_gsc_context(dev)    platform_get_drvdata(to_platform_device(dev))
 81 #define get_ctx_from_ippdrv(ippdrv)     container_of(ippdrv,\
 82                                         struct gsc_context, ippdrv);
 83 #define gsc_read(offset)                readl(ctx->regs + (offset))
 84 #define gsc_write(cfg, offset)  writel(cfg, ctx->regs + (offset))
 85 
 86 /*
 87  * A structure of scaler.
 88  *
 89  * @range: narrow, wide.
 90  * @pre_shfactor: pre sclaer shift factor.
 91  * @pre_hratio: horizontal ratio of the prescaler.
 92  * @pre_vratio: vertical ratio of the prescaler.
 93  * @main_hratio: the main scaler's horizontal ratio.
 94  * @main_vratio: the main scaler's vertical ratio.
 95  */
 96 struct gsc_scaler {
 97         bool    range;
 98         u32     pre_shfactor;
 99         u32     pre_hratio;
100         u32     pre_vratio;
101         unsigned long main_hratio;
102         unsigned long main_vratio;
103 };
104 
105 /*
106  * A structure of scaler capability.
107  *
108  * find user manual 49.2 features.
109  * @tile_w: tile mode or rotation width.
110  * @tile_h: tile mode or rotation height.
111  * @w: other cases width.
112  * @h: other cases height.
113  */
114 struct gsc_capability {
115         /* tile or rotation */
116         u32     tile_w;
117         u32     tile_h;
118         /* other cases */
119         u32     w;
120         u32     h;
121 };
122 
123 /*
124  * A structure of gsc context.
125  *
126  * @ippdrv: prepare initialization using ippdrv.
127  * @regs_res: register resources.
128  * @regs: memory mapped io registers.
129  * @lock: locking of operations.
130  * @gsc_clk: gsc gate clock.
131  * @sc: scaler infomations.
132  * @id: gsc id.
133  * @irq: irq number.
134  * @rotation: supports rotation of src.
135  * @suspended: qos operations.
136  */
137 struct gsc_context {
138         struct exynos_drm_ippdrv        ippdrv;
139         struct resource *regs_res;
140         void __iomem    *regs;
141         struct mutex    lock;
142         struct clk      *gsc_clk;
143         struct gsc_scaler       sc;
144         int     id;
145         int     irq;
146         bool    rotation;
147         bool    suspended;
148 };
149 
150 /* 8-tap Filter Coefficient */
151 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
152         {       /* Ratio <= 65536 (~8:8) */
153                 {  0,  0,   0, 128,   0,   0,  0,  0 },
154                 { -1,  2,  -6, 127,   7,  -2,  1,  0 },
155                 { -1,  4, -12, 125,  16,  -5,  1,  0 },
156                 { -1,  5, -15, 120,  25,  -8,  2,  0 },
157                 { -1,  6, -18, 114,  35, -10,  3, -1 },
158                 { -1,  6, -20, 107,  46, -13,  4, -1 },
159                 { -2,  7, -21,  99,  57, -16,  5, -1 },
160                 { -1,  6, -20,  89,  68, -18,  5, -1 },
161                 { -1,  6, -20,  79,  79, -20,  6, -1 },
162                 { -1,  5, -18,  68,  89, -20,  6, -1 },
163                 { -1,  5, -16,  57,  99, -21,  7, -2 },
164                 { -1,  4, -13,  46, 107, -20,  6, -1 },
165                 { -1,  3, -10,  35, 114, -18,  6, -1 },
166                 {  0,  2,  -8,  25, 120, -15,  5, -1 },
167                 {  0,  1,  -5,  16, 125, -12,  4, -1 },
168                 {  0,  1,  -2,   7, 127,  -6,  2, -1 }
169         }, {    /* 65536 < Ratio <= 74898 (~8:7) */
170                 {  3, -8,  14, 111,  13,  -8,  3,  0 },
171                 {  2, -6,   7, 112,  21, -10,  3, -1 },
172                 {  2, -4,   1, 110,  28, -12,  4, -1 },
173                 {  1, -2,  -3, 106,  36, -13,  4, -1 },
174                 {  1, -1,  -7, 103,  44, -15,  4, -1 },
175                 {  1,  1, -11,  97,  53, -16,  4, -1 },
176                 {  0,  2, -13,  91,  61, -16,  4, -1 },
177                 {  0,  3, -15,  85,  69, -17,  4, -1 },
178                 {  0,  3, -16,  77,  77, -16,  3,  0 },
179                 { -1,  4, -17,  69,  85, -15,  3,  0 },
180                 { -1,  4, -16,  61,  91, -13,  2,  0 },
181                 { -1,  4, -16,  53,  97, -11,  1,  1 },
182                 { -1,  4, -15,  44, 103,  -7, -1,  1 },
183                 { -1,  4, -13,  36, 106,  -3, -2,  1 },
184                 { -1,  4, -12,  28, 110,   1, -4,  2 },
185                 { -1,  3, -10,  21, 112,   7, -6,  2 }
186         }, {    /* 74898 < Ratio <= 87381 (~8:6) */
187                 { 2, -11,  25,  96, 25, -11,   2,  0 },
188                 { 2, -10,  19,  96, 31, -12,   2,  0 },
189                 { 2,  -9,  14,  94, 37, -12,   2,  0 },
190                 { 2,  -8,  10,  92, 43, -12,   1,  0 },
191                 { 2,  -7,   5,  90, 49, -12,   1,  0 },
192                 { 2,  -5,   1,  86, 55, -12,   0,  1 },
193                 { 2,  -4,  -2,  82, 61, -11,  -1,  1 },
194                 { 1,  -3,  -5,  77, 67,  -9,  -1,  1 },
195                 { 1,  -2,  -7,  72, 72,  -7,  -2,  1 },
196                 { 1,  -1,  -9,  67, 77,  -5,  -3,  1 },
197                 { 1,  -1, -11,  61, 82,  -2,  -4,  2 },
198                 { 1,   0, -12,  55, 86,   1,  -5,  2 },
199                 { 0,   1, -12,  49, 90,   5,  -7,  2 },
200                 { 0,   1, -12,  43, 92,  10,  -8,  2 },
201                 { 0,   2, -12,  37, 94,  14,  -9,  2 },
202                 { 0,   2, -12,  31, 96,  19, -10,  2 }
203         }, {    /* 87381 < Ratio <= 104857 (~8:5) */
204                 { -1,  -8, 33,  80, 33,  -8,  -1,  0 },
205                 { -1,  -8, 28,  80, 37,  -7,  -2,  1 },
206                 {  0,  -8, 24,  79, 41,  -7,  -2,  1 },
207                 {  0,  -8, 20,  78, 46,  -6,  -3,  1 },
208                 {  0,  -8, 16,  76, 50,  -4,  -3,  1 },
209                 {  0,  -7, 13,  74, 54,  -3,  -4,  1 },
210                 {  1,  -7, 10,  71, 58,  -1,  -5,  1 },
211                 {  1,  -6,  6,  68, 62,   1,  -5,  1 },
212                 {  1,  -6,  4,  65, 65,   4,  -6,  1 },
213                 {  1,  -5,  1,  62, 68,   6,  -6,  1 },
214                 {  1,  -5, -1,  58, 71,  10,  -7,  1 },
215                 {  1,  -4, -3,  54, 74,  13,  -7,  0 },
216                 {  1,  -3, -4,  50, 76,  16,  -8,  0 },
217                 {  1,  -3, -6,  46, 78,  20,  -8,  0 },
218                 {  1,  -2, -7,  41, 79,  24,  -8,  0 },
219                 {  1,  -2, -7,  37, 80,  28,  -8, -1 }
220         }, {    /* 104857 < Ratio <= 131072 (~8:4) */
221                 { -3,   0, 35,  64, 35,   0,  -3,  0 },
222                 { -3,  -1, 32,  64, 38,   1,  -3,  0 },
223                 { -2,  -2, 29,  63, 41,   2,  -3,  0 },
224                 { -2,  -3, 27,  63, 43,   4,  -4,  0 },
225                 { -2,  -3, 24,  61, 46,   6,  -4,  0 },
226                 { -2,  -3, 21,  60, 49,   7,  -4,  0 },
227                 { -1,  -4, 19,  59, 51,   9,  -4, -1 },
228                 { -1,  -4, 16,  57, 53,  12,  -4, -1 },
229                 { -1,  -4, 14,  55, 55,  14,  -4, -1 },
230                 { -1,  -4, 12,  53, 57,  16,  -4, -1 },
231                 { -1,  -4,  9,  51, 59,  19,  -4, -1 },
232                 {  0,  -4,  7,  49, 60,  21,  -3, -2 },
233                 {  0,  -4,  6,  46, 61,  24,  -3, -2 },
234                 {  0,  -4,  4,  43, 63,  27,  -3, -2 },
235                 {  0,  -3,  2,  41, 63,  29,  -2, -2 },
236                 {  0,  -3,  1,  38, 64,  32,  -1, -3 }
237         }, {    /* 131072 < Ratio <= 174762 (~8:3) */
238                 { -1,   8, 33,  48, 33,   8,  -1,  0 },
239                 { -1,   7, 31,  49, 35,   9,  -1, -1 },
240                 { -1,   6, 30,  49, 36,  10,  -1, -1 },
241                 { -1,   5, 28,  48, 38,  12,  -1, -1 },
242                 { -1,   4, 26,  48, 39,  13,   0, -1 },
243                 { -1,   3, 24,  47, 41,  15,   0, -1 },
244                 { -1,   2, 23,  47, 42,  16,   0, -1 },
245                 { -1,   2, 21,  45, 43,  18,   1, -1 },
246                 { -1,   1, 19,  45, 45,  19,   1, -1 },
247                 { -1,   1, 18,  43, 45,  21,   2, -1 },
248                 { -1,   0, 16,  42, 47,  23,   2, -1 },
249                 { -1,   0, 15,  41, 47,  24,   3, -1 },
250                 { -1,   0, 13,  39, 48,  26,   4, -1 },
251                 { -1,  -1, 12,  38, 48,  28,   5, -1 },
252                 { -1,  -1, 10,  36, 49,  30,   6, -1 },
253                 { -1,  -1,  9,  35, 49,  31,   7, -1 }
254         }, {    /* 174762 < Ratio <= 262144 (~8:2) */
255                 {  2,  13, 30,  38, 30,  13,   2,  0 },
256                 {  2,  12, 29,  38, 30,  14,   3,  0 },
257                 {  2,  11, 28,  38, 31,  15,   3,  0 },
258                 {  2,  10, 26,  38, 32,  16,   4,  0 },
259                 {  1,  10, 26,  37, 33,  17,   4,  0 },
260                 {  1,   9, 24,  37, 34,  18,   5,  0 },
261                 {  1,   8, 24,  37, 34,  19,   5,  0 },
262                 {  1,   7, 22,  36, 35,  20,   6,  1 },
263                 {  1,   6, 21,  36, 36,  21,   6,  1 },
264                 {  1,   6, 20,  35, 36,  22,   7,  1 },
265                 {  0,   5, 19,  34, 37,  24,   8,  1 },
266                 {  0,   5, 18,  34, 37,  24,   9,  1 },
267                 {  0,   4, 17,  33, 37,  26,  10,  1 },
268                 {  0,   4, 16,  32, 38,  26,  10,  2 },
269                 {  0,   3, 15,  31, 38,  28,  11,  2 },
270                 {  0,   3, 14,  30, 38,  29,  12,  2 }
271         }
272 };
273 
274 /* 4-tap Filter Coefficient */
275 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
276         {       /* Ratio <= 65536 (~8:8) */
277                 {  0, 128,   0,  0 },
278                 { -4, 127,   5,  0 },
279                 { -6, 124,  11, -1 },
280                 { -8, 118,  19, -1 },
281                 { -8, 111,  27, -2 },
282                 { -8, 102,  37, -3 },
283                 { -8,  92,  48, -4 },
284                 { -7,  81,  59, -5 },
285                 { -6,  70,  70, -6 },
286                 { -5,  59,  81, -7 },
287                 { -4,  48,  92, -8 },
288                 { -3,  37, 102, -8 },
289                 { -2,  27, 111, -8 },
290                 { -1,  19, 118, -8 },
291                 { -1,  11, 124, -6 },
292                 {  0,   5, 127, -4 }
293         }, {    /* 65536 < Ratio <= 74898 (~8:7) */
294                 {  8, 112,   8,  0 },
295                 {  4, 111,  14, -1 },
296                 {  1, 109,  20, -2 },
297                 { -2, 105,  27, -2 },
298                 { -3, 100,  34, -3 },
299                 { -5,  93,  43, -3 },
300                 { -5,  86,  51, -4 },
301                 { -5,  77,  60, -4 },
302                 { -5,  69,  69, -5 },
303                 { -4,  60,  77, -5 },
304                 { -4,  51,  86, -5 },
305                 { -3,  43,  93, -5 },
306                 { -3,  34, 100, -3 },
307                 { -2,  27, 105, -2 },
308                 { -2,  20, 109,  1 },
309                 { -1,  14, 111,  4 }
310         }, {    /* 74898 < Ratio <= 87381 (~8:6) */
311                 { 16,  96,  16,  0 },
312                 { 12,  97,  21, -2 },
313                 {  8,  96,  26, -2 },
314                 {  5,  93,  32, -2 },
315                 {  2,  89,  39, -2 },
316                 {  0,  84,  46, -2 },
317                 { -1,  79,  53, -3 },
318                 { -2,  73,  59, -2 },
319                 { -2,  66,  66, -2 },
320                 { -2,  59,  73, -2 },
321                 { -3,  53,  79, -1 },
322                 { -2,  46,  84,  0 },
323                 { -2,  39,  89,  2 },
324                 { -2,  32,  93,  5 },
325                 { -2,  26,  96,  8 },
326                 { -2,  21,  97, 12 }
327         }, {    /* 87381 < Ratio <= 104857 (~8:5) */
328                 { 22,  84,  22,  0 },
329                 { 18,  85,  26, -1 },
330                 { 14,  84,  31, -1 },
331                 { 11,  82,  36, -1 },
332                 {  8,  79,  42, -1 },
333                 {  6,  76,  47, -1 },
334                 {  4,  72,  52,  0 },
335                 {  2,  68,  58,  0 },
336                 {  1,  63,  63,  1 },
337                 {  0,  58,  68,  2 },
338                 {  0,  52,  72,  4 },
339                 { -1,  47,  76,  6 },
340                 { -1,  42,  79,  8 },
341                 { -1,  36,  82, 11 },
342                 { -1,  31,  84, 14 },
343                 { -1,  26,  85, 18 }
344         }, {    /* 104857 < Ratio <= 131072 (~8:4) */
345                 { 26,  76,  26,  0 },
346                 { 22,  76,  30,  0 },
347                 { 19,  75,  34,  0 },
348                 { 16,  73,  38,  1 },
349                 { 13,  71,  43,  1 },
350                 { 10,  69,  47,  2 },
351                 {  8,  66,  51,  3 },
352                 {  6,  63,  55,  4 },
353                 {  5,  59,  59,  5 },
354                 {  4,  55,  63,  6 },
355                 {  3,  51,  66,  8 },
356                 {  2,  47,  69, 10 },
357                 {  1,  43,  71, 13 },
358                 {  1,  38,  73, 16 },
359                 {  0,  34,  75, 19 },
360                 {  0,  30,  76, 22 }
361         }, {    /* 131072 < Ratio <= 174762 (~8:3) */
362                 { 29,  70,  29,  0 },
363                 { 26,  68,  32,  2 },
364                 { 23,  67,  36,  2 },
365                 { 20,  66,  39,  3 },
366                 { 17,  65,  43,  3 },
367                 { 15,  63,  46,  4 },
368                 { 12,  61,  50,  5 },
369                 { 10,  58,  53,  7 },
370                 {  8,  56,  56,  8 },
371                 {  7,  53,  58, 10 },
372                 {  5,  50,  61, 12 },
373                 {  4,  46,  63, 15 },
374                 {  3,  43,  65, 17 },
375                 {  3,  39,  66, 20 },
376                 {  2,  36,  67, 23 },
377                 {  2,  32,  68, 26 }
378         }, {    /* 174762 < Ratio <= 262144 (~8:2) */
379                 { 32,  64,  32,  0 },
380                 { 28,  63,  34,  3 },
381                 { 25,  62,  37,  4 },
382                 { 22,  62,  40,  4 },
383                 { 19,  61,  43,  5 },
384                 { 17,  59,  46,  6 },
385                 { 15,  58,  48,  7 },
386                 { 13,  55,  51,  9 },
387                 { 11,  53,  53, 11 },
388                 {  9,  51,  55, 13 },
389                 {  7,  48,  58, 15 },
390                 {  6,  46,  59, 17 },
391                 {  5,  43,  61, 19 },
392                 {  4,  40,  62, 22 },
393                 {  4,  37,  62, 25 },
394                 {  3,  34,  63, 28 }
395         }
396 };
397 
398 static int gsc_sw_reset(struct gsc_context *ctx)
399 {
400         u32 cfg;
401         int count = GSC_RESET_TIMEOUT;
402 
403         /* s/w reset */
404         cfg = (GSC_SW_RESET_SRESET);
405         gsc_write(cfg, GSC_SW_RESET);
406 
407         /* wait s/w reset complete */
408         while (count--) {
409                 cfg = gsc_read(GSC_SW_RESET);
410                 if (!cfg)
411                         break;
412                 usleep_range(1000, 2000);
413         }
414 
415         if (cfg) {
416                 DRM_ERROR("failed to reset gsc h/w.\n");
417                 return -EBUSY;
418         }
419 
420         /* reset sequence */
421         cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
422         cfg |= (GSC_IN_BASE_ADDR_MASK |
423                 GSC_IN_BASE_ADDR_PINGPONG(0));
424         gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
425         gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
426         gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
427 
428         cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
429         cfg |= (GSC_OUT_BASE_ADDR_MASK |
430                 GSC_OUT_BASE_ADDR_PINGPONG(0));
431         gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
432         gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
433         gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
434 
435         return 0;
436 }
437 
438 static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable)
439 {
440         u32 gscblk_cfg;
441 
442         gscblk_cfg = readl(SYSREG_GSCBLK_CFG1);
443 
444         if (enable)
445                 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |
446                                 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |
447                                 GSC_BLK_SW_RESET_WB_DEST(ctx->id);
448         else
449                 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);
450 
451         writel(gscblk_cfg, SYSREG_GSCBLK_CFG1);
452 }
453 
454 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
455                 bool overflow, bool done)
456 {
457         u32 cfg;
458 
459         DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
460                         enable, overflow, done);
461 
462         cfg = gsc_read(GSC_IRQ);
463         cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
464 
465         if (enable)
466                 cfg |= GSC_IRQ_ENABLE;
467         else
468                 cfg &= ~GSC_IRQ_ENABLE;
469 
470         if (overflow)
471                 cfg &= ~GSC_IRQ_OR_MASK;
472         else
473                 cfg |= GSC_IRQ_OR_MASK;
474 
475         if (done)
476                 cfg &= ~GSC_IRQ_FRMDONE_MASK;
477         else
478                 cfg |= GSC_IRQ_FRMDONE_MASK;
479 
480         gsc_write(cfg, GSC_IRQ);
481 }
482 
483 
484 static int gsc_src_set_fmt(struct device *dev, u32 fmt)
485 {
486         struct gsc_context *ctx = get_gsc_context(dev);
487         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
488         u32 cfg;
489 
490         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
491 
492         cfg = gsc_read(GSC_IN_CON);
493         cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
494                  GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
495                  GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
496                  GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
497 
498         switch (fmt) {
499         case DRM_FORMAT_RGB565:
500                 cfg |= GSC_IN_RGB565;
501                 break;
502         case DRM_FORMAT_XRGB8888:
503                 cfg |= GSC_IN_XRGB8888;
504                 break;
505         case DRM_FORMAT_BGRX8888:
506                 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
507                 break;
508         case DRM_FORMAT_YUYV:
509                 cfg |= (GSC_IN_YUV422_1P |
510                         GSC_IN_YUV422_1P_ORDER_LSB_Y |
511                         GSC_IN_CHROMA_ORDER_CBCR);
512                 break;
513         case DRM_FORMAT_YVYU:
514                 cfg |= (GSC_IN_YUV422_1P |
515                         GSC_IN_YUV422_1P_ORDER_LSB_Y |
516                         GSC_IN_CHROMA_ORDER_CRCB);
517                 break;
518         case DRM_FORMAT_UYVY:
519                 cfg |= (GSC_IN_YUV422_1P |
520                         GSC_IN_YUV422_1P_OEDER_LSB_C |
521                         GSC_IN_CHROMA_ORDER_CBCR);
522                 break;
523         case DRM_FORMAT_VYUY:
524                 cfg |= (GSC_IN_YUV422_1P |
525                         GSC_IN_YUV422_1P_OEDER_LSB_C |
526                         GSC_IN_CHROMA_ORDER_CRCB);
527                 break;
528         case DRM_FORMAT_NV21:
529         case DRM_FORMAT_NV61:
530                 cfg |= (GSC_IN_CHROMA_ORDER_CRCB |
531                         GSC_IN_YUV420_2P);
532                 break;
533         case DRM_FORMAT_YUV422:
534                 cfg |= GSC_IN_YUV422_3P;
535                 break;
536         case DRM_FORMAT_YUV420:
537         case DRM_FORMAT_YVU420:
538                 cfg |= GSC_IN_YUV420_3P;
539                 break;
540         case DRM_FORMAT_NV12:
541         case DRM_FORMAT_NV16:
542                 cfg |= (GSC_IN_CHROMA_ORDER_CBCR |
543                         GSC_IN_YUV420_2P);
544                 break;
545         case DRM_FORMAT_NV12MT:
546                 cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
547                 break;
548         default:
549                 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
550                 return -EINVAL;
551         }
552 
553         gsc_write(cfg, GSC_IN_CON);
554 
555         return 0;
556 }
557 
558 static int gsc_src_set_transf(struct device *dev,
559                 enum drm_exynos_degree degree,
560                 enum drm_exynos_flip flip, bool *swap)
561 {
562         struct gsc_context *ctx = get_gsc_context(dev);
563         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
564         u32 cfg;
565 
566         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
567 
568         cfg = gsc_read(GSC_IN_CON);
569         cfg &= ~GSC_IN_ROT_MASK;
570 
571         switch (degree) {
572         case EXYNOS_DRM_DEGREE_0:
573                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
574                         cfg |= GSC_IN_ROT_XFLIP;
575                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
576                         cfg |= GSC_IN_ROT_YFLIP;
577                 break;
578         case EXYNOS_DRM_DEGREE_90:
579                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
580                         cfg |= GSC_IN_ROT_90_XFLIP;
581                 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
582                         cfg |= GSC_IN_ROT_90_YFLIP;
583                 else
584                         cfg |= GSC_IN_ROT_90;
585                 break;
586         case EXYNOS_DRM_DEGREE_180:
587                 cfg |= GSC_IN_ROT_180;
588                 break;
589         case EXYNOS_DRM_DEGREE_270:
590                 cfg |= GSC_IN_ROT_270;
591                 break;
592         default:
593                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
594                 return -EINVAL;
595         }
596 
597         gsc_write(cfg, GSC_IN_CON);
598 
599         ctx->rotation = cfg &
600                 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
601         *swap = ctx->rotation;
602 
603         return 0;
604 }
605 
606 static int gsc_src_set_size(struct device *dev, int swap,
607                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
608 {
609         struct gsc_context *ctx = get_gsc_context(dev);
610         struct drm_exynos_pos img_pos = *pos;
611         struct gsc_scaler *sc = &ctx->sc;
612         u32 cfg;
613 
614         DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
615                 swap, pos->x, pos->y, pos->w, pos->h);
616 
617         if (swap) {
618                 img_pos.w = pos->h;
619                 img_pos.h = pos->w;
620         }
621 
622         /* pixel offset */
623         cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
624                 GSC_SRCIMG_OFFSET_Y(img_pos.y));
625         gsc_write(cfg, GSC_SRCIMG_OFFSET);
626 
627         /* cropped size */
628         cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
629                 GSC_CROPPED_HEIGHT(img_pos.h));
630         gsc_write(cfg, GSC_CROPPED_SIZE);
631 
632         DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
633 
634         /* original size */
635         cfg = gsc_read(GSC_SRCIMG_SIZE);
636         cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
637                 GSC_SRCIMG_WIDTH_MASK);
638 
639         cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
640                 GSC_SRCIMG_HEIGHT(sz->vsize));
641 
642         gsc_write(cfg, GSC_SRCIMG_SIZE);
643 
644         cfg = gsc_read(GSC_IN_CON);
645         cfg &= ~GSC_IN_RGB_TYPE_MASK;
646 
647         DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
648 
649         if (pos->w >= GSC_WIDTH_ITU_709)
650                 if (sc->range)
651                         cfg |= GSC_IN_RGB_HD_WIDE;
652                 else
653                         cfg |= GSC_IN_RGB_HD_NARROW;
654         else
655                 if (sc->range)
656                         cfg |= GSC_IN_RGB_SD_WIDE;
657                 else
658                         cfg |= GSC_IN_RGB_SD_NARROW;
659 
660         gsc_write(cfg, GSC_IN_CON);
661 
662         return 0;
663 }
664 
665 static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
666                 enum drm_exynos_ipp_buf_type buf_type)
667 {
668         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
669         bool masked;
670         u32 cfg;
671         u32 mask = 0x00000001 << buf_id;
672 
673         DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
674 
675         /* mask register set */
676         cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
677 
678         switch (buf_type) {
679         case IPP_BUF_ENQUEUE:
680                 masked = false;
681                 break;
682         case IPP_BUF_DEQUEUE:
683                 masked = true;
684                 break;
685         default:
686                 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
687                 return -EINVAL;
688         }
689 
690         /* sequence id */
691         cfg &= ~mask;
692         cfg |= masked << buf_id;
693         gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
694         gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
695         gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
696 
697         return 0;
698 }
699 
700 static int gsc_src_set_addr(struct device *dev,
701                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
702                 enum drm_exynos_ipp_buf_type buf_type)
703 {
704         struct gsc_context *ctx = get_gsc_context(dev);
705         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
706         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
707         struct drm_exynos_ipp_property *property;
708 
709         if (!c_node) {
710                 DRM_ERROR("failed to get c_node.\n");
711                 return -EFAULT;
712         }
713 
714         property = &c_node->property;
715 
716         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
717                 property->prop_id, buf_id, buf_type);
718 
719         if (buf_id > GSC_MAX_SRC) {
720                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
721                 return -EINVAL;
722         }
723 
724         /* address register set */
725         switch (buf_type) {
726         case IPP_BUF_ENQUEUE:
727                 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
728                         GSC_IN_BASE_ADDR_Y(buf_id));
729                 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
730                         GSC_IN_BASE_ADDR_CB(buf_id));
731                 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
732                         GSC_IN_BASE_ADDR_CR(buf_id));
733                 break;
734         case IPP_BUF_DEQUEUE:
735                 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
736                 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
737                 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
738                 break;
739         default:
740                 /* bypass */
741                 break;
742         }
743 
744         return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
745 }
746 
747 static struct exynos_drm_ipp_ops gsc_src_ops = {
748         .set_fmt = gsc_src_set_fmt,
749         .set_transf = gsc_src_set_transf,
750         .set_size = gsc_src_set_size,
751         .set_addr = gsc_src_set_addr,
752 };
753 
754 static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
755 {
756         struct gsc_context *ctx = get_gsc_context(dev);
757         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
758         u32 cfg;
759 
760         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
761 
762         cfg = gsc_read(GSC_OUT_CON);
763         cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
764                  GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
765                  GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
766                  GSC_OUT_GLOBAL_ALPHA_MASK);
767 
768         switch (fmt) {
769         case DRM_FORMAT_RGB565:
770                 cfg |= GSC_OUT_RGB565;
771                 break;
772         case DRM_FORMAT_XRGB8888:
773                 cfg |= GSC_OUT_XRGB8888;
774                 break;
775         case DRM_FORMAT_BGRX8888:
776                 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
777                 break;
778         case DRM_FORMAT_YUYV:
779                 cfg |= (GSC_OUT_YUV422_1P |
780                         GSC_OUT_YUV422_1P_ORDER_LSB_Y |
781                         GSC_OUT_CHROMA_ORDER_CBCR);
782                 break;
783         case DRM_FORMAT_YVYU:
784                 cfg |= (GSC_OUT_YUV422_1P |
785                         GSC_OUT_YUV422_1P_ORDER_LSB_Y |
786                         GSC_OUT_CHROMA_ORDER_CRCB);
787                 break;
788         case DRM_FORMAT_UYVY:
789                 cfg |= (GSC_OUT_YUV422_1P |
790                         GSC_OUT_YUV422_1P_OEDER_LSB_C |
791                         GSC_OUT_CHROMA_ORDER_CBCR);
792                 break;
793         case DRM_FORMAT_VYUY:
794                 cfg |= (GSC_OUT_YUV422_1P |
795                         GSC_OUT_YUV422_1P_OEDER_LSB_C |
796                         GSC_OUT_CHROMA_ORDER_CRCB);
797                 break;
798         case DRM_FORMAT_NV21:
799         case DRM_FORMAT_NV61:
800                 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
801                 break;
802         case DRM_FORMAT_YUV422:
803         case DRM_FORMAT_YUV420:
804         case DRM_FORMAT_YVU420:
805                 cfg |= GSC_OUT_YUV420_3P;
806                 break;
807         case DRM_FORMAT_NV12:
808         case DRM_FORMAT_NV16:
809                 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |
810                         GSC_OUT_YUV420_2P);
811                 break;
812         case DRM_FORMAT_NV12MT:
813                 cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE);
814                 break;
815         default:
816                 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
817                 return -EINVAL;
818         }
819 
820         gsc_write(cfg, GSC_OUT_CON);
821 
822         return 0;
823 }
824 
825 static int gsc_dst_set_transf(struct device *dev,
826                 enum drm_exynos_degree degree,
827                 enum drm_exynos_flip flip, bool *swap)
828 {
829         struct gsc_context *ctx = get_gsc_context(dev);
830         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
831         u32 cfg;
832 
833         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
834 
835         cfg = gsc_read(GSC_IN_CON);
836         cfg &= ~GSC_IN_ROT_MASK;
837 
838         switch (degree) {
839         case EXYNOS_DRM_DEGREE_0:
840                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
841                         cfg |= GSC_IN_ROT_XFLIP;
842                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
843                         cfg |= GSC_IN_ROT_YFLIP;
844                 break;
845         case EXYNOS_DRM_DEGREE_90:
846                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
847                         cfg |= GSC_IN_ROT_90_XFLIP;
848                 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
849                         cfg |= GSC_IN_ROT_90_YFLIP;
850                 else
851                         cfg |= GSC_IN_ROT_90;
852                 break;
853         case EXYNOS_DRM_DEGREE_180:
854                 cfg |= GSC_IN_ROT_180;
855                 break;
856         case EXYNOS_DRM_DEGREE_270:
857                 cfg |= GSC_IN_ROT_270;
858                 break;
859         default:
860                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
861                 return -EINVAL;
862         }
863 
864         gsc_write(cfg, GSC_IN_CON);
865 
866         ctx->rotation = cfg &
867                 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
868         *swap = ctx->rotation;
869 
870         return 0;
871 }
872 
873 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
874 {
875         DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
876 
877         if (src >= dst * 8) {
878                 DRM_ERROR("failed to make ratio and shift.\n");
879                 return -EINVAL;
880         } else if (src >= dst * 4)
881                 *ratio = 4;
882         else if (src >= dst * 2)
883                 *ratio = 2;
884         else
885                 *ratio = 1;
886 
887         return 0;
888 }
889 
890 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
891 {
892         if (hratio == 4 && vratio == 4)
893                 *shfactor = 4;
894         else if ((hratio == 4 && vratio == 2) ||
895                  (hratio == 2 && vratio == 4))
896                 *shfactor = 3;
897         else if ((hratio == 4 && vratio == 1) ||
898                  (hratio == 1 && vratio == 4) ||
899                  (hratio == 2 && vratio == 2))
900                 *shfactor = 2;
901         else if (hratio == 1 && vratio == 1)
902                 *shfactor = 0;
903         else
904                 *shfactor = 1;
905 }
906 
907 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
908                 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
909 {
910         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
911         u32 cfg;
912         u32 src_w, src_h, dst_w, dst_h;
913         int ret = 0;
914 
915         src_w = src->w;
916         src_h = src->h;
917 
918         if (ctx->rotation) {
919                 dst_w = dst->h;
920                 dst_h = dst->w;
921         } else {
922                 dst_w = dst->w;
923                 dst_h = dst->h;
924         }
925 
926         ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
927         if (ret) {
928                 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
929                 return ret;
930         }
931 
932         ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
933         if (ret) {
934                 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
935                 return ret;
936         }
937 
938         DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n",
939                 sc->pre_hratio, sc->pre_vratio);
940 
941         sc->main_hratio = (src_w << 16) / dst_w;
942         sc->main_vratio = (src_h << 16) / dst_h;
943 
944         DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
945                 sc->main_hratio, sc->main_vratio);
946 
947         gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
948                 &sc->pre_shfactor);
949 
950         DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor);
951 
952         cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
953                 GSC_PRESC_H_RATIO(sc->pre_hratio) |
954                 GSC_PRESC_V_RATIO(sc->pre_vratio));
955         gsc_write(cfg, GSC_PRE_SCALE_RATIO);
956 
957         return ret;
958 }
959 
960 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
961 {
962         int i, j, k, sc_ratio;
963 
964         if (main_hratio <= GSC_SC_UP_MAX_RATIO)
965                 sc_ratio = 0;
966         else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
967                 sc_ratio = 1;
968         else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
969                 sc_ratio = 2;
970         else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
971                 sc_ratio = 3;
972         else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
973                 sc_ratio = 4;
974         else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
975                 sc_ratio = 5;
976         else
977                 sc_ratio = 6;
978 
979         for (i = 0; i < GSC_COEF_PHASE; i++)
980                 for (j = 0; j < GSC_COEF_H_8T; j++)
981                         for (k = 0; k < GSC_COEF_DEPTH; k++)
982                                 gsc_write(h_coef_8t[sc_ratio][i][j],
983                                         GSC_HCOEF(i, j, k));
984 }
985 
986 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
987 {
988         int i, j, k, sc_ratio;
989 
990         if (main_vratio <= GSC_SC_UP_MAX_RATIO)
991                 sc_ratio = 0;
992         else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
993                 sc_ratio = 1;
994         else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
995                 sc_ratio = 2;
996         else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
997                 sc_ratio = 3;
998         else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
999                 sc_ratio = 4;
1000         else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
1001                 sc_ratio = 5;
1002         else
1003                 sc_ratio = 6;
1004 
1005         for (i = 0; i < GSC_COEF_PHASE; i++)
1006                 for (j = 0; j < GSC_COEF_V_4T; j++)
1007                         for (k = 0; k < GSC_COEF_DEPTH; k++)
1008                                 gsc_write(v_coef_4t[sc_ratio][i][j],
1009                                         GSC_VCOEF(i, j, k));
1010 }
1011 
1012 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
1013 {
1014         u32 cfg;
1015 
1016         DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
1017                 sc->main_hratio, sc->main_vratio);
1018 
1019         gsc_set_h_coef(ctx, sc->main_hratio);
1020         cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
1021         gsc_write(cfg, GSC_MAIN_H_RATIO);
1022 
1023         gsc_set_v_coef(ctx, sc->main_vratio);
1024         cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
1025         gsc_write(cfg, GSC_MAIN_V_RATIO);
1026 }
1027 
1028 static int gsc_dst_set_size(struct device *dev, int swap,
1029                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1030 {
1031         struct gsc_context *ctx = get_gsc_context(dev);
1032         struct drm_exynos_pos img_pos = *pos;
1033         struct gsc_scaler *sc = &ctx->sc;
1034         u32 cfg;
1035 
1036         DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
1037                 swap, pos->x, pos->y, pos->w, pos->h);
1038 
1039         if (swap) {
1040                 img_pos.w = pos->h;
1041                 img_pos.h = pos->w;
1042         }
1043 
1044         /* pixel offset */
1045         cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
1046                 GSC_DSTIMG_OFFSET_Y(pos->y));
1047         gsc_write(cfg, GSC_DSTIMG_OFFSET);
1048 
1049         /* scaled size */
1050         cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
1051         gsc_write(cfg, GSC_SCALED_SIZE);
1052 
1053         DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
1054 
1055         /* original size */
1056         cfg = gsc_read(GSC_DSTIMG_SIZE);
1057         cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
1058                 GSC_DSTIMG_WIDTH_MASK);
1059         cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
1060                 GSC_DSTIMG_HEIGHT(sz->vsize));
1061         gsc_write(cfg, GSC_DSTIMG_SIZE);
1062 
1063         cfg = gsc_read(GSC_OUT_CON);
1064         cfg &= ~GSC_OUT_RGB_TYPE_MASK;
1065 
1066         DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
1067 
1068         if (pos->w >= GSC_WIDTH_ITU_709)
1069                 if (sc->range)
1070                         cfg |= GSC_OUT_RGB_HD_WIDE;
1071                 else
1072                         cfg |= GSC_OUT_RGB_HD_NARROW;
1073         else
1074                 if (sc->range)
1075                         cfg |= GSC_OUT_RGB_SD_WIDE;
1076                 else
1077                         cfg |= GSC_OUT_RGB_SD_NARROW;
1078 
1079         gsc_write(cfg, GSC_OUT_CON);
1080 
1081         return 0;
1082 }
1083 
1084 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
1085 {
1086         u32 cfg, i, buf_num = GSC_REG_SZ;
1087         u32 mask = 0x00000001;
1088 
1089         cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1090 
1091         for (i = 0; i < GSC_REG_SZ; i++)
1092                 if (cfg & (mask << i))
1093                         buf_num--;
1094 
1095         DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1096 
1097         return buf_num;
1098 }
1099 
1100 static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
1101                 enum drm_exynos_ipp_buf_type buf_type)
1102 {
1103         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1104         bool masked;
1105         u32 cfg;
1106         u32 mask = 0x00000001 << buf_id;
1107         int ret = 0;
1108 
1109         DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1110 
1111         mutex_lock(&ctx->lock);
1112 
1113         /* mask register set */
1114         cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1115 
1116         switch (buf_type) {
1117         case IPP_BUF_ENQUEUE:
1118                 masked = false;
1119                 break;
1120         case IPP_BUF_DEQUEUE:
1121                 masked = true;
1122                 break;
1123         default:
1124                 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1125                 ret =  -EINVAL;
1126                 goto err_unlock;
1127         }
1128 
1129         /* sequence id */
1130         cfg &= ~mask;
1131         cfg |= masked << buf_id;
1132         gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
1133         gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
1134         gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
1135 
1136         /* interrupt enable */
1137         if (buf_type == IPP_BUF_ENQUEUE &&
1138             gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
1139                 gsc_handle_irq(ctx, true, false, true);
1140 
1141         /* interrupt disable */
1142         if (buf_type == IPP_BUF_DEQUEUE &&
1143             gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
1144                 gsc_handle_irq(ctx, false, false, true);
1145 
1146 err_unlock:
1147         mutex_unlock(&ctx->lock);
1148         return ret;
1149 }
1150 
1151 static int gsc_dst_set_addr(struct device *dev,
1152                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1153                 enum drm_exynos_ipp_buf_type buf_type)
1154 {
1155         struct gsc_context *ctx = get_gsc_context(dev);
1156         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1157         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1158         struct drm_exynos_ipp_property *property;
1159 
1160         if (!c_node) {
1161                 DRM_ERROR("failed to get c_node.\n");
1162                 return -EFAULT;
1163         }
1164 
1165         property = &c_node->property;
1166 
1167         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1168                 property->prop_id, buf_id, buf_type);
1169 
1170         if (buf_id > GSC_MAX_DST) {
1171                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1172                 return -EINVAL;
1173         }
1174 
1175         /* address register set */
1176         switch (buf_type) {
1177         case IPP_BUF_ENQUEUE:
1178                 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1179                         GSC_OUT_BASE_ADDR_Y(buf_id));
1180                 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1181                         GSC_OUT_BASE_ADDR_CB(buf_id));
1182                 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1183                         GSC_OUT_BASE_ADDR_CR(buf_id));
1184                 break;
1185         case IPP_BUF_DEQUEUE:
1186                 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
1187                 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
1188                 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
1189                 break;
1190         default:
1191                 /* bypass */
1192                 break;
1193         }
1194 
1195         return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
1196 }
1197 
1198 static struct exynos_drm_ipp_ops gsc_dst_ops = {
1199         .set_fmt = gsc_dst_set_fmt,
1200         .set_transf = gsc_dst_set_transf,
1201         .set_size = gsc_dst_set_size,
1202         .set_addr = gsc_dst_set_addr,
1203 };
1204 
1205 static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable)
1206 {
1207         DRM_DEBUG_KMS("enable[%d]\n", enable);
1208 
1209         if (enable) {
1210                 clk_enable(ctx->gsc_clk);
1211                 ctx->suspended = false;
1212         } else {
1213                 clk_disable(ctx->gsc_clk);
1214                 ctx->suspended = true;
1215         }
1216 
1217         return 0;
1218 }
1219 
1220 static int gsc_get_src_buf_index(struct gsc_context *ctx)
1221 {
1222         u32 cfg, curr_index, i;
1223         u32 buf_id = GSC_MAX_SRC;
1224         int ret;
1225 
1226         DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1227 
1228         cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
1229         curr_index = GSC_IN_CURR_GET_INDEX(cfg);
1230 
1231         for (i = curr_index; i < GSC_MAX_SRC; i++) {
1232                 if (!((cfg >> i) & 0x1)) {
1233                         buf_id = i;
1234                         break;
1235                 }
1236         }
1237 
1238         if (buf_id == GSC_MAX_SRC) {
1239                 DRM_ERROR("failed to get in buffer index.\n");
1240                 return -EINVAL;
1241         }
1242 
1243         ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1244         if (ret < 0) {
1245                 DRM_ERROR("failed to dequeue.\n");
1246                 return ret;
1247         }
1248 
1249         DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1250                 curr_index, buf_id);
1251 
1252         return buf_id;
1253 }
1254 
1255 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
1256 {
1257         u32 cfg, curr_index, i;
1258         u32 buf_id = GSC_MAX_DST;
1259         int ret;
1260 
1261         DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1262 
1263         cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1264         curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1265 
1266         for (i = curr_index; i < GSC_MAX_DST; i++) {
1267                 if (!((cfg >> i) & 0x1)) {
1268                         buf_id = i;
1269                         break;
1270                 }
1271         }
1272 
1273         if (buf_id == GSC_MAX_DST) {
1274                 DRM_ERROR("failed to get out buffer index.\n");
1275                 return -EINVAL;
1276         }
1277 
1278         ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1279         if (ret < 0) {
1280                 DRM_ERROR("failed to dequeue.\n");
1281                 return ret;
1282         }
1283 
1284         DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1285                 curr_index, buf_id);
1286 
1287         return buf_id;
1288 }
1289 
1290 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1291 {
1292         struct gsc_context *ctx = dev_id;
1293         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1294         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1295         struct drm_exynos_ipp_event_work *event_work =
1296                 c_node->event_work;
1297         u32 status;
1298         int buf_id[EXYNOS_DRM_OPS_MAX];
1299 
1300         DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1301 
1302         status = gsc_read(GSC_IRQ);
1303         if (status & GSC_IRQ_STATUS_OR_IRQ) {
1304                 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
1305                         ctx->id, status);
1306                 return IRQ_NONE;
1307         }
1308 
1309         if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1310                 dev_dbg(ippdrv->dev, "occurred frame done at %d, status 0x%x.\n",
1311                         ctx->id, status);
1312 
1313                 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);
1314                 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)
1315                         return IRQ_HANDLED;
1316 
1317                 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);
1318                 if (buf_id[EXYNOS_DRM_OPS_DST] < 0)
1319                         return IRQ_HANDLED;
1320 
1321                 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n",
1322                         buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);
1323 
1324                 event_work->ippdrv = ippdrv;
1325                 event_work->buf_id[EXYNOS_DRM_OPS_SRC] =
1326                         buf_id[EXYNOS_DRM_OPS_SRC];
1327                 event_work->buf_id[EXYNOS_DRM_OPS_DST] =
1328                         buf_id[EXYNOS_DRM_OPS_DST];
1329                 queue_work(ippdrv->event_workq,
1330                         (struct work_struct *)event_work);
1331         }
1332 
1333         return IRQ_HANDLED;
1334 }
1335 
1336 static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1337 {
1338         struct drm_exynos_ipp_prop_list *prop_list;
1339 
1340         prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL);
1341         if (!prop_list)
1342                 return -ENOMEM;
1343 
1344         prop_list->version = 1;
1345         prop_list->writeback = 1;
1346         prop_list->refresh_min = GSC_REFRESH_MIN;
1347         prop_list->refresh_max = GSC_REFRESH_MAX;
1348         prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1349                                 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1350         prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1351                                 (1 << EXYNOS_DRM_DEGREE_90) |
1352                                 (1 << EXYNOS_DRM_DEGREE_180) |
1353                                 (1 << EXYNOS_DRM_DEGREE_270);
1354         prop_list->csc = 1;
1355         prop_list->crop = 1;
1356         prop_list->crop_max.hsize = GSC_CROP_MAX;
1357         prop_list->crop_max.vsize = GSC_CROP_MAX;
1358         prop_list->crop_min.hsize = GSC_CROP_MIN;
1359         prop_list->crop_min.vsize = GSC_CROP_MIN;
1360         prop_list->scale = 1;
1361         prop_list->scale_max.hsize = GSC_SCALE_MAX;
1362         prop_list->scale_max.vsize = GSC_SCALE_MAX;
1363         prop_list->scale_min.hsize = GSC_SCALE_MIN;
1364         prop_list->scale_min.vsize = GSC_SCALE_MIN;
1365 
1366         ippdrv->prop_list = prop_list;
1367 
1368         return 0;
1369 }
1370 
1371 static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
1372 {
1373         switch (flip) {
1374         case EXYNOS_DRM_FLIP_NONE:
1375         case EXYNOS_DRM_FLIP_VERTICAL:
1376         case EXYNOS_DRM_FLIP_HORIZONTAL:
1377         case EXYNOS_DRM_FLIP_BOTH:
1378                 return true;
1379         default:
1380                 DRM_DEBUG_KMS("invalid flip\n");
1381                 return false;
1382         }
1383 }
1384 
1385 static int gsc_ippdrv_check_property(struct device *dev,
1386                 struct drm_exynos_ipp_property *property)
1387 {
1388         struct gsc_context *ctx = get_gsc_context(dev);
1389         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1390         struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list;
1391         struct drm_exynos_ipp_config *config;
1392         struct drm_exynos_pos *pos;
1393         struct drm_exynos_sz *sz;
1394         bool swap;
1395         int i;
1396 
1397         for_each_ipp_ops(i) {
1398                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1399                         (property->cmd == IPP_CMD_WB))
1400                         continue;
1401 
1402                 config = &property->config[i];
1403                 pos = &config->pos;
1404                 sz = &config->sz;
1405 
1406                 /* check for flip */
1407                 if (!gsc_check_drm_flip(config->flip)) {
1408                         DRM_ERROR("invalid flip.\n");
1409                         goto err_property;
1410                 }
1411 
1412                 /* check for degree */
1413                 switch (config->degree) {
1414                 case EXYNOS_DRM_DEGREE_90:
1415                 case EXYNOS_DRM_DEGREE_270:
1416                         swap = true;
1417                         break;
1418                 case EXYNOS_DRM_DEGREE_0:
1419                 case EXYNOS_DRM_DEGREE_180:
1420                         swap = false;
1421                         break;
1422                 default:
1423                         DRM_ERROR("invalid degree.\n");
1424                         goto err_property;
1425                 }
1426 
1427                 /* check for buffer bound */
1428                 if ((pos->x + pos->w > sz->hsize) ||
1429                         (pos->y + pos->h > sz->vsize)) {
1430                         DRM_ERROR("out of buf bound.\n");
1431                         goto err_property;
1432                 }
1433 
1434                 /* check for crop */
1435                 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1436                         if (swap) {
1437                                 if ((pos->h < pp->crop_min.hsize) ||
1438                                         (sz->vsize > pp->crop_max.hsize) ||
1439                                         (pos->w < pp->crop_min.vsize) ||
1440                                         (sz->hsize > pp->crop_max.vsize)) {
1441                                         DRM_ERROR("out of crop size.\n");
1442                                         goto err_property;
1443                                 }
1444                         } else {
1445                                 if ((pos->w < pp->crop_min.hsize) ||
1446                                         (sz->hsize > pp->crop_max.hsize) ||
1447                                         (pos->h < pp->crop_min.vsize) ||
1448                                         (sz->vsize > pp->crop_max.vsize)) {
1449                                         DRM_ERROR("out of crop size.\n");
1450                                         goto err_property;
1451                                 }
1452                         }
1453                 }
1454 
1455                 /* check for scale */
1456                 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1457                         if (swap) {
1458                                 if ((pos->h < pp->scale_min.hsize) ||
1459                                         (sz->vsize > pp->scale_max.hsize) ||
1460                                         (pos->w < pp->scale_min.vsize) ||
1461                                         (sz->hsize > pp->scale_max.vsize)) {
1462                                         DRM_ERROR("out of scale size.\n");
1463                                         goto err_property;
1464                                 }
1465                         } else {
1466                                 if ((pos->w < pp->scale_min.hsize) ||
1467                                         (sz->hsize > pp->scale_max.hsize) ||
1468                                         (pos->h < pp->scale_min.vsize) ||
1469                                         (sz->vsize > pp->scale_max.vsize)) {
1470                                         DRM_ERROR("out of scale size.\n");
1471                                         goto err_property;
1472                                 }
1473                         }
1474                 }
1475         }
1476 
1477         return 0;
1478 
1479 err_property:
1480         for_each_ipp_ops(i) {
1481                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1482                         (property->cmd == IPP_CMD_WB))
1483                         continue;
1484 
1485                 config = &property->config[i];
1486                 pos = &config->pos;
1487                 sz = &config->sz;
1488 
1489                 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1490                         i ? "dst" : "src", config->flip, config->degree,
1491                         pos->x, pos->y, pos->w, pos->h,
1492                         sz->hsize, sz->vsize);
1493         }
1494 
1495         return -EINVAL;
1496 }
1497 
1498 
1499 static int gsc_ippdrv_reset(struct device *dev)
1500 {
1501         struct gsc_context *ctx = get_gsc_context(dev);
1502         struct gsc_scaler *sc = &ctx->sc;
1503         int ret;
1504 
1505         /* reset h/w block */
1506         ret = gsc_sw_reset(ctx);
1507         if (ret < 0) {
1508                 dev_err(dev, "failed to reset hardware.\n");
1509                 return ret;
1510         }
1511 
1512         /* scaler setting */
1513         memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1514         sc->range = true;
1515 
1516         return 0;
1517 }
1518 
1519 static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1520 {
1521         struct gsc_context *ctx = get_gsc_context(dev);
1522         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1523         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1524         struct drm_exynos_ipp_property *property;
1525         struct drm_exynos_ipp_config *config;
1526         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
1527         struct drm_exynos_ipp_set_wb set_wb;
1528         u32 cfg;
1529         int ret, i;
1530 
1531         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1532 
1533         if (!c_node) {
1534                 DRM_ERROR("failed to get c_node.\n");
1535                 return -EINVAL;
1536         }
1537 
1538         property = &c_node->property;
1539 
1540         gsc_handle_irq(ctx, true, false, true);
1541 
1542         for_each_ipp_ops(i) {
1543                 config = &property->config[i];
1544                 img_pos[i] = config->pos;
1545         }
1546 
1547         switch (cmd) {
1548         case IPP_CMD_M2M:
1549                 /* enable one shot */
1550                 cfg = gsc_read(GSC_ENABLE);
1551                 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1552                         GSC_ENABLE_CLK_GATE_MODE_MASK);
1553                 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1554                 gsc_write(cfg, GSC_ENABLE);
1555 
1556                 /* src dma memory */
1557                 cfg = gsc_read(GSC_IN_CON);
1558                 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1559                 cfg |= GSC_IN_PATH_MEMORY;
1560                 gsc_write(cfg, GSC_IN_CON);
1561 
1562                 /* dst dma memory */
1563                 cfg = gsc_read(GSC_OUT_CON);
1564                 cfg |= GSC_OUT_PATH_MEMORY;
1565                 gsc_write(cfg, GSC_OUT_CON);
1566                 break;
1567         case IPP_CMD_WB:
1568                 set_wb.enable = 1;
1569                 set_wb.refresh = property->refresh_rate;
1570                 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1571                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1572 
1573                 /* src local path */
1574                 cfg = gsc_read(GSC_IN_CON);
1575                 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1576                 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
1577                 gsc_write(cfg, GSC_IN_CON);
1578 
1579                 /* dst dma memory */
1580                 cfg = gsc_read(GSC_OUT_CON);
1581                 cfg |= GSC_OUT_PATH_MEMORY;
1582                 gsc_write(cfg, GSC_OUT_CON);
1583                 break;
1584         case IPP_CMD_OUTPUT:
1585                 /* src dma memory */
1586                 cfg = gsc_read(GSC_IN_CON);
1587                 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1588                 cfg |= GSC_IN_PATH_MEMORY;
1589                 gsc_write(cfg, GSC_IN_CON);
1590 
1591                 /* dst local path */
1592                 cfg = gsc_read(GSC_OUT_CON);
1593                 cfg |= GSC_OUT_PATH_MEMORY;
1594                 gsc_write(cfg, GSC_OUT_CON);
1595                 break;
1596         default:
1597                 ret = -EINVAL;
1598                 dev_err(dev, "invalid operations.\n");
1599                 return ret;
1600         }
1601 
1602         ret = gsc_set_prescaler(ctx, &ctx->sc,
1603                 &img_pos[EXYNOS_DRM_OPS_SRC],
1604                 &img_pos[EXYNOS_DRM_OPS_DST]);
1605         if (ret) {
1606                 dev_err(dev, "failed to set precalser.\n");
1607                 return ret;
1608         }
1609 
1610         gsc_set_scaler(ctx, &ctx->sc);
1611 
1612         cfg = gsc_read(GSC_ENABLE);
1613         cfg |= GSC_ENABLE_ON;
1614         gsc_write(cfg, GSC_ENABLE);
1615 
1616         return 0;
1617 }
1618 
1619 static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1620 {
1621         struct gsc_context *ctx = get_gsc_context(dev);
1622         struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1623         u32 cfg;
1624 
1625         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1626 
1627         switch (cmd) {
1628         case IPP_CMD_M2M:
1629                 /* bypass */
1630                 break;
1631         case IPP_CMD_WB:
1632                 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1633                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1634                 break;
1635         case IPP_CMD_OUTPUT:
1636         default:
1637                 dev_err(dev, "invalid operations.\n");
1638                 break;
1639         }
1640 
1641         gsc_handle_irq(ctx, false, false, true);
1642 
1643         /* reset sequence */
1644         gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
1645         gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
1646         gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
1647 
1648         cfg = gsc_read(GSC_ENABLE);
1649         cfg &= ~GSC_ENABLE_ON;
1650         gsc_write(cfg, GSC_ENABLE);
1651 }
1652 
1653 static int gsc_probe(struct platform_device *pdev)
1654 {
1655         struct device *dev = &pdev->dev;
1656         struct gsc_context *ctx;
1657         struct resource *res;
1658         struct exynos_drm_ippdrv *ippdrv;
1659         int ret;
1660 
1661         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1662         if (!ctx)
1663                 return -ENOMEM;
1664 
1665         /* clock control */
1666         ctx->gsc_clk = devm_clk_get(dev, "gscl");
1667         if (IS_ERR(ctx->gsc_clk)) {
1668                 dev_err(dev, "failed to get gsc clock.\n");
1669                 return PTR_ERR(ctx->gsc_clk);
1670         }
1671 
1672         /* resource memory */
1673         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1674         ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1675         if (IS_ERR(ctx->regs))
1676                 return PTR_ERR(ctx->regs);
1677 
1678         /* resource irq */
1679         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1680         if (!res) {
1681                 dev_err(dev, "failed to request irq resource.\n");
1682                 return -ENOENT;
1683         }
1684 
1685         ctx->irq = res->start;
1686         ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
1687                 IRQF_ONESHOT, "drm_gsc", ctx);
1688         if (ret < 0) {
1689                 dev_err(dev, "failed to request irq.\n");
1690                 return ret;
1691         }
1692 
1693         /* context initailization */
1694         ctx->id = pdev->id;
1695 
1696         ippdrv = &ctx->ippdrv;
1697         ippdrv->dev = dev;
1698         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
1699         ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
1700         ippdrv->check_property = gsc_ippdrv_check_property;
1701         ippdrv->reset = gsc_ippdrv_reset;
1702         ippdrv->start = gsc_ippdrv_start;
1703         ippdrv->stop = gsc_ippdrv_stop;
1704         ret = gsc_init_prop_list(ippdrv);
1705         if (ret < 0) {
1706                 dev_err(dev, "failed to init property list.\n");
1707                 return ret;
1708         }
1709 
1710         DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1711 
1712         mutex_init(&ctx->lock);
1713         platform_set_drvdata(pdev, ctx);
1714 
1715         pm_runtime_set_active(dev);
1716         pm_runtime_enable(dev);
1717 
1718         ret = exynos_drm_ippdrv_register(ippdrv);
1719         if (ret < 0) {
1720                 dev_err(dev, "failed to register drm gsc device.\n");
1721                 goto err_ippdrv_register;
1722         }
1723 
1724         dev_info(dev, "drm gsc registered successfully.\n");
1725 
1726         return 0;
1727 
1728 err_ippdrv_register:
1729         pm_runtime_disable(dev);
1730         return ret;
1731 }
1732 
1733 static int gsc_remove(struct platform_device *pdev)
1734 {
1735         struct device *dev = &pdev->dev;
1736         struct gsc_context *ctx = get_gsc_context(dev);
1737         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1738 
1739         exynos_drm_ippdrv_unregister(ippdrv);
1740         mutex_destroy(&ctx->lock);
1741 
1742         pm_runtime_set_suspended(dev);
1743         pm_runtime_disable(dev);
1744 
1745         return 0;
1746 }
1747 
1748 #ifdef CONFIG_PM_SLEEP
1749 static int gsc_suspend(struct device *dev)
1750 {
1751         struct gsc_context *ctx = get_gsc_context(dev);
1752 
1753         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1754 
1755         if (pm_runtime_suspended(dev))
1756                 return 0;
1757 
1758         return gsc_clk_ctrl(ctx, false);
1759 }
1760 
1761 static int gsc_resume(struct device *dev)
1762 {
1763         struct gsc_context *ctx = get_gsc_context(dev);
1764 
1765         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1766 
1767         if (!pm_runtime_suspended(dev))
1768                 return gsc_clk_ctrl(ctx, true);
1769 
1770         return 0;
1771 }
1772 #endif
1773 
1774 #ifdef CONFIG_PM_RUNTIME
1775 static int gsc_runtime_suspend(struct device *dev)
1776 {
1777         struct gsc_context *ctx = get_gsc_context(dev);
1778 
1779         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1780 
1781         return  gsc_clk_ctrl(ctx, false);
1782 }
1783 
1784 static int gsc_runtime_resume(struct device *dev)
1785 {
1786         struct gsc_context *ctx = get_gsc_context(dev);
1787 
1788         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1789 
1790         return  gsc_clk_ctrl(ctx, true);
1791 }
1792 #endif
1793 
1794 static const struct dev_pm_ops gsc_pm_ops = {
1795         SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume)
1796         SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1797 };
1798 
1799 struct platform_driver gsc_driver = {
1800         .probe          = gsc_probe,
1801         .remove         = gsc_remove,
1802         .driver         = {
1803                 .name   = "exynos-drm-gsc",
1804                 .owner  = THIS_MODULE,
1805                 .pm     = &gsc_pm_ops,
1806         },
1807 };
1808 
1809 

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