Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/gpu/drm/exynos/exynos_drm_fimc.c

  1 /*
  2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3  * Authors:
  4  *      Eunchul Kim <chulspro.kim@samsung.com>
  5  *      Jinyoung Jeon <jy0.jeon@samsung.com>
  6  *      Sangmin Lee <lsmin.lee@samsung.com>
  7  *
  8  * This program is free software; you can redistribute  it and/or modify it
  9  * under  the terms of  the GNU General  Public License as published by the
 10  * Free Software Foundation;  either version 2 of the  License, or (at your
 11  * option) any later version.
 12  *
 13  */
 14 #include <linux/kernel.h>
 15 #include <linux/platform_device.h>
 16 #include <linux/mfd/syscon.h>
 17 #include <linux/regmap.h>
 18 #include <linux/clk.h>
 19 #include <linux/pm_runtime.h>
 20 #include <linux/of.h>
 21 #include <linux/spinlock.h>
 22 
 23 #include <drm/drmP.h>
 24 #include <drm/exynos_drm.h>
 25 #include "regs-fimc.h"
 26 #include "exynos_drm_drv.h"
 27 #include "exynos_drm_ipp.h"
 28 #include "exynos_drm_fimc.h"
 29 
 30 /*
 31  * FIMC stands for Fully Interactive Mobile Camera and
 32  * supports image scaler/rotator and input/output DMA operations.
 33  * input DMA reads image data from the memory.
 34  * output DMA writes image data to memory.
 35  * FIMC supports image rotation and image effect functions.
 36  *
 37  * M2M operation : supports crop/scale/rotation/csc so on.
 38  * Memory ----> FIMC H/W ----> Memory.
 39  * Writeback operation : supports cloned screen with FIMD.
 40  * FIMD ----> FIMC H/W ----> Memory.
 41  * Output operation : supports direct display using local path.
 42  * Memory ----> FIMC H/W ----> FIMD.
 43  */
 44 
 45 /*
 46  * TODO
 47  * 1. check suspend/resume api if needed.
 48  * 2. need to check use case platform_device_id.
 49  * 3. check src/dst size with, height.
 50  * 4. added check_prepare api for right register.
 51  * 5. need to add supported list in prop_list.
 52  * 6. check prescaler/scaler optimization.
 53  */
 54 
 55 #define FIMC_MAX_DEVS   4
 56 #define FIMC_MAX_SRC    2
 57 #define FIMC_MAX_DST    32
 58 #define FIMC_SHFACTOR   10
 59 #define FIMC_BUF_STOP   1
 60 #define FIMC_BUF_START  2
 61 #define FIMC_WIDTH_ITU_709      1280
 62 #define FIMC_REFRESH_MAX        60
 63 #define FIMC_REFRESH_MIN        12
 64 #define FIMC_CROP_MAX   8192
 65 #define FIMC_CROP_MIN   32
 66 #define FIMC_SCALE_MAX  4224
 67 #define FIMC_SCALE_MIN  32
 68 
 69 #define get_fimc_context(dev)   platform_get_drvdata(to_platform_device(dev))
 70 #define get_ctx_from_ippdrv(ippdrv)     container_of(ippdrv,\
 71                                         struct fimc_context, ippdrv);
 72 enum fimc_wb {
 73         FIMC_WB_NONE,
 74         FIMC_WB_A,
 75         FIMC_WB_B,
 76 };
 77 
 78 enum {
 79         FIMC_CLK_LCLK,
 80         FIMC_CLK_GATE,
 81         FIMC_CLK_WB_A,
 82         FIMC_CLK_WB_B,
 83         FIMC_CLK_MUX,
 84         FIMC_CLK_PARENT,
 85         FIMC_CLKS_MAX
 86 };
 87 
 88 static const char * const fimc_clock_names[] = {
 89         [FIMC_CLK_LCLK]   = "sclk_fimc",
 90         [FIMC_CLK_GATE]   = "fimc",
 91         [FIMC_CLK_WB_A]   = "pxl_async0",
 92         [FIMC_CLK_WB_B]   = "pxl_async1",
 93         [FIMC_CLK_MUX]    = "mux",
 94         [FIMC_CLK_PARENT] = "parent",
 95 };
 96 
 97 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
 98 
 99 /*
100  * A structure of scaler.
101  *
102  * @range: narrow, wide.
103  * @bypass: unused scaler path.
104  * @up_h: horizontal scale up.
105  * @up_v: vertical scale up.
106  * @hratio: horizontal ratio.
107  * @vratio: vertical ratio.
108  */
109 struct fimc_scaler {
110         bool    range;
111         bool bypass;
112         bool up_h;
113         bool up_v;
114         u32 hratio;
115         u32 vratio;
116 };
117 
118 /*
119  * A structure of scaler capability.
120  *
121  * find user manual table 43-1.
122  * @in_hori: scaler input horizontal size.
123  * @bypass: scaler bypass mode.
124  * @dst_h_wo_rot: target horizontal size without output rotation.
125  * @dst_h_rot: target horizontal size with output rotation.
126  * @rl_w_wo_rot: real width without input rotation.
127  * @rl_h_rot: real height without output rotation.
128  */
129 struct fimc_capability {
130         /* scaler */
131         u32     in_hori;
132         u32     bypass;
133         /* output rotator */
134         u32     dst_h_wo_rot;
135         u32     dst_h_rot;
136         /* input rotator */
137         u32     rl_w_wo_rot;
138         u32     rl_h_rot;
139 };
140 
141 /*
142  * A structure of fimc context.
143  *
144  * @ippdrv: prepare initialization using ippdrv.
145  * @regs_res: register resources.
146  * @regs: memory mapped io registers.
147  * @lock: locking of operations.
148  * @clocks: fimc clocks.
149  * @clk_frequency: LCLK clock frequency.
150  * @sysreg: handle to SYSREG block regmap.
151  * @sc: scaler infomations.
152  * @pol: porarity of writeback.
153  * @id: fimc id.
154  * @irq: irq number.
155  * @suspended: qos operations.
156  */
157 struct fimc_context {
158         struct exynos_drm_ippdrv        ippdrv;
159         struct resource *regs_res;
160         void __iomem    *regs;
161         spinlock_t      lock;
162         struct clk      *clocks[FIMC_CLKS_MAX];
163         u32             clk_frequency;
164         struct regmap   *sysreg;
165         struct fimc_scaler      sc;
166         struct exynos_drm_ipp_pol       pol;
167         int     id;
168         int     irq;
169         bool    suspended;
170 };
171 
172 static u32 fimc_read(struct fimc_context *ctx, u32 reg)
173 {
174         return readl(ctx->regs + reg);
175 }
176 
177 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
178 {
179         writel(val, ctx->regs + reg);
180 }
181 
182 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
183 {
184         void __iomem *r = ctx->regs + reg;
185 
186         writel(readl(r) | bits, r);
187 }
188 
189 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
190 {
191         void __iomem *r = ctx->regs + reg;
192 
193         writel(readl(r) & ~bits, r);
194 }
195 
196 static void fimc_sw_reset(struct fimc_context *ctx)
197 {
198         u32 cfg;
199 
200         /* stop dma operation */
201         cfg = fimc_read(ctx, EXYNOS_CISTATUS);
202         if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
203                 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
204 
205         fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
206 
207         /* disable image capture */
208         fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
209                 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
210 
211         /* s/w reset */
212         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
213 
214         /* s/w reset complete */
215         fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
216 
217         /* reset sequence */
218         fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
219 }
220 
221 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
222 {
223         return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
224                                   SYSREG_FIMD0WB_DEST_MASK,
225                                   ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
226 }
227 
228 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
229 {
230         u32 cfg;
231 
232         DRM_DEBUG_KMS("wb[%d]\n", wb);
233 
234         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
235         cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
236                 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
237                 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
238                 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
239                 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
240                 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
241 
242         switch (wb) {
243         case FIMC_WB_A:
244                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
245                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
246                 break;
247         case FIMC_WB_B:
248                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
249                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
250                 break;
251         case FIMC_WB_NONE:
252         default:
253                 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
254                         EXYNOS_CIGCTRL_SELWRITEBACK_A |
255                         EXYNOS_CIGCTRL_SELCAM_MIPI_A |
256                         EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
257                 break;
258         }
259 
260         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
261 }
262 
263 static void fimc_set_polarity(struct fimc_context *ctx,
264                 struct exynos_drm_ipp_pol *pol)
265 {
266         u32 cfg;
267 
268         DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
269                 pol->inv_pclk, pol->inv_vsync);
270         DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
271                 pol->inv_href, pol->inv_hsync);
272 
273         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
274         cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
275                  EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
276 
277         if (pol->inv_pclk)
278                 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
279         if (pol->inv_vsync)
280                 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
281         if (pol->inv_href)
282                 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
283         if (pol->inv_hsync)
284                 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
285 
286         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
287 }
288 
289 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
290 {
291         u32 cfg;
292 
293         DRM_DEBUG_KMS("enable[%d]\n", enable);
294 
295         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
296         if (enable)
297                 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
298         else
299                 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
300 
301         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
302 }
303 
304 static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
305 {
306         u32 cfg;
307 
308         DRM_DEBUG_KMS("enable[%d]\n", enable);
309 
310         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
311         if (enable) {
312                 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
313                 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
314         } else
315                 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
316         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
317 }
318 
319 static void fimc_clear_irq(struct fimc_context *ctx)
320 {
321         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
322 }
323 
324 static bool fimc_check_ovf(struct fimc_context *ctx)
325 {
326         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
327         u32 status, flag;
328 
329         status = fimc_read(ctx, EXYNOS_CISTATUS);
330         flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
331                 EXYNOS_CISTATUS_OVFICR;
332 
333         DRM_DEBUG_KMS("flag[0x%x]\n", flag);
334 
335         if (status & flag) {
336                 fimc_set_bits(ctx, EXYNOS_CIWDOFST,
337                         EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
338                         EXYNOS_CIWDOFST_CLROVFICR);
339 
340                 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
341                         ctx->id, status);
342                 return true;
343         }
344 
345         return false;
346 }
347 
348 static bool fimc_check_frame_end(struct fimc_context *ctx)
349 {
350         u32 cfg;
351 
352         cfg = fimc_read(ctx, EXYNOS_CISTATUS);
353 
354         DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
355 
356         if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
357                 return false;
358 
359         cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
360         fimc_write(ctx, cfg, EXYNOS_CISTATUS);
361 
362         return true;
363 }
364 
365 static int fimc_get_buf_id(struct fimc_context *ctx)
366 {
367         u32 cfg;
368         int frame_cnt, buf_id;
369 
370         cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
371         frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
372 
373         if (frame_cnt == 0)
374                 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
375 
376         DRM_DEBUG_KMS("present[%d]before[%d]\n",
377                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
378                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
379 
380         if (frame_cnt == 0) {
381                 DRM_ERROR("failed to get frame count.\n");
382                 return -EIO;
383         }
384 
385         buf_id = frame_cnt - 1;
386         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
387 
388         return buf_id;
389 }
390 
391 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
392 {
393         u32 cfg;
394 
395         DRM_DEBUG_KMS("enable[%d]\n", enable);
396 
397         cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
398         if (enable)
399                 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
400         else
401                 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
402 
403         fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
404 }
405 
406 
407 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
408 {
409         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
410         u32 cfg;
411 
412         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
413 
414         /* RGB */
415         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
416         cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
417 
418         switch (fmt) {
419         case DRM_FORMAT_RGB565:
420                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
421                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
422                 return 0;
423         case DRM_FORMAT_RGB888:
424         case DRM_FORMAT_XRGB8888:
425                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
426                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
427                 return 0;
428         default:
429                 /* bypass */
430                 break;
431         }
432 
433         /* YUV */
434         cfg = fimc_read(ctx, EXYNOS_MSCTRL);
435         cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
436                 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
437                 EXYNOS_MSCTRL_ORDER422_YCBYCR);
438 
439         switch (fmt) {
440         case DRM_FORMAT_YUYV:
441                 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
442                 break;
443         case DRM_FORMAT_YVYU:
444                 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
445                 break;
446         case DRM_FORMAT_UYVY:
447                 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
448                 break;
449         case DRM_FORMAT_VYUY:
450         case DRM_FORMAT_YUV444:
451                 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
452                 break;
453         case DRM_FORMAT_NV21:
454         case DRM_FORMAT_NV61:
455                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
456                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
457                 break;
458         case DRM_FORMAT_YUV422:
459         case DRM_FORMAT_YUV420:
460         case DRM_FORMAT_YVU420:
461                 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
462                 break;
463         case DRM_FORMAT_NV12:
464         case DRM_FORMAT_NV16:
465                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
466                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
467                 break;
468         default:
469                 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
470                 return -EINVAL;
471         }
472 
473         fimc_write(ctx, cfg, EXYNOS_MSCTRL);
474 
475         return 0;
476 }
477 
478 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
479 {
480         struct fimc_context *ctx = get_fimc_context(dev);
481         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
482         u32 cfg;
483 
484         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
485 
486         cfg = fimc_read(ctx, EXYNOS_MSCTRL);
487         cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
488 
489         switch (fmt) {
490         case DRM_FORMAT_RGB565:
491         case DRM_FORMAT_RGB888:
492         case DRM_FORMAT_XRGB8888:
493                 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
494                 break;
495         case DRM_FORMAT_YUV444:
496                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
497                 break;
498         case DRM_FORMAT_YUYV:
499         case DRM_FORMAT_YVYU:
500         case DRM_FORMAT_UYVY:
501         case DRM_FORMAT_VYUY:
502                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
503                 break;
504         case DRM_FORMAT_NV16:
505         case DRM_FORMAT_NV61:
506         case DRM_FORMAT_YUV422:
507                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
508                 break;
509         case DRM_FORMAT_YUV420:
510         case DRM_FORMAT_YVU420:
511         case DRM_FORMAT_NV12:
512         case DRM_FORMAT_NV21:
513                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
514                 break;
515         default:
516                 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
517                 return -EINVAL;
518         }
519 
520         fimc_write(ctx, cfg, EXYNOS_MSCTRL);
521 
522         cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
523         cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
524 
525         cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
526 
527         fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
528 
529         return fimc_src_set_fmt_order(ctx, fmt);
530 }
531 
532 static int fimc_src_set_transf(struct device *dev,
533                 enum drm_exynos_degree degree,
534                 enum drm_exynos_flip flip, bool *swap)
535 {
536         struct fimc_context *ctx = get_fimc_context(dev);
537         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
538         u32 cfg1, cfg2;
539 
540         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
541 
542         cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
543         cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
544                 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
545 
546         cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
547         cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
548 
549         switch (degree) {
550         case EXYNOS_DRM_DEGREE_0:
551                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
552                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
553                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
554                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
555                 break;
556         case EXYNOS_DRM_DEGREE_90:
557                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
558                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
559                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
560                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
561                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
562                 break;
563         case EXYNOS_DRM_DEGREE_180:
564                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
565                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
566                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
567                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
568                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
569                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
570                 break;
571         case EXYNOS_DRM_DEGREE_270:
572                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
573                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
574                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
575                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
576                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
577                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
578                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
579                 break;
580         default:
581                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
582                 return -EINVAL;
583         }
584 
585         fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
586         fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
587         *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
588 
589         return 0;
590 }
591 
592 static int fimc_set_window(struct fimc_context *ctx,
593                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
594 {
595         u32 cfg, h1, h2, v1, v2;
596 
597         /* cropped image */
598         h1 = pos->x;
599         h2 = sz->hsize - pos->w - pos->x;
600         v1 = pos->y;
601         v2 = sz->vsize - pos->h - pos->y;
602 
603         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
604                 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
605         DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
606 
607         /*
608          * set window offset 1, 2 size
609          * check figure 43-21 in user manual
610          */
611         cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
612         cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
613                 EXYNOS_CIWDOFST_WINVEROFST_MASK);
614         cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
615                 EXYNOS_CIWDOFST_WINVEROFST(v1));
616         cfg |= EXYNOS_CIWDOFST_WINOFSEN;
617         fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
618 
619         cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
620                 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
621         fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
622 
623         return 0;
624 }
625 
626 static int fimc_src_set_size(struct device *dev, int swap,
627                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
628 {
629         struct fimc_context *ctx = get_fimc_context(dev);
630         struct drm_exynos_pos img_pos = *pos;
631         struct drm_exynos_sz img_sz = *sz;
632         u32 cfg;
633 
634         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
635                 swap, sz->hsize, sz->vsize);
636 
637         /* original size */
638         cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
639                 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
640 
641         fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
642 
643         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
644 
645         if (swap) {
646                 img_pos.w = pos->h;
647                 img_pos.h = pos->w;
648                 img_sz.hsize = sz->vsize;
649                 img_sz.vsize = sz->hsize;
650         }
651 
652         /* set input DMA image size */
653         cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
654         cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
655                 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
656         cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
657                 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
658         fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
659 
660         /*
661          * set input FIFO image size
662          * for now, we support only ITU601 8 bit mode
663          */
664         cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
665                 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
666                 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
667         fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
668 
669         /* offset Y(RGB), Cb, Cr */
670         cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
671                 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
672         fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
673         cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
674                 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
675         fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
676         cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
677                 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
678         fimc_write(ctx, cfg, EXYNOS_CIICROFF);
679 
680         return fimc_set_window(ctx, &img_pos, &img_sz);
681 }
682 
683 static int fimc_src_set_addr(struct device *dev,
684                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
685                 enum drm_exynos_ipp_buf_type buf_type)
686 {
687         struct fimc_context *ctx = get_fimc_context(dev);
688         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
689         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
690         struct drm_exynos_ipp_property *property;
691         struct drm_exynos_ipp_config *config;
692 
693         if (!c_node) {
694                 DRM_ERROR("failed to get c_node.\n");
695                 return -EINVAL;
696         }
697 
698         property = &c_node->property;
699 
700         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
701                 property->prop_id, buf_id, buf_type);
702 
703         if (buf_id > FIMC_MAX_SRC) {
704                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
705                 return -ENOMEM;
706         }
707 
708         /* address register set */
709         switch (buf_type) {
710         case IPP_BUF_ENQUEUE:
711                 config = &property->config[EXYNOS_DRM_OPS_SRC];
712                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
713                         EXYNOS_CIIYSA0);
714 
715                 if (config->fmt == DRM_FORMAT_YVU420) {
716                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
717                                 EXYNOS_CIICBSA0);
718                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
719                                 EXYNOS_CIICRSA0);
720                 } else {
721                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
722                                 EXYNOS_CIICBSA0);
723                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
724                                 EXYNOS_CIICRSA0);
725                 }
726                 break;
727         case IPP_BUF_DEQUEUE:
728                 fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
729                 fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
730                 fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
731                 break;
732         default:
733                 /* bypass */
734                 break;
735         }
736 
737         return 0;
738 }
739 
740 static struct exynos_drm_ipp_ops fimc_src_ops = {
741         .set_fmt = fimc_src_set_fmt,
742         .set_transf = fimc_src_set_transf,
743         .set_size = fimc_src_set_size,
744         .set_addr = fimc_src_set_addr,
745 };
746 
747 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
748 {
749         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
750         u32 cfg;
751 
752         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
753 
754         /* RGB */
755         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
756         cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
757 
758         switch (fmt) {
759         case DRM_FORMAT_RGB565:
760                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
761                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
762                 return 0;
763         case DRM_FORMAT_RGB888:
764                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
765                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
766                 return 0;
767         case DRM_FORMAT_XRGB8888:
768                 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
769                         EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
770                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
771                 break;
772         default:
773                 /* bypass */
774                 break;
775         }
776 
777         /* YUV */
778         cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
779         cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
780                 EXYNOS_CIOCTRL_ORDER422_MASK |
781                 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
782 
783         switch (fmt) {
784         case DRM_FORMAT_XRGB8888:
785                 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
786                 break;
787         case DRM_FORMAT_YUYV:
788                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
789                 break;
790         case DRM_FORMAT_YVYU:
791                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
792                 break;
793         case DRM_FORMAT_UYVY:
794                 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
795                 break;
796         case DRM_FORMAT_VYUY:
797                 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
798                 break;
799         case DRM_FORMAT_NV21:
800         case DRM_FORMAT_NV61:
801                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
802                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
803                 break;
804         case DRM_FORMAT_YUV422:
805         case DRM_FORMAT_YUV420:
806         case DRM_FORMAT_YVU420:
807                 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
808                 break;
809         case DRM_FORMAT_NV12:
810         case DRM_FORMAT_NV16:
811                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
812                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
813                 break;
814         default:
815                 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
816                 return -EINVAL;
817         }
818 
819         fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
820 
821         return 0;
822 }
823 
824 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
825 {
826         struct fimc_context *ctx = get_fimc_context(dev);
827         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
828         u32 cfg;
829 
830         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
831 
832         cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
833 
834         if (fmt == DRM_FORMAT_AYUV) {
835                 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
836                 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
837         } else {
838                 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
839                 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
840 
841                 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
842                 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
843 
844                 switch (fmt) {
845                 case DRM_FORMAT_RGB565:
846                 case DRM_FORMAT_RGB888:
847                 case DRM_FORMAT_XRGB8888:
848                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
849                         break;
850                 case DRM_FORMAT_YUYV:
851                 case DRM_FORMAT_YVYU:
852                 case DRM_FORMAT_UYVY:
853                 case DRM_FORMAT_VYUY:
854                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
855                         break;
856                 case DRM_FORMAT_NV16:
857                 case DRM_FORMAT_NV61:
858                 case DRM_FORMAT_YUV422:
859                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
860                         break;
861                 case DRM_FORMAT_YUV420:
862                 case DRM_FORMAT_YVU420:
863                 case DRM_FORMAT_NV12:
864                 case DRM_FORMAT_NV21:
865                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
866                         break;
867                 default:
868                         dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
869                                 fmt);
870                         return -EINVAL;
871                 }
872 
873                 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
874         }
875 
876         cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
877         cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
878 
879         cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
880 
881         fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
882 
883         return fimc_dst_set_fmt_order(ctx, fmt);
884 }
885 
886 static int fimc_dst_set_transf(struct device *dev,
887                 enum drm_exynos_degree degree,
888                 enum drm_exynos_flip flip, bool *swap)
889 {
890         struct fimc_context *ctx = get_fimc_context(dev);
891         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
892         u32 cfg;
893 
894         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
895 
896         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
897         cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
898         cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
899 
900         switch (degree) {
901         case EXYNOS_DRM_DEGREE_0:
902                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
903                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
904                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
905                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
906                 break;
907         case EXYNOS_DRM_DEGREE_90:
908                 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
909                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
910                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
911                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
912                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
913                 break;
914         case EXYNOS_DRM_DEGREE_180:
915                 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
916                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
917                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
918                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
919                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
920                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
921                 break;
922         case EXYNOS_DRM_DEGREE_270:
923                 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
924                         EXYNOS_CITRGFMT_FLIP_X_MIRROR |
925                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
926                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
927                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
928                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
929                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
930                 break;
931         default:
932                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
933                 return -EINVAL;
934         }
935 
936         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
937         *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
938 
939         return 0;
940 }
941 
942 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
943                 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
944 {
945         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
946         u32 cfg, cfg_ext, shfactor;
947         u32 pre_dst_width, pre_dst_height;
948         u32 hfactor, vfactor;
949         int ret = 0;
950         u32 src_w, src_h, dst_w, dst_h;
951 
952         cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
953         if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
954                 src_w = src->h;
955                 src_h = src->w;
956         } else {
957                 src_w = src->w;
958                 src_h = src->h;
959         }
960 
961         if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
962                 dst_w = dst->h;
963                 dst_h = dst->w;
964         } else {
965                 dst_w = dst->w;
966                 dst_h = dst->h;
967         }
968 
969         /* fimc_ippdrv_check_property assures that dividers are not null */
970         hfactor = fls(src_w / dst_w / 2);
971         if (hfactor > FIMC_SHFACTOR / 2) {
972                 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
973                 return -EINVAL;
974         }
975 
976         vfactor = fls(src_h / dst_h / 2);
977         if (vfactor > FIMC_SHFACTOR / 2) {
978                 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
979                 return -EINVAL;
980         }
981 
982         pre_dst_width = src_w >> hfactor;
983         pre_dst_height = src_h >> vfactor;
984         DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
985                 pre_dst_width, pre_dst_height);
986         DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
987 
988         sc->hratio = (src_w << 14) / (dst_w << hfactor);
989         sc->vratio = (src_h << 14) / (dst_h << vfactor);
990         sc->up_h = (dst_w >= src_w) ? true : false;
991         sc->up_v = (dst_h >= src_h) ? true : false;
992         DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
993                 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
994 
995         shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
996         DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
997 
998         cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
999                 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1000                 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1001         fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
1002 
1003         cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1004                 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1005         fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
1006 
1007         return ret;
1008 }
1009 
1010 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1011 {
1012         u32 cfg, cfg_ext;
1013 
1014         DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1015                 sc->range, sc->bypass, sc->up_h, sc->up_v);
1016         DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1017                 sc->hratio, sc->vratio);
1018 
1019         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
1020         cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1021                 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1022                 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1023                 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1024                 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1025                 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1026 
1027         if (sc->range)
1028                 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1029                         EXYNOS_CISCCTRL_CSCY2R_WIDE);
1030         if (sc->bypass)
1031                 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1032         if (sc->up_h)
1033                 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1034         if (sc->up_v)
1035                 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1036 
1037         cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1038                 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1039         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
1040 
1041         cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
1042         cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1043         cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1044         cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1045                 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1046         fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
1047 }
1048 
1049 static int fimc_dst_set_size(struct device *dev, int swap,
1050                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1051 {
1052         struct fimc_context *ctx = get_fimc_context(dev);
1053         struct drm_exynos_pos img_pos = *pos;
1054         struct drm_exynos_sz img_sz = *sz;
1055         u32 cfg;
1056 
1057         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1058                 swap, sz->hsize, sz->vsize);
1059 
1060         /* original size */
1061         cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1062                 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1063 
1064         fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
1065 
1066         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1067 
1068         /* CSC ITU */
1069         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
1070         cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1071 
1072         if (sz->hsize >= FIMC_WIDTH_ITU_709)
1073                 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1074         else
1075                 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1076 
1077         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
1078 
1079         if (swap) {
1080                 img_pos.w = pos->h;
1081                 img_pos.h = pos->w;
1082                 img_sz.hsize = sz->vsize;
1083                 img_sz.vsize = sz->hsize;
1084         }
1085 
1086         /* target image size */
1087         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
1088         cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1089                 EXYNOS_CITRGFMT_TARGETV_MASK);
1090         cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1091                 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1092         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
1093 
1094         /* target area */
1095         cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1096         fimc_write(ctx, cfg, EXYNOS_CITAREA);
1097 
1098         /* offset Y(RGB), Cb, Cr */
1099         cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1100                 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1101         fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
1102         cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1103                 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1104         fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
1105         cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1106                 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1107         fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
1108 
1109         return 0;
1110 }
1111 
1112 static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1113                 enum drm_exynos_ipp_buf_type buf_type)
1114 {
1115         unsigned long flags;
1116         u32 buf_num;
1117         u32 cfg;
1118 
1119         DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1120 
1121         spin_lock_irqsave(&ctx->lock, flags);
1122 
1123         cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1124 
1125         if (buf_type == IPP_BUF_ENQUEUE)
1126                 cfg |= (1 << buf_id);
1127         else
1128                 cfg &= ~(1 << buf_id);
1129 
1130         fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
1131 
1132         buf_num = hweight32(cfg);
1133 
1134         if (buf_type == IPP_BUF_ENQUEUE && buf_num >= FIMC_BUF_START)
1135                 fimc_mask_irq(ctx, true);
1136         else if (buf_type == IPP_BUF_DEQUEUE && buf_num <= FIMC_BUF_STOP)
1137                 fimc_mask_irq(ctx, false);
1138 
1139         spin_unlock_irqrestore(&ctx->lock, flags);
1140 }
1141 
1142 static int fimc_dst_set_addr(struct device *dev,
1143                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1144                 enum drm_exynos_ipp_buf_type buf_type)
1145 {
1146         struct fimc_context *ctx = get_fimc_context(dev);
1147         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1148         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1149         struct drm_exynos_ipp_property *property;
1150         struct drm_exynos_ipp_config *config;
1151 
1152         if (!c_node) {
1153                 DRM_ERROR("failed to get c_node.\n");
1154                 return -EINVAL;
1155         }
1156 
1157         property = &c_node->property;
1158 
1159         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1160                 property->prop_id, buf_id, buf_type);
1161 
1162         if (buf_id > FIMC_MAX_DST) {
1163                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1164                 return -ENOMEM;
1165         }
1166 
1167         /* address register set */
1168         switch (buf_type) {
1169         case IPP_BUF_ENQUEUE:
1170                 config = &property->config[EXYNOS_DRM_OPS_DST];
1171 
1172                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
1173                         EXYNOS_CIOYSA(buf_id));
1174 
1175                 if (config->fmt == DRM_FORMAT_YVU420) {
1176                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1177                                 EXYNOS_CIOCBSA(buf_id));
1178                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1179                                 EXYNOS_CIOCRSA(buf_id));
1180                 } else {
1181                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1182                                 EXYNOS_CIOCBSA(buf_id));
1183                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1184                                 EXYNOS_CIOCRSA(buf_id));
1185                 }
1186                 break;
1187         case IPP_BUF_DEQUEUE:
1188                 fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id));
1189                 fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id));
1190                 fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id));
1191                 break;
1192         default:
1193                 /* bypass */
1194                 break;
1195         }
1196 
1197         fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1198 
1199         return 0;
1200 }
1201 
1202 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1203         .set_fmt = fimc_dst_set_fmt,
1204         .set_transf = fimc_dst_set_transf,
1205         .set_size = fimc_dst_set_size,
1206         .set_addr = fimc_dst_set_addr,
1207 };
1208 
1209 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1210 {
1211         DRM_DEBUG_KMS("enable[%d]\n", enable);
1212 
1213         if (enable) {
1214                 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1215                 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1216                 ctx->suspended = false;
1217         } else {
1218                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1219                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1220                 ctx->suspended = true;
1221         }
1222 
1223         return 0;
1224 }
1225 
1226 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1227 {
1228         struct fimc_context *ctx = dev_id;
1229         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1230         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1231         struct drm_exynos_ipp_event_work *event_work =
1232                 c_node->event_work;
1233         int buf_id;
1234 
1235         DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1236 
1237         fimc_clear_irq(ctx);
1238         if (fimc_check_ovf(ctx))
1239                 return IRQ_NONE;
1240 
1241         if (!fimc_check_frame_end(ctx))
1242                 return IRQ_NONE;
1243 
1244         buf_id = fimc_get_buf_id(ctx);
1245         if (buf_id < 0)
1246                 return IRQ_HANDLED;
1247 
1248         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1249 
1250         fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1251 
1252         event_work->ippdrv = ippdrv;
1253         event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1254         queue_work(ippdrv->event_workq, &event_work->work);
1255 
1256         return IRQ_HANDLED;
1257 }
1258 
1259 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1260 {
1261         struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1262 
1263         prop_list->version = 1;
1264         prop_list->writeback = 1;
1265         prop_list->refresh_min = FIMC_REFRESH_MIN;
1266         prop_list->refresh_max = FIMC_REFRESH_MAX;
1267         prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1268                                 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1269                                 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1270         prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1271                                 (1 << EXYNOS_DRM_DEGREE_90) |
1272                                 (1 << EXYNOS_DRM_DEGREE_180) |
1273                                 (1 << EXYNOS_DRM_DEGREE_270);
1274         prop_list->csc = 1;
1275         prop_list->crop = 1;
1276         prop_list->crop_max.hsize = FIMC_CROP_MAX;
1277         prop_list->crop_max.vsize = FIMC_CROP_MAX;
1278         prop_list->crop_min.hsize = FIMC_CROP_MIN;
1279         prop_list->crop_min.vsize = FIMC_CROP_MIN;
1280         prop_list->scale = 1;
1281         prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1282         prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1283         prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1284         prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1285 
1286         return 0;
1287 }
1288 
1289 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1290 {
1291         switch (flip) {
1292         case EXYNOS_DRM_FLIP_NONE:
1293         case EXYNOS_DRM_FLIP_VERTICAL:
1294         case EXYNOS_DRM_FLIP_HORIZONTAL:
1295         case EXYNOS_DRM_FLIP_BOTH:
1296                 return true;
1297         default:
1298                 DRM_DEBUG_KMS("invalid flip\n");
1299                 return false;
1300         }
1301 }
1302 
1303 static int fimc_ippdrv_check_property(struct device *dev,
1304                 struct drm_exynos_ipp_property *property)
1305 {
1306         struct fimc_context *ctx = get_fimc_context(dev);
1307         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1308         struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1309         struct drm_exynos_ipp_config *config;
1310         struct drm_exynos_pos *pos;
1311         struct drm_exynos_sz *sz;
1312         bool swap;
1313         int i;
1314 
1315         for_each_ipp_ops(i) {
1316                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1317                         (property->cmd == IPP_CMD_WB))
1318                         continue;
1319 
1320                 config = &property->config[i];
1321                 pos = &config->pos;
1322                 sz = &config->sz;
1323 
1324                 /* check for flip */
1325                 if (!fimc_check_drm_flip(config->flip)) {
1326                         DRM_ERROR("invalid flip.\n");
1327                         goto err_property;
1328                 }
1329 
1330                 /* check for degree */
1331                 switch (config->degree) {
1332                 case EXYNOS_DRM_DEGREE_90:
1333                 case EXYNOS_DRM_DEGREE_270:
1334                         swap = true;
1335                         break;
1336                 case EXYNOS_DRM_DEGREE_0:
1337                 case EXYNOS_DRM_DEGREE_180:
1338                         swap = false;
1339                         break;
1340                 default:
1341                         DRM_ERROR("invalid degree.\n");
1342                         goto err_property;
1343                 }
1344 
1345                 /* check for buffer bound */
1346                 if ((pos->x + pos->w > sz->hsize) ||
1347                         (pos->y + pos->h > sz->vsize)) {
1348                         DRM_ERROR("out of buf bound.\n");
1349                         goto err_property;
1350                 }
1351 
1352                 /* check for crop */
1353                 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1354                         if (swap) {
1355                                 if ((pos->h < pp->crop_min.hsize) ||
1356                                         (sz->vsize > pp->crop_max.hsize) ||
1357                                         (pos->w < pp->crop_min.vsize) ||
1358                                         (sz->hsize > pp->crop_max.vsize)) {
1359                                         DRM_ERROR("out of crop size.\n");
1360                                         goto err_property;
1361                                 }
1362                         } else {
1363                                 if ((pos->w < pp->crop_min.hsize) ||
1364                                         (sz->hsize > pp->crop_max.hsize) ||
1365                                         (pos->h < pp->crop_min.vsize) ||
1366                                         (sz->vsize > pp->crop_max.vsize)) {
1367                                         DRM_ERROR("out of crop size.\n");
1368                                         goto err_property;
1369                                 }
1370                         }
1371                 }
1372 
1373                 /* check for scale */
1374                 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1375                         if (swap) {
1376                                 if ((pos->h < pp->scale_min.hsize) ||
1377                                         (sz->vsize > pp->scale_max.hsize) ||
1378                                         (pos->w < pp->scale_min.vsize) ||
1379                                         (sz->hsize > pp->scale_max.vsize)) {
1380                                         DRM_ERROR("out of scale size.\n");
1381                                         goto err_property;
1382                                 }
1383                         } else {
1384                                 if ((pos->w < pp->scale_min.hsize) ||
1385                                         (sz->hsize > pp->scale_max.hsize) ||
1386                                         (pos->h < pp->scale_min.vsize) ||
1387                                         (sz->vsize > pp->scale_max.vsize)) {
1388                                         DRM_ERROR("out of scale size.\n");
1389                                         goto err_property;
1390                                 }
1391                         }
1392                 }
1393         }
1394 
1395         return 0;
1396 
1397 err_property:
1398         for_each_ipp_ops(i) {
1399                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1400                         (property->cmd == IPP_CMD_WB))
1401                         continue;
1402 
1403                 config = &property->config[i];
1404                 pos = &config->pos;
1405                 sz = &config->sz;
1406 
1407                 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1408                         i ? "dst" : "src", config->flip, config->degree,
1409                         pos->x, pos->y, pos->w, pos->h,
1410                         sz->hsize, sz->vsize);
1411         }
1412 
1413         return -EINVAL;
1414 }
1415 
1416 static void fimc_clear_addr(struct fimc_context *ctx)
1417 {
1418         int i;
1419 
1420         for (i = 0; i < FIMC_MAX_SRC; i++) {
1421                 fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
1422                 fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
1423                 fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
1424         }
1425 
1426         for (i = 0; i < FIMC_MAX_DST; i++) {
1427                 fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
1428                 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
1429                 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
1430         }
1431 }
1432 
1433 static int fimc_ippdrv_reset(struct device *dev)
1434 {
1435         struct fimc_context *ctx = get_fimc_context(dev);
1436 
1437         /* reset h/w block */
1438         fimc_sw_reset(ctx);
1439 
1440         /* reset scaler capability */
1441         memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1442 
1443         fimc_clear_addr(ctx);
1444 
1445         return 0;
1446 }
1447 
1448 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1449 {
1450         struct fimc_context *ctx = get_fimc_context(dev);
1451         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1452         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1453         struct drm_exynos_ipp_property *property;
1454         struct drm_exynos_ipp_config *config;
1455         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
1456         struct drm_exynos_ipp_set_wb set_wb;
1457         int ret, i;
1458         u32 cfg0, cfg1;
1459 
1460         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1461 
1462         if (!c_node) {
1463                 DRM_ERROR("failed to get c_node.\n");
1464                 return -EINVAL;
1465         }
1466 
1467         property = &c_node->property;
1468 
1469         fimc_mask_irq(ctx, true);
1470 
1471         for_each_ipp_ops(i) {
1472                 config = &property->config[i];
1473                 img_pos[i] = config->pos;
1474         }
1475 
1476         ret = fimc_set_prescaler(ctx, &ctx->sc,
1477                 &img_pos[EXYNOS_DRM_OPS_SRC],
1478                 &img_pos[EXYNOS_DRM_OPS_DST]);
1479         if (ret) {
1480                 dev_err(dev, "failed to set precalser.\n");
1481                 return ret;
1482         }
1483 
1484         /* If set ture, we can save jpeg about screen */
1485         fimc_handle_jpeg(ctx, false);
1486         fimc_set_scaler(ctx, &ctx->sc);
1487         fimc_set_polarity(ctx, &ctx->pol);
1488 
1489         switch (cmd) {
1490         case IPP_CMD_M2M:
1491                 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1492                 fimc_handle_lastend(ctx, false);
1493 
1494                 /* setup dma */
1495                 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1496                 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1497                 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1498                 fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1499                 break;
1500         case IPP_CMD_WB:
1501                 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1502                 fimc_handle_lastend(ctx, true);
1503 
1504                 /* setup FIMD */
1505                 ret = fimc_set_camblk_fimd0_wb(ctx);
1506                 if (ret < 0) {
1507                         dev_err(dev, "camblk setup failed.\n");
1508                         return ret;
1509                 }
1510 
1511                 set_wb.enable = 1;
1512                 set_wb.refresh = property->refresh_rate;
1513                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1514                 break;
1515         case IPP_CMD_OUTPUT:
1516         default:
1517                 ret = -EINVAL;
1518                 dev_err(dev, "invalid operations.\n");
1519                 return ret;
1520         }
1521 
1522         /* Reset status */
1523         fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1524 
1525         cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1526         cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1527         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1528 
1529         /* Scaler */
1530         cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1531         cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1532         cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1533                 EXYNOS_CISCCTRL_SCALERSTART);
1534 
1535         fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1536 
1537         /* Enable image capture*/
1538         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1539         fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1540 
1541         /* Disable frame end irq */
1542         fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1543 
1544         fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1545 
1546         if (cmd == IPP_CMD_M2M)
1547                 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1548 
1549         return 0;
1550 }
1551 
1552 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1553 {
1554         struct fimc_context *ctx = get_fimc_context(dev);
1555         struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1556         u32 cfg;
1557 
1558         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1559 
1560         switch (cmd) {
1561         case IPP_CMD_M2M:
1562                 /* Source clear */
1563                 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1564                 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1565                 cfg &= ~EXYNOS_MSCTRL_ENVID;
1566                 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1567                 break;
1568         case IPP_CMD_WB:
1569                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1570                 break;
1571         case IPP_CMD_OUTPUT:
1572         default:
1573                 dev_err(dev, "invalid operations.\n");
1574                 break;
1575         }
1576 
1577         fimc_mask_irq(ctx, false);
1578 
1579         /* reset sequence */
1580         fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1581 
1582         /* Scaler disable */
1583         fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1584 
1585         /* Disable image capture */
1586         fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1587                 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1588 
1589         /* Enable frame end irq */
1590         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1591 }
1592 
1593 static void fimc_put_clocks(struct fimc_context *ctx)
1594 {
1595         int i;
1596 
1597         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1598                 if (IS_ERR(ctx->clocks[i]))
1599                         continue;
1600                 clk_put(ctx->clocks[i]);
1601                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1602         }
1603 }
1604 
1605 static int fimc_setup_clocks(struct fimc_context *ctx)
1606 {
1607         struct device *fimc_dev = ctx->ippdrv.dev;
1608         struct device *dev;
1609         int ret, i;
1610 
1611         for (i = 0; i < FIMC_CLKS_MAX; i++)
1612                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1613 
1614         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1615                 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1616                         dev = fimc_dev->parent;
1617                 else
1618                         dev = fimc_dev;
1619 
1620                 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1621                 if (IS_ERR(ctx->clocks[i])) {
1622                         if (i >= FIMC_CLK_MUX)
1623                                 break;
1624                         ret = PTR_ERR(ctx->clocks[i]);
1625                         dev_err(fimc_dev, "failed to get clock: %s\n",
1626                                                 fimc_clock_names[i]);
1627                         goto e_clk_free;
1628                 }
1629         }
1630 
1631         /* Optional FIMC LCLK parent clock setting */
1632         if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1633                 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1634                                      ctx->clocks[FIMC_CLK_PARENT]);
1635                 if (ret < 0) {
1636                         dev_err(fimc_dev, "failed to set parent.\n");
1637                         goto e_clk_free;
1638                 }
1639         }
1640 
1641         ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1642         if (ret < 0)
1643                 goto e_clk_free;
1644 
1645         ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1646         if (!ret)
1647                 return ret;
1648 e_clk_free:
1649         fimc_put_clocks(ctx);
1650         return ret;
1651 }
1652 
1653 static int fimc_parse_dt(struct fimc_context *ctx)
1654 {
1655         struct device_node *node = ctx->ippdrv.dev->of_node;
1656 
1657         /* Handle only devices that support the LCD Writeback data path */
1658         if (!of_property_read_bool(node, "samsung,lcd-wb"))
1659                 return -ENODEV;
1660 
1661         if (of_property_read_u32(node, "clock-frequency",
1662                                         &ctx->clk_frequency))
1663                 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1664 
1665         ctx->id = of_alias_get_id(node, "fimc");
1666 
1667         if (ctx->id < 0) {
1668                 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1669                 return -EINVAL;
1670         }
1671 
1672         return 0;
1673 }
1674 
1675 static int fimc_probe(struct platform_device *pdev)
1676 {
1677         struct device *dev = &pdev->dev;
1678         struct fimc_context *ctx;
1679         struct resource *res;
1680         struct exynos_drm_ippdrv *ippdrv;
1681         int ret;
1682 
1683         if (!dev->of_node) {
1684                 dev_err(dev, "device tree node not found.\n");
1685                 return -ENODEV;
1686         }
1687 
1688         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1689         if (!ctx)
1690                 return -ENOMEM;
1691 
1692         ctx->ippdrv.dev = dev;
1693 
1694         ret = fimc_parse_dt(ctx);
1695         if (ret < 0)
1696                 return ret;
1697 
1698         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1699                                                 "samsung,sysreg");
1700         if (IS_ERR(ctx->sysreg)) {
1701                 dev_err(dev, "syscon regmap lookup failed.\n");
1702                 return PTR_ERR(ctx->sysreg);
1703         }
1704 
1705         /* resource memory */
1706         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1707         ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1708         if (IS_ERR(ctx->regs))
1709                 return PTR_ERR(ctx->regs);
1710 
1711         /* resource irq */
1712         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1713         if (!res) {
1714                 dev_err(dev, "failed to request irq resource.\n");
1715                 return -ENOENT;
1716         }
1717 
1718         ctx->irq = res->start;
1719         ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1720                 IRQF_ONESHOT, "drm_fimc", ctx);
1721         if (ret < 0) {
1722                 dev_err(dev, "failed to request irq.\n");
1723                 return ret;
1724         }
1725 
1726         ret = fimc_setup_clocks(ctx);
1727         if (ret < 0)
1728                 return ret;
1729 
1730         ippdrv = &ctx->ippdrv;
1731         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1732         ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1733         ippdrv->check_property = fimc_ippdrv_check_property;
1734         ippdrv->reset = fimc_ippdrv_reset;
1735         ippdrv->start = fimc_ippdrv_start;
1736         ippdrv->stop = fimc_ippdrv_stop;
1737         ret = fimc_init_prop_list(ippdrv);
1738         if (ret < 0) {
1739                 dev_err(dev, "failed to init property list.\n");
1740                 goto err_put_clk;
1741         }
1742 
1743         DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1744 
1745         spin_lock_init(&ctx->lock);
1746         platform_set_drvdata(pdev, ctx);
1747 
1748         pm_runtime_set_active(dev);
1749         pm_runtime_enable(dev);
1750 
1751         ret = exynos_drm_ippdrv_register(ippdrv);
1752         if (ret < 0) {
1753                 dev_err(dev, "failed to register drm fimc device.\n");
1754                 goto err_pm_dis;
1755         }
1756 
1757         dev_info(dev, "drm fimc registered successfully.\n");
1758 
1759         return 0;
1760 
1761 err_pm_dis:
1762         pm_runtime_disable(dev);
1763 err_put_clk:
1764         fimc_put_clocks(ctx);
1765 
1766         return ret;
1767 }
1768 
1769 static int fimc_remove(struct platform_device *pdev)
1770 {
1771         struct device *dev = &pdev->dev;
1772         struct fimc_context *ctx = get_fimc_context(dev);
1773         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1774 
1775         exynos_drm_ippdrv_unregister(ippdrv);
1776 
1777         fimc_put_clocks(ctx);
1778         pm_runtime_set_suspended(dev);
1779         pm_runtime_disable(dev);
1780 
1781         return 0;
1782 }
1783 
1784 #ifdef CONFIG_PM_SLEEP
1785 static int fimc_suspend(struct device *dev)
1786 {
1787         struct fimc_context *ctx = get_fimc_context(dev);
1788 
1789         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1790 
1791         if (pm_runtime_suspended(dev))
1792                 return 0;
1793 
1794         return fimc_clk_ctrl(ctx, false);
1795 }
1796 
1797 static int fimc_resume(struct device *dev)
1798 {
1799         struct fimc_context *ctx = get_fimc_context(dev);
1800 
1801         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1802 
1803         if (!pm_runtime_suspended(dev))
1804                 return fimc_clk_ctrl(ctx, true);
1805 
1806         return 0;
1807 }
1808 #endif
1809 
1810 #ifdef CONFIG_PM
1811 static int fimc_runtime_suspend(struct device *dev)
1812 {
1813         struct fimc_context *ctx = get_fimc_context(dev);
1814 
1815         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1816 
1817         return  fimc_clk_ctrl(ctx, false);
1818 }
1819 
1820 static int fimc_runtime_resume(struct device *dev)
1821 {
1822         struct fimc_context *ctx = get_fimc_context(dev);
1823 
1824         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1825 
1826         return  fimc_clk_ctrl(ctx, true);
1827 }
1828 #endif
1829 
1830 static const struct dev_pm_ops fimc_pm_ops = {
1831         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1832         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1833 };
1834 
1835 static const struct of_device_id fimc_of_match[] = {
1836         { .compatible = "samsung,exynos4210-fimc" },
1837         { .compatible = "samsung,exynos4212-fimc" },
1838         { },
1839 };
1840 MODULE_DEVICE_TABLE(of, fimc_of_match);
1841 
1842 struct platform_driver fimc_driver = {
1843         .probe          = fimc_probe,
1844         .remove         = fimc_remove,
1845         .driver         = {
1846                 .of_match_table = fimc_of_match,
1847                 .name   = "exynos-drm-fimc",
1848                 .owner  = THIS_MODULE,
1849                 .pm     = &fimc_pm_ops,
1850         },
1851 };
1852 
1853 

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