Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/gpu/drm/drm_edid.c

  1 /*
  2  * Copyright (c) 2006 Luc Verhaegen (quirks list)
  3  * Copyright (c) 2007-2008 Intel Corporation
  4  *   Jesse Barnes <jesse.barnes@intel.com>
  5  * Copyright 2010 Red Hat, Inc.
  6  *
  7  * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
  8  * FB layer.
  9  *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
 10  *
 11  * Permission is hereby granted, free of charge, to any person obtaining a
 12  * copy of this software and associated documentation files (the "Software"),
 13  * to deal in the Software without restriction, including without limitation
 14  * the rights to use, copy, modify, merge, publish, distribute, sub license,
 15  * and/or sell copies of the Software, and to permit persons to whom the
 16  * Software is furnished to do so, subject to the following conditions:
 17  *
 18  * The above copyright notice and this permission notice (including the
 19  * next paragraph) shall be included in all copies or substantial portions
 20  * of the Software.
 21  *
 22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 24  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 27  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 28  * DEALINGS IN THE SOFTWARE.
 29  */
 30 #include <linux/kernel.h>
 31 #include <linux/slab.h>
 32 #include <linux/hdmi.h>
 33 #include <linux/i2c.h>
 34 #include <linux/module.h>
 35 #include <linux/vga_switcheroo.h>
 36 #include <drm/drmP.h>
 37 #include <drm/drm_edid.h>
 38 #include <drm/drm_displayid.h>
 39 
 40 #define version_greater(edid, maj, min) \
 41         (((edid)->version > (maj)) || \
 42          ((edid)->version == (maj) && (edid)->revision > (min)))
 43 
 44 #define EDID_EST_TIMINGS 16
 45 #define EDID_STD_TIMINGS 8
 46 #define EDID_DETAILED_TIMINGS 4
 47 
 48 /*
 49  * EDID blocks out in the wild have a variety of bugs, try to collect
 50  * them here (note that userspace may work around broken monitors first,
 51  * but fixes should make their way here so that the kernel "just works"
 52  * on as many displays as possible).
 53  */
 54 
 55 /* First detailed mode wrong, use largest 60Hz mode */
 56 #define EDID_QUIRK_PREFER_LARGE_60              (1 << 0)
 57 /* Reported 135MHz pixel clock is too high, needs adjustment */
 58 #define EDID_QUIRK_135_CLOCK_TOO_HIGH           (1 << 1)
 59 /* Prefer the largest mode at 75 Hz */
 60 #define EDID_QUIRK_PREFER_LARGE_75              (1 << 2)
 61 /* Detail timing is in cm not mm */
 62 #define EDID_QUIRK_DETAILED_IN_CM               (1 << 3)
 63 /* Detailed timing descriptors have bogus size values, so just take the
 64  * maximum size and use that.
 65  */
 66 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE    (1 << 4)
 67 /* Monitor forgot to set the first detailed is preferred bit. */
 68 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED     (1 << 5)
 69 /* use +hsync +vsync for detailed mode */
 70 #define EDID_QUIRK_DETAILED_SYNC_PP             (1 << 6)
 71 /* Force reduced-blanking timings for detailed modes */
 72 #define EDID_QUIRK_FORCE_REDUCED_BLANKING       (1 << 7)
 73 /* Force 8bpc */
 74 #define EDID_QUIRK_FORCE_8BPC                   (1 << 8)
 75 /* Force 12bpc */
 76 #define EDID_QUIRK_FORCE_12BPC                  (1 << 9)
 77 /* Force 6bpc */
 78 #define EDID_QUIRK_FORCE_6BPC                   (1 << 10)
 79 
 80 struct detailed_mode_closure {
 81         struct drm_connector *connector;
 82         struct edid *edid;
 83         bool preferred;
 84         u32 quirks;
 85         int modes;
 86 };
 87 
 88 #define LEVEL_DMT       0
 89 #define LEVEL_GTF       1
 90 #define LEVEL_GTF2      2
 91 #define LEVEL_CVT       3
 92 
 93 static struct edid_quirk {
 94         char vendor[4];
 95         int product_id;
 96         u32 quirks;
 97 } edid_quirk_list[] = {
 98         /* Acer AL1706 */
 99         { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
100         /* Acer F51 */
101         { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
102         /* Unknown Acer */
103         { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
104 
105         /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
106         { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
107 
108         /* Belinea 10 15 55 */
109         { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
110         { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
111 
112         /* Envision Peripherals, Inc. EN-7100e */
113         { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
114         /* Envision EN2028 */
115         { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
116 
117         /* Funai Electronics PM36B */
118         { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
119           EDID_QUIRK_DETAILED_IN_CM },
120 
121         /* LG Philips LCD LP154W01-A5 */
122         { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
123         { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
124 
125         /* Philips 107p5 CRT */
126         { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
127 
128         /* Proview AY765C */
129         { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
130 
131         /* Samsung SyncMaster 205BW.  Note: irony */
132         { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
133         /* Samsung SyncMaster 22[5-6]BW */
134         { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
135         { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
136 
137         /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
138         { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
139 
140         /* ViewSonic VA2026w */
141         { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
142 
143         /* Medion MD 30217 PG */
144         { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
145 
146         /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
147         { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
148 };
149 
150 /*
151  * Autogenerated from the DMT spec.
152  * This table is copied from xfree86/modes/xf86EdidModes.c.
153  */
154 static const struct drm_display_mode drm_dmt_modes[] = {
155         /* 0x01 - 640x350@85Hz */
156         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
157                    736, 832, 0, 350, 382, 385, 445, 0,
158                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
159         /* 0x02 - 640x400@85Hz */
160         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
161                    736, 832, 0, 400, 401, 404, 445, 0,
162                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
163         /* 0x03 - 720x400@85Hz */
164         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
165                    828, 936, 0, 400, 401, 404, 446, 0,
166                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
167         /* 0x04 - 640x480@60Hz */
168         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
169                    752, 800, 0, 480, 490, 492, 525, 0,
170                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
171         /* 0x05 - 640x480@72Hz */
172         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
173                    704, 832, 0, 480, 489, 492, 520, 0,
174                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
175         /* 0x06 - 640x480@75Hz */
176         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
177                    720, 840, 0, 480, 481, 484, 500, 0,
178                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
179         /* 0x07 - 640x480@85Hz */
180         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
181                    752, 832, 0, 480, 481, 484, 509, 0,
182                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
183         /* 0x08 - 800x600@56Hz */
184         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
185                    896, 1024, 0, 600, 601, 603, 625, 0,
186                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
187         /* 0x09 - 800x600@60Hz */
188         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
189                    968, 1056, 0, 600, 601, 605, 628, 0,
190                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
191         /* 0x0a - 800x600@72Hz */
192         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
193                    976, 1040, 0, 600, 637, 643, 666, 0,
194                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
195         /* 0x0b - 800x600@75Hz */
196         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
197                    896, 1056, 0, 600, 601, 604, 625, 0,
198                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
199         /* 0x0c - 800x600@85Hz */
200         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
201                    896, 1048, 0, 600, 601, 604, 631, 0,
202                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
203         /* 0x0d - 800x600@120Hz RB */
204         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
205                    880, 960, 0, 600, 603, 607, 636, 0,
206                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
207         /* 0x0e - 848x480@60Hz */
208         { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
209                    976, 1088, 0, 480, 486, 494, 517, 0,
210                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
211         /* 0x0f - 1024x768@43Hz, interlace */
212         { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
213                    1208, 1264, 0, 768, 768, 776, 817, 0,
214                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
215                    DRM_MODE_FLAG_INTERLACE) },
216         /* 0x10 - 1024x768@60Hz */
217         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
218                    1184, 1344, 0, 768, 771, 777, 806, 0,
219                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
220         /* 0x11 - 1024x768@70Hz */
221         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
222                    1184, 1328, 0, 768, 771, 777, 806, 0,
223                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
224         /* 0x12 - 1024x768@75Hz */
225         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
226                    1136, 1312, 0, 768, 769, 772, 800, 0,
227                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
228         /* 0x13 - 1024x768@85Hz */
229         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
230                    1168, 1376, 0, 768, 769, 772, 808, 0,
231                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
232         /* 0x14 - 1024x768@120Hz RB */
233         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
234                    1104, 1184, 0, 768, 771, 775, 813, 0,
235                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
236         /* 0x15 - 1152x864@75Hz */
237         { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
238                    1344, 1600, 0, 864, 865, 868, 900, 0,
239                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
240         /* 0x55 - 1280x720@60Hz */
241         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
242                    1430, 1650, 0, 720, 725, 730, 750, 0,
243                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
244         /* 0x16 - 1280x768@60Hz RB */
245         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
246                    1360, 1440, 0, 768, 771, 778, 790, 0,
247                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
248         /* 0x17 - 1280x768@60Hz */
249         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
250                    1472, 1664, 0, 768, 771, 778, 798, 0,
251                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
252         /* 0x18 - 1280x768@75Hz */
253         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
254                    1488, 1696, 0, 768, 771, 778, 805, 0,
255                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
256         /* 0x19 - 1280x768@85Hz */
257         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
258                    1496, 1712, 0, 768, 771, 778, 809, 0,
259                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
260         /* 0x1a - 1280x768@120Hz RB */
261         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
262                    1360, 1440, 0, 768, 771, 778, 813, 0,
263                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
264         /* 0x1b - 1280x800@60Hz RB */
265         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
266                    1360, 1440, 0, 800, 803, 809, 823, 0,
267                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
268         /* 0x1c - 1280x800@60Hz */
269         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
270                    1480, 1680, 0, 800, 803, 809, 831, 0,
271                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
272         /* 0x1d - 1280x800@75Hz */
273         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
274                    1488, 1696, 0, 800, 803, 809, 838, 0,
275                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
276         /* 0x1e - 1280x800@85Hz */
277         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
278                    1496, 1712, 0, 800, 803, 809, 843, 0,
279                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
280         /* 0x1f - 1280x800@120Hz RB */
281         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
282                    1360, 1440, 0, 800, 803, 809, 847, 0,
283                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
284         /* 0x20 - 1280x960@60Hz */
285         { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
286                    1488, 1800, 0, 960, 961, 964, 1000, 0,
287                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288         /* 0x21 - 1280x960@85Hz */
289         { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
290                    1504, 1728, 0, 960, 961, 964, 1011, 0,
291                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292         /* 0x22 - 1280x960@120Hz RB */
293         { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
294                    1360, 1440, 0, 960, 963, 967, 1017, 0,
295                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296         /* 0x23 - 1280x1024@60Hz */
297         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
298                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
299                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300         /* 0x24 - 1280x1024@75Hz */
301         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
302                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
303                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
304         /* 0x25 - 1280x1024@85Hz */
305         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
306                    1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
307                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
308         /* 0x26 - 1280x1024@120Hz RB */
309         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
310                    1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
311                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
312         /* 0x27 - 1360x768@60Hz */
313         { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
314                    1536, 1792, 0, 768, 771, 777, 795, 0,
315                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
316         /* 0x28 - 1360x768@120Hz RB */
317         { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
318                    1440, 1520, 0, 768, 771, 776, 813, 0,
319                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
320         /* 0x51 - 1366x768@60Hz */
321         { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
322                    1579, 1792, 0, 768, 771, 774, 798, 0,
323                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
324         /* 0x56 - 1366x768@60Hz */
325         { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
326                    1436, 1500, 0, 768, 769, 772, 800, 0,
327                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
328         /* 0x29 - 1400x1050@60Hz RB */
329         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
330                    1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
331                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
332         /* 0x2a - 1400x1050@60Hz */
333         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
334                    1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
335                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
336         /* 0x2b - 1400x1050@75Hz */
337         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
338                    1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
339                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
340         /* 0x2c - 1400x1050@85Hz */
341         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
342                    1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
343                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
344         /* 0x2d - 1400x1050@120Hz RB */
345         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
346                    1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
347                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
348         /* 0x2e - 1440x900@60Hz RB */
349         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
350                    1520, 1600, 0, 900, 903, 909, 926, 0,
351                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
352         /* 0x2f - 1440x900@60Hz */
353         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
354                    1672, 1904, 0, 900, 903, 909, 934, 0,
355                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
356         /* 0x30 - 1440x900@75Hz */
357         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
358                    1688, 1936, 0, 900, 903, 909, 942, 0,
359                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
360         /* 0x31 - 1440x900@85Hz */
361         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
362                    1696, 1952, 0, 900, 903, 909, 948, 0,
363                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364         /* 0x32 - 1440x900@120Hz RB */
365         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
366                    1520, 1600, 0, 900, 903, 909, 953, 0,
367                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
368         /* 0x53 - 1600x900@60Hz */
369         { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
370                    1704, 1800, 0, 900, 901, 904, 1000, 0,
371                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
372         /* 0x33 - 1600x1200@60Hz */
373         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
374                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
375                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
376         /* 0x34 - 1600x1200@65Hz */
377         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
378                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
379                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
380         /* 0x35 - 1600x1200@70Hz */
381         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
382                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
383                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
384         /* 0x36 - 1600x1200@75Hz */
385         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
386                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
387                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
388         /* 0x37 - 1600x1200@85Hz */
389         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
390                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
391                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
392         /* 0x38 - 1600x1200@120Hz RB */
393         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
394                    1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
395                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
396         /* 0x39 - 1680x1050@60Hz RB */
397         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
398                    1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
399                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
400         /* 0x3a - 1680x1050@60Hz */
401         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
402                    1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
403                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
404         /* 0x3b - 1680x1050@75Hz */
405         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
406                    1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
407                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
408         /* 0x3c - 1680x1050@85Hz */
409         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
410                    1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
411                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
412         /* 0x3d - 1680x1050@120Hz RB */
413         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
414                    1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
415                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
416         /* 0x3e - 1792x1344@60Hz */
417         { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
418                    2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
419                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
420         /* 0x3f - 1792x1344@75Hz */
421         { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
422                    2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
423                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
424         /* 0x40 - 1792x1344@120Hz RB */
425         { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
426                    1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
427                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
428         /* 0x41 - 1856x1392@60Hz */
429         { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
430                    2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
431                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432         /* 0x42 - 1856x1392@75Hz */
433         { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
434                    2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
435                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436         /* 0x43 - 1856x1392@120Hz RB */
437         { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
438                    1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
439                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
440         /* 0x52 - 1920x1080@60Hz */
441         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
442                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
443                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
444         /* 0x44 - 1920x1200@60Hz RB */
445         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
446                    2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
447                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448         /* 0x45 - 1920x1200@60Hz */
449         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
450                    2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
451                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452         /* 0x46 - 1920x1200@75Hz */
453         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
454                    2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
455                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456         /* 0x47 - 1920x1200@85Hz */
457         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
458                    2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
459                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
460         /* 0x48 - 1920x1200@120Hz RB */
461         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
462                    2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
463                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
464         /* 0x49 - 1920x1440@60Hz */
465         { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
466                    2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
467                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
468         /* 0x4a - 1920x1440@75Hz */
469         { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
470                    2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
471                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
472         /* 0x4b - 1920x1440@120Hz RB */
473         { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
474                    2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
475                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
476         /* 0x54 - 2048x1152@60Hz */
477         { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
478                    2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
479                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
480         /* 0x4c - 2560x1600@60Hz RB */
481         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
482                    2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
483                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
484         /* 0x4d - 2560x1600@60Hz */
485         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
486                    3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
487                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
488         /* 0x4e - 2560x1600@75Hz */
489         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
490                    3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
491                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
492         /* 0x4f - 2560x1600@85Hz */
493         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
494                    3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
495                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
496         /* 0x50 - 2560x1600@120Hz RB */
497         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
498                    2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
499                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
500         /* 0x57 - 4096x2160@60Hz RB */
501         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
502                    4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
503                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
504         /* 0x58 - 4096x2160@59.94Hz RB */
505         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
506                    4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
507                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
508 };
509 
510 /*
511  * These more or less come from the DMT spec.  The 720x400 modes are
512  * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
513  * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
514  * should be 1152x870, again for the Mac, but instead we use the x864 DMT
515  * mode.
516  *
517  * The DMT modes have been fact-checked; the rest are mild guesses.
518  */
519 static const struct drm_display_mode edid_est_modes[] = {
520         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
521                    968, 1056, 0, 600, 601, 605, 628, 0,
522                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
523         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
524                    896, 1024, 0, 600, 601, 603,  625, 0,
525                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
526         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
527                    720, 840, 0, 480, 481, 484, 500, 0,
528                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
529         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
530                    704,  832, 0, 480, 489, 492, 520, 0,
531                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
532         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
533                    768,  864, 0, 480, 483, 486, 525, 0,
534                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
535         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
536                    752, 800, 0, 480, 490, 492, 525, 0,
537                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
538         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
539                    846, 900, 0, 400, 421, 423,  449, 0,
540                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
541         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
542                    846,  900, 0, 400, 412, 414, 449, 0,
543                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
544         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
545                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
546                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
547         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
548                    1136, 1312, 0,  768, 769, 772, 800, 0,
549                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
550         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
551                    1184, 1328, 0,  768, 771, 777, 806, 0,
552                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
553         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
554                    1184, 1344, 0,  768, 771, 777, 806, 0,
555                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
556         { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
557                    1208, 1264, 0, 768, 768, 776, 817, 0,
558                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
559         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
560                    928, 1152, 0, 624, 625, 628, 667, 0,
561                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
562         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
563                    896, 1056, 0, 600, 601, 604,  625, 0,
564                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
565         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
566                    976, 1040, 0, 600, 637, 643, 666, 0,
567                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
568         { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
569                    1344, 1600, 0,  864, 865, 868, 900, 0,
570                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
571 };
572 
573 struct minimode {
574         short w;
575         short h;
576         short r;
577         short rb;
578 };
579 
580 static const struct minimode est3_modes[] = {
581         /* byte 6 */
582         { 640, 350, 85, 0 },
583         { 640, 400, 85, 0 },
584         { 720, 400, 85, 0 },
585         { 640, 480, 85, 0 },
586         { 848, 480, 60, 0 },
587         { 800, 600, 85, 0 },
588         { 1024, 768, 85, 0 },
589         { 1152, 864, 75, 0 },
590         /* byte 7 */
591         { 1280, 768, 60, 1 },
592         { 1280, 768, 60, 0 },
593         { 1280, 768, 75, 0 },
594         { 1280, 768, 85, 0 },
595         { 1280, 960, 60, 0 },
596         { 1280, 960, 85, 0 },
597         { 1280, 1024, 60, 0 },
598         { 1280, 1024, 85, 0 },
599         /* byte 8 */
600         { 1360, 768, 60, 0 },
601         { 1440, 900, 60, 1 },
602         { 1440, 900, 60, 0 },
603         { 1440, 900, 75, 0 },
604         { 1440, 900, 85, 0 },
605         { 1400, 1050, 60, 1 },
606         { 1400, 1050, 60, 0 },
607         { 1400, 1050, 75, 0 },
608         /* byte 9 */
609         { 1400, 1050, 85, 0 },
610         { 1680, 1050, 60, 1 },
611         { 1680, 1050, 60, 0 },
612         { 1680, 1050, 75, 0 },
613         { 1680, 1050, 85, 0 },
614         { 1600, 1200, 60, 0 },
615         { 1600, 1200, 65, 0 },
616         { 1600, 1200, 70, 0 },
617         /* byte 10 */
618         { 1600, 1200, 75, 0 },
619         { 1600, 1200, 85, 0 },
620         { 1792, 1344, 60, 0 },
621         { 1792, 1344, 75, 0 },
622         { 1856, 1392, 60, 0 },
623         { 1856, 1392, 75, 0 },
624         { 1920, 1200, 60, 1 },
625         { 1920, 1200, 60, 0 },
626         /* byte 11 */
627         { 1920, 1200, 75, 0 },
628         { 1920, 1200, 85, 0 },
629         { 1920, 1440, 60, 0 },
630         { 1920, 1440, 75, 0 },
631 };
632 
633 static const struct minimode extra_modes[] = {
634         { 1024, 576,  60, 0 },
635         { 1366, 768,  60, 0 },
636         { 1600, 900,  60, 0 },
637         { 1680, 945,  60, 0 },
638         { 1920, 1080, 60, 0 },
639         { 2048, 1152, 60, 0 },
640         { 2048, 1536, 60, 0 },
641 };
642 
643 /*
644  * Probably taken from CEA-861 spec.
645  * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
646  *
647  * Index using the VIC.
648  */
649 static const struct drm_display_mode edid_cea_modes[] = {
650         /* 0 - dummy, VICs start at 1 */
651         { },
652         /* 1 - 640x480@60Hz */
653         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
654                    752, 800, 0, 480, 490, 492, 525, 0,
655                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
656           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
657         /* 2 - 720x480@60Hz */
658         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
659                    798, 858, 0, 480, 489, 495, 525, 0,
660                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
661           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
662         /* 3 - 720x480@60Hz */
663         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
664                    798, 858, 0, 480, 489, 495, 525, 0,
665                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
666           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
667         /* 4 - 1280x720@60Hz */
668         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
669                    1430, 1650, 0, 720, 725, 730, 750, 0,
670                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
671           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
672         /* 5 - 1920x1080i@60Hz */
673         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
674                    2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
675                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
676                         DRM_MODE_FLAG_INTERLACE),
677           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
678         /* 6 - 720(1440)x480i@60Hz */
679         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
680                    801, 858, 0, 480, 488, 494, 525, 0,
681                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
682                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
683           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
684         /* 7 - 720(1440)x480i@60Hz */
685         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
686                    801, 858, 0, 480, 488, 494, 525, 0,
687                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
688                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
689           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
690         /* 8 - 720(1440)x240@60Hz */
691         { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
692                    801, 858, 0, 240, 244, 247, 262, 0,
693                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
694                         DRM_MODE_FLAG_DBLCLK),
695           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
696         /* 9 - 720(1440)x240@60Hz */
697         { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
698                    801, 858, 0, 240, 244, 247, 262, 0,
699                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
700                         DRM_MODE_FLAG_DBLCLK),
701           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
702         /* 10 - 2880x480i@60Hz */
703         { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
704                    3204, 3432, 0, 480, 488, 494, 525, 0,
705                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
706                         DRM_MODE_FLAG_INTERLACE),
707           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
708         /* 11 - 2880x480i@60Hz */
709         { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
710                    3204, 3432, 0, 480, 488, 494, 525, 0,
711                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
712                         DRM_MODE_FLAG_INTERLACE),
713           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
714         /* 12 - 2880x240@60Hz */
715         { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
716                    3204, 3432, 0, 240, 244, 247, 262, 0,
717                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
718           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
719         /* 13 - 2880x240@60Hz */
720         { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
721                    3204, 3432, 0, 240, 244, 247, 262, 0,
722                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
723           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
724         /* 14 - 1440x480@60Hz */
725         { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
726                    1596, 1716, 0, 480, 489, 495, 525, 0,
727                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
728           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
729         /* 15 - 1440x480@60Hz */
730         { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
731                    1596, 1716, 0, 480, 489, 495, 525, 0,
732                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
733           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734         /* 16 - 1920x1080@60Hz */
735         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
736                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
737                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
738           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
739         /* 17 - 720x576@50Hz */
740         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
741                    796, 864, 0, 576, 581, 586, 625, 0,
742                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
744         /* 18 - 720x576@50Hz */
745         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
746                    796, 864, 0, 576, 581, 586, 625, 0,
747                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
748           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
749         /* 19 - 1280x720@50Hz */
750         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
751                    1760, 1980, 0, 720, 725, 730, 750, 0,
752                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
753           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
754         /* 20 - 1920x1080i@50Hz */
755         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
756                    2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
757                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
758                         DRM_MODE_FLAG_INTERLACE),
759           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
760         /* 21 - 720(1440)x576i@50Hz */
761         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
762                    795, 864, 0, 576, 580, 586, 625, 0,
763                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
764                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
765           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
766         /* 22 - 720(1440)x576i@50Hz */
767         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
768                    795, 864, 0, 576, 580, 586, 625, 0,
769                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
770                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
771           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
772         /* 23 - 720(1440)x288@50Hz */
773         { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
774                    795, 864, 0, 288, 290, 293, 312, 0,
775                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
776                         DRM_MODE_FLAG_DBLCLK),
777           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
778         /* 24 - 720(1440)x288@50Hz */
779         { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
780                    795, 864, 0, 288, 290, 293, 312, 0,
781                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
782                         DRM_MODE_FLAG_DBLCLK),
783           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
784         /* 25 - 2880x576i@50Hz */
785         { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
786                    3180, 3456, 0, 576, 580, 586, 625, 0,
787                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
788                         DRM_MODE_FLAG_INTERLACE),
789           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
790         /* 26 - 2880x576i@50Hz */
791         { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
792                    3180, 3456, 0, 576, 580, 586, 625, 0,
793                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
794                         DRM_MODE_FLAG_INTERLACE),
795           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
796         /* 27 - 2880x288@50Hz */
797         { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
798                    3180, 3456, 0, 288, 290, 293, 312, 0,
799                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
801         /* 28 - 2880x288@50Hz */
802         { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
803                    3180, 3456, 0, 288, 290, 293, 312, 0,
804                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
805           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
806         /* 29 - 1440x576@50Hz */
807         { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
808                    1592, 1728, 0, 576, 581, 586, 625, 0,
809                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811         /* 30 - 1440x576@50Hz */
812         { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
813                    1592, 1728, 0, 576, 581, 586, 625, 0,
814                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816         /* 31 - 1920x1080@50Hz */
817         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
818                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
819                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821         /* 32 - 1920x1080@24Hz */
822         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
823                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
824                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
825           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826         /* 33 - 1920x1080@25Hz */
827         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
828                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
829                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
830           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
831         /* 34 - 1920x1080@30Hz */
832         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
833                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
834                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
835           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
836         /* 35 - 2880x480@60Hz */
837         { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
838                    3192, 3432, 0, 480, 489, 495, 525, 0,
839                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
840           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841         /* 36 - 2880x480@60Hz */
842         { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
843                    3192, 3432, 0, 480, 489, 495, 525, 0,
844                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
845           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
846         /* 37 - 2880x576@50Hz */
847         { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
848                    3184, 3456, 0, 576, 581, 586, 625, 0,
849                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
850           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
851         /* 38 - 2880x576@50Hz */
852         { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
853                    3184, 3456, 0, 576, 581, 586, 625, 0,
854                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
855           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
856         /* 39 - 1920x1080i@50Hz */
857         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
858                    2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
859                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
860                         DRM_MODE_FLAG_INTERLACE),
861           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862         /* 40 - 1920x1080i@100Hz */
863         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
864                    2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
865                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
866                         DRM_MODE_FLAG_INTERLACE),
867           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868         /* 41 - 1280x720@100Hz */
869         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
870                    1760, 1980, 0, 720, 725, 730, 750, 0,
871                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
872           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873         /* 42 - 720x576@100Hz */
874         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
875                    796, 864, 0, 576, 581, 586, 625, 0,
876                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878         /* 43 - 720x576@100Hz */
879         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
880                    796, 864, 0, 576, 581, 586, 625, 0,
881                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883         /* 44 - 720(1440)x576i@100Hz */
884         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
885                    795, 864, 0, 576, 580, 586, 625, 0,
886                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
887                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
888           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
889         /* 45 - 720(1440)x576i@100Hz */
890         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
891                    795, 864, 0, 576, 580, 586, 625, 0,
892                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
893                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
894           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895         /* 46 - 1920x1080i@120Hz */
896         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
897                    2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
898                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
899                         DRM_MODE_FLAG_INTERLACE),
900           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901         /* 47 - 1280x720@120Hz */
902         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
903                    1430, 1650, 0, 720, 725, 730, 750, 0,
904                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906         /* 48 - 720x480@120Hz */
907         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
908                    798, 858, 0, 480, 489, 495, 525, 0,
909                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
910           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
911         /* 49 - 720x480@120Hz */
912         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
913                    798, 858, 0, 480, 489, 495, 525, 0,
914                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
915           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
916         /* 50 - 720(1440)x480i@120Hz */
917         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
918                    801, 858, 0, 480, 488, 494, 525, 0,
919                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
920                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
921           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
922         /* 51 - 720(1440)x480i@120Hz */
923         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
924                    801, 858, 0, 480, 488, 494, 525, 0,
925                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
926                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
927           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928         /* 52 - 720x576@200Hz */
929         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
930                    796, 864, 0, 576, 581, 586, 625, 0,
931                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
932           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
933         /* 53 - 720x576@200Hz */
934         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
935                    796, 864, 0, 576, 581, 586, 625, 0,
936                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
937           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
938         /* 54 - 720(1440)x576i@200Hz */
939         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
940                    795, 864, 0, 576, 580, 586, 625, 0,
941                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
942                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
943           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
944         /* 55 - 720(1440)x576i@200Hz */
945         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946                    795, 864, 0, 576, 580, 586, 625, 0,
947                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
948                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
949           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950         /* 56 - 720x480@240Hz */
951         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
952                    798, 858, 0, 480, 489, 495, 525, 0,
953                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
954           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
955         /* 57 - 720x480@240Hz */
956         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
957                    798, 858, 0, 480, 489, 495, 525, 0,
958                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
959           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960         /* 58 - 720(1440)x480i@240Hz */
961         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
962                    801, 858, 0, 480, 488, 494, 525, 0,
963                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
964                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
965           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
966         /* 59 - 720(1440)x480i@240Hz */
967         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
968                    801, 858, 0, 480, 488, 494, 525, 0,
969                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
970                         DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
971           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972         /* 60 - 1280x720@24Hz */
973         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
974                    3080, 3300, 0, 720, 725, 730, 750, 0,
975                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
976           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977         /* 61 - 1280x720@25Hz */
978         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
979                    3740, 3960, 0, 720, 725, 730, 750, 0,
980                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
981           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982         /* 62 - 1280x720@30Hz */
983         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
984                    3080, 3300, 0, 720, 725, 730, 750, 0,
985                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
986           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
987         /* 63 - 1920x1080@120Hz */
988         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
989                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
990                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
991          .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992         /* 64 - 1920x1080@100Hz */
993         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
994                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
995                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
996          .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
997 };
998 
999 /*
1000  * HDMI 1.4 4k modes. Index using the VIC.
1001  */
1002 static const struct drm_display_mode edid_4k_modes[] = {
1003         /* 0 - dummy, VICs start at 1 */
1004         { },
1005         /* 1 - 3840x2160@30Hz */
1006         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1007                    3840, 4016, 4104, 4400, 0,
1008                    2160, 2168, 2178, 2250, 0,
1009                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1010           .vrefresh = 30, },
1011         /* 2 - 3840x2160@25Hz */
1012         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1013                    3840, 4896, 4984, 5280, 0,
1014                    2160, 2168, 2178, 2250, 0,
1015                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1016           .vrefresh = 25, },
1017         /* 3 - 3840x2160@24Hz */
1018         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1019                    3840, 5116, 5204, 5500, 0,
1020                    2160, 2168, 2178, 2250, 0,
1021                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1022           .vrefresh = 24, },
1023         /* 4 - 4096x2160@24Hz (SMPTE) */
1024         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1025                    4096, 5116, 5204, 5500, 0,
1026                    2160, 2168, 2178, 2250, 0,
1027                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028           .vrefresh = 24, },
1029 };
1030 
1031 /*** DDC fetch and block validation ***/
1032 
1033 static const u8 edid_header[] = {
1034         0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1035 };
1036 
1037 /**
1038  * drm_edid_header_is_valid - sanity check the header of the base EDID block
1039  * @raw_edid: pointer to raw base EDID block
1040  *
1041  * Sanity check the header of the base EDID block.
1042  *
1043  * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1044  */
1045 int drm_edid_header_is_valid(const u8 *raw_edid)
1046 {
1047         int i, score = 0;
1048 
1049         for (i = 0; i < sizeof(edid_header); i++)
1050                 if (raw_edid[i] == edid_header[i])
1051                         score++;
1052 
1053         return score;
1054 }
1055 EXPORT_SYMBOL(drm_edid_header_is_valid);
1056 
1057 static int edid_fixup __read_mostly = 6;
1058 module_param_named(edid_fixup, edid_fixup, int, 0400);
1059 MODULE_PARM_DESC(edid_fixup,
1060                  "Minimum number of valid EDID header bytes (0-8, default 6)");
1061 
1062 static void drm_get_displayid(struct drm_connector *connector,
1063                               struct edid *edid);
1064 
1065 static int drm_edid_block_checksum(const u8 *raw_edid)
1066 {
1067         int i;
1068         u8 csum = 0;
1069         for (i = 0; i < EDID_LENGTH; i++)
1070                 csum += raw_edid[i];
1071 
1072         return csum;
1073 }
1074 
1075 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1076 {
1077         if (memchr_inv(in_edid, 0, length))
1078                 return false;
1079 
1080         return true;
1081 }
1082 
1083 /**
1084  * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1085  * @raw_edid: pointer to raw EDID block
1086  * @block: type of block to validate (0 for base, extension otherwise)
1087  * @print_bad_edid: if true, dump bad EDID blocks to the console
1088  * @edid_corrupt: if true, the header or checksum is invalid
1089  *
1090  * Validate a base or extension EDID block and optionally dump bad blocks to
1091  * the console.
1092  *
1093  * Return: True if the block is valid, false otherwise.
1094  */
1095 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1096                           bool *edid_corrupt)
1097 {
1098         u8 csum;
1099         struct edid *edid = (struct edid *)raw_edid;
1100 
1101         if (WARN_ON(!raw_edid))
1102                 return false;
1103 
1104         if (edid_fixup > 8 || edid_fixup < 0)
1105                 edid_fixup = 6;
1106 
1107         if (block == 0) {
1108                 int score = drm_edid_header_is_valid(raw_edid);
1109                 if (score == 8) {
1110                         if (edid_corrupt)
1111                                 *edid_corrupt = false;
1112                 } else if (score >= edid_fixup) {
1113                         /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1114                          * The corrupt flag needs to be set here otherwise, the
1115                          * fix-up code here will correct the problem, the
1116                          * checksum is correct and the test fails
1117                          */
1118                         if (edid_corrupt)
1119                                 *edid_corrupt = true;
1120                         DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1121                         memcpy(raw_edid, edid_header, sizeof(edid_header));
1122                 } else {
1123                         if (edid_corrupt)
1124                                 *edid_corrupt = true;
1125                         goto bad;
1126                 }
1127         }
1128 
1129         csum = drm_edid_block_checksum(raw_edid);
1130         if (csum) {
1131                 if (print_bad_edid) {
1132                         DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1133                 }
1134 
1135                 if (edid_corrupt)
1136                         *edid_corrupt = true;
1137 
1138                 /* allow CEA to slide through, switches mangle this */
1139                 if (raw_edid[0] != 0x02)
1140                         goto bad;
1141         }
1142 
1143         /* per-block-type checks */
1144         switch (raw_edid[0]) {
1145         case 0: /* base */
1146                 if (edid->version != 1) {
1147                         DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1148                         goto bad;
1149                 }
1150 
1151                 if (edid->revision > 4)
1152                         DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1153                 break;
1154 
1155         default:
1156                 break;
1157         }
1158 
1159         return true;
1160 
1161 bad:
1162         if (print_bad_edid) {
1163                 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1164                         printk(KERN_ERR "EDID block is all zeroes\n");
1165                 } else {
1166                         printk(KERN_ERR "Raw EDID:\n");
1167                         print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1168                                raw_edid, EDID_LENGTH, false);
1169                 }
1170         }
1171         return false;
1172 }
1173 EXPORT_SYMBOL(drm_edid_block_valid);
1174 
1175 /**
1176  * drm_edid_is_valid - sanity check EDID data
1177  * @edid: EDID data
1178  *
1179  * Sanity-check an entire EDID record (including extensions)
1180  *
1181  * Return: True if the EDID data is valid, false otherwise.
1182  */
1183 bool drm_edid_is_valid(struct edid *edid)
1184 {
1185         int i;
1186         u8 *raw = (u8 *)edid;
1187 
1188         if (!edid)
1189                 return false;
1190 
1191         for (i = 0; i <= edid->extensions; i++)
1192                 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1193                         return false;
1194 
1195         return true;
1196 }
1197 EXPORT_SYMBOL(drm_edid_is_valid);
1198 
1199 #define DDC_SEGMENT_ADDR 0x30
1200 /**
1201  * drm_do_probe_ddc_edid() - get EDID information via I2C
1202  * @data: I2C device adapter
1203  * @buf: EDID data buffer to be filled
1204  * @block: 128 byte EDID block to start fetching from
1205  * @len: EDID data buffer length to fetch
1206  *
1207  * Try to fetch EDID information by calling I2C driver functions.
1208  *
1209  * Return: 0 on success or -1 on failure.
1210  */
1211 static int
1212 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1213 {
1214         struct i2c_adapter *adapter = data;
1215         unsigned char start = block * EDID_LENGTH;
1216         unsigned char segment = block >> 1;
1217         unsigned char xfers = segment ? 3 : 2;
1218         int ret, retries = 5;
1219 
1220         /*
1221          * The core I2C driver will automatically retry the transfer if the
1222          * adapter reports EAGAIN. However, we find that bit-banging transfers
1223          * are susceptible to errors under a heavily loaded machine and
1224          * generate spurious NAKs and timeouts. Retrying the transfer
1225          * of the individual block a few times seems to overcome this.
1226          */
1227         do {
1228                 struct i2c_msg msgs[] = {
1229                         {
1230                                 .addr   = DDC_SEGMENT_ADDR,
1231                                 .flags  = 0,
1232                                 .len    = 1,
1233                                 .buf    = &segment,
1234                         }, {
1235                                 .addr   = DDC_ADDR,
1236                                 .flags  = 0,
1237                                 .len    = 1,
1238                                 .buf    = &start,
1239                         }, {
1240                                 .addr   = DDC_ADDR,
1241                                 .flags  = I2C_M_RD,
1242                                 .len    = len,
1243                                 .buf    = buf,
1244                         }
1245                 };
1246 
1247                 /*
1248                  * Avoid sending the segment addr to not upset non-compliant
1249                  * DDC monitors.
1250                  */
1251                 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1252 
1253                 if (ret == -ENXIO) {
1254                         DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1255                                         adapter->name);
1256                         break;
1257                 }
1258         } while (ret != xfers && --retries);
1259 
1260         return ret == xfers ? 0 : -1;
1261 }
1262 
1263 static void connector_bad_edid(struct drm_connector *connector,
1264                                u8 *edid, int num_blocks)
1265 {
1266         int i;
1267 
1268         if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1269                 return;
1270 
1271         dev_warn(connector->dev->dev,
1272                  "%s: EDID is invalid:\n",
1273                  connector->name);
1274         for (i = 0; i < num_blocks; i++) {
1275                 u8 *block = edid + i * EDID_LENGTH;
1276                 char prefix[20];
1277 
1278                 if (drm_edid_is_zero(block, EDID_LENGTH))
1279                         sprintf(prefix, "\t[%02x] ZERO ", i);
1280                 else if (!drm_edid_block_valid(block, i, false, NULL))
1281                         sprintf(prefix, "\t[%02x] BAD  ", i);
1282                 else
1283                         sprintf(prefix, "\t[%02x] GOOD ", i);
1284 
1285                 print_hex_dump(KERN_WARNING,
1286                                prefix, DUMP_PREFIX_NONE, 16, 1,
1287                                block, EDID_LENGTH, false);
1288         }
1289 }
1290 
1291 /**
1292  * drm_do_get_edid - get EDID data using a custom EDID block read function
1293  * @connector: connector we're probing
1294  * @get_edid_block: EDID block read function
1295  * @data: private data passed to the block read function
1296  *
1297  * When the I2C adapter connected to the DDC bus is hidden behind a device that
1298  * exposes a different interface to read EDID blocks this function can be used
1299  * to get EDID data using a custom block read function.
1300  *
1301  * As in the general case the DDC bus is accessible by the kernel at the I2C
1302  * level, drivers must make all reasonable efforts to expose it as an I2C
1303  * adapter and use drm_get_edid() instead of abusing this function.
1304  *
1305  * Return: Pointer to valid EDID or NULL if we couldn't find any.
1306  */
1307 struct edid *drm_do_get_edid(struct drm_connector *connector,
1308         int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1309                               size_t len),
1310         void *data)
1311 {
1312         int i, j = 0, valid_extensions = 0;
1313         u8 *edid, *new;
1314 
1315         if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1316                 return NULL;
1317 
1318         /* base block fetch */
1319         for (i = 0; i < 4; i++) {
1320                 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1321                         goto out;
1322                 if (drm_edid_block_valid(edid, 0, false,
1323                                          &connector->edid_corrupt))
1324                         break;
1325                 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1326                         connector->null_edid_counter++;
1327                         goto carp;
1328                 }
1329         }
1330         if (i == 4)
1331                 goto carp;
1332 
1333         /* if there's no extensions, we're done */
1334         valid_extensions = edid[0x7e];
1335         if (valid_extensions == 0)
1336                 return (struct edid *)edid;
1337 
1338         new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1339         if (!new)
1340                 goto out;
1341         edid = new;
1342 
1343         for (j = 1; j <= edid[0x7e]; j++) {
1344                 u8 *block = edid + j * EDID_LENGTH;
1345 
1346                 for (i = 0; i < 4; i++) {
1347                         if (get_edid_block(data, block, j, EDID_LENGTH))
1348                                 goto out;
1349                         if (drm_edid_block_valid(block, j, false, NULL))
1350                                 break;
1351                 }
1352 
1353                 if (i == 4)
1354                         valid_extensions--;
1355         }
1356 
1357         if (valid_extensions != edid[0x7e]) {
1358                 u8 *base;
1359 
1360                 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1361 
1362                 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1363                 edid[0x7e] = valid_extensions;
1364 
1365                 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1366                 if (!new)
1367                         goto out;
1368 
1369                 base = new;
1370                 for (i = 0; i <= edid[0x7e]; i++) {
1371                         u8 *block = edid + i * EDID_LENGTH;
1372 
1373                         if (!drm_edid_block_valid(block, i, false, NULL))
1374                                 continue;
1375 
1376                         memcpy(base, block, EDID_LENGTH);
1377                         base += EDID_LENGTH;
1378                 }
1379 
1380                 kfree(edid);
1381                 edid = new;
1382         }
1383 
1384         return (struct edid *)edid;
1385 
1386 carp:
1387         connector_bad_edid(connector, edid, 1);
1388 out:
1389         kfree(edid);
1390         return NULL;
1391 }
1392 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1393 
1394 /**
1395  * drm_probe_ddc() - probe DDC presence
1396  * @adapter: I2C adapter to probe
1397  *
1398  * Return: True on success, false on failure.
1399  */
1400 bool
1401 drm_probe_ddc(struct i2c_adapter *adapter)
1402 {
1403         unsigned char out;
1404 
1405         return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1406 }
1407 EXPORT_SYMBOL(drm_probe_ddc);
1408 
1409 /**
1410  * drm_get_edid - get EDID data, if available
1411  * @connector: connector we're probing
1412  * @adapter: I2C adapter to use for DDC
1413  *
1414  * Poke the given I2C channel to grab EDID data if possible.  If found,
1415  * attach it to the connector.
1416  *
1417  * Return: Pointer to valid EDID or NULL if we couldn't find any.
1418  */
1419 struct edid *drm_get_edid(struct drm_connector *connector,
1420                           struct i2c_adapter *adapter)
1421 {
1422         struct edid *edid;
1423 
1424         if (!drm_probe_ddc(adapter))
1425                 return NULL;
1426 
1427         edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1428         if (edid)
1429                 drm_get_displayid(connector, edid);
1430         return edid;
1431 }
1432 EXPORT_SYMBOL(drm_get_edid);
1433 
1434 /**
1435  * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1436  * @connector: connector we're probing
1437  * @adapter: I2C adapter to use for DDC
1438  *
1439  * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1440  * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1441  * switch DDC to the GPU which is retrieving EDID.
1442  *
1443  * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1444  */
1445 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1446                                      struct i2c_adapter *adapter)
1447 {
1448         struct pci_dev *pdev = connector->dev->pdev;
1449         struct edid *edid;
1450 
1451         vga_switcheroo_lock_ddc(pdev);
1452         edid = drm_get_edid(connector, adapter);
1453         vga_switcheroo_unlock_ddc(pdev);
1454 
1455         return edid;
1456 }
1457 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1458 
1459 /**
1460  * drm_edid_duplicate - duplicate an EDID and the extensions
1461  * @edid: EDID to duplicate
1462  *
1463  * Return: Pointer to duplicated EDID or NULL on allocation failure.
1464  */
1465 struct edid *drm_edid_duplicate(const struct edid *edid)
1466 {
1467         return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1468 }
1469 EXPORT_SYMBOL(drm_edid_duplicate);
1470 
1471 /*** EDID parsing ***/
1472 
1473 /**
1474  * edid_vendor - match a string against EDID's obfuscated vendor field
1475  * @edid: EDID to match
1476  * @vendor: vendor string
1477  *
1478  * Returns true if @vendor is in @edid, false otherwise
1479  */
1480 static bool edid_vendor(struct edid *edid, char *vendor)
1481 {
1482         char edid_vendor[3];
1483 
1484         edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1485         edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1486                           ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1487         edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1488 
1489         return !strncmp(edid_vendor, vendor, 3);
1490 }
1491 
1492 /**
1493  * edid_get_quirks - return quirk flags for a given EDID
1494  * @edid: EDID to process
1495  *
1496  * This tells subsequent routines what fixes they need to apply.
1497  */
1498 static u32 edid_get_quirks(struct edid *edid)
1499 {
1500         struct edid_quirk *quirk;
1501         int i;
1502 
1503         for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1504                 quirk = &edid_quirk_list[i];
1505 
1506                 if (edid_vendor(edid, quirk->vendor) &&
1507                     (EDID_PRODUCT_ID(edid) == quirk->product_id))
1508                         return quirk->quirks;
1509         }
1510 
1511         return 0;
1512 }
1513 
1514 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1515 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1516 
1517 /**
1518  * edid_fixup_preferred - set preferred modes based on quirk list
1519  * @connector: has mode list to fix up
1520  * @quirks: quirks list
1521  *
1522  * Walk the mode list for @connector, clearing the preferred status
1523  * on existing modes and setting it anew for the right mode ala @quirks.
1524  */
1525 static void edid_fixup_preferred(struct drm_connector *connector,
1526                                  u32 quirks)
1527 {
1528         struct drm_display_mode *t, *cur_mode, *preferred_mode;
1529         int target_refresh = 0;
1530         int cur_vrefresh, preferred_vrefresh;
1531 
1532         if (list_empty(&connector->probed_modes))
1533                 return;
1534 
1535         if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1536                 target_refresh = 60;
1537         if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1538                 target_refresh = 75;
1539 
1540         preferred_mode = list_first_entry(&connector->probed_modes,
1541                                           struct drm_display_mode, head);
1542 
1543         list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1544                 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1545 
1546                 if (cur_mode == preferred_mode)
1547                         continue;
1548 
1549                 /* Largest mode is preferred */
1550                 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1551                         preferred_mode = cur_mode;
1552 
1553                 cur_vrefresh = cur_mode->vrefresh ?
1554                         cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1555                 preferred_vrefresh = preferred_mode->vrefresh ?
1556                         preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1557                 /* At a given size, try to get closest to target refresh */
1558                 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1559                     MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1560                     MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1561                         preferred_mode = cur_mode;
1562                 }
1563         }
1564 
1565         preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1566 }
1567 
1568 static bool
1569 mode_is_rb(const struct drm_display_mode *mode)
1570 {
1571         return (mode->htotal - mode->hdisplay == 160) &&
1572                (mode->hsync_end - mode->hdisplay == 80) &&
1573                (mode->hsync_end - mode->hsync_start == 32) &&
1574                (mode->vsync_start - mode->vdisplay == 3);
1575 }
1576 
1577 /*
1578  * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1579  * @dev: Device to duplicate against
1580  * @hsize: Mode width
1581  * @vsize: Mode height
1582  * @fresh: Mode refresh rate
1583  * @rb: Mode reduced-blanking-ness
1584  *
1585  * Walk the DMT mode list looking for a match for the given parameters.
1586  *
1587  * Return: A newly allocated copy of the mode, or NULL if not found.
1588  */
1589 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1590                                            int hsize, int vsize, int fresh,
1591                                            bool rb)
1592 {
1593         int i;
1594 
1595         for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1596                 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1597                 if (hsize != ptr->hdisplay)
1598                         continue;
1599                 if (vsize != ptr->vdisplay)
1600                         continue;
1601                 if (fresh != drm_mode_vrefresh(ptr))
1602                         continue;
1603                 if (rb != mode_is_rb(ptr))
1604                         continue;
1605 
1606                 return drm_mode_duplicate(dev, ptr);
1607         }
1608 
1609         return NULL;
1610 }
1611 EXPORT_SYMBOL(drm_mode_find_dmt);
1612 
1613 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1614 
1615 static void
1616 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1617 {
1618         int i, n = 0;
1619         u8 d = ext[0x02];
1620         u8 *det_base = ext + d;
1621 
1622         n = (127 - d) / 18;
1623         for (i = 0; i < n; i++)
1624                 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1625 }
1626 
1627 static void
1628 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1629 {
1630         unsigned int i, n = min((int)ext[0x02], 6);
1631         u8 *det_base = ext + 5;
1632 
1633         if (ext[0x01] != 1)
1634                 return; /* unknown version */
1635 
1636         for (i = 0; i < n; i++)
1637                 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1638 }
1639 
1640 static void
1641 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1642 {
1643         int i;
1644         struct edid *edid = (struct edid *)raw_edid;
1645 
1646         if (edid == NULL)
1647                 return;
1648 
1649         for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1650                 cb(&(edid->detailed_timings[i]), closure);
1651 
1652         for (i = 1; i <= raw_edid[0x7e]; i++) {
1653                 u8 *ext = raw_edid + (i * EDID_LENGTH);
1654                 switch (*ext) {
1655                 case CEA_EXT:
1656                         cea_for_each_detailed_block(ext, cb, closure);
1657                         break;
1658                 case VTB_EXT:
1659                         vtb_for_each_detailed_block(ext, cb, closure);
1660                         break;
1661                 default:
1662                         break;
1663                 }
1664         }
1665 }
1666 
1667 static void
1668 is_rb(struct detailed_timing *t, void *data)
1669 {
1670         u8 *r = (u8 *)t;
1671         if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1672                 if (r[15] & 0x10)
1673                         *(bool *)data = true;
1674 }
1675 
1676 /* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
1677 static bool
1678 drm_monitor_supports_rb(struct edid *edid)
1679 {
1680         if (edid->revision >= 4) {
1681                 bool ret = false;
1682                 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1683                 return ret;
1684         }
1685 
1686         return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1687 }
1688 
1689 static void
1690 find_gtf2(struct detailed_timing *t, void *data)
1691 {
1692         u8 *r = (u8 *)t;
1693         if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1694                 *(u8 **)data = r;
1695 }
1696 
1697 /* Secondary GTF curve kicks in above some break frequency */
1698 static int
1699 drm_gtf2_hbreak(struct edid *edid)
1700 {
1701         u8 *r = NULL;
1702         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1703         return r ? (r[12] * 2) : 0;
1704 }
1705 
1706 static int
1707 drm_gtf2_2c(struct edid *edid)
1708 {
1709         u8 *r = NULL;
1710         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1711         return r ? r[13] : 0;
1712 }
1713 
1714 static int
1715 drm_gtf2_m(struct edid *edid)
1716 {
1717         u8 *r = NULL;
1718         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1719         return r ? (r[15] << 8) + r[14] : 0;
1720 }
1721 
1722 static int
1723 drm_gtf2_k(struct edid *edid)
1724 {
1725         u8 *r = NULL;
1726         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1727         return r ? r[16] : 0;
1728 }
1729 
1730 static int
1731 drm_gtf2_2j(struct edid *edid)
1732 {
1733         u8 *r = NULL;
1734         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1735         return r ? r[17] : 0;
1736 }
1737 
1738 /**
1739  * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1740  * @edid: EDID block to scan
1741  */
1742 static int standard_timing_level(struct edid *edid)
1743 {
1744         if (edid->revision >= 2) {
1745                 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1746                         return LEVEL_CVT;
1747                 if (drm_gtf2_hbreak(edid))
1748                         return LEVEL_GTF2;
1749                 return LEVEL_GTF;
1750         }
1751         return LEVEL_DMT;
1752 }
1753 
1754 /*
1755  * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
1756  * monitors fill with ascii space (0x20) instead.
1757  */
1758 static int
1759 bad_std_timing(u8 a, u8 b)
1760 {
1761         return (a == 0x00 && b == 0x00) ||
1762                (a == 0x01 && b == 0x01) ||
1763                (a == 0x20 && b == 0x20);
1764 }
1765 
1766 /**
1767  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1768  * @connector: connector of for the EDID block
1769  * @edid: EDID block to scan
1770  * @t: standard timing params
1771  *
1772  * Take the standard timing params (in this case width, aspect, and refresh)
1773  * and convert them into a real mode using CVT/GTF/DMT.
1774  */
1775 static struct drm_display_mode *
1776 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1777              struct std_timing *t)
1778 {
1779         struct drm_device *dev = connector->dev;
1780         struct drm_display_mode *m, *mode = NULL;
1781         int hsize, vsize;
1782         int vrefresh_rate;
1783         unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1784                 >> EDID_TIMING_ASPECT_SHIFT;
1785         unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1786                 >> EDID_TIMING_VFREQ_SHIFT;
1787         int timing_level = standard_timing_level(edid);
1788 
1789         if (bad_std_timing(t->hsize, t->vfreq_aspect))
1790                 return NULL;
1791 
1792         /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1793         hsize = t->hsize * 8 + 248;
1794         /* vrefresh_rate = vfreq + 60 */
1795         vrefresh_rate = vfreq + 60;
1796         /* the vdisplay is calculated based on the aspect ratio */
1797         if (aspect_ratio == 0) {
1798                 if (edid->revision < 3)
1799                         vsize = hsize;
1800                 else
1801                         vsize = (hsize * 10) / 16;
1802         } else if (aspect_ratio == 1)
1803                 vsize = (hsize * 3) / 4;
1804         else if (aspect_ratio == 2)
1805                 vsize = (hsize * 4) / 5;
1806         else
1807                 vsize = (hsize * 9) / 16;
1808 
1809         /* HDTV hack, part 1 */
1810         if (vrefresh_rate == 60 &&
1811             ((hsize == 1360 && vsize == 765) ||
1812              (hsize == 1368 && vsize == 769))) {
1813                 hsize = 1366;
1814                 vsize = 768;
1815         }
1816 
1817         /*
1818          * If this connector already has a mode for this size and refresh
1819          * rate (because it came from detailed or CVT info), use that
1820          * instead.  This way we don't have to guess at interlace or
1821          * reduced blanking.
1822          */
1823         list_for_each_entry(m, &connector->probed_modes, head)
1824                 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1825                     drm_mode_vrefresh(m) == vrefresh_rate)
1826                         return NULL;
1827 
1828         /* HDTV hack, part 2 */
1829         if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1830                 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1831                                     false);
1832                 mode->hdisplay = 1366;
1833                 mode->hsync_start = mode->hsync_start - 1;
1834                 mode->hsync_end = mode->hsync_end - 1;
1835                 return mode;
1836         }
1837 
1838         /* check whether it can be found in default mode table */
1839         if (drm_monitor_supports_rb(edid)) {
1840                 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1841                                          true);
1842                 if (mode)
1843                         return mode;
1844         }
1845         mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1846         if (mode)
1847                 return mode;
1848 
1849         /* okay, generate it */
1850         switch (timing_level) {
1851         case LEVEL_DMT:
1852                 break;
1853         case LEVEL_GTF:
1854                 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1855                 break;
1856         case LEVEL_GTF2:
1857                 /*
1858                  * This is potentially wrong if there's ever a monitor with
1859                  * more than one ranges section, each claiming a different
1860                  * secondary GTF curve.  Please don't do that.
1861                  */
1862                 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1863                 if (!mode)
1864                         return NULL;
1865                 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1866                         drm_mode_destroy(dev, mode);
1867                         mode = drm_gtf_mode_complex(dev, hsize, vsize,
1868                                                     vrefresh_rate, 0, 0,
1869                                                     drm_gtf2_m(edid),
1870                                                     drm_gtf2_2c(edid),
1871                                                     drm_gtf2_k(edid),
1872                                                     drm_gtf2_2j(edid));
1873                 }
1874                 break;
1875         case LEVEL_CVT:
1876                 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1877                                     false);
1878                 break;
1879         }
1880         return mode;
1881 }
1882 
1883 /*
1884  * EDID is delightfully ambiguous about how interlaced modes are to be
1885  * encoded.  Our internal representation is of frame height, but some
1886  * HDTV detailed timings are encoded as field height.
1887  *
1888  * The format list here is from CEA, in frame size.  Technically we
1889  * should be checking refresh rate too.  Whatever.
1890  */
1891 static void
1892 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1893                             struct detailed_pixel_timing *pt)
1894 {
1895         int i;
1896         static const struct {
1897                 int w, h;
1898         } cea_interlaced[] = {
1899                 { 1920, 1080 },
1900                 {  720,  480 },
1901                 { 1440,  480 },
1902                 { 2880,  480 },
1903                 {  720,  576 },
1904                 { 1440,  576 },
1905                 { 2880,  576 },
1906         };
1907 
1908         if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1909                 return;
1910 
1911         for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1912                 if ((mode->hdisplay == cea_interlaced[i].w) &&
1913                     (mode->vdisplay == cea_interlaced[i].h / 2)) {
1914                         mode->vdisplay *= 2;
1915                         mode->vsync_start *= 2;
1916                         mode->vsync_end *= 2;
1917                         mode->vtotal *= 2;
1918                         mode->vtotal |= 1;
1919                 }
1920         }
1921 
1922         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1923 }
1924 
1925 /**
1926  * drm_mode_detailed - create a new mode from an EDID detailed timing section
1927  * @dev: DRM device (needed to create new mode)
1928  * @edid: EDID block
1929  * @timing: EDID detailed timing info
1930  * @quirks: quirks to apply
1931  *
1932  * An EDID detailed timing block contains enough info for us to create and
1933  * return a new struct drm_display_mode.
1934  */
1935 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1936                                                   struct edid *edid,
1937                                                   struct detailed_timing *timing,
1938                                                   u32 quirks)
1939 {
1940         struct drm_display_mode *mode;
1941         struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1942         unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1943         unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1944         unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1945         unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1946         unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1947         unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1948         unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1949         unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1950 
1951         /* ignore tiny modes */
1952         if (hactive < 64 || vactive < 64)
1953                 return NULL;
1954 
1955         if (pt->misc & DRM_EDID_PT_STEREO) {
1956                 DRM_DEBUG_KMS("stereo mode not supported\n");
1957                 return NULL;
1958         }
1959         if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1960                 DRM_DEBUG_KMS("composite sync not supported\n");
1961         }
1962 
1963         /* it is incorrect if hsync/vsync width is zero */
1964         if (!hsync_pulse_width || !vsync_pulse_width) {
1965                 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1966                                 "Wrong Hsync/Vsync pulse width\n");
1967                 return NULL;
1968         }
1969 
1970         if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1971                 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1972                 if (!mode)
1973                         return NULL;
1974 
1975                 goto set_size;
1976         }
1977 
1978         mode = drm_mode_create(dev);
1979         if (!mode)
1980                 return NULL;
1981 
1982         if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1983                 timing->pixel_clock = cpu_to_le16(1088);
1984 
1985         mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1986 
1987         mode->hdisplay = hactive;
1988         mode->hsync_start = mode->hdisplay + hsync_offset;
1989         mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1990         mode->htotal = mode->hdisplay + hblank;
1991 
1992         mode->vdisplay = vactive;
1993         mode->vsync_start = mode->vdisplay + vsync_offset;
1994         mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1995         mode->vtotal = mode->vdisplay + vblank;
1996 
1997         /* Some EDIDs have bogus h/vtotal values */
1998         if (mode->hsync_end > mode->htotal)
1999                 mode->htotal = mode->hsync_end + 1;
2000         if (mode->vsync_end > mode->vtotal)
2001                 mode->vtotal = mode->vsync_end + 1;
2002 
2003         drm_mode_do_interlace_quirk(mode, pt);
2004 
2005         if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2006                 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2007         }
2008 
2009         mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2010                 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2011         mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2012                 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2013 
2014 set_size:
2015         mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2016         mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2017 
2018         if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2019                 mode->width_mm *= 10;
2020                 mode->height_mm *= 10;
2021         }
2022 
2023         if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2024                 mode->width_mm = edid->width_cm * 10;
2025                 mode->height_mm = edid->height_cm * 10;
2026         }
2027 
2028         mode->type = DRM_MODE_TYPE_DRIVER;
2029         mode->vrefresh = drm_mode_vrefresh(mode);
2030         drm_mode_set_name(mode);
2031 
2032         return mode;
2033 }
2034 
2035 static bool
2036 mode_in_hsync_range(const struct drm_display_mode *mode,
2037                     struct edid *edid, u8 *t)
2038 {
2039         int hsync, hmin, hmax;
2040 
2041         hmin = t[7];
2042         if (edid->revision >= 4)
2043             hmin += ((t[4] & 0x04) ? 255 : 0);
2044         hmax = t[8];
2045         if (edid->revision >= 4)
2046             hmax += ((t[4] & 0x08) ? 255 : 0);
2047         hsync = drm_mode_hsync(mode);
2048 
2049         return (hsync <= hmax && hsync >= hmin);
2050 }
2051 
2052 static bool
2053 mode_in_vsync_range(const struct drm_display_mode *mode,
2054                     struct edid *edid, u8 *t)
2055 {
2056         int vsync, vmin, vmax;
2057 
2058         vmin = t[5];
2059         if (edid->revision >= 4)
2060             vmin += ((t[4] & 0x01) ? 255 : 0);
2061         vmax = t[6];
2062         if (edid->revision >= 4)
2063             vmax += ((t[4] & 0x02) ? 255 : 0);
2064         vsync = drm_mode_vrefresh(mode);
2065 
2066         return (vsync <= vmax && vsync >= vmin);
2067 }
2068 
2069 static u32
2070 range_pixel_clock(struct edid *edid, u8 *t)
2071 {
2072         /* unspecified */
2073         if (t[9] == 0 || t[9] == 255)
2074                 return 0;
2075 
2076         /* 1.4 with CVT support gives us real precision, yay */
2077         if (edid->revision >= 4 && t[10] == 0x04)
2078                 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2079 
2080         /* 1.3 is pathetic, so fuzz up a bit */
2081         return t[9] * 10000 + 5001;
2082 }
2083 
2084 static bool
2085 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2086               struct detailed_timing *timing)
2087 {
2088         u32 max_clock;
2089         u8 *t = (u8 *)timing;
2090 
2091         if (!mode_in_hsync_range(mode, edid, t))
2092                 return false;
2093 
2094         if (!mode_in_vsync_range(mode, edid, t))
2095                 return false;
2096 
2097         if ((max_clock = range_pixel_clock(edid, t)))
2098                 if (mode->clock > max_clock)
2099                         return false;
2100 
2101         /* 1.4 max horizontal check */
2102         if (edid->revision >= 4 && t[10] == 0x04)
2103                 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2104                         return false;
2105 
2106         if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2107                 return false;
2108 
2109         return true;
2110 }
2111 
2112 static bool valid_inferred_mode(const struct drm_connector *connector,
2113                                 const struct drm_display_mode *mode)
2114 {
2115         const struct drm_display_mode *m;
2116         bool ok = false;
2117 
2118         list_for_each_entry(m, &connector->probed_modes, head) {
2119                 if (mode->hdisplay == m->hdisplay &&
2120                     mode->vdisplay == m->vdisplay &&
2121                     drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2122                         return false; /* duplicated */
2123                 if (mode->hdisplay <= m->hdisplay &&
2124                     mode->vdisplay <= m->vdisplay)
2125                         ok = true;
2126         }
2127         return ok;
2128 }
2129 
2130 static int
2131 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2132                         struct detailed_timing *timing)
2133 {
2134         int i, modes = 0;
2135         struct drm_display_mode *newmode;
2136         struct drm_device *dev = connector->dev;
2137 
2138         for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2139                 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2140                     valid_inferred_mode(connector, drm_dmt_modes + i)) {
2141                         newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2142                         if (newmode) {
2143                                 drm_mode_probed_add(connector, newmode);
2144                                 modes++;
2145                         }
2146                 }
2147         }
2148 
2149         return modes;
2150 }
2151 
2152 /* fix up 1366x768 mode from 1368x768;
2153  * GFT/CVT can't express 1366 width which isn't dividable by 8
2154  */
2155 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2156 {
2157         if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2158                 mode->hdisplay = 1366;
2159                 mode->hsync_start--;
2160                 mode->hsync_end--;
2161                 drm_mode_set_name(mode);
2162         }
2163 }
2164 
2165 static int
2166 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2167                         struct detailed_timing *timing)
2168 {
2169         int i, modes = 0;
2170         struct drm_display_mode *newmode;
2171         struct drm_device *dev = connector->dev;
2172 
2173         for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2174                 const struct minimode *m = &extra_modes[i];
2175                 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2176                 if (!newmode)
2177                         return modes;
2178 
2179                 fixup_mode_1366x768(newmode);
2180                 if (!mode_in_range(newmode, edid, timing) ||
2181                     !valid_inferred_mode(connector, newmode)) {
2182                         drm_mode_destroy(dev, newmode);
2183                         continue;
2184                 }
2185 
2186                 drm_mode_probed_add(connector, newmode);
2187                 modes++;
2188         }
2189 
2190         return modes;
2191 }
2192 
2193 static int
2194 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2195                         struct detailed_timing *timing)
2196 {
2197         int i, modes = 0;
2198         struct drm_display_mode *newmode;
2199         struct drm_device *dev = connector->dev;
2200         bool rb = drm_monitor_supports_rb(edid);
2201 
2202         for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2203                 const struct minimode *m = &extra_modes[i];
2204                 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2205                 if (!newmode)
2206                         return modes;
2207 
2208                 fixup_mode_1366x768(newmode);
2209                 if (!mode_in_range(newmode, edid, timing) ||
2210                     !valid_inferred_mode(connector, newmode)) {
2211                         drm_mode_destroy(dev, newmode);
2212                         continue;
2213                 }
2214 
2215                 drm_mode_probed_add(connector, newmode);
2216                 modes++;
2217         }
2218 
2219         return modes;
2220 }
2221 
2222 static void
2223 do_inferred_modes(struct detailed_timing *timing, void *c)
2224 {
2225         struct detailed_mode_closure *closure = c;
2226         struct detailed_non_pixel *data = &timing->data.other_data;
2227         struct detailed_data_monitor_range *range = &data->data.range;
2228 
2229         if (data->type != EDID_DETAIL_MONITOR_RANGE)
2230                 return;
2231 
2232         closure->modes += drm_dmt_modes_for_range(closure->connector,
2233                                                   closure->edid,
2234                                                   timing);
2235         
2236         if (!version_greater(closure->edid, 1, 1))
2237                 return; /* GTF not defined yet */
2238 
2239         switch (range->flags) {
2240         case 0x02: /* secondary gtf, XXX could do more */
2241         case 0x00: /* default gtf */
2242                 closure->modes += drm_gtf_modes_for_range(closure->connector,
2243                                                           closure->edid,
2244                                                           timing);
2245                 break;
2246         case 0x04: /* cvt, only in 1.4+ */
2247                 if (!version_greater(closure->edid, 1, 3))
2248                         break;
2249 
2250                 closure->modes += drm_cvt_modes_for_range(closure->connector,
2251                                                           closure->edid,
2252                                                           timing);
2253                 break;
2254         case 0x01: /* just the ranges, no formula */
2255         default:
2256                 break;
2257         }
2258 }
2259 
2260 static int
2261 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2262 {
2263         struct detailed_mode_closure closure = {
2264                 .connector = connector,
2265                 .edid = edid,
2266         };
2267 
2268         if (version_greater(edid, 1, 0))
2269                 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2270                                             &closure);
2271 
2272         return closure.modes;
2273 }
2274 
2275 static int
2276 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2277 {
2278         int i, j, m, modes = 0;
2279         struct drm_display_mode *mode;
2280         u8 *est = ((u8 *)timing) + 6;
2281 
2282         for (i = 0; i < 6; i++) {
2283                 for (j = 7; j >= 0; j--) {
2284                         m = (i * 8) + (7 - j);
2285                         if (m >= ARRAY_SIZE(est3_modes))
2286                                 break;
2287                         if (est[i] & (1 << j)) {
2288                                 mode = drm_mode_find_dmt(connector->dev,
2289                                                          est3_modes[m].w,
2290                                                          est3_modes[m].h,
2291                                                          est3_modes[m].r,
2292                                                          est3_modes[m].rb);
2293                                 if (mode) {
2294                                         drm_mode_probed_add(connector, mode);
2295                                         modes++;
2296                                 }
2297                         }
2298                 }
2299         }
2300 
2301         return modes;
2302 }
2303 
2304 static void
2305 do_established_modes(struct detailed_timing *timing, void *c)
2306 {
2307         struct detailed_mode_closure *closure = c;
2308         struct detailed_non_pixel *data = &timing->data.other_data;
2309 
2310         if (data->type == EDID_DETAIL_EST_TIMINGS)
2311                 closure->modes += drm_est3_modes(closure->connector, timing);
2312 }
2313 
2314 /**
2315  * add_established_modes - get est. modes from EDID and add them
2316  * @connector: connector to add mode(s) to
2317  * @edid: EDID block to scan
2318  *
2319  * Each EDID block contains a bitmap of the supported "established modes" list
2320  * (defined above).  Tease them out and add them to the global modes list.
2321  */
2322 static int
2323 add_established_modes(struct drm_connector *connector, struct edid *edid)
2324 {
2325         struct drm_device *dev = connector->dev;
2326         unsigned long est_bits = edid->established_timings.t1 |
2327                 (edid->established_timings.t2 << 8) |
2328                 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2329         int i, modes = 0;
2330         struct detailed_mode_closure closure = {
2331                 .connector = connector,
2332                 .edid = edid,
2333         };
2334 
2335         for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2336                 if (est_bits & (1<<i)) {
2337                         struct drm_display_mode *newmode;
2338                         newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2339                         if (newmode) {
2340                                 drm_mode_probed_add(connector, newmode);
2341                                 modes++;
2342                         }
2343                 }
2344         }
2345 
2346         if (version_greater(edid, 1, 0))
2347                     drm_for_each_detailed_block((u8 *)edid,
2348                                                 do_established_modes, &closure);
2349 
2350         return modes + closure.modes;
2351 }
2352 
2353 static void
2354 do_standard_modes(struct detailed_timing *timing, void *c)
2355 {
2356         struct detailed_mode_closure *closure = c;
2357         struct detailed_non_pixel *data = &timing->data.other_data;
2358         struct drm_connector *connector = closure->connector;
2359         struct edid *edid = closure->edid;
2360 
2361         if (data->type == EDID_DETAIL_STD_MODES) {
2362                 int i;
2363                 for (i = 0; i < 6; i++) {
2364                         struct std_timing *std;
2365                         struct drm_display_mode *newmode;
2366 
2367                         std = &data->data.timings[i];
2368                         newmode = drm_mode_std(connector, edid, std);
2369                         if (newmode) {
2370                                 drm_mode_probed_add(connector, newmode);
2371                                 closure->modes++;
2372                         }
2373                 }
2374         }
2375 }
2376 
2377 /**
2378  * add_standard_modes - get std. modes from EDID and add them
2379  * @connector: connector to add mode(s) to
2380  * @edid: EDID block to scan
2381  *
2382  * Standard modes can be calculated using the appropriate standard (DMT,
2383  * GTF or CVT. Grab them from @edid and add them to the list.
2384  */
2385 static int
2386 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2387 {
2388         int i, modes = 0;
2389         struct detailed_mode_closure closure = {
2390                 .connector = connector,
2391                 .edid = edid,
2392         };
2393 
2394         for (i = 0; i < EDID_STD_TIMINGS; i++) {
2395                 struct drm_display_mode *newmode;
2396 
2397                 newmode = drm_mode_std(connector, edid,
2398                                        &edid->standard_timings[i]);
2399                 if (newmode) {
2400                         drm_mode_probed_add(connector, newmode);
2401                         modes++;
2402                 }
2403         }
2404 
2405         if (version_greater(edid, 1, 0))
2406                 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2407                                             &closure);
2408 
2409         /* XXX should also look for standard codes in VTB blocks */
2410 
2411         return modes + closure.modes;
2412 }
2413 
2414 static int drm_cvt_modes(struct drm_connector *connector,
2415                          struct detailed_timing *timing)
2416 {
2417         int i, j, modes = 0;
2418         struct drm_display_mode *newmode;
2419         struct drm_device *dev = connector->dev;
2420         struct cvt_timing *cvt;
2421         const int rates[] = { 60, 85, 75, 60, 50 };
2422         const u8 empty[3] = { 0, 0, 0 };
2423 
2424         for (i = 0; i < 4; i++) {
2425                 int uninitialized_var(width), height;
2426                 cvt = &(timing->data.other_data.data.cvt[i]);
2427 
2428                 if (!memcmp(cvt->code, empty, 3))
2429                         continue;
2430 
2431                 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2432                 switch (cvt->code[1] & 0x0c) {
2433                 case 0x00:
2434                         width = height * 4 / 3;
2435                         break;
2436                 case 0x04:
2437                         width = height * 16 / 9;
2438                         break;
2439                 case 0x08:
2440                         width = height * 16 / 10;
2441                         break;
2442                 case 0x0c:
2443                         width = height * 15 / 9;
2444                         break;
2445                 }
2446 
2447                 for (j = 1; j < 5; j++) {
2448                         if (cvt->code[2] & (1 << j)) {
2449                                 newmode = drm_cvt_mode(dev, width, height,
2450                                                        rates[j], j == 0,
2451                                                        false, false);
2452                                 if (newmode) {
2453                                         drm_mode_probed_add(connector, newmode);
2454                                         modes++;
2455                                 }
2456                         }
2457                 }
2458         }
2459 
2460         return modes;
2461 }
2462 
2463 static void
2464 do_cvt_mode(struct detailed_timing *timing, void *c)
2465 {
2466         struct detailed_mode_closure *closure = c;
2467         struct detailed_non_pixel *data = &timing->data.other_data;
2468 
2469         if (data->type == EDID_DETAIL_CVT_3BYTE)
2470                 closure->modes += drm_cvt_modes(closure->connector, timing);
2471 }
2472 
2473 static int
2474 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2475 {       
2476         struct detailed_mode_closure closure = {
2477                 .connector = connector,
2478                 .edid = edid,
2479         };
2480 
2481         if (version_greater(edid, 1, 2))
2482                 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2483 
2484         /* XXX should also look for CVT codes in VTB blocks */
2485 
2486         return closure.modes;
2487 }
2488 
2489 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2490 
2491 static void
2492 do_detailed_mode(struct detailed_timing *timing, void *c)
2493 {
2494         struct detailed_mode_closure *closure = c;
2495         struct drm_display_mode *newmode;
2496 
2497         if (timing->pixel_clock) {
2498                 newmode = drm_mode_detailed(closure->connector->dev,
2499                                             closure->edid, timing,
2500                                             closure->quirks);
2501                 if (!newmode)
2502                         return;
2503 
2504                 if (closure->preferred)
2505                         newmode->type |= DRM_MODE_TYPE_PREFERRED;
2506 
2507                 /*
2508                  * Detailed modes are limited to 10kHz pixel clock resolution,
2509                  * so fix up anything that looks like CEA/HDMI mode, but the clock
2510                  * is just slightly off.
2511                  */
2512                 fixup_detailed_cea_mode_clock(newmode);
2513 
2514                 drm_mode_probed_add(closure->connector, newmode);
2515                 closure->modes++;
2516                 closure->preferred = 0;
2517         }
2518 }
2519 
2520 /*
2521  * add_detailed_modes - Add modes from detailed timings
2522  * @connector: attached connector
2523  * @edid: EDID block to scan
2524  * @quirks: quirks to apply
2525  */
2526 static int
2527 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2528                    u32 quirks)
2529 {
2530         struct detailed_mode_closure closure = {
2531                 .connector = connector,
2532                 .edid = edid,
2533                 .preferred = 1,
2534                 .quirks = quirks,
2535         };
2536 
2537         if (closure.preferred && !version_greater(edid, 1, 3))
2538                 closure.preferred =
2539                     (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2540 
2541         drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2542 
2543         return closure.modes;
2544 }
2545 
2546 #define AUDIO_BLOCK     0x01
2547 #define VIDEO_BLOCK     0x02
2548 #define VENDOR_BLOCK    0x03
2549 #define SPEAKER_BLOCK   0x04
2550 #define VIDEO_CAPABILITY_BLOCK  0x07
2551 #define EDID_BASIC_AUDIO        (1 << 6)
2552 #define EDID_CEA_YCRCB444       (1 << 5)
2553 #define EDID_CEA_YCRCB422       (1 << 4)
2554 #define EDID_CEA_VCDB_QS        (1 << 6)
2555 
2556 /*
2557  * Search EDID for CEA extension block.
2558  */
2559 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2560 {
2561         u8 *edid_ext = NULL;
2562         int i;
2563 
2564         /* No EDID or EDID extensions */
2565         if (edid == NULL || edid->extensions == 0)
2566                 return NULL;
2567 
2568         /* Find CEA extension */
2569         for (i = 0; i < edid->extensions; i++) {
2570                 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2571                 if (edid_ext[0] == ext_id)
2572                         break;
2573         }
2574 
2575         if (i == edid->extensions)
2576                 return NULL;
2577 
2578         return edid_ext;
2579 }
2580 
2581 static u8 *drm_find_cea_extension(struct edid *edid)
2582 {
2583         return drm_find_edid_extension(edid, CEA_EXT);
2584 }
2585 
2586 static u8 *drm_find_displayid_extension(struct edid *edid)
2587 {
2588         return drm_find_edid_extension(edid, DISPLAYID_EXT);
2589 }
2590 
2591 /*
2592  * Calculate the alternate clock for the CEA mode
2593  * (60Hz vs. 59.94Hz etc.)
2594  */
2595 static unsigned int
2596 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2597 {
2598         unsigned int clock = cea_mode->clock;
2599 
2600         if (cea_mode->vrefresh % 6 != 0)
2601                 return clock;
2602 
2603         /*
2604          * edid_cea_modes contains the 59.94Hz
2605          * variant for 240 and 480 line modes,
2606          * and the 60Hz variant otherwise.
2607          */
2608         if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2609                 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2610         else
2611                 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2612 
2613         return clock;
2614 }
2615 
2616 static bool
2617 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2618 {
2619         /*
2620          * For certain VICs the spec allows the vertical
2621          * front porch to vary by one or two lines.
2622          *
2623          * cea_modes[] stores the variant with the shortest
2624          * vertical front porch. We can adjust the mode to
2625          * get the other variants by simply increasing the
2626          * vertical front porch length.
2627          */
2628         BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2629                      edid_cea_modes[9].vtotal != 262 ||
2630                      edid_cea_modes[12].vtotal != 262 ||
2631                      edid_cea_modes[13].vtotal != 262 ||
2632                      edid_cea_modes[23].vtotal != 312 ||
2633                      edid_cea_modes[24].vtotal != 312 ||
2634                      edid_cea_modes[27].vtotal != 312 ||
2635                      edid_cea_modes[28].vtotal != 312);
2636 
2637         if (((vic == 8 || vic == 9 ||
2638               vic == 12 || vic == 13) && mode->vtotal < 263) ||
2639             ((vic == 23 || vic == 24 ||
2640               vic == 27 || vic == 28) && mode->vtotal < 314)) {
2641                 mode->vsync_start++;
2642                 mode->vsync_end++;
2643                 mode->vtotal++;
2644 
2645                 return true;
2646         }
2647 
2648         return false;
2649 }
2650 
2651 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2652                                              unsigned int clock_tolerance)
2653 {
2654         u8 vic;
2655 
2656         if (!to_match->clock)
2657                 return 0;
2658 
2659         for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2660                 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2661                 unsigned int clock1, clock2;
2662 
2663                 /* Check both 60Hz and 59.94Hz */
2664                 clock1 = cea_mode.clock;
2665                 clock2 = cea_mode_alternate_clock(&cea_mode);
2666 
2667                 if (abs(to_match->clock - clock1) > clock_tolerance &&
2668                     abs(to_match->clock - clock2) > clock_tolerance)
2669                         continue;
2670 
2671                 do {
2672                         if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2673                                 return vic;
2674                 } while (cea_mode_alternate_timings(vic, &cea_mode));
2675         }
2676 
2677         return 0;
2678 }
2679 
2680 /**
2681  * drm_match_cea_mode - look for a CEA mode matching given mode
2682  * @to_match: display mode
2683  *
2684  * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2685  * mode.
2686  */
2687 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2688 {
2689         u8 vic;
2690 
2691         if (!to_match->clock)
2692                 return 0;
2693 
2694         for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2695                 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2696                 unsigned int clock1, clock2;
2697 
2698                 /* Check both 60Hz and 59.94Hz */
2699                 clock1 = cea_mode.clock;
2700                 clock2 = cea_mode_alternate_clock(&cea_mode);
2701 
2702                 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2703                     KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2704                         continue;
2705 
2706                 do {
2707                         if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2708                                 return vic;
2709                 } while (cea_mode_alternate_timings(vic, &cea_mode));
2710         }
2711 
2712         return 0;
2713 }
2714 EXPORT_SYMBOL(drm_match_cea_mode);
2715 
2716 static bool drm_valid_cea_vic(u8 vic)
2717 {
2718         return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2719 }
2720 
2721 /**
2722  * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2723  * the input VIC from the CEA mode list
2724  * @video_code: ID given to each of the CEA modes
2725  *
2726  * Returns picture aspect ratio
2727  */
2728 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2729 {
2730         return edid_cea_modes[video_code].picture_aspect_ratio;
2731 }
2732 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2733 
2734 /*
2735  * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2736  * specific block).
2737  *
2738  * It's almost like cea_mode_alternate_clock(), we just need to add an
2739  * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2740  * one.
2741  */
2742 static unsigned int
2743 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2744 {
2745         if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2746                 return hdmi_mode->clock;
2747 
2748         return cea_mode_alternate_clock(hdmi_mode);
2749 }
2750 
2751 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2752                                               unsigned int clock_tolerance)
2753 {
2754         u8 vic;
2755 
2756         if (!to_match->clock)
2757                 return 0;
2758 
2759         for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2760                 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2761                 unsigned int clock1, clock2;
2762 
2763                 /* Make sure to also match alternate clocks */
2764                 clock1 = hdmi_mode->clock;
2765                 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2766 
2767                 if (abs(to_match->clock - clock1) > clock_tolerance &&
2768                     abs(to_match->clock - clock2) > clock_tolerance)
2769                         continue;
2770 
2771                 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2772                         return vic;
2773         }
2774 
2775         return 0;
2776 }
2777 
2778 /*
2779  * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2780  * @to_match: display mode
2781  *
2782  * An HDMI mode is one defined in the HDMI vendor specific block.
2783  *
2784  * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2785  */
2786 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2787 {
2788         u8 vic;
2789 
2790         if (!to_match->clock)
2791                 return 0;
2792 
2793         for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2794                 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2795                 unsigned int clock1, clock2;
2796 
2797                 /* Make sure to also match alternate clocks */
2798                 clock1 = hdmi_mode->clock;
2799                 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2800 
2801                 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2802                      KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2803                     drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2804                         return vic;
2805         }
2806         return 0;
2807 }
2808 
2809 static bool drm_valid_hdmi_vic(u8 vic)
2810 {
2811         return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2812 }
2813 
2814 static int
2815 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2816 {
2817         struct drm_device *dev = connector->dev;
2818         struct drm_display_mode *mode, *tmp;
2819         LIST_HEAD(list);
2820         int modes = 0;
2821 
2822         /* Don't add CEA modes if the CEA extension block is missing */
2823         if (!drm_find_cea_extension(edid))
2824                 return 0;
2825 
2826         /*
2827          * Go through all probed modes and create a new mode
2828          * with the alternate clock for certain CEA modes.
2829          */
2830         list_for_each_entry(mode, &connector->probed_modes, head) {
2831                 const struct drm_display_mode *cea_mode = NULL;
2832                 struct drm_display_mode *newmode;
2833                 u8 vic = drm_match_cea_mode(mode);
2834                 unsigned int clock1, clock2;
2835 
2836                 if (drm_valid_cea_vic(vic)) {
2837                         cea_mode = &edid_cea_modes[vic];
2838                         clock2 = cea_mode_alternate_clock(cea_mode);
2839                 } else {
2840                         vic = drm_match_hdmi_mode(mode);
2841                         if (drm_valid_hdmi_vic(vic)) {
2842                                 cea_mode = &edid_4k_modes[vic];
2843                                 clock2 = hdmi_mode_alternate_clock(cea_mode);
2844                         }
2845                 }
2846 
2847                 if (!cea_mode)
2848                         continue;
2849 
2850                 clock1 = cea_mode->clock;
2851 
2852                 if (clock1 == clock2)
2853                         continue;
2854 
2855                 if (mode->clock != clock1 && mode->clock != clock2)
2856                         continue;
2857 
2858                 newmode = drm_mode_duplicate(dev, cea_mode);
2859                 if (!newmode)
2860                         continue;
2861 
2862                 /* Carry over the stereo flags */
2863                 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2864 
2865                 /*
2866                  * The current mode could be either variant. Make
2867                  * sure to pick the "other" clock for the new mode.
2868                  */
2869                 if (mode->clock != clock1)
2870                         newmode->clock = clock1;
2871                 else
2872                         newmode->clock = clock2;
2873 
2874                 list_add_tail(&newmode->head, &list);
2875         }
2876 
2877         list_for_each_entry_safe(mode, tmp, &list, head) {
2878                 list_del(&mode->head);
2879                 drm_mode_probed_add(connector, mode);
2880                 modes++;
2881         }
2882 
2883         return modes;
2884 }
2885 
2886 static struct drm_display_mode *
2887 drm_display_mode_from_vic_index(struct drm_connector *connector,
2888                                 const u8 *video_db, u8 video_len,
2889                                 u8 video_index)
2890 {
2891         struct drm_device *dev = connector->dev;
2892         struct drm_display_mode *newmode;
2893         u8 vic;
2894 
2895         if (video_db == NULL || video_index >= video_len)
2896                 return NULL;
2897 
2898         /* CEA modes are numbered 1..127 */
2899         vic = (video_db[video_index] & 127);
2900         if (!drm_valid_cea_vic(vic))
2901                 return NULL;
2902 
2903         newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2904         if (!newmode)
2905                 return NULL;
2906 
2907         newmode->vrefresh = 0;
2908 
2909         return newmode;
2910 }
2911 
2912 static int
2913 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2914 {
2915         int i, modes = 0;
2916 
2917         for (i = 0; i < len; i++) {
2918                 struct drm_display_mode *mode;
2919                 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2920                 if (mode) {
2921                         drm_mode_probed_add(connector, mode);
2922                         modes++;
2923                 }
2924         }
2925 
2926         return modes;
2927 }
2928 
2929 struct stereo_mandatory_mode {
2930         int width, height, vrefresh;
2931         unsigned int flags;
2932 };
2933 
2934 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2935         { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2936         { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2937         { 1920, 1080, 50,
2938           DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2939         { 1920, 1080, 60,
2940           DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2941         { 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2942         { 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2943         { 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2944         { 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2945 };
2946 
2947 static bool
2948 stereo_match_mandatory(const struct drm_display_mode *mode,
2949                        const struct stereo_mandatory_mode *stereo_mode)
2950 {
2951         unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2952 
2953         return mode->hdisplay == stereo_mode->width &&
2954                mode->vdisplay == stereo_mode->height &&
2955                interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2956                drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2957 }
2958 
2959 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2960 {
2961         struct drm_device *dev = connector->dev;
2962         const struct drm_display_mode *mode;
2963         struct list_head stereo_modes;
2964         int modes = 0, i;
2965 
2966         INIT_LIST_HEAD(&stereo_modes);
2967 
2968         list_for_each_entry(mode, &connector->probed_modes, head) {
2969                 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2970                         const struct stereo_mandatory_mode *mandatory;
2971                         struct drm_display_mode *new_mode;
2972 
2973                         if (!stereo_match_mandatory(mode,
2974                                                     &stereo_mandatory_modes[i]))
2975                                 continue;
2976 
2977                         mandatory = &stereo_mandatory_modes[i];
2978                         new_mode = drm_mode_duplicate(dev, mode);
2979                         if (!new_mode)
2980                                 continue;
2981 
2982                         new_mode->flags |= mandatory->flags;
2983                         list_add_tail(&new_mode->head, &stereo_modes);
2984                         modes++;
2985                 }
2986         }
2987 
2988         list_splice_tail(&stereo_modes, &connector->probed_modes);
2989 
2990         return modes;
2991 }
2992 
2993 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2994 {
2995         struct drm_device *dev = connector->dev;
2996         struct drm_display_mode *newmode;
2997 
2998         if (!drm_valid_hdmi_vic(vic)) {
2999                 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3000                 return 0;
3001         }
3002 
3003         newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3004         if (!newmode)
3005                 return 0;
3006 
3007         drm_mode_probed_add(connector, newmode);
3008 
3009         return 1;
3010 }
3011 
3012 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3013                                const u8 *video_db, u8 video_len, u8 video_index)
3014 {
3015         struct drm_display_mode *newmode;
3016         int modes = 0;
3017 
3018         if (structure & (1 << 0)) {
3019                 newmode = drm_display_mode_from_vic_index(connector, video_db,
3020                                                           video_len,
3021                                                           video_index);
3022                 if (newmode) {
3023                         newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3024                         drm_mode_probed_add(connector, newmode);
3025                         modes++;
3026                 }
3027         }
3028         if (structure & (1 << 6)) {
3029                 newmode = drm_display_mode_from_vic_index(connector, video_db,
3030                                                           video_len,
3031                                                           video_index);
3032                 if (newmode) {
3033                         newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3034                         drm_mode_probed_add(connector, newmode);
3035                         modes++;
3036                 }
3037         }
3038         if (structure & (1 << 8)) {
3039                 newmode = drm_display_mode_from_vic_index(connector, video_db,
3040                                                           video_len,
3041                                                           video_index);
3042                 if (newmode) {
3043                         newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3044                         drm_mode_probed_add(connector, newmode);
3045                         modes++;
3046                 }
3047         }
3048 
3049         return modes;
3050 }
3051 
3052 /*
3053  * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3054  * @connector: connector corresponding to the HDMI sink
3055  * @db: start of the CEA vendor specific block
3056  * @len: length of the CEA block payload, ie. one can access up to db[len]
3057  *
3058  * Parses the HDMI VSDB looking for modes to add to @connector. This function
3059  * also adds the stereo 3d modes when applicable.
3060  */
3061 static int
3062 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3063                    const u8 *video_db, u8 video_len)
3064 {
3065         int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3066         u8 vic_len, hdmi_3d_len = 0;
3067         u16 mask;
3068         u16 structure_all;
3069 
3070         if (len < 8)
3071                 goto out;
3072 
3073         /* no HDMI_Video_Present */
3074         if (!(db[8] & (1 << 5)))
3075                 goto out;
3076 
3077         /* Latency_Fields_Present */
3078         if (db[8] & (1 << 7))
3079                 offset += 2;
3080 
3081         /* I_Latency_Fields_Present */
3082         if (db[8] & (1 << 6))
3083                 offset += 2;
3084 
3085         /* the declared length is not long enough for the 2 first bytes
3086          * of additional video format capabilities */
3087         if (len < (8 + offset + 2))
3088                 goto out;
3089 
3090         /* 3D_Present */
3091         offset++;
3092         if (db[8 + offset] & (1 << 7)) {
3093                 modes += add_hdmi_mandatory_stereo_modes(connector);
3094 
3095                 /* 3D_Multi_present */
3096                 multi_present = (db[8 + offset] & 0x60) >> 5;
3097         }
3098 
3099         offset++;
3100         vic_len = db[8 + offset] >> 5;
3101         hdmi_3d_len = db[8 + offset] & 0x1f;
3102 
3103         for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3104                 u8 vic;
3105 
3106                 vic = db[9 + offset + i];
3107                 modes += add_hdmi_mode(connector, vic);
3108         }
3109         offset += 1 + vic_len;
3110 
3111         if (multi_present == 1)
3112                 multi_len = 2;
3113         else if (multi_present == 2)
3114                 multi_len = 4;
3115         else
3116                 multi_len = 0;
3117 
3118         if (len < (8 + offset + hdmi_3d_len - 1))
3119                 goto out;
3120 
3121         if (hdmi_3d_len < multi_len)
3122                 goto out;
3123 
3124         if (multi_present == 1 || multi_present == 2) {
3125                 /* 3D_Structure_ALL */
3126                 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3127 
3128                 /* check if 3D_MASK is present */
3129                 if (multi_present == 2)
3130                         mask = (db[10 + offset] << 8) | db[11 + offset];
3131                 else
3132                         mask = 0xffff;
3133 
3134                 for (i = 0; i < 16; i++) {
3135                         if (mask & (1 << i))
3136                                 modes += add_3d_struct_modes(connector,
3137                                                 structure_all,
3138                                                 video_db,
3139                                                 video_len, i);
3140                 }
3141         }
3142 
3143         offset += multi_len;
3144 
3145         for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3146                 int vic_index;
3147                 struct drm_display_mode *newmode = NULL;
3148                 unsigned int newflag = 0;
3149                 bool detail_present;
3150 
3151                 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3152 
3153                 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3154                         break;
3155 
3156                 /* 2D_VIC_order_X */
3157                 vic_index = db[8 + offset + i] >> 4;
3158 
3159                 /* 3D_Structure_X */
3160                 switch (db[8 + offset + i] & 0x0f) {
3161                 case 0:
3162                         newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3163                         break;
3164                 case 6:
3165                         newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3166                         break;
3167                 case 8:
3168                         /* 3D_Detail_X */
3169                         if ((db[9 + offset + i] >> 4) == 1)
3170                                 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3171                         break;
3172                 }
3173 
3174                 if (newflag != 0) {
3175                         newmode = drm_display_mode_from_vic_index(connector,
3176                                                                   video_db,
3177                                                                   video_len,
3178                                                                   vic_index);
3179 
3180                         if (newmode) {
3181                                 newmode->flags |= newflag;
3182                                 drm_mode_probed_add(connector, newmode);
3183                                 modes++;
3184                         }
3185                 }
3186 
3187                 if (detail_present)
3188                         i++;
3189         }
3190 
3191 out:
3192         return modes;
3193 }
3194 
3195 static int
3196 cea_db_payload_len(const u8 *db)
3197 {
3198         return db[0] & 0x1f;
3199 }
3200 
3201 static int
3202 cea_db_tag(const u8 *db)
3203 {
3204         return db[0] >> 5;
3205 }
3206 
3207 static int
3208 cea_revision(const u8 *cea)
3209 {
3210         return cea[1];
3211 }
3212 
3213 static int
3214 cea_db_offsets(const u8 *cea, int *start, int *end)
3215 {
3216         /* Data block offset in CEA extension block */
3217         *start = 4;
3218         *end = cea[2];
3219         if (*end == 0)
3220                 *end = 127;
3221         if (*end < 4 || *end > 127)
3222                 return -ERANGE;
3223         return 0;
3224 }
3225 
3226 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3227 {
3228         int hdmi_id;
3229 
3230         if (cea_db_tag(db) != VENDOR_BLOCK)
3231                 return false;
3232 
3233         if (cea_db_payload_len(db) < 5)
3234                 return false;
3235 
3236         hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3237 
3238         return hdmi_id == HDMI_IEEE_OUI;
3239 }
3240 
3241 #define for_each_cea_db(cea, i, start, end) \
3242         for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3243 
3244 static int
3245 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3246 {
3247         const u8 *cea = drm_find_cea_extension(edid);
3248         const u8 *db, *hdmi = NULL, *video = NULL;
3249         u8 dbl, hdmi_len, video_len = 0;
3250         int modes = 0;
3251 
3252         if (cea && cea_revision(cea) >= 3) {
3253                 int i, start, end;
3254 
3255                 if (cea_db_offsets(cea, &start, &end))
3256                         return 0;
3257 
3258                 for_each_cea_db(cea, i, start, end) {
3259                         db = &cea[i];
3260                         dbl = cea_db_payload_len(db);
3261 
3262                         if (cea_db_tag(db) == VIDEO_BLOCK) {
3263                                 video = db + 1;
3264                                 video_len = dbl;
3265                                 modes += do_cea_modes(connector, video, dbl);
3266                         }
3267                         else if (cea_db_is_hdmi_vsdb(db)) {
3268                                 hdmi = db;
3269                                 hdmi_len = dbl;
3270                         }
3271                 }
3272         }
3273 
3274         /*
3275          * We parse the HDMI VSDB after having added the cea modes as we will
3276          * be patching their flags when the sink supports stereo 3D.
3277          */
3278         if (hdmi)
3279                 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3280                                             video_len);
3281 
3282         return modes;
3283 }
3284 
3285 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3286 {
3287         const struct drm_display_mode *cea_mode;
3288         int clock1, clock2, clock;
3289         u8 vic;
3290         const char *type;
3291 
3292         /*
3293          * allow 5kHz clock difference either way to account for
3294          * the 10kHz clock resolution limit of detailed timings.
3295          */
3296         vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3297         if (drm_valid_cea_vic(vic)) {
3298                 type = "CEA";
3299                 cea_mode = &edid_cea_modes[vic];
3300                 clock1 = cea_mode->clock;
3301                 clock2 = cea_mode_alternate_clock(cea_mode);
3302         } else {
3303                 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3304                 if (drm_valid_hdmi_vic(vic)) {
3305                         type = "HDMI";
3306                         cea_mode = &edid_4k_modes[vic];
3307                         clock1 = cea_mode->clock;
3308                         clock2 = hdmi_mode_alternate_clock(cea_mode);
3309                 } else {
3310                         return;
3311                 }
3312         }
3313 
3314         /* pick whichever is closest */
3315         if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3316                 clock = clock1;
3317         else
3318                 clock = clock2;
3319 
3320         if (mode->clock == clock)
3321                 return;
3322 
3323         DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3324                   type, vic, mode->clock, clock);
3325         mode->clock = clock;
3326 }
3327 
3328 static void
3329 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3330 {
3331         u8 len = cea_db_payload_len(db);
3332 
3333         if (len >= 6)
3334                 connector->eld[5] |= (db[6] >> 7) << 1;  /* Supports_AI */
3335         if (len >= 8) {
3336                 connector->latency_present[0] = db[8] >> 7;
3337                 connector->latency_present[1] = (db[8] >> 6) & 1;
3338         }
3339         if (len >= 9)
3340                 connector->video_latency[0] = db[9];
3341         if (len >= 10)
3342                 connector->audio_latency[0] = db[10];
3343         if (len >= 11)
3344                 connector->video_latency[1] = db[11];
3345         if (len >= 12)
3346                 connector->audio_latency[1] = db[12];
3347 
3348         DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3349                       "video latency %d %d, "
3350                       "audio latency %d %d\n",
3351                       connector->latency_present[0],
3352                       connector->latency_present[1],
3353                       connector->video_latency[0],
3354                       connector->video_latency[1],
3355                       connector->audio_latency[0],
3356                       connector->audio_latency[1]);
3357 }
3358 
3359 static void
3360 monitor_name(struct detailed_timing *t, void *data)
3361 {
3362         if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3363                 *(u8 **)data = t->data.other_data.data.str.str;
3364 }
3365 
3366 static int get_monitor_name(struct edid *edid, char name[13])
3367 {
3368         char *edid_name = NULL;
3369         int mnl;
3370 
3371         if (!edid || !name)
3372                 return 0;
3373 
3374         drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3375         for (mnl = 0; edid_name && mnl < 13; mnl++) {
3376                 if (edid_name[mnl] == 0x0a)
3377                         break;
3378 
3379                 name[mnl] = edid_name[mnl];
3380         }
3381 
3382         return mnl;
3383 }
3384 
3385 /**
3386  * drm_edid_get_monitor_name - fetch the monitor name from the edid
3387  * @edid: monitor EDID information
3388  * @name: pointer to a character array to hold the name of the monitor
3389  * @bufsize: The size of the name buffer (should be at least 14 chars.)
3390  *
3391  */
3392 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3393 {
3394         int name_length;
3395         char buf[13];
3396         
3397         if (bufsize <= 0)
3398                 return;
3399 
3400         name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3401         memcpy(name, buf, name_length);
3402         name[name_length] = '\0';
3403 }
3404 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3405 
3406 /**
3407  * drm_edid_to_eld - build ELD from EDID
3408  * @connector: connector corresponding to the HDMI/DP sink
3409  * @edid: EDID to parse
3410  *
3411  * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3412  * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3413  * fill in.
3414  */
3415 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3416 {
3417         uint8_t *eld = connector->eld;
3418         u8 *cea;
3419         u8 *db;
3420         int total_sad_count = 0;
3421         int mnl;
3422         int dbl;
3423 
3424         memset(eld, 0, sizeof(connector->eld));
3425 
3426         connector->latency_present[0] = false;
3427         connector->latency_present[1] = false;
3428         connector->video_latency[0] = 0;
3429         connector->audio_latency[0] = 0;
3430         connector->video_latency[1] = 0;
3431         connector->audio_latency[1] = 0;
3432 
3433         cea = drm_find_cea_extension(edid);
3434         if (!cea) {
3435                 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3436                 return;
3437         }
3438 
3439         mnl = get_monitor_name(edid, eld + 20);
3440 
3441         eld[4] = (cea[1] << 5) | mnl;
3442         DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3443 
3444         eld[0] = 2 << 3;                /* ELD version: 2 */
3445 
3446         eld[16] = edid->mfg_id[0];
3447         eld[17] = edid->mfg_id[1];
3448         eld[18] = edid->prod_code[0];
3449         eld[19] = edid->prod_code[1];
3450 
3451         if (cea_revision(cea) >= 3) {
3452                 int i, start, end;
3453 
3454                 if (cea_db_offsets(cea, &start, &end)) {
3455                         start = 0;
3456                         end = 0;
3457                 }
3458 
3459                 for_each_cea_db(cea, i, start, end) {
3460                         db = &cea[i];
3461                         dbl = cea_db_payload_len(db);
3462 
3463                         switch (cea_db_tag(db)) {
3464                                 int sad_count;
3465 
3466                         case AUDIO_BLOCK:
3467                                 /* Audio Data Block, contains SADs */
3468                                 sad_count = min(dbl / 3, 15 - total_sad_count);
3469                                 if (sad_count >= 1)
3470                                         memcpy(eld + 20 + mnl + total_sad_count * 3,
3471                                                &db[1], sad_count * 3);
3472                                 total_sad_count += sad_count;
3473                                 break;
3474                         case SPEAKER_BLOCK:
3475                                 /* Speaker Allocation Data Block */
3476                                 if (dbl >= 1)
3477                                         eld[7] = db[1];
3478                                 break;
3479                         case VENDOR_BLOCK:
3480                                 /* HDMI Vendor-Specific Data Block */
3481                                 if (cea_db_is_hdmi_vsdb(db))
3482                                         drm_parse_hdmi_vsdb_audio(connector, db);
3483                                 break;
3484                         default:
3485                                 break;
3486                         }
3487                 }
3488         }
3489         eld[5] |= total_sad_count << 4;
3490 
3491         eld[DRM_ELD_BASELINE_ELD_LEN] =
3492                 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3493 
3494         DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3495                       drm_eld_size(eld), total_sad_count);
3496 }
3497 EXPORT_SYMBOL(drm_edid_to_eld);
3498 
3499 /**
3500  * drm_edid_to_sad - extracts SADs from EDID
3501  * @edid: EDID to parse
3502  * @sads: pointer that will be set to the extracted SADs
3503  *
3504  * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3505  *
3506  * Note: The returned pointer needs to be freed using kfree().
3507  *
3508  * Return: The number of found SADs or negative number on error.
3509  */
3510 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3511 {
3512         int count = 0;
3513         int i, start, end, dbl;
3514         u8 *cea;
3515 
3516         cea = drm_find_cea_extension(edid);
3517         if (!cea) {
3518                 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3519                 return -ENOENT;
3520         }
3521 
3522         if (cea_revision(cea) < 3) {
3523                 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3524                 return -ENOTSUPP;
3525         }
3526 
3527         if (cea_db_offsets(cea, &start, &end)) {
3528                 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3529                 return -EPROTO;
3530         }
3531 
3532         for_each_cea_db(cea, i, start, end) {
3533                 u8 *db = &cea[i];
3534 
3535                 if (cea_db_tag(db) == AUDIO_BLOCK) {
3536                         int j;
3537                         dbl = cea_db_payload_len(db);
3538 
3539                         count = dbl / 3; /* SAD is 3B */
3540                         *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3541                         if (!*sads)
3542                                 return -ENOMEM;
3543                         for (j = 0; j < count; j++) {
3544                                 u8 *sad = &db[1 + j * 3];
3545 
3546                                 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3547                                 (*sads)[j].channels = sad[0] & 0x7;
3548                                 (*sads)[j].freq = sad[1] & 0x7F;
3549                                 (*sads)[j].byte2 = sad[2];
3550                         }
3551                         break;
3552                 }
3553         }
3554 
3555         return count;
3556 }
3557 EXPORT_SYMBOL(drm_edid_to_sad);
3558 
3559 /**
3560  * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3561  * @edid: EDID to parse
3562  * @sadb: pointer to the speaker block
3563  *
3564  * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3565  *
3566  * Note: The returned pointer needs to be freed using kfree().
3567  *
3568  * Return: The number of found Speaker Allocation Blocks or negative number on
3569  * error.
3570  */
3571 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3572 {
3573         int count = 0;
3574         int i, start, end, dbl;
3575         const u8 *cea;
3576 
3577         cea = drm_find_cea_extension(edid);
3578         if (!cea) {
3579                 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3580                 return -ENOENT;
3581         }
3582 
3583         if (cea_revision(cea) < 3) {
3584                 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3585                 return -ENOTSUPP;
3586         }
3587 
3588         if (cea_db_offsets(cea, &start, &end)) {
3589                 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3590                 return -EPROTO;
3591         }
3592 
3593         for_each_cea_db(cea, i, start, end) {
3594                 const u8 *db = &cea[i];
3595 
3596                 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3597                         dbl = cea_db_payload_len(db);
3598 
3599                         /* Speaker Allocation Data Block */
3600                         if (dbl == 3) {
3601                                 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3602                                 if (!*sadb)
3603                                         return -ENOMEM;
3604                                 count = dbl;
3605                                 break;
3606                         }
3607                 }
3608         }
3609 
3610         return count;
3611 }
3612 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3613 
3614 /**
3615  * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3616  * @connector: connector associated with the HDMI/DP sink
3617  * @mode: the display mode
3618  *
3619  * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3620  * the sink doesn't support audio or video.
3621  */
3622 int drm_av_sync_delay(struct drm_connector *connector,
3623                       const struct drm_display_mode *mode)
3624 {
3625         int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3626         int a, v;
3627 
3628         if (!connector->latency_present[0])
3629                 return 0;
3630         if (!connector->latency_present[1])
3631                 i = 0;
3632 
3633         a = connector->audio_latency[i];
3634         v = connector->video_latency[i];
3635 
3636         /*
3637          * HDMI/DP sink doesn't support audio or video?
3638          */
3639         if (a == 255 || v == 255)
3640                 return 0;
3641 
3642         /*
3643          * Convert raw EDID values to millisecond.
3644          * Treat unknown latency as 0ms.
3645          */
3646         if (a)
3647                 a = min(2 * (a - 1), 500);
3648         if (v)
3649                 v = min(2 * (v - 1), 500);
3650 
3651         return max(v - a, 0);
3652 }
3653 EXPORT_SYMBOL(drm_av_sync_delay);
3654 
3655 /**
3656  * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3657  * @edid: monitor EDID information
3658  *
3659  * Parse the CEA extension according to CEA-861-B.
3660  *
3661  * Return: True if the monitor is HDMI, false if not or unknown.
3662  */
3663 bool drm_detect_hdmi_monitor(struct edid *edid)
3664 {
3665         u8 *edid_ext;
3666         int i;
3667         int start_offset, end_offset;
3668 
3669         edid_ext = drm_find_cea_extension(edid);
3670         if (!edid_ext)
3671                 return false;
3672 
3673         if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3674                 return false;
3675 
3676         /*
3677          * Because HDMI identifier is in Vendor Specific Block,
3678          * search it from all data blocks of CEA extension.
3679          */
3680         for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3681                 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3682                         return true;
3683         }
3684 
3685         return false;
3686 }
3687 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3688 
3689 /**
3690  * drm_detect_monitor_audio - check monitor audio capability
3691  * @edid: EDID block to scan
3692  *
3693  * Monitor should have CEA extension block.
3694  * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3695  * audio' only. If there is any audio extension block and supported
3696  * audio format, assume at least 'basic audio' support, even if 'basic
3697  * audio' is not defined in EDID.
3698  *
3699  * Return: True if the monitor supports audio, false otherwise.
3700  */
3701 bool drm_detect_monitor_audio(struct edid *edid)
3702 {
3703         u8 *edid_ext;
3704         int i, j;
3705         bool has_audio = false;
3706         int start_offset, end_offset;
3707 
3708         edid_ext = drm_find_cea_extension(edid);
3709         if (!edid_ext)
3710                 goto end;
3711 
3712         has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3713 
3714         if (has_audio) {
3715                 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3716                 goto end;
3717         }
3718 
3719         if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3720                 goto end;
3721 
3722         for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3723                 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3724                         has_audio = true;
3725                         for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3726                                 DRM_DEBUG_KMS("CEA audio format %d\n",
3727                                               (edid_ext[i + j] >> 3) & 0xf);
3728                         goto end;
3729                 }
3730         }
3731 end:
3732         return has_audio;
3733 }
3734 EXPORT_SYMBOL(drm_detect_monitor_audio);
3735 
3736 /**
3737  * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3738  * @edid: EDID block to scan
3739  *
3740  * Check whether the monitor reports the RGB quantization range selection
3741  * as supported. The AVI infoframe can then be used to inform the monitor
3742  * which quantization range (full or limited) is used.
3743  *
3744  * Return: True if the RGB quantization range is selectable, false otherwise.
3745  */
3746 bool drm_rgb_quant_range_selectable(struct edid *edid)
3747 {
3748         u8 *edid_ext;
3749         int i, start, end;
3750 
3751         edid_ext = drm_find_cea_extension(edid);
3752         if (!edid_ext)
3753                 return false;
3754 
3755         if (cea_db_offsets(edid_ext, &start, &end))
3756                 return false;
3757 
3758         for_each_cea_db(edid_ext, i, start, end) {
3759                 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3760                     cea_db_payload_len(&edid_ext[i]) == 2) {
3761                         DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3762                         return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3763                 }
3764         }
3765 
3766         return false;
3767 }
3768 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3769 
3770 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
3771                                            const u8 *hdmi)
3772 {
3773         struct drm_display_info *info = &connector->display_info;
3774         unsigned int dc_bpc = 0;
3775 
3776         /* HDMI supports at least 8 bpc */
3777         info->bpc = 8;
3778 
3779         if (cea_db_payload_len(hdmi) < 6)
3780                 return;
3781 
3782         if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3783                 dc_bpc = 10;
3784                 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3785                 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3786                           connector->name);
3787         }
3788 
3789         if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3790                 dc_bpc = 12;
3791                 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3792                 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3793                           connector->name);
3794         }
3795 
3796         if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3797                 dc_bpc = 16;
3798                 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3799                 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3800                           connector->name);
3801         }
3802 
3803         if (dc_bpc == 0) {
3804                 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3805                           connector->name);
3806                 return;
3807         }
3808 
3809         DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3810                   connector->name, dc_bpc);
3811         info->bpc = dc_bpc;
3812 
3813         /*
3814          * Deep color support mandates RGB444 support for all video
3815          * modes and forbids YCRCB422 support for all video modes per
3816          * HDMI 1.3 spec.
3817          */
3818         info->color_formats = DRM_COLOR_FORMAT_RGB444;
3819 
3820         /* YCRCB444 is optional according to spec. */
3821         if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3822                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3823                 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3824                           connector->name);
3825         }
3826 
3827         /*
3828          * Spec says that if any deep color mode is supported at all,
3829          * then deep color 36 bit must be supported.
3830          */
3831         if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3832                 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3833                           connector->name);
3834         }
3835 }
3836 
3837 static void
3838 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
3839 {
3840         struct drm_display_info *info = &connector->display_info;
3841         u8 len = cea_db_payload_len(db);
3842 
3843         if (len >= 6)
3844                 info->dvi_dual = db[6] & 1;
3845         if (len >= 7)
3846                 info->max_tmds_clock = db[7] * 5000;
3847 
3848         DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3849                       "max TMDS clock %d kHz\n",
3850                       info->dvi_dual,
3851                       info->max_tmds_clock);
3852 
3853         drm_parse_hdmi_deep_color_info(connector, db);
3854 }
3855 
3856 static void drm_parse_cea_ext(struct drm_connector *connector,
3857                               struct edid *edid)
3858 {
3859         struct drm_display_info *info = &connector->display_info;
3860         const u8 *edid_ext;
3861         int i, start, end;
3862 
3863         edid_ext = drm_find_cea_extension(edid);
3864         if (!edid_ext)
3865                 return;
3866 
3867         info->cea_rev = edid_ext[1];
3868 
3869         /* The existence of a CEA block should imply RGB support */
3870         info->color_formats = DRM_COLOR_FORMAT_RGB444;
3871         if (edid_ext[3] & EDID_CEA_YCRCB444)
3872                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3873         if (edid_ext[3] & EDID_CEA_YCRCB422)
3874                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3875 
3876         if (cea_db_offsets(edid_ext, &start, &end))
3877                 return;
3878 
3879         for_each_cea_db(edid_ext, i, start, end) {
3880                 const u8 *db = &edid_ext[i];
3881 
3882                 if (cea_db_is_hdmi_vsdb(db))
3883                         drm_parse_hdmi_vsdb_video(connector, db);
3884         }
3885 }
3886 
3887 static void drm_add_display_info(struct drm_connector *connector,
3888                                  struct edid *edid)
3889 {
3890         struct drm_display_info *info = &connector->display_info;
3891 
3892         info->width_mm = edid->width_cm * 10;
3893         info->height_mm = edid->height_cm * 10;
3894 
3895         /* driver figures it out in this case */
3896         info->bpc = 0;
3897         info->color_formats = 0;
3898         info->cea_rev = 0;
3899         info->max_tmds_clock = 0;
3900         info->dvi_dual = false;
3901 
3902         if (edid->revision < 3)
3903                 return;
3904 
3905         if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3906                 return;
3907 
3908         drm_parse_cea_ext(connector, edid);
3909 
3910         /*
3911          * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
3912          *
3913          * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
3914          * tells us to assume 8 bpc color depth if the EDID doesn't have
3915          * extensions which tell otherwise.
3916          */
3917         if ((info->bpc == 0) && (edid->revision < 4) &&
3918             (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
3919                 info->bpc = 8;
3920                 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
3921                           connector->name, info->bpc);
3922         }
3923 
3924         /* Only defined for 1.4 with digital displays */
3925         if (edid->revision < 4)
3926                 return;
3927 
3928         switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3929         case DRM_EDID_DIGITAL_DEPTH_6:
3930                 info->bpc = 6;
3931                 break;
3932         case DRM_EDID_DIGITAL_DEPTH_8:
3933                 info->bpc = 8;
3934                 break;
3935         case DRM_EDID_DIGITAL_DEPTH_10:
3936                 info->bpc = 10;
3937                 break;
3938         case DRM_EDID_DIGITAL_DEPTH_12:
3939                 info->bpc = 12;
3940                 break;
3941         case DRM_EDID_DIGITAL_DEPTH_14:
3942                 info->bpc = 14;
3943                 break;
3944         case DRM_EDID_DIGITAL_DEPTH_16:
3945                 info->bpc = 16;
3946                 break;
3947         case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3948         default:
3949                 info->bpc = 0;
3950                 break;
3951         }
3952 
3953         DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3954                           connector->name, info->bpc);
3955 
3956         info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3957         if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3958                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3959         if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3960                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3961 }
3962 
3963 static int validate_displayid(u8 *displayid, int length, int idx)
3964 {
3965         int i;
3966         u8 csum = 0;
3967         struct displayid_hdr *base;
3968 
3969         base = (struct displayid_hdr *)&displayid[idx];
3970 
3971         DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
3972                       base->rev, base->bytes, base->prod_id, base->ext_count);
3973 
3974         if (base->bytes + 5 > length - idx)
3975                 return -EINVAL;
3976         for (i = idx; i <= base->bytes + 5; i++) {
3977                 csum += displayid[i];
3978         }
3979         if (csum) {
3980                 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
3981                 return -EINVAL;
3982         }
3983         return 0;
3984 }
3985 
3986 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
3987                                                             struct displayid_detailed_timings_1 *timings)
3988 {
3989         struct drm_display_mode *mode;
3990         unsigned pixel_clock = (timings->pixel_clock[0] |
3991                                 (timings->pixel_clock[1] << 8) |
3992                                 (timings->pixel_clock[2] << 16));
3993         unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
3994         unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
3995         unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
3996         unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
3997         unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
3998         unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
3999         unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4000         unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4001         bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4002         bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4003         mode = drm_mode_create(dev);
4004         if (!mode)
4005                 return NULL;
4006 
4007         mode->clock = pixel_clock * 10;
4008         mode->hdisplay = hactive;
4009         mode->hsync_start = mode->hdisplay + hsync;
4010         mode->hsync_end = mode->hsync_start + hsync_width;
4011         mode->htotal = mode->hdisplay + hblank;
4012 
4013         mode->vdisplay = vactive;
4014         mode->vsync_start = mode->vdisplay + vsync;
4015         mode->vsync_end = mode->vsync_start + vsync_width;
4016         mode->vtotal = mode->vdisplay + vblank;
4017 
4018         mode->flags = 0;
4019         mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4020         mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4021         mode->type = DRM_MODE_TYPE_DRIVER;
4022 
4023         if (timings->flags & 0x80)
4024                 mode->type |= DRM_MODE_TYPE_PREFERRED;
4025         mode->vrefresh = drm_mode_vrefresh(mode);
4026         drm_mode_set_name(mode);
4027 
4028         return mode;
4029 }
4030 
4031 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4032                                           struct displayid_block *block)
4033 {
4034         struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4035         int i;
4036         int num_timings;
4037         struct drm_display_mode *newmode;
4038         int num_modes = 0;
4039         /* blocks must be multiple of 20 bytes length */
4040         if (block->num_bytes % 20)
4041                 return 0;
4042 
4043         num_timings = block->num_bytes / 20;
4044         for (i = 0; i < num_timings; i++) {
4045                 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4046 
4047                 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4048                 if (!newmode)
4049                         continue;
4050 
4051                 drm_mode_probed_add(connector, newmode);
4052                 num_modes++;
4053         }
4054         return num_modes;
4055 }
4056 
4057 static int add_displayid_detailed_modes(struct drm_connector *connector,
4058                                         struct edid *edid)
4059 {
4060         u8 *displayid;
4061         int ret;
4062         int idx = 1;
4063         int length = EDID_LENGTH;
4064         struct displayid_block *block;
4065         int num_modes = 0;
4066 
4067         displayid = drm_find_displayid_extension(edid);
4068         if (!displayid)
4069                 return 0;
4070 
4071         ret = validate_displayid(displayid, length, idx);
4072         if (ret)
4073                 return 0;
4074 
4075         idx += sizeof(struct displayid_hdr);
4076         while (block = (struct displayid_block *)&displayid[idx],
4077                idx + sizeof(struct displayid_block) <= length &&
4078                idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4079                block->num_bytes > 0) {
4080                 idx += block->num_bytes + sizeof(struct displayid_block);
4081                 switch (block->tag) {
4082                 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4083                         num_modes += add_displayid_detailed_1_modes(connector, block);
4084                         break;
4085                 }
4086         }
4087         return num_modes;
4088 }
4089 
4090 /**
4091  * drm_add_edid_modes - add modes from EDID data, if available
4092  * @connector: connector we're probing
4093  * @edid: EDID data
4094  *
4095  * Add the specified modes to the connector's mode list. Also fills out the
4096  * &drm_display_info structure in @connector with any information which can be
4097  * derived from the edid.
4098  *
4099  * Return: The number of modes added or 0 if we couldn't find any.
4100  */
4101 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4102 {
4103         int num_modes = 0;
4104         u32 quirks;
4105 
4106         if (edid == NULL) {
4107                 return 0;
4108         }
4109         if (!drm_edid_is_valid(edid)) {
4110                 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4111                          connector->name);
4112                 return 0;
4113         }
4114 
4115         quirks = edid_get_quirks(edid);
4116 
4117         /*
4118          * EDID spec says modes should be preferred in this order:
4119          * - preferred detailed mode
4120          * - other detailed modes from base block
4121          * - detailed modes from extension blocks
4122          * - CVT 3-byte code modes
4123          * - standard timing codes
4124          * - established timing codes
4125          * - modes inferred from GTF or CVT range information
4126          *
4127          * We get this pretty much right.
4128          *
4129          * XXX order for additional mode types in extension blocks?
4130          */
4131         num_modes += add_detailed_modes(connector, edid, quirks);
4132         num_modes += add_cvt_modes(connector, edid);
4133         num_modes += add_standard_modes(connector, edid);
4134         num_modes += add_established_modes(connector, edid);
4135         num_modes += add_cea_modes(connector, edid);
4136         num_modes += add_alternate_cea_modes(connector, edid);
4137         num_modes += add_displayid_detailed_modes(connector, edid);
4138         if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4139                 num_modes += add_inferred_modes(connector, edid);
4140 
4141         if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4142                 edid_fixup_preferred(connector, quirks);
4143 
4144         drm_add_display_info(connector, edid);
4145 
4146         if (quirks & EDID_QUIRK_FORCE_6BPC)
4147                 connector->display_info.bpc = 6;
4148 
4149         if (quirks & EDID_QUIRK_FORCE_8BPC)
4150                 connector->display_info.bpc = 8;
4151 
4152         if (quirks & EDID_QUIRK_FORCE_12BPC)
4153                 connector->display_info.bpc = 12;
4154 
4155         return num_modes;
4156 }
4157 EXPORT_SYMBOL(drm_add_edid_modes);
4158 
4159 /**
4160  * drm_add_modes_noedid - add modes for the connectors without EDID
4161  * @connector: connector we're probing
4162  * @hdisplay: the horizontal display limit
4163  * @vdisplay: the vertical display limit
4164  *
4165  * Add the specified modes to the connector's mode list. Only when the
4166  * hdisplay/vdisplay is not beyond the given limit, it will be added.
4167  *
4168  * Return: The number of modes added or 0 if we couldn't find any.
4169  */
4170 int drm_add_modes_noedid(struct drm_connector *connector,
4171                         int hdisplay, int vdisplay)
4172 {
4173         int i, count, num_modes = 0;
4174         struct drm_display_mode *mode;
4175         struct drm_device *dev = connector->dev;
4176 
4177         count = ARRAY_SIZE(drm_dmt_modes);
4178         if (hdisplay < 0)
4179                 hdisplay = 0;
4180         if (vdisplay < 0)
4181                 vdisplay = 0;
4182 
4183         for (i = 0; i < count; i++) {
4184                 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4185                 if (hdisplay && vdisplay) {
4186                         /*
4187                          * Only when two are valid, they will be used to check
4188                          * whether the mode should be added to the mode list of
4189                          * the connector.
4190                          */
4191                         if (ptr->hdisplay > hdisplay ||
4192                                         ptr->vdisplay > vdisplay)
4193                                 continue;
4194                 }
4195                 if (drm_mode_vrefresh(ptr) > 61)
4196                         continue;
4197                 mode = drm_mode_duplicate(dev, ptr);
4198                 if (mode) {
4199                         drm_mode_probed_add(connector, mode);
4200                         num_modes++;
4201                 }
4202         }
4203         return num_modes;
4204 }
4205 EXPORT_SYMBOL(drm_add_modes_noedid);
4206 
4207 /**
4208  * drm_set_preferred_mode - Sets the preferred mode of a connector
4209  * @connector: connector whose mode list should be processed
4210  * @hpref: horizontal resolution of preferred mode
4211  * @vpref: vertical resolution of preferred mode
4212  *
4213  * Marks a mode as preferred if it matches the resolution specified by @hpref
4214  * and @vpref.
4215  */
4216 void drm_set_preferred_mode(struct drm_connector *connector,
4217                            int hpref, int vpref)
4218 {
4219         struct drm_display_mode *mode;
4220 
4221         list_for_each_entry(mode, &connector->probed_modes, head) {
4222                 if (mode->hdisplay == hpref &&
4223                     mode->vdisplay == vpref)
4224                         mode->type |= DRM_MODE_TYPE_PREFERRED;
4225         }
4226 }
4227 EXPORT_SYMBOL(drm_set_preferred_mode);
4228 
4229 /**
4230  * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4231  *                                              data from a DRM display mode
4232  * @frame: HDMI AVI infoframe
4233  * @mode: DRM display mode
4234  *
4235  * Return: 0 on success or a negative error code on failure.
4236  */
4237 int
4238 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4239                                          const struct drm_display_mode *mode)
4240 {
4241         int err;
4242 
4243         if (!frame || !mode)
4244                 return -EINVAL;
4245 
4246         err = hdmi_avi_infoframe_init(frame);
4247         if (err < 0)
4248                 return err;
4249 
4250         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4251                 frame->pixel_repeat = 1;
4252 
4253         frame->video_code = drm_match_cea_mode(mode);
4254 
4255         frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4256 
4257         /*
4258          * Populate picture aspect ratio from either
4259          * user input (if specified) or from the CEA mode list.
4260          */
4261         if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4262                 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4263                 frame->picture_aspect = mode->picture_aspect_ratio;
4264         else if (frame->video_code > 0)
4265                 frame->picture_aspect = drm_get_cea_aspect_ratio(
4266                                                 frame->video_code);
4267 
4268         frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4269         frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4270 
4271         return 0;
4272 }
4273 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4274 
4275 static enum hdmi_3d_structure
4276 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4277 {
4278         u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4279 
4280         switch (layout) {
4281         case DRM_MODE_FLAG_3D_FRAME_PACKING:
4282                 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4283         case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4284                 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4285         case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4286                 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4287         case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4288                 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4289         case DRM_MODE_FLAG_3D_L_DEPTH:
4290                 return HDMI_3D_STRUCTURE_L_DEPTH;
4291         case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4292                 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4293         case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4294                 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4295         case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4296                 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4297         default:
4298                 return HDMI_3D_STRUCTURE_INVALID;
4299         }
4300 }
4301 
4302 /**
4303  * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4304  * data from a DRM display mode
4305  * @frame: HDMI vendor infoframe
4306  * @mode: DRM display mode
4307  *
4308  * Note that there's is a need to send HDMI vendor infoframes only when using a
4309  * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4310  * function will return -EINVAL, error that can be safely ignored.
4311  *
4312  * Return: 0 on success or a negative error code on failure.
4313  */
4314 int
4315 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4316                                             const struct drm_display_mode *mode)
4317 {
4318         int err;
4319         u32 s3d_flags;
4320         u8 vic;
4321 
4322         if (!frame || !mode)
4323                 return -EINVAL;
4324 
4325         vic = drm_match_hdmi_mode(mode);
4326         s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4327 
4328         if (!vic && !s3d_flags)
4329                 return -EINVAL;
4330 
4331         if (vic && s3d_flags)
4332                 return -EINVAL;
4333 
4334         err = hdmi_vendor_infoframe_init(frame);
4335         if (err < 0)
4336                 return err;
4337 
4338         if (vic)
4339                 frame->vic = vic;
4340         else
4341                 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4342 
4343         return 0;
4344 }
4345 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4346 
4347 static int drm_parse_tiled_block(struct drm_connector *connector,
4348                                  struct displayid_block *block)
4349 {
4350         struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4351         u16 w, h;
4352         u8 tile_v_loc, tile_h_loc;
4353         u8 num_v_tile, num_h_tile;
4354         struct drm_tile_group *tg;
4355 
4356         w = tile->tile_size[0] | tile->tile_size[1] << 8;
4357         h = tile->tile_size[2] | tile->tile_size[3] << 8;
4358 
4359         num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4360         num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4361         tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4362         tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4363 
4364         connector->has_tile = true;
4365         if (tile->tile_cap & 0x80)
4366                 connector->tile_is_single_monitor = true;
4367 
4368         connector->num_h_tile = num_h_tile + 1;
4369         connector->num_v_tile = num_v_tile + 1;
4370         connector->tile_h_loc = tile_h_loc;
4371         connector->tile_v_loc = tile_v_loc;
4372         connector->tile_h_size = w + 1;
4373         connector->tile_v_size = h + 1;
4374 
4375         DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4376         DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4377         DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4378                       num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4379         DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4380 
4381         tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4382         if (!tg) {
4383                 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4384         }
4385         if (!tg)
4386                 return -ENOMEM;
4387 
4388         if (connector->tile_group != tg) {
4389                 /* if we haven't got a pointer,
4390                    take the reference, drop ref to old tile group */
4391                 if (connector->tile_group) {
4392                         drm_mode_put_tile_group(connector->dev, connector->tile_group);
4393                 }
4394                 connector->tile_group = tg;
4395         } else
4396                 /* if same tile group, then release the ref we just took. */
4397                 drm_mode_put_tile_group(connector->dev, tg);
4398         return 0;
4399 }
4400 
4401 static int drm_parse_display_id(struct drm_connector *connector,
4402                                 u8 *displayid, int length,
4403                                 bool is_edid_extension)
4404 {
4405         /* if this is an EDID extension the first byte will be 0x70 */
4406         int idx = 0;
4407         struct displayid_block *block;
4408         int ret;
4409 
4410         if (is_edid_extension)
4411                 idx = 1;
4412 
4413         ret = validate_displayid(displayid, length, idx);
4414         if (ret)
4415                 return ret;
4416 
4417         idx += sizeof(struct displayid_hdr);
4418         while (block = (struct displayid_block *)&displayid[idx],
4419                idx + sizeof(struct displayid_block) <= length &&
4420                idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4421                block->num_bytes > 0) {
4422                 idx += block->num_bytes + sizeof(struct displayid_block);
4423                 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4424                               block->tag, block->rev, block->num_bytes);
4425 
4426                 switch (block->tag) {
4427                 case DATA_BLOCK_TILED_DISPLAY:
4428                         ret = drm_parse_tiled_block(connector, block);
4429                         if (ret)
4430                                 return ret;
4431                         break;
4432                 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4433                         /* handled in mode gathering code. */
4434                         break;
4435                 default:
4436                         DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4437                         break;
4438                 }
4439         }
4440         return 0;
4441 }
4442 
4443 static void drm_get_displayid(struct drm_connector *connector,
4444                               struct edid *edid)
4445 {
4446         void *displayid = NULL;
4447         int ret;
4448         connector->has_tile = false;
4449         displayid = drm_find_displayid_extension(edid);
4450         if (!displayid) {
4451                 /* drop reference to any tile group we had */
4452                 goto out_drop_ref;
4453         }
4454 
4455         ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4456         if (ret < 0)
4457                 goto out_drop_ref;
4458         if (!connector->has_tile)
4459                 goto out_drop_ref;
4460         return;
4461 out_drop_ref:
4462         if (connector->tile_group) {
4463                 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4464                 connector->tile_group = NULL;
4465         }
4466         return;
4467 }
4468 

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