Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/gpio/gpio-lpc32xx.c

  1 /*
  2  * GPIO driver for LPC32xx SoC
  3  *
  4  * Author: Kevin Wells <kevin.wells@nxp.com>
  5  *
  6  * Copyright (C) 2010 NXP Semiconductors
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/init.h>
 21 #include <linux/io.h>
 22 #include <linux/errno.h>
 23 #include <linux/gpio.h>
 24 #include <linux/of.h>
 25 #include <linux/of_gpio.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/module.h>
 28 
 29 #include <mach/hardware.h>
 30 #include <mach/platform.h>
 31 
 32 #define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
 33 #define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
 34 #define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
 35 #define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
 36 #define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
 37 #define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
 38 #define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
 39 #define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
 40 #define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
 41 #define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
 42 #define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
 43 #define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
 44 #define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
 45 #define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
 46 #define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
 47 #define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
 48 #define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
 49 #define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
 50 #define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
 51 #define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
 52 #define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
 53 #define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
 54 #define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
 55 #define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
 56 #define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
 57 #define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
 58 #define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
 59 
 60 #define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
 61 #define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
 62 #define GPO3_PIN_TO_BIT(x)                      (1 << (x))
 63 #define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
 64 #define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
 65 #define GPIO3_PIN_IN_SEL(x, y)                  (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
 66 #define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
 67 #define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
 68 #define GPO3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
 69 
 70 #define LPC32XX_GPIO_P0_MAX     8
 71 #define LPC32XX_GPIO_P1_MAX     24
 72 #define LPC32XX_GPIO_P2_MAX     13
 73 #define LPC32XX_GPIO_P3_MAX     6
 74 #define LPC32XX_GPI_P3_MAX      29
 75 #define LPC32XX_GPO_P3_MAX      24
 76 
 77 #define LPC32XX_GPIO_P0_GRP     0
 78 #define LPC32XX_GPIO_P1_GRP     (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
 79 #define LPC32XX_GPIO_P2_GRP     (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
 80 #define LPC32XX_GPIO_P3_GRP     (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
 81 #define LPC32XX_GPI_P3_GRP      (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
 82 #define LPC32XX_GPO_P3_GRP      (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
 83 
 84 struct gpio_regs {
 85         void __iomem *inp_state;
 86         void __iomem *outp_state;
 87         void __iomem *outp_set;
 88         void __iomem *outp_clr;
 89         void __iomem *dir_set;
 90         void __iomem *dir_clr;
 91 };
 92 
 93 /*
 94  * GPIO names
 95  */
 96 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
 97         "p0.0", "p0.1", "p0.2", "p0.3",
 98         "p0.4", "p0.5", "p0.6", "p0.7"
 99 };
100 
101 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
102         "p1.0", "p1.1", "p1.2", "p1.3",
103         "p1.4", "p1.5", "p1.6", "p1.7",
104         "p1.8", "p1.9", "p1.10", "p1.11",
105         "p1.12", "p1.13", "p1.14", "p1.15",
106         "p1.16", "p1.17", "p1.18", "p1.19",
107         "p1.20", "p1.21", "p1.22", "p1.23",
108 };
109 
110 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
111         "p2.0", "p2.1", "p2.2", "p2.3",
112         "p2.4", "p2.5", "p2.6", "p2.7",
113         "p2.8", "p2.9", "p2.10", "p2.11",
114         "p2.12"
115 };
116 
117 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
118         "gpio00", "gpio01", "gpio02", "gpio03",
119         "gpio04", "gpio05"
120 };
121 
122 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
123         "gpi00", "gpi01", "gpi02", "gpi03",
124         "gpi04", "gpi05", "gpi06", "gpi07",
125         "gpi08", "gpi09",  NULL,    NULL,
126          NULL,    NULL,    NULL,   "gpi15",
127         "gpi16", "gpi17", "gpi18", "gpi19",
128         "gpi20", "gpi21", "gpi22", "gpi23",
129         "gpi24", "gpi25", "gpi26", "gpi27",
130         "gpi28"
131 };
132 
133 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
134         "gpo00", "gpo01", "gpo02", "gpo03",
135         "gpo04", "gpo05", "gpo06", "gpo07",
136         "gpo08", "gpo09", "gpo10", "gpo11",
137         "gpo12", "gpo13", "gpo14", "gpo15",
138         "gpo16", "gpo17", "gpo18", "gpo19",
139         "gpo20", "gpo21", "gpo22", "gpo23"
140 };
141 
142 static struct gpio_regs gpio_grp_regs_p0 = {
143         .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
144         .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
145         .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
146         .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
147         .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
148 };
149 
150 static struct gpio_regs gpio_grp_regs_p1 = {
151         .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
152         .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
153         .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
154         .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
155         .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
156 };
157 
158 static struct gpio_regs gpio_grp_regs_p2 = {
159         .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
160         .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
161         .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
162         .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
163         .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
164 };
165 
166 static struct gpio_regs gpio_grp_regs_p3 = {
167         .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
168         .outp_state     = LPC32XX_GPIO_P3_OUTP_STATE,
169         .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
170         .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
171         .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
172         .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
173 };
174 
175 struct lpc32xx_gpio_chip {
176         struct gpio_chip        chip;
177         struct gpio_regs        *gpio_grp;
178 };
179 
180 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
181         unsigned pin, int input)
182 {
183         if (input)
184                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
185                         group->gpio_grp->dir_clr);
186         else
187                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
188                         group->gpio_grp->dir_set);
189 }
190 
191 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
192         unsigned pin, int input)
193 {
194         u32 u = GPIO3_PIN_TO_BIT(pin);
195 
196         if (input)
197                 __raw_writel(u, group->gpio_grp->dir_clr);
198         else
199                 __raw_writel(u, group->gpio_grp->dir_set);
200 }
201 
202 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
203         unsigned pin, int high)
204 {
205         if (high)
206                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
207                         group->gpio_grp->outp_set);
208         else
209                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
210                         group->gpio_grp->outp_clr);
211 }
212 
213 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
214         unsigned pin, int high)
215 {
216         u32 u = GPIO3_PIN_TO_BIT(pin);
217 
218         if (high)
219                 __raw_writel(u, group->gpio_grp->outp_set);
220         else
221                 __raw_writel(u, group->gpio_grp->outp_clr);
222 }
223 
224 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
225         unsigned pin, int high)
226 {
227         if (high)
228                 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
229         else
230                 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
231 }
232 
233 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
234         unsigned pin)
235 {
236         return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
237                 pin);
238 }
239 
240 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
241         unsigned pin)
242 {
243         int state = __raw_readl(group->gpio_grp->inp_state);
244 
245         /*
246          * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
247          * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
248          */
249         return GPIO3_PIN_IN_SEL(state, pin);
250 }
251 
252 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
253         unsigned pin)
254 {
255         return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
256 }
257 
258 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
259         unsigned pin)
260 {
261         return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
262 }
263 
264 /*
265  * GPIO primitives.
266  */
267 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
268         unsigned pin)
269 {
270         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
271 
272         __set_gpio_dir_p012(group, pin, 1);
273 
274         return 0;
275 }
276 
277 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
278         unsigned pin)
279 {
280         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
281 
282         __set_gpio_dir_p3(group, pin, 1);
283 
284         return 0;
285 }
286 
287 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
288         unsigned pin)
289 {
290         return 0;
291 }
292 
293 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
294 {
295         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
296 
297         return !!__get_gpio_state_p012(group, pin);
298 }
299 
300 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
301 {
302         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
303 
304         return !!__get_gpio_state_p3(group, pin);
305 }
306 
307 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
308 {
309         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
310 
311         return !!__get_gpi_state_p3(group, pin);
312 }
313 
314 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
315         int value)
316 {
317         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
318 
319         __set_gpio_level_p012(group, pin, value);
320         __set_gpio_dir_p012(group, pin, 0);
321 
322         return 0;
323 }
324 
325 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
326         int value)
327 {
328         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
329 
330         __set_gpio_level_p3(group, pin, value);
331         __set_gpio_dir_p3(group, pin, 0);
332 
333         return 0;
334 }
335 
336 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
337         int value)
338 {
339         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
340 
341         __set_gpo_level_p3(group, pin, value);
342         return 0;
343 }
344 
345 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
346         int value)
347 {
348         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
349 
350         __set_gpio_level_p012(group, pin, value);
351 }
352 
353 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
354         int value)
355 {
356         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
357 
358         __set_gpio_level_p3(group, pin, value);
359 }
360 
361 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
362         int value)
363 {
364         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
365 
366         __set_gpo_level_p3(group, pin, value);
367 }
368 
369 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
370 {
371         struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
372 
373         return !!__get_gpo_state_p3(group, pin);
374 }
375 
376 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
377 {
378         if (pin < chip->ngpio)
379                 return 0;
380 
381         return -EINVAL;
382 }
383 
384 static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
385 {
386         return -ENXIO;
387 }
388 
389 static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
390 {
391         return -ENXIO;
392 }
393 
394 static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
395 {
396         return -ENXIO;
397 }
398 
399 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
400         {
401                 .chip = {
402                         .label                  = "gpio_p0",
403                         .direction_input        = lpc32xx_gpio_dir_input_p012,
404                         .get                    = lpc32xx_gpio_get_value_p012,
405                         .direction_output       = lpc32xx_gpio_dir_output_p012,
406                         .set                    = lpc32xx_gpio_set_value_p012,
407                         .request                = lpc32xx_gpio_request,
408                         .to_irq                 = lpc32xx_gpio_to_irq_p01,
409                         .base                   = LPC32XX_GPIO_P0_GRP,
410                         .ngpio                  = LPC32XX_GPIO_P0_MAX,
411                         .names                  = gpio_p0_names,
412                         .can_sleep              = false,
413                 },
414                 .gpio_grp = &gpio_grp_regs_p0,
415         },
416         {
417                 .chip = {
418                         .label                  = "gpio_p1",
419                         .direction_input        = lpc32xx_gpio_dir_input_p012,
420                         .get                    = lpc32xx_gpio_get_value_p012,
421                         .direction_output       = lpc32xx_gpio_dir_output_p012,
422                         .set                    = lpc32xx_gpio_set_value_p012,
423                         .request                = lpc32xx_gpio_request,
424                         .to_irq                 = lpc32xx_gpio_to_irq_p01,
425                         .base                   = LPC32XX_GPIO_P1_GRP,
426                         .ngpio                  = LPC32XX_GPIO_P1_MAX,
427                         .names                  = gpio_p1_names,
428                         .can_sleep              = false,
429                 },
430                 .gpio_grp = &gpio_grp_regs_p1,
431         },
432         {
433                 .chip = {
434                         .label                  = "gpio_p2",
435                         .direction_input        = lpc32xx_gpio_dir_input_p012,
436                         .get                    = lpc32xx_gpio_get_value_p012,
437                         .direction_output       = lpc32xx_gpio_dir_output_p012,
438                         .set                    = lpc32xx_gpio_set_value_p012,
439                         .request                = lpc32xx_gpio_request,
440                         .base                   = LPC32XX_GPIO_P2_GRP,
441                         .ngpio                  = LPC32XX_GPIO_P2_MAX,
442                         .names                  = gpio_p2_names,
443                         .can_sleep              = false,
444                 },
445                 .gpio_grp = &gpio_grp_regs_p2,
446         },
447         {
448                 .chip = {
449                         .label                  = "gpio_p3",
450                         .direction_input        = lpc32xx_gpio_dir_input_p3,
451                         .get                    = lpc32xx_gpio_get_value_p3,
452                         .direction_output       = lpc32xx_gpio_dir_output_p3,
453                         .set                    = lpc32xx_gpio_set_value_p3,
454                         .request                = lpc32xx_gpio_request,
455                         .to_irq                 = lpc32xx_gpio_to_irq_gpio_p3,
456                         .base                   = LPC32XX_GPIO_P3_GRP,
457                         .ngpio                  = LPC32XX_GPIO_P3_MAX,
458                         .names                  = gpio_p3_names,
459                         .can_sleep              = false,
460                 },
461                 .gpio_grp = &gpio_grp_regs_p3,
462         },
463         {
464                 .chip = {
465                         .label                  = "gpi_p3",
466                         .direction_input        = lpc32xx_gpio_dir_in_always,
467                         .get                    = lpc32xx_gpi_get_value,
468                         .request                = lpc32xx_gpio_request,
469                         .to_irq                 = lpc32xx_gpio_to_irq_gpi_p3,
470                         .base                   = LPC32XX_GPI_P3_GRP,
471                         .ngpio                  = LPC32XX_GPI_P3_MAX,
472                         .names                  = gpi_p3_names,
473                         .can_sleep              = false,
474                 },
475                 .gpio_grp = &gpio_grp_regs_p3,
476         },
477         {
478                 .chip = {
479                         .label                  = "gpo_p3",
480                         .direction_output       = lpc32xx_gpio_dir_out_always,
481                         .set                    = lpc32xx_gpo_set_value,
482                         .get                    = lpc32xx_gpo_get_value,
483                         .request                = lpc32xx_gpio_request,
484                         .base                   = LPC32XX_GPO_P3_GRP,
485                         .ngpio                  = LPC32XX_GPO_P3_MAX,
486                         .names                  = gpo_p3_names,
487                         .can_sleep              = false,
488                 },
489                 .gpio_grp = &gpio_grp_regs_p3,
490         },
491 };
492 
493 static int lpc32xx_of_xlate(struct gpio_chip *gc,
494                             const struct of_phandle_args *gpiospec, u32 *flags)
495 {
496         /* Is this the correct bank? */
497         u32 bank = gpiospec->args[0];
498         if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
499             (gc != &lpc32xx_gpiochip[bank].chip)))
500                 return -EINVAL;
501 
502         if (flags)
503                 *flags = gpiospec->args[2];
504         return gpiospec->args[1];
505 }
506 
507 static int lpc32xx_gpio_probe(struct platform_device *pdev)
508 {
509         int i;
510 
511         for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
512                 if (pdev->dev.of_node) {
513                         lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
514                         lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
515                         lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
516                 }
517                 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
518                                   &lpc32xx_gpiochip[i]);
519         }
520 
521         return 0;
522 }
523 
524 #ifdef CONFIG_OF
525 static const struct of_device_id lpc32xx_gpio_of_match[] = {
526         { .compatible = "nxp,lpc3220-gpio", },
527         { },
528 };
529 #endif
530 
531 static struct platform_driver lpc32xx_gpio_driver = {
532         .driver         = {
533                 .name   = "lpc32xx-gpio",
534                 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
535         },
536         .probe          = lpc32xx_gpio_probe,
537 };
538 
539 module_platform_driver(lpc32xx_gpio_driver);
540 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us