Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/gpio/gpio-lpc32xx.c

  1 /*
  2  * GPIO driver for LPC32xx SoC
  3  *
  4  * Author: Kevin Wells <kevin.wells@nxp.com>
  5  *
  6  * Copyright (C) 2010 NXP Semiconductors
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16  * GNU General Public License for more details.
 17  */
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/init.h>
 21 #include <linux/io.h>
 22 #include <linux/errno.h>
 23 #include <linux/gpio.h>
 24 #include <linux/of.h>
 25 #include <linux/of_gpio.h>
 26 #include <linux/platform_device.h>
 27 #include <linux/module.h>
 28 #include <linux/platform_data/gpio-lpc32xx.h>
 29 
 30 #include <mach/hardware.h>
 31 #include <mach/platform.h>
 32 #include <mach/irqs.h>
 33 
 34 #define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
 35 #define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
 36 #define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
 37 #define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
 38 #define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
 39 #define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
 40 #define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
 41 #define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
 42 #define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
 43 #define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
 44 #define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
 45 #define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
 46 #define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
 47 #define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
 48 #define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
 49 #define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
 50 #define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
 51 #define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
 52 #define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
 53 #define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
 54 #define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
 55 #define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
 56 #define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
 57 #define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
 58 #define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
 59 #define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
 60 #define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
 61 
 62 #define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
 63 #define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
 64 #define GPO3_PIN_TO_BIT(x)                      (1 << (x))
 65 #define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
 66 #define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
 67 #define GPIO3_PIN_IN_SEL(x, y)                  (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
 68 #define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
 69 #define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
 70 #define GPO3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
 71 
 72 struct gpio_regs {
 73         void __iomem *inp_state;
 74         void __iomem *outp_state;
 75         void __iomem *outp_set;
 76         void __iomem *outp_clr;
 77         void __iomem *dir_set;
 78         void __iomem *dir_clr;
 79 };
 80 
 81 /*
 82  * GPIO names
 83  */
 84 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
 85         "p0.0", "p0.1", "p0.2", "p0.3",
 86         "p0.4", "p0.5", "p0.6", "p0.7"
 87 };
 88 
 89 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
 90         "p1.0", "p1.1", "p1.2", "p1.3",
 91         "p1.4", "p1.5", "p1.6", "p1.7",
 92         "p1.8", "p1.9", "p1.10", "p1.11",
 93         "p1.12", "p1.13", "p1.14", "p1.15",
 94         "p1.16", "p1.17", "p1.18", "p1.19",
 95         "p1.20", "p1.21", "p1.22", "p1.23",
 96 };
 97 
 98 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
 99         "p2.0", "p2.1", "p2.2", "p2.3",
100         "p2.4", "p2.5", "p2.6", "p2.7",
101         "p2.8", "p2.9", "p2.10", "p2.11",
102         "p2.12"
103 };
104 
105 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
106         "gpio00", "gpio01", "gpio02", "gpio03",
107         "gpio04", "gpio05"
108 };
109 
110 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
111         "gpi00", "gpi01", "gpi02", "gpi03",
112         "gpi04", "gpi05", "gpi06", "gpi07",
113         "gpi08", "gpi09",  NULL,    NULL,
114          NULL,    NULL,    NULL,   "gpi15",
115         "gpi16", "gpi17", "gpi18", "gpi19",
116         "gpi20", "gpi21", "gpi22", "gpi23",
117         "gpi24", "gpi25", "gpi26", "gpi27",
118         "gpi28"
119 };
120 
121 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
122         "gpo00", "gpo01", "gpo02", "gpo03",
123         "gpo04", "gpo05", "gpo06", "gpo07",
124         "gpo08", "gpo09", "gpo10", "gpo11",
125         "gpo12", "gpo13", "gpo14", "gpo15",
126         "gpo16", "gpo17", "gpo18", "gpo19",
127         "gpo20", "gpo21", "gpo22", "gpo23"
128 };
129 
130 static struct gpio_regs gpio_grp_regs_p0 = {
131         .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
132         .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
133         .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
134         .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
135         .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
136 };
137 
138 static struct gpio_regs gpio_grp_regs_p1 = {
139         .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
140         .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
141         .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
142         .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
143         .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
144 };
145 
146 static struct gpio_regs gpio_grp_regs_p2 = {
147         .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
148         .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
149         .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
150         .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
151         .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
152 };
153 
154 static struct gpio_regs gpio_grp_regs_p3 = {
155         .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
156         .outp_state     = LPC32XX_GPIO_P3_OUTP_STATE,
157         .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
158         .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
159         .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
160         .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
161 };
162 
163 struct lpc32xx_gpio_chip {
164         struct gpio_chip        chip;
165         struct gpio_regs        *gpio_grp;
166 };
167 
168 static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
169         struct gpio_chip *gpc)
170 {
171         return container_of(gpc, struct lpc32xx_gpio_chip, chip);
172 }
173 
174 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
175         unsigned pin, int input)
176 {
177         if (input)
178                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
179                         group->gpio_grp->dir_clr);
180         else
181                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
182                         group->gpio_grp->dir_set);
183 }
184 
185 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
186         unsigned pin, int input)
187 {
188         u32 u = GPIO3_PIN_TO_BIT(pin);
189 
190         if (input)
191                 __raw_writel(u, group->gpio_grp->dir_clr);
192         else
193                 __raw_writel(u, group->gpio_grp->dir_set);
194 }
195 
196 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
197         unsigned pin, int high)
198 {
199         if (high)
200                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
201                         group->gpio_grp->outp_set);
202         else
203                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
204                         group->gpio_grp->outp_clr);
205 }
206 
207 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
208         unsigned pin, int high)
209 {
210         u32 u = GPIO3_PIN_TO_BIT(pin);
211 
212         if (high)
213                 __raw_writel(u, group->gpio_grp->outp_set);
214         else
215                 __raw_writel(u, group->gpio_grp->outp_clr);
216 }
217 
218 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
219         unsigned pin, int high)
220 {
221         if (high)
222                 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
223         else
224                 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
225 }
226 
227 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
228         unsigned pin)
229 {
230         return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
231                 pin);
232 }
233 
234 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
235         unsigned pin)
236 {
237         int state = __raw_readl(group->gpio_grp->inp_state);
238 
239         /*
240          * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
241          * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
242          */
243         return GPIO3_PIN_IN_SEL(state, pin);
244 }
245 
246 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
247         unsigned pin)
248 {
249         return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
250 }
251 
252 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
253         unsigned pin)
254 {
255         return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
256 }
257 
258 /*
259  * GPIO primitives.
260  */
261 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
262         unsigned pin)
263 {
264         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
265 
266         __set_gpio_dir_p012(group, pin, 1);
267 
268         return 0;
269 }
270 
271 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
272         unsigned pin)
273 {
274         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
275 
276         __set_gpio_dir_p3(group, pin, 1);
277 
278         return 0;
279 }
280 
281 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
282         unsigned pin)
283 {
284         return 0;
285 }
286 
287 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
288 {
289         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
290 
291         return __get_gpio_state_p012(group, pin);
292 }
293 
294 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
295 {
296         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
297 
298         return __get_gpio_state_p3(group, pin);
299 }
300 
301 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
302 {
303         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
304 
305         return __get_gpi_state_p3(group, pin);
306 }
307 
308 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
309         int value)
310 {
311         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
312 
313         __set_gpio_level_p012(group, pin, value);
314         __set_gpio_dir_p012(group, pin, 0);
315 
316         return 0;
317 }
318 
319 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
320         int value)
321 {
322         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
323 
324         __set_gpio_level_p3(group, pin, value);
325         __set_gpio_dir_p3(group, pin, 0);
326 
327         return 0;
328 }
329 
330 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
331         int value)
332 {
333         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
334 
335         __set_gpo_level_p3(group, pin, value);
336         return 0;
337 }
338 
339 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
340         int value)
341 {
342         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
343 
344         __set_gpio_level_p012(group, pin, value);
345 }
346 
347 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
348         int value)
349 {
350         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
351 
352         __set_gpio_level_p3(group, pin, value);
353 }
354 
355 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
356         int value)
357 {
358         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
359 
360         __set_gpo_level_p3(group, pin, value);
361 }
362 
363 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
364 {
365         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
366 
367         return __get_gpo_state_p3(group, pin);
368 }
369 
370 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
371 {
372         if (pin < chip->ngpio)
373                 return 0;
374 
375         return -EINVAL;
376 }
377 
378 static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
379 {
380         return IRQ_LPC32XX_P0_P1_IRQ;
381 }
382 
383 static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
384         IRQ_LPC32XX_GPIO_00,
385         IRQ_LPC32XX_GPIO_01,
386         IRQ_LPC32XX_GPIO_02,
387         IRQ_LPC32XX_GPIO_03,
388         IRQ_LPC32XX_GPIO_04,
389         IRQ_LPC32XX_GPIO_05,
390 };
391 
392 static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
393 {
394         if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
395                 return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
396         return -ENXIO;
397 }
398 
399 static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
400         IRQ_LPC32XX_GPI_00,
401         IRQ_LPC32XX_GPI_01,
402         IRQ_LPC32XX_GPI_02,
403         IRQ_LPC32XX_GPI_03,
404         IRQ_LPC32XX_GPI_04,
405         IRQ_LPC32XX_GPI_05,
406         IRQ_LPC32XX_GPI_06,
407         IRQ_LPC32XX_GPI_07,
408         IRQ_LPC32XX_GPI_08,
409         IRQ_LPC32XX_GPI_09,
410         -ENXIO, /* 10 */
411         -ENXIO, /* 11 */
412         -ENXIO, /* 12 */
413         -ENXIO, /* 13 */
414         -ENXIO, /* 14 */
415         -ENXIO, /* 15 */
416         -ENXIO, /* 16 */
417         -ENXIO, /* 17 */
418         -ENXIO, /* 18 */
419         IRQ_LPC32XX_GPI_19,
420         -ENXIO, /* 20 */
421         -ENXIO, /* 21 */
422         -ENXIO, /* 22 */
423         -ENXIO, /* 23 */
424         -ENXIO, /* 24 */
425         -ENXIO, /* 25 */
426         -ENXIO, /* 26 */
427         -ENXIO, /* 27 */
428         IRQ_LPC32XX_GPI_28,
429 };
430 
431 static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
432 {
433         if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
434                 return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
435         return -ENXIO;
436 }
437 
438 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
439         {
440                 .chip = {
441                         .label                  = "gpio_p0",
442                         .direction_input        = lpc32xx_gpio_dir_input_p012,
443                         .get                    = lpc32xx_gpio_get_value_p012,
444                         .direction_output       = lpc32xx_gpio_dir_output_p012,
445                         .set                    = lpc32xx_gpio_set_value_p012,
446                         .request                = lpc32xx_gpio_request,
447                         .to_irq                 = lpc32xx_gpio_to_irq_p01,
448                         .base                   = LPC32XX_GPIO_P0_GRP,
449                         .ngpio                  = LPC32XX_GPIO_P0_MAX,
450                         .names                  = gpio_p0_names,
451                         .can_sleep              = false,
452                 },
453                 .gpio_grp = &gpio_grp_regs_p0,
454         },
455         {
456                 .chip = {
457                         .label                  = "gpio_p1",
458                         .direction_input        = lpc32xx_gpio_dir_input_p012,
459                         .get                    = lpc32xx_gpio_get_value_p012,
460                         .direction_output       = lpc32xx_gpio_dir_output_p012,
461                         .set                    = lpc32xx_gpio_set_value_p012,
462                         .request                = lpc32xx_gpio_request,
463                         .to_irq                 = lpc32xx_gpio_to_irq_p01,
464                         .base                   = LPC32XX_GPIO_P1_GRP,
465                         .ngpio                  = LPC32XX_GPIO_P1_MAX,
466                         .names                  = gpio_p1_names,
467                         .can_sleep              = false,
468                 },
469                 .gpio_grp = &gpio_grp_regs_p1,
470         },
471         {
472                 .chip = {
473                         .label                  = "gpio_p2",
474                         .direction_input        = lpc32xx_gpio_dir_input_p012,
475                         .get                    = lpc32xx_gpio_get_value_p012,
476                         .direction_output       = lpc32xx_gpio_dir_output_p012,
477                         .set                    = lpc32xx_gpio_set_value_p012,
478                         .request                = lpc32xx_gpio_request,
479                         .base                   = LPC32XX_GPIO_P2_GRP,
480                         .ngpio                  = LPC32XX_GPIO_P2_MAX,
481                         .names                  = gpio_p2_names,
482                         .can_sleep              = false,
483                 },
484                 .gpio_grp = &gpio_grp_regs_p2,
485         },
486         {
487                 .chip = {
488                         .label                  = "gpio_p3",
489                         .direction_input        = lpc32xx_gpio_dir_input_p3,
490                         .get                    = lpc32xx_gpio_get_value_p3,
491                         .direction_output       = lpc32xx_gpio_dir_output_p3,
492                         .set                    = lpc32xx_gpio_set_value_p3,
493                         .request                = lpc32xx_gpio_request,
494                         .to_irq                 = lpc32xx_gpio_to_irq_gpio_p3,
495                         .base                   = LPC32XX_GPIO_P3_GRP,
496                         .ngpio                  = LPC32XX_GPIO_P3_MAX,
497                         .names                  = gpio_p3_names,
498                         .can_sleep              = false,
499                 },
500                 .gpio_grp = &gpio_grp_regs_p3,
501         },
502         {
503                 .chip = {
504                         .label                  = "gpi_p3",
505                         .direction_input        = lpc32xx_gpio_dir_in_always,
506                         .get                    = lpc32xx_gpi_get_value,
507                         .request                = lpc32xx_gpio_request,
508                         .to_irq                 = lpc32xx_gpio_to_irq_gpi_p3,
509                         .base                   = LPC32XX_GPI_P3_GRP,
510                         .ngpio                  = LPC32XX_GPI_P3_MAX,
511                         .names                  = gpi_p3_names,
512                         .can_sleep              = false,
513                 },
514                 .gpio_grp = &gpio_grp_regs_p3,
515         },
516         {
517                 .chip = {
518                         .label                  = "gpo_p3",
519                         .direction_output       = lpc32xx_gpio_dir_out_always,
520                         .set                    = lpc32xx_gpo_set_value,
521                         .get                    = lpc32xx_gpo_get_value,
522                         .request                = lpc32xx_gpio_request,
523                         .base                   = LPC32XX_GPO_P3_GRP,
524                         .ngpio                  = LPC32XX_GPO_P3_MAX,
525                         .names                  = gpo_p3_names,
526                         .can_sleep              = false,
527                 },
528                 .gpio_grp = &gpio_grp_regs_p3,
529         },
530 };
531 
532 static int lpc32xx_of_xlate(struct gpio_chip *gc,
533                             const struct of_phandle_args *gpiospec, u32 *flags)
534 {
535         /* Is this the correct bank? */
536         u32 bank = gpiospec->args[0];
537         if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
538             (gc != &lpc32xx_gpiochip[bank].chip)))
539                 return -EINVAL;
540 
541         if (flags)
542                 *flags = gpiospec->args[2];
543         return gpiospec->args[1];
544 }
545 
546 static int lpc32xx_gpio_probe(struct platform_device *pdev)
547 {
548         int i;
549 
550         for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
551                 if (pdev->dev.of_node) {
552                         lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
553                         lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
554                         lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
555                 }
556                 gpiochip_add(&lpc32xx_gpiochip[i].chip);
557         }
558 
559         return 0;
560 }
561 
562 #ifdef CONFIG_OF
563 static const struct of_device_id lpc32xx_gpio_of_match[] = {
564         { .compatible = "nxp,lpc3220-gpio", },
565         { },
566 };
567 #endif
568 
569 static struct platform_driver lpc32xx_gpio_driver = {
570         .driver         = {
571                 .name   = "lpc32xx-gpio",
572                 .owner  = THIS_MODULE,
573                 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
574         },
575         .probe          = lpc32xx_gpio_probe,
576 };
577 
578 module_platform_driver(lpc32xx_gpio_driver);
579 

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