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Linux/drivers/gpio/gpio-davinci.c

  1 /*
  2  * TI DaVinci GPIO Support
  3  *
  4  * Copyright (c) 2006-2007 David Brownell
  5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  */
 12 #include <linux/gpio.h>
 13 #include <linux/errno.h>
 14 #include <linux/kernel.h>
 15 #include <linux/clk.h>
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/irq.h>
 19 #include <linux/irqdomain.h>
 20 #include <linux/module.h>
 21 #include <linux/of.h>
 22 #include <linux/of_device.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/platform_data/gpio-davinci.h>
 25 #include <linux/irqchip/chained_irq.h>
 26 
 27 struct davinci_gpio_regs {
 28         u32     dir;
 29         u32     out_data;
 30         u32     set_data;
 31         u32     clr_data;
 32         u32     in_data;
 33         u32     set_rising;
 34         u32     clr_rising;
 35         u32     set_falling;
 36         u32     clr_falling;
 37         u32     intstat;
 38 };
 39 
 40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
 41 
 42 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
 43 
 44 static void __iomem *gpio_base;
 45 
 46 static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
 47 {
 48         void __iomem *ptr;
 49 
 50         if (gpio < 32 * 1)
 51                 ptr = gpio_base + 0x10;
 52         else if (gpio < 32 * 2)
 53                 ptr = gpio_base + 0x38;
 54         else if (gpio < 32 * 3)
 55                 ptr = gpio_base + 0x60;
 56         else if (gpio < 32 * 4)
 57                 ptr = gpio_base + 0x88;
 58         else if (gpio < 32 * 5)
 59                 ptr = gpio_base + 0xb0;
 60         else
 61                 ptr = NULL;
 62         return ptr;
 63 }
 64 
 65 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
 66 {
 67         struct davinci_gpio_regs __iomem *g;
 68 
 69         g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
 70 
 71         return g;
 72 }
 73 
 74 static int davinci_gpio_irq_setup(struct platform_device *pdev);
 75 
 76 /*--------------------------------------------------------------------------*/
 77 
 78 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
 79 static inline int __davinci_direction(struct gpio_chip *chip,
 80                         unsigned offset, bool out, int value)
 81 {
 82         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 83         struct davinci_gpio_regs __iomem *g = d->regs;
 84         unsigned long flags;
 85         u32 temp;
 86         u32 mask = 1 << offset;
 87 
 88         spin_lock_irqsave(&d->lock, flags);
 89         temp = readl_relaxed(&g->dir);
 90         if (out) {
 91                 temp &= ~mask;
 92                 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
 93         } else {
 94                 temp |= mask;
 95         }
 96         writel_relaxed(temp, &g->dir);
 97         spin_unlock_irqrestore(&d->lock, flags);
 98 
 99         return 0;
100 }
101 
102 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
103 {
104         return __davinci_direction(chip, offset, false, 0);
105 }
106 
107 static int
108 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
109 {
110         return __davinci_direction(chip, offset, true, value);
111 }
112 
113 /*
114  * Read the pin's value (works even if it's set up as output);
115  * returns zero/nonzero.
116  *
117  * Note that changes are synched to the GPIO clock, so reading values back
118  * right after you've set them may give old values.
119  */
120 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
121 {
122         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
123         struct davinci_gpio_regs __iomem *g = d->regs;
124 
125         return !!((1 << offset) & readl_relaxed(&g->in_data));
126 }
127 
128 /*
129  * Assuming the pin is muxed as a gpio output, set its output value.
130  */
131 static void
132 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
133 {
134         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
135         struct davinci_gpio_regs __iomem *g = d->regs;
136 
137         writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
138 }
139 
140 static struct davinci_gpio_platform_data *
141 davinci_gpio_get_pdata(struct platform_device *pdev)
142 {
143         struct device_node *dn = pdev->dev.of_node;
144         struct davinci_gpio_platform_data *pdata;
145         int ret;
146         u32 val;
147 
148         if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
149                 return dev_get_platdata(&pdev->dev);
150 
151         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
152         if (!pdata)
153                 return NULL;
154 
155         ret = of_property_read_u32(dn, "ti,ngpio", &val);
156         if (ret)
157                 goto of_err;
158 
159         pdata->ngpio = val;
160 
161         ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
162         if (ret)
163                 goto of_err;
164 
165         pdata->gpio_unbanked = val;
166 
167         return pdata;
168 
169 of_err:
170         dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
171         return NULL;
172 }
173 
174 #ifdef CONFIG_OF_GPIO
175 static int davinci_gpio_of_xlate(struct gpio_chip *gc,
176                              const struct of_phandle_args *gpiospec,
177                              u32 *flags)
178 {
179         struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent);
180         struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent);
181 
182         if (gpiospec->args[0] > pdata->ngpio)
183                 return -EINVAL;
184 
185         if (gc != &chips[gpiospec->args[0] / 32].chip)
186                 return -EINVAL;
187 
188         if (flags)
189                 *flags = gpiospec->args[1];
190 
191         return gpiospec->args[0] % 32;
192 }
193 #endif
194 
195 static int davinci_gpio_probe(struct platform_device *pdev)
196 {
197         int i, base;
198         unsigned ngpio, nbank;
199         struct davinci_gpio_controller *chips;
200         struct davinci_gpio_platform_data *pdata;
201         struct davinci_gpio_regs __iomem *regs;
202         struct device *dev = &pdev->dev;
203         struct resource *res;
204 
205         pdata = davinci_gpio_get_pdata(pdev);
206         if (!pdata) {
207                 dev_err(dev, "No platform data found\n");
208                 return -EINVAL;
209         }
210 
211         dev->platform_data = pdata;
212 
213         /*
214          * The gpio banks conceptually expose a segmented bitmap,
215          * and "ngpio" is one more than the largest zero-based
216          * bit index that's valid.
217          */
218         ngpio = pdata->ngpio;
219         if (ngpio == 0) {
220                 dev_err(dev, "How many GPIOs?\n");
221                 return -EINVAL;
222         }
223 
224         if (WARN_ON(ARCH_NR_GPIOS < ngpio))
225                 ngpio = ARCH_NR_GPIOS;
226 
227         nbank = DIV_ROUND_UP(ngpio, 32);
228         chips = devm_kzalloc(dev,
229                              nbank * sizeof(struct davinci_gpio_controller),
230                              GFP_KERNEL);
231         if (!chips)
232                 return -ENOMEM;
233 
234         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
235         gpio_base = devm_ioremap_resource(dev, res);
236         if (IS_ERR(gpio_base))
237                 return PTR_ERR(gpio_base);
238 
239         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
240                 chips[i].chip.label = "DaVinci";
241 
242                 chips[i].chip.direction_input = davinci_direction_in;
243                 chips[i].chip.get = davinci_gpio_get;
244                 chips[i].chip.direction_output = davinci_direction_out;
245                 chips[i].chip.set = davinci_gpio_set;
246 
247                 chips[i].chip.base = base;
248                 chips[i].chip.ngpio = ngpio - base;
249                 if (chips[i].chip.ngpio > 32)
250                         chips[i].chip.ngpio = 32;
251 
252 #ifdef CONFIG_OF_GPIO
253                 chips[i].chip.of_gpio_n_cells = 2;
254                 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
255                 chips[i].chip.parent = dev;
256                 chips[i].chip.of_node = dev->of_node;
257 #endif
258                 spin_lock_init(&chips[i].lock);
259 
260                 regs = gpio2regs(base);
261                 if (!regs)
262                         return -ENXIO;
263                 chips[i].regs = regs;
264                 chips[i].set_data = &regs->set_data;
265                 chips[i].clr_data = &regs->clr_data;
266                 chips[i].in_data = &regs->in_data;
267 
268                 gpiochip_add_data(&chips[i].chip, &chips[i]);
269         }
270 
271         platform_set_drvdata(pdev, chips);
272         davinci_gpio_irq_setup(pdev);
273         return 0;
274 }
275 
276 /*--------------------------------------------------------------------------*/
277 /*
278  * We expect irqs will normally be set up as input pins, but they can also be
279  * used as output pins ... which is convenient for testing.
280  *
281  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
282  * to their GPIOBNK0 irq, with a bit less overhead.
283  *
284  * All those INTC hookups (direct, plus several IRQ banks) can also
285  * serve as EDMA event triggers.
286  */
287 
288 static void gpio_irq_disable(struct irq_data *d)
289 {
290         struct davinci_gpio_regs __iomem *g = irq2regs(d);
291         u32 mask = (u32) irq_data_get_irq_handler_data(d);
292 
293         writel_relaxed(mask, &g->clr_falling);
294         writel_relaxed(mask, &g->clr_rising);
295 }
296 
297 static void gpio_irq_enable(struct irq_data *d)
298 {
299         struct davinci_gpio_regs __iomem *g = irq2regs(d);
300         u32 mask = (u32) irq_data_get_irq_handler_data(d);
301         unsigned status = irqd_get_trigger_type(d);
302 
303         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
304         if (!status)
305                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
306 
307         if (status & IRQ_TYPE_EDGE_FALLING)
308                 writel_relaxed(mask, &g->set_falling);
309         if (status & IRQ_TYPE_EDGE_RISING)
310                 writel_relaxed(mask, &g->set_rising);
311 }
312 
313 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
314 {
315         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
316                 return -EINVAL;
317 
318         return 0;
319 }
320 
321 static struct irq_chip gpio_irqchip = {
322         .name           = "GPIO",
323         .irq_enable     = gpio_irq_enable,
324         .irq_disable    = gpio_irq_disable,
325         .irq_set_type   = gpio_irq_type,
326         .flags          = IRQCHIP_SET_TYPE_MASKED,
327 };
328 
329 static void gpio_irq_handler(struct irq_desc *desc)
330 {
331         unsigned int irq = irq_desc_get_irq(desc);
332         struct davinci_gpio_regs __iomem *g;
333         u32 mask = 0xffff;
334         struct davinci_gpio_controller *d;
335 
336         d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
337         g = (struct davinci_gpio_regs __iomem *)d->regs;
338 
339         /* we only care about one bank */
340         if (irq & 1)
341                 mask <<= 16;
342 
343         /* temporarily mask (level sensitive) parent IRQ */
344         chained_irq_enter(irq_desc_get_chip(desc), desc);
345         while (1) {
346                 u32             status;
347                 int             bit;
348 
349                 /* ack any irqs */
350                 status = readl_relaxed(&g->intstat) & mask;
351                 if (!status)
352                         break;
353                 writel_relaxed(status, &g->intstat);
354 
355                 /* now demux them to the right lowlevel handler */
356 
357                 while (status) {
358                         bit = __ffs(status);
359                         status &= ~BIT(bit);
360                         generic_handle_irq(
361                                 irq_find_mapping(d->irq_domain,
362                                                  d->chip.base + bit));
363                 }
364         }
365         chained_irq_exit(irq_desc_get_chip(desc), desc);
366         /* now it may re-trigger */
367 }
368 
369 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
370 {
371         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
372 
373         if (d->irq_domain)
374                 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
375         else
376                 return -ENXIO;
377 }
378 
379 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
380 {
381         struct davinci_gpio_controller *d = gpiochip_get_data(chip);
382 
383         /*
384          * NOTE:  we assume for now that only irqs in the first gpio_chip
385          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
386          */
387         if (offset < d->gpio_unbanked)
388                 return d->gpio_irq + offset;
389         else
390                 return -ENODEV;
391 }
392 
393 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
394 {
395         struct davinci_gpio_controller *d;
396         struct davinci_gpio_regs __iomem *g;
397         u32 mask;
398 
399         d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
400         g = (struct davinci_gpio_regs __iomem *)d->regs;
401         mask = __gpio_mask(data->irq - d->gpio_irq);
402 
403         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
404                 return -EINVAL;
405 
406         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
407                      ? &g->set_falling : &g->clr_falling);
408         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
409                      ? &g->set_rising : &g->clr_rising);
410 
411         return 0;
412 }
413 
414 static int
415 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
416                      irq_hw_number_t hw)
417 {
418         struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
419 
420         irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
421                                 "davinci_gpio");
422         irq_set_irq_type(irq, IRQ_TYPE_NONE);
423         irq_set_chip_data(irq, (__force void *)g);
424         irq_set_handler_data(irq, (void *)__gpio_mask(hw));
425 
426         return 0;
427 }
428 
429 static const struct irq_domain_ops davinci_gpio_irq_ops = {
430         .map = davinci_gpio_irq_map,
431         .xlate = irq_domain_xlate_onetwocell,
432 };
433 
434 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
435 {
436         static struct irq_chip_type gpio_unbanked;
437 
438         gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
439 
440         return &gpio_unbanked.chip;
441 };
442 
443 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
444 {
445         static struct irq_chip gpio_unbanked;
446 
447         gpio_unbanked = *irq_get_chip(irq);
448         return &gpio_unbanked;
449 };
450 
451 static const struct of_device_id davinci_gpio_ids[];
452 
453 /*
454  * NOTE:  for suspend/resume, probably best to make a platform_device with
455  * suspend_late/resume_resume calls hooking into results of the set_wake()
456  * calls ... so if no gpios are wakeup events the clock can be disabled,
457  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
458  * (dm6446) can be set appropriately for GPIOV33 pins.
459  */
460 
461 static int davinci_gpio_irq_setup(struct platform_device *pdev)
462 {
463         unsigned        gpio, bank;
464         int             irq;
465         struct clk      *clk;
466         u32             binten = 0;
467         unsigned        ngpio, bank_irq;
468         struct device *dev = &pdev->dev;
469         struct resource *res;
470         struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
471         struct davinci_gpio_platform_data *pdata = dev->platform_data;
472         struct davinci_gpio_regs __iomem *g;
473         struct irq_domain       *irq_domain = NULL;
474         const struct of_device_id *match;
475         struct irq_chip *irq_chip;
476         gpio_get_irq_chip_cb_t gpio_get_irq_chip;
477 
478         /*
479          * Use davinci_gpio_get_irq_chip by default to handle non DT cases
480          */
481         gpio_get_irq_chip = davinci_gpio_get_irq_chip;
482         match = of_match_device(of_match_ptr(davinci_gpio_ids),
483                                 dev);
484         if (match)
485                 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
486 
487         ngpio = pdata->ngpio;
488         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
489         if (!res) {
490                 dev_err(dev, "Invalid IRQ resource\n");
491                 return -EBUSY;
492         }
493 
494         bank_irq = res->start;
495 
496         if (!bank_irq) {
497                 dev_err(dev, "Invalid IRQ resource\n");
498                 return -ENODEV;
499         }
500 
501         clk = devm_clk_get(dev, "gpio");
502         if (IS_ERR(clk)) {
503                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
504                        PTR_ERR(clk));
505                 return PTR_ERR(clk);
506         }
507         clk_prepare_enable(clk);
508 
509         if (!pdata->gpio_unbanked) {
510                 irq = irq_alloc_descs(-1, 0, ngpio, 0);
511                 if (irq < 0) {
512                         dev_err(dev, "Couldn't allocate IRQ numbers\n");
513                         return irq;
514                 }
515 
516                 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
517                                                         &davinci_gpio_irq_ops,
518                                                         chips);
519                 if (!irq_domain) {
520                         dev_err(dev, "Couldn't register an IRQ domain\n");
521                         return -ENODEV;
522                 }
523         }
524 
525         /*
526          * Arrange gpio_to_irq() support, handling either direct IRQs or
527          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
528          * IRQs, while the others use banked IRQs, would need some setup
529          * tweaks to recognize hardware which can do that.
530          */
531         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
532                 chips[bank].chip.to_irq = gpio_to_irq_banked;
533                 chips[bank].irq_domain = irq_domain;
534         }
535 
536         /*
537          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
538          * controller only handling trigger modes.  We currently assume no
539          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
540          */
541         if (pdata->gpio_unbanked) {
542                 /* pass "bank 0" GPIO IRQs to AINTC */
543                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
544                 chips[0].gpio_irq = bank_irq;
545                 chips[0].gpio_unbanked = pdata->gpio_unbanked;
546                 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
547 
548                 /* AINTC handles mask/unmask; GPIO handles triggering */
549                 irq = bank_irq;
550                 irq_chip = gpio_get_irq_chip(irq);
551                 irq_chip->name = "GPIO-AINTC";
552                 irq_chip->irq_set_type = gpio_irq_type_unbanked;
553 
554                 /* default trigger: both edges */
555                 g = gpio2regs(0);
556                 writel_relaxed(~0, &g->set_falling);
557                 writel_relaxed(~0, &g->set_rising);
558 
559                 /* set the direct IRQs up to use that irqchip */
560                 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
561                         irq_set_chip(irq, irq_chip);
562                         irq_set_handler_data(irq, &chips[gpio / 32]);
563                         irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
564                 }
565 
566                 goto done;
567         }
568 
569         /*
570          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
571          * then chain through our own handler.
572          */
573         for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
574                 /* disabled by default, enabled only as needed */
575                 g = gpio2regs(gpio);
576                 writel_relaxed(~0, &g->clr_falling);
577                 writel_relaxed(~0, &g->clr_rising);
578 
579                 /*
580                  * Each chip handles 32 gpios, and each irq bank consists of 16
581                  * gpio irqs. Pass the irq bank's corresponding controller to
582                  * the chained irq handler.
583                  */
584                 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
585                                                  &chips[gpio / 32]);
586 
587                 binten |= BIT(bank);
588         }
589 
590 done:
591         /*
592          * BINTEN -- per-bank interrupt enable. genirq would also let these
593          * bits be set/cleared dynamically.
594          */
595         writel_relaxed(binten, gpio_base + BINTEN);
596 
597         return 0;
598 }
599 
600 #if IS_ENABLED(CONFIG_OF)
601 static const struct of_device_id davinci_gpio_ids[] = {
602         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
603         { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
604         { /* sentinel */ },
605 };
606 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
607 #endif
608 
609 static struct platform_driver davinci_gpio_driver = {
610         .probe          = davinci_gpio_probe,
611         .driver         = {
612                 .name           = "davinci_gpio",
613                 .of_match_table = of_match_ptr(davinci_gpio_ids),
614         },
615 };
616 
617 /**
618  * GPIO driver registration needs to be done before machine_init functions
619  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
620  */
621 static int __init davinci_gpio_drv_reg(void)
622 {
623         return platform_driver_register(&davinci_gpio_driver);
624 }
625 postcore_initcall(davinci_gpio_drv_reg);
626 

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