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Linux/drivers/gpio/gpio-davinci.c

  1 /*
  2  * TI DaVinci GPIO Support
  3  *
  4  * Copyright (c) 2006-2007 David Brownell
  5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License as published by
  9  * the Free Software Foundation; either version 2 of the License, or
 10  * (at your option) any later version.
 11  */
 12 #include <linux/gpio.h>
 13 #include <linux/errno.h>
 14 #include <linux/kernel.h>
 15 #include <linux/clk.h>
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/irq.h>
 19 #include <linux/irqdomain.h>
 20 #include <linux/module.h>
 21 #include <linux/of.h>
 22 #include <linux/of_device.h>
 23 #include <linux/platform_device.h>
 24 #include <linux/platform_data/gpio-davinci.h>
 25 #include <linux/irqchip/chained_irq.h>
 26 
 27 struct davinci_gpio_regs {
 28         u32     dir;
 29         u32     out_data;
 30         u32     set_data;
 31         u32     clr_data;
 32         u32     in_data;
 33         u32     set_rising;
 34         u32     clr_rising;
 35         u32     set_falling;
 36         u32     clr_falling;
 37         u32     intstat;
 38 };
 39 
 40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
 41 
 42 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
 43 
 44 #define chip2controller(chip)   \
 45         container_of(chip, struct davinci_gpio_controller, chip)
 46 
 47 static void __iomem *gpio_base;
 48 
 49 static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
 50 {
 51         void __iomem *ptr;
 52 
 53         if (gpio < 32 * 1)
 54                 ptr = gpio_base + 0x10;
 55         else if (gpio < 32 * 2)
 56                 ptr = gpio_base + 0x38;
 57         else if (gpio < 32 * 3)
 58                 ptr = gpio_base + 0x60;
 59         else if (gpio < 32 * 4)
 60                 ptr = gpio_base + 0x88;
 61         else if (gpio < 32 * 5)
 62                 ptr = gpio_base + 0xb0;
 63         else
 64                 ptr = NULL;
 65         return ptr;
 66 }
 67 
 68 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 69 {
 70         struct davinci_gpio_regs __iomem *g;
 71 
 72         g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
 73 
 74         return g;
 75 }
 76 
 77 static int davinci_gpio_irq_setup(struct platform_device *pdev);
 78 
 79 /*--------------------------------------------------------------------------*/
 80 
 81 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
 82 static inline int __davinci_direction(struct gpio_chip *chip,
 83                         unsigned offset, bool out, int value)
 84 {
 85         struct davinci_gpio_controller *d = chip2controller(chip);
 86         struct davinci_gpio_regs __iomem *g = d->regs;
 87         unsigned long flags;
 88         u32 temp;
 89         u32 mask = 1 << offset;
 90 
 91         spin_lock_irqsave(&d->lock, flags);
 92         temp = readl_relaxed(&g->dir);
 93         if (out) {
 94                 temp &= ~mask;
 95                 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
 96         } else {
 97                 temp |= mask;
 98         }
 99         writel_relaxed(temp, &g->dir);
100         spin_unlock_irqrestore(&d->lock, flags);
101 
102         return 0;
103 }
104 
105 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
106 {
107         return __davinci_direction(chip, offset, false, 0);
108 }
109 
110 static int
111 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
112 {
113         return __davinci_direction(chip, offset, true, value);
114 }
115 
116 /*
117  * Read the pin's value (works even if it's set up as output);
118  * returns zero/nonzero.
119  *
120  * Note that changes are synched to the GPIO clock, so reading values back
121  * right after you've set them may give old values.
122  */
123 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
124 {
125         struct davinci_gpio_controller *d = chip2controller(chip);
126         struct davinci_gpio_regs __iomem *g = d->regs;
127 
128         return (1 << offset) & readl_relaxed(&g->in_data);
129 }
130 
131 /*
132  * Assuming the pin is muxed as a gpio output, set its output value.
133  */
134 static void
135 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
136 {
137         struct davinci_gpio_controller *d = chip2controller(chip);
138         struct davinci_gpio_regs __iomem *g = d->regs;
139 
140         writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
141 }
142 
143 static struct davinci_gpio_platform_data *
144 davinci_gpio_get_pdata(struct platform_device *pdev)
145 {
146         struct device_node *dn = pdev->dev.of_node;
147         struct davinci_gpio_platform_data *pdata;
148         int ret;
149         u32 val;
150 
151         if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
152                 return pdev->dev.platform_data;
153 
154         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
155         if (!pdata)
156                 return NULL;
157 
158         ret = of_property_read_u32(dn, "ti,ngpio", &val);
159         if (ret)
160                 goto of_err;
161 
162         pdata->ngpio = val;
163 
164         ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
165         if (ret)
166                 goto of_err;
167 
168         pdata->gpio_unbanked = val;
169 
170         return pdata;
171 
172 of_err:
173         dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
174         return NULL;
175 }
176 
177 #ifdef CONFIG_OF_GPIO
178 static int davinci_gpio_of_xlate(struct gpio_chip *gc,
179                              const struct of_phandle_args *gpiospec,
180                              u32 *flags)
181 {
182         struct davinci_gpio_controller *chips = dev_get_drvdata(gc->dev);
183         struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->dev);
184 
185         if (gpiospec->args[0] > pdata->ngpio)
186                 return -EINVAL;
187 
188         if (gc != &chips[gpiospec->args[0] / 32].chip)
189                 return -EINVAL;
190 
191         if (flags)
192                 *flags = gpiospec->args[1];
193 
194         return gpiospec->args[0] % 32;
195 }
196 #endif
197 
198 static int davinci_gpio_probe(struct platform_device *pdev)
199 {
200         int i, base;
201         unsigned ngpio;
202         struct davinci_gpio_controller *chips;
203         struct davinci_gpio_platform_data *pdata;
204         struct davinci_gpio_regs __iomem *regs;
205         struct device *dev = &pdev->dev;
206         struct resource *res;
207 
208         pdata = davinci_gpio_get_pdata(pdev);
209         if (!pdata) {
210                 dev_err(dev, "No platform data found\n");
211                 return -EINVAL;
212         }
213 
214         dev->platform_data = pdata;
215 
216         /*
217          * The gpio banks conceptually expose a segmented bitmap,
218          * and "ngpio" is one more than the largest zero-based
219          * bit index that's valid.
220          */
221         ngpio = pdata->ngpio;
222         if (ngpio == 0) {
223                 dev_err(dev, "How many GPIOs?\n");
224                 return -EINVAL;
225         }
226 
227         if (WARN_ON(ARCH_NR_GPIOS < ngpio))
228                 ngpio = ARCH_NR_GPIOS;
229 
230         chips = devm_kzalloc(dev,
231                              ngpio * sizeof(struct davinci_gpio_controller),
232                              GFP_KERNEL);
233         if (!chips) {
234                 dev_err(dev, "Memory allocation failed\n");
235                 return -ENOMEM;
236         }
237 
238         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239         if (!res) {
240                 dev_err(dev, "Invalid memory resource\n");
241                 return -EBUSY;
242         }
243 
244         gpio_base = devm_ioremap_resource(dev, res);
245         if (IS_ERR(gpio_base))
246                 return PTR_ERR(gpio_base);
247 
248         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
249                 chips[i].chip.label = "DaVinci";
250 
251                 chips[i].chip.direction_input = davinci_direction_in;
252                 chips[i].chip.get = davinci_gpio_get;
253                 chips[i].chip.direction_output = davinci_direction_out;
254                 chips[i].chip.set = davinci_gpio_set;
255 
256                 chips[i].chip.base = base;
257                 chips[i].chip.ngpio = ngpio - base;
258                 if (chips[i].chip.ngpio > 32)
259                         chips[i].chip.ngpio = 32;
260 
261 #ifdef CONFIG_OF_GPIO
262                 chips[i].chip.of_gpio_n_cells = 2;
263                 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
264                 chips[i].chip.dev = dev;
265                 chips[i].chip.of_node = dev->of_node;
266 #endif
267                 spin_lock_init(&chips[i].lock);
268 
269                 regs = gpio2regs(base);
270                 chips[i].regs = regs;
271                 chips[i].set_data = &regs->set_data;
272                 chips[i].clr_data = &regs->clr_data;
273                 chips[i].in_data = &regs->in_data;
274 
275                 gpiochip_add(&chips[i].chip);
276         }
277 
278         platform_set_drvdata(pdev, chips);
279         davinci_gpio_irq_setup(pdev);
280         return 0;
281 }
282 
283 /*--------------------------------------------------------------------------*/
284 /*
285  * We expect irqs will normally be set up as input pins, but they can also be
286  * used as output pins ... which is convenient for testing.
287  *
288  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
289  * to their GPIOBNK0 irq, with a bit less overhead.
290  *
291  * All those INTC hookups (direct, plus several IRQ banks) can also
292  * serve as EDMA event triggers.
293  */
294 
295 static void gpio_irq_disable(struct irq_data *d)
296 {
297         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
298         u32 mask = (u32) irq_data_get_irq_handler_data(d);
299 
300         writel_relaxed(mask, &g->clr_falling);
301         writel_relaxed(mask, &g->clr_rising);
302 }
303 
304 static void gpio_irq_enable(struct irq_data *d)
305 {
306         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
307         u32 mask = (u32) irq_data_get_irq_handler_data(d);
308         unsigned status = irqd_get_trigger_type(d);
309 
310         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
311         if (!status)
312                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
313 
314         if (status & IRQ_TYPE_EDGE_FALLING)
315                 writel_relaxed(mask, &g->set_falling);
316         if (status & IRQ_TYPE_EDGE_RISING)
317                 writel_relaxed(mask, &g->set_rising);
318 }
319 
320 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
321 {
322         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
323                 return -EINVAL;
324 
325         return 0;
326 }
327 
328 static struct irq_chip gpio_irqchip = {
329         .name           = "GPIO",
330         .irq_enable     = gpio_irq_enable,
331         .irq_disable    = gpio_irq_disable,
332         .irq_set_type   = gpio_irq_type,
333         .flags          = IRQCHIP_SET_TYPE_MASKED,
334 };
335 
336 static void
337 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
338 {
339         struct davinci_gpio_regs __iomem *g;
340         u32 mask = 0xffff;
341         struct davinci_gpio_controller *d;
342 
343         d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
344         g = (struct davinci_gpio_regs __iomem *)d->regs;
345 
346         /* we only care about one bank */
347         if (irq & 1)
348                 mask <<= 16;
349 
350         /* temporarily mask (level sensitive) parent IRQ */
351         chained_irq_enter(irq_desc_get_chip(desc), desc);
352         while (1) {
353                 u32             status;
354                 int             bit;
355 
356                 /* ack any irqs */
357                 status = readl_relaxed(&g->intstat) & mask;
358                 if (!status)
359                         break;
360                 writel_relaxed(status, &g->intstat);
361 
362                 /* now demux them to the right lowlevel handler */
363 
364                 while (status) {
365                         bit = __ffs(status);
366                         status &= ~BIT(bit);
367                         generic_handle_irq(
368                                 irq_find_mapping(d->irq_domain,
369                                                  d->chip.base + bit));
370                 }
371         }
372         chained_irq_exit(irq_desc_get_chip(desc), desc);
373         /* now it may re-trigger */
374 }
375 
376 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
377 {
378         struct davinci_gpio_controller *d = chip2controller(chip);
379 
380         if (d->irq_domain)
381                 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
382         else
383                 return -ENXIO;
384 }
385 
386 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
387 {
388         struct davinci_gpio_controller *d = chip2controller(chip);
389 
390         /*
391          * NOTE:  we assume for now that only irqs in the first gpio_chip
392          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
393          */
394         if (offset < d->gpio_unbanked)
395                 return d->gpio_irq + offset;
396         else
397                 return -ENODEV;
398 }
399 
400 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
401 {
402         struct davinci_gpio_controller *d;
403         struct davinci_gpio_regs __iomem *g;
404         u32 mask;
405 
406         d = (struct davinci_gpio_controller *)data->handler_data;
407         g = (struct davinci_gpio_regs __iomem *)d->regs;
408         mask = __gpio_mask(data->irq - d->gpio_irq);
409 
410         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
411                 return -EINVAL;
412 
413         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
414                      ? &g->set_falling : &g->clr_falling);
415         writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
416                      ? &g->set_rising : &g->clr_rising);
417 
418         return 0;
419 }
420 
421 static int
422 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
423                      irq_hw_number_t hw)
424 {
425         struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
426 
427         irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
428                                 "davinci_gpio");
429         irq_set_irq_type(irq, IRQ_TYPE_NONE);
430         irq_set_chip_data(irq, (__force void *)g);
431         irq_set_handler_data(irq, (void *)__gpio_mask(hw));
432         set_irq_flags(irq, IRQF_VALID);
433 
434         return 0;
435 }
436 
437 static const struct irq_domain_ops davinci_gpio_irq_ops = {
438         .map = davinci_gpio_irq_map,
439         .xlate = irq_domain_xlate_onetwocell,
440 };
441 
442 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
443 {
444         static struct irq_chip_type gpio_unbanked;
445 
446         gpio_unbanked = *container_of(irq_get_chip(irq),
447                                       struct irq_chip_type, chip);
448 
449         return &gpio_unbanked.chip;
450 };
451 
452 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
453 {
454         static struct irq_chip gpio_unbanked;
455 
456         gpio_unbanked = *irq_get_chip(irq);
457         return &gpio_unbanked;
458 };
459 
460 static const struct of_device_id davinci_gpio_ids[];
461 
462 /*
463  * NOTE:  for suspend/resume, probably best to make a platform_device with
464  * suspend_late/resume_resume calls hooking into results of the set_wake()
465  * calls ... so if no gpios are wakeup events the clock can be disabled,
466  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
467  * (dm6446) can be set appropriately for GPIOV33 pins.
468  */
469 
470 static int davinci_gpio_irq_setup(struct platform_device *pdev)
471 {
472         unsigned        gpio, bank;
473         int             irq;
474         struct clk      *clk;
475         u32             binten = 0;
476         unsigned        ngpio, bank_irq;
477         struct device *dev = &pdev->dev;
478         struct resource *res;
479         struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
480         struct davinci_gpio_platform_data *pdata = dev->platform_data;
481         struct davinci_gpio_regs __iomem *g;
482         struct irq_domain       *irq_domain = NULL;
483         const struct of_device_id *match;
484         struct irq_chip *irq_chip;
485         gpio_get_irq_chip_cb_t gpio_get_irq_chip;
486 
487         /*
488          * Use davinci_gpio_get_irq_chip by default to handle non DT cases
489          */
490         gpio_get_irq_chip = davinci_gpio_get_irq_chip;
491         match = of_match_device(of_match_ptr(davinci_gpio_ids),
492                                 dev);
493         if (match)
494                 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
495 
496         ngpio = pdata->ngpio;
497         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
498         if (!res) {
499                 dev_err(dev, "Invalid IRQ resource\n");
500                 return -EBUSY;
501         }
502 
503         bank_irq = res->start;
504 
505         if (!bank_irq) {
506                 dev_err(dev, "Invalid IRQ resource\n");
507                 return -ENODEV;
508         }
509 
510         clk = devm_clk_get(dev, "gpio");
511         if (IS_ERR(clk)) {
512                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
513                        PTR_ERR(clk));
514                 return PTR_ERR(clk);
515         }
516         clk_prepare_enable(clk);
517 
518         if (!pdata->gpio_unbanked) {
519                 irq = irq_alloc_descs(-1, 0, ngpio, 0);
520                 if (irq < 0) {
521                         dev_err(dev, "Couldn't allocate IRQ numbers\n");
522                         return irq;
523                 }
524 
525                 irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
526                                                         &davinci_gpio_irq_ops,
527                                                         chips);
528                 if (!irq_domain) {
529                         dev_err(dev, "Couldn't register an IRQ domain\n");
530                         return -ENODEV;
531                 }
532         }
533 
534         /*
535          * Arrange gpio_to_irq() support, handling either direct IRQs or
536          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
537          * IRQs, while the others use banked IRQs, would need some setup
538          * tweaks to recognize hardware which can do that.
539          */
540         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
541                 chips[bank].chip.to_irq = gpio_to_irq_banked;
542                 chips[bank].irq_domain = irq_domain;
543         }
544 
545         /*
546          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
547          * controller only handling trigger modes.  We currently assume no
548          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
549          */
550         if (pdata->gpio_unbanked) {
551                 /* pass "bank 0" GPIO IRQs to AINTC */
552                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
553                 chips[0].gpio_irq = bank_irq;
554                 chips[0].gpio_unbanked = pdata->gpio_unbanked;
555                 binten = BIT(0);
556 
557                 /* AINTC handles mask/unmask; GPIO handles triggering */
558                 irq = bank_irq;
559                 irq_chip = gpio_get_irq_chip(irq);
560                 irq_chip->name = "GPIO-AINTC";
561                 irq_chip->irq_set_type = gpio_irq_type_unbanked;
562 
563                 /* default trigger: both edges */
564                 g = gpio2regs(0);
565                 writel_relaxed(~0, &g->set_falling);
566                 writel_relaxed(~0, &g->set_rising);
567 
568                 /* set the direct IRQs up to use that irqchip */
569                 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
570                         irq_set_chip(irq, irq_chip);
571                         irq_set_handler_data(irq, &chips[gpio / 32]);
572                         irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
573                 }
574 
575                 goto done;
576         }
577 
578         /*
579          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
580          * then chain through our own handler.
581          */
582         for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
583                 /* disabled by default, enabled only as needed */
584                 g = gpio2regs(gpio);
585                 writel_relaxed(~0, &g->clr_falling);
586                 writel_relaxed(~0, &g->clr_rising);
587 
588                 /* set up all irqs in this bank */
589                 irq_set_chained_handler(bank_irq, gpio_irq_handler);
590 
591                 /*
592                  * Each chip handles 32 gpios, and each irq bank consists of 16
593                  * gpio irqs. Pass the irq bank's corresponding controller to
594                  * the chained irq handler.
595                  */
596                 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
597 
598                 binten |= BIT(bank);
599         }
600 
601 done:
602         /*
603          * BINTEN -- per-bank interrupt enable. genirq would also let these
604          * bits be set/cleared dynamically.
605          */
606         writel_relaxed(binten, gpio_base + BINTEN);
607 
608         return 0;
609 }
610 
611 #if IS_ENABLED(CONFIG_OF)
612 static const struct of_device_id davinci_gpio_ids[] = {
613         { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
614         { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
615         { /* sentinel */ },
616 };
617 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
618 #endif
619 
620 static struct platform_driver davinci_gpio_driver = {
621         .probe          = davinci_gpio_probe,
622         .driver         = {
623                 .name           = "davinci_gpio",
624                 .owner          = THIS_MODULE,
625                 .of_match_table = of_match_ptr(davinci_gpio_ids),
626         },
627 };
628 
629 /**
630  * GPIO driver registration needs to be done before machine_init functions
631  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
632  */
633 static int __init davinci_gpio_drv_reg(void)
634 {
635         return platform_driver_register(&davinci_gpio_driver);
636 }
637 postcore_initcall(davinci_gpio_drv_reg);
638 

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