Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/dma/tegra20-apb-dma.c

  1 /*
  2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
  3  *
  4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
  5  *
  6  * This program is free software; you can redistribute it and/or modify it
  7  * under the terms and conditions of the GNU General Public License,
  8  * version 2, as published by the Free Software Foundation.
  9  *
 10  * This program is distributed in the hope it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  * more details.
 14  *
 15  * You should have received a copy of the GNU General Public License
 16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 17  */
 18 
 19 #include <linux/bitops.h>
 20 #include <linux/clk.h>
 21 #include <linux/delay.h>
 22 #include <linux/dmaengine.h>
 23 #include <linux/dma-mapping.h>
 24 #include <linux/err.h>
 25 #include <linux/init.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/io.h>
 28 #include <linux/mm.h>
 29 #include <linux/module.h>
 30 #include <linux/of.h>
 31 #include <linux/of_device.h>
 32 #include <linux/of_dma.h>
 33 #include <linux/platform_device.h>
 34 #include <linux/pm.h>
 35 #include <linux/pm_runtime.h>
 36 #include <linux/reset.h>
 37 #include <linux/slab.h>
 38 
 39 #include "dmaengine.h"
 40 
 41 #define TEGRA_APBDMA_GENERAL                    0x0
 42 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
 43 
 44 #define TEGRA_APBDMA_CONTROL                    0x010
 45 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
 46 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
 47 
 48 /* CSR register */
 49 #define TEGRA_APBDMA_CHAN_CSR                   0x00
 50 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
 51 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
 52 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
 53 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
 54 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
 55 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
 56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
 57 #define TEGRA_APBDMA_CSR_REQ_SEL_MASK           0x1F
 58 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
 59 
 60 /* STATUS register */
 61 #define TEGRA_APBDMA_CHAN_STATUS                0x004
 62 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
 63 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
 64 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
 65 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
 66 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
 67 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
 68 
 69 #define TEGRA_APBDMA_CHAN_CSRE                  0x00C
 70 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE            (1 << 31)
 71 
 72 /* AHB memory address */
 73 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
 74 
 75 /* AHB sequence register */
 76 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
 77 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
 78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
 79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
 80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
 81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
 82 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
 83 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
 84 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
 85 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
 86 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
 87 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
 88 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
 89 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
 90 
 91 /* APB address */
 92 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
 93 
 94 /* APB sequence register */
 95 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
 96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
 97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
 98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
 99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
100 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
101 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
102 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
103 
104 /* Tegra148 specific registers */
105 #define TEGRA_APBDMA_CHAN_WCOUNT                0x20
106 
107 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER         0x24
108 
109 /*
110  * If any burst is in flight and DMA paused then this is the time to complete
111  * on-flight burst and update DMA status register.
112  */
113 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
114 
115 /* Channel base address offset from APBDMA base address */
116 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
117 
118 #define TEGRA_APBDMA_SLAVE_ID_INVALID   (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)
119 
120 struct tegra_dma;
121 
122 /*
123  * tegra_dma_chip_data Tegra chip specific DMA data
124  * @nr_channels: Number of channels available in the controller.
125  * @channel_reg_size: Channel register size/stride.
126  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
127  * @support_channel_pause: Support channel wise pause of dma.
128  * @support_separate_wcount_reg: Support separate word count register.
129  */
130 struct tegra_dma_chip_data {
131         int nr_channels;
132         int channel_reg_size;
133         int max_dma_count;
134         bool support_channel_pause;
135         bool support_separate_wcount_reg;
136 };
137 
138 /* DMA channel registers */
139 struct tegra_dma_channel_regs {
140         unsigned long   csr;
141         unsigned long   ahb_ptr;
142         unsigned long   apb_ptr;
143         unsigned long   ahb_seq;
144         unsigned long   apb_seq;
145         unsigned long   wcount;
146 };
147 
148 /*
149  * tegra_dma_sg_req: Dma request details to configure hardware. This
150  * contains the details for one transfer to configure DMA hw.
151  * The client's request for data transfer can be broken into multiple
152  * sub-transfer as per requester details and hw support.
153  * This sub transfer get added in the list of transfer and point to Tegra
154  * DMA descriptor which manages the transfer details.
155  */
156 struct tegra_dma_sg_req {
157         struct tegra_dma_channel_regs   ch_regs;
158         int                             req_len;
159         bool                            configured;
160         bool                            last_sg;
161         struct list_head                node;
162         struct tegra_dma_desc           *dma_desc;
163 };
164 
165 /*
166  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
167  * This descriptor keep track of transfer status, callbacks and request
168  * counts etc.
169  */
170 struct tegra_dma_desc {
171         struct dma_async_tx_descriptor  txd;
172         int                             bytes_requested;
173         int                             bytes_transferred;
174         enum dma_status                 dma_status;
175         struct list_head                node;
176         struct list_head                tx_list;
177         struct list_head                cb_node;
178         int                             cb_count;
179 };
180 
181 struct tegra_dma_channel;
182 
183 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
184                                 bool to_terminate);
185 
186 /* tegra_dma_channel: Channel specific information */
187 struct tegra_dma_channel {
188         struct dma_chan         dma_chan;
189         char                    name[30];
190         bool                    config_init;
191         int                     id;
192         int                     irq;
193         void __iomem            *chan_addr;
194         spinlock_t              lock;
195         bool                    busy;
196         struct tegra_dma        *tdma;
197         bool                    cyclic;
198 
199         /* Different lists for managing the requests */
200         struct list_head        free_sg_req;
201         struct list_head        pending_sg_req;
202         struct list_head        free_dma_desc;
203         struct list_head        cb_desc;
204 
205         /* ISR handler and tasklet for bottom half of isr handling */
206         dma_isr_handler         isr_handler;
207         struct tasklet_struct   tasklet;
208 
209         /* Channel-slave specific configuration */
210         unsigned int slave_id;
211         struct dma_slave_config dma_sconfig;
212         struct tegra_dma_channel_regs   channel_reg;
213 };
214 
215 /* tegra_dma: Tegra DMA specific information */
216 struct tegra_dma {
217         struct dma_device               dma_dev;
218         struct device                   *dev;
219         struct clk                      *dma_clk;
220         struct reset_control            *rst;
221         spinlock_t                      global_lock;
222         void __iomem                    *base_addr;
223         const struct tegra_dma_chip_data *chip_data;
224 
225         /*
226          * Counter for managing global pausing of the DMA controller.
227          * Only applicable for devices that don't support individual
228          * channel pausing.
229          */
230         u32                             global_pause_count;
231 
232         /* Some register need to be cache before suspend */
233         u32                             reg_gen;
234 
235         /* Last member of the structure */
236         struct tegra_dma_channel channels[0];
237 };
238 
239 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
240 {
241         writel(val, tdma->base_addr + reg);
242 }
243 
244 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
245 {
246         return readl(tdma->base_addr + reg);
247 }
248 
249 static inline void tdc_write(struct tegra_dma_channel *tdc,
250                 u32 reg, u32 val)
251 {
252         writel(val, tdc->chan_addr + reg);
253 }
254 
255 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
256 {
257         return readl(tdc->chan_addr + reg);
258 }
259 
260 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
261 {
262         return container_of(dc, struct tegra_dma_channel, dma_chan);
263 }
264 
265 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
266                 struct dma_async_tx_descriptor *td)
267 {
268         return container_of(td, struct tegra_dma_desc, txd);
269 }
270 
271 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
272 {
273         return &tdc->dma_chan.dev->device;
274 }
275 
276 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
277 static int tegra_dma_runtime_suspend(struct device *dev);
278 static int tegra_dma_runtime_resume(struct device *dev);
279 
280 /* Get DMA desc from free list, if not there then allocate it.  */
281 static struct tegra_dma_desc *tegra_dma_desc_get(
282                 struct tegra_dma_channel *tdc)
283 {
284         struct tegra_dma_desc *dma_desc;
285         unsigned long flags;
286 
287         spin_lock_irqsave(&tdc->lock, flags);
288 
289         /* Do not allocate if desc are waiting for ack */
290         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
291                 if (async_tx_test_ack(&dma_desc->txd)) {
292                         list_del(&dma_desc->node);
293                         spin_unlock_irqrestore(&tdc->lock, flags);
294                         dma_desc->txd.flags = 0;
295                         return dma_desc;
296                 }
297         }
298 
299         spin_unlock_irqrestore(&tdc->lock, flags);
300 
301         /* Allocate DMA desc */
302         dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
303         if (!dma_desc)
304                 return NULL;
305 
306         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
307         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
308         dma_desc->txd.flags = 0;
309         return dma_desc;
310 }
311 
312 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
313                 struct tegra_dma_desc *dma_desc)
314 {
315         unsigned long flags;
316 
317         spin_lock_irqsave(&tdc->lock, flags);
318         if (!list_empty(&dma_desc->tx_list))
319                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
320         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
321         spin_unlock_irqrestore(&tdc->lock, flags);
322 }
323 
324 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
325                 struct tegra_dma_channel *tdc)
326 {
327         struct tegra_dma_sg_req *sg_req = NULL;
328         unsigned long flags;
329 
330         spin_lock_irqsave(&tdc->lock, flags);
331         if (!list_empty(&tdc->free_sg_req)) {
332                 sg_req = list_first_entry(&tdc->free_sg_req,
333                                         typeof(*sg_req), node);
334                 list_del(&sg_req->node);
335                 spin_unlock_irqrestore(&tdc->lock, flags);
336                 return sg_req;
337         }
338         spin_unlock_irqrestore(&tdc->lock, flags);
339 
340         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
341 
342         return sg_req;
343 }
344 
345 static int tegra_dma_slave_config(struct dma_chan *dc,
346                 struct dma_slave_config *sconfig)
347 {
348         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
349 
350         if (!list_empty(&tdc->pending_sg_req)) {
351                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
352                 return -EBUSY;
353         }
354 
355         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
356         if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) {
357                 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
358                         return -EINVAL;
359                 tdc->slave_id = sconfig->slave_id;
360         }
361         tdc->config_init = true;
362         return 0;
363 }
364 
365 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
366         bool wait_for_burst_complete)
367 {
368         struct tegra_dma *tdma = tdc->tdma;
369 
370         spin_lock(&tdma->global_lock);
371 
372         if (tdc->tdma->global_pause_count == 0) {
373                 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
374                 if (wait_for_burst_complete)
375                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
376         }
377 
378         tdc->tdma->global_pause_count++;
379 
380         spin_unlock(&tdma->global_lock);
381 }
382 
383 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
384 {
385         struct tegra_dma *tdma = tdc->tdma;
386 
387         spin_lock(&tdma->global_lock);
388 
389         if (WARN_ON(tdc->tdma->global_pause_count == 0))
390                 goto out;
391 
392         if (--tdc->tdma->global_pause_count == 0)
393                 tdma_write(tdma, TEGRA_APBDMA_GENERAL,
394                            TEGRA_APBDMA_GENERAL_ENABLE);
395 
396 out:
397         spin_unlock(&tdma->global_lock);
398 }
399 
400 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
401         bool wait_for_burst_complete)
402 {
403         struct tegra_dma *tdma = tdc->tdma;
404 
405         if (tdma->chip_data->support_channel_pause) {
406                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
407                                 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
408                 if (wait_for_burst_complete)
409                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
410         } else {
411                 tegra_dma_global_pause(tdc, wait_for_burst_complete);
412         }
413 }
414 
415 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
416 {
417         struct tegra_dma *tdma = tdc->tdma;
418 
419         if (tdma->chip_data->support_channel_pause) {
420                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
421         } else {
422                 tegra_dma_global_resume(tdc);
423         }
424 }
425 
426 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
427 {
428         u32 csr;
429         u32 status;
430 
431         /* Disable interrupts */
432         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
433         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
434         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
435 
436         /* Disable DMA */
437         csr &= ~TEGRA_APBDMA_CSR_ENB;
438         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
439 
440         /* Clear interrupt status if it is there */
441         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
442         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
443                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
444                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
445         }
446         tdc->busy = false;
447 }
448 
449 static void tegra_dma_start(struct tegra_dma_channel *tdc,
450                 struct tegra_dma_sg_req *sg_req)
451 {
452         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
453 
454         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
455         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
456         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
457         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
458         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
459         if (tdc->tdma->chip_data->support_separate_wcount_reg)
460                 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
461 
462         /* Start DMA */
463         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
464                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
465 }
466 
467 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
468                 struct tegra_dma_sg_req *nsg_req)
469 {
470         unsigned long status;
471 
472         /*
473          * The DMA controller reloads the new configuration for next transfer
474          * after last burst of current transfer completes.
475          * If there is no IEC status then this makes sure that last burst
476          * has not be completed. There may be case that last burst is on
477          * flight and so it can complete but because DMA is paused, it
478          * will not generates interrupt as well as not reload the new
479          * configuration.
480          * If there is already IEC status then interrupt handler need to
481          * load new configuration.
482          */
483         tegra_dma_pause(tdc, false);
484         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
485 
486         /*
487          * If interrupt is pending then do nothing as the ISR will handle
488          * the programing for new request.
489          */
490         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
491                 dev_err(tdc2dev(tdc),
492                         "Skipping new configuration as interrupt is pending\n");
493                 tegra_dma_resume(tdc);
494                 return;
495         }
496 
497         /* Safe to program new configuration */
498         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
499         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
500         if (tdc->tdma->chip_data->support_separate_wcount_reg)
501                 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
502                                                 nsg_req->ch_regs.wcount);
503         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
504                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
505         nsg_req->configured = true;
506 
507         tegra_dma_resume(tdc);
508 }
509 
510 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
511 {
512         struct tegra_dma_sg_req *sg_req;
513 
514         if (list_empty(&tdc->pending_sg_req))
515                 return;
516 
517         sg_req = list_first_entry(&tdc->pending_sg_req,
518                                         typeof(*sg_req), node);
519         tegra_dma_start(tdc, sg_req);
520         sg_req->configured = true;
521         tdc->busy = true;
522 }
523 
524 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
525 {
526         struct tegra_dma_sg_req *hsgreq;
527         struct tegra_dma_sg_req *hnsgreq;
528 
529         if (list_empty(&tdc->pending_sg_req))
530                 return;
531 
532         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
533         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
534                 hnsgreq = list_first_entry(&hsgreq->node,
535                                         typeof(*hnsgreq), node);
536                 tegra_dma_configure_for_next(tdc, hnsgreq);
537         }
538 }
539 
540 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
541         struct tegra_dma_sg_req *sg_req, unsigned long status)
542 {
543         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
544 }
545 
546 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
547 {
548         struct tegra_dma_sg_req *sgreq;
549         struct tegra_dma_desc *dma_desc;
550 
551         while (!list_empty(&tdc->pending_sg_req)) {
552                 sgreq = list_first_entry(&tdc->pending_sg_req,
553                                                 typeof(*sgreq), node);
554                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
555                 if (sgreq->last_sg) {
556                         dma_desc = sgreq->dma_desc;
557                         dma_desc->dma_status = DMA_ERROR;
558                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
559 
560                         /* Add in cb list if it is not there. */
561                         if (!dma_desc->cb_count)
562                                 list_add_tail(&dma_desc->cb_node,
563                                                         &tdc->cb_desc);
564                         dma_desc->cb_count++;
565                 }
566         }
567         tdc->isr_handler = NULL;
568 }
569 
570 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
571                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
572 {
573         struct tegra_dma_sg_req *hsgreq = NULL;
574 
575         if (list_empty(&tdc->pending_sg_req)) {
576                 dev_err(tdc2dev(tdc), "Dma is running without req\n");
577                 tegra_dma_stop(tdc);
578                 return false;
579         }
580 
581         /*
582          * Check that head req on list should be in flight.
583          * If it is not in flight then abort transfer as
584          * looping of transfer can not continue.
585          */
586         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
587         if (!hsgreq->configured) {
588                 tegra_dma_stop(tdc);
589                 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
590                 tegra_dma_abort_all(tdc);
591                 return false;
592         }
593 
594         /* Configure next request */
595         if (!to_terminate)
596                 tdc_configure_next_head_desc(tdc);
597         return true;
598 }
599 
600 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
601         bool to_terminate)
602 {
603         struct tegra_dma_sg_req *sgreq;
604         struct tegra_dma_desc *dma_desc;
605 
606         tdc->busy = false;
607         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
608         dma_desc = sgreq->dma_desc;
609         dma_desc->bytes_transferred += sgreq->req_len;
610 
611         list_del(&sgreq->node);
612         if (sgreq->last_sg) {
613                 dma_desc->dma_status = DMA_COMPLETE;
614                 dma_cookie_complete(&dma_desc->txd);
615                 if (!dma_desc->cb_count)
616                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
617                 dma_desc->cb_count++;
618                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
619         }
620         list_add_tail(&sgreq->node, &tdc->free_sg_req);
621 
622         /* Do not start DMA if it is going to be terminate */
623         if (to_terminate || list_empty(&tdc->pending_sg_req))
624                 return;
625 
626         tdc_start_head_req(tdc);
627 }
628 
629 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
630                 bool to_terminate)
631 {
632         struct tegra_dma_sg_req *sgreq;
633         struct tegra_dma_desc *dma_desc;
634         bool st;
635 
636         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
637         dma_desc = sgreq->dma_desc;
638         dma_desc->bytes_transferred += sgreq->req_len;
639 
640         /* Callback need to be call */
641         if (!dma_desc->cb_count)
642                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
643         dma_desc->cb_count++;
644 
645         /* If not last req then put at end of pending list */
646         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
647                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
648                 sgreq->configured = false;
649                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
650                 if (!st)
651                         dma_desc->dma_status = DMA_ERROR;
652         }
653 }
654 
655 static void tegra_dma_tasklet(unsigned long data)
656 {
657         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
658         struct dmaengine_desc_callback cb;
659         struct tegra_dma_desc *dma_desc;
660         unsigned long flags;
661         int cb_count;
662 
663         spin_lock_irqsave(&tdc->lock, flags);
664         while (!list_empty(&tdc->cb_desc)) {
665                 dma_desc  = list_first_entry(&tdc->cb_desc,
666                                         typeof(*dma_desc), cb_node);
667                 list_del(&dma_desc->cb_node);
668                 dmaengine_desc_get_callback(&dma_desc->txd, &cb);
669                 cb_count = dma_desc->cb_count;
670                 dma_desc->cb_count = 0;
671                 spin_unlock_irqrestore(&tdc->lock, flags);
672                 while (cb_count--)
673                         dmaengine_desc_callback_invoke(&cb, NULL);
674                 spin_lock_irqsave(&tdc->lock, flags);
675         }
676         spin_unlock_irqrestore(&tdc->lock, flags);
677 }
678 
679 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
680 {
681         struct tegra_dma_channel *tdc = dev_id;
682         unsigned long status;
683         unsigned long flags;
684 
685         spin_lock_irqsave(&tdc->lock, flags);
686 
687         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
688         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
689                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
690                 tdc->isr_handler(tdc, false);
691                 tasklet_schedule(&tdc->tasklet);
692                 spin_unlock_irqrestore(&tdc->lock, flags);
693                 return IRQ_HANDLED;
694         }
695 
696         spin_unlock_irqrestore(&tdc->lock, flags);
697         dev_info(tdc2dev(tdc),
698                 "Interrupt already served status 0x%08lx\n", status);
699         return IRQ_NONE;
700 }
701 
702 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
703 {
704         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
705         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
706         unsigned long flags;
707         dma_cookie_t cookie;
708 
709         spin_lock_irqsave(&tdc->lock, flags);
710         dma_desc->dma_status = DMA_IN_PROGRESS;
711         cookie = dma_cookie_assign(&dma_desc->txd);
712         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
713         spin_unlock_irqrestore(&tdc->lock, flags);
714         return cookie;
715 }
716 
717 static void tegra_dma_issue_pending(struct dma_chan *dc)
718 {
719         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
720         unsigned long flags;
721 
722         spin_lock_irqsave(&tdc->lock, flags);
723         if (list_empty(&tdc->pending_sg_req)) {
724                 dev_err(tdc2dev(tdc), "No DMA request\n");
725                 goto end;
726         }
727         if (!tdc->busy) {
728                 tdc_start_head_req(tdc);
729 
730                 /* Continuous single mode: Configure next req */
731                 if (tdc->cyclic) {
732                         /*
733                          * Wait for 1 burst time for configure DMA for
734                          * next transfer.
735                          */
736                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
737                         tdc_configure_next_head_desc(tdc);
738                 }
739         }
740 end:
741         spin_unlock_irqrestore(&tdc->lock, flags);
742 }
743 
744 static int tegra_dma_terminate_all(struct dma_chan *dc)
745 {
746         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
747         struct tegra_dma_sg_req *sgreq;
748         struct tegra_dma_desc *dma_desc;
749         unsigned long flags;
750         unsigned long status;
751         unsigned long wcount;
752         bool was_busy;
753 
754         spin_lock_irqsave(&tdc->lock, flags);
755         if (list_empty(&tdc->pending_sg_req)) {
756                 spin_unlock_irqrestore(&tdc->lock, flags);
757                 return 0;
758         }
759 
760         if (!tdc->busy)
761                 goto skip_dma_stop;
762 
763         /* Pause DMA before checking the queue status */
764         tegra_dma_pause(tdc, true);
765 
766         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
767         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
768                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
769                 tdc->isr_handler(tdc, true);
770                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
771         }
772         if (tdc->tdma->chip_data->support_separate_wcount_reg)
773                 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
774         else
775                 wcount = status;
776 
777         was_busy = tdc->busy;
778         tegra_dma_stop(tdc);
779 
780         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
781                 sgreq = list_first_entry(&tdc->pending_sg_req,
782                                         typeof(*sgreq), node);
783                 sgreq->dma_desc->bytes_transferred +=
784                                 get_current_xferred_count(tdc, sgreq, wcount);
785         }
786         tegra_dma_resume(tdc);
787 
788 skip_dma_stop:
789         tegra_dma_abort_all(tdc);
790 
791         while (!list_empty(&tdc->cb_desc)) {
792                 dma_desc  = list_first_entry(&tdc->cb_desc,
793                                         typeof(*dma_desc), cb_node);
794                 list_del(&dma_desc->cb_node);
795                 dma_desc->cb_count = 0;
796         }
797         spin_unlock_irqrestore(&tdc->lock, flags);
798         return 0;
799 }
800 
801 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
802         dma_cookie_t cookie, struct dma_tx_state *txstate)
803 {
804         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
805         struct tegra_dma_desc *dma_desc;
806         struct tegra_dma_sg_req *sg_req;
807         enum dma_status ret;
808         unsigned long flags;
809         unsigned int residual;
810 
811         ret = dma_cookie_status(dc, cookie, txstate);
812         if (ret == DMA_COMPLETE)
813                 return ret;
814 
815         spin_lock_irqsave(&tdc->lock, flags);
816 
817         /* Check on wait_ack desc status */
818         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
819                 if (dma_desc->txd.cookie == cookie) {
820                         ret = dma_desc->dma_status;
821                         goto found;
822                 }
823         }
824 
825         /* Check in pending list */
826         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
827                 dma_desc = sg_req->dma_desc;
828                 if (dma_desc->txd.cookie == cookie) {
829                         ret = dma_desc->dma_status;
830                         goto found;
831                 }
832         }
833 
834         dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie);
835         dma_desc = NULL;
836 
837 found:
838         if (dma_desc && txstate) {
839                 residual = dma_desc->bytes_requested -
840                            (dma_desc->bytes_transferred %
841                             dma_desc->bytes_requested);
842                 dma_set_residue(txstate, residual);
843         }
844 
845         spin_unlock_irqrestore(&tdc->lock, flags);
846         return ret;
847 }
848 
849 static inline int get_bus_width(struct tegra_dma_channel *tdc,
850                 enum dma_slave_buswidth slave_bw)
851 {
852         switch (slave_bw) {
853         case DMA_SLAVE_BUSWIDTH_1_BYTE:
854                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
855         case DMA_SLAVE_BUSWIDTH_2_BYTES:
856                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
857         case DMA_SLAVE_BUSWIDTH_4_BYTES:
858                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
859         case DMA_SLAVE_BUSWIDTH_8_BYTES:
860                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
861         default:
862                 dev_warn(tdc2dev(tdc),
863                         "slave bw is not supported, using 32bits\n");
864                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
865         }
866 }
867 
868 static inline int get_burst_size(struct tegra_dma_channel *tdc,
869         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
870 {
871         int burst_byte;
872         int burst_ahb_width;
873 
874         /*
875          * burst_size from client is in terms of the bus_width.
876          * convert them into AHB memory width which is 4 byte.
877          */
878         burst_byte = burst_size * slave_bw;
879         burst_ahb_width = burst_byte / 4;
880 
881         /* If burst size is 0 then calculate the burst size based on length */
882         if (!burst_ahb_width) {
883                 if (len & 0xF)
884                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
885                 else if ((len >> 4) & 0x1)
886                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
887                 else
888                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
889         }
890         if (burst_ahb_width < 4)
891                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
892         else if (burst_ahb_width < 8)
893                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
894         else
895                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
896 }
897 
898 static int get_transfer_param(struct tegra_dma_channel *tdc,
899         enum dma_transfer_direction direction, unsigned long *apb_addr,
900         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
901         enum dma_slave_buswidth *slave_bw)
902 {
903         switch (direction) {
904         case DMA_MEM_TO_DEV:
905                 *apb_addr = tdc->dma_sconfig.dst_addr;
906                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
907                 *burst_size = tdc->dma_sconfig.dst_maxburst;
908                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
909                 *csr = TEGRA_APBDMA_CSR_DIR;
910                 return 0;
911 
912         case DMA_DEV_TO_MEM:
913                 *apb_addr = tdc->dma_sconfig.src_addr;
914                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
915                 *burst_size = tdc->dma_sconfig.src_maxburst;
916                 *slave_bw = tdc->dma_sconfig.src_addr_width;
917                 *csr = 0;
918                 return 0;
919 
920         default:
921                 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
922                 return -EINVAL;
923         }
924         return -EINVAL;
925 }
926 
927 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
928         struct tegra_dma_channel_regs *ch_regs, u32 len)
929 {
930         u32 len_field = (len - 4) & 0xFFFC;
931 
932         if (tdc->tdma->chip_data->support_separate_wcount_reg)
933                 ch_regs->wcount = len_field;
934         else
935                 ch_regs->csr |= len_field;
936 }
937 
938 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
939         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
940         enum dma_transfer_direction direction, unsigned long flags,
941         void *context)
942 {
943         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
944         struct tegra_dma_desc *dma_desc;
945         unsigned int i;
946         struct scatterlist *sg;
947         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
948         struct list_head req_list;
949         struct tegra_dma_sg_req  *sg_req = NULL;
950         u32 burst_size;
951         enum dma_slave_buswidth slave_bw;
952 
953         if (!tdc->config_init) {
954                 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
955                 return NULL;
956         }
957         if (sg_len < 1) {
958                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
959                 return NULL;
960         }
961 
962         if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
963                                 &burst_size, &slave_bw) < 0)
964                 return NULL;
965 
966         INIT_LIST_HEAD(&req_list);
967 
968         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
969         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
970                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
971         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
972 
973         csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
974         csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
975         if (flags & DMA_PREP_INTERRUPT)
976                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
977 
978         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
979 
980         dma_desc = tegra_dma_desc_get(tdc);
981         if (!dma_desc) {
982                 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
983                 return NULL;
984         }
985         INIT_LIST_HEAD(&dma_desc->tx_list);
986         INIT_LIST_HEAD(&dma_desc->cb_node);
987         dma_desc->cb_count = 0;
988         dma_desc->bytes_requested = 0;
989         dma_desc->bytes_transferred = 0;
990         dma_desc->dma_status = DMA_IN_PROGRESS;
991 
992         /* Make transfer requests */
993         for_each_sg(sgl, sg, sg_len, i) {
994                 u32 len, mem;
995 
996                 mem = sg_dma_address(sg);
997                 len = sg_dma_len(sg);
998 
999                 if ((len & 3) || (mem & 3) ||
1000                                 (len > tdc->tdma->chip_data->max_dma_count)) {
1001                         dev_err(tdc2dev(tdc),
1002                                 "Dma length/memory address is not supported\n");
1003                         tegra_dma_desc_put(tdc, dma_desc);
1004                         return NULL;
1005                 }
1006 
1007                 sg_req = tegra_dma_sg_req_get(tdc);
1008                 if (!sg_req) {
1009                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1010                         tegra_dma_desc_put(tdc, dma_desc);
1011                         return NULL;
1012                 }
1013 
1014                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1015                 dma_desc->bytes_requested += len;
1016 
1017                 sg_req->ch_regs.apb_ptr = apb_ptr;
1018                 sg_req->ch_regs.ahb_ptr = mem;
1019                 sg_req->ch_regs.csr = csr;
1020                 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1021                 sg_req->ch_regs.apb_seq = apb_seq;
1022                 sg_req->ch_regs.ahb_seq = ahb_seq;
1023                 sg_req->configured = false;
1024                 sg_req->last_sg = false;
1025                 sg_req->dma_desc = dma_desc;
1026                 sg_req->req_len = len;
1027 
1028                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1029         }
1030         sg_req->last_sg = true;
1031         if (flags & DMA_CTRL_ACK)
1032                 dma_desc->txd.flags = DMA_CTRL_ACK;
1033 
1034         /*
1035          * Make sure that mode should not be conflicting with currently
1036          * configured mode.
1037          */
1038         if (!tdc->isr_handler) {
1039                 tdc->isr_handler = handle_once_dma_done;
1040                 tdc->cyclic = false;
1041         } else {
1042                 if (tdc->cyclic) {
1043                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1044                         tegra_dma_desc_put(tdc, dma_desc);
1045                         return NULL;
1046                 }
1047         }
1048 
1049         return &dma_desc->txd;
1050 }
1051 
1052 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1053         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1054         size_t period_len, enum dma_transfer_direction direction,
1055         unsigned long flags)
1056 {
1057         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1058         struct tegra_dma_desc *dma_desc = NULL;
1059         struct tegra_dma_sg_req *sg_req = NULL;
1060         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1061         int len;
1062         size_t remain_len;
1063         dma_addr_t mem = buf_addr;
1064         u32 burst_size;
1065         enum dma_slave_buswidth slave_bw;
1066 
1067         if (!buf_len || !period_len) {
1068                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1069                 return NULL;
1070         }
1071 
1072         if (!tdc->config_init) {
1073                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1074                 return NULL;
1075         }
1076 
1077         /*
1078          * We allow to take more number of requests till DMA is
1079          * not started. The driver will loop over all requests.
1080          * Once DMA is started then new requests can be queued only after
1081          * terminating the DMA.
1082          */
1083         if (tdc->busy) {
1084                 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1085                 return NULL;
1086         }
1087 
1088         /*
1089          * We only support cycle transfer when buf_len is multiple of
1090          * period_len.
1091          */
1092         if (buf_len % period_len) {
1093                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1094                 return NULL;
1095         }
1096 
1097         len = period_len;
1098         if ((len & 3) || (buf_addr & 3) ||
1099                         (len > tdc->tdma->chip_data->max_dma_count)) {
1100                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1101                 return NULL;
1102         }
1103 
1104         if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1105                                 &burst_size, &slave_bw) < 0)
1106                 return NULL;
1107 
1108         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1109         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1110                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1111         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1112 
1113         csr |= TEGRA_APBDMA_CSR_FLOW;
1114         if (flags & DMA_PREP_INTERRUPT)
1115                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1116         csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1117 
1118         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1119 
1120         dma_desc = tegra_dma_desc_get(tdc);
1121         if (!dma_desc) {
1122                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1123                 return NULL;
1124         }
1125 
1126         INIT_LIST_HEAD(&dma_desc->tx_list);
1127         INIT_LIST_HEAD(&dma_desc->cb_node);
1128         dma_desc->cb_count = 0;
1129 
1130         dma_desc->bytes_transferred = 0;
1131         dma_desc->bytes_requested = buf_len;
1132         remain_len = buf_len;
1133 
1134         /* Split transfer equal to period size */
1135         while (remain_len) {
1136                 sg_req = tegra_dma_sg_req_get(tdc);
1137                 if (!sg_req) {
1138                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1139                         tegra_dma_desc_put(tdc, dma_desc);
1140                         return NULL;
1141                 }
1142 
1143                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1144                 sg_req->ch_regs.apb_ptr = apb_ptr;
1145                 sg_req->ch_regs.ahb_ptr = mem;
1146                 sg_req->ch_regs.csr = csr;
1147                 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1148                 sg_req->ch_regs.apb_seq = apb_seq;
1149                 sg_req->ch_regs.ahb_seq = ahb_seq;
1150                 sg_req->configured = false;
1151                 sg_req->last_sg = false;
1152                 sg_req->dma_desc = dma_desc;
1153                 sg_req->req_len = len;
1154 
1155                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1156                 remain_len -= len;
1157                 mem += len;
1158         }
1159         sg_req->last_sg = true;
1160         if (flags & DMA_CTRL_ACK)
1161                 dma_desc->txd.flags = DMA_CTRL_ACK;
1162 
1163         /*
1164          * Make sure that mode should not be conflicting with currently
1165          * configured mode.
1166          */
1167         if (!tdc->isr_handler) {
1168                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1169                 tdc->cyclic = true;
1170         } else {
1171                 if (!tdc->cyclic) {
1172                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1173                         tegra_dma_desc_put(tdc, dma_desc);
1174                         return NULL;
1175                 }
1176         }
1177 
1178         return &dma_desc->txd;
1179 }
1180 
1181 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1182 {
1183         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1184         struct tegra_dma *tdma = tdc->tdma;
1185         int ret;
1186 
1187         dma_cookie_init(&tdc->dma_chan);
1188         tdc->config_init = false;
1189 
1190         ret = pm_runtime_get_sync(tdma->dev);
1191         if (ret < 0)
1192                 return ret;
1193 
1194         return 0;
1195 }
1196 
1197 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1198 {
1199         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1200         struct tegra_dma *tdma = tdc->tdma;
1201         struct tegra_dma_desc *dma_desc;
1202         struct tegra_dma_sg_req *sg_req;
1203         struct list_head dma_desc_list;
1204         struct list_head sg_req_list;
1205         unsigned long flags;
1206 
1207         INIT_LIST_HEAD(&dma_desc_list);
1208         INIT_LIST_HEAD(&sg_req_list);
1209 
1210         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1211 
1212         if (tdc->busy)
1213                 tegra_dma_terminate_all(dc);
1214 
1215         spin_lock_irqsave(&tdc->lock, flags);
1216         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1217         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1218         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1219         INIT_LIST_HEAD(&tdc->cb_desc);
1220         tdc->config_init = false;
1221         tdc->isr_handler = NULL;
1222         spin_unlock_irqrestore(&tdc->lock, flags);
1223 
1224         while (!list_empty(&dma_desc_list)) {
1225                 dma_desc = list_first_entry(&dma_desc_list,
1226                                         typeof(*dma_desc), node);
1227                 list_del(&dma_desc->node);
1228                 kfree(dma_desc);
1229         }
1230 
1231         while (!list_empty(&sg_req_list)) {
1232                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1233                 list_del(&sg_req->node);
1234                 kfree(sg_req);
1235         }
1236         pm_runtime_put(tdma->dev);
1237 
1238         tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1239 }
1240 
1241 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1242                                            struct of_dma *ofdma)
1243 {
1244         struct tegra_dma *tdma = ofdma->of_dma_data;
1245         struct dma_chan *chan;
1246         struct tegra_dma_channel *tdc;
1247 
1248         if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {
1249                 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
1250                 return NULL;
1251         }
1252 
1253         chan = dma_get_any_slave_channel(&tdma->dma_dev);
1254         if (!chan)
1255                 return NULL;
1256 
1257         tdc = to_tegra_dma_chan(chan);
1258         tdc->slave_id = dma_spec->args[0];
1259 
1260         return chan;
1261 }
1262 
1263 /* Tegra20 specific DMA controller information */
1264 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1265         .nr_channels            = 16,
1266         .channel_reg_size       = 0x20,
1267         .max_dma_count          = 1024UL * 64,
1268         .support_channel_pause  = false,
1269         .support_separate_wcount_reg = false,
1270 };
1271 
1272 /* Tegra30 specific DMA controller information */
1273 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1274         .nr_channels            = 32,
1275         .channel_reg_size       = 0x20,
1276         .max_dma_count          = 1024UL * 64,
1277         .support_channel_pause  = false,
1278         .support_separate_wcount_reg = false,
1279 };
1280 
1281 /* Tegra114 specific DMA controller information */
1282 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1283         .nr_channels            = 32,
1284         .channel_reg_size       = 0x20,
1285         .max_dma_count          = 1024UL * 64,
1286         .support_channel_pause  = true,
1287         .support_separate_wcount_reg = false,
1288 };
1289 
1290 /* Tegra148 specific DMA controller information */
1291 static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1292         .nr_channels            = 32,
1293         .channel_reg_size       = 0x40,
1294         .max_dma_count          = 1024UL * 64,
1295         .support_channel_pause  = true,
1296         .support_separate_wcount_reg = true,
1297 };
1298 
1299 static int tegra_dma_probe(struct platform_device *pdev)
1300 {
1301         struct resource *res;
1302         struct tegra_dma *tdma;
1303         int ret;
1304         int i;
1305         const struct tegra_dma_chip_data *cdata;
1306 
1307         cdata = of_device_get_match_data(&pdev->dev);
1308         if (!cdata) {
1309                 dev_err(&pdev->dev, "Error: No device match data found\n");
1310                 return -ENODEV;
1311         }
1312 
1313         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1314                         sizeof(struct tegra_dma_channel), GFP_KERNEL);
1315         if (!tdma)
1316                 return -ENOMEM;
1317 
1318         tdma->dev = &pdev->dev;
1319         tdma->chip_data = cdata;
1320         platform_set_drvdata(pdev, tdma);
1321 
1322         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1323         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1324         if (IS_ERR(tdma->base_addr))
1325                 return PTR_ERR(tdma->base_addr);
1326 
1327         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1328         if (IS_ERR(tdma->dma_clk)) {
1329                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1330                 return PTR_ERR(tdma->dma_clk);
1331         }
1332 
1333         tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1334         if (IS_ERR(tdma->rst)) {
1335                 dev_err(&pdev->dev, "Error: Missing reset\n");
1336                 return PTR_ERR(tdma->rst);
1337         }
1338 
1339         spin_lock_init(&tdma->global_lock);
1340 
1341         pm_runtime_enable(&pdev->dev);
1342         if (!pm_runtime_enabled(&pdev->dev))
1343                 ret = tegra_dma_runtime_resume(&pdev->dev);
1344         else
1345                 ret = pm_runtime_get_sync(&pdev->dev);
1346 
1347         if (ret < 0) {
1348                 pm_runtime_disable(&pdev->dev);
1349                 return ret;
1350         }
1351 
1352         /* Reset DMA controller */
1353         reset_control_assert(tdma->rst);
1354         udelay(2);
1355         reset_control_deassert(tdma->rst);
1356 
1357         /* Enable global DMA registers */
1358         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1359         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1360         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1361 
1362         pm_runtime_put(&pdev->dev);
1363 
1364         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1365         for (i = 0; i < cdata->nr_channels; i++) {
1366                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1367 
1368                 tdc->chan_addr = tdma->base_addr +
1369                                  TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1370                                  (i * cdata->channel_reg_size);
1371 
1372                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1373                 if (!res) {
1374                         ret = -EINVAL;
1375                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1376                         goto err_irq;
1377                 }
1378                 tdc->irq = res->start;
1379                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1380                 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);
1381                 if (ret) {
1382                         dev_err(&pdev->dev,
1383                                 "request_irq failed with err %d channel %d\n",
1384                                 ret, i);
1385                         goto err_irq;
1386                 }
1387 
1388                 tdc->dma_chan.device = &tdma->dma_dev;
1389                 dma_cookie_init(&tdc->dma_chan);
1390                 list_add_tail(&tdc->dma_chan.device_node,
1391                                 &tdma->dma_dev.channels);
1392                 tdc->tdma = tdma;
1393                 tdc->id = i;
1394                 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1395 
1396                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1397                                 (unsigned long)tdc);
1398                 spin_lock_init(&tdc->lock);
1399 
1400                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1401                 INIT_LIST_HEAD(&tdc->free_sg_req);
1402                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1403                 INIT_LIST_HEAD(&tdc->cb_desc);
1404         }
1405 
1406         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1407         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1408         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1409 
1410         tdma->global_pause_count = 0;
1411         tdma->dma_dev.dev = &pdev->dev;
1412         tdma->dma_dev.device_alloc_chan_resources =
1413                                         tegra_dma_alloc_chan_resources;
1414         tdma->dma_dev.device_free_chan_resources =
1415                                         tegra_dma_free_chan_resources;
1416         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1417         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1418         tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1419                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1420                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1421                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1422         tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1423                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1424                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1425                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1426         tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1427         /*
1428          * XXX The hardware appears to support
1429          * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1430          * only used by this driver during tegra_dma_terminate_all()
1431          */
1432         tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1433         tdma->dma_dev.device_config = tegra_dma_slave_config;
1434         tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1435         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1436         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1437 
1438         ret = dma_async_device_register(&tdma->dma_dev);
1439         if (ret < 0) {
1440                 dev_err(&pdev->dev,
1441                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1442                 goto err_irq;
1443         }
1444 
1445         ret = of_dma_controller_register(pdev->dev.of_node,
1446                                          tegra_dma_of_xlate, tdma);
1447         if (ret < 0) {
1448                 dev_err(&pdev->dev,
1449                         "Tegra20 APB DMA OF registration failed %d\n", ret);
1450                 goto err_unregister_dma_dev;
1451         }
1452 
1453         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1454                         cdata->nr_channels);
1455         return 0;
1456 
1457 err_unregister_dma_dev:
1458         dma_async_device_unregister(&tdma->dma_dev);
1459 err_irq:
1460         while (--i >= 0) {
1461                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1462 
1463                 free_irq(tdc->irq, tdc);
1464                 tasklet_kill(&tdc->tasklet);
1465         }
1466 
1467         pm_runtime_disable(&pdev->dev);
1468         if (!pm_runtime_status_suspended(&pdev->dev))
1469                 tegra_dma_runtime_suspend(&pdev->dev);
1470         return ret;
1471 }
1472 
1473 static int tegra_dma_remove(struct platform_device *pdev)
1474 {
1475         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1476         int i;
1477         struct tegra_dma_channel *tdc;
1478 
1479         dma_async_device_unregister(&tdma->dma_dev);
1480 
1481         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1482                 tdc = &tdma->channels[i];
1483                 free_irq(tdc->irq, tdc);
1484                 tasklet_kill(&tdc->tasklet);
1485         }
1486 
1487         pm_runtime_disable(&pdev->dev);
1488         if (!pm_runtime_status_suspended(&pdev->dev))
1489                 tegra_dma_runtime_suspend(&pdev->dev);
1490 
1491         return 0;
1492 }
1493 
1494 static int tegra_dma_runtime_suspend(struct device *dev)
1495 {
1496         struct tegra_dma *tdma = dev_get_drvdata(dev);
1497 
1498         clk_disable_unprepare(tdma->dma_clk);
1499         return 0;
1500 }
1501 
1502 static int tegra_dma_runtime_resume(struct device *dev)
1503 {
1504         struct tegra_dma *tdma = dev_get_drvdata(dev);
1505         int ret;
1506 
1507         ret = clk_prepare_enable(tdma->dma_clk);
1508         if (ret < 0) {
1509                 dev_err(dev, "clk_enable failed: %d\n", ret);
1510                 return ret;
1511         }
1512         return 0;
1513 }
1514 
1515 #ifdef CONFIG_PM_SLEEP
1516 static int tegra_dma_pm_suspend(struct device *dev)
1517 {
1518         struct tegra_dma *tdma = dev_get_drvdata(dev);
1519         int i;
1520         int ret;
1521 
1522         /* Enable clock before accessing register */
1523         ret = pm_runtime_get_sync(dev);
1524         if (ret < 0)
1525                 return ret;
1526 
1527         tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1528         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1529                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1530                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1531 
1532                 /* Only save the state of DMA channels that are in use */
1533                 if (!tdc->config_init)
1534                         continue;
1535 
1536                 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1537                 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1538                 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1539                 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1540                 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1541                 if (tdma->chip_data->support_separate_wcount_reg)
1542                         ch_reg->wcount = tdc_read(tdc,
1543                                                   TEGRA_APBDMA_CHAN_WCOUNT);
1544         }
1545 
1546         /* Disable clock */
1547         pm_runtime_put(dev);
1548         return 0;
1549 }
1550 
1551 static int tegra_dma_pm_resume(struct device *dev)
1552 {
1553         struct tegra_dma *tdma = dev_get_drvdata(dev);
1554         int i;
1555         int ret;
1556 
1557         /* Enable clock before accessing register */
1558         ret = pm_runtime_get_sync(dev);
1559         if (ret < 0)
1560                 return ret;
1561 
1562         tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1563         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1564         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1565 
1566         for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1567                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1568                 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1569 
1570                 /* Only restore the state of DMA channels that are in use */
1571                 if (!tdc->config_init)
1572                         continue;
1573 
1574                 if (tdma->chip_data->support_separate_wcount_reg)
1575                         tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
1576                                   ch_reg->wcount);
1577                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1578                 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1579                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1580                 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1581                 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1582                         (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1583         }
1584 
1585         /* Disable clock */
1586         pm_runtime_put(dev);
1587         return 0;
1588 }
1589 #endif
1590 
1591 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1592         SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
1593                            NULL)
1594         SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
1595 };
1596 
1597 static const struct of_device_id tegra_dma_of_match[] = {
1598         {
1599                 .compatible = "nvidia,tegra148-apbdma",
1600                 .data = &tegra148_dma_chip_data,
1601         }, {
1602                 .compatible = "nvidia,tegra114-apbdma",
1603                 .data = &tegra114_dma_chip_data,
1604         }, {
1605                 .compatible = "nvidia,tegra30-apbdma",
1606                 .data = &tegra30_dma_chip_data,
1607         }, {
1608                 .compatible = "nvidia,tegra20-apbdma",
1609                 .data = &tegra20_dma_chip_data,
1610         }, {
1611         },
1612 };
1613 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1614 
1615 static struct platform_driver tegra_dmac_driver = {
1616         .driver = {
1617                 .name   = "tegra-apbdma",
1618                 .pm     = &tegra_dma_dev_pm_ops,
1619                 .of_match_table = tegra_dma_of_match,
1620         },
1621         .probe          = tegra_dma_probe,
1622         .remove         = tegra_dma_remove,
1623 };
1624 
1625 module_platform_driver(tegra_dmac_driver);
1626 
1627 MODULE_ALIAS("platform:tegra20-apbdma");
1628 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1629 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1630 MODULE_LICENSE("GPL v2");
1631 

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