Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/dma/ste_dma40.c

  1 /*
  2  * Copyright (C) Ericsson AB 2007-2008
  3  * Copyright (C) ST-Ericsson SA 2008-2010
  4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
  5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
  6  * License terms: GNU General Public License (GPL) version 2
  7  */
  8 
  9 #include <linux/dma-mapping.h>
 10 #include <linux/kernel.h>
 11 #include <linux/slab.h>
 12 #include <linux/export.h>
 13 #include <linux/dmaengine.h>
 14 #include <linux/platform_device.h>
 15 #include <linux/clk.h>
 16 #include <linux/delay.h>
 17 #include <linux/log2.h>
 18 #include <linux/pm.h>
 19 #include <linux/pm_runtime.h>
 20 #include <linux/err.h>
 21 #include <linux/of.h>
 22 #include <linux/of_dma.h>
 23 #include <linux/amba/bus.h>
 24 #include <linux/regulator/consumer.h>
 25 #include <linux/platform_data/dma-ste-dma40.h>
 26 
 27 #include "dmaengine.h"
 28 #include "ste_dma40_ll.h"
 29 
 30 #define D40_NAME "dma40"
 31 
 32 #define D40_PHY_CHAN -1
 33 
 34 /* For masking out/in 2 bit channel positions */
 35 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
 36 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
 37 
 38 /* Maximum iterations taken before giving up suspending a channel */
 39 #define D40_SUSPEND_MAX_IT 500
 40 
 41 /* Milliseconds */
 42 #define DMA40_AUTOSUSPEND_DELAY 100
 43 
 44 /* Hardware requirement on LCLA alignment */
 45 #define LCLA_ALIGNMENT 0x40000
 46 
 47 /* Max number of links per event group */
 48 #define D40_LCLA_LINK_PER_EVENT_GRP 128
 49 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
 50 
 51 /* Max number of logical channels per physical channel */
 52 #define D40_MAX_LOG_CHAN_PER_PHY 32
 53 
 54 /* Attempts before giving up to trying to get pages that are aligned */
 55 #define MAX_LCLA_ALLOC_ATTEMPTS 256
 56 
 57 /* Bit markings for allocation map */
 58 #define D40_ALLOC_FREE          BIT(31)
 59 #define D40_ALLOC_PHY           BIT(30)
 60 #define D40_ALLOC_LOG_FREE      0
 61 
 62 #define D40_MEMCPY_MAX_CHANS    8
 63 
 64 /* Reserved event lines for memcpy only. */
 65 #define DB8500_DMA_MEMCPY_EV_0  51
 66 #define DB8500_DMA_MEMCPY_EV_1  56
 67 #define DB8500_DMA_MEMCPY_EV_2  57
 68 #define DB8500_DMA_MEMCPY_EV_3  58
 69 #define DB8500_DMA_MEMCPY_EV_4  59
 70 #define DB8500_DMA_MEMCPY_EV_5  60
 71 
 72 static int dma40_memcpy_channels[] = {
 73         DB8500_DMA_MEMCPY_EV_0,
 74         DB8500_DMA_MEMCPY_EV_1,
 75         DB8500_DMA_MEMCPY_EV_2,
 76         DB8500_DMA_MEMCPY_EV_3,
 77         DB8500_DMA_MEMCPY_EV_4,
 78         DB8500_DMA_MEMCPY_EV_5,
 79 };
 80 
 81 /* Default configuration for physcial memcpy */
 82 static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
 83         .mode = STEDMA40_MODE_PHYSICAL,
 84         .dir = DMA_MEM_TO_MEM,
 85 
 86         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 87         .src_info.psize = STEDMA40_PSIZE_PHY_1,
 88         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 89 
 90         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 91         .dst_info.psize = STEDMA40_PSIZE_PHY_1,
 92         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 93 };
 94 
 95 /* Default configuration for logical memcpy */
 96 static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 97         .mode = STEDMA40_MODE_LOGICAL,
 98         .dir = DMA_MEM_TO_MEM,
 99 
100         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
101         .src_info.psize = STEDMA40_PSIZE_LOG_1,
102         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
103 
104         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
105         .dst_info.psize = STEDMA40_PSIZE_LOG_1,
106         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
107 };
108 
109 /**
110  * enum 40_command - The different commands and/or statuses.
111  *
112  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
113  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
114  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
115  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
116  */
117 enum d40_command {
118         D40_DMA_STOP            = 0,
119         D40_DMA_RUN             = 1,
120         D40_DMA_SUSPEND_REQ     = 2,
121         D40_DMA_SUSPENDED       = 3
122 };
123 
124 /*
125  * enum d40_events - The different Event Enables for the event lines.
126  *
127  * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
128  * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
129  * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
130  * @D40_ROUND_EVENTLINE: Status check for event line.
131  */
132 
133 enum d40_events {
134         D40_DEACTIVATE_EVENTLINE        = 0,
135         D40_ACTIVATE_EVENTLINE          = 1,
136         D40_SUSPEND_REQ_EVENTLINE       = 2,
137         D40_ROUND_EVENTLINE             = 3
138 };
139 
140 /*
141  * These are the registers that has to be saved and later restored
142  * when the DMA hw is powered off.
143  * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
144  */
145 static u32 d40_backup_regs[] = {
146         D40_DREG_LCPA,
147         D40_DREG_LCLA,
148         D40_DREG_PRMSE,
149         D40_DREG_PRMSO,
150         D40_DREG_PRMOE,
151         D40_DREG_PRMOO,
152 };
153 
154 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
155 
156 /*
157  * since 9540 and 8540 has the same HW revision
158  * use v4a for 9540 or ealier
159  * use v4b for 8540 or later
160  * HW revision:
161  * DB8500ed has revision 0
162  * DB8500v1 has revision 2
163  * DB8500v2 has revision 3
164  * AP9540v1 has revision 4
165  * DB8540v1 has revision 4
166  * TODO: Check if all these registers have to be saved/restored on dma40 v4a
167  */
168 static u32 d40_backup_regs_v4a[] = {
169         D40_DREG_PSEG1,
170         D40_DREG_PSEG2,
171         D40_DREG_PSEG3,
172         D40_DREG_PSEG4,
173         D40_DREG_PCEG1,
174         D40_DREG_PCEG2,
175         D40_DREG_PCEG3,
176         D40_DREG_PCEG4,
177         D40_DREG_RSEG1,
178         D40_DREG_RSEG2,
179         D40_DREG_RSEG3,
180         D40_DREG_RSEG4,
181         D40_DREG_RCEG1,
182         D40_DREG_RCEG2,
183         D40_DREG_RCEG3,
184         D40_DREG_RCEG4,
185 };
186 
187 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
188 
189 static u32 d40_backup_regs_v4b[] = {
190         D40_DREG_CPSEG1,
191         D40_DREG_CPSEG2,
192         D40_DREG_CPSEG3,
193         D40_DREG_CPSEG4,
194         D40_DREG_CPSEG5,
195         D40_DREG_CPCEG1,
196         D40_DREG_CPCEG2,
197         D40_DREG_CPCEG3,
198         D40_DREG_CPCEG4,
199         D40_DREG_CPCEG5,
200         D40_DREG_CRSEG1,
201         D40_DREG_CRSEG2,
202         D40_DREG_CRSEG3,
203         D40_DREG_CRSEG4,
204         D40_DREG_CRSEG5,
205         D40_DREG_CRCEG1,
206         D40_DREG_CRCEG2,
207         D40_DREG_CRCEG3,
208         D40_DREG_CRCEG4,
209         D40_DREG_CRCEG5,
210 };
211 
212 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
213 
214 static u32 d40_backup_regs_chan[] = {
215         D40_CHAN_REG_SSCFG,
216         D40_CHAN_REG_SSELT,
217         D40_CHAN_REG_SSPTR,
218         D40_CHAN_REG_SSLNK,
219         D40_CHAN_REG_SDCFG,
220         D40_CHAN_REG_SDELT,
221         D40_CHAN_REG_SDPTR,
222         D40_CHAN_REG_SDLNK,
223 };
224 
225 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
226                              BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
227 
228 /**
229  * struct d40_interrupt_lookup - lookup table for interrupt handler
230  *
231  * @src: Interrupt mask register.
232  * @clr: Interrupt clear register.
233  * @is_error: true if this is an error interrupt.
234  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
235  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
236  */
237 struct d40_interrupt_lookup {
238         u32 src;
239         u32 clr;
240         bool is_error;
241         int offset;
242 };
243 
244 
245 static struct d40_interrupt_lookup il_v4a[] = {
246         {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
247         {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
248         {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
249         {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
250         {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
251         {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
252         {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
253         {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
254         {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
255         {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
256 };
257 
258 static struct d40_interrupt_lookup il_v4b[] = {
259         {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false,  0},
260         {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
261         {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
262         {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
263         {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
264         {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true,   0},
265         {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true,  32},
266         {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true,  64},
267         {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true,  96},
268         {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true,  128},
269         {D40_DREG_CPCTIS,  D40_DREG_CPCICR,  false, D40_PHY_CHAN},
270         {D40_DREG_CPCEIS,  D40_DREG_CPCICR,  true,  D40_PHY_CHAN},
271 };
272 
273 /**
274  * struct d40_reg_val - simple lookup struct
275  *
276  * @reg: The register.
277  * @val: The value that belongs to the register in reg.
278  */
279 struct d40_reg_val {
280         unsigned int reg;
281         unsigned int val;
282 };
283 
284 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
285         /* Clock every part of the DMA block from start */
286         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
287 
288         /* Interrupts on all logical channels */
289         { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
290         { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
291         { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
292         { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
293         { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
294         { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
295         { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
296         { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
297         { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
298         { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
299         { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
300         { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
301 };
302 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
303         /* Clock every part of the DMA block from start */
304         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
305 
306         /* Interrupts on all logical channels */
307         { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
308         { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
309         { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
310         { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
311         { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
312         { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
313         { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
314         { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
315         { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
316         { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
317         { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
318         { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
319         { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
320         { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
321         { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
322 };
323 
324 /**
325  * struct d40_lli_pool - Structure for keeping LLIs in memory
326  *
327  * @base: Pointer to memory area when the pre_alloc_lli's are not large
328  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
329  * pre_alloc_lli is used.
330  * @dma_addr: DMA address, if mapped
331  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
332  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
333  * one buffer to one buffer.
334  */
335 struct d40_lli_pool {
336         void    *base;
337         int      size;
338         dma_addr_t      dma_addr;
339         /* Space for dst and src, plus an extra for padding */
340         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
341 };
342 
343 /**
344  * struct d40_desc - A descriptor is one DMA job.
345  *
346  * @lli_phy: LLI settings for physical channel. Both src and dst=
347  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
348  * lli_len equals one.
349  * @lli_log: Same as above but for logical channels.
350  * @lli_pool: The pool with two entries pre-allocated.
351  * @lli_len: Number of llis of current descriptor.
352  * @lli_current: Number of transferred llis.
353  * @lcla_alloc: Number of LCLA entries allocated.
354  * @txd: DMA engine struct. Used for among other things for communication
355  * during a transfer.
356  * @node: List entry.
357  * @is_in_client_list: true if the client owns this descriptor.
358  * @cyclic: true if this is a cyclic job
359  *
360  * This descriptor is used for both logical and physical transfers.
361  */
362 struct d40_desc {
363         /* LLI physical */
364         struct d40_phy_lli_bidir         lli_phy;
365         /* LLI logical */
366         struct d40_log_lli_bidir         lli_log;
367 
368         struct d40_lli_pool              lli_pool;
369         int                              lli_len;
370         int                              lli_current;
371         int                              lcla_alloc;
372 
373         struct dma_async_tx_descriptor   txd;
374         struct list_head                 node;
375 
376         bool                             is_in_client_list;
377         bool                             cyclic;
378 };
379 
380 /**
381  * struct d40_lcla_pool - LCLA pool settings and data.
382  *
383  * @base: The virtual address of LCLA. 18 bit aligned.
384  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
385  * This pointer is only there for clean-up on error.
386  * @pages: The number of pages needed for all physical channels.
387  * Only used later for clean-up on error
388  * @lock: Lock to protect the content in this struct.
389  * @alloc_map: big map over which LCLA entry is own by which job.
390  */
391 struct d40_lcla_pool {
392         void            *base;
393         dma_addr_t      dma_addr;
394         void            *base_unaligned;
395         int              pages;
396         spinlock_t       lock;
397         struct d40_desc **alloc_map;
398 };
399 
400 /**
401  * struct d40_phy_res - struct for handling eventlines mapped to physical
402  * channels.
403  *
404  * @lock: A lock protection this entity.
405  * @reserved: True if used by secure world or otherwise.
406  * @num: The physical channel number of this entity.
407  * @allocated_src: Bit mapped to show which src event line's are mapped to
408  * this physical channel. Can also be free or physically allocated.
409  * @allocated_dst: Same as for src but is dst.
410  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
411  * event line number.
412  * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
413  */
414 struct d40_phy_res {
415         spinlock_t lock;
416         bool       reserved;
417         int        num;
418         u32        allocated_src;
419         u32        allocated_dst;
420         bool       use_soft_lli;
421 };
422 
423 struct d40_base;
424 
425 /**
426  * struct d40_chan - Struct that describes a channel.
427  *
428  * @lock: A spinlock to protect this struct.
429  * @log_num: The logical number, if any of this channel.
430  * @pending_tx: The number of pending transfers. Used between interrupt handler
431  * and tasklet.
432  * @busy: Set to true when transfer is ongoing on this channel.
433  * @phy_chan: Pointer to physical channel which this instance runs on. If this
434  * point is NULL, then the channel is not allocated.
435  * @chan: DMA engine handle.
436  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
437  * transfer and call client callback.
438  * @client: Cliented owned descriptor list.
439  * @pending_queue: Submitted jobs, to be issued by issue_pending()
440  * @active: Active descriptor.
441  * @done: Completed jobs
442  * @queue: Queued jobs.
443  * @prepare_queue: Prepared jobs.
444  * @dma_cfg: The client configuration of this dma channel.
445  * @configured: whether the dma_cfg configuration is valid
446  * @base: Pointer to the device instance struct.
447  * @src_def_cfg: Default cfg register setting for src.
448  * @dst_def_cfg: Default cfg register setting for dst.
449  * @log_def: Default logical channel settings.
450  * @lcpa: Pointer to dst and src lcpa settings.
451  * @runtime_addr: runtime configured address.
452  * @runtime_direction: runtime configured direction.
453  *
454  * This struct can either "be" a logical or a physical channel.
455  */
456 struct d40_chan {
457         spinlock_t                       lock;
458         int                              log_num;
459         int                              pending_tx;
460         bool                             busy;
461         struct d40_phy_res              *phy_chan;
462         struct dma_chan                  chan;
463         struct tasklet_struct            tasklet;
464         struct list_head                 client;
465         struct list_head                 pending_queue;
466         struct list_head                 active;
467         struct list_head                 done;
468         struct list_head                 queue;
469         struct list_head                 prepare_queue;
470         struct stedma40_chan_cfg         dma_cfg;
471         bool                             configured;
472         struct d40_base                 *base;
473         /* Default register configurations */
474         u32                              src_def_cfg;
475         u32                              dst_def_cfg;
476         struct d40_def_lcsp              log_def;
477         struct d40_log_lli_full         *lcpa;
478         /* Runtime reconfiguration */
479         dma_addr_t                      runtime_addr;
480         enum dma_transfer_direction     runtime_direction;
481 };
482 
483 /**
484  * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
485  * controller
486  *
487  * @backup: the pointer to the registers address array for backup
488  * @backup_size: the size of the registers address array for backup
489  * @realtime_en: the realtime enable register
490  * @realtime_clear: the realtime clear register
491  * @high_prio_en: the high priority enable register
492  * @high_prio_clear: the high priority clear register
493  * @interrupt_en: the interrupt enable register
494  * @interrupt_clear: the interrupt clear register
495  * @il: the pointer to struct d40_interrupt_lookup
496  * @il_size: the size of d40_interrupt_lookup array
497  * @init_reg: the pointer to the struct d40_reg_val
498  * @init_reg_size: the size of d40_reg_val array
499  */
500 struct d40_gen_dmac {
501         u32                             *backup;
502         u32                              backup_size;
503         u32                              realtime_en;
504         u32                              realtime_clear;
505         u32                              high_prio_en;
506         u32                              high_prio_clear;
507         u32                              interrupt_en;
508         u32                              interrupt_clear;
509         struct d40_interrupt_lookup     *il;
510         u32                              il_size;
511         struct d40_reg_val              *init_reg;
512         u32                              init_reg_size;
513 };
514 
515 /**
516  * struct d40_base - The big global struct, one for each probe'd instance.
517  *
518  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
519  * @execmd_lock: Lock for execute command usage since several channels share
520  * the same physical register.
521  * @dev: The device structure.
522  * @virtbase: The virtual base address of the DMA's register.
523  * @rev: silicon revision detected.
524  * @clk: Pointer to the DMA clock structure.
525  * @phy_start: Physical memory start of the DMA registers.
526  * @phy_size: Size of the DMA register map.
527  * @irq: The IRQ number.
528  * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
529  * transfers).
530  * @num_phy_chans: The number of physical channels. Read from HW. This
531  * is the number of available channels for this driver, not counting "Secure
532  * mode" allocated physical channels.
533  * @num_log_chans: The number of logical channels. Calculated from
534  * num_phy_chans.
535  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
536  * @dma_slave: dma_device channels that can do only do slave transfers.
537  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
538  * @phy_chans: Room for all possible physical channels in system.
539  * @log_chans: Room for all possible logical channels in system.
540  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
541  * to log_chans entries.
542  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
543  * to phy_chans entries.
544  * @plat_data: Pointer to provided platform_data which is the driver
545  * configuration.
546  * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
547  * @phy_res: Vector containing all physical channels.
548  * @lcla_pool: lcla pool settings and data.
549  * @lcpa_base: The virtual mapped address of LCPA.
550  * @phy_lcpa: The physical address of the LCPA.
551  * @lcpa_size: The size of the LCPA area.
552  * @desc_slab: cache for descriptors.
553  * @reg_val_backup: Here the values of some hardware registers are stored
554  * before the DMA is powered off. They are restored when the power is back on.
555  * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
556  * later
557  * @reg_val_backup_chan: Backup data for standard channel parameter registers.
558  * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
559  * @gen_dmac: the struct for generic registers values to represent u8500/8540
560  * DMA controller
561  */
562 struct d40_base {
563         spinlock_t                       interrupt_lock;
564         spinlock_t                       execmd_lock;
565         struct device                    *dev;
566         void __iomem                     *virtbase;
567         u8                                rev:4;
568         struct clk                       *clk;
569         phys_addr_t                       phy_start;
570         resource_size_t                   phy_size;
571         int                               irq;
572         int                               num_memcpy_chans;
573         int                               num_phy_chans;
574         int                               num_log_chans;
575         struct device_dma_parameters      dma_parms;
576         struct dma_device                 dma_both;
577         struct dma_device                 dma_slave;
578         struct dma_device                 dma_memcpy;
579         struct d40_chan                  *phy_chans;
580         struct d40_chan                  *log_chans;
581         struct d40_chan                 **lookup_log_chans;
582         struct d40_chan                 **lookup_phy_chans;
583         struct stedma40_platform_data    *plat_data;
584         struct regulator                 *lcpa_regulator;
585         /* Physical half channels */
586         struct d40_phy_res               *phy_res;
587         struct d40_lcla_pool              lcla_pool;
588         void                             *lcpa_base;
589         dma_addr_t                        phy_lcpa;
590         resource_size_t                   lcpa_size;
591         struct kmem_cache                *desc_slab;
592         u32                               reg_val_backup[BACKUP_REGS_SZ];
593         u32                               reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
594         u32                              *reg_val_backup_chan;
595         u16                               gcc_pwr_off_mask;
596         struct d40_gen_dmac               gen_dmac;
597 };
598 
599 static struct device *chan2dev(struct d40_chan *d40c)
600 {
601         return &d40c->chan.dev->device;
602 }
603 
604 static bool chan_is_physical(struct d40_chan *chan)
605 {
606         return chan->log_num == D40_PHY_CHAN;
607 }
608 
609 static bool chan_is_logical(struct d40_chan *chan)
610 {
611         return !chan_is_physical(chan);
612 }
613 
614 static void __iomem *chan_base(struct d40_chan *chan)
615 {
616         return chan->base->virtbase + D40_DREG_PCBASE +
617                chan->phy_chan->num * D40_DREG_PCDELTA;
618 }
619 
620 #define d40_err(dev, format, arg...)            \
621         dev_err(dev, "[%s] " format, __func__, ## arg)
622 
623 #define chan_err(d40c, format, arg...)          \
624         d40_err(chan2dev(d40c), format, ## arg)
625 
626 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
627                               int lli_len)
628 {
629         bool is_log = chan_is_logical(d40c);
630         u32 align;
631         void *base;
632 
633         if (is_log)
634                 align = sizeof(struct d40_log_lli);
635         else
636                 align = sizeof(struct d40_phy_lli);
637 
638         if (lli_len == 1) {
639                 base = d40d->lli_pool.pre_alloc_lli;
640                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
641                 d40d->lli_pool.base = NULL;
642         } else {
643                 d40d->lli_pool.size = lli_len * 2 * align;
644 
645                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
646                 d40d->lli_pool.base = base;
647 
648                 if (d40d->lli_pool.base == NULL)
649                         return -ENOMEM;
650         }
651 
652         if (is_log) {
653                 d40d->lli_log.src = PTR_ALIGN(base, align);
654                 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
655 
656                 d40d->lli_pool.dma_addr = 0;
657         } else {
658                 d40d->lli_phy.src = PTR_ALIGN(base, align);
659                 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
660 
661                 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
662                                                          d40d->lli_phy.src,
663                                                          d40d->lli_pool.size,
664                                                          DMA_TO_DEVICE);
665 
666                 if (dma_mapping_error(d40c->base->dev,
667                                       d40d->lli_pool.dma_addr)) {
668                         kfree(d40d->lli_pool.base);
669                         d40d->lli_pool.base = NULL;
670                         d40d->lli_pool.dma_addr = 0;
671                         return -ENOMEM;
672                 }
673         }
674 
675         return 0;
676 }
677 
678 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
679 {
680         if (d40d->lli_pool.dma_addr)
681                 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
682                                  d40d->lli_pool.size, DMA_TO_DEVICE);
683 
684         kfree(d40d->lli_pool.base);
685         d40d->lli_pool.base = NULL;
686         d40d->lli_pool.size = 0;
687         d40d->lli_log.src = NULL;
688         d40d->lli_log.dst = NULL;
689         d40d->lli_phy.src = NULL;
690         d40d->lli_phy.dst = NULL;
691 }
692 
693 static int d40_lcla_alloc_one(struct d40_chan *d40c,
694                               struct d40_desc *d40d)
695 {
696         unsigned long flags;
697         int i;
698         int ret = -EINVAL;
699 
700         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
701 
702         /*
703          * Allocate both src and dst at the same time, therefore the half
704          * start on 1 since 0 can't be used since zero is used as end marker.
705          */
706         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
707                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
708 
709                 if (!d40c->base->lcla_pool.alloc_map[idx]) {
710                         d40c->base->lcla_pool.alloc_map[idx] = d40d;
711                         d40d->lcla_alloc++;
712                         ret = i;
713                         break;
714                 }
715         }
716 
717         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
718 
719         return ret;
720 }
721 
722 static int d40_lcla_free_all(struct d40_chan *d40c,
723                              struct d40_desc *d40d)
724 {
725         unsigned long flags;
726         int i;
727         int ret = -EINVAL;
728 
729         if (chan_is_physical(d40c))
730                 return 0;
731 
732         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
733 
734         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
735                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
736 
737                 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
738                         d40c->base->lcla_pool.alloc_map[idx] = NULL;
739                         d40d->lcla_alloc--;
740                         if (d40d->lcla_alloc == 0) {
741                                 ret = 0;
742                                 break;
743                         }
744                 }
745         }
746 
747         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
748 
749         return ret;
750 
751 }
752 
753 static void d40_desc_remove(struct d40_desc *d40d)
754 {
755         list_del(&d40d->node);
756 }
757 
758 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
759 {
760         struct d40_desc *desc = NULL;
761 
762         if (!list_empty(&d40c->client)) {
763                 struct d40_desc *d;
764                 struct d40_desc *_d;
765 
766                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
767                         if (async_tx_test_ack(&d->txd)) {
768                                 d40_desc_remove(d);
769                                 desc = d;
770                                 memset(desc, 0, sizeof(*desc));
771                                 break;
772                         }
773                 }
774         }
775 
776         if (!desc)
777                 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
778 
779         if (desc)
780                 INIT_LIST_HEAD(&desc->node);
781 
782         return desc;
783 }
784 
785 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
786 {
787 
788         d40_pool_lli_free(d40c, d40d);
789         d40_lcla_free_all(d40c, d40d);
790         kmem_cache_free(d40c->base->desc_slab, d40d);
791 }
792 
793 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
794 {
795         list_add_tail(&desc->node, &d40c->active);
796 }
797 
798 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
799 {
800         struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
801         struct d40_phy_lli *lli_src = desc->lli_phy.src;
802         void __iomem *base = chan_base(chan);
803 
804         writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
805         writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
806         writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
807         writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
808 
809         writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
810         writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
811         writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
812         writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
813 }
814 
815 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
816 {
817         list_add_tail(&desc->node, &d40c->done);
818 }
819 
820 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
821 {
822         struct d40_lcla_pool *pool = &chan->base->lcla_pool;
823         struct d40_log_lli_bidir *lli = &desc->lli_log;
824         int lli_current = desc->lli_current;
825         int lli_len = desc->lli_len;
826         bool cyclic = desc->cyclic;
827         int curr_lcla = -EINVAL;
828         int first_lcla = 0;
829         bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
830         bool linkback;
831 
832         /*
833          * We may have partially running cyclic transfers, in case we did't get
834          * enough LCLA entries.
835          */
836         linkback = cyclic && lli_current == 0;
837 
838         /*
839          * For linkback, we need one LCLA even with only one link, because we
840          * can't link back to the one in LCPA space
841          */
842         if (linkback || (lli_len - lli_current > 1)) {
843                 /*
844                  * If the channel is expected to use only soft_lli don't
845                  * allocate a lcla. This is to avoid a HW issue that exists
846                  * in some controller during a peripheral to memory transfer
847                  * that uses linked lists.
848                  */
849                 if (!(chan->phy_chan->use_soft_lli &&
850                         chan->dma_cfg.dir == DMA_DEV_TO_MEM))
851                         curr_lcla = d40_lcla_alloc_one(chan, desc);
852 
853                 first_lcla = curr_lcla;
854         }
855 
856         /*
857          * For linkback, we normally load the LCPA in the loop since we need to
858          * link it to the second LCLA and not the first.  However, if we
859          * couldn't even get a first LCLA, then we have to run in LCPA and
860          * reload manually.
861          */
862         if (!linkback || curr_lcla == -EINVAL) {
863                 unsigned int flags = 0;
864 
865                 if (curr_lcla == -EINVAL)
866                         flags |= LLI_TERM_INT;
867 
868                 d40_log_lli_lcpa_write(chan->lcpa,
869                                        &lli->dst[lli_current],
870                                        &lli->src[lli_current],
871                                        curr_lcla,
872                                        flags);
873                 lli_current++;
874         }
875 
876         if (curr_lcla < 0)
877                 goto out;
878 
879         for (; lli_current < lli_len; lli_current++) {
880                 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
881                                            8 * curr_lcla * 2;
882                 struct d40_log_lli *lcla = pool->base + lcla_offset;
883                 unsigned int flags = 0;
884                 int next_lcla;
885 
886                 if (lli_current + 1 < lli_len)
887                         next_lcla = d40_lcla_alloc_one(chan, desc);
888                 else
889                         next_lcla = linkback ? first_lcla : -EINVAL;
890 
891                 if (cyclic || next_lcla == -EINVAL)
892                         flags |= LLI_TERM_INT;
893 
894                 if (linkback && curr_lcla == first_lcla) {
895                         /* First link goes in both LCPA and LCLA */
896                         d40_log_lli_lcpa_write(chan->lcpa,
897                                                &lli->dst[lli_current],
898                                                &lli->src[lli_current],
899                                                next_lcla, flags);
900                 }
901 
902                 /*
903                  * One unused LCLA in the cyclic case if the very first
904                  * next_lcla fails...
905                  */
906                 d40_log_lli_lcla_write(lcla,
907                                        &lli->dst[lli_current],
908                                        &lli->src[lli_current],
909                                        next_lcla, flags);
910 
911                 /*
912                  * Cache maintenance is not needed if lcla is
913                  * mapped in esram
914                  */
915                 if (!use_esram_lcla) {
916                         dma_sync_single_range_for_device(chan->base->dev,
917                                                 pool->dma_addr, lcla_offset,
918                                                 2 * sizeof(struct d40_log_lli),
919                                                 DMA_TO_DEVICE);
920                 }
921                 curr_lcla = next_lcla;
922 
923                 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
924                         lli_current++;
925                         break;
926                 }
927         }
928 
929 out:
930         desc->lli_current = lli_current;
931 }
932 
933 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
934 {
935         if (chan_is_physical(d40c)) {
936                 d40_phy_lli_load(d40c, d40d);
937                 d40d->lli_current = d40d->lli_len;
938         } else
939                 d40_log_lli_to_lcxa(d40c, d40d);
940 }
941 
942 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
943 {
944         struct d40_desc *d;
945 
946         if (list_empty(&d40c->active))
947                 return NULL;
948 
949         d = list_first_entry(&d40c->active,
950                              struct d40_desc,
951                              node);
952         return d;
953 }
954 
955 /* remove desc from current queue and add it to the pending_queue */
956 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
957 {
958         d40_desc_remove(desc);
959         desc->is_in_client_list = false;
960         list_add_tail(&desc->node, &d40c->pending_queue);
961 }
962 
963 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
964 {
965         struct d40_desc *d;
966 
967         if (list_empty(&d40c->pending_queue))
968                 return NULL;
969 
970         d = list_first_entry(&d40c->pending_queue,
971                              struct d40_desc,
972                              node);
973         return d;
974 }
975 
976 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
977 {
978         struct d40_desc *d;
979 
980         if (list_empty(&d40c->queue))
981                 return NULL;
982 
983         d = list_first_entry(&d40c->queue,
984                              struct d40_desc,
985                              node);
986         return d;
987 }
988 
989 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
990 {
991         if (list_empty(&d40c->done))
992                 return NULL;
993 
994         return list_first_entry(&d40c->done, struct d40_desc, node);
995 }
996 
997 static int d40_psize_2_burst_size(bool is_log, int psize)
998 {
999         if (is_log) {
1000                 if (psize == STEDMA40_PSIZE_LOG_1)
1001                         return 1;
1002         } else {
1003                 if (psize == STEDMA40_PSIZE_PHY_1)
1004                         return 1;
1005         }
1006 
1007         return 2 << psize;
1008 }
1009 
1010 /*
1011  * The dma only supports transmitting packages up to
1012  * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1013  *
1014  * Calculate the total number of dma elements required to send the entire sg list.
1015  */
1016 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1017 {
1018         int dmalen;
1019         u32 max_w = max(data_width1, data_width2);
1020         u32 min_w = min(data_width1, data_width2);
1021         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
1022 
1023         if (seg_max > STEDMA40_MAX_SEG_SIZE)
1024                 seg_max -= max_w;
1025 
1026         if (!IS_ALIGNED(size, max_w))
1027                 return -EINVAL;
1028 
1029         if (size <= seg_max)
1030                 dmalen = 1;
1031         else {
1032                 dmalen = size / seg_max;
1033                 if (dmalen * seg_max < size)
1034                         dmalen++;
1035         }
1036         return dmalen;
1037 }
1038 
1039 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1040                            u32 data_width1, u32 data_width2)
1041 {
1042         struct scatterlist *sg;
1043         int i;
1044         int len = 0;
1045         int ret;
1046 
1047         for_each_sg(sgl, sg, sg_len, i) {
1048                 ret = d40_size_2_dmalen(sg_dma_len(sg),
1049                                         data_width1, data_width2);
1050                 if (ret < 0)
1051                         return ret;
1052                 len += ret;
1053         }
1054         return len;
1055 }
1056 
1057 static int __d40_execute_command_phy(struct d40_chan *d40c,
1058                                      enum d40_command command)
1059 {
1060         u32 status;
1061         int i;
1062         void __iomem *active_reg;
1063         int ret = 0;
1064         unsigned long flags;
1065         u32 wmask;
1066 
1067         if (command == D40_DMA_STOP) {
1068                 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1069                 if (ret)
1070                         return ret;
1071         }
1072 
1073         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1074 
1075         if (d40c->phy_chan->num % 2 == 0)
1076                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1077         else
1078                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1079 
1080         if (command == D40_DMA_SUSPEND_REQ) {
1081                 status = (readl(active_reg) &
1082                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1083                         D40_CHAN_POS(d40c->phy_chan->num);
1084 
1085                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1086                         goto done;
1087         }
1088 
1089         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1090         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1091                active_reg);
1092 
1093         if (command == D40_DMA_SUSPEND_REQ) {
1094 
1095                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1096                         status = (readl(active_reg) &
1097                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1098                                 D40_CHAN_POS(d40c->phy_chan->num);
1099 
1100                         cpu_relax();
1101                         /*
1102                          * Reduce the number of bus accesses while
1103                          * waiting for the DMA to suspend.
1104                          */
1105                         udelay(3);
1106 
1107                         if (status == D40_DMA_STOP ||
1108                             status == D40_DMA_SUSPENDED)
1109                                 break;
1110                 }
1111 
1112                 if (i == D40_SUSPEND_MAX_IT) {
1113                         chan_err(d40c,
1114                                 "unable to suspend the chl %d (log: %d) status %x\n",
1115                                 d40c->phy_chan->num, d40c->log_num,
1116                                 status);
1117                         dump_stack();
1118                         ret = -EBUSY;
1119                 }
1120 
1121         }
1122 done:
1123         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1124         return ret;
1125 }
1126 
1127 static void d40_term_all(struct d40_chan *d40c)
1128 {
1129         struct d40_desc *d40d;
1130         struct d40_desc *_d;
1131 
1132         /* Release completed descriptors */
1133         while ((d40d = d40_first_done(d40c))) {
1134                 d40_desc_remove(d40d);
1135                 d40_desc_free(d40c, d40d);
1136         }
1137 
1138         /* Release active descriptors */
1139         while ((d40d = d40_first_active_get(d40c))) {
1140                 d40_desc_remove(d40d);
1141                 d40_desc_free(d40c, d40d);
1142         }
1143 
1144         /* Release queued descriptors waiting for transfer */
1145         while ((d40d = d40_first_queued(d40c))) {
1146                 d40_desc_remove(d40d);
1147                 d40_desc_free(d40c, d40d);
1148         }
1149 
1150         /* Release pending descriptors */
1151         while ((d40d = d40_first_pending(d40c))) {
1152                 d40_desc_remove(d40d);
1153                 d40_desc_free(d40c, d40d);
1154         }
1155 
1156         /* Release client owned descriptors */
1157         if (!list_empty(&d40c->client))
1158                 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1159                         d40_desc_remove(d40d);
1160                         d40_desc_free(d40c, d40d);
1161                 }
1162 
1163         /* Release descriptors in prepare queue */
1164         if (!list_empty(&d40c->prepare_queue))
1165                 list_for_each_entry_safe(d40d, _d,
1166                                          &d40c->prepare_queue, node) {
1167                         d40_desc_remove(d40d);
1168                         d40_desc_free(d40c, d40d);
1169                 }
1170 
1171         d40c->pending_tx = 0;
1172 }
1173 
1174 static void __d40_config_set_event(struct d40_chan *d40c,
1175                                    enum d40_events event_type, u32 event,
1176                                    int reg)
1177 {
1178         void __iomem *addr = chan_base(d40c) + reg;
1179         int tries;
1180         u32 status;
1181 
1182         switch (event_type) {
1183 
1184         case D40_DEACTIVATE_EVENTLINE:
1185 
1186                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1187                        | ~D40_EVENTLINE_MASK(event), addr);
1188                 break;
1189 
1190         case D40_SUSPEND_REQ_EVENTLINE:
1191                 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1192                           D40_EVENTLINE_POS(event);
1193 
1194                 if (status == D40_DEACTIVATE_EVENTLINE ||
1195                     status == D40_SUSPEND_REQ_EVENTLINE)
1196                         break;
1197 
1198                 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1199                        | ~D40_EVENTLINE_MASK(event), addr);
1200 
1201                 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1202 
1203                         status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1204                                   D40_EVENTLINE_POS(event);
1205 
1206                         cpu_relax();
1207                         /*
1208                          * Reduce the number of bus accesses while
1209                          * waiting for the DMA to suspend.
1210                          */
1211                         udelay(3);
1212 
1213                         if (status == D40_DEACTIVATE_EVENTLINE)
1214                                 break;
1215                 }
1216 
1217                 if (tries == D40_SUSPEND_MAX_IT) {
1218                         chan_err(d40c,
1219                                 "unable to stop the event_line chl %d (log: %d)"
1220                                 "status %x\n", d40c->phy_chan->num,
1221                                  d40c->log_num, status);
1222                 }
1223                 break;
1224 
1225         case D40_ACTIVATE_EVENTLINE:
1226         /*
1227          * The hardware sometimes doesn't register the enable when src and dst
1228          * event lines are active on the same logical channel.  Retry to ensure
1229          * it does.  Usually only one retry is sufficient.
1230          */
1231                 tries = 100;
1232                 while (--tries) {
1233                         writel((D40_ACTIVATE_EVENTLINE <<
1234                                 D40_EVENTLINE_POS(event)) |
1235                                 ~D40_EVENTLINE_MASK(event), addr);
1236 
1237                         if (readl(addr) & D40_EVENTLINE_MASK(event))
1238                                 break;
1239                 }
1240 
1241                 if (tries != 99)
1242                         dev_dbg(chan2dev(d40c),
1243                                 "[%s] workaround enable S%cLNK (%d tries)\n",
1244                                 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1245                                 100 - tries);
1246 
1247                 WARN_ON(!tries);
1248                 break;
1249 
1250         case D40_ROUND_EVENTLINE:
1251                 BUG();
1252                 break;
1253 
1254         }
1255 }
1256 
1257 static void d40_config_set_event(struct d40_chan *d40c,
1258                                  enum d40_events event_type)
1259 {
1260         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1261 
1262         /* Enable event line connected to device (or memcpy) */
1263         if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1264             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1265                 __d40_config_set_event(d40c, event_type, event,
1266                                        D40_CHAN_REG_SSLNK);
1267 
1268         if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
1269                 __d40_config_set_event(d40c, event_type, event,
1270                                        D40_CHAN_REG_SDLNK);
1271 }
1272 
1273 static u32 d40_chan_has_events(struct d40_chan *d40c)
1274 {
1275         void __iomem *chanbase = chan_base(d40c);
1276         u32 val;
1277 
1278         val = readl(chanbase + D40_CHAN_REG_SSLNK);
1279         val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1280 
1281         return val;
1282 }
1283 
1284 static int
1285 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1286 {
1287         unsigned long flags;
1288         int ret = 0;
1289         u32 active_status;
1290         void __iomem *active_reg;
1291 
1292         if (d40c->phy_chan->num % 2 == 0)
1293                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1294         else
1295                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1296 
1297 
1298         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1299 
1300         switch (command) {
1301         case D40_DMA_STOP:
1302         case D40_DMA_SUSPEND_REQ:
1303 
1304                 active_status = (readl(active_reg) &
1305                                  D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1306                                  D40_CHAN_POS(d40c->phy_chan->num);
1307 
1308                 if (active_status == D40_DMA_RUN)
1309                         d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1310                 else
1311                         d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1312 
1313                 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1314                         ret = __d40_execute_command_phy(d40c, command);
1315 
1316                 break;
1317 
1318         case D40_DMA_RUN:
1319 
1320                 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1321                 ret = __d40_execute_command_phy(d40c, command);
1322                 break;
1323 
1324         case D40_DMA_SUSPENDED:
1325                 BUG();
1326                 break;
1327         }
1328 
1329         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1330         return ret;
1331 }
1332 
1333 static int d40_channel_execute_command(struct d40_chan *d40c,
1334                                        enum d40_command command)
1335 {
1336         if (chan_is_logical(d40c))
1337                 return __d40_execute_command_log(d40c, command);
1338         else
1339                 return __d40_execute_command_phy(d40c, command);
1340 }
1341 
1342 static u32 d40_get_prmo(struct d40_chan *d40c)
1343 {
1344         static const unsigned int phy_map[] = {
1345                 [STEDMA40_PCHAN_BASIC_MODE]
1346                         = D40_DREG_PRMO_PCHAN_BASIC,
1347                 [STEDMA40_PCHAN_MODULO_MODE]
1348                         = D40_DREG_PRMO_PCHAN_MODULO,
1349                 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1350                         = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1351         };
1352         static const unsigned int log_map[] = {
1353                 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1354                         = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1355                 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1356                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1357                 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1358                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1359         };
1360 
1361         if (chan_is_physical(d40c))
1362                 return phy_map[d40c->dma_cfg.mode_opt];
1363         else
1364                 return log_map[d40c->dma_cfg.mode_opt];
1365 }
1366 
1367 static void d40_config_write(struct d40_chan *d40c)
1368 {
1369         u32 addr_base;
1370         u32 var;
1371 
1372         /* Odd addresses are even addresses + 4 */
1373         addr_base = (d40c->phy_chan->num % 2) * 4;
1374         /* Setup channel mode to logical or physical */
1375         var = ((u32)(chan_is_logical(d40c)) + 1) <<
1376                 D40_CHAN_POS(d40c->phy_chan->num);
1377         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1378 
1379         /* Setup operational mode option register */
1380         var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1381 
1382         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1383 
1384         if (chan_is_logical(d40c)) {
1385                 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1386                            & D40_SREG_ELEM_LOG_LIDX_MASK;
1387                 void __iomem *chanbase = chan_base(d40c);
1388 
1389                 /* Set default config for CFG reg */
1390                 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1391                 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1392 
1393                 /* Set LIDX for lcla */
1394                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1395                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1396 
1397                 /* Clear LNK which will be used by d40_chan_has_events() */
1398                 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1399                 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1400         }
1401 }
1402 
1403 static u32 d40_residue(struct d40_chan *d40c)
1404 {
1405         u32 num_elt;
1406 
1407         if (chan_is_logical(d40c))
1408                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1409                         >> D40_MEM_LCSP2_ECNT_POS;
1410         else {
1411                 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1412                 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1413                           >> D40_SREG_ELEM_PHY_ECNT_POS;
1414         }
1415 
1416         return num_elt * d40c->dma_cfg.dst_info.data_width;
1417 }
1418 
1419 static bool d40_tx_is_linked(struct d40_chan *d40c)
1420 {
1421         bool is_link;
1422 
1423         if (chan_is_logical(d40c))
1424                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
1425         else
1426                 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1427                           & D40_SREG_LNK_PHYS_LNK_MASK;
1428 
1429         return is_link;
1430 }
1431 
1432 static int d40_pause(struct dma_chan *chan)
1433 {
1434         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1435         int res = 0;
1436         unsigned long flags;
1437 
1438         if (d40c->phy_chan == NULL) {
1439                 chan_err(d40c, "Channel is not allocated!\n");
1440                 return -EINVAL;
1441         }
1442 
1443         if (!d40c->busy)
1444                 return 0;
1445 
1446         spin_lock_irqsave(&d40c->lock, flags);
1447         pm_runtime_get_sync(d40c->base->dev);
1448 
1449         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1450 
1451         pm_runtime_mark_last_busy(d40c->base->dev);
1452         pm_runtime_put_autosuspend(d40c->base->dev);
1453         spin_unlock_irqrestore(&d40c->lock, flags);
1454         return res;
1455 }
1456 
1457 static int d40_resume(struct dma_chan *chan)
1458 {
1459         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1460         int res = 0;
1461         unsigned long flags;