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Linux/drivers/dma/s3c24xx-dma.c

  1 /*
  2  * S3C24XX DMA handling
  3  *
  4  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  5  *
  6  * based on amba-pl08x.c
  7  *
  8  * Copyright (c) 2006 ARM Ltd.
  9  * Copyright (c) 2010 ST-Ericsson SA
 10  *
 11  * Author: Peter Pearse <peter.pearse@arm.com>
 12  * Author: Linus Walleij <linus.walleij@stericsson.com>
 13  *
 14  * This program is free software; you can redistribute it and/or modify it
 15  * under the terms of the GNU General Public License as published by the Free
 16  * Software Foundation; either version 2 of the License, or (at your option)
 17  * any later version.
 18  *
 19  * The DMA controllers in S3C24XX SoCs have a varying number of DMA signals
 20  * that can be routed to any of the 4 to 8 hardware-channels.
 21  *
 22  * Therefore on these DMA controllers the number of channels
 23  * and the number of incoming DMA signals are two totally different things.
 24  * It is usually not possible to theoretically handle all physical signals,
 25  * so a multiplexing scheme with possible denial of use is necessary.
 26  *
 27  * Open items:
 28  * - bursts
 29  */
 30 
 31 #include <linux/platform_device.h>
 32 #include <linux/types.h>
 33 #include <linux/dmaengine.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/interrupt.h>
 36 #include <linux/clk.h>
 37 #include <linux/module.h>
 38 #include <linux/slab.h>
 39 #include <linux/platform_data/dma-s3c24xx.h>
 40 
 41 #include "dmaengine.h"
 42 #include "virt-dma.h"
 43 
 44 #define MAX_DMA_CHANNELS        8
 45 
 46 #define S3C24XX_DISRC                   0x00
 47 #define S3C24XX_DISRCC                  0x04
 48 #define S3C24XX_DISRCC_INC_INCREMENT    0
 49 #define S3C24XX_DISRCC_INC_FIXED        BIT(0)
 50 #define S3C24XX_DISRCC_LOC_AHB          0
 51 #define S3C24XX_DISRCC_LOC_APB          BIT(1)
 52 
 53 #define S3C24XX_DIDST                   0x08
 54 #define S3C24XX_DIDSTC                  0x0c
 55 #define S3C24XX_DIDSTC_INC_INCREMENT    0
 56 #define S3C24XX_DIDSTC_INC_FIXED        BIT(0)
 57 #define S3C24XX_DIDSTC_LOC_AHB          0
 58 #define S3C24XX_DIDSTC_LOC_APB          BIT(1)
 59 #define S3C24XX_DIDSTC_INT_TC0          0
 60 #define S3C24XX_DIDSTC_INT_RELOAD       BIT(2)
 61 
 62 #define S3C24XX_DCON                    0x10
 63 
 64 #define S3C24XX_DCON_TC_MASK            0xfffff
 65 #define S3C24XX_DCON_DSZ_BYTE           (0 << 20)
 66 #define S3C24XX_DCON_DSZ_HALFWORD       (1 << 20)
 67 #define S3C24XX_DCON_DSZ_WORD           (2 << 20)
 68 #define S3C24XX_DCON_DSZ_MASK           (3 << 20)
 69 #define S3C24XX_DCON_DSZ_SHIFT          20
 70 #define S3C24XX_DCON_AUTORELOAD         0
 71 #define S3C24XX_DCON_NORELOAD           BIT(22)
 72 #define S3C24XX_DCON_HWTRIG             BIT(23)
 73 #define S3C24XX_DCON_HWSRC_SHIFT        24
 74 #define S3C24XX_DCON_SERV_SINGLE        0
 75 #define S3C24XX_DCON_SERV_WHOLE         BIT(27)
 76 #define S3C24XX_DCON_TSZ_UNIT           0
 77 #define S3C24XX_DCON_TSZ_BURST4         BIT(28)
 78 #define S3C24XX_DCON_INT                BIT(29)
 79 #define S3C24XX_DCON_SYNC_PCLK          0
 80 #define S3C24XX_DCON_SYNC_HCLK          BIT(30)
 81 #define S3C24XX_DCON_DEMAND             0
 82 #define S3C24XX_DCON_HANDSHAKE          BIT(31)
 83 
 84 #define S3C24XX_DSTAT                   0x14
 85 #define S3C24XX_DSTAT_STAT_BUSY         BIT(20)
 86 #define S3C24XX_DSTAT_CURRTC_MASK       0xfffff
 87 
 88 #define S3C24XX_DMASKTRIG               0x20
 89 #define S3C24XX_DMASKTRIG_SWTRIG        BIT(0)
 90 #define S3C24XX_DMASKTRIG_ON            BIT(1)
 91 #define S3C24XX_DMASKTRIG_STOP          BIT(2)
 92 
 93 #define S3C24XX_DMAREQSEL               0x24
 94 #define S3C24XX_DMAREQSEL_HW            BIT(0)
 95 
 96 /*
 97  * S3C2410, S3C2440 and S3C2442 SoCs cannot select any physical channel
 98  * for a DMA source. Instead only specific channels are valid.
 99  * All of these SoCs have 4 physical channels and the number of request
100  * source bits is 3. Additionally we also need 1 bit to mark the channel
101  * as valid.
102  * Therefore we separate the chansel element of the channel data into 4
103  * parts of 4 bits each, to hold the information if the channel is valid
104  * and the hw request source to use.
105  *
106  * Example:
107  * SDI is valid on channels 0, 2 and 3 - with varying hw request sources.
108  * For it the chansel field would look like
109  *
110  * ((BIT(3) | 1) << 3 * 4) | // channel 3, with request source 1
111  * ((BIT(3) | 2) << 2 * 4) | // channel 2, with request source 2
112  * ((BIT(3) | 2) << 0 * 4)   // channel 0, with request source 2
113  */
114 #define S3C24XX_CHANSEL_WIDTH           4
115 #define S3C24XX_CHANSEL_VALID           BIT(3)
116 #define S3C24XX_CHANSEL_REQ_MASK        7
117 
118 /*
119  * struct soc_data - vendor-specific config parameters for individual SoCs
120  * @stride: spacing between the registers of each channel
121  * @has_reqsel: does the controller use the newer requestselection mechanism
122  * @has_clocks: are controllable dma-clocks present
123  */
124 struct soc_data {
125         int stride;
126         bool has_reqsel;
127         bool has_clocks;
128 };
129 
130 /*
131  * enum s3c24xx_dma_chan_state - holds the virtual channel states
132  * @S3C24XX_DMA_CHAN_IDLE: the channel is idle
133  * @S3C24XX_DMA_CHAN_RUNNING: the channel has allocated a physical transport
134  * channel and is running a transfer on it
135  * @S3C24XX_DMA_CHAN_WAITING: the channel is waiting for a physical transport
136  * channel to become available (only pertains to memcpy channels)
137  */
138 enum s3c24xx_dma_chan_state {
139         S3C24XX_DMA_CHAN_IDLE,
140         S3C24XX_DMA_CHAN_RUNNING,
141         S3C24XX_DMA_CHAN_WAITING,
142 };
143 
144 /*
145  * struct s3c24xx_sg - structure containing data per sg
146  * @src_addr: src address of sg
147  * @dst_addr: dst address of sg
148  * @len: transfer len in bytes
149  * @node: node for txd's dsg_list
150  */
151 struct s3c24xx_sg {
152         dma_addr_t src_addr;
153         dma_addr_t dst_addr;
154         size_t len;
155         struct list_head node;
156 };
157 
158 /*
159  * struct s3c24xx_txd - wrapper for struct dma_async_tx_descriptor
160  * @vd: virtual DMA descriptor
161  * @dsg_list: list of children sg's
162  * @at: sg currently being transfered
163  * @width: transfer width
164  * @disrcc: value for source control register
165  * @didstc: value for destination control register
166  * @dcon: base value for dcon register
167  * @cyclic: indicate cyclic transfer
168  */
169 struct s3c24xx_txd {
170         struct virt_dma_desc vd;
171         struct list_head dsg_list;
172         struct list_head *at;
173         u8 width;
174         u32 disrcc;
175         u32 didstc;
176         u32 dcon;
177         bool cyclic;
178 };
179 
180 struct s3c24xx_dma_chan;
181 
182 /*
183  * struct s3c24xx_dma_phy - holder for the physical channels
184  * @id: physical index to this channel
185  * @valid: does the channel have all required elements
186  * @base: virtual memory base (remapped) for the this channel
187  * @irq: interrupt for this channel
188  * @clk: clock for this channel
189  * @lock: a lock to use when altering an instance of this struct
190  * @serving: virtual channel currently being served by this physicalchannel
191  * @host: a pointer to the host (internal use)
192  */
193 struct s3c24xx_dma_phy {
194         unsigned int                    id;
195         bool                            valid;
196         void __iomem                    *base;
197         int                             irq;
198         struct clk                      *clk;
199         spinlock_t                      lock;
200         struct s3c24xx_dma_chan         *serving;
201         struct s3c24xx_dma_engine       *host;
202 };
203 
204 /*
205  * struct s3c24xx_dma_chan - this structure wraps a DMA ENGINE channel
206  * @id: the id of the channel
207  * @name: name of the channel
208  * @vc: wrappped virtual channel
209  * @phy: the physical channel utilized by this channel, if there is one
210  * @runtime_addr: address for RX/TX according to the runtime config
211  * @at: active transaction on this channel
212  * @lock: a lock for this channel data
213  * @host: a pointer to the host (internal use)
214  * @state: whether the channel is idle, running etc
215  * @slave: whether this channel is a device (slave) or for memcpy
216  */
217 struct s3c24xx_dma_chan {
218         int id;
219         const char *name;
220         struct virt_dma_chan vc;
221         struct s3c24xx_dma_phy *phy;
222         struct dma_slave_config cfg;
223         struct s3c24xx_txd *at;
224         struct s3c24xx_dma_engine *host;
225         enum s3c24xx_dma_chan_state state;
226         bool slave;
227 };
228 
229 /*
230  * struct s3c24xx_dma_engine - the local state holder for the S3C24XX
231  * @pdev: the corresponding platform device
232  * @pdata: platform data passed in from the platform/machine
233  * @base: virtual memory base (remapped)
234  * @slave: slave engine for this instance
235  * @memcpy: memcpy engine for this instance
236  * @phy_chans: array of data for the physical channels
237  */
238 struct s3c24xx_dma_engine {
239         struct platform_device                  *pdev;
240         const struct s3c24xx_dma_platdata       *pdata;
241         struct soc_data                         *sdata;
242         void __iomem                            *base;
243         struct dma_device                       slave;
244         struct dma_device                       memcpy;
245         struct s3c24xx_dma_phy                  *phy_chans;
246 };
247 
248 /*
249  * Physical channel handling
250  */
251 
252 /*
253  * Check whether a certain channel is busy or not.
254  */
255 static int s3c24xx_dma_phy_busy(struct s3c24xx_dma_phy *phy)
256 {
257         unsigned int val = readl(phy->base + S3C24XX_DSTAT);
258         return val & S3C24XX_DSTAT_STAT_BUSY;
259 }
260 
261 static bool s3c24xx_dma_phy_valid(struct s3c24xx_dma_chan *s3cchan,
262                                   struct s3c24xx_dma_phy *phy)
263 {
264         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
265         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
266         struct s3c24xx_dma_channel *cdata = &pdata->channels[s3cchan->id];
267         int phyvalid;
268 
269         /* every phy is valid for memcopy channels */
270         if (!s3cchan->slave)
271                 return true;
272 
273         /* On newer variants all phys can be used for all virtual channels */
274         if (s3cdma->sdata->has_reqsel)
275                 return true;
276 
277         phyvalid = (cdata->chansel >> (phy->id * S3C24XX_CHANSEL_WIDTH));
278         return (phyvalid & S3C24XX_CHANSEL_VALID) ? true : false;
279 }
280 
281 /*
282  * Allocate a physical channel for a virtual channel
283  *
284  * Try to locate a physical channel to be used for this transfer. If all
285  * are taken return NULL and the requester will have to cope by using
286  * some fallback PIO mode or retrying later.
287  */
288 static
289 struct s3c24xx_dma_phy *s3c24xx_dma_get_phy(struct s3c24xx_dma_chan *s3cchan)
290 {
291         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
292         struct s3c24xx_dma_phy *phy = NULL;
293         unsigned long flags;
294         int i;
295         int ret;
296 
297         for (i = 0; i < s3cdma->pdata->num_phy_channels; i++) {
298                 phy = &s3cdma->phy_chans[i];
299 
300                 if (!phy->valid)
301                         continue;
302 
303                 if (!s3c24xx_dma_phy_valid(s3cchan, phy))
304                         continue;
305 
306                 spin_lock_irqsave(&phy->lock, flags);
307 
308                 if (!phy->serving) {
309                         phy->serving = s3cchan;
310                         spin_unlock_irqrestore(&phy->lock, flags);
311                         break;
312                 }
313 
314                 spin_unlock_irqrestore(&phy->lock, flags);
315         }
316 
317         /* No physical channel available, cope with it */
318         if (i == s3cdma->pdata->num_phy_channels) {
319                 dev_warn(&s3cdma->pdev->dev, "no phy channel available\n");
320                 return NULL;
321         }
322 
323         /* start the phy clock */
324         if (s3cdma->sdata->has_clocks) {
325                 ret = clk_enable(phy->clk);
326                 if (ret) {
327                         dev_err(&s3cdma->pdev->dev, "could not enable clock for channel %d, err %d\n",
328                                 phy->id, ret);
329                         phy->serving = NULL;
330                         return NULL;
331                 }
332         }
333 
334         return phy;
335 }
336 
337 /*
338  * Mark the physical channel as free.
339  *
340  * This drops the link between the physical and virtual channel.
341  */
342 static inline void s3c24xx_dma_put_phy(struct s3c24xx_dma_phy *phy)
343 {
344         struct s3c24xx_dma_engine *s3cdma = phy->host;
345 
346         if (s3cdma->sdata->has_clocks)
347                 clk_disable(phy->clk);
348 
349         phy->serving = NULL;
350 }
351 
352 /*
353  * Stops the channel by writing the stop bit.
354  * This should not be used for an on-going transfer, but as a method of
355  * shutting down a channel (eg, when it's no longer used) or terminating a
356  * transfer.
357  */
358 static void s3c24xx_dma_terminate_phy(struct s3c24xx_dma_phy *phy)
359 {
360         writel(S3C24XX_DMASKTRIG_STOP, phy->base + S3C24XX_DMASKTRIG);
361 }
362 
363 /*
364  * Virtual channel handling
365  */
366 
367 static inline
368 struct s3c24xx_dma_chan *to_s3c24xx_dma_chan(struct dma_chan *chan)
369 {
370         return container_of(chan, struct s3c24xx_dma_chan, vc.chan);
371 }
372 
373 static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan *s3cchan)
374 {
375         struct s3c24xx_dma_phy *phy = s3cchan->phy;
376         struct s3c24xx_txd *txd = s3cchan->at;
377         u32 tc = readl(phy->base + S3C24XX_DSTAT) & S3C24XX_DSTAT_CURRTC_MASK;
378 
379         return tc * txd->width;
380 }
381 
382 static int s3c24xx_dma_set_runtime_config(struct dma_chan *chan,
383                                   struct dma_slave_config *config)
384 {
385         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
386         unsigned long flags;
387         int ret = 0;
388 
389         /* Reject definitely invalid configurations */
390         if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
391             config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
392                 return -EINVAL;
393 
394         spin_lock_irqsave(&s3cchan->vc.lock, flags);
395 
396         if (!s3cchan->slave) {
397                 ret = -EINVAL;
398                 goto out;
399         }
400 
401         s3cchan->cfg = *config;
402 
403 out:
404         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
405         return ret;
406 }
407 
408 /*
409  * Transfer handling
410  */
411 
412 static inline
413 struct s3c24xx_txd *to_s3c24xx_txd(struct dma_async_tx_descriptor *tx)
414 {
415         return container_of(tx, struct s3c24xx_txd, vd.tx);
416 }
417 
418 static struct s3c24xx_txd *s3c24xx_dma_get_txd(void)
419 {
420         struct s3c24xx_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
421 
422         if (txd) {
423                 INIT_LIST_HEAD(&txd->dsg_list);
424                 txd->dcon = S3C24XX_DCON_INT | S3C24XX_DCON_NORELOAD;
425         }
426 
427         return txd;
428 }
429 
430 static void s3c24xx_dma_free_txd(struct s3c24xx_txd *txd)
431 {
432         struct s3c24xx_sg *dsg, *_dsg;
433 
434         list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
435                 list_del(&dsg->node);
436                 kfree(dsg);
437         }
438 
439         kfree(txd);
440 }
441 
442 static void s3c24xx_dma_start_next_sg(struct s3c24xx_dma_chan *s3cchan,
443                                        struct s3c24xx_txd *txd)
444 {
445         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
446         struct s3c24xx_dma_phy *phy = s3cchan->phy;
447         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
448         struct s3c24xx_sg *dsg = list_entry(txd->at, struct s3c24xx_sg, node);
449         u32 dcon = txd->dcon;
450         u32 val;
451 
452         /* transfer-size and -count from len and width */
453         switch (txd->width) {
454         case 1:
455                 dcon |= S3C24XX_DCON_DSZ_BYTE | dsg->len;
456                 break;
457         case 2:
458                 dcon |= S3C24XX_DCON_DSZ_HALFWORD | (dsg->len / 2);
459                 break;
460         case 4:
461                 dcon |= S3C24XX_DCON_DSZ_WORD | (dsg->len / 4);
462                 break;
463         }
464 
465         if (s3cchan->slave) {
466                 struct s3c24xx_dma_channel *cdata =
467                                         &pdata->channels[s3cchan->id];
468 
469                 if (s3cdma->sdata->has_reqsel) {
470                         writel_relaxed((cdata->chansel << 1) |
471                                                         S3C24XX_DMAREQSEL_HW,
472                                         phy->base + S3C24XX_DMAREQSEL);
473                 } else {
474                         int csel = cdata->chansel >> (phy->id *
475                                                         S3C24XX_CHANSEL_WIDTH);
476 
477                         csel &= S3C24XX_CHANSEL_REQ_MASK;
478                         dcon |= csel << S3C24XX_DCON_HWSRC_SHIFT;
479                         dcon |= S3C24XX_DCON_HWTRIG;
480                 }
481         } else {
482                 if (s3cdma->sdata->has_reqsel)
483                         writel_relaxed(0, phy->base + S3C24XX_DMAREQSEL);
484         }
485 
486         writel_relaxed(dsg->src_addr, phy->base + S3C24XX_DISRC);
487         writel_relaxed(txd->disrcc, phy->base + S3C24XX_DISRCC);
488         writel_relaxed(dsg->dst_addr, phy->base + S3C24XX_DIDST);
489         writel_relaxed(txd->didstc, phy->base + S3C24XX_DIDSTC);
490         writel_relaxed(dcon, phy->base + S3C24XX_DCON);
491 
492         val = readl_relaxed(phy->base + S3C24XX_DMASKTRIG);
493         val &= ~S3C24XX_DMASKTRIG_STOP;
494         val |= S3C24XX_DMASKTRIG_ON;
495 
496         /* trigger the dma operation for memcpy transfers */
497         if (!s3cchan->slave)
498                 val |= S3C24XX_DMASKTRIG_SWTRIG;
499 
500         writel(val, phy->base + S3C24XX_DMASKTRIG);
501 }
502 
503 /*
504  * Set the initial DMA register values and start first sg.
505  */
506 static void s3c24xx_dma_start_next_txd(struct s3c24xx_dma_chan *s3cchan)
507 {
508         struct s3c24xx_dma_phy *phy = s3cchan->phy;
509         struct virt_dma_desc *vd = vchan_next_desc(&s3cchan->vc);
510         struct s3c24xx_txd *txd = to_s3c24xx_txd(&vd->tx);
511 
512         list_del(&txd->vd.node);
513 
514         s3cchan->at = txd;
515 
516         /* Wait for channel inactive */
517         while (s3c24xx_dma_phy_busy(phy))
518                 cpu_relax();
519 
520         /* point to the first element of the sg list */
521         txd->at = txd->dsg_list.next;
522         s3c24xx_dma_start_next_sg(s3cchan, txd);
523 }
524 
525 static void s3c24xx_dma_free_txd_list(struct s3c24xx_dma_engine *s3cdma,
526                                 struct s3c24xx_dma_chan *s3cchan)
527 {
528         LIST_HEAD(head);
529 
530         vchan_get_all_descriptors(&s3cchan->vc, &head);
531         vchan_dma_desc_free_list(&s3cchan->vc, &head);
532 }
533 
534 /*
535  * Try to allocate a physical channel.  When successful, assign it to
536  * this virtual channel, and initiate the next descriptor.  The
537  * virtual channel lock must be held at this point.
538  */
539 static void s3c24xx_dma_phy_alloc_and_start(struct s3c24xx_dma_chan *s3cchan)
540 {
541         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
542         struct s3c24xx_dma_phy *phy;
543 
544         phy = s3c24xx_dma_get_phy(s3cchan);
545         if (!phy) {
546                 dev_dbg(&s3cdma->pdev->dev, "no physical channel available for xfer on %s\n",
547                         s3cchan->name);
548                 s3cchan->state = S3C24XX_DMA_CHAN_WAITING;
549                 return;
550         }
551 
552         dev_dbg(&s3cdma->pdev->dev, "allocated physical channel %d for xfer on %s\n",
553                 phy->id, s3cchan->name);
554 
555         s3cchan->phy = phy;
556         s3cchan->state = S3C24XX_DMA_CHAN_RUNNING;
557 
558         s3c24xx_dma_start_next_txd(s3cchan);
559 }
560 
561 static void s3c24xx_dma_phy_reassign_start(struct s3c24xx_dma_phy *phy,
562         struct s3c24xx_dma_chan *s3cchan)
563 {
564         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
565 
566         dev_dbg(&s3cdma->pdev->dev, "reassigned physical channel %d for xfer on %s\n",
567                 phy->id, s3cchan->name);
568 
569         /*
570          * We do this without taking the lock; we're really only concerned
571          * about whether this pointer is NULL or not, and we're guaranteed
572          * that this will only be called when it _already_ is non-NULL.
573          */
574         phy->serving = s3cchan;
575         s3cchan->phy = phy;
576         s3cchan->state = S3C24XX_DMA_CHAN_RUNNING;
577         s3c24xx_dma_start_next_txd(s3cchan);
578 }
579 
580 /*
581  * Free a physical DMA channel, potentially reallocating it to another
582  * virtual channel if we have any pending.
583  */
584 static void s3c24xx_dma_phy_free(struct s3c24xx_dma_chan *s3cchan)
585 {
586         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
587         struct s3c24xx_dma_chan *p, *next;
588 
589 retry:
590         next = NULL;
591 
592         /* Find a waiting virtual channel for the next transfer. */
593         list_for_each_entry(p, &s3cdma->memcpy.channels, vc.chan.device_node)
594                 if (p->state == S3C24XX_DMA_CHAN_WAITING) {
595                         next = p;
596                         break;
597                 }
598 
599         if (!next) {
600                 list_for_each_entry(p, &s3cdma->slave.channels,
601                                     vc.chan.device_node)
602                         if (p->state == S3C24XX_DMA_CHAN_WAITING &&
603                                       s3c24xx_dma_phy_valid(p, s3cchan->phy)) {
604                                 next = p;
605                                 break;
606                         }
607         }
608 
609         /* Ensure that the physical channel is stopped */
610         s3c24xx_dma_terminate_phy(s3cchan->phy);
611 
612         if (next) {
613                 bool success;
614 
615                 /*
616                  * Eww.  We know this isn't going to deadlock
617                  * but lockdep probably doesn't.
618                  */
619                 spin_lock(&next->vc.lock);
620                 /* Re-check the state now that we have the lock */
621                 success = next->state == S3C24XX_DMA_CHAN_WAITING;
622                 if (success)
623                         s3c24xx_dma_phy_reassign_start(s3cchan->phy, next);
624                 spin_unlock(&next->vc.lock);
625 
626                 /* If the state changed, try to find another channel */
627                 if (!success)
628                         goto retry;
629         } else {
630                 /* No more jobs, so free up the physical channel */
631                 s3c24xx_dma_put_phy(s3cchan->phy);
632         }
633 
634         s3cchan->phy = NULL;
635         s3cchan->state = S3C24XX_DMA_CHAN_IDLE;
636 }
637 
638 static void s3c24xx_dma_desc_free(struct virt_dma_desc *vd)
639 {
640         struct s3c24xx_txd *txd = to_s3c24xx_txd(&vd->tx);
641         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(vd->tx.chan);
642 
643         if (!s3cchan->slave)
644                 dma_descriptor_unmap(&vd->tx);
645 
646         s3c24xx_dma_free_txd(txd);
647 }
648 
649 static irqreturn_t s3c24xx_dma_irq(int irq, void *data)
650 {
651         struct s3c24xx_dma_phy *phy = data;
652         struct s3c24xx_dma_chan *s3cchan = phy->serving;
653         struct s3c24xx_txd *txd;
654 
655         dev_dbg(&phy->host->pdev->dev, "interrupt on channel %d\n", phy->id);
656 
657         /*
658          * Interrupts happen to notify the completion of a transfer and the
659          * channel should have moved into its stop state already on its own.
660          * Therefore interrupts on channels not bound to a virtual channel
661          * should never happen. Nevertheless send a terminate command to the
662          * channel if the unlikely case happens.
663          */
664         if (unlikely(!s3cchan)) {
665                 dev_err(&phy->host->pdev->dev, "interrupt on unused channel %d\n",
666                         phy->id);
667 
668                 s3c24xx_dma_terminate_phy(phy);
669 
670                 return IRQ_HANDLED;
671         }
672 
673         spin_lock(&s3cchan->vc.lock);
674         txd = s3cchan->at;
675         if (txd) {
676                 /* when more sg's are in this txd, start the next one */
677                 if (!list_is_last(txd->at, &txd->dsg_list)) {
678                         txd->at = txd->at->next;
679                         if (txd->cyclic)
680                                 vchan_cyclic_callback(&txd->vd);
681                         s3c24xx_dma_start_next_sg(s3cchan, txd);
682                 } else if (!txd->cyclic) {
683                         s3cchan->at = NULL;
684                         vchan_cookie_complete(&txd->vd);
685 
686                         /*
687                          * And start the next descriptor (if any),
688                          * otherwise free this channel.
689                          */
690                         if (vchan_next_desc(&s3cchan->vc))
691                                 s3c24xx_dma_start_next_txd(s3cchan);
692                         else
693                                 s3c24xx_dma_phy_free(s3cchan);
694                 } else {
695                         vchan_cyclic_callback(&txd->vd);
696 
697                         /* Cyclic: reset at beginning */
698                         txd->at = txd->dsg_list.next;
699                         s3c24xx_dma_start_next_sg(s3cchan, txd);
700                 }
701         }
702         spin_unlock(&s3cchan->vc.lock);
703 
704         return IRQ_HANDLED;
705 }
706 
707 /*
708  * The DMA ENGINE API
709  */
710 
711 static int s3c24xx_dma_terminate_all(struct dma_chan *chan)
712 {
713         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
714         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
715         unsigned long flags;
716         int ret = 0;
717 
718         spin_lock_irqsave(&s3cchan->vc.lock, flags);
719 
720         if (!s3cchan->phy && !s3cchan->at) {
721                 dev_err(&s3cdma->pdev->dev, "trying to terminate already stopped channel %d\n",
722                         s3cchan->id);
723                 ret = -EINVAL;
724                 goto unlock;
725         }
726 
727         s3cchan->state = S3C24XX_DMA_CHAN_IDLE;
728 
729         /* Mark physical channel as free */
730         if (s3cchan->phy)
731                 s3c24xx_dma_phy_free(s3cchan);
732 
733         /* Dequeue current job */
734         if (s3cchan->at) {
735                 s3c24xx_dma_desc_free(&s3cchan->at->vd);
736                 s3cchan->at = NULL;
737         }
738 
739         /* Dequeue jobs not yet fired as well */
740         s3c24xx_dma_free_txd_list(s3cdma, s3cchan);
741 unlock:
742         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
743 
744         return ret;
745 }
746 
747 static void s3c24xx_dma_free_chan_resources(struct dma_chan *chan)
748 {
749         /* Ensure all queued descriptors are freed */
750         vchan_free_chan_resources(to_virt_chan(chan));
751 }
752 
753 static enum dma_status s3c24xx_dma_tx_status(struct dma_chan *chan,
754                 dma_cookie_t cookie, struct dma_tx_state *txstate)
755 {
756         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
757         struct s3c24xx_txd *txd;
758         struct s3c24xx_sg *dsg;
759         struct virt_dma_desc *vd;
760         unsigned long flags;
761         enum dma_status ret;
762         size_t bytes = 0;
763 
764         spin_lock_irqsave(&s3cchan->vc.lock, flags);
765         ret = dma_cookie_status(chan, cookie, txstate);
766 
767         /*
768          * There's no point calculating the residue if there's
769          * no txstate to store the value.
770          */
771         if (ret == DMA_COMPLETE || !txstate) {
772                 spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
773                 return ret;
774         }
775 
776         vd = vchan_find_desc(&s3cchan->vc, cookie);
777         if (vd) {
778                 /* On the issued list, so hasn't been processed yet */
779                 txd = to_s3c24xx_txd(&vd->tx);
780 
781                 list_for_each_entry(dsg, &txd->dsg_list, node)
782                         bytes += dsg->len;
783         } else {
784                 /*
785                  * Currently running, so sum over the pending sg's and
786                  * the currently active one.
787                  */
788                 txd = s3cchan->at;
789 
790                 dsg = list_entry(txd->at, struct s3c24xx_sg, node);
791                 list_for_each_entry_from(dsg, &txd->dsg_list, node)
792                         bytes += dsg->len;
793 
794                 bytes += s3c24xx_dma_getbytes_chan(s3cchan);
795         }
796         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
797 
798         /*
799          * This cookie not complete yet
800          * Get number of bytes left in the active transactions and queue
801          */
802         dma_set_residue(txstate, bytes);
803 
804         /* Whether waiting or running, we're in progress */
805         return ret;
806 }
807 
808 /*
809  * Initialize a descriptor to be used by memcpy submit
810  */
811 static struct dma_async_tx_descriptor *s3c24xx_dma_prep_memcpy(
812                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
813                 size_t len, unsigned long flags)
814 {
815         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
816         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
817         struct s3c24xx_txd *txd;
818         struct s3c24xx_sg *dsg;
819         int src_mod, dest_mod;
820 
821         dev_dbg(&s3cdma->pdev->dev, "prepare memcpy of %zu bytes from %s\n",
822                         len, s3cchan->name);
823 
824         if ((len & S3C24XX_DCON_TC_MASK) != len) {
825                 dev_err(&s3cdma->pdev->dev, "memcpy size %zu to large\n", len);
826                 return NULL;
827         }
828 
829         txd = s3c24xx_dma_get_txd();
830         if (!txd)
831                 return NULL;
832 
833         dsg = kzalloc(sizeof(*dsg), GFP_NOWAIT);
834         if (!dsg) {
835                 s3c24xx_dma_free_txd(txd);
836                 return NULL;
837         }
838         list_add_tail(&dsg->node, &txd->dsg_list);
839 
840         dsg->src_addr = src;
841         dsg->dst_addr = dest;
842         dsg->len = len;
843 
844         /*
845          * Determine a suitable transfer width.
846          * The DMA controller cannot fetch/store information which is not
847          * naturally aligned on the bus, i.e., a 4 byte fetch must start at
848          * an address divisible by 4 - more generally addr % width must be 0.
849          */
850         src_mod = src % 4;
851         dest_mod = dest % 4;
852         switch (len % 4) {
853         case 0:
854                 txd->width = (src_mod == 0 && dest_mod == 0) ? 4 : 1;
855                 break;
856         case 2:
857                 txd->width = ((src_mod == 2 || src_mod == 0) &&
858                               (dest_mod == 2 || dest_mod == 0)) ? 2 : 1;
859                 break;
860         default:
861                 txd->width = 1;
862                 break;
863         }
864 
865         txd->disrcc = S3C24XX_DISRCC_LOC_AHB | S3C24XX_DISRCC_INC_INCREMENT;
866         txd->didstc = S3C24XX_DIDSTC_LOC_AHB | S3C24XX_DIDSTC_INC_INCREMENT;
867         txd->dcon |= S3C24XX_DCON_DEMAND | S3C24XX_DCON_SYNC_HCLK |
868                      S3C24XX_DCON_SERV_WHOLE;
869 
870         return vchan_tx_prep(&s3cchan->vc, &txd->vd, flags);
871 }
872 
873 static struct dma_async_tx_descriptor *s3c24xx_dma_prep_dma_cyclic(
874         struct dma_chan *chan, dma_addr_t addr, size_t size, size_t period,
875         enum dma_transfer_direction direction, unsigned long flags)
876 {
877         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
878         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
879         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
880         struct s3c24xx_dma_channel *cdata = &pdata->channels[s3cchan->id];
881         struct s3c24xx_txd *txd;
882         struct s3c24xx_sg *dsg;
883         unsigned sg_len;
884         dma_addr_t slave_addr;
885         u32 hwcfg = 0;
886         int i;
887 
888         dev_dbg(&s3cdma->pdev->dev,
889                 "prepare cyclic transaction of %zu bytes with period %zu from %s\n",
890                 size, period, s3cchan->name);
891 
892         if (!is_slave_direction(direction)) {
893                 dev_err(&s3cdma->pdev->dev,
894                         "direction %d unsupported\n", direction);
895                 return NULL;
896         }
897 
898         txd = s3c24xx_dma_get_txd();
899         if (!txd)
900                 return NULL;
901 
902         txd->cyclic = 1;
903 
904         if (cdata->handshake)
905                 txd->dcon |= S3C24XX_DCON_HANDSHAKE;
906 
907         switch (cdata->bus) {
908         case S3C24XX_DMA_APB:
909                 txd->dcon |= S3C24XX_DCON_SYNC_PCLK;
910                 hwcfg |= S3C24XX_DISRCC_LOC_APB;
911                 break;
912         case S3C24XX_DMA_AHB:
913                 txd->dcon |= S3C24XX_DCON_SYNC_HCLK;
914                 hwcfg |= S3C24XX_DISRCC_LOC_AHB;
915                 break;
916         }
917 
918         /*
919          * Always assume our peripheral desintation is a fixed
920          * address in memory.
921          */
922         hwcfg |= S3C24XX_DISRCC_INC_FIXED;
923 
924         /*
925          * Individual dma operations are requested by the slave,
926          * so serve only single atomic operations (S3C24XX_DCON_SERV_SINGLE).
927          */
928         txd->dcon |= S3C24XX_DCON_SERV_SINGLE;
929 
930         if (direction == DMA_MEM_TO_DEV) {
931                 txd->disrcc = S3C24XX_DISRCC_LOC_AHB |
932                               S3C24XX_DISRCC_INC_INCREMENT;
933                 txd->didstc = hwcfg;
934                 slave_addr = s3cchan->cfg.dst_addr;
935                 txd->width = s3cchan->cfg.dst_addr_width;
936         } else {
937                 txd->disrcc = hwcfg;
938                 txd->didstc = S3C24XX_DIDSTC_LOC_AHB |
939                               S3C24XX_DIDSTC_INC_INCREMENT;
940                 slave_addr = s3cchan->cfg.src_addr;
941                 txd->width = s3cchan->cfg.src_addr_width;
942         }
943 
944         sg_len = size / period;
945 
946         for (i = 0; i < sg_len; i++) {
947                 dsg = kzalloc(sizeof(*dsg), GFP_NOWAIT);
948                 if (!dsg) {
949                         s3c24xx_dma_free_txd(txd);
950                         return NULL;
951                 }
952                 list_add_tail(&dsg->node, &txd->dsg_list);
953 
954                 dsg->len = period;
955                 /* Check last period length */
956                 if (i == sg_len - 1)
957                         dsg->len = size - period * i;
958                 if (direction == DMA_MEM_TO_DEV) {
959                         dsg->src_addr = addr + period * i;
960                         dsg->dst_addr = slave_addr;
961                 } else { /* DMA_DEV_TO_MEM */
962                         dsg->src_addr = slave_addr;
963                         dsg->dst_addr = addr + period * i;
964                 }
965         }
966 
967         return vchan_tx_prep(&s3cchan->vc, &txd->vd, flags);
968 }
969 
970 static struct dma_async_tx_descriptor *s3c24xx_dma_prep_slave_sg(
971                 struct dma_chan *chan, struct scatterlist *sgl,
972                 unsigned int sg_len, enum dma_transfer_direction direction,
973                 unsigned long flags, void *context)
974 {
975         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
976         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
977         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
978         struct s3c24xx_dma_channel *cdata = &pdata->channels[s3cchan->id];
979         struct s3c24xx_txd *txd;
980         struct s3c24xx_sg *dsg;
981         struct scatterlist *sg;
982         dma_addr_t slave_addr;
983         u32 hwcfg = 0;
984         int tmp;
985 
986         dev_dbg(&s3cdma->pdev->dev, "prepare transaction of %d bytes from %s\n",
987                         sg_dma_len(sgl), s3cchan->name);
988 
989         txd = s3c24xx_dma_get_txd();
990         if (!txd)
991                 return NULL;
992 
993         if (cdata->handshake)
994                 txd->dcon |= S3C24XX_DCON_HANDSHAKE;
995 
996         switch (cdata->bus) {
997         case S3C24XX_DMA_APB:
998                 txd->dcon |= S3C24XX_DCON_SYNC_PCLK;
999                 hwcfg |= S3C24XX_DISRCC_LOC_APB;
1000                 break;
1001         case S3C24XX_DMA_AHB:
1002                 txd->dcon |= S3C24XX_DCON_SYNC_HCLK;
1003                 hwcfg |= S3C24XX_DISRCC_LOC_AHB;
1004                 break;
1005         }
1006 
1007         /*
1008          * Always assume our peripheral desintation is a fixed
1009          * address in memory.
1010          */
1011         hwcfg |= S3C24XX_DISRCC_INC_FIXED;
1012 
1013         /*
1014          * Individual dma operations are requested by the slave,
1015          * so serve only single atomic operations (S3C24XX_DCON_SERV_SINGLE).
1016          */
1017         txd->dcon |= S3C24XX_DCON_SERV_SINGLE;
1018 
1019         if (direction == DMA_MEM_TO_DEV) {
1020                 txd->disrcc = S3C24XX_DISRCC_LOC_AHB |
1021                               S3C24XX_DISRCC_INC_INCREMENT;
1022                 txd->didstc = hwcfg;
1023                 slave_addr = s3cchan->cfg.dst_addr;
1024                 txd->width = s3cchan->cfg.dst_addr_width;
1025         } else if (direction == DMA_DEV_TO_MEM) {
1026                 txd->disrcc = hwcfg;
1027                 txd->didstc = S3C24XX_DIDSTC_LOC_AHB |
1028                               S3C24XX_DIDSTC_INC_INCREMENT;
1029                 slave_addr = s3cchan->cfg.src_addr;
1030                 txd->width = s3cchan->cfg.src_addr_width;
1031         } else {
1032                 s3c24xx_dma_free_txd(txd);
1033                 dev_err(&s3cdma->pdev->dev,
1034                         "direction %d unsupported\n", direction);
1035                 return NULL;
1036         }
1037 
1038         for_each_sg(sgl, sg, sg_len, tmp) {
1039                 dsg = kzalloc(sizeof(*dsg), GFP_NOWAIT);
1040                 if (!dsg) {
1041                         s3c24xx_dma_free_txd(txd);
1042                         return NULL;
1043                 }
1044                 list_add_tail(&dsg->node, &txd->dsg_list);
1045 
1046                 dsg->len = sg_dma_len(sg);
1047                 if (direction == DMA_MEM_TO_DEV) {
1048                         dsg->src_addr = sg_dma_address(sg);
1049                         dsg->dst_addr = slave_addr;
1050                 } else { /* DMA_DEV_TO_MEM */
1051                         dsg->src_addr = slave_addr;
1052                         dsg->dst_addr = sg_dma_address(sg);
1053                 }
1054         }
1055 
1056         return vchan_tx_prep(&s3cchan->vc, &txd->vd, flags);
1057 }
1058 
1059 /*
1060  * Slave transactions callback to the slave device to allow
1061  * synchronization of slave DMA signals with the DMAC enable
1062  */
1063 static void s3c24xx_dma_issue_pending(struct dma_chan *chan)
1064 {
1065         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
1066         unsigned long flags;
1067 
1068         spin_lock_irqsave(&s3cchan->vc.lock, flags);
1069         if (vchan_issue_pending(&s3cchan->vc)) {
1070                 if (!s3cchan->phy && s3cchan->state != S3C24XX_DMA_CHAN_WAITING)
1071                         s3c24xx_dma_phy_alloc_and_start(s3cchan);
1072         }
1073         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
1074 }
1075 
1076 /*
1077  * Bringup and teardown
1078  */
1079 
1080 /*
1081  * Initialise the DMAC memcpy/slave channels.
1082  * Make a local wrapper to hold required data
1083  */
1084 static int s3c24xx_dma_init_virtual_channels(struct s3c24xx_dma_engine *s3cdma,
1085                 struct dma_device *dmadev, unsigned int channels, bool slave)
1086 {
1087         struct s3c24xx_dma_chan *chan;
1088         int i;
1089 
1090         INIT_LIST_HEAD(&dmadev->channels);
1091 
1092         /*
1093          * Register as many many memcpy as we have physical channels,
1094          * we won't always be able to use all but the code will have
1095          * to cope with that situation.
1096          */
1097         for (i = 0; i < channels; i++) {
1098                 chan = devm_kzalloc(dmadev->dev, sizeof(*chan), GFP_KERNEL);
1099                 if (!chan)
1100                         return -ENOMEM;
1101 
1102                 chan->id = i;
1103                 chan->host = s3cdma;
1104                 chan->state = S3C24XX_DMA_CHAN_IDLE;
1105 
1106                 if (slave) {
1107                         chan->slave = true;
1108                         chan->name = kasprintf(GFP_KERNEL, "slave%d", i);
1109                         if (!chan->name)
1110                                 return -ENOMEM;
1111                 } else {
1112                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1113                         if (!chan->name)
1114                                 return -ENOMEM;
1115                 }
1116                 dev_dbg(dmadev->dev,
1117                          "initialize virtual channel \"%s\"\n",
1118                          chan->name);
1119 
1120                 chan->vc.desc_free = s3c24xx_dma_desc_free;
1121                 vchan_init(&chan->vc, dmadev);
1122         }
1123         dev_info(dmadev->dev, "initialized %d virtual %s channels\n",
1124                  i, slave ? "slave" : "memcpy");
1125         return i;
1126 }
1127 
1128 static void s3c24xx_dma_free_virtual_channels(struct dma_device *dmadev)
1129 {
1130         struct s3c24xx_dma_chan *chan = NULL;
1131         struct s3c24xx_dma_chan *next;
1132 
1133         list_for_each_entry_safe(chan,
1134                                  next, &dmadev->channels, vc.chan.device_node) {
1135                 list_del(&chan->vc.chan.device_node);
1136                 tasklet_kill(&chan->vc.task);
1137         }
1138 }
1139 
1140 /* s3c2410, s3c2440 and s3c2442 have a 0x40 stride without separate clocks */
1141 static struct soc_data soc_s3c2410 = {
1142         .stride = 0x40,
1143         .has_reqsel = false,
1144         .has_clocks = false,
1145 };
1146 
1147 /* s3c2412 and s3c2413 have a 0x40 stride and dmareqsel mechanism */
1148 static struct soc_data soc_s3c2412 = {
1149         .stride = 0x40,
1150         .has_reqsel = true,
1151         .has_clocks = true,
1152 };
1153 
1154 /* s3c2443 and following have a 0x100 stride and dmareqsel mechanism */
1155 static struct soc_data soc_s3c2443 = {
1156         .stride = 0x100,
1157         .has_reqsel = true,
1158         .has_clocks = true,
1159 };
1160 
1161 static const struct platform_device_id s3c24xx_dma_driver_ids[] = {
1162         {
1163                 .name           = "s3c2410-dma",
1164                 .driver_data    = (kernel_ulong_t)&soc_s3c2410,
1165         }, {
1166                 .name           = "s3c2412-dma",
1167                 .driver_data    = (kernel_ulong_t)&soc_s3c2412,
1168         }, {
1169                 .name           = "s3c2443-dma",
1170                 .driver_data    = (kernel_ulong_t)&soc_s3c2443,
1171         },
1172         { },
1173 };
1174 
1175 static struct soc_data *s3c24xx_dma_get_soc_data(struct platform_device *pdev)
1176 {
1177         return (struct soc_data *)
1178                          platform_get_device_id(pdev)->driver_data;
1179 }
1180 
1181 static int s3c24xx_dma_probe(struct platform_device *pdev)
1182 {
1183         const struct s3c24xx_dma_platdata *pdata = dev_get_platdata(&pdev->dev);
1184         struct s3c24xx_dma_engine *s3cdma;
1185         struct soc_data *sdata;
1186         struct resource *res;
1187         int ret;
1188         int i;
1189 
1190         if (!pdata) {
1191                 dev_err(&pdev->dev, "platform data missing\n");
1192                 return -ENODEV;
1193         }
1194 
1195         /* Basic sanity check */
1196         if (pdata->num_phy_channels > MAX_DMA_CHANNELS) {
1197                 dev_err(&pdev->dev, "to many dma channels %d, max %d\n",
1198                         pdata->num_phy_channels, MAX_DMA_CHANNELS);
1199                 return -EINVAL;
1200         }
1201 
1202         sdata = s3c24xx_dma_get_soc_data(pdev);
1203         if (!sdata)
1204                 return -EINVAL;
1205 
1206         s3cdma = devm_kzalloc(&pdev->dev, sizeof(*s3cdma), GFP_KERNEL);
1207         if (!s3cdma)
1208                 return -ENOMEM;
1209 
1210         s3cdma->pdev = pdev;
1211         s3cdma->pdata = pdata;
1212         s3cdma->sdata = sdata;
1213 
1214         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1215         s3cdma->base = devm_ioremap_resource(&pdev->dev, res);
1216         if (IS_ERR(s3cdma->base))
1217                 return PTR_ERR(s3cdma->base);
1218 
1219         s3cdma->phy_chans = devm_kzalloc(&pdev->dev,
1220                                               sizeof(struct s3c24xx_dma_phy) *
1221                                                         pdata->num_phy_channels,
1222                                               GFP_KERNEL);
1223         if (!s3cdma->phy_chans)
1224                 return -ENOMEM;
1225 
1226         /* acquire irqs and clocks for all physical channels */
1227         for (i = 0; i < pdata->num_phy_channels; i++) {
1228                 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1229                 char clk_name[6];
1230 
1231                 phy->id = i;
1232                 phy->base = s3cdma->base + (i * sdata->stride);
1233                 phy->host = s3cdma;
1234 
1235                 phy->irq = platform_get_irq(pdev, i);
1236                 if (phy->irq < 0) {
1237                         dev_err(&pdev->dev, "failed to get irq %d, err %d\n",
1238                                 i, phy->irq);
1239                         continue;
1240                 }
1241 
1242                 ret = devm_request_irq(&pdev->dev, phy->irq, s3c24xx_dma_irq,
1243                                        0, pdev->name, phy);
1244                 if (ret) {
1245                         dev_err(&pdev->dev, "Unable to request irq for channel %d, error %d\n",
1246                                 i, ret);
1247                         continue;
1248                 }
1249 
1250                 if (sdata->has_clocks) {
1251                         sprintf(clk_name, "dma.%d", i);
1252                         phy->clk = devm_clk_get(&pdev->dev, clk_name);
1253                         if (IS_ERR(phy->clk) && sdata->has_clocks) {
1254                                 dev_err(&pdev->dev, "unable to acquire clock for channel %d, error %lu\n",
1255                                         i, PTR_ERR(phy->clk));
1256                                 continue;
1257                         }
1258 
1259                         ret = clk_prepare(phy->clk);
1260                         if (ret) {
1261                                 dev_err(&pdev->dev, "clock for phy %d failed, error %d\n",
1262                                         i, ret);
1263                                 continue;
1264                         }
1265                 }
1266 
1267                 spin_lock_init(&phy->lock);
1268                 phy->valid = true;
1269 
1270                 dev_dbg(&pdev->dev, "physical channel %d is %s\n",
1271                         i, s3c24xx_dma_phy_busy(phy) ? "BUSY" : "FREE");
1272         }
1273 
1274         /* Initialize memcpy engine */
1275         dma_cap_set(DMA_MEMCPY, s3cdma->memcpy.cap_mask);
1276         dma_cap_set(DMA_PRIVATE, s3cdma->memcpy.cap_mask);
1277         s3cdma->memcpy.dev = &pdev->dev;
1278         s3cdma->memcpy.device_free_chan_resources =
1279                                         s3c24xx_dma_free_chan_resources;
1280         s3cdma->memcpy.device_prep_dma_memcpy = s3c24xx_dma_prep_memcpy;
1281         s3cdma->memcpy.device_tx_status = s3c24xx_dma_tx_status;
1282         s3cdma->memcpy.device_issue_pending = s3c24xx_dma_issue_pending;
1283         s3cdma->memcpy.device_config = s3c24xx_dma_set_runtime_config;
1284         s3cdma->memcpy.device_terminate_all = s3c24xx_dma_terminate_all;
1285 
1286         /* Initialize slave engine for SoC internal dedicated peripherals */
1287         dma_cap_set(DMA_SLAVE, s3cdma->slave.cap_mask);
1288         dma_cap_set(DMA_CYCLIC, s3cdma->slave.cap_mask);
1289         dma_cap_set(DMA_PRIVATE, s3cdma->slave.cap_mask);
1290         s3cdma->slave.dev = &pdev->dev;
1291         s3cdma->slave.device_free_chan_resources =
1292                                         s3c24xx_dma_free_chan_resources;
1293         s3cdma->slave.device_tx_status = s3c24xx_dma_tx_status;
1294         s3cdma->slave.device_issue_pending = s3c24xx_dma_issue_pending;
1295         s3cdma->slave.device_prep_slave_sg = s3c24xx_dma_prep_slave_sg;
1296         s3cdma->slave.device_prep_dma_cyclic = s3c24xx_dma_prep_dma_cyclic;
1297         s3cdma->slave.device_config = s3c24xx_dma_set_runtime_config;
1298         s3cdma->slave.device_terminate_all = s3c24xx_dma_terminate_all;
1299         s3cdma->slave.filter.map = pdata->slave_map;
1300         s3cdma->slave.filter.mapcnt = pdata->slavecnt;
1301         s3cdma->slave.filter.fn = s3c24xx_dma_filter;
1302 
1303         /* Register as many memcpy channels as there are physical channels */
1304         ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->memcpy,
1305                                                 pdata->num_phy_channels, false);
1306         if (ret <= 0) {
1307                 dev_warn(&pdev->dev,
1308                          "%s failed to enumerate memcpy channels - %d\n",
1309                          __func__, ret);
1310                 goto err_memcpy;
1311         }
1312 
1313         /* Register slave channels */
1314         ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->slave,
1315                                 pdata->num_channels, true);
1316         if (ret <= 0) {
1317                 dev_warn(&pdev->dev,
1318                         "%s failed to enumerate slave channels - %d\n",
1319                                 __func__, ret);
1320                 goto err_slave;
1321         }
1322 
1323         ret = dma_async_device_register(&s3cdma->memcpy);
1324         if (ret) {
1325                 dev_warn(&pdev->dev,
1326                         "%s failed to register memcpy as an async device - %d\n",
1327                         __func__, ret);
1328                 goto err_memcpy_reg;
1329         }
1330 
1331         ret = dma_async_device_register(&s3cdma->slave);
1332         if (ret) {
1333                 dev_warn(&pdev->dev,
1334                         "%s failed to register slave as an async device - %d\n",
1335                         __func__, ret);
1336                 goto err_slave_reg;
1337         }
1338 
1339         platform_set_drvdata(pdev, s3cdma);
1340         dev_info(&pdev->dev, "Loaded dma driver with %d physical channels\n",
1341                  pdata->num_phy_channels);
1342 
1343         return 0;
1344 
1345 err_slave_reg:
1346         dma_async_device_unregister(&s3cdma->memcpy);
1347 err_memcpy_reg:
1348         s3c24xx_dma_free_virtual_channels(&s3cdma->slave);
1349 err_slave:
1350         s3c24xx_dma_free_virtual_channels(&s3cdma->memcpy);
1351 err_memcpy:
1352         if (sdata->has_clocks)
1353                 for (i = 0; i < pdata->num_phy_channels; i++) {
1354                         struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1355                         if (phy->valid)
1356                                 clk_unprepare(phy->clk);
1357                 }
1358 
1359         return ret;
1360 }
1361 
1362 static void s3c24xx_dma_free_irq(struct platform_device *pdev,
1363                                 struct s3c24xx_dma_engine *s3cdma)
1364 {
1365         int i;
1366 
1367         for (i = 0; i < s3cdma->pdata->num_phy_channels; i++) {
1368                 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1369 
1370                 devm_free_irq(&pdev->dev, phy->irq, phy);
1371         }
1372 }
1373 
1374 static int s3c24xx_dma_remove(struct platform_device *pdev)
1375 {
1376         const struct s3c24xx_dma_platdata *pdata = dev_get_platdata(&pdev->dev);
1377         struct s3c24xx_dma_engine *s3cdma = platform_get_drvdata(pdev);
1378         struct soc_data *sdata = s3c24xx_dma_get_soc_data(pdev);
1379         int i;
1380 
1381         dma_async_device_unregister(&s3cdma->slave);
1382         dma_async_device_unregister(&s3cdma->memcpy);
1383 
1384         s3c24xx_dma_free_irq(pdev, s3cdma);
1385 
1386         s3c24xx_dma_free_virtual_channels(&s3cdma->slave);
1387         s3c24xx_dma_free_virtual_channels(&s3cdma->memcpy);
1388 
1389         if (sdata->has_clocks)
1390                 for (i = 0; i < pdata->num_phy_channels; i++) {
1391                         struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1392                         if (phy->valid)
1393                                 clk_unprepare(phy->clk);
1394                 }
1395 
1396         return 0;
1397 }
1398 
1399 static struct platform_driver s3c24xx_dma_driver = {
1400         .driver         = {
1401                 .name   = "s3c24xx-dma",
1402         },
1403         .id_table       = s3c24xx_dma_driver_ids,
1404         .probe          = s3c24xx_dma_probe,
1405         .remove         = s3c24xx_dma_remove,
1406 };
1407 
1408 module_platform_driver(s3c24xx_dma_driver);
1409 
1410 bool s3c24xx_dma_filter(struct dma_chan *chan, void *param)
1411 {
1412         struct s3c24xx_dma_chan *s3cchan;
1413 
1414         if (chan->device->dev->driver != &s3c24xx_dma_driver.driver)
1415                 return false;
1416 
1417         s3cchan = to_s3c24xx_dma_chan(chan);
1418 
1419         return s3cchan->id == (uintptr_t)param;
1420 }
1421 EXPORT_SYMBOL(s3c24xx_dma_filter);
1422 
1423 MODULE_DESCRIPTION("S3C24XX DMA Driver");
1424 MODULE_AUTHOR("Heiko Stuebner");
1425 MODULE_LICENSE("GPL v2");
1426 

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