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Linux/drivers/dma/s3c24xx-dma.c

  1 /*
  2  * S3C24XX DMA handling
  3  *
  4  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  5  *
  6  * based on amba-pl08x.c
  7  *
  8  * Copyright (c) 2006 ARM Ltd.
  9  * Copyright (c) 2010 ST-Ericsson SA
 10  *
 11  * Author: Peter Pearse <peter.pearse@arm.com>
 12  * Author: Linus Walleij <linus.walleij@stericsson.com>
 13  *
 14  * This program is free software; you can redistribute it and/or modify it
 15  * under the terms of the GNU General Public License as published by the Free
 16  * Software Foundation; either version 2 of the License, or (at your option)
 17  * any later version.
 18  *
 19  * The DMA controllers in S3C24XX SoCs have a varying number of DMA signals
 20  * that can be routed to any of the 4 to 8 hardware-channels.
 21  *
 22  * Therefore on these DMA controllers the number of channels
 23  * and the number of incoming DMA signals are two totally different things.
 24  * It is usually not possible to theoretically handle all physical signals,
 25  * so a multiplexing scheme with possible denial of use is necessary.
 26  *
 27  * Open items:
 28  * - bursts
 29  */
 30 
 31 #include <linux/platform_device.h>
 32 #include <linux/types.h>
 33 #include <linux/dmaengine.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/interrupt.h>
 36 #include <linux/clk.h>
 37 #include <linux/module.h>
 38 #include <linux/slab.h>
 39 #include <linux/platform_data/dma-s3c24xx.h>
 40 
 41 #include "dmaengine.h"
 42 #include "virt-dma.h"
 43 
 44 #define MAX_DMA_CHANNELS        8
 45 
 46 #define S3C24XX_DISRC                   0x00
 47 #define S3C24XX_DISRCC                  0x04
 48 #define S3C24XX_DISRCC_INC_INCREMENT    0
 49 #define S3C24XX_DISRCC_INC_FIXED        BIT(0)
 50 #define S3C24XX_DISRCC_LOC_AHB          0
 51 #define S3C24XX_DISRCC_LOC_APB          BIT(1)
 52 
 53 #define S3C24XX_DIDST                   0x08
 54 #define S3C24XX_DIDSTC                  0x0c
 55 #define S3C24XX_DIDSTC_INC_INCREMENT    0
 56 #define S3C24XX_DIDSTC_INC_FIXED        BIT(0)
 57 #define S3C24XX_DIDSTC_LOC_AHB          0
 58 #define S3C24XX_DIDSTC_LOC_APB          BIT(1)
 59 #define S3C24XX_DIDSTC_INT_TC0          0
 60 #define S3C24XX_DIDSTC_INT_RELOAD       BIT(2)
 61 
 62 #define S3C24XX_DCON                    0x10
 63 
 64 #define S3C24XX_DCON_TC_MASK            0xfffff
 65 #define S3C24XX_DCON_DSZ_BYTE           (0 << 20)
 66 #define S3C24XX_DCON_DSZ_HALFWORD       (1 << 20)
 67 #define S3C24XX_DCON_DSZ_WORD           (2 << 20)
 68 #define S3C24XX_DCON_DSZ_MASK           (3 << 20)
 69 #define S3C24XX_DCON_DSZ_SHIFT          20
 70 #define S3C24XX_DCON_AUTORELOAD         0
 71 #define S3C24XX_DCON_NORELOAD           BIT(22)
 72 #define S3C24XX_DCON_HWTRIG             BIT(23)
 73 #define S3C24XX_DCON_HWSRC_SHIFT        24
 74 #define S3C24XX_DCON_SERV_SINGLE        0
 75 #define S3C24XX_DCON_SERV_WHOLE         BIT(27)
 76 #define S3C24XX_DCON_TSZ_UNIT           0
 77 #define S3C24XX_DCON_TSZ_BURST4         BIT(28)
 78 #define S3C24XX_DCON_INT                BIT(29)
 79 #define S3C24XX_DCON_SYNC_PCLK          0
 80 #define S3C24XX_DCON_SYNC_HCLK          BIT(30)
 81 #define S3C24XX_DCON_DEMAND             0
 82 #define S3C24XX_DCON_HANDSHAKE          BIT(31)
 83 
 84 #define S3C24XX_DSTAT                   0x14
 85 #define S3C24XX_DSTAT_STAT_BUSY         BIT(20)
 86 #define S3C24XX_DSTAT_CURRTC_MASK       0xfffff
 87 
 88 #define S3C24XX_DMASKTRIG               0x20
 89 #define S3C24XX_DMASKTRIG_SWTRIG        BIT(0)
 90 #define S3C24XX_DMASKTRIG_ON            BIT(1)
 91 #define S3C24XX_DMASKTRIG_STOP          BIT(2)
 92 
 93 #define S3C24XX_DMAREQSEL               0x24
 94 #define S3C24XX_DMAREQSEL_HW            BIT(0)
 95 
 96 /*
 97  * S3C2410, S3C2440 and S3C2442 SoCs cannot select any physical channel
 98  * for a DMA source. Instead only specific channels are valid.
 99  * All of these SoCs have 4 physical channels and the number of request
100  * source bits is 3. Additionally we also need 1 bit to mark the channel
101  * as valid.
102  * Therefore we separate the chansel element of the channel data into 4
103  * parts of 4 bits each, to hold the information if the channel is valid
104  * and the hw request source to use.
105  *
106  * Example:
107  * SDI is valid on channels 0, 2 and 3 - with varying hw request sources.
108  * For it the chansel field would look like
109  *
110  * ((BIT(3) | 1) << 3 * 4) | // channel 3, with request source 1
111  * ((BIT(3) | 2) << 2 * 4) | // channel 2, with request source 2
112  * ((BIT(3) | 2) << 0 * 4)   // channel 0, with request source 2
113  */
114 #define S3C24XX_CHANSEL_WIDTH           4
115 #define S3C24XX_CHANSEL_VALID           BIT(3)
116 #define S3C24XX_CHANSEL_REQ_MASK        7
117 
118 /*
119  * struct soc_data - vendor-specific config parameters for individual SoCs
120  * @stride: spacing between the registers of each channel
121  * @has_reqsel: does the controller use the newer requestselection mechanism
122  * @has_clocks: are controllable dma-clocks present
123  */
124 struct soc_data {
125         int stride;
126         bool has_reqsel;
127         bool has_clocks;
128 };
129 
130 /*
131  * enum s3c24xx_dma_chan_state - holds the virtual channel states
132  * @S3C24XX_DMA_CHAN_IDLE: the channel is idle
133  * @S3C24XX_DMA_CHAN_RUNNING: the channel has allocated a physical transport
134  * channel and is running a transfer on it
135  * @S3C24XX_DMA_CHAN_WAITING: the channel is waiting for a physical transport
136  * channel to become available (only pertains to memcpy channels)
137  */
138 enum s3c24xx_dma_chan_state {
139         S3C24XX_DMA_CHAN_IDLE,
140         S3C24XX_DMA_CHAN_RUNNING,
141         S3C24XX_DMA_CHAN_WAITING,
142 };
143 
144 /*
145  * struct s3c24xx_sg - structure containing data per sg
146  * @src_addr: src address of sg
147  * @dst_addr: dst address of sg
148  * @len: transfer len in bytes
149  * @node: node for txd's dsg_list
150  */
151 struct s3c24xx_sg {
152         dma_addr_t src_addr;
153         dma_addr_t dst_addr;
154         size_t len;
155         struct list_head node;
156 };
157 
158 /*
159  * struct s3c24xx_txd - wrapper for struct dma_async_tx_descriptor
160  * @vd: virtual DMA descriptor
161  * @dsg_list: list of children sg's
162  * @at: sg currently being transfered
163  * @width: transfer width
164  * @disrcc: value for source control register
165  * @didstc: value for destination control register
166  * @dcon: base value for dcon register
167  * @cyclic: indicate cyclic transfer
168  */
169 struct s3c24xx_txd {
170         struct virt_dma_desc vd;
171         struct list_head dsg_list;
172         struct list_head *at;
173         u8 width;
174         u32 disrcc;
175         u32 didstc;
176         u32 dcon;
177         bool cyclic;
178 };
179 
180 struct s3c24xx_dma_chan;
181 
182 /*
183  * struct s3c24xx_dma_phy - holder for the physical channels
184  * @id: physical index to this channel
185  * @valid: does the channel have all required elements
186  * @base: virtual memory base (remapped) for the this channel
187  * @irq: interrupt for this channel
188  * @clk: clock for this channel
189  * @lock: a lock to use when altering an instance of this struct
190  * @serving: virtual channel currently being served by this physicalchannel
191  * @host: a pointer to the host (internal use)
192  */
193 struct s3c24xx_dma_phy {
194         unsigned int                    id;
195         bool                            valid;
196         void __iomem                    *base;
197         int                             irq;
198         struct clk                      *clk;
199         spinlock_t                      lock;
200         struct s3c24xx_dma_chan         *serving;
201         struct s3c24xx_dma_engine       *host;
202 };
203 
204 /*
205  * struct s3c24xx_dma_chan - this structure wraps a DMA ENGINE channel
206  * @id: the id of the channel
207  * @name: name of the channel
208  * @vc: wrappped virtual channel
209  * @phy: the physical channel utilized by this channel, if there is one
210  * @runtime_addr: address for RX/TX according to the runtime config
211  * @at: active transaction on this channel
212  * @lock: a lock for this channel data
213  * @host: a pointer to the host (internal use)
214  * @state: whether the channel is idle, running etc
215  * @slave: whether this channel is a device (slave) or for memcpy
216  */
217 struct s3c24xx_dma_chan {
218         int id;
219         const char *name;
220         struct virt_dma_chan vc;
221         struct s3c24xx_dma_phy *phy;
222         struct dma_slave_config cfg;
223         struct s3c24xx_txd *at;
224         struct s3c24xx_dma_engine *host;
225         enum s3c24xx_dma_chan_state state;
226         bool slave;
227 };
228 
229 /*
230  * struct s3c24xx_dma_engine - the local state holder for the S3C24XX
231  * @pdev: the corresponding platform device
232  * @pdata: platform data passed in from the platform/machine
233  * @base: virtual memory base (remapped)
234  * @slave: slave engine for this instance
235  * @memcpy: memcpy engine for this instance
236  * @phy_chans: array of data for the physical channels
237  */
238 struct s3c24xx_dma_engine {
239         struct platform_device                  *pdev;
240         const struct s3c24xx_dma_platdata       *pdata;
241         struct soc_data                         *sdata;
242         void __iomem                            *base;
243         struct dma_device                       slave;
244         struct dma_device                       memcpy;
245         struct s3c24xx_dma_phy                  *phy_chans;
246 };
247 
248 /*
249  * Physical channel handling
250  */
251 
252 /*
253  * Check whether a certain channel is busy or not.
254  */
255 static int s3c24xx_dma_phy_busy(struct s3c24xx_dma_phy *phy)
256 {
257         unsigned int val = readl(phy->base + S3C24XX_DSTAT);
258         return val & S3C24XX_DSTAT_STAT_BUSY;
259 }
260 
261 static bool s3c24xx_dma_phy_valid(struct s3c24xx_dma_chan *s3cchan,
262                                   struct s3c24xx_dma_phy *phy)
263 {
264         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
265         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
266         struct s3c24xx_dma_channel *cdata = &pdata->channels[s3cchan->id];
267         int phyvalid;
268 
269         /* every phy is valid for memcopy channels */
270         if (!s3cchan->slave)
271                 return true;
272 
273         /* On newer variants all phys can be used for all virtual channels */
274         if (s3cdma->sdata->has_reqsel)
275                 return true;
276 
277         phyvalid = (cdata->chansel >> (phy->id * S3C24XX_CHANSEL_WIDTH));
278         return (phyvalid & S3C24XX_CHANSEL_VALID) ? true : false;
279 }
280 
281 /*
282  * Allocate a physical channel for a virtual channel
283  *
284  * Try to locate a physical channel to be used for this transfer. If all
285  * are taken return NULL and the requester will have to cope by using
286  * some fallback PIO mode or retrying later.
287  */
288 static
289 struct s3c24xx_dma_phy *s3c24xx_dma_get_phy(struct s3c24xx_dma_chan *s3cchan)
290 {
291         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
292         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
293         struct s3c24xx_dma_channel *cdata;
294         struct s3c24xx_dma_phy *phy = NULL;
295         unsigned long flags;
296         int i;
297         int ret;
298 
299         if (s3cchan->slave)
300                 cdata = &pdata->channels[s3cchan->id];
301 
302         for (i = 0; i < s3cdma->pdata->num_phy_channels; i++) {
303                 phy = &s3cdma->phy_chans[i];
304 
305                 if (!phy->valid)
306                         continue;
307 
308                 if (!s3c24xx_dma_phy_valid(s3cchan, phy))
309                         continue;
310 
311                 spin_lock_irqsave(&phy->lock, flags);
312 
313                 if (!phy->serving) {
314                         phy->serving = s3cchan;
315                         spin_unlock_irqrestore(&phy->lock, flags);
316                         break;
317                 }
318 
319                 spin_unlock_irqrestore(&phy->lock, flags);
320         }
321 
322         /* No physical channel available, cope with it */
323         if (i == s3cdma->pdata->num_phy_channels) {
324                 dev_warn(&s3cdma->pdev->dev, "no phy channel available\n");
325                 return NULL;
326         }
327 
328         /* start the phy clock */
329         if (s3cdma->sdata->has_clocks) {
330                 ret = clk_enable(phy->clk);
331                 if (ret) {
332                         dev_err(&s3cdma->pdev->dev, "could not enable clock for channel %d, err %d\n",
333                                 phy->id, ret);
334                         phy->serving = NULL;
335                         return NULL;
336                 }
337         }
338 
339         return phy;
340 }
341 
342 /*
343  * Mark the physical channel as free.
344  *
345  * This drops the link between the physical and virtual channel.
346  */
347 static inline void s3c24xx_dma_put_phy(struct s3c24xx_dma_phy *phy)
348 {
349         struct s3c24xx_dma_engine *s3cdma = phy->host;
350 
351         if (s3cdma->sdata->has_clocks)
352                 clk_disable(phy->clk);
353 
354         phy->serving = NULL;
355 }
356 
357 /*
358  * Stops the channel by writing the stop bit.
359  * This should not be used for an on-going transfer, but as a method of
360  * shutting down a channel (eg, when it's no longer used) or terminating a
361  * transfer.
362  */
363 static void s3c24xx_dma_terminate_phy(struct s3c24xx_dma_phy *phy)
364 {
365         writel(S3C24XX_DMASKTRIG_STOP, phy->base + S3C24XX_DMASKTRIG);
366 }
367 
368 /*
369  * Virtual channel handling
370  */
371 
372 static inline
373 struct s3c24xx_dma_chan *to_s3c24xx_dma_chan(struct dma_chan *chan)
374 {
375         return container_of(chan, struct s3c24xx_dma_chan, vc.chan);
376 }
377 
378 static u32 s3c24xx_dma_getbytes_chan(struct s3c24xx_dma_chan *s3cchan)
379 {
380         struct s3c24xx_dma_phy *phy = s3cchan->phy;
381         struct s3c24xx_txd *txd = s3cchan->at;
382         u32 tc = readl(phy->base + S3C24XX_DSTAT) & S3C24XX_DSTAT_CURRTC_MASK;
383 
384         return tc * txd->width;
385 }
386 
387 static int s3c24xx_dma_set_runtime_config(struct s3c24xx_dma_chan *s3cchan,
388                                   struct dma_slave_config *config)
389 {
390         if (!s3cchan->slave)
391                 return -EINVAL;
392 
393         /* Reject definitely invalid configurations */
394         if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
395             config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
396                 return -EINVAL;
397 
398         s3cchan->cfg = *config;
399 
400         return 0;
401 }
402 
403 /*
404  * Transfer handling
405  */
406 
407 static inline
408 struct s3c24xx_txd *to_s3c24xx_txd(struct dma_async_tx_descriptor *tx)
409 {
410         return container_of(tx, struct s3c24xx_txd, vd.tx);
411 }
412 
413 static struct s3c24xx_txd *s3c24xx_dma_get_txd(void)
414 {
415         struct s3c24xx_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
416 
417         if (txd) {
418                 INIT_LIST_HEAD(&txd->dsg_list);
419                 txd->dcon = S3C24XX_DCON_INT | S3C24XX_DCON_NORELOAD;
420         }
421 
422         return txd;
423 }
424 
425 static void s3c24xx_dma_free_txd(struct s3c24xx_txd *txd)
426 {
427         struct s3c24xx_sg *dsg, *_dsg;
428 
429         list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
430                 list_del(&dsg->node);
431                 kfree(dsg);
432         }
433 
434         kfree(txd);
435 }
436 
437 static void s3c24xx_dma_start_next_sg(struct s3c24xx_dma_chan *s3cchan,
438                                        struct s3c24xx_txd *txd)
439 {
440         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
441         struct s3c24xx_dma_phy *phy = s3cchan->phy;
442         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
443         struct s3c24xx_sg *dsg = list_entry(txd->at, struct s3c24xx_sg, node);
444         u32 dcon = txd->dcon;
445         u32 val;
446 
447         /* transfer-size and -count from len and width */
448         switch (txd->width) {
449         case 1:
450                 dcon |= S3C24XX_DCON_DSZ_BYTE | dsg->len;
451                 break;
452         case 2:
453                 dcon |= S3C24XX_DCON_DSZ_HALFWORD | (dsg->len / 2);
454                 break;
455         case 4:
456                 dcon |= S3C24XX_DCON_DSZ_WORD | (dsg->len / 4);
457                 break;
458         }
459 
460         if (s3cchan->slave) {
461                 struct s3c24xx_dma_channel *cdata =
462                                         &pdata->channels[s3cchan->id];
463 
464                 if (s3cdma->sdata->has_reqsel) {
465                         writel_relaxed((cdata->chansel << 1) |
466                                                         S3C24XX_DMAREQSEL_HW,
467                                         phy->base + S3C24XX_DMAREQSEL);
468                 } else {
469                         int csel = cdata->chansel >> (phy->id *
470                                                         S3C24XX_CHANSEL_WIDTH);
471 
472                         csel &= S3C24XX_CHANSEL_REQ_MASK;
473                         dcon |= csel << S3C24XX_DCON_HWSRC_SHIFT;
474                         dcon |= S3C24XX_DCON_HWTRIG;
475                 }
476         } else {
477                 if (s3cdma->sdata->has_reqsel)
478                         writel_relaxed(0, phy->base + S3C24XX_DMAREQSEL);
479         }
480 
481         writel_relaxed(dsg->src_addr, phy->base + S3C24XX_DISRC);
482         writel_relaxed(txd->disrcc, phy->base + S3C24XX_DISRCC);
483         writel_relaxed(dsg->dst_addr, phy->base + S3C24XX_DIDST);
484         writel_relaxed(txd->didstc, phy->base + S3C24XX_DIDSTC);
485         writel_relaxed(dcon, phy->base + S3C24XX_DCON);
486 
487         val = readl_relaxed(phy->base + S3C24XX_DMASKTRIG);
488         val &= ~S3C24XX_DMASKTRIG_STOP;
489         val |= S3C24XX_DMASKTRIG_ON;
490 
491         /* trigger the dma operation for memcpy transfers */
492         if (!s3cchan->slave)
493                 val |= S3C24XX_DMASKTRIG_SWTRIG;
494 
495         writel(val, phy->base + S3C24XX_DMASKTRIG);
496 }
497 
498 /*
499  * Set the initial DMA register values and start first sg.
500  */
501 static void s3c24xx_dma_start_next_txd(struct s3c24xx_dma_chan *s3cchan)
502 {
503         struct s3c24xx_dma_phy *phy = s3cchan->phy;
504         struct virt_dma_desc *vd = vchan_next_desc(&s3cchan->vc);
505         struct s3c24xx_txd *txd = to_s3c24xx_txd(&vd->tx);
506 
507         list_del(&txd->vd.node);
508 
509         s3cchan->at = txd;
510 
511         /* Wait for channel inactive */
512         while (s3c24xx_dma_phy_busy(phy))
513                 cpu_relax();
514 
515         /* point to the first element of the sg list */
516         txd->at = txd->dsg_list.next;
517         s3c24xx_dma_start_next_sg(s3cchan, txd);
518 }
519 
520 static void s3c24xx_dma_free_txd_list(struct s3c24xx_dma_engine *s3cdma,
521                                 struct s3c24xx_dma_chan *s3cchan)
522 {
523         LIST_HEAD(head);
524 
525         vchan_get_all_descriptors(&s3cchan->vc, &head);
526         vchan_dma_desc_free_list(&s3cchan->vc, &head);
527 }
528 
529 /*
530  * Try to allocate a physical channel.  When successful, assign it to
531  * this virtual channel, and initiate the next descriptor.  The
532  * virtual channel lock must be held at this point.
533  */
534 static void s3c24xx_dma_phy_alloc_and_start(struct s3c24xx_dma_chan *s3cchan)
535 {
536         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
537         struct s3c24xx_dma_phy *phy;
538 
539         phy = s3c24xx_dma_get_phy(s3cchan);
540         if (!phy) {
541                 dev_dbg(&s3cdma->pdev->dev, "no physical channel available for xfer on %s\n",
542                         s3cchan->name);
543                 s3cchan->state = S3C24XX_DMA_CHAN_WAITING;
544                 return;
545         }
546 
547         dev_dbg(&s3cdma->pdev->dev, "allocated physical channel %d for xfer on %s\n",
548                 phy->id, s3cchan->name);
549 
550         s3cchan->phy = phy;
551         s3cchan->state = S3C24XX_DMA_CHAN_RUNNING;
552 
553         s3c24xx_dma_start_next_txd(s3cchan);
554 }
555 
556 static void s3c24xx_dma_phy_reassign_start(struct s3c24xx_dma_phy *phy,
557         struct s3c24xx_dma_chan *s3cchan)
558 {
559         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
560 
561         dev_dbg(&s3cdma->pdev->dev, "reassigned physical channel %d for xfer on %s\n",
562                 phy->id, s3cchan->name);
563 
564         /*
565          * We do this without taking the lock; we're really only concerned
566          * about whether this pointer is NULL or not, and we're guaranteed
567          * that this will only be called when it _already_ is non-NULL.
568          */
569         phy->serving = s3cchan;
570         s3cchan->phy = phy;
571         s3cchan->state = S3C24XX_DMA_CHAN_RUNNING;
572         s3c24xx_dma_start_next_txd(s3cchan);
573 }
574 
575 /*
576  * Free a physical DMA channel, potentially reallocating it to another
577  * virtual channel if we have any pending.
578  */
579 static void s3c24xx_dma_phy_free(struct s3c24xx_dma_chan *s3cchan)
580 {
581         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
582         struct s3c24xx_dma_chan *p, *next;
583 
584 retry:
585         next = NULL;
586 
587         /* Find a waiting virtual channel for the next transfer. */
588         list_for_each_entry(p, &s3cdma->memcpy.channels, vc.chan.device_node)
589                 if (p->state == S3C24XX_DMA_CHAN_WAITING) {
590                         next = p;
591                         break;
592                 }
593 
594         if (!next) {
595                 list_for_each_entry(p, &s3cdma->slave.channels,
596                                     vc.chan.device_node)
597                         if (p->state == S3C24XX_DMA_CHAN_WAITING &&
598                                       s3c24xx_dma_phy_valid(p, s3cchan->phy)) {
599                                 next = p;
600                                 break;
601                         }
602         }
603 
604         /* Ensure that the physical channel is stopped */
605         s3c24xx_dma_terminate_phy(s3cchan->phy);
606 
607         if (next) {
608                 bool success;
609 
610                 /*
611                  * Eww.  We know this isn't going to deadlock
612                  * but lockdep probably doesn't.
613                  */
614                 spin_lock(&next->vc.lock);
615                 /* Re-check the state now that we have the lock */
616                 success = next->state == S3C24XX_DMA_CHAN_WAITING;
617                 if (success)
618                         s3c24xx_dma_phy_reassign_start(s3cchan->phy, next);
619                 spin_unlock(&next->vc.lock);
620 
621                 /* If the state changed, try to find another channel */
622                 if (!success)
623                         goto retry;
624         } else {
625                 /* No more jobs, so free up the physical channel */
626                 s3c24xx_dma_put_phy(s3cchan->phy);
627         }
628 
629         s3cchan->phy = NULL;
630         s3cchan->state = S3C24XX_DMA_CHAN_IDLE;
631 }
632 
633 static void s3c24xx_dma_desc_free(struct virt_dma_desc *vd)
634 {
635         struct s3c24xx_txd *txd = to_s3c24xx_txd(&vd->tx);
636         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(vd->tx.chan);
637 
638         if (!s3cchan->slave)
639                 dma_descriptor_unmap(&vd->tx);
640 
641         s3c24xx_dma_free_txd(txd);
642 }
643 
644 static irqreturn_t s3c24xx_dma_irq(int irq, void *data)
645 {
646         struct s3c24xx_dma_phy *phy = data;
647         struct s3c24xx_dma_chan *s3cchan = phy->serving;
648         struct s3c24xx_txd *txd;
649 
650         dev_dbg(&phy->host->pdev->dev, "interrupt on channel %d\n", phy->id);
651 
652         /*
653          * Interrupts happen to notify the completion of a transfer and the
654          * channel should have moved into its stop state already on its own.
655          * Therefore interrupts on channels not bound to a virtual channel
656          * should never happen. Nevertheless send a terminate command to the
657          * channel if the unlikely case happens.
658          */
659         if (unlikely(!s3cchan)) {
660                 dev_err(&phy->host->pdev->dev, "interrupt on unused channel %d\n",
661                         phy->id);
662 
663                 s3c24xx_dma_terminate_phy(phy);
664 
665                 return IRQ_HANDLED;
666         }
667 
668         spin_lock(&s3cchan->vc.lock);
669         txd = s3cchan->at;
670         if (txd) {
671                 /* when more sg's are in this txd, start the next one */
672                 if (!list_is_last(txd->at, &txd->dsg_list)) {
673                         txd->at = txd->at->next;
674                         if (txd->cyclic)
675                                 vchan_cyclic_callback(&txd->vd);
676                         s3c24xx_dma_start_next_sg(s3cchan, txd);
677                 } else if (!txd->cyclic) {
678                         s3cchan->at = NULL;
679                         vchan_cookie_complete(&txd->vd);
680 
681                         /*
682                          * And start the next descriptor (if any),
683                          * otherwise free this channel.
684                          */
685                         if (vchan_next_desc(&s3cchan->vc))
686                                 s3c24xx_dma_start_next_txd(s3cchan);
687                         else
688                                 s3c24xx_dma_phy_free(s3cchan);
689                 } else {
690                         vchan_cyclic_callback(&txd->vd);
691 
692                         /* Cyclic: reset at beginning */
693                         txd->at = txd->dsg_list.next;
694                         s3c24xx_dma_start_next_sg(s3cchan, txd);
695                 }
696         }
697         spin_unlock(&s3cchan->vc.lock);
698 
699         return IRQ_HANDLED;
700 }
701 
702 /*
703  * The DMA ENGINE API
704  */
705 
706 static int s3c24xx_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
707                          unsigned long arg)
708 {
709         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
710         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
711         unsigned long flags;
712         int ret = 0;
713 
714         spin_lock_irqsave(&s3cchan->vc.lock, flags);
715 
716         switch (cmd) {
717         case DMA_SLAVE_CONFIG:
718                 ret = s3c24xx_dma_set_runtime_config(s3cchan,
719                                               (struct dma_slave_config *)arg);
720                 break;
721         case DMA_TERMINATE_ALL:
722                 if (!s3cchan->phy && !s3cchan->at) {
723                         dev_err(&s3cdma->pdev->dev, "trying to terminate already stopped channel %d\n",
724                                 s3cchan->id);
725                         ret = -EINVAL;
726                         break;
727                 }
728 
729                 s3cchan->state = S3C24XX_DMA_CHAN_IDLE;
730 
731                  /* Mark physical channel as free */
732                 if (s3cchan->phy)
733                         s3c24xx_dma_phy_free(s3cchan);
734 
735                 /* Dequeue current job */
736                 if (s3cchan->at) {
737                         s3c24xx_dma_desc_free(&s3cchan->at->vd);
738                         s3cchan->at = NULL;
739                 }
740 
741                 /* Dequeue jobs not yet fired as well */
742                 s3c24xx_dma_free_txd_list(s3cdma, s3cchan);
743                 break;
744         default:
745                 /* Unknown command */
746                 ret = -ENXIO;
747                 break;
748         }
749 
750         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
751 
752         return ret;
753 }
754 
755 static int s3c24xx_dma_alloc_chan_resources(struct dma_chan *chan)
756 {
757         return 0;
758 }
759 
760 static void s3c24xx_dma_free_chan_resources(struct dma_chan *chan)
761 {
762         /* Ensure all queued descriptors are freed */
763         vchan_free_chan_resources(to_virt_chan(chan));
764 }
765 
766 static enum dma_status s3c24xx_dma_tx_status(struct dma_chan *chan,
767                 dma_cookie_t cookie, struct dma_tx_state *txstate)
768 {
769         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
770         struct s3c24xx_txd *txd;
771         struct s3c24xx_sg *dsg;
772         struct virt_dma_desc *vd;
773         unsigned long flags;
774         enum dma_status ret;
775         size_t bytes = 0;
776 
777         spin_lock_irqsave(&s3cchan->vc.lock, flags);
778         ret = dma_cookie_status(chan, cookie, txstate);
779         if (ret == DMA_COMPLETE) {
780                 spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
781                 return ret;
782         }
783 
784         /*
785          * There's no point calculating the residue if there's
786          * no txstate to store the value.
787          */
788         if (!txstate) {
789                 spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
790                 return ret;
791         }
792 
793         vd = vchan_find_desc(&s3cchan->vc, cookie);
794         if (vd) {
795                 /* On the issued list, so hasn't been processed yet */
796                 txd = to_s3c24xx_txd(&vd->tx);
797 
798                 list_for_each_entry(dsg, &txd->dsg_list, node)
799                         bytes += dsg->len;
800         } else {
801                 /*
802                  * Currently running, so sum over the pending sg's and
803                  * the currently active one.
804                  */
805                 txd = s3cchan->at;
806 
807                 dsg = list_entry(txd->at, struct s3c24xx_sg, node);
808                 list_for_each_entry_from(dsg, &txd->dsg_list, node)
809                         bytes += dsg->len;
810 
811                 bytes += s3c24xx_dma_getbytes_chan(s3cchan);
812         }
813         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
814 
815         /*
816          * This cookie not complete yet
817          * Get number of bytes left in the active transactions and queue
818          */
819         dma_set_residue(txstate, bytes);
820 
821         /* Whether waiting or running, we're in progress */
822         return ret;
823 }
824 
825 /*
826  * Initialize a descriptor to be used by memcpy submit
827  */
828 static struct dma_async_tx_descriptor *s3c24xx_dma_prep_memcpy(
829                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
830                 size_t len, unsigned long flags)
831 {
832         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
833         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
834         struct s3c24xx_txd *txd;
835         struct s3c24xx_sg *dsg;
836         int src_mod, dest_mod;
837 
838         dev_dbg(&s3cdma->pdev->dev, "prepare memcpy of %d bytes from %s\n",
839                         len, s3cchan->name);
840 
841         if ((len & S3C24XX_DCON_TC_MASK) != len) {
842                 dev_err(&s3cdma->pdev->dev, "memcpy size %d to large\n", len);
843                 return NULL;
844         }
845 
846         txd = s3c24xx_dma_get_txd();
847         if (!txd)
848                 return NULL;
849 
850         dsg = kzalloc(sizeof(*dsg), GFP_NOWAIT);
851         if (!dsg) {
852                 s3c24xx_dma_free_txd(txd);
853                 return NULL;
854         }
855         list_add_tail(&dsg->node, &txd->dsg_list);
856 
857         dsg->src_addr = src;
858         dsg->dst_addr = dest;
859         dsg->len = len;
860 
861         /*
862          * Determine a suitable transfer width.
863          * The DMA controller cannot fetch/store information which is not
864          * naturally aligned on the bus, i.e., a 4 byte fetch must start at
865          * an address divisible by 4 - more generally addr % width must be 0.
866          */
867         src_mod = src % 4;
868         dest_mod = dest % 4;
869         switch (len % 4) {
870         case 0:
871                 txd->width = (src_mod == 0 && dest_mod == 0) ? 4 : 1;
872                 break;
873         case 2:
874                 txd->width = ((src_mod == 2 || src_mod == 0) &&
875                               (dest_mod == 2 || dest_mod == 0)) ? 2 : 1;
876                 break;
877         default:
878                 txd->width = 1;
879                 break;
880         }
881 
882         txd->disrcc = S3C24XX_DISRCC_LOC_AHB | S3C24XX_DISRCC_INC_INCREMENT;
883         txd->didstc = S3C24XX_DIDSTC_LOC_AHB | S3C24XX_DIDSTC_INC_INCREMENT;
884         txd->dcon |= S3C24XX_DCON_DEMAND | S3C24XX_DCON_SYNC_HCLK |
885                      S3C24XX_DCON_SERV_WHOLE;
886 
887         return vchan_tx_prep(&s3cchan->vc, &txd->vd, flags);
888 }
889 
890 static struct dma_async_tx_descriptor *s3c24xx_dma_prep_dma_cyclic(
891         struct dma_chan *chan, dma_addr_t addr, size_t size, size_t period,
892         enum dma_transfer_direction direction, unsigned long flags,
893         void *context)
894 {
895         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
896         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
897         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
898         struct s3c24xx_dma_channel *cdata = &pdata->channels[s3cchan->id];
899         struct s3c24xx_txd *txd;
900         struct s3c24xx_sg *dsg;
901         unsigned sg_len;
902         dma_addr_t slave_addr;
903         u32 hwcfg = 0;
904         int i;
905 
906         dev_dbg(&s3cdma->pdev->dev,
907                 "prepare cyclic transaction of %zu bytes with period %zu from %s\n",
908                 size, period, s3cchan->name);
909 
910         if (!is_slave_direction(direction)) {
911                 dev_err(&s3cdma->pdev->dev,
912                         "direction %d unsupported\n", direction);
913                 return NULL;
914         }
915 
916         txd = s3c24xx_dma_get_txd();
917         if (!txd)
918                 return NULL;
919 
920         txd->cyclic = 1;
921 
922         if (cdata->handshake)
923                 txd->dcon |= S3C24XX_DCON_HANDSHAKE;
924 
925         switch (cdata->bus) {
926         case S3C24XX_DMA_APB:
927                 txd->dcon |= S3C24XX_DCON_SYNC_PCLK;
928                 hwcfg |= S3C24XX_DISRCC_LOC_APB;
929                 break;
930         case S3C24XX_DMA_AHB:
931                 txd->dcon |= S3C24XX_DCON_SYNC_HCLK;
932                 hwcfg |= S3C24XX_DISRCC_LOC_AHB;
933                 break;
934         }
935 
936         /*
937          * Always assume our peripheral desintation is a fixed
938          * address in memory.
939          */
940         hwcfg |= S3C24XX_DISRCC_INC_FIXED;
941 
942         /*
943          * Individual dma operations are requested by the slave,
944          * so serve only single atomic operations (S3C24XX_DCON_SERV_SINGLE).
945          */
946         txd->dcon |= S3C24XX_DCON_SERV_SINGLE;
947 
948         if (direction == DMA_MEM_TO_DEV) {
949                 txd->disrcc = S3C24XX_DISRCC_LOC_AHB |
950                               S3C24XX_DISRCC_INC_INCREMENT;
951                 txd->didstc = hwcfg;
952                 slave_addr = s3cchan->cfg.dst_addr;
953                 txd->width = s3cchan->cfg.dst_addr_width;
954         } else {
955                 txd->disrcc = hwcfg;
956                 txd->didstc = S3C24XX_DIDSTC_LOC_AHB |
957                               S3C24XX_DIDSTC_INC_INCREMENT;
958                 slave_addr = s3cchan->cfg.src_addr;
959                 txd->width = s3cchan->cfg.src_addr_width;
960         }
961 
962         sg_len = size / period;
963 
964         for (i = 0; i < sg_len; i++) {
965                 dsg = kzalloc(sizeof(*dsg), GFP_NOWAIT);
966                 if (!dsg) {
967                         s3c24xx_dma_free_txd(txd);
968                         return NULL;
969                 }
970                 list_add_tail(&dsg->node, &txd->dsg_list);
971 
972                 dsg->len = period;
973                 /* Check last period length */
974                 if (i == sg_len - 1)
975                         dsg->len = size - period * i;
976                 if (direction == DMA_MEM_TO_DEV) {
977                         dsg->src_addr = addr + period * i;
978                         dsg->dst_addr = slave_addr;
979                 } else { /* DMA_DEV_TO_MEM */
980                         dsg->src_addr = slave_addr;
981                         dsg->dst_addr = addr + period * i;
982                 }
983         }
984 
985         return vchan_tx_prep(&s3cchan->vc, &txd->vd, flags);
986 }
987 
988 static struct dma_async_tx_descriptor *s3c24xx_dma_prep_slave_sg(
989                 struct dma_chan *chan, struct scatterlist *sgl,
990                 unsigned int sg_len, enum dma_transfer_direction direction,
991                 unsigned long flags, void *context)
992 {
993         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
994         struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
995         const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
996         struct s3c24xx_dma_channel *cdata = &pdata->channels[s3cchan->id];
997         struct s3c24xx_txd *txd;
998         struct s3c24xx_sg *dsg;
999         struct scatterlist *sg;
1000         dma_addr_t slave_addr;
1001         u32 hwcfg = 0;
1002         int tmp;
1003 
1004         dev_dbg(&s3cdma->pdev->dev, "prepare transaction of %d bytes from %s\n",
1005                         sg_dma_len(sgl), s3cchan->name);
1006 
1007         txd = s3c24xx_dma_get_txd();
1008         if (!txd)
1009                 return NULL;
1010 
1011         if (cdata->handshake)
1012                 txd->dcon |= S3C24XX_DCON_HANDSHAKE;
1013 
1014         switch (cdata->bus) {
1015         case S3C24XX_DMA_APB:
1016                 txd->dcon |= S3C24XX_DCON_SYNC_PCLK;
1017                 hwcfg |= S3C24XX_DISRCC_LOC_APB;
1018                 break;
1019         case S3C24XX_DMA_AHB:
1020                 txd->dcon |= S3C24XX_DCON_SYNC_HCLK;
1021                 hwcfg |= S3C24XX_DISRCC_LOC_AHB;
1022                 break;
1023         }
1024 
1025         /*
1026          * Always assume our peripheral desintation is a fixed
1027          * address in memory.
1028          */
1029         hwcfg |= S3C24XX_DISRCC_INC_FIXED;
1030 
1031         /*
1032          * Individual dma operations are requested by the slave,
1033          * so serve only single atomic operations (S3C24XX_DCON_SERV_SINGLE).
1034          */
1035         txd->dcon |= S3C24XX_DCON_SERV_SINGLE;
1036 
1037         if (direction == DMA_MEM_TO_DEV) {
1038                 txd->disrcc = S3C24XX_DISRCC_LOC_AHB |
1039                               S3C24XX_DISRCC_INC_INCREMENT;
1040                 txd->didstc = hwcfg;
1041                 slave_addr = s3cchan->cfg.dst_addr;
1042                 txd->width = s3cchan->cfg.dst_addr_width;
1043         } else if (direction == DMA_DEV_TO_MEM) {
1044                 txd->disrcc = hwcfg;
1045                 txd->didstc = S3C24XX_DIDSTC_LOC_AHB |
1046                               S3C24XX_DIDSTC_INC_INCREMENT;
1047                 slave_addr = s3cchan->cfg.src_addr;
1048                 txd->width = s3cchan->cfg.src_addr_width;
1049         } else {
1050                 s3c24xx_dma_free_txd(txd);
1051                 dev_err(&s3cdma->pdev->dev,
1052                         "direction %d unsupported\n", direction);
1053                 return NULL;
1054         }
1055 
1056         for_each_sg(sgl, sg, sg_len, tmp) {
1057                 dsg = kzalloc(sizeof(*dsg), GFP_NOWAIT);
1058                 if (!dsg) {
1059                         s3c24xx_dma_free_txd(txd);
1060                         return NULL;
1061                 }
1062                 list_add_tail(&dsg->node, &txd->dsg_list);
1063 
1064                 dsg->len = sg_dma_len(sg);
1065                 if (direction == DMA_MEM_TO_DEV) {
1066                         dsg->src_addr = sg_dma_address(sg);
1067                         dsg->dst_addr = slave_addr;
1068                 } else { /* DMA_DEV_TO_MEM */
1069                         dsg->src_addr = slave_addr;
1070                         dsg->dst_addr = sg_dma_address(sg);
1071                 }
1072         }
1073 
1074         return vchan_tx_prep(&s3cchan->vc, &txd->vd, flags);
1075 }
1076 
1077 /*
1078  * Slave transactions callback to the slave device to allow
1079  * synchronization of slave DMA signals with the DMAC enable
1080  */
1081 static void s3c24xx_dma_issue_pending(struct dma_chan *chan)
1082 {
1083         struct s3c24xx_dma_chan *s3cchan = to_s3c24xx_dma_chan(chan);
1084         unsigned long flags;
1085 
1086         spin_lock_irqsave(&s3cchan->vc.lock, flags);
1087         if (vchan_issue_pending(&s3cchan->vc)) {
1088                 if (!s3cchan->phy && s3cchan->state != S3C24XX_DMA_CHAN_WAITING)
1089                         s3c24xx_dma_phy_alloc_and_start(s3cchan);
1090         }
1091         spin_unlock_irqrestore(&s3cchan->vc.lock, flags);
1092 }
1093 
1094 /*
1095  * Bringup and teardown
1096  */
1097 
1098 /*
1099  * Initialise the DMAC memcpy/slave channels.
1100  * Make a local wrapper to hold required data
1101  */
1102 static int s3c24xx_dma_init_virtual_channels(struct s3c24xx_dma_engine *s3cdma,
1103                 struct dma_device *dmadev, unsigned int channels, bool slave)
1104 {
1105         struct s3c24xx_dma_chan *chan;
1106         int i;
1107 
1108         INIT_LIST_HEAD(&dmadev->channels);
1109 
1110         /*
1111          * Register as many many memcpy as we have physical channels,
1112          * we won't always be able to use all but the code will have
1113          * to cope with that situation.
1114          */
1115         for (i = 0; i < channels; i++) {
1116                 chan = devm_kzalloc(dmadev->dev, sizeof(*chan), GFP_KERNEL);
1117                 if (!chan) {
1118                         dev_err(dmadev->dev,
1119                                 "%s no memory for channel\n", __func__);
1120                         return -ENOMEM;
1121                 }
1122 
1123                 chan->id = i;
1124                 chan->host = s3cdma;
1125                 chan->state = S3C24XX_DMA_CHAN_IDLE;
1126 
1127                 if (slave) {
1128                         chan->slave = true;
1129                         chan->name = kasprintf(GFP_KERNEL, "slave%d", i);
1130                         if (!chan->name)
1131                                 return -ENOMEM;
1132                 } else {
1133                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1134                         if (!chan->name)
1135                                 return -ENOMEM;
1136                 }
1137                 dev_dbg(dmadev->dev,
1138                          "initialize virtual channel \"%s\"\n",
1139                          chan->name);
1140 
1141                 chan->vc.desc_free = s3c24xx_dma_desc_free;
1142                 vchan_init(&chan->vc, dmadev);
1143         }
1144         dev_info(dmadev->dev, "initialized %d virtual %s channels\n",
1145                  i, slave ? "slave" : "memcpy");
1146         return i;
1147 }
1148 
1149 static void s3c24xx_dma_free_virtual_channels(struct dma_device *dmadev)
1150 {
1151         struct s3c24xx_dma_chan *chan = NULL;
1152         struct s3c24xx_dma_chan *next;
1153 
1154         list_for_each_entry_safe(chan,
1155                                  next, &dmadev->channels, vc.chan.device_node)
1156                 list_del(&chan->vc.chan.device_node);
1157 }
1158 
1159 /* s3c2410, s3c2440 and s3c2442 have a 0x40 stride without separate clocks */
1160 static struct soc_data soc_s3c2410 = {
1161         .stride = 0x40,
1162         .has_reqsel = false,
1163         .has_clocks = false,
1164 };
1165 
1166 /* s3c2412 and s3c2413 have a 0x40 stride and dmareqsel mechanism */
1167 static struct soc_data soc_s3c2412 = {
1168         .stride = 0x40,
1169         .has_reqsel = true,
1170         .has_clocks = true,
1171 };
1172 
1173 /* s3c2443 and following have a 0x100 stride and dmareqsel mechanism */
1174 static struct soc_data soc_s3c2443 = {
1175         .stride = 0x100,
1176         .has_reqsel = true,
1177         .has_clocks = true,
1178 };
1179 
1180 static struct platform_device_id s3c24xx_dma_driver_ids[] = {
1181         {
1182                 .name           = "s3c2410-dma",
1183                 .driver_data    = (kernel_ulong_t)&soc_s3c2410,
1184         }, {
1185                 .name           = "s3c2412-dma",
1186                 .driver_data    = (kernel_ulong_t)&soc_s3c2412,
1187         }, {
1188                 .name           = "s3c2443-dma",
1189                 .driver_data    = (kernel_ulong_t)&soc_s3c2443,
1190         },
1191         { },
1192 };
1193 
1194 static struct soc_data *s3c24xx_dma_get_soc_data(struct platform_device *pdev)
1195 {
1196         return (struct soc_data *)
1197                          platform_get_device_id(pdev)->driver_data;
1198 }
1199 
1200 static int s3c24xx_dma_probe(struct platform_device *pdev)
1201 {
1202         const struct s3c24xx_dma_platdata *pdata = dev_get_platdata(&pdev->dev);
1203         struct s3c24xx_dma_engine *s3cdma;
1204         struct soc_data *sdata;
1205         struct resource *res;
1206         int ret;
1207         int i;
1208 
1209         if (!pdata) {
1210                 dev_err(&pdev->dev, "platform data missing\n");
1211                 return -ENODEV;
1212         }
1213 
1214         /* Basic sanity check */
1215         if (pdata->num_phy_channels > MAX_DMA_CHANNELS) {
1216                 dev_err(&pdev->dev, "to many dma channels %d, max %d\n",
1217                         pdata->num_phy_channels, MAX_DMA_CHANNELS);
1218                 return -EINVAL;
1219         }
1220 
1221         sdata = s3c24xx_dma_get_soc_data(pdev);
1222         if (!sdata)
1223                 return -EINVAL;
1224 
1225         s3cdma = devm_kzalloc(&pdev->dev, sizeof(*s3cdma), GFP_KERNEL);
1226         if (!s3cdma)
1227                 return -ENOMEM;
1228 
1229         s3cdma->pdev = pdev;
1230         s3cdma->pdata = pdata;
1231         s3cdma->sdata = sdata;
1232 
1233         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1234         s3cdma->base = devm_ioremap_resource(&pdev->dev, res);
1235         if (IS_ERR(s3cdma->base))
1236                 return PTR_ERR(s3cdma->base);
1237 
1238         s3cdma->phy_chans = devm_kzalloc(&pdev->dev,
1239                                               sizeof(struct s3c24xx_dma_phy) *
1240                                                         pdata->num_phy_channels,
1241                                               GFP_KERNEL);
1242         if (!s3cdma->phy_chans)
1243                 return -ENOMEM;
1244 
1245         /* aquire irqs and clocks for all physical channels */
1246         for (i = 0; i < pdata->num_phy_channels; i++) {
1247                 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1248                 char clk_name[6];
1249 
1250                 phy->id = i;
1251                 phy->base = s3cdma->base + (i * sdata->stride);
1252                 phy->host = s3cdma;
1253 
1254                 phy->irq = platform_get_irq(pdev, i);
1255                 if (phy->irq < 0) {
1256                         dev_err(&pdev->dev, "failed to get irq %d, err %d\n",
1257                                 i, phy->irq);
1258                         continue;
1259                 }
1260 
1261                 ret = devm_request_irq(&pdev->dev, phy->irq, s3c24xx_dma_irq,
1262                                        0, pdev->name, phy);
1263                 if (ret) {
1264                         dev_err(&pdev->dev, "Unable to request irq for channel %d, error %d\n",
1265                                 i, ret);
1266                         continue;
1267                 }
1268 
1269                 if (sdata->has_clocks) {
1270                         sprintf(clk_name, "dma.%d", i);
1271                         phy->clk = devm_clk_get(&pdev->dev, clk_name);
1272                         if (IS_ERR(phy->clk) && sdata->has_clocks) {
1273                                 dev_err(&pdev->dev, "unable to aquire clock for channel %d, error %lu",
1274                                         i, PTR_ERR(phy->clk));
1275                                 continue;
1276                         }
1277 
1278                         ret = clk_prepare(phy->clk);
1279                         if (ret) {
1280                                 dev_err(&pdev->dev, "clock for phy %d failed, error %d\n",
1281                                         i, ret);
1282                                 continue;
1283                         }
1284                 }
1285 
1286                 spin_lock_init(&phy->lock);
1287                 phy->valid = true;
1288 
1289                 dev_dbg(&pdev->dev, "physical channel %d is %s\n",
1290                         i, s3c24xx_dma_phy_busy(phy) ? "BUSY" : "FREE");
1291         }
1292 
1293         /* Initialize memcpy engine */
1294         dma_cap_set(DMA_MEMCPY, s3cdma->memcpy.cap_mask);
1295         dma_cap_set(DMA_PRIVATE, s3cdma->memcpy.cap_mask);
1296         s3cdma->memcpy.dev = &pdev->dev;
1297         s3cdma->memcpy.device_alloc_chan_resources =
1298                                         s3c24xx_dma_alloc_chan_resources;
1299         s3cdma->memcpy.device_free_chan_resources =
1300                                         s3c24xx_dma_free_chan_resources;
1301         s3cdma->memcpy.device_prep_dma_memcpy = s3c24xx_dma_prep_memcpy;
1302         s3cdma->memcpy.device_tx_status = s3c24xx_dma_tx_status;
1303         s3cdma->memcpy.device_issue_pending = s3c24xx_dma_issue_pending;
1304         s3cdma->memcpy.device_control = s3c24xx_dma_control;
1305 
1306         /* Initialize slave engine for SoC internal dedicated peripherals */
1307         dma_cap_set(DMA_SLAVE, s3cdma->slave.cap_mask);
1308         dma_cap_set(DMA_CYCLIC, s3cdma->slave.cap_mask);
1309         dma_cap_set(DMA_PRIVATE, s3cdma->slave.cap_mask);
1310         s3cdma->slave.dev = &pdev->dev;
1311         s3cdma->slave.device_alloc_chan_resources =
1312                                         s3c24xx_dma_alloc_chan_resources;
1313         s3cdma->slave.device_free_chan_resources =
1314                                         s3c24xx_dma_free_chan_resources;
1315         s3cdma->slave.device_tx_status = s3c24xx_dma_tx_status;
1316         s3cdma->slave.device_issue_pending = s3c24xx_dma_issue_pending;
1317         s3cdma->slave.device_prep_slave_sg = s3c24xx_dma_prep_slave_sg;
1318         s3cdma->slave.device_prep_dma_cyclic = s3c24xx_dma_prep_dma_cyclic;
1319         s3cdma->slave.device_control = s3c24xx_dma_control;
1320 
1321         /* Register as many memcpy channels as there are physical channels */
1322         ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->memcpy,
1323                                                 pdata->num_phy_channels, false);
1324         if (ret <= 0) {
1325                 dev_warn(&pdev->dev,
1326                          "%s failed to enumerate memcpy channels - %d\n",
1327                          __func__, ret);
1328                 goto err_memcpy;
1329         }
1330 
1331         /* Register slave channels */
1332         ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->slave,
1333                                 pdata->num_channels, true);
1334         if (ret <= 0) {
1335                 dev_warn(&pdev->dev,
1336                         "%s failed to enumerate slave channels - %d\n",
1337                                 __func__, ret);
1338                 goto err_slave;
1339         }
1340 
1341         ret = dma_async_device_register(&s3cdma->memcpy);
1342         if (ret) {
1343                 dev_warn(&pdev->dev,
1344                         "%s failed to register memcpy as an async device - %d\n",
1345                         __func__, ret);
1346                 goto err_memcpy_reg;
1347         }
1348 
1349         ret = dma_async_device_register(&s3cdma->slave);
1350         if (ret) {
1351                 dev_warn(&pdev->dev,
1352                         "%s failed to register slave as an async device - %d\n",
1353                         __func__, ret);
1354                 goto err_slave_reg;
1355         }
1356 
1357         platform_set_drvdata(pdev, s3cdma);
1358         dev_info(&pdev->dev, "Loaded dma driver with %d physical channels\n",
1359                  pdata->num_phy_channels);
1360 
1361         return 0;
1362 
1363 err_slave_reg:
1364         dma_async_device_unregister(&s3cdma->memcpy);
1365 err_memcpy_reg:
1366         s3c24xx_dma_free_virtual_channels(&s3cdma->slave);
1367 err_slave:
1368         s3c24xx_dma_free_virtual_channels(&s3cdma->memcpy);
1369 err_memcpy:
1370         if (sdata->has_clocks)
1371                 for (i = 0; i < pdata->num_phy_channels; i++) {
1372                         struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1373                         if (phy->valid)
1374                                 clk_unprepare(phy->clk);
1375                 }
1376 
1377         return ret;
1378 }
1379 
1380 static int s3c24xx_dma_remove(struct platform_device *pdev)
1381 {
1382         const struct s3c24xx_dma_platdata *pdata = dev_get_platdata(&pdev->dev);
1383         struct s3c24xx_dma_engine *s3cdma = platform_get_drvdata(pdev);
1384         struct soc_data *sdata = s3c24xx_dma_get_soc_data(pdev);
1385         int i;
1386 
1387         dma_async_device_unregister(&s3cdma->slave);
1388         dma_async_device_unregister(&s3cdma->memcpy);
1389 
1390         s3c24xx_dma_free_virtual_channels(&s3cdma->slave);
1391         s3c24xx_dma_free_virtual_channels(&s3cdma->memcpy);
1392 
1393         if (sdata->has_clocks)
1394                 for (i = 0; i < pdata->num_phy_channels; i++) {
1395                         struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1396                         if (phy->valid)
1397                                 clk_unprepare(phy->clk);
1398                 }
1399 
1400         return 0;
1401 }
1402 
1403 static struct platform_driver s3c24xx_dma_driver = {
1404         .driver         = {
1405                 .name   = "s3c24xx-dma",
1406                 .owner  = THIS_MODULE,
1407         },
1408         .id_table       = s3c24xx_dma_driver_ids,
1409         .probe          = s3c24xx_dma_probe,
1410         .remove         = s3c24xx_dma_remove,
1411 };
1412 
1413 module_platform_driver(s3c24xx_dma_driver);
1414 
1415 bool s3c24xx_dma_filter(struct dma_chan *chan, void *param)
1416 {
1417         struct s3c24xx_dma_chan *s3cchan;
1418 
1419         if (chan->device->dev->driver != &s3c24xx_dma_driver.driver)
1420                 return false;
1421 
1422         s3cchan = to_s3c24xx_dma_chan(chan);
1423 
1424         return s3cchan->id == (int)param;
1425 }
1426 EXPORT_SYMBOL(s3c24xx_dma_filter);
1427 
1428 MODULE_DESCRIPTION("S3C24XX DMA Driver");
1429 MODULE_AUTHOR("Heiko Stuebner");
1430 MODULE_LICENSE("GPL v2");
1431 

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