Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/dma/mv_xor.c

  1 /*
  2  * offload engine driver for the Marvell XOR engine
  3  * Copyright (C) 2007, 2008, Marvell International Ltd.
  4  *
  5  * This program is free software; you can redistribute it and/or modify it
  6  * under the terms and conditions of the GNU General Public License,
  7  * version 2, as published by the Free Software Foundation.
  8  *
  9  * This program is distributed in the hope it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12  * more details.
 13  */
 14 
 15 #include <linux/init.h>
 16 #include <linux/slab.h>
 17 #include <linux/delay.h>
 18 #include <linux/dma-mapping.h>
 19 #include <linux/spinlock.h>
 20 #include <linux/interrupt.h>
 21 #include <linux/of_device.h>
 22 #include <linux/platform_device.h>
 23 #include <linux/memory.h>
 24 #include <linux/clk.h>
 25 #include <linux/of.h>
 26 #include <linux/of_irq.h>
 27 #include <linux/irqdomain.h>
 28 #include <linux/cpumask.h>
 29 #include <linux/platform_data/dma-mv_xor.h>
 30 
 31 #include "dmaengine.h"
 32 #include "mv_xor.h"
 33 
 34 enum mv_xor_type {
 35         XOR_ORION,
 36         XOR_ARMADA_38X,
 37         XOR_ARMADA_37XX,
 38 };
 39 
 40 enum mv_xor_mode {
 41         XOR_MODE_IN_REG,
 42         XOR_MODE_IN_DESC,
 43 };
 44 
 45 static void mv_xor_issue_pending(struct dma_chan *chan);
 46 
 47 #define to_mv_xor_chan(chan)            \
 48         container_of(chan, struct mv_xor_chan, dmachan)
 49 
 50 #define to_mv_xor_slot(tx)              \
 51         container_of(tx, struct mv_xor_desc_slot, async_tx)
 52 
 53 #define mv_chan_to_devp(chan)           \
 54         ((chan)->dmadev.dev)
 55 
 56 static void mv_desc_init(struct mv_xor_desc_slot *desc,
 57                          dma_addr_t addr, u32 byte_count,
 58                          enum dma_ctrl_flags flags)
 59 {
 60         struct mv_xor_desc *hw_desc = desc->hw_desc;
 61 
 62         hw_desc->status = XOR_DESC_DMA_OWNED;
 63         hw_desc->phy_next_desc = 0;
 64         /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */
 65         hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ?
 66                                 XOR_DESC_EOD_INT_EN : 0;
 67         hw_desc->phy_dest_addr = addr;
 68         hw_desc->byte_count = byte_count;
 69 }
 70 
 71 static void mv_desc_set_mode(struct mv_xor_desc_slot *desc)
 72 {
 73         struct mv_xor_desc *hw_desc = desc->hw_desc;
 74 
 75         switch (desc->type) {
 76         case DMA_XOR:
 77         case DMA_INTERRUPT:
 78                 hw_desc->desc_command |= XOR_DESC_OPERATION_XOR;
 79                 break;
 80         case DMA_MEMCPY:
 81                 hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY;
 82                 break;
 83         default:
 84                 BUG();
 85                 return;
 86         }
 87 }
 88 
 89 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
 90                                   u32 next_desc_addr)
 91 {
 92         struct mv_xor_desc *hw_desc = desc->hw_desc;
 93         BUG_ON(hw_desc->phy_next_desc);
 94         hw_desc->phy_next_desc = next_desc_addr;
 95 }
 96 
 97 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
 98                                  int index, dma_addr_t addr)
 99 {
100         struct mv_xor_desc *hw_desc = desc->hw_desc;
101         hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
102         if (desc->type == DMA_XOR)
103                 hw_desc->desc_command |= (1 << index);
104 }
105 
106 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
107 {
108         return readl_relaxed(XOR_CURR_DESC(chan));
109 }
110 
111 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
112                                         u32 next_desc_addr)
113 {
114         writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
115 }
116 
117 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
118 {
119         u32 val = readl_relaxed(XOR_INTR_MASK(chan));
120         val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
121         writel_relaxed(val, XOR_INTR_MASK(chan));
122 }
123 
124 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
125 {
126         u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
127         intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
128         return intr_cause;
129 }
130 
131 static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan)
132 {
133         u32 val;
134 
135         val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED;
136         val = ~(val << (chan->idx * 16));
137         dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
138         writel_relaxed(val, XOR_INTR_CAUSE(chan));
139 }
140 
141 static void mv_chan_clear_err_status(struct mv_xor_chan *chan)
142 {
143         u32 val = 0xFFFF0000 >> (chan->idx * 16);
144         writel_relaxed(val, XOR_INTR_CAUSE(chan));
145 }
146 
147 static void mv_chan_set_mode(struct mv_xor_chan *chan,
148                              u32 op_mode)
149 {
150         u32 config = readl_relaxed(XOR_CONFIG(chan));
151 
152         config &= ~0x7;
153         config |= op_mode;
154 
155 #if defined(__BIG_ENDIAN)
156         config |= XOR_DESCRIPTOR_SWAP;
157 #else
158         config &= ~XOR_DESCRIPTOR_SWAP;
159 #endif
160 
161         writel_relaxed(config, XOR_CONFIG(chan));
162 }
163 
164 static void mv_chan_activate(struct mv_xor_chan *chan)
165 {
166         dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
167 
168         /* writel ensures all descriptors are flushed before activation */
169         writel(BIT(0), XOR_ACTIVATION(chan));
170 }
171 
172 static char mv_chan_is_busy(struct mv_xor_chan *chan)
173 {
174         u32 state = readl_relaxed(XOR_ACTIVATION(chan));
175 
176         state = (state >> 4) & 0x3;
177 
178         return (state == 1) ? 1 : 0;
179 }
180 
181 /*
182  * mv_chan_start_new_chain - program the engine to operate on new
183  * chain headed by sw_desc
184  * Caller must hold &mv_chan->lock while calling this function
185  */
186 static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
187                                     struct mv_xor_desc_slot *sw_desc)
188 {
189         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
190                 __func__, __LINE__, sw_desc);
191 
192         /* set the hardware chain */
193         mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
194 
195         mv_chan->pending++;
196         mv_xor_issue_pending(&mv_chan->dmachan);
197 }
198 
199 static dma_cookie_t
200 mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
201                                 struct mv_xor_chan *mv_chan,
202                                 dma_cookie_t cookie)
203 {
204         BUG_ON(desc->async_tx.cookie < 0);
205 
206         if (desc->async_tx.cookie > 0) {
207                 cookie = desc->async_tx.cookie;
208 
209                 /* call the callback (must not sleep or submit new
210                  * operations to this channel)
211                  */
212                 if (desc->async_tx.callback)
213                         desc->async_tx.callback(
214                                 desc->async_tx.callback_param);
215 
216                 dma_descriptor_unmap(&desc->async_tx);
217         }
218 
219         /* run dependent operations */
220         dma_run_dependencies(&desc->async_tx);
221 
222         return cookie;
223 }
224 
225 static int
226 mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan)
227 {
228         struct mv_xor_desc_slot *iter, *_iter;
229 
230         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
231         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
232                                  node) {
233 
234                 if (async_tx_test_ack(&iter->async_tx))
235                         list_move_tail(&iter->node, &mv_chan->free_slots);
236         }
237         return 0;
238 }
239 
240 static int
241 mv_desc_clean_slot(struct mv_xor_desc_slot *desc,
242                    struct mv_xor_chan *mv_chan)
243 {
244         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
245                 __func__, __LINE__, desc, desc->async_tx.flags);
246 
247         /* the client is allowed to attach dependent operations
248          * until 'ack' is set
249          */
250         if (!async_tx_test_ack(&desc->async_tx))
251                 /* move this slot to the completed_slots */
252                 list_move_tail(&desc->node, &mv_chan->completed_slots);
253         else
254                 list_move_tail(&desc->node, &mv_chan->free_slots);
255 
256         return 0;
257 }
258 
259 /* This function must be called with the mv_xor_chan spinlock held */
260 static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan)
261 {
262         struct mv_xor_desc_slot *iter, *_iter;
263         dma_cookie_t cookie = 0;
264         int busy = mv_chan_is_busy(mv_chan);
265         u32 current_desc = mv_chan_get_current_desc(mv_chan);
266         int current_cleaned = 0;
267         struct mv_xor_desc *hw_desc;
268 
269         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
270         dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
271         mv_chan_clean_completed_slots(mv_chan);
272 
273         /* free completed slots from the chain starting with
274          * the oldest descriptor
275          */
276 
277         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
278                                  node) {
279 
280                 /* clean finished descriptors */
281                 hw_desc = iter->hw_desc;
282                 if (hw_desc->status & XOR_DESC_SUCCESS) {
283                         cookie = mv_desc_run_tx_complete_actions(iter, mv_chan,
284                                                                  cookie);
285 
286                         /* done processing desc, clean slot */
287                         mv_desc_clean_slot(iter, mv_chan);
288 
289                         /* break if we did cleaned the current */
290                         if (iter->async_tx.phys == current_desc) {
291                                 current_cleaned = 1;
292                                 break;
293                         }
294                 } else {
295                         if (iter->async_tx.phys == current_desc) {
296                                 current_cleaned = 0;
297                                 break;
298                         }
299                 }
300         }
301 
302         if ((busy == 0) && !list_empty(&mv_chan->chain)) {
303                 if (current_cleaned) {
304                         /*
305                          * current descriptor cleaned and removed, run
306                          * from list head
307                          */
308                         iter = list_entry(mv_chan->chain.next,
309                                           struct mv_xor_desc_slot,
310                                           node);
311                         mv_chan_start_new_chain(mv_chan, iter);
312                 } else {
313                         if (!list_is_last(&iter->node, &mv_chan->chain)) {
314                                 /*
315                                  * descriptors are still waiting after
316                                  * current, trigger them
317                                  */
318                                 iter = list_entry(iter->node.next,
319                                                   struct mv_xor_desc_slot,
320                                                   node);
321                                 mv_chan_start_new_chain(mv_chan, iter);
322                         } else {
323                                 /*
324                                  * some descriptors are still waiting
325                                  * to be cleaned
326                                  */
327                                 tasklet_schedule(&mv_chan->irq_tasklet);
328                         }
329                 }
330         }
331 
332         if (cookie > 0)
333                 mv_chan->dmachan.completed_cookie = cookie;
334 }
335 
336 static void mv_xor_tasklet(unsigned long data)
337 {
338         struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
339 
340         spin_lock_bh(&chan->lock);
341         mv_chan_slot_cleanup(chan);
342         spin_unlock_bh(&chan->lock);
343 }
344 
345 static struct mv_xor_desc_slot *
346 mv_chan_alloc_slot(struct mv_xor_chan *mv_chan)
347 {
348         struct mv_xor_desc_slot *iter;
349 
350         spin_lock_bh(&mv_chan->lock);
351 
352         if (!list_empty(&mv_chan->free_slots)) {
353                 iter = list_first_entry(&mv_chan->free_slots,
354                                         struct mv_xor_desc_slot,
355                                         node);
356 
357                 list_move_tail(&iter->node, &mv_chan->allocated_slots);
358 
359                 spin_unlock_bh(&mv_chan->lock);
360 
361                 /* pre-ack descriptor */
362                 async_tx_ack(&iter->async_tx);
363                 iter->async_tx.cookie = -EBUSY;
364 
365                 return iter;
366 
367         }
368 
369         spin_unlock_bh(&mv_chan->lock);
370 
371         /* try to free some slots if the allocation fails */
372         tasklet_schedule(&mv_chan->irq_tasklet);
373 
374         return NULL;
375 }
376 
377 /************************ DMA engine API functions ****************************/
378 static dma_cookie_t
379 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
380 {
381         struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
382         struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
383         struct mv_xor_desc_slot *old_chain_tail;
384         dma_cookie_t cookie;
385         int new_hw_chain = 1;
386 
387         dev_dbg(mv_chan_to_devp(mv_chan),
388                 "%s sw_desc %p: async_tx %p\n",
389                 __func__, sw_desc, &sw_desc->async_tx);
390 
391         spin_lock_bh(&mv_chan->lock);
392         cookie = dma_cookie_assign(tx);
393 
394         if (list_empty(&mv_chan->chain))
395                 list_move_tail(&sw_desc->node, &mv_chan->chain);
396         else {
397                 new_hw_chain = 0;
398 
399                 old_chain_tail = list_entry(mv_chan->chain.prev,
400                                             struct mv_xor_desc_slot,
401                                             node);
402                 list_move_tail(&sw_desc->node, &mv_chan->chain);
403 
404                 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
405                         &old_chain_tail->async_tx.phys);
406 
407                 /* fix up the hardware chain */
408                 mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
409 
410                 /* if the channel is not busy */
411                 if (!mv_chan_is_busy(mv_chan)) {
412                         u32 current_desc = mv_chan_get_current_desc(mv_chan);
413                         /*
414                          * and the curren desc is the end of the chain before
415                          * the append, then we need to start the channel
416                          */
417                         if (current_desc == old_chain_tail->async_tx.phys)
418                                 new_hw_chain = 1;
419                 }
420         }
421 
422         if (new_hw_chain)
423                 mv_chan_start_new_chain(mv_chan, sw_desc);
424 
425         spin_unlock_bh(&mv_chan->lock);
426 
427         return cookie;
428 }
429 
430 /* returns the number of allocated descriptors */
431 static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
432 {
433         void *virt_desc;
434         dma_addr_t dma_desc;
435         int idx;
436         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
437         struct mv_xor_desc_slot *slot = NULL;
438         int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
439 
440         /* Allocate descriptor slots */
441         idx = mv_chan->slots_allocated;
442         while (idx < num_descs_in_pool) {
443                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
444                 if (!slot) {
445                         dev_info(mv_chan_to_devp(mv_chan),
446                                  "channel only initialized %d descriptor slots",
447                                  idx);
448                         break;
449                 }
450                 virt_desc = mv_chan->dma_desc_pool_virt;
451                 slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
452 
453                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
454                 slot->async_tx.tx_submit = mv_xor_tx_submit;
455                 INIT_LIST_HEAD(&slot->node);
456                 dma_desc = mv_chan->dma_desc_pool;
457                 slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
458                 slot->idx = idx++;
459 
460                 spin_lock_bh(&mv_chan->lock);
461                 mv_chan->slots_allocated = idx;
462                 list_add_tail(&slot->node, &mv_chan->free_slots);
463                 spin_unlock_bh(&mv_chan->lock);
464         }
465 
466         dev_dbg(mv_chan_to_devp(mv_chan),
467                 "allocated %d descriptor slots\n",
468                 mv_chan->slots_allocated);
469 
470         return mv_chan->slots_allocated ? : -ENOMEM;
471 }
472 
473 static struct dma_async_tx_descriptor *
474 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
475                     unsigned int src_cnt, size_t len, unsigned long flags)
476 {
477         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
478         struct mv_xor_desc_slot *sw_desc;
479 
480         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
481                 return NULL;
482 
483         BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
484 
485         dev_dbg(mv_chan_to_devp(mv_chan),
486                 "%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
487                 __func__, src_cnt, len, &dest, flags);
488 
489         sw_desc = mv_chan_alloc_slot(mv_chan);
490         if (sw_desc) {
491                 sw_desc->type = DMA_XOR;
492                 sw_desc->async_tx.flags = flags;
493                 mv_desc_init(sw_desc, dest, len, flags);
494                 if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
495                         mv_desc_set_mode(sw_desc);
496                 while (src_cnt--)
497                         mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
498         }
499 
500         dev_dbg(mv_chan_to_devp(mv_chan),
501                 "%s sw_desc %p async_tx %p \n",
502                 __func__, sw_desc, &sw_desc->async_tx);
503         return sw_desc ? &sw_desc->async_tx : NULL;
504 }
505 
506 static struct dma_async_tx_descriptor *
507 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
508                 size_t len, unsigned long flags)
509 {
510         /*
511          * A MEMCPY operation is identical to an XOR operation with only
512          * a single source address.
513          */
514         return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
515 }
516 
517 static struct dma_async_tx_descriptor *
518 mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
519 {
520         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
521         dma_addr_t src, dest;
522         size_t len;
523 
524         src = mv_chan->dummy_src_addr;
525         dest = mv_chan->dummy_dst_addr;
526         len = MV_XOR_MIN_BYTE_COUNT;
527 
528         /*
529          * We implement the DMA_INTERRUPT operation as a minimum sized
530          * XOR operation with a single dummy source address.
531          */
532         return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
533 }
534 
535 static void mv_xor_free_chan_resources(struct dma_chan *chan)
536 {
537         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
538         struct mv_xor_desc_slot *iter, *_iter;
539         int in_use_descs = 0;
540 
541         spin_lock_bh(&mv_chan->lock);
542 
543         mv_chan_slot_cleanup(mv_chan);
544 
545         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
546                                         node) {
547                 in_use_descs++;
548                 list_move_tail(&iter->node, &mv_chan->free_slots);
549         }
550         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
551                                  node) {
552                 in_use_descs++;
553                 list_move_tail(&iter->node, &mv_chan->free_slots);
554         }
555         list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots,
556                                  node) {
557                 in_use_descs++;
558                 list_move_tail(&iter->node, &mv_chan->free_slots);
559         }
560         list_for_each_entry_safe_reverse(
561                 iter, _iter, &mv_chan->free_slots, node) {
562                 list_del(&iter->node);
563                 kfree(iter);
564                 mv_chan->slots_allocated--;
565         }
566 
567         dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
568                 __func__, mv_chan->slots_allocated);
569         spin_unlock_bh(&mv_chan->lock);
570 
571         if (in_use_descs)
572                 dev_err(mv_chan_to_devp(mv_chan),
573                         "freeing %d in use descriptors!\n", in_use_descs);
574 }
575 
576 /**
577  * mv_xor_status - poll the status of an XOR transaction
578  * @chan: XOR channel handle
579  * @cookie: XOR transaction identifier
580  * @txstate: XOR transactions state holder (or NULL)
581  */
582 static enum dma_status mv_xor_status(struct dma_chan *chan,
583                                           dma_cookie_t cookie,
584                                           struct dma_tx_state *txstate)
585 {
586         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
587         enum dma_status ret;
588 
589         ret = dma_cookie_status(chan, cookie, txstate);
590         if (ret == DMA_COMPLETE)
591                 return ret;
592 
593         spin_lock_bh(&mv_chan->lock);
594         mv_chan_slot_cleanup(mv_chan);
595         spin_unlock_bh(&mv_chan->lock);
596 
597         return dma_cookie_status(chan, cookie, txstate);
598 }
599 
600 static void mv_chan_dump_regs(struct mv_xor_chan *chan)
601 {
602         u32 val;
603 
604         val = readl_relaxed(XOR_CONFIG(chan));
605         dev_err(mv_chan_to_devp(chan), "config       0x%08x\n", val);
606 
607         val = readl_relaxed(XOR_ACTIVATION(chan));
608         dev_err(mv_chan_to_devp(chan), "activation   0x%08x\n", val);
609 
610         val = readl_relaxed(XOR_INTR_CAUSE(chan));
611         dev_err(mv_chan_to_devp(chan), "intr cause   0x%08x\n", val);
612 
613         val = readl_relaxed(XOR_INTR_MASK(chan));
614         dev_err(mv_chan_to_devp(chan), "intr mask    0x%08x\n", val);
615 
616         val = readl_relaxed(XOR_ERROR_CAUSE(chan));
617         dev_err(mv_chan_to_devp(chan), "error cause  0x%08x\n", val);
618 
619         val = readl_relaxed(XOR_ERROR_ADDR(chan));
620         dev_err(mv_chan_to_devp(chan), "error addr   0x%08x\n", val);
621 }
622 
623 static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan,
624                                           u32 intr_cause)
625 {
626         if (intr_cause & XOR_INT_ERR_DECODE) {
627                 dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
628                 return;
629         }
630 
631         dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
632                 chan->idx, intr_cause);
633 
634         mv_chan_dump_regs(chan);
635         WARN_ON(1);
636 }
637 
638 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
639 {
640         struct mv_xor_chan *chan = data;
641         u32 intr_cause = mv_chan_get_intr_cause(chan);
642 
643         dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
644 
645         if (intr_cause & XOR_INTR_ERRORS)
646                 mv_chan_err_interrupt_handler(chan, intr_cause);
647 
648         tasklet_schedule(&chan->irq_tasklet);
649 
650         mv_chan_clear_eoc_cause(chan);
651 
652         return IRQ_HANDLED;
653 }
654 
655 static void mv_xor_issue_pending(struct dma_chan *chan)
656 {
657         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
658 
659         if (mv_chan->pending >= MV_XOR_THRESHOLD) {
660                 mv_chan->pending = 0;
661                 mv_chan_activate(mv_chan);
662         }
663 }
664 
665 /*
666  * Perform a transaction to verify the HW works.
667  */
668 
669 static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
670 {
671         int i, ret;
672         void *src, *dest;
673         dma_addr_t src_dma, dest_dma;
674         struct dma_chan *dma_chan;
675         dma_cookie_t cookie;
676         struct dma_async_tx_descriptor *tx;
677         struct dmaengine_unmap_data *unmap;
678         int err = 0;
679 
680         src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
681         if (!src)
682                 return -ENOMEM;
683 
684         dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
685         if (!dest) {
686                 kfree(src);
687                 return -ENOMEM;
688         }
689 
690         /* Fill in src buffer */
691         for (i = 0; i < PAGE_SIZE; i++)
692                 ((u8 *) src)[i] = (u8)i;
693 
694         dma_chan = &mv_chan->dmachan;
695         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
696                 err = -ENODEV;
697                 goto out;
698         }
699 
700         unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
701         if (!unmap) {
702                 err = -ENOMEM;
703                 goto free_resources;
704         }
705 
706         src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src),
707                                (size_t)src & ~PAGE_MASK, PAGE_SIZE,
708                                DMA_TO_DEVICE);
709         unmap->addr[0] = src_dma;
710 
711         ret = dma_mapping_error(dma_chan->device->dev, src_dma);
712         if (ret) {
713                 err = -ENOMEM;
714                 goto free_resources;
715         }
716         unmap->to_cnt = 1;
717 
718         dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest),
719                                 (size_t)dest & ~PAGE_MASK, PAGE_SIZE,
720                                 DMA_FROM_DEVICE);
721         unmap->addr[1] = dest_dma;
722 
723         ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
724         if (ret) {
725                 err = -ENOMEM;
726                 goto free_resources;
727         }
728         unmap->from_cnt = 1;
729         unmap->len = PAGE_SIZE;
730 
731         tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
732                                     PAGE_SIZE, 0);
733         if (!tx) {
734                 dev_err(dma_chan->device->dev,
735                         "Self-test cannot prepare operation, disabling\n");
736                 err = -ENODEV;
737                 goto free_resources;
738         }
739 
740         cookie = mv_xor_tx_submit(tx);
741         if (dma_submit_error(cookie)) {
742                 dev_err(dma_chan->device->dev,
743                         "Self-test submit error, disabling\n");
744                 err = -ENODEV;
745                 goto free_resources;
746         }
747 
748         mv_xor_issue_pending(dma_chan);
749         async_tx_ack(tx);
750         msleep(1);
751 
752         if (mv_xor_status(dma_chan, cookie, NULL) !=
753             DMA_COMPLETE) {
754                 dev_err(dma_chan->device->dev,
755                         "Self-test copy timed out, disabling\n");
756                 err = -ENODEV;
757                 goto free_resources;
758         }
759 
760         dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
761                                 PAGE_SIZE, DMA_FROM_DEVICE);
762         if (memcmp(src, dest, PAGE_SIZE)) {
763                 dev_err(dma_chan->device->dev,
764                         "Self-test copy failed compare, disabling\n");
765                 err = -ENODEV;
766                 goto free_resources;
767         }
768 
769 free_resources:
770         dmaengine_unmap_put(unmap);
771         mv_xor_free_chan_resources(dma_chan);
772 out:
773         kfree(src);
774         kfree(dest);
775         return err;
776 }
777 
778 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
779 static int
780 mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
781 {
782         int i, src_idx, ret;
783         struct page *dest;
784         struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
785         dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
786         dma_addr_t dest_dma;
787         struct dma_async_tx_descriptor *tx;
788         struct dmaengine_unmap_data *unmap;
789         struct dma_chan *dma_chan;
790         dma_cookie_t cookie;
791         u8 cmp_byte = 0;
792         u32 cmp_word;
793         int err = 0;
794         int src_count = MV_XOR_NUM_SRC_TEST;
795 
796         for (src_idx = 0; src_idx < src_count; src_idx++) {
797                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
798                 if (!xor_srcs[src_idx]) {
799                         while (src_idx--)
800                                 __free_page(xor_srcs[src_idx]);
801                         return -ENOMEM;
802                 }
803         }
804 
805         dest = alloc_page(GFP_KERNEL);
806         if (!dest) {
807                 while (src_idx--)
808                         __free_page(xor_srcs[src_idx]);
809                 return -ENOMEM;
810         }
811 
812         /* Fill in src buffers */
813         for (src_idx = 0; src_idx < src_count; src_idx++) {
814                 u8 *ptr = page_address(xor_srcs[src_idx]);
815                 for (i = 0; i < PAGE_SIZE; i++)
816                         ptr[i] = (1 << src_idx);
817         }
818 
819         for (src_idx = 0; src_idx < src_count; src_idx++)
820                 cmp_byte ^= (u8) (1 << src_idx);
821 
822         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
823                 (cmp_byte << 8) | cmp_byte;
824 
825         memset(page_address(dest), 0, PAGE_SIZE);
826 
827         dma_chan = &mv_chan->dmachan;
828         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
829                 err = -ENODEV;
830                 goto out;
831         }
832 
833         unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
834                                          GFP_KERNEL);
835         if (!unmap) {
836                 err = -ENOMEM;
837                 goto free_resources;
838         }
839 
840         /* test xor */
841         for (i = 0; i < src_count; i++) {
842                 unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
843                                               0, PAGE_SIZE, DMA_TO_DEVICE);
844                 dma_srcs[i] = unmap->addr[i];
845                 ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
846                 if (ret) {
847                         err = -ENOMEM;
848                         goto free_resources;
849                 }
850                 unmap->to_cnt++;
851         }
852 
853         unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
854                                       DMA_FROM_DEVICE);
855         dest_dma = unmap->addr[src_count];
856         ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
857         if (ret) {
858                 err = -ENOMEM;
859                 goto free_resources;
860         }
861         unmap->from_cnt = 1;
862         unmap->len = PAGE_SIZE;
863 
864         tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
865                                  src_count, PAGE_SIZE, 0);
866         if (!tx) {
867                 dev_err(dma_chan->device->dev,
868                         "Self-test cannot prepare operation, disabling\n");
869                 err = -ENODEV;
870                 goto free_resources;
871         }
872 
873         cookie = mv_xor_tx_submit(tx);
874         if (dma_submit_error(cookie)) {
875                 dev_err(dma_chan->device->dev,
876                         "Self-test submit error, disabling\n");
877                 err = -ENODEV;
878                 goto free_resources;
879         }
880 
881         mv_xor_issue_pending(dma_chan);
882         async_tx_ack(tx);
883         msleep(8);
884 
885         if (mv_xor_status(dma_chan, cookie, NULL) !=
886             DMA_COMPLETE) {
887                 dev_err(dma_chan->device->dev,
888                         "Self-test xor timed out, disabling\n");
889                 err = -ENODEV;
890                 goto free_resources;
891         }
892 
893         dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
894                                 PAGE_SIZE, DMA_FROM_DEVICE);
895         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
896                 u32 *ptr = page_address(dest);
897                 if (ptr[i] != cmp_word) {
898                         dev_err(dma_chan->device->dev,
899                                 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
900                                 i, ptr[i], cmp_word);
901                         err = -ENODEV;
902                         goto free_resources;
903                 }
904         }
905 
906 free_resources:
907         dmaengine_unmap_put(unmap);
908         mv_xor_free_chan_resources(dma_chan);
909 out:
910         src_idx = src_count;
911         while (src_idx--)
912                 __free_page(xor_srcs[src_idx]);
913         __free_page(dest);
914         return err;
915 }
916 
917 static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
918 {
919         struct dma_chan *chan, *_chan;
920         struct device *dev = mv_chan->dmadev.dev;
921 
922         dma_async_device_unregister(&mv_chan->dmadev);
923 
924         dma_free_coherent(dev, MV_XOR_POOL_SIZE,
925                           mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
926         dma_unmap_single(dev, mv_chan->dummy_src_addr,
927                          MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
928         dma_unmap_single(dev, mv_chan->dummy_dst_addr,
929                          MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
930 
931         list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
932                                  device_node) {
933                 list_del(&chan->device_node);
934         }
935 
936         free_irq(mv_chan->irq, mv_chan);
937 
938         return 0;
939 }
940 
941 static struct mv_xor_chan *
942 mv_xor_channel_add(struct mv_xor_device *xordev,
943                    struct platform_device *pdev,
944                    int idx, dma_cap_mask_t cap_mask, int irq)
945 {
946         int ret = 0;
947         struct mv_xor_chan *mv_chan;
948         struct dma_device *dma_dev;
949 
950         mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
951         if (!mv_chan)
952                 return ERR_PTR(-ENOMEM);
953 
954         mv_chan->idx = idx;
955         mv_chan->irq = irq;
956         if (xordev->xor_type == XOR_ORION)
957                 mv_chan->op_in_desc = XOR_MODE_IN_REG;
958         else
959                 mv_chan->op_in_desc = XOR_MODE_IN_DESC;
960 
961         dma_dev = &mv_chan->dmadev;
962 
963         /*
964          * These source and destination dummy buffers are used to implement
965          * a DMA_INTERRUPT operation as a minimum-sized XOR operation.
966          * Hence, we only need to map the buffers at initialization-time.
967          */
968         mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
969                 mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
970         mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
971                 mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
972 
973         /* allocate coherent memory for hardware descriptors
974          * note: writecombine gives slightly better performance, but
975          * requires that we explicitly flush the writes
976          */
977         mv_chan->dma_desc_pool_virt =
978           dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
979                        GFP_KERNEL);
980         if (!mv_chan->dma_desc_pool_virt)
981                 return ERR_PTR(-ENOMEM);
982 
983         /* discover transaction capabilites from the platform data */
984         dma_dev->cap_mask = cap_mask;
985 
986         INIT_LIST_HEAD(&dma_dev->channels);
987 
988         /* set base routines */
989         dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
990         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
991         dma_dev->device_tx_status = mv_xor_status;
992         dma_dev->device_issue_pending = mv_xor_issue_pending;
993         dma_dev->dev = &pdev->dev;
994 
995         /* set prep routines based on capability */
996         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
997                 dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt;
998         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
999                 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1000         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1001                 dma_dev->max_xor = 8;
1002                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1003         }
1004 
1005         mv_chan->mmr_base = xordev->xor_base;
1006         mv_chan->mmr_high_base = xordev->xor_high_base;
1007         tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1008                      mv_chan);
1009 
1010         /* clear errors before enabling interrupts */
1011         mv_chan_clear_err_status(mv_chan);
1012 
1013         ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1014                           0, dev_name(&pdev->dev), mv_chan);
1015         if (ret)
1016                 goto err_free_dma;
1017 
1018         mv_chan_unmask_interrupts(mv_chan);
1019 
1020         if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
1021                 mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC);
1022         else
1023                 mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR);
1024 
1025         spin_lock_init(&mv_chan->lock);
1026         INIT_LIST_HEAD(&mv_chan->chain);
1027         INIT_LIST_HEAD(&mv_chan->completed_slots);
1028         INIT_LIST_HEAD(&mv_chan->free_slots);
1029         INIT_LIST_HEAD(&mv_chan->allocated_slots);
1030         mv_chan->dmachan.device = dma_dev;
1031         dma_cookie_init(&mv_chan->dmachan);
1032 
1033         list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1034 
1035         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1036                 ret = mv_chan_memcpy_self_test(mv_chan);
1037                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1038                 if (ret)
1039                         goto err_free_irq;
1040         }
1041 
1042         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1043                 ret = mv_chan_xor_self_test(mv_chan);
1044                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1045                 if (ret)
1046                         goto err_free_irq;
1047         }
1048 
1049         dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n",
1050                  mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode",
1051                  dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1052                  dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1053                  dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1054 
1055         dma_async_device_register(dma_dev);
1056         return mv_chan;
1057 
1058 err_free_irq:
1059         free_irq(mv_chan->irq, mv_chan);
1060 err_free_dma:
1061         dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
1062                           mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1063         return ERR_PTR(ret);
1064 }
1065 
1066 static void
1067 mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
1068                          const struct mbus_dram_target_info *dram)
1069 {
1070         void __iomem *base = xordev->xor_high_base;
1071         u32 win_enable = 0;
1072         int i;
1073 
1074         for (i = 0; i < 8; i++) {
1075                 writel(0, base + WINDOW_BASE(i));
1076                 writel(0, base + WINDOW_SIZE(i));
1077                 if (i < 4)
1078                         writel(0, base + WINDOW_REMAP_HIGH(i));
1079         }
1080 
1081         for (i = 0; i < dram->num_cs; i++) {
1082                 const struct mbus_dram_window *cs = dram->cs + i;
1083 
1084                 writel((cs->base & 0xffff0000) |
1085                        (cs->mbus_attr << 8) |
1086                        dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1087                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1088 
1089                 win_enable |= (1 << i);
1090                 win_enable |= 3 << (16 + (2 * i));
1091         }
1092 
1093         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1094         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1095         writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1096         writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1097 }
1098 
1099 static void
1100 mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
1101 {
1102         void __iomem *base = xordev->xor_high_base;
1103         u32 win_enable = 0;
1104         int i;
1105 
1106         for (i = 0; i < 8; i++) {
1107                 writel(0, base + WINDOW_BASE(i));
1108                 writel(0, base + WINDOW_SIZE(i));
1109                 if (i < 4)
1110                         writel(0, base + WINDOW_REMAP_HIGH(i));
1111         }
1112         /*
1113          * For Armada3700 open default 4GB Mbus window. The dram
1114          * related configuration are done at AXIS level.
1115          */
1116         writel(0xffff0000, base + WINDOW_SIZE(0));
1117         win_enable |= 1;
1118         win_enable |= 3 << 16;
1119 
1120         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1121         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1122         writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1123         writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1124 }
1125 
1126 /*
1127  * Since this XOR driver is basically used only for RAID5, we don't
1128  * need to care about synchronizing ->suspend with DMA activity,
1129  * because the DMA engine will naturally be quiet due to the block
1130  * devices being suspended.
1131  */
1132 static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
1133 {
1134         struct mv_xor_device *xordev = platform_get_drvdata(pdev);
1135         int i;
1136 
1137         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1138                 struct mv_xor_chan *mv_chan = xordev->channels[i];
1139 
1140                 if (!mv_chan)
1141                         continue;
1142 
1143                 mv_chan->saved_config_reg =
1144                         readl_relaxed(XOR_CONFIG(mv_chan));
1145                 mv_chan->saved_int_mask_reg =
1146                         readl_relaxed(XOR_INTR_MASK(mv_chan));
1147         }
1148 
1149         return 0;
1150 }
1151 
1152 static int mv_xor_resume(struct platform_device *dev)
1153 {
1154         struct mv_xor_device *xordev = platform_get_drvdata(dev);
1155         const struct mbus_dram_target_info *dram;
1156         int i;
1157 
1158         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1159                 struct mv_xor_chan *mv_chan = xordev->channels[i];
1160 
1161                 if (!mv_chan)
1162                         continue;
1163 
1164                 writel_relaxed(mv_chan->saved_config_reg,
1165                                XOR_CONFIG(mv_chan));
1166                 writel_relaxed(mv_chan->saved_int_mask_reg,
1167                                XOR_INTR_MASK(mv_chan));
1168         }
1169 
1170         if (xordev->xor_type == XOR_ARMADA_37XX) {
1171                 mv_xor_conf_mbus_windows_a3700(xordev);
1172                 return 0;
1173         }
1174 
1175         dram = mv_mbus_dram_info();
1176         if (dram)
1177                 mv_xor_conf_mbus_windows(xordev, dram);
1178 
1179         return 0;
1180 }
1181 
1182 static const struct of_device_id mv_xor_dt_ids[] = {
1183         { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
1184         { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
1185         { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
1186         {},
1187 };
1188 
1189 static unsigned int mv_xor_engine_count;
1190 
1191 static int mv_xor_probe(struct platform_device *pdev)
1192 {
1193         const struct mbus_dram_target_info *dram;
1194         struct mv_xor_device *xordev;
1195         struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
1196         struct resource *res;
1197         unsigned int max_engines, max_channels;
1198         int i, ret;
1199 
1200         dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
1201 
1202         xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1203         if (!xordev)
1204                 return -ENOMEM;
1205 
1206         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207         if (!res)
1208                 return -ENODEV;
1209 
1210         xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1211                                         resource_size(res));
1212         if (!xordev->xor_base)
1213                 return -EBUSY;
1214 
1215         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1216         if (!res)
1217                 return -ENODEV;
1218 
1219         xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1220                                              resource_size(res));
1221         if (!xordev->xor_high_base)
1222                 return -EBUSY;
1223 
1224         platform_set_drvdata(pdev, xordev);
1225 
1226 
1227         /*
1228          * We need to know which type of XOR device we use before
1229          * setting up. In non-dt case it can only be the legacy one.
1230          */
1231         xordev->xor_type = XOR_ORION;
1232         if (pdev->dev.of_node) {
1233                 const struct of_device_id *of_id =
1234                         of_match_device(mv_xor_dt_ids,
1235                                         &pdev->dev);
1236 
1237                 xordev->xor_type = (uintptr_t)of_id->data;
1238         }
1239 
1240         /*
1241          * (Re-)program MBUS remapping windows if we are asked to.
1242          */
1243         if (xordev->xor_type == XOR_ARMADA_37XX) {
1244                 mv_xor_conf_mbus_windows_a3700(xordev);
1245         } else {
1246                 dram = mv_mbus_dram_info();
1247                 if (dram)
1248                         mv_xor_conf_mbus_windows(xordev, dram);
1249         }
1250 
1251         /* Not all platforms can gate the clock, so it is not
1252          * an error if the clock does not exists.
1253          */
1254         xordev->clk = clk_get(&pdev->dev, NULL);
1255         if (!IS_ERR(xordev->clk))
1256                 clk_prepare_enable(xordev->clk);
1257 
1258         /*
1259          * We don't want to have more than one channel per CPU in
1260          * order for async_tx to perform well. So we limit the number
1261          * of engines and channels so that we take into account this
1262          * constraint. Note that we also want to use channels from
1263          * separate engines when possible.  For dual-CPU Armada 3700
1264          * SoC with single XOR engine allow using its both channels.
1265          */
1266         max_engines = num_present_cpus();
1267         if (xordev->xor_type == XOR_ARMADA_37XX)
1268                 max_channels =  num_present_cpus();
1269         else
1270                 max_channels = min_t(unsigned int,
1271                                      MV_XOR_MAX_CHANNELS,
1272                                      DIV_ROUND_UP(num_present_cpus(), 2));
1273 
1274         if (mv_xor_engine_count >= max_engines)
1275                 return 0;
1276 
1277         if (pdev->dev.of_node) {
1278                 struct device_node *np;
1279                 int i = 0;
1280 
1281                 for_each_child_of_node(pdev->dev.of_node, np) {
1282                         struct mv_xor_chan *chan;
1283                         dma_cap_mask_t cap_mask;
1284                         int irq;
1285 
1286                         if (i >= max_channels)
1287                                 continue;
1288 
1289                         dma_cap_zero(cap_mask);
1290                         dma_cap_set(DMA_MEMCPY, cap_mask);
1291                         dma_cap_set(DMA_XOR, cap_mask);
1292                         dma_cap_set(DMA_INTERRUPT, cap_mask);
1293 
1294                         irq = irq_of_parse_and_map(np, 0);
1295                         if (!irq) {
1296                                 ret = -ENODEV;
1297                                 goto err_channel_add;
1298                         }
1299 
1300                         chan = mv_xor_channel_add(xordev, pdev, i,
1301                                                   cap_mask, irq);
1302                         if (IS_ERR(chan)) {
1303                                 ret = PTR_ERR(chan);
1304                                 irq_dispose_mapping(irq);
1305                                 goto err_channel_add;
1306                         }
1307 
1308                         xordev->channels[i] = chan;
1309                         i++;
1310                 }
1311         } else if (pdata && pdata->channels) {
1312                 for (i = 0; i < max_channels; i++) {
1313                         struct mv_xor_channel_data *cd;
1314                         struct mv_xor_chan *chan;
1315                         int irq;
1316 
1317                         cd = &pdata->channels[i];
1318                         if (!cd) {
1319                                 ret = -ENODEV;
1320                                 goto err_channel_add;
1321                         }
1322 
1323                         irq = platform_get_irq(pdev, i);
1324                         if (irq < 0) {
1325                                 ret = irq;
1326                                 goto err_channel_add;
1327                         }
1328 
1329                         chan = mv_xor_channel_add(xordev, pdev, i,
1330                                                   cd->cap_mask, irq);
1331                         if (IS_ERR(chan)) {
1332                                 ret = PTR_ERR(chan);
1333                                 goto err_channel_add;
1334                         }
1335 
1336                         xordev->channels[i] = chan;
1337                 }
1338         }
1339 
1340         return 0;
1341 
1342 err_channel_add:
1343         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
1344                 if (xordev->channels[i]) {
1345                         mv_xor_channel_remove(xordev->channels[i]);
1346                         if (pdev->dev.of_node)
1347                                 irq_dispose_mapping(xordev->channels[i]->irq);
1348                 }
1349 
1350         if (!IS_ERR(xordev->clk)) {
1351                 clk_disable_unprepare(xordev->clk);
1352                 clk_put(xordev->clk);
1353         }
1354 
1355         return ret;
1356 }
1357 
1358 static struct platform_driver mv_xor_driver = {
1359         .probe          = mv_xor_probe,
1360         .suspend        = mv_xor_suspend,
1361         .resume         = mv_xor_resume,
1362         .driver         = {
1363                 .name           = MV_XOR_NAME,
1364                 .of_match_table = of_match_ptr(mv_xor_dt_ids),
1365         },
1366 };
1367 
1368 
1369 static int __init mv_xor_init(void)
1370 {
1371         return platform_driver_register(&mv_xor_driver);
1372 }
1373 device_initcall(mv_xor_init);
1374 
1375 /*
1376 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1377 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1378 MODULE_LICENSE("GPL");
1379 */
1380 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us