Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/dma/mmp_tdma.c

  1 /*
  2  * Driver For Marvell Two-channel DMA Engine
  3  *
  4  * Copyright: Marvell International Ltd.
  5  *
  6  * The code contained herein is licensed under the GNU General Public
  7  * License. You may obtain a copy of the GNU General Public License
  8  * Version 2 or later at the following locations:
  9  *
 10  */
 11 
 12 #include <linux/err.h>
 13 #include <linux/module.h>
 14 #include <linux/init.h>
 15 #include <linux/types.h>
 16 #include <linux/interrupt.h>
 17 #include <linux/dma-mapping.h>
 18 #include <linux/slab.h>
 19 #include <linux/dmaengine.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/device.h>
 22 #include <mach/regs-icu.h>
 23 #include <linux/platform_data/dma-mmp_tdma.h>
 24 #include <linux/of_device.h>
 25 #include <linux/of_dma.h>
 26 
 27 #include "dmaengine.h"
 28 
 29 /*
 30  * Two-Channel DMA registers
 31  */
 32 #define TDBCR           0x00    /* Byte Count */
 33 #define TDSAR           0x10    /* Src Addr */
 34 #define TDDAR           0x20    /* Dst Addr */
 35 #define TDNDPR          0x30    /* Next Desc */
 36 #define TDCR            0x40    /* Control */
 37 #define TDCP            0x60    /* Priority*/
 38 #define TDCDPR          0x70    /* Current Desc */
 39 #define TDIMR           0x80    /* Int Mask */
 40 #define TDISR           0xa0    /* Int Status */
 41 
 42 /* Two-Channel DMA Control Register */
 43 #define TDCR_SSZ_8_BITS         (0x0 << 22)     /* Sample Size */
 44 #define TDCR_SSZ_12_BITS        (0x1 << 22)
 45 #define TDCR_SSZ_16_BITS        (0x2 << 22)
 46 #define TDCR_SSZ_20_BITS        (0x3 << 22)
 47 #define TDCR_SSZ_24_BITS        (0x4 << 22)
 48 #define TDCR_SSZ_32_BITS        (0x5 << 22)
 49 #define TDCR_SSZ_SHIFT          (0x1 << 22)
 50 #define TDCR_SSZ_MASK           (0x7 << 22)
 51 #define TDCR_SSPMOD             (0x1 << 21)     /* SSP MOD */
 52 #define TDCR_ABR                (0x1 << 20)     /* Channel Abort */
 53 #define TDCR_CDE                (0x1 << 17)     /* Close Desc Enable */
 54 #define TDCR_PACKMOD            (0x1 << 16)     /* Pack Mode (ADMA Only) */
 55 #define TDCR_CHANACT            (0x1 << 14)     /* Channel Active */
 56 #define TDCR_FETCHND            (0x1 << 13)     /* Fetch Next Desc */
 57 #define TDCR_CHANEN             (0x1 << 12)     /* Channel Enable */
 58 #define TDCR_INTMODE            (0x1 << 10)     /* Interrupt Mode */
 59 #define TDCR_CHAINMOD           (0x1 << 9)      /* Chain Mode */
 60 #define TDCR_BURSTSZ_MSK        (0x7 << 6)      /* Burst Size */
 61 #define TDCR_BURSTSZ_4B         (0x0 << 6)
 62 #define TDCR_BURSTSZ_8B         (0x1 << 6)
 63 #define TDCR_BURSTSZ_16B        (0x3 << 6)
 64 #define TDCR_BURSTSZ_32B        (0x6 << 6)
 65 #define TDCR_BURSTSZ_64B        (0x7 << 6)
 66 #define TDCR_BURSTSZ_SQU_1B             (0x5 << 6)
 67 #define TDCR_BURSTSZ_SQU_2B             (0x6 << 6)
 68 #define TDCR_BURSTSZ_SQU_4B             (0x0 << 6)
 69 #define TDCR_BURSTSZ_SQU_8B             (0x1 << 6)
 70 #define TDCR_BURSTSZ_SQU_16B    (0x3 << 6)
 71 #define TDCR_BURSTSZ_SQU_32B    (0x7 << 6)
 72 #define TDCR_BURSTSZ_128B       (0x5 << 6)
 73 #define TDCR_DSTDIR_MSK         (0x3 << 4)      /* Dst Direction */
 74 #define TDCR_DSTDIR_ADDR_HOLD   (0x2 << 4)      /* Dst Addr Hold */
 75 #define TDCR_DSTDIR_ADDR_INC    (0x0 << 4)      /* Dst Addr Increment */
 76 #define TDCR_SRCDIR_MSK         (0x3 << 2)      /* Src Direction */
 77 #define TDCR_SRCDIR_ADDR_HOLD   (0x2 << 2)      /* Src Addr Hold */
 78 #define TDCR_SRCDIR_ADDR_INC    (0x0 << 2)      /* Src Addr Increment */
 79 #define TDCR_DSTDESCCONT        (0x1 << 1)
 80 #define TDCR_SRCDESTCONT        (0x1 << 0)
 81 
 82 /* Two-Channel DMA Int Mask Register */
 83 #define TDIMR_COMP              (0x1 << 0)
 84 
 85 /* Two-Channel DMA Int Status Register */
 86 #define TDISR_COMP              (0x1 << 0)
 87 
 88 /*
 89  * Two-Channel DMA Descriptor Struct
 90  * NOTE: desc's buf must be aligned to 16 bytes.
 91  */
 92 struct mmp_tdma_desc {
 93         u32 byte_cnt;
 94         u32 src_addr;
 95         u32 dst_addr;
 96         u32 nxt_desc;
 97 };
 98 
 99 enum mmp_tdma_type {
100         MMP_AUD_TDMA = 0,
101         PXA910_SQU,
102 };
103 
104 #define TDMA_ALIGNMENT          3
105 #define TDMA_MAX_XFER_BYTES    SZ_64K
106 
107 struct mmp_tdma_chan {
108         struct device                   *dev;
109         struct dma_chan                 chan;
110         struct dma_async_tx_descriptor  desc;
111         struct tasklet_struct           tasklet;
112 
113         struct mmp_tdma_desc            *desc_arr;
114         phys_addr_t                     desc_arr_phys;
115         int                             desc_num;
116         enum dma_transfer_direction     dir;
117         dma_addr_t                      dev_addr;
118         u32                             burst_sz;
119         enum dma_slave_buswidth         buswidth;
120         enum dma_status                 status;
121 
122         int                             idx;
123         enum mmp_tdma_type              type;
124         int                             irq;
125         void __iomem                    *reg_base;
126 
127         size_t                          buf_len;
128         size_t                          period_len;
129         size_t                          pos;
130 
131         struct gen_pool                 *pool;
132 };
133 
134 #define TDMA_CHANNEL_NUM 2
135 struct mmp_tdma_device {
136         struct device                   *dev;
137         void __iomem                    *base;
138         struct dma_device               device;
139         struct mmp_tdma_chan            *tdmac[TDMA_CHANNEL_NUM];
140 };
141 
142 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
143 
144 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
145 {
146         writel(phys, tdmac->reg_base + TDNDPR);
147         writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
148                                         tdmac->reg_base + TDCR);
149 }
150 
151 static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
152 {
153         if (enable)
154                 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
155         else
156                 writel(0, tdmac->reg_base + TDIMR);
157 }
158 
159 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
160 {
161         /* enable dma chan */
162         writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
163                                         tdmac->reg_base + TDCR);
164         tdmac->status = DMA_IN_PROGRESS;
165 }
166 
167 static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
168 {
169         writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
170                                         tdmac->reg_base + TDCR);
171 
172         tdmac->status = DMA_COMPLETE;
173 }
174 
175 static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
176 {
177         writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
178                                         tdmac->reg_base + TDCR);
179         tdmac->status = DMA_IN_PROGRESS;
180 }
181 
182 static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
183 {
184         writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
185                                         tdmac->reg_base + TDCR);
186         tdmac->status = DMA_PAUSED;
187 }
188 
189 static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
190 {
191         unsigned int tdcr = 0;
192 
193         mmp_tdma_disable_chan(tdmac);
194 
195         if (tdmac->dir == DMA_MEM_TO_DEV)
196                 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
197         else if (tdmac->dir == DMA_DEV_TO_MEM)
198                 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
199 
200         if (tdmac->type == MMP_AUD_TDMA) {
201                 tdcr |= TDCR_PACKMOD;
202 
203                 switch (tdmac->burst_sz) {
204                 case 4:
205                         tdcr |= TDCR_BURSTSZ_4B;
206                         break;
207                 case 8:
208                         tdcr |= TDCR_BURSTSZ_8B;
209                         break;
210                 case 16:
211                         tdcr |= TDCR_BURSTSZ_16B;
212                         break;
213                 case 32:
214                         tdcr |= TDCR_BURSTSZ_32B;
215                         break;
216                 case 64:
217                         tdcr |= TDCR_BURSTSZ_64B;
218                         break;
219                 case 128:
220                         tdcr |= TDCR_BURSTSZ_128B;
221                         break;
222                 default:
223                         dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
224                         return -EINVAL;
225                 }
226 
227                 switch (tdmac->buswidth) {
228                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
229                         tdcr |= TDCR_SSZ_8_BITS;
230                         break;
231                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
232                         tdcr |= TDCR_SSZ_16_BITS;
233                         break;
234                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
235                         tdcr |= TDCR_SSZ_32_BITS;
236                         break;
237                 default:
238                         dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
239                         return -EINVAL;
240                 }
241         } else if (tdmac->type == PXA910_SQU) {
242                 tdcr |= TDCR_SSPMOD;
243 
244                 switch (tdmac->burst_sz) {
245                 case 1:
246                         tdcr |= TDCR_BURSTSZ_SQU_1B;
247                         break;
248                 case 2:
249                         tdcr |= TDCR_BURSTSZ_SQU_2B;
250                         break;
251                 case 4:
252                         tdcr |= TDCR_BURSTSZ_SQU_4B;
253                         break;
254                 case 8:
255                         tdcr |= TDCR_BURSTSZ_SQU_8B;
256                         break;
257                 case 16:
258                         tdcr |= TDCR_BURSTSZ_SQU_16B;
259                         break;
260                 case 32:
261                         tdcr |= TDCR_BURSTSZ_SQU_32B;
262                         break;
263                 default:
264                         dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
265                         return -EINVAL;
266                 }
267         }
268 
269         writel(tdcr, tdmac->reg_base + TDCR);
270         return 0;
271 }
272 
273 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
274 {
275         u32 reg = readl(tdmac->reg_base + TDISR);
276 
277         if (reg & TDISR_COMP) {
278                 /* clear irq */
279                 reg &= ~TDISR_COMP;
280                 writel(reg, tdmac->reg_base + TDISR);
281 
282                 return 0;
283         }
284         return -EAGAIN;
285 }
286 
287 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
288 {
289         struct mmp_tdma_chan *tdmac = dev_id;
290 
291         if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
292                 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
293                 tasklet_schedule(&tdmac->tasklet);
294                 return IRQ_HANDLED;
295         } else
296                 return IRQ_NONE;
297 }
298 
299 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
300 {
301         struct mmp_tdma_device *tdev = dev_id;
302         int i, ret;
303         int irq_num = 0;
304 
305         for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
306                 struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
307 
308                 ret = mmp_tdma_chan_handler(irq, tdmac);
309                 if (ret == IRQ_HANDLED)
310                         irq_num++;
311         }
312 
313         if (irq_num)
314                 return IRQ_HANDLED;
315         else
316                 return IRQ_NONE;
317 }
318 
319 static void dma_do_tasklet(unsigned long data)
320 {
321         struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
322 
323         if (tdmac->desc.callback)
324                 tdmac->desc.callback(tdmac->desc.callback_param);
325 
326 }
327 
328 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
329 {
330         struct gen_pool *gpool;
331         int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
332 
333         gpool = tdmac->pool;
334         if (tdmac->desc_arr)
335                 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
336                                 size);
337         tdmac->desc_arr = NULL;
338 
339         return;
340 }
341 
342 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
343 {
344         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
345 
346         mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
347 
348         return 0;
349 }
350 
351 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
352 {
353         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
354         int ret;
355 
356         dma_async_tx_descriptor_init(&tdmac->desc, chan);
357         tdmac->desc.tx_submit = mmp_tdma_tx_submit;
358 
359         if (tdmac->irq) {
360                 ret = devm_request_irq(tdmac->dev, tdmac->irq,
361                         mmp_tdma_chan_handler, 0, "tdma", tdmac);
362                 if (ret)
363                         return ret;
364         }
365         return 1;
366 }
367 
368 static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
369 {
370         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
371 
372         if (tdmac->irq)
373                 devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
374         mmp_tdma_free_descriptor(tdmac);
375         return;
376 }
377 
378 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
379 {
380         struct gen_pool *gpool;
381         int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
382 
383         gpool = tdmac->pool;
384         if (!gpool)
385                 return NULL;
386 
387         tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
388 
389         return tdmac->desc_arr;
390 }
391 
392 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
393                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
394                 size_t period_len, enum dma_transfer_direction direction,
395                 unsigned long flags)
396 {
397         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
398         struct mmp_tdma_desc *desc;
399         int num_periods = buf_len / period_len;
400         int i = 0, buf = 0;
401 
402         if (tdmac->status != DMA_COMPLETE)
403                 return NULL;
404 
405         if (period_len > TDMA_MAX_XFER_BYTES) {
406                 dev_err(tdmac->dev,
407                                 "maximum period size exceeded: %d > %d\n",
408                                 period_len, TDMA_MAX_XFER_BYTES);
409                 goto err_out;
410         }
411 
412         tdmac->status = DMA_IN_PROGRESS;
413         tdmac->desc_num = num_periods;
414         desc = mmp_tdma_alloc_descriptor(tdmac);
415         if (!desc)
416                 goto err_out;
417 
418         while (buf < buf_len) {
419                 desc = &tdmac->desc_arr[i];
420 
421                 if (i + 1 == num_periods)
422                         desc->nxt_desc = tdmac->desc_arr_phys;
423                 else
424                         desc->nxt_desc = tdmac->desc_arr_phys +
425                                 sizeof(*desc) * (i + 1);
426 
427                 if (direction == DMA_MEM_TO_DEV) {
428                         desc->src_addr = dma_addr;
429                         desc->dst_addr = tdmac->dev_addr;
430                 } else {
431                         desc->src_addr = tdmac->dev_addr;
432                         desc->dst_addr = dma_addr;
433                 }
434                 desc->byte_cnt = period_len;
435                 dma_addr += period_len;
436                 buf += period_len;
437                 i++;
438         }
439 
440         /* enable interrupt */
441         if (flags & DMA_PREP_INTERRUPT)
442                 mmp_tdma_enable_irq(tdmac, true);
443 
444         tdmac->buf_len = buf_len;
445         tdmac->period_len = period_len;
446         tdmac->pos = 0;
447 
448         return &tdmac->desc;
449 
450 err_out:
451         tdmac->status = DMA_ERROR;
452         return NULL;
453 }
454 
455 static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
456                 unsigned long arg)
457 {
458         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
459         struct dma_slave_config *dmaengine_cfg = (void *)arg;
460         int ret = 0;
461 
462         switch (cmd) {
463         case DMA_TERMINATE_ALL:
464                 mmp_tdma_disable_chan(tdmac);
465                 /* disable interrupt */
466                 mmp_tdma_enable_irq(tdmac, false);
467                 break;
468         case DMA_PAUSE:
469                 mmp_tdma_pause_chan(tdmac);
470                 break;
471         case DMA_RESUME:
472                 mmp_tdma_resume_chan(tdmac);
473                 break;
474         case DMA_SLAVE_CONFIG:
475                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
476                         tdmac->dev_addr = dmaengine_cfg->src_addr;
477                         tdmac->burst_sz = dmaengine_cfg->src_maxburst;
478                         tdmac->buswidth = dmaengine_cfg->src_addr_width;
479                 } else {
480                         tdmac->dev_addr = dmaengine_cfg->dst_addr;
481                         tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
482                         tdmac->buswidth = dmaengine_cfg->dst_addr_width;
483                 }
484                 tdmac->dir = dmaengine_cfg->direction;
485                 return mmp_tdma_config_chan(tdmac);
486         default:
487                 ret = -ENOSYS;
488         }
489 
490         return ret;
491 }
492 
493 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
494                         dma_cookie_t cookie, struct dma_tx_state *txstate)
495 {
496         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
497 
498         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
499                          tdmac->buf_len - tdmac->pos);
500 
501         return tdmac->status;
502 }
503 
504 static void mmp_tdma_issue_pending(struct dma_chan *chan)
505 {
506         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
507 
508         mmp_tdma_enable_chan(tdmac);
509 }
510 
511 static int mmp_tdma_remove(struct platform_device *pdev)
512 {
513         struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
514 
515         dma_async_device_unregister(&tdev->device);
516         return 0;
517 }
518 
519 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
520                                         int idx, int irq,
521                                         int type, struct gen_pool *pool)
522 {
523         struct mmp_tdma_chan *tdmac;
524 
525         if (idx >= TDMA_CHANNEL_NUM) {
526                 dev_err(tdev->dev, "too many channels for device!\n");
527                 return -EINVAL;
528         }
529 
530         /* alloc channel */
531         tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
532         if (!tdmac) {
533                 dev_err(tdev->dev, "no free memory for DMA channels!\n");
534                 return -ENOMEM;
535         }
536         if (irq)
537                 tdmac->irq = irq;
538         tdmac->dev         = tdev->dev;
539         tdmac->chan.device = &tdev->device;
540         tdmac->idx         = idx;
541         tdmac->type        = type;
542         tdmac->reg_base    = tdev->base + idx * 4;
543         tdmac->pool        = pool;
544         tdmac->status = DMA_COMPLETE;
545         tdev->tdmac[tdmac->idx] = tdmac;
546         tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
547 
548         /* add the channel to tdma_chan list */
549         list_add_tail(&tdmac->chan.device_node,
550                         &tdev->device.channels);
551         return 0;
552 }
553 
554 struct mmp_tdma_filter_param {
555         struct device_node *of_node;
556         unsigned int chan_id;
557 };
558 
559 static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
560 {
561         struct mmp_tdma_filter_param *param = fn_param;
562         struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
563         struct dma_device *pdma_device = tdmac->chan.device;
564 
565         if (pdma_device->dev->of_node != param->of_node)
566                 return false;
567 
568         if (chan->chan_id != param->chan_id)
569                 return false;
570 
571         return true;
572 }
573 
574 struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
575                                struct of_dma *ofdma)
576 {
577         struct mmp_tdma_device *tdev = ofdma->of_dma_data;
578         dma_cap_mask_t mask = tdev->device.cap_mask;
579         struct mmp_tdma_filter_param param;
580 
581         if (dma_spec->args_count != 1)
582                 return NULL;
583 
584         param.of_node = ofdma->of_node;
585         param.chan_id = dma_spec->args[0];
586 
587         if (param.chan_id >= TDMA_CHANNEL_NUM)
588                 return NULL;
589 
590         return dma_request_channel(mask, mmp_tdma_filter_fn, &param);
591 }
592 
593 static struct of_device_id mmp_tdma_dt_ids[] = {
594         { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
595         { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
596         {}
597 };
598 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
599 
600 static int mmp_tdma_probe(struct platform_device *pdev)
601 {
602         enum mmp_tdma_type type;
603         const struct of_device_id *of_id;
604         struct mmp_tdma_device *tdev;
605         struct resource *iores;
606         int i, ret;
607         int irq = 0, irq_num = 0;
608         int chan_num = TDMA_CHANNEL_NUM;
609         struct gen_pool *pool;
610 
611         of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
612         if (of_id)
613                 type = (enum mmp_tdma_type) of_id->data;
614         else
615                 type = platform_get_device_id(pdev)->driver_data;
616 
617         /* always have couple channels */
618         tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
619         if (!tdev)
620                 return -ENOMEM;
621 
622         tdev->dev = &pdev->dev;
623 
624         for (i = 0; i < chan_num; i++) {
625                 if (platform_get_irq(pdev, i) > 0)
626                         irq_num++;
627         }
628 
629         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
630         tdev->base = devm_ioremap_resource(&pdev->dev, iores);
631         if (IS_ERR(tdev->base))
632                 return PTR_ERR(tdev->base);
633 
634         INIT_LIST_HEAD(&tdev->device.channels);
635 
636         if (pdev->dev.of_node)
637                 pool = of_get_named_gen_pool(pdev->dev.of_node, "asram", 0);
638         else
639                 pool = sram_get_gpool("asram");
640         if (!pool) {
641                 dev_err(&pdev->dev, "asram pool not available\n");
642                 return -ENOMEM;
643         }
644 
645         if (irq_num != chan_num) {
646                 irq = platform_get_irq(pdev, 0);
647                 ret = devm_request_irq(&pdev->dev, irq,
648                         mmp_tdma_int_handler, 0, "tdma", tdev);
649                 if (ret)
650                         return ret;
651         }
652 
653         /* initialize channel parameters */
654         for (i = 0; i < chan_num; i++) {
655                 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
656                 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
657                 if (ret)
658                         return ret;
659         }
660 
661         dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
662         dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
663         tdev->device.dev = &pdev->dev;
664         tdev->device.device_alloc_chan_resources =
665                                         mmp_tdma_alloc_chan_resources;
666         tdev->device.device_free_chan_resources =
667                                         mmp_tdma_free_chan_resources;
668         tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
669         tdev->device.device_tx_status = mmp_tdma_tx_status;
670         tdev->device.device_issue_pending = mmp_tdma_issue_pending;
671         tdev->device.device_control = mmp_tdma_control;
672         tdev->device.copy_align = TDMA_ALIGNMENT;
673 
674         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
675         platform_set_drvdata(pdev, tdev);
676 
677         ret = dma_async_device_register(&tdev->device);
678         if (ret) {
679                 dev_err(tdev->device.dev, "unable to register\n");
680                 return ret;
681         }
682 
683         if (pdev->dev.of_node) {
684                 ret = of_dma_controller_register(pdev->dev.of_node,
685                                                         mmp_tdma_xlate, tdev);
686                 if (ret) {
687                         dev_err(tdev->device.dev,
688                                 "failed to register controller\n");
689                         dma_async_device_unregister(&tdev->device);
690                 }
691         }
692 
693         dev_info(tdev->device.dev, "initialized\n");
694         return 0;
695 }
696 
697 static const struct platform_device_id mmp_tdma_id_table[] = {
698         { "mmp-adma",   MMP_AUD_TDMA },
699         { "pxa910-squ", PXA910_SQU },
700         { },
701 };
702 
703 static struct platform_driver mmp_tdma_driver = {
704         .driver         = {
705                 .name   = "mmp-tdma",
706                 .owner  = THIS_MODULE,
707                 .of_match_table = mmp_tdma_dt_ids,
708         },
709         .id_table       = mmp_tdma_id_table,
710         .probe          = mmp_tdma_probe,
711         .remove         = mmp_tdma_remove,
712 };
713 
714 module_platform_driver(mmp_tdma_driver);
715 
716 MODULE_LICENSE("GPL");
717 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
718 MODULE_ALIAS("platform:mmp-tdma");
719 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
720 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
721 

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