Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/dma/imx-sdma.c

  1 /*
  2  * drivers/dma/imx-sdma.c
  3  *
  4  * This file contains a driver for the Freescale Smart DMA engine
  5  *
  6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  7  *
  8  * Based on code from Freescale:
  9  *
 10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 11  *
 12  * The code contained herein is licensed under the GNU General Public
 13  * License. You may obtain a copy of the GNU General Public License
 14  * Version 2 or later at the following locations:
 15  *
 16  * http://www.opensource.org/licenses/gpl-license.html
 17  * http://www.gnu.org/copyleft/gpl.html
 18  */
 19 
 20 #include <linux/init.h>
 21 #include <linux/module.h>
 22 #include <linux/types.h>
 23 #include <linux/bitops.h>
 24 #include <linux/mm.h>
 25 #include <linux/interrupt.h>
 26 #include <linux/clk.h>
 27 #include <linux/delay.h>
 28 #include <linux/sched.h>
 29 #include <linux/semaphore.h>
 30 #include <linux/spinlock.h>
 31 #include <linux/device.h>
 32 #include <linux/dma-mapping.h>
 33 #include <linux/firmware.h>
 34 #include <linux/slab.h>
 35 #include <linux/platform_device.h>
 36 #include <linux/dmaengine.h>
 37 #include <linux/of.h>
 38 #include <linux/of_device.h>
 39 #include <linux/of_dma.h>
 40 
 41 #include <asm/irq.h>
 42 #include <linux/platform_data/dma-imx-sdma.h>
 43 #include <linux/platform_data/dma-imx.h>
 44 
 45 #include "dmaengine.h"
 46 
 47 /* SDMA registers */
 48 #define SDMA_H_C0PTR            0x000
 49 #define SDMA_H_INTR             0x004
 50 #define SDMA_H_STATSTOP         0x008
 51 #define SDMA_H_START            0x00c
 52 #define SDMA_H_EVTOVR           0x010
 53 #define SDMA_H_DSPOVR           0x014
 54 #define SDMA_H_HOSTOVR          0x018
 55 #define SDMA_H_EVTPEND          0x01c
 56 #define SDMA_H_DSPENBL          0x020
 57 #define SDMA_H_RESET            0x024
 58 #define SDMA_H_EVTERR           0x028
 59 #define SDMA_H_INTRMSK          0x02c
 60 #define SDMA_H_PSW              0x030
 61 #define SDMA_H_EVTERRDBG        0x034
 62 #define SDMA_H_CONFIG           0x038
 63 #define SDMA_ONCE_ENB           0x040
 64 #define SDMA_ONCE_DATA          0x044
 65 #define SDMA_ONCE_INSTR         0x048
 66 #define SDMA_ONCE_STAT          0x04c
 67 #define SDMA_ONCE_CMD           0x050
 68 #define SDMA_EVT_MIRROR         0x054
 69 #define SDMA_ILLINSTADDR        0x058
 70 #define SDMA_CHN0ADDR           0x05c
 71 #define SDMA_ONCE_RTB           0x060
 72 #define SDMA_XTRIG_CONF1        0x070
 73 #define SDMA_XTRIG_CONF2        0x074
 74 #define SDMA_CHNENBL0_IMX35     0x200
 75 #define SDMA_CHNENBL0_IMX31     0x080
 76 #define SDMA_CHNPRI_0           0x100
 77 
 78 /*
 79  * Buffer descriptor status values.
 80  */
 81 #define BD_DONE  0x01
 82 #define BD_WRAP  0x02
 83 #define BD_CONT  0x04
 84 #define BD_INTR  0x08
 85 #define BD_RROR  0x10
 86 #define BD_LAST  0x20
 87 #define BD_EXTD  0x80
 88 
 89 /*
 90  * Data Node descriptor status values.
 91  */
 92 #define DND_END_OF_FRAME  0x80
 93 #define DND_END_OF_XFER   0x40
 94 #define DND_DONE          0x20
 95 #define DND_UNUSED        0x01
 96 
 97 /*
 98  * IPCV2 descriptor status values.
 99  */
100 #define BD_IPCV2_END_OF_FRAME  0x40
101 
102 #define IPCV2_MAX_NODES        50
103 /*
104  * Error bit set in the CCB status field by the SDMA,
105  * in setbd routine, in case of a transfer error
106  */
107 #define DATA_ERROR  0x10000000
108 
109 /*
110  * Buffer descriptor commands.
111  */
112 #define C0_ADDR             0x01
113 #define C0_LOAD             0x02
114 #define C0_DUMP             0x03
115 #define C0_SETCTX           0x07
116 #define C0_GETCTX           0x03
117 #define C0_SETDM            0x01
118 #define C0_SETPM            0x04
119 #define C0_GETDM            0x02
120 #define C0_GETPM            0x08
121 /*
122  * Change endianness indicator in the BD command field
123  */
124 #define CHANGE_ENDIANNESS   0x80
125 
126 /*
127  * Mode/Count of data node descriptors - IPCv2
128  */
129 struct sdma_mode_count {
130         u32 count   : 16; /* size of the buffer pointed by this BD */
131         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
132         u32 command :  8; /* command mostlky used for channel 0 */
133 };
134 
135 /*
136  * Buffer descriptor
137  */
138 struct sdma_buffer_descriptor {
139         struct sdma_mode_count  mode;
140         u32 buffer_addr;        /* address of the buffer described */
141         u32 ext_buffer_addr;    /* extended buffer address */
142 } __attribute__ ((packed));
143 
144 /**
145  * struct sdma_channel_control - Channel control Block
146  *
147  * @current_bd_ptr      current buffer descriptor processed
148  * @base_bd_ptr         first element of buffer descriptor array
149  * @unused              padding. The SDMA engine expects an array of 128 byte
150  *                      control blocks
151  */
152 struct sdma_channel_control {
153         u32 current_bd_ptr;
154         u32 base_bd_ptr;
155         u32 unused[2];
156 } __attribute__ ((packed));
157 
158 /**
159  * struct sdma_state_registers - SDMA context for a channel
160  *
161  * @pc:         program counter
162  * @t:          test bit: status of arithmetic & test instruction
163  * @rpc:        return program counter
164  * @sf:         source fault while loading data
165  * @spc:        loop start program counter
166  * @df:         destination fault while storing data
167  * @epc:        loop end program counter
168  * @lm:         loop mode
169  */
170 struct sdma_state_registers {
171         u32 pc     :14;
172         u32 unused1: 1;
173         u32 t      : 1;
174         u32 rpc    :14;
175         u32 unused0: 1;
176         u32 sf     : 1;
177         u32 spc    :14;
178         u32 unused2: 1;
179         u32 df     : 1;
180         u32 epc    :14;
181         u32 lm     : 2;
182 } __attribute__ ((packed));
183 
184 /**
185  * struct sdma_context_data - sdma context specific to a channel
186  *
187  * @channel_state:      channel state bits
188  * @gReg:               general registers
189  * @mda:                burst dma destination address register
190  * @msa:                burst dma source address register
191  * @ms:                 burst dma status register
192  * @md:                 burst dma data register
193  * @pda:                peripheral dma destination address register
194  * @psa:                peripheral dma source address register
195  * @ps:                 peripheral dma status register
196  * @pd:                 peripheral dma data register
197  * @ca:                 CRC polynomial register
198  * @cs:                 CRC accumulator register
199  * @dda:                dedicated core destination address register
200  * @dsa:                dedicated core source address register
201  * @ds:                 dedicated core status register
202  * @dd:                 dedicated core data register
203  */
204 struct sdma_context_data {
205         struct sdma_state_registers  channel_state;
206         u32  gReg[8];
207         u32  mda;
208         u32  msa;
209         u32  ms;
210         u32  md;
211         u32  pda;
212         u32  psa;
213         u32  ps;
214         u32  pd;
215         u32  ca;
216         u32  cs;
217         u32  dda;
218         u32  dsa;
219         u32  ds;
220         u32  dd;
221         u32  scratch0;
222         u32  scratch1;
223         u32  scratch2;
224         u32  scratch3;
225         u32  scratch4;
226         u32  scratch5;
227         u32  scratch6;
228         u32  scratch7;
229 } __attribute__ ((packed));
230 
231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
232 
233 struct sdma_engine;
234 
235 /**
236  * struct sdma_channel - housekeeping for a SDMA channel
237  *
238  * @sdma                pointer to the SDMA engine for this channel
239  * @channel             the channel number, matches dmaengine chan_id + 1
240  * @direction           transfer type. Needed for setting SDMA script
241  * @peripheral_type     Peripheral type. Needed for setting SDMA script
242  * @event_id0           aka dma request line
243  * @event_id1           for channels that use 2 events
244  * @word_size           peripheral access size
245  * @buf_tail            ID of the buffer that was processed
246  * @num_bd              max NUM_BD. number of descriptors currently handling
247  */
248 struct sdma_channel {
249         struct sdma_engine              *sdma;
250         unsigned int                    channel;
251         enum dma_transfer_direction             direction;
252         enum sdma_peripheral_type       peripheral_type;
253         unsigned int                    event_id0;
254         unsigned int                    event_id1;
255         enum dma_slave_buswidth         word_size;
256         unsigned int                    buf_tail;
257         unsigned int                    num_bd;
258         unsigned int                    period_len;
259         struct sdma_buffer_descriptor   *bd;
260         dma_addr_t                      bd_phys;
261         unsigned int                    pc_from_device, pc_to_device;
262         unsigned long                   flags;
263         dma_addr_t                      per_address;
264         unsigned long                   event_mask[2];
265         unsigned long                   watermark_level;
266         u32                             shp_addr, per_addr;
267         struct dma_chan                 chan;
268         spinlock_t                      lock;
269         struct dma_async_tx_descriptor  desc;
270         enum dma_status                 status;
271         unsigned int                    chn_count;
272         unsigned int                    chn_real_count;
273         struct tasklet_struct           tasklet;
274 };
275 
276 #define IMX_DMA_SG_LOOP         BIT(0)
277 
278 #define MAX_DMA_CHANNELS 32
279 #define MXC_SDMA_DEFAULT_PRIORITY 1
280 #define MXC_SDMA_MIN_PRIORITY 1
281 #define MXC_SDMA_MAX_PRIORITY 7
282 
283 #define SDMA_FIRMWARE_MAGIC 0x414d4453
284 
285 /**
286  * struct sdma_firmware_header - Layout of the firmware image
287  *
288  * @magic               "SDMA"
289  * @version_major       increased whenever layout of struct sdma_script_start_addrs
290  *                      changes.
291  * @version_minor       firmware minor version (for binary compatible changes)
292  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
293  * @num_script_addrs    Number of script addresses in this image
294  * @ram_code_start      offset of SDMA ram image in this firmware image
295  * @ram_code_size       size of SDMA ram image
296  * @script_addrs        Stores the start address of the SDMA scripts
297  *                      (in SDMA memory space)
298  */
299 struct sdma_firmware_header {
300         u32     magic;
301         u32     version_major;
302         u32     version_minor;
303         u32     script_addrs_start;
304         u32     num_script_addrs;
305         u32     ram_code_start;
306         u32     ram_code_size;
307 };
308 
309 struct sdma_driver_data {
310         int chnenbl0;
311         int num_events;
312         struct sdma_script_start_addrs  *script_addrs;
313 };
314 
315 struct sdma_engine {
316         struct device                   *dev;
317         struct device_dma_parameters    dma_parms;
318         struct sdma_channel             channel[MAX_DMA_CHANNELS];
319         struct sdma_channel_control     *channel_control;
320         void __iomem                    *regs;
321         struct sdma_context_data        *context;
322         dma_addr_t                      context_phys;
323         struct dma_device               dma_device;
324         struct clk                      *clk_ipg;
325         struct clk                      *clk_ahb;
326         spinlock_t                      channel_0_lock;
327         u32                             script_number;
328         struct sdma_script_start_addrs  *script_addrs;
329         const struct sdma_driver_data   *drvdata;
330 };
331 
332 static struct sdma_driver_data sdma_imx31 = {
333         .chnenbl0 = SDMA_CHNENBL0_IMX31,
334         .num_events = 32,
335 };
336 
337 static struct sdma_script_start_addrs sdma_script_imx25 = {
338         .ap_2_ap_addr = 729,
339         .uart_2_mcu_addr = 904,
340         .per_2_app_addr = 1255,
341         .mcu_2_app_addr = 834,
342         .uartsh_2_mcu_addr = 1120,
343         .per_2_shp_addr = 1329,
344         .mcu_2_shp_addr = 1048,
345         .ata_2_mcu_addr = 1560,
346         .mcu_2_ata_addr = 1479,
347         .app_2_per_addr = 1189,
348         .app_2_mcu_addr = 770,
349         .shp_2_per_addr = 1407,
350         .shp_2_mcu_addr = 979,
351 };
352 
353 static struct sdma_driver_data sdma_imx25 = {
354         .chnenbl0 = SDMA_CHNENBL0_IMX35,
355         .num_events = 48,
356         .script_addrs = &sdma_script_imx25,
357 };
358 
359 static struct sdma_driver_data sdma_imx35 = {
360         .chnenbl0 = SDMA_CHNENBL0_IMX35,
361         .num_events = 48,
362 };
363 
364 static struct sdma_script_start_addrs sdma_script_imx51 = {
365         .ap_2_ap_addr = 642,
366         .uart_2_mcu_addr = 817,
367         .mcu_2_app_addr = 747,
368         .mcu_2_shp_addr = 961,
369         .ata_2_mcu_addr = 1473,
370         .mcu_2_ata_addr = 1392,
371         .app_2_per_addr = 1033,
372         .app_2_mcu_addr = 683,
373         .shp_2_per_addr = 1251,
374         .shp_2_mcu_addr = 892,
375 };
376 
377 static struct sdma_driver_data sdma_imx51 = {
378         .chnenbl0 = SDMA_CHNENBL0_IMX35,
379         .num_events = 48,
380         .script_addrs = &sdma_script_imx51,
381 };
382 
383 static struct sdma_script_start_addrs sdma_script_imx53 = {
384         .ap_2_ap_addr = 642,
385         .app_2_mcu_addr = 683,
386         .mcu_2_app_addr = 747,
387         .uart_2_mcu_addr = 817,
388         .shp_2_mcu_addr = 891,
389         .mcu_2_shp_addr = 960,
390         .uartsh_2_mcu_addr = 1032,
391         .spdif_2_mcu_addr = 1100,
392         .mcu_2_spdif_addr = 1134,
393         .firi_2_mcu_addr = 1193,
394         .mcu_2_firi_addr = 1290,
395 };
396 
397 static struct sdma_driver_data sdma_imx53 = {
398         .chnenbl0 = SDMA_CHNENBL0_IMX35,
399         .num_events = 48,
400         .script_addrs = &sdma_script_imx53,
401 };
402 
403 static struct sdma_script_start_addrs sdma_script_imx6q = {
404         .ap_2_ap_addr = 642,
405         .uart_2_mcu_addr = 817,
406         .mcu_2_app_addr = 747,
407         .per_2_per_addr = 6331,
408         .uartsh_2_mcu_addr = 1032,
409         .mcu_2_shp_addr = 960,
410         .app_2_mcu_addr = 683,
411         .shp_2_mcu_addr = 891,
412         .spdif_2_mcu_addr = 1100,
413         .mcu_2_spdif_addr = 1134,
414 };
415 
416 static struct sdma_driver_data sdma_imx6q = {
417         .chnenbl0 = SDMA_CHNENBL0_IMX35,
418         .num_events = 48,
419         .script_addrs = &sdma_script_imx6q,
420 };
421 
422 static struct platform_device_id sdma_devtypes[] = {
423         {
424                 .name = "imx25-sdma",
425                 .driver_data = (unsigned long)&sdma_imx25,
426         }, {
427                 .name = "imx31-sdma",
428                 .driver_data = (unsigned long)&sdma_imx31,
429         }, {
430                 .name = "imx35-sdma",
431                 .driver_data = (unsigned long)&sdma_imx35,
432         }, {
433                 .name = "imx51-sdma",
434                 .driver_data = (unsigned long)&sdma_imx51,
435         }, {
436                 .name = "imx53-sdma",
437                 .driver_data = (unsigned long)&sdma_imx53,
438         }, {
439                 .name = "imx6q-sdma",
440                 .driver_data = (unsigned long)&sdma_imx6q,
441         }, {
442                 /* sentinel */
443         }
444 };
445 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
446 
447 static const struct of_device_id sdma_dt_ids[] = {
448         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
449         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
450         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
451         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
452         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
453         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
454         { /* sentinel */ }
455 };
456 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
457 
458 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
459 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
460 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
461 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
462 
463 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
464 {
465         u32 chnenbl0 = sdma->drvdata->chnenbl0;
466         return chnenbl0 + event * 4;
467 }
468 
469 static int sdma_config_ownership(struct sdma_channel *sdmac,
470                 bool event_override, bool mcu_override, bool dsp_override)
471 {
472         struct sdma_engine *sdma = sdmac->sdma;
473         int channel = sdmac->channel;
474         unsigned long evt, mcu, dsp;
475 
476         if (event_override && mcu_override && dsp_override)
477                 return -EINVAL;
478 
479         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
480         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
481         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
482 
483         if (dsp_override)
484                 __clear_bit(channel, &dsp);
485         else
486                 __set_bit(channel, &dsp);
487 
488         if (event_override)
489                 __clear_bit(channel, &evt);
490         else
491                 __set_bit(channel, &evt);
492 
493         if (mcu_override)
494                 __clear_bit(channel, &mcu);
495         else
496                 __set_bit(channel, &mcu);
497 
498         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
499         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
500         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
501 
502         return 0;
503 }
504 
505 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
506 {
507         writel(BIT(channel), sdma->regs + SDMA_H_START);
508 }
509 
510 /*
511  * sdma_run_channel0 - run a channel and wait till it's done
512  */
513 static int sdma_run_channel0(struct sdma_engine *sdma)
514 {
515         int ret;
516         unsigned long timeout = 500;
517 
518         sdma_enable_channel(sdma, 0);
519 
520         while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
521                 if (timeout-- <= 0)
522                         break;
523                 udelay(1);
524         }
525 
526         if (ret) {
527                 /* Clear the interrupt status */
528                 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
529         } else {
530                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
531         }
532 
533         return ret ? 0 : -ETIMEDOUT;
534 }
535 
536 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
537                 u32 address)
538 {
539         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
540         void *buf_virt;
541         dma_addr_t buf_phys;
542         int ret;
543         unsigned long flags;
544 
545         buf_virt = dma_alloc_coherent(NULL,
546                         size,
547                         &buf_phys, GFP_KERNEL);
548         if (!buf_virt) {
549                 return -ENOMEM;
550         }
551 
552         spin_lock_irqsave(&sdma->channel_0_lock, flags);
553 
554         bd0->mode.command = C0_SETPM;
555         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
556         bd0->mode.count = size / 2;
557         bd0->buffer_addr = buf_phys;
558         bd0->ext_buffer_addr = address;
559 
560         memcpy(buf_virt, buf, size);
561 
562         ret = sdma_run_channel0(sdma);
563 
564         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
565 
566         dma_free_coherent(NULL, size, buf_virt, buf_phys);
567 
568         return ret;
569 }
570 
571 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
572 {
573         struct sdma_engine *sdma = sdmac->sdma;
574         int channel = sdmac->channel;
575         unsigned long val;
576         u32 chnenbl = chnenbl_ofs(sdma, event);
577 
578         val = readl_relaxed(sdma->regs + chnenbl);
579         __set_bit(channel, &val);
580         writel_relaxed(val, sdma->regs + chnenbl);
581 }
582 
583 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
584 {
585         struct sdma_engine *sdma = sdmac->sdma;
586         int channel = sdmac->channel;
587         u32 chnenbl = chnenbl_ofs(sdma, event);
588         unsigned long val;
589 
590         val = readl_relaxed(sdma->regs + chnenbl);
591         __clear_bit(channel, &val);
592         writel_relaxed(val, sdma->regs + chnenbl);
593 }
594 
595 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
596 {
597         if (sdmac->desc.callback)
598                 sdmac->desc.callback(sdmac->desc.callback_param);
599 }
600 
601 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
602 {
603         struct sdma_buffer_descriptor *bd;
604 
605         /*
606          * loop mode. Iterate over descriptors, re-setup them and
607          * call callback function.
608          */
609         while (1) {
610                 bd = &sdmac->bd[sdmac->buf_tail];
611 
612                 if (bd->mode.status & BD_DONE)
613                         break;
614 
615                 if (bd->mode.status & BD_RROR)
616                         sdmac->status = DMA_ERROR;
617 
618                 bd->mode.status |= BD_DONE;
619                 sdmac->buf_tail++;
620                 sdmac->buf_tail %= sdmac->num_bd;
621         }
622 }
623 
624 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
625 {
626         struct sdma_buffer_descriptor *bd;
627         int i, error = 0;
628 
629         sdmac->chn_real_count = 0;
630         /*
631          * non loop mode. Iterate over all descriptors, collect
632          * errors and call callback function
633          */
634         for (i = 0; i < sdmac->num_bd; i++) {
635                 bd = &sdmac->bd[i];
636 
637                  if (bd->mode.status & (BD_DONE | BD_RROR))
638                         error = -EIO;
639                  sdmac->chn_real_count += bd->mode.count;
640         }
641 
642         if (error)
643                 sdmac->status = DMA_ERROR;
644         else
645                 sdmac->status = DMA_COMPLETE;
646 
647         dma_cookie_complete(&sdmac->desc);
648         if (sdmac->desc.callback)
649                 sdmac->desc.callback(sdmac->desc.callback_param);
650 }
651 
652 static void sdma_tasklet(unsigned long data)
653 {
654         struct sdma_channel *sdmac = (struct sdma_channel *) data;
655 
656         if (sdmac->flags & IMX_DMA_SG_LOOP)
657                 sdma_handle_channel_loop(sdmac);
658         else
659                 mxc_sdma_handle_channel_normal(sdmac);
660 }
661 
662 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
663 {
664         struct sdma_engine *sdma = dev_id;
665         unsigned long stat;
666 
667         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
668         /* not interested in channel 0 interrupts */
669         stat &= ~1;
670         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
671 
672         while (stat) {
673                 int channel = fls(stat) - 1;
674                 struct sdma_channel *sdmac = &sdma->channel[channel];
675 
676                 if (sdmac->flags & IMX_DMA_SG_LOOP)
677                         sdma_update_channel_loop(sdmac);
678 
679                 tasklet_schedule(&sdmac->tasklet);
680 
681                 __clear_bit(channel, &stat);
682         }
683 
684         return IRQ_HANDLED;
685 }
686 
687 /*
688  * sets the pc of SDMA script according to the peripheral type
689  */
690 static void sdma_get_pc(struct sdma_channel *sdmac,
691                 enum sdma_peripheral_type peripheral_type)
692 {
693         struct sdma_engine *sdma = sdmac->sdma;
694         int per_2_emi = 0, emi_2_per = 0;
695         /*
696          * These are needed once we start to support transfers between
697          * two peripherals or memory-to-memory transfers
698          */
699         int per_2_per = 0, emi_2_emi = 0;
700 
701         sdmac->pc_from_device = 0;
702         sdmac->pc_to_device = 0;
703 
704         switch (peripheral_type) {
705         case IMX_DMATYPE_MEMORY:
706                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
707                 break;
708         case IMX_DMATYPE_DSP:
709                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
710                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
711                 break;
712         case IMX_DMATYPE_FIRI:
713                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
714                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
715                 break;
716         case IMX_DMATYPE_UART:
717                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
718                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
719                 break;
720         case IMX_DMATYPE_UART_SP:
721                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
722                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
723                 break;
724         case IMX_DMATYPE_ATA:
725                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
726                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
727                 break;
728         case IMX_DMATYPE_CSPI:
729         case IMX_DMATYPE_EXT:
730         case IMX_DMATYPE_SSI:
731                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
732                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
733                 break;
734         case IMX_DMATYPE_SSI_DUAL:
735                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
736                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
737                 break;
738         case IMX_DMATYPE_SSI_SP:
739         case IMX_DMATYPE_MMC:
740         case IMX_DMATYPE_SDHC:
741         case IMX_DMATYPE_CSPI_SP:
742         case IMX_DMATYPE_ESAI:
743         case IMX_DMATYPE_MSHC_SP:
744                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
745                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
746                 break;
747         case IMX_DMATYPE_ASRC:
748                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
749                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
750                 per_2_per = sdma->script_addrs->per_2_per_addr;
751                 break;
752         case IMX_DMATYPE_MSHC:
753                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
754                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
755                 break;
756         case IMX_DMATYPE_CCM:
757                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
758                 break;
759         case IMX_DMATYPE_SPDIF:
760                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
761                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
762                 break;
763         case IMX_DMATYPE_IPU_MEMORY:
764                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
765                 break;
766         default:
767                 break;
768         }
769 
770         sdmac->pc_from_device = per_2_emi;
771         sdmac->pc_to_device = emi_2_per;
772 }
773 
774 static int sdma_load_context(struct sdma_channel *sdmac)
775 {
776         struct sdma_engine *sdma = sdmac->sdma;
777         int channel = sdmac->channel;
778         int load_address;
779         struct sdma_context_data *context = sdma->context;
780         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
781         int ret;
782         unsigned long flags;
783 
784         if (sdmac->direction == DMA_DEV_TO_MEM) {
785                 load_address = sdmac->pc_from_device;
786         } else {
787                 load_address = sdmac->pc_to_device;
788         }
789 
790         if (load_address < 0)
791                 return load_address;
792 
793         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
794         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
795         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
796         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
797         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
798         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
799 
800         spin_lock_irqsave(&sdma->channel_0_lock, flags);
801 
802         memset(context, 0, sizeof(*context));
803         context->channel_state.pc = load_address;
804 
805         /* Send by context the event mask,base address for peripheral
806          * and watermark level
807          */
808         context->gReg[0] = sdmac->event_mask[1];
809         context->gReg[1] = sdmac->event_mask[0];
810         context->gReg[2] = sdmac->per_addr;
811         context->gReg[6] = sdmac->shp_addr;
812         context->gReg[7] = sdmac->watermark_level;
813 
814         bd0->mode.command = C0_SETDM;
815         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
816         bd0->mode.count = sizeof(*context) / 4;
817         bd0->buffer_addr = sdma->context_phys;
818         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
819         ret = sdma_run_channel0(sdma);
820 
821         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
822 
823         return ret;
824 }
825 
826 static void sdma_disable_channel(struct sdma_channel *sdmac)
827 {
828         struct sdma_engine *sdma = sdmac->sdma;
829         int channel = sdmac->channel;
830 
831         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
832         sdmac->status = DMA_ERROR;
833 }
834 
835 static int sdma_config_channel(struct sdma_channel *sdmac)
836 {
837         int ret;
838 
839         sdma_disable_channel(sdmac);
840 
841         sdmac->event_mask[0] = 0;
842         sdmac->event_mask[1] = 0;
843         sdmac->shp_addr = 0;
844         sdmac->per_addr = 0;
845 
846         if (sdmac->event_id0) {
847                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
848                         return -EINVAL;
849                 sdma_event_enable(sdmac, sdmac->event_id0);
850         }
851 
852         switch (sdmac->peripheral_type) {
853         case IMX_DMATYPE_DSP:
854                 sdma_config_ownership(sdmac, false, true, true);
855                 break;
856         case IMX_DMATYPE_MEMORY:
857                 sdma_config_ownership(sdmac, false, true, false);
858                 break;
859         default:
860                 sdma_config_ownership(sdmac, true, true, false);
861                 break;
862         }
863 
864         sdma_get_pc(sdmac, sdmac->peripheral_type);
865 
866         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
867                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
868                 /* Handle multiple event channels differently */
869                 if (sdmac->event_id1) {
870                         sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
871                         if (sdmac->event_id1 > 31)
872                                 __set_bit(31, &sdmac->watermark_level);
873                         sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
874                         if (sdmac->event_id0 > 31)
875                                 __set_bit(30, &sdmac->watermark_level);
876                 } else {
877                         __set_bit(sdmac->event_id0, sdmac->event_mask);
878                 }
879                 /* Watermark Level */
880                 sdmac->watermark_level |= sdmac->watermark_level;
881                 /* Address */
882                 sdmac->shp_addr = sdmac->per_address;
883         } else {
884                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
885         }
886 
887         ret = sdma_load_context(sdmac);
888 
889         return ret;
890 }
891 
892 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
893                 unsigned int priority)
894 {
895         struct sdma_engine *sdma = sdmac->sdma;
896         int channel = sdmac->channel;
897 
898         if (priority < MXC_SDMA_MIN_PRIORITY
899             || priority > MXC_SDMA_MAX_PRIORITY) {
900                 return -EINVAL;
901         }
902 
903         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
904 
905         return 0;
906 }
907 
908 static int sdma_request_channel(struct sdma_channel *sdmac)
909 {
910         struct sdma_engine *sdma = sdmac->sdma;
911         int channel = sdmac->channel;
912         int ret = -EBUSY;
913 
914         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
915         if (!sdmac->bd) {
916                 ret = -ENOMEM;
917                 goto out;
918         }
919 
920         memset(sdmac->bd, 0, PAGE_SIZE);
921 
922         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
923         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
924 
925         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
926         return 0;
927 out:
928 
929         return ret;
930 }
931 
932 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
933 {
934         return container_of(chan, struct sdma_channel, chan);
935 }
936 
937 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
938 {
939         unsigned long flags;
940         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
941         dma_cookie_t cookie;
942 
943         spin_lock_irqsave(&sdmac->lock, flags);
944 
945         cookie = dma_cookie_assign(tx);
946 
947         spin_unlock_irqrestore(&sdmac->lock, flags);
948 
949         return cookie;
950 }
951 
952 static int sdma_alloc_chan_resources(struct dma_chan *chan)
953 {
954         struct sdma_channel *sdmac = to_sdma_chan(chan);
955         struct imx_dma_data *data = chan->private;
956         int prio, ret;
957 
958         if (!data)
959                 return -EINVAL;
960 
961         switch (data->priority) {
962         case DMA_PRIO_HIGH:
963                 prio = 3;
964                 break;
965         case DMA_PRIO_MEDIUM:
966                 prio = 2;
967                 break;
968         case DMA_PRIO_LOW:
969         default:
970                 prio = 1;
971                 break;
972         }
973 
974         sdmac->peripheral_type = data->peripheral_type;
975         sdmac->event_id0 = data->dma_request;
976 
977         clk_enable(sdmac->sdma->clk_ipg);
978         clk_enable(sdmac->sdma->clk_ahb);
979 
980         ret = sdma_request_channel(sdmac);
981         if (ret)
982                 return ret;
983 
984         ret = sdma_set_channel_priority(sdmac, prio);
985         if (ret)
986                 return ret;
987 
988         dma_async_tx_descriptor_init(&sdmac->desc, chan);
989         sdmac->desc.tx_submit = sdma_tx_submit;
990         /* txd.flags will be overwritten in prep funcs */
991         sdmac->desc.flags = DMA_CTRL_ACK;
992 
993         return 0;
994 }
995 
996 static void sdma_free_chan_resources(struct dma_chan *chan)
997 {
998         struct sdma_channel *sdmac = to_sdma_chan(chan);
999         struct sdma_engine *sdma = sdmac->sdma;
1000 
1001         sdma_disable_channel(sdmac);
1002 
1003         if (sdmac->event_id0)
1004                 sdma_event_disable(sdmac, sdmac->event_id0);
1005         if (sdmac->event_id1)
1006                 sdma_event_disable(sdmac, sdmac->event_id1);
1007 
1008         sdmac->event_id0 = 0;
1009         sdmac->event_id1 = 0;
1010 
1011         sdma_set_channel_priority(sdmac, 0);
1012 
1013         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1014 
1015         clk_disable(sdma->clk_ipg);
1016         clk_disable(sdma->clk_ahb);
1017 }
1018 
1019 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1020                 struct dma_chan *chan, struct scatterlist *sgl,
1021                 unsigned int sg_len, enum dma_transfer_direction direction,
1022                 unsigned long flags, void *context)
1023 {
1024         struct sdma_channel *sdmac = to_sdma_chan(chan);
1025         struct sdma_engine *sdma = sdmac->sdma;
1026         int ret, i, count;
1027         int channel = sdmac->channel;
1028         struct scatterlist *sg;
1029 
1030         if (sdmac->status == DMA_IN_PROGRESS)
1031                 return NULL;
1032         sdmac->status = DMA_IN_PROGRESS;
1033 
1034         sdmac->flags = 0;
1035 
1036         sdmac->buf_tail = 0;
1037 
1038         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1039                         sg_len, channel);
1040 
1041         sdmac->direction = direction;
1042         ret = sdma_load_context(sdmac);
1043         if (ret)
1044                 goto err_out;
1045 
1046         if (sg_len > NUM_BD) {
1047                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1048                                 channel, sg_len, NUM_BD);
1049                 ret = -EINVAL;
1050                 goto err_out;
1051         }
1052 
1053         sdmac->chn_count = 0;
1054         for_each_sg(sgl, sg, sg_len, i) {
1055                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1056                 int param;
1057 
1058                 bd->buffer_addr = sg->dma_address;
1059 
1060                 count = sg_dma_len(sg);
1061 
1062                 if (count > 0xffff) {
1063                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1064                                         channel, count, 0xffff);
1065                         ret = -EINVAL;
1066                         goto err_out;
1067                 }
1068 
1069                 bd->mode.count = count;
1070                 sdmac->chn_count += count;
1071 
1072                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1073                         ret =  -EINVAL;
1074                         goto err_out;
1075                 }
1076 
1077                 switch (sdmac->word_size) {
1078                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1079                         bd->mode.command = 0;
1080                         if (count & 3 || sg->dma_address & 3)
1081                                 return NULL;
1082                         break;
1083                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1084                         bd->mode.command = 2;
1085                         if (count & 1 || sg->dma_address & 1)
1086                                 return NULL;
1087                         break;
1088                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1089                         bd->mode.command = 1;
1090                         break;
1091                 default:
1092                         return NULL;
1093                 }
1094 
1095                 param = BD_DONE | BD_EXTD | BD_CONT;
1096 
1097                 if (i + 1 == sg_len) {
1098                         param |= BD_INTR;
1099                         param |= BD_LAST;
1100                         param &= ~BD_CONT;
1101                 }
1102 
1103                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1104                                 i, count, (u64)sg->dma_address,
1105                                 param & BD_WRAP ? "wrap" : "",
1106                                 param & BD_INTR ? " intr" : "");
1107 
1108                 bd->mode.status = param;
1109         }
1110 
1111         sdmac->num_bd = sg_len;
1112         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1113 
1114         return &sdmac->desc;
1115 err_out:
1116         sdmac->status = DMA_ERROR;
1117         return NULL;
1118 }
1119 
1120 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1121                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1122                 size_t period_len, enum dma_transfer_direction direction,
1123                 unsigned long flags, void *context)
1124 {
1125         struct sdma_channel *sdmac = to_sdma_chan(chan);
1126         struct sdma_engine *sdma = sdmac->sdma;
1127         int num_periods = buf_len / period_len;
1128         int channel = sdmac->channel;
1129         int ret, i = 0, buf = 0;
1130 
1131         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1132 
1133         if (sdmac->status == DMA_IN_PROGRESS)
1134                 return NULL;
1135 
1136         sdmac->status = DMA_IN_PROGRESS;
1137 
1138         sdmac->buf_tail = 0;
1139         sdmac->period_len = period_len;
1140 
1141         sdmac->flags |= IMX_DMA_SG_LOOP;
1142         sdmac->direction = direction;
1143         ret = sdma_load_context(sdmac);
1144         if (ret)
1145                 goto err_out;
1146 
1147         if (num_periods > NUM_BD) {
1148                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1149                                 channel, num_periods, NUM_BD);
1150                 goto err_out;
1151         }
1152 
1153         if (period_len > 0xffff) {
1154                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1155                                 channel, period_len, 0xffff);
1156                 goto err_out;
1157         }
1158 
1159         while (buf < buf_len) {
1160                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1161                 int param;
1162 
1163                 bd->buffer_addr = dma_addr;
1164 
1165                 bd->mode.count = period_len;
1166 
1167                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1168                         goto err_out;
1169                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1170                         bd->mode.command = 0;
1171                 else
1172                         bd->mode.command = sdmac->word_size;
1173 
1174                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1175                 if (i + 1 == num_periods)
1176                         param |= BD_WRAP;
1177 
1178                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1179                                 i, period_len, (u64)dma_addr,
1180                                 param & BD_WRAP ? "wrap" : "",
1181                                 param & BD_INTR ? " intr" : "");
1182 
1183                 bd->mode.status = param;
1184 
1185                 dma_addr += period_len;
1186                 buf += period_len;
1187 
1188                 i++;
1189         }
1190 
1191         sdmac->num_bd = num_periods;
1192         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1193 
1194         return &sdmac->desc;
1195 err_out:
1196         sdmac->status = DMA_ERROR;
1197         return NULL;
1198 }
1199 
1200 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1201                 unsigned long arg)
1202 {
1203         struct sdma_channel *sdmac = to_sdma_chan(chan);
1204         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1205 
1206         switch (cmd) {
1207         case DMA_TERMINATE_ALL:
1208                 sdma_disable_channel(sdmac);
1209                 return 0;
1210         case DMA_SLAVE_CONFIG:
1211                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1212                         sdmac->per_address = dmaengine_cfg->src_addr;
1213                         sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1214                                                 dmaengine_cfg->src_addr_width;
1215                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1216                 } else {
1217                         sdmac->per_address = dmaengine_cfg->dst_addr;
1218                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1219                                                 dmaengine_cfg->dst_addr_width;
1220                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1221                 }
1222                 sdmac->direction = dmaengine_cfg->direction;
1223                 return sdma_config_channel(sdmac);
1224         default:
1225                 return -ENOSYS;
1226         }
1227 
1228         return -EINVAL;
1229 }
1230 
1231 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1232                                       dma_cookie_t cookie,
1233                                       struct dma_tx_state *txstate)
1234 {
1235         struct sdma_channel *sdmac = to_sdma_chan(chan);
1236         u32 residue;
1237 
1238         if (sdmac->flags & IMX_DMA_SG_LOOP)
1239                 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1240         else
1241                 residue = sdmac->chn_count - sdmac->chn_real_count;
1242 
1243         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1244                          residue);
1245 
1246         return sdmac->status;
1247 }
1248 
1249 static void sdma_issue_pending(struct dma_chan *chan)
1250 {
1251         struct sdma_channel *sdmac = to_sdma_chan(chan);
1252         struct sdma_engine *sdma = sdmac->sdma;
1253 
1254         if (sdmac->status == DMA_IN_PROGRESS)
1255                 sdma_enable_channel(sdma, sdmac->channel);
1256 }
1257 
1258 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1259 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1260 
1261 static void sdma_add_scripts(struct sdma_engine *sdma,
1262                 const struct sdma_script_start_addrs *addr)
1263 {
1264         s32 *addr_arr = (u32 *)addr;
1265         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1266         int i;
1267 
1268         /* use the default firmware in ROM if missing external firmware */
1269         if (!sdma->script_number)
1270                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1271 
1272         for (i = 0; i < sdma->script_number; i++)
1273                 if (addr_arr[i] > 0)
1274                         saddr_arr[i] = addr_arr[i];
1275 }
1276 
1277 static void sdma_load_firmware(const struct firmware *fw, void *context)
1278 {
1279         struct sdma_engine *sdma = context;
1280         const struct sdma_firmware_header *header;
1281         const struct sdma_script_start_addrs *addr;
1282         unsigned short *ram_code;
1283 
1284         if (!fw) {
1285                 dev_err(sdma->dev, "firmware not found\n");
1286                 return;
1287         }
1288 
1289         if (fw->size < sizeof(*header))
1290                 goto err_firmware;
1291 
1292         header = (struct sdma_firmware_header *)fw->data;
1293 
1294         if (header->magic != SDMA_FIRMWARE_MAGIC)
1295                 goto err_firmware;
1296         if (header->ram_code_start + header->ram_code_size > fw->size)
1297                 goto err_firmware;
1298         switch (header->version_major) {
1299                 case 1:
1300                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1301                         break;
1302                 case 2:
1303                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1304                         break;
1305                 default:
1306                         dev_err(sdma->dev, "unknown firmware version\n");
1307                         goto err_firmware;
1308         }
1309 
1310         addr = (void *)header + header->script_addrs_start;
1311         ram_code = (void *)header + header->ram_code_start;
1312 
1313         clk_enable(sdma->clk_ipg);
1314         clk_enable(sdma->clk_ahb);
1315         /* download the RAM image for SDMA */
1316         sdma_load_script(sdma, ram_code,
1317                         header->ram_code_size,
1318                         addr->ram_code_start_addr);
1319         clk_disable(sdma->clk_ipg);
1320         clk_disable(sdma->clk_ahb);
1321 
1322         sdma_add_scripts(sdma, addr);
1323 
1324         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1325                         header->version_major,
1326                         header->version_minor);
1327 
1328 err_firmware:
1329         release_firmware(fw);
1330 }
1331 
1332 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1333                 const char *fw_name)
1334 {
1335         int ret;
1336 
1337         ret = request_firmware_nowait(THIS_MODULE,
1338                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1339                         GFP_KERNEL, sdma, sdma_load_firmware);
1340 
1341         return ret;
1342 }
1343 
1344 static int __init sdma_init(struct sdma_engine *sdma)
1345 {
1346         int i, ret;
1347         dma_addr_t ccb_phys;
1348 
1349         clk_enable(sdma->clk_ipg);
1350         clk_enable(sdma->clk_ahb);
1351 
1352         /* Be sure SDMA has not started yet */
1353         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1354 
1355         sdma->channel_control = dma_alloc_coherent(NULL,
1356                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1357                         sizeof(struct sdma_context_data),
1358                         &ccb_phys, GFP_KERNEL);
1359 
1360         if (!sdma->channel_control) {
1361                 ret = -ENOMEM;
1362                 goto err_dma_alloc;
1363         }
1364 
1365         sdma->context = (void *)sdma->channel_control +
1366                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1367         sdma->context_phys = ccb_phys +
1368                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1369 
1370         /* Zero-out the CCB structures array just allocated */
1371         memset(sdma->channel_control, 0,
1372                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1373 
1374         /* disable all channels */
1375         for (i = 0; i < sdma->drvdata->num_events; i++)
1376                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1377 
1378         /* All channels have priority 0 */
1379         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1380                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1381 
1382         ret = sdma_request_channel(&sdma->channel[0]);
1383         if (ret)
1384                 goto err_dma_alloc;
1385 
1386         sdma_config_ownership(&sdma->channel[0], false, true, false);
1387 
1388         /* Set Command Channel (Channel Zero) */
1389         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1390 
1391         /* Set bits of CONFIG register but with static context switching */
1392         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1393         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1394 
1395         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1396 
1397         /* Set bits of CONFIG register with given context switching mode */
1398         writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1399 
1400         /* Initializes channel's priorities */
1401         sdma_set_channel_priority(&sdma->channel[0], 7);
1402 
1403         clk_disable(sdma->clk_ipg);
1404         clk_disable(sdma->clk_ahb);
1405 
1406         return 0;
1407 
1408 err_dma_alloc:
1409         clk_disable(sdma->clk_ipg);
1410         clk_disable(sdma->clk_ahb);
1411         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1412         return ret;
1413 }
1414 
1415 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1416 {
1417         struct imx_dma_data *data = fn_param;
1418 
1419         if (!imx_dma_is_general_purpose(chan))
1420                 return false;
1421 
1422         chan->private = data;
1423 
1424         return true;
1425 }
1426 
1427 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1428                                    struct of_dma *ofdma)
1429 {
1430         struct sdma_engine *sdma = ofdma->of_dma_data;
1431         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1432         struct imx_dma_data data;
1433 
1434         if (dma_spec->args_count != 3)
1435                 return NULL;
1436 
1437         data.dma_request = dma_spec->args[0];
1438         data.peripheral_type = dma_spec->args[1];
1439         data.priority = dma_spec->args[2];
1440 
1441         return dma_request_channel(mask, sdma_filter_fn, &data);
1442 }
1443 
1444 static int __init sdma_probe(struct platform_device *pdev)
1445 {
1446         const struct of_device_id *of_id =
1447                         of_match_device(sdma_dt_ids, &pdev->dev);
1448         struct device_node *np = pdev->dev.of_node;
1449         const char *fw_name;
1450         int ret;
1451         int irq;
1452         struct resource *iores;
1453         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1454         int i;
1455         struct sdma_engine *sdma;
1456         s32 *saddr_arr;
1457         const struct sdma_driver_data *drvdata = NULL;
1458 
1459         if (of_id)
1460                 drvdata = of_id->data;
1461         else if (pdev->id_entry)
1462                 drvdata = (void *)pdev->id_entry->driver_data;
1463 
1464         if (!drvdata) {
1465                 dev_err(&pdev->dev, "unable to find driver data\n");
1466                 return -EINVAL;
1467         }
1468 
1469         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1470         if (ret)
1471                 return ret;
1472 
1473         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1474         if (!sdma)
1475                 return -ENOMEM;
1476 
1477         spin_lock_init(&sdma->channel_0_lock);
1478 
1479         sdma->dev = &pdev->dev;
1480         sdma->drvdata = drvdata;
1481 
1482         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1483         irq = platform_get_irq(pdev, 0);
1484         if (!iores || irq < 0) {
1485                 ret = -EINVAL;
1486                 goto err_irq;
1487         }
1488 
1489         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1490                 ret = -EBUSY;
1491                 goto err_request_region;
1492         }
1493 
1494         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1495         if (IS_ERR(sdma->clk_ipg)) {
1496                 ret = PTR_ERR(sdma->clk_ipg);
1497                 goto err_clk;
1498         }
1499 
1500         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1501         if (IS_ERR(sdma->clk_ahb)) {
1502                 ret = PTR_ERR(sdma->clk_ahb);
1503                 goto err_clk;
1504         }
1505 
1506         clk_prepare(sdma->clk_ipg);
1507         clk_prepare(sdma->clk_ahb);
1508 
1509         sdma->regs = ioremap(iores->start, resource_size(iores));
1510         if (!sdma->regs) {
1511                 ret = -ENOMEM;
1512                 goto err_ioremap;
1513         }
1514 
1515         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1516         if (ret)
1517                 goto err_request_irq;
1518 
1519         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1520         if (!sdma->script_addrs) {
1521                 ret = -ENOMEM;
1522                 goto err_alloc;
1523         }
1524 
1525         /* initially no scripts available */
1526         saddr_arr = (s32 *)sdma->script_addrs;
1527         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1528                 saddr_arr[i] = -EINVAL;
1529 
1530         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1531         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1532 
1533         INIT_LIST_HEAD(&sdma->dma_device.channels);
1534         /* Initialize channel parameters */
1535         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1536                 struct sdma_channel *sdmac = &sdma->channel[i];
1537 
1538                 sdmac->sdma = sdma;
1539                 spin_lock_init(&sdmac->lock);
1540 
1541                 sdmac->chan.device = &sdma->dma_device;
1542                 dma_cookie_init(&sdmac->chan);
1543                 sdmac->channel = i;
1544 
1545                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1546                              (unsigned long) sdmac);
1547                 /*
1548                  * Add the channel to the DMAC list. Do not add channel 0 though
1549                  * because we need it internally in the SDMA driver. This also means
1550                  * that channel 0 in dmaengine counting matches sdma channel 1.
1551                  */
1552                 if (i)
1553                         list_add_tail(&sdmac->chan.device_node,
1554                                         &sdma->dma_device.channels);
1555         }
1556 
1557         ret = sdma_init(sdma);
1558         if (ret)
1559                 goto err_init;
1560 
1561         if (sdma->drvdata->script_addrs)
1562                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1563         if (pdata && pdata->script_addrs)
1564                 sdma_add_scripts(sdma, pdata->script_addrs);
1565 
1566         if (pdata) {
1567                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1568                 if (ret)
1569                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1570         } else {
1571                 /*
1572                  * Because that device tree does not encode ROM script address,
1573                  * the RAM script in firmware is mandatory for device tree
1574                  * probe, otherwise it fails.
1575                  */
1576                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1577                                               &fw_name);
1578                 if (ret)
1579                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1580                 else {
1581                         ret = sdma_get_firmware(sdma, fw_name);
1582                         if (ret)
1583                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1584                 }
1585         }
1586 
1587         sdma->dma_device.dev = &pdev->dev;
1588 
1589         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1590         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1591         sdma->dma_device.device_tx_status = sdma_tx_status;
1592         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1593         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1594         sdma->dma_device.device_control = sdma_control;
1595         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1596         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1597         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1598 
1599         ret = dma_async_device_register(&sdma->dma_device);
1600         if (ret) {
1601                 dev_err(&pdev->dev, "unable to register\n");
1602                 goto err_init;
1603         }
1604 
1605         if (np) {
1606                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1607                 if (ret) {
1608                         dev_err(&pdev->dev, "failed to register controller\n");
1609                         goto err_register;
1610                 }
1611         }
1612 
1613         dev_info(sdma->dev, "initialized\n");
1614 
1615         return 0;
1616 
1617 err_register:
1618         dma_async_device_unregister(&sdma->dma_device);
1619 err_init:
1620         kfree(sdma->script_addrs);
1621 err_alloc:
1622         free_irq(irq, sdma);
1623 err_request_irq:
1624         iounmap(sdma->regs);
1625 err_ioremap:
1626 err_clk:
1627         release_mem_region(iores->start, resource_size(iores));
1628 err_request_region:
1629 err_irq:
1630         kfree(sdma);
1631         return ret;
1632 }
1633 
1634 static int sdma_remove(struct platform_device *pdev)
1635 {
1636         return -EBUSY;
1637 }
1638 
1639 static struct platform_driver sdma_driver = {
1640         .driver         = {
1641                 .name   = "imx-sdma",
1642                 .of_match_table = sdma_dt_ids,
1643         },
1644         .id_table       = sdma_devtypes,
1645         .remove         = sdma_remove,
1646 };
1647 
1648 static int __init sdma_module_init(void)
1649 {
1650         return platform_driver_probe(&sdma_driver, sdma_probe);
1651 }
1652 module_init(sdma_module_init);
1653 
1654 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1655 MODULE_DESCRIPTION("i.MX SDMA driver");
1656 MODULE_LICENSE("GPL");
1657 

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