Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/dma/fsldma.c

  1 /*
  2  * Freescale MPC85xx, MPC83xx DMA Engine support
  3  *
  4  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  5  *
  6  * Author:
  7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
  8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
  9  *
 10  * Description:
 11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
 12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
 13  *   The support for MPC8349 DMA controller is also added.
 14  *
 15  * This driver instructs the DMA controller to issue the PCI Read Multiple
 16  * command for PCI read operations, instead of using the default PCI Read Line
 17  * command. Please be aware that this setting may result in read pre-fetching
 18  * on some platforms.
 19  *
 20  * This is free software; you can redistribute it and/or modify
 21  * it under the terms of the GNU General Public License as published by
 22  * the Free Software Foundation; either version 2 of the License, or
 23  * (at your option) any later version.
 24  *
 25  */
 26 
 27 #include <linux/init.h>
 28 #include <linux/module.h>
 29 #include <linux/pci.h>
 30 #include <linux/slab.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/dmaengine.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/dmapool.h>
 36 #include <linux/of_address.h>
 37 #include <linux/of_irq.h>
 38 #include <linux/of_platform.h>
 39 #include <linux/fsldma.h>
 40 #include "dmaengine.h"
 41 #include "fsldma.h"
 42 
 43 #define chan_dbg(chan, fmt, arg...)                                     \
 44         dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
 45 #define chan_err(chan, fmt, arg...)                                     \
 46         dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
 47 
 48 static const char msg_ld_oom[] = "No free memory for link descriptor";
 49 
 50 /*
 51  * Register Helpers
 52  */
 53 
 54 static void set_sr(struct fsldma_chan *chan, u32 val)
 55 {
 56         DMA_OUT(chan, &chan->regs->sr, val, 32);
 57 }
 58 
 59 static u32 get_sr(struct fsldma_chan *chan)
 60 {
 61         return DMA_IN(chan, &chan->regs->sr, 32);
 62 }
 63 
 64 static void set_mr(struct fsldma_chan *chan, u32 val)
 65 {
 66         DMA_OUT(chan, &chan->regs->mr, val, 32);
 67 }
 68 
 69 static u32 get_mr(struct fsldma_chan *chan)
 70 {
 71         return DMA_IN(chan, &chan->regs->mr, 32);
 72 }
 73 
 74 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
 75 {
 76         DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
 77 }
 78 
 79 static dma_addr_t get_cdar(struct fsldma_chan *chan)
 80 {
 81         return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
 82 }
 83 
 84 static void set_bcr(struct fsldma_chan *chan, u32 val)
 85 {
 86         DMA_OUT(chan, &chan->regs->bcr, val, 32);
 87 }
 88 
 89 static u32 get_bcr(struct fsldma_chan *chan)
 90 {
 91         return DMA_IN(chan, &chan->regs->bcr, 32);
 92 }
 93 
 94 /*
 95  * Descriptor Helpers
 96  */
 97 
 98 static void set_desc_cnt(struct fsldma_chan *chan,
 99                                 struct fsl_dma_ld_hw *hw, u32 count)
100 {
101         hw->count = CPU_TO_DMA(chan, count, 32);
102 }
103 
104 static void set_desc_src(struct fsldma_chan *chan,
105                          struct fsl_dma_ld_hw *hw, dma_addr_t src)
106 {
107         u64 snoop_bits;
108 
109         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111         hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
112 }
113 
114 static void set_desc_dst(struct fsldma_chan *chan,
115                          struct fsl_dma_ld_hw *hw, dma_addr_t dst)
116 {
117         u64 snoop_bits;
118 
119         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121         hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122 }
123 
124 static void set_desc_next(struct fsldma_chan *chan,
125                           struct fsl_dma_ld_hw *hw, dma_addr_t next)
126 {
127         u64 snoop_bits;
128 
129         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130                 ? FSL_DMA_SNEN : 0;
131         hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132 }
133 
134 static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
135 {
136         u64 snoop_bits;
137 
138         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
139                 ? FSL_DMA_SNEN : 0;
140 
141         desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142                 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
143                         | snoop_bits, 64);
144 }
145 
146 /*
147  * DMA Engine Hardware Control Helpers
148  */
149 
150 static void dma_init(struct fsldma_chan *chan)
151 {
152         /* Reset the channel */
153         set_mr(chan, 0);
154 
155         switch (chan->feature & FSL_DMA_IP_MASK) {
156         case FSL_DMA_IP_85XX:
157                 /* Set the channel to below modes:
158                  * EIE - Error interrupt enable
159                  * EOLNIE - End of links interrupt enable
160                  * BWC - Bandwidth sharing among channels
161                  */
162                 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163                         | FSL_DMA_MR_EOLNIE);
164                 break;
165         case FSL_DMA_IP_83XX:
166                 /* Set the channel to below modes:
167                  * EOTIE - End-of-transfer interrupt enable
168                  * PRC_RM - PCI read multiple
169                  */
170                 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
171                 break;
172         }
173 }
174 
175 static int dma_is_idle(struct fsldma_chan *chan)
176 {
177         u32 sr = get_sr(chan);
178         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179 }
180 
181 /*
182  * Start the DMA controller
183  *
184  * Preconditions:
185  * - the CDAR register must point to the start descriptor
186  * - the MRn[CS] bit must be cleared
187  */
188 static void dma_start(struct fsldma_chan *chan)
189 {
190         u32 mode;
191 
192         mode = get_mr(chan);
193 
194         if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
195                 set_bcr(chan, 0);
196                 mode |= FSL_DMA_MR_EMP_EN;
197         } else {
198                 mode &= ~FSL_DMA_MR_EMP_EN;
199         }
200 
201         if (chan->feature & FSL_DMA_CHAN_START_EXT) {
202                 mode |= FSL_DMA_MR_EMS_EN;
203         } else {
204                 mode &= ~FSL_DMA_MR_EMS_EN;
205                 mode |= FSL_DMA_MR_CS;
206         }
207 
208         set_mr(chan, mode);
209 }
210 
211 static void dma_halt(struct fsldma_chan *chan)
212 {
213         u32 mode;
214         int i;
215 
216         /* read the mode register */
217         mode = get_mr(chan);
218 
219         /*
220          * The 85xx controller supports channel abort, which will stop
221          * the current transfer. On 83xx, this bit is the transfer error
222          * mask bit, which should not be changed.
223          */
224         if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225                 mode |= FSL_DMA_MR_CA;
226                 set_mr(chan, mode);
227 
228                 mode &= ~FSL_DMA_MR_CA;
229         }
230 
231         /* stop the DMA controller */
232         mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
233         set_mr(chan, mode);
234 
235         /* wait for the DMA controller to become idle */
236         for (i = 0; i < 100; i++) {
237                 if (dma_is_idle(chan))
238                         return;
239 
240                 udelay(10);
241         }
242 
243         if (!dma_is_idle(chan))
244                 chan_err(chan, "DMA halt timeout!\n");
245 }
246 
247 /**
248  * fsl_chan_set_src_loop_size - Set source address hold transfer size
249  * @chan : Freescale DMA channel
250  * @size     : Address loop size, 0 for disable loop
251  *
252  * The set source address hold transfer size. The source
253  * address hold or loop transfer size is when the DMA transfer
254  * data from source address (SA), if the loop size is 4, the DMA will
255  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256  * SA + 1 ... and so on.
257  */
258 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
259 {
260         u32 mode;
261 
262         mode = get_mr(chan);
263 
264         switch (size) {
265         case 0:
266                 mode &= ~FSL_DMA_MR_SAHE;
267                 break;
268         case 1:
269         case 2:
270         case 4:
271         case 8:
272                 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
273                 break;
274         }
275 
276         set_mr(chan, mode);
277 }
278 
279 /**
280  * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
281  * @chan : Freescale DMA channel
282  * @size     : Address loop size, 0 for disable loop
283  *
284  * The set destination address hold transfer size. The destination
285  * address hold or loop transfer size is when the DMA transfer
286  * data to destination address (TA), if the loop size is 4, the DMA will
287  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288  * TA + 1 ... and so on.
289  */
290 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
291 {
292         u32 mode;
293 
294         mode = get_mr(chan);
295 
296         switch (size) {
297         case 0:
298                 mode &= ~FSL_DMA_MR_DAHE;
299                 break;
300         case 1:
301         case 2:
302         case 4:
303         case 8:
304                 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
305                 break;
306         }
307 
308         set_mr(chan, mode);
309 }
310 
311 /**
312  * fsl_chan_set_request_count - Set DMA Request Count for external control
313  * @chan : Freescale DMA channel
314  * @size     : Number of bytes to transfer in a single request
315  *
316  * The Freescale DMA channel can be controlled by the external signal DREQ#.
317  * The DMA request count is how many bytes are allowed to transfer before
318  * pausing the channel, after which a new assertion of DREQ# resumes channel
319  * operation.
320  *
321  * A size of 0 disables external pause control. The maximum size is 1024.
322  */
323 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
324 {
325         u32 mode;
326 
327         BUG_ON(size > 1024);
328 
329         mode = get_mr(chan);
330         mode |= (__ilog2(size) << 24) & 0x0f000000;
331 
332         set_mr(chan, mode);
333 }
334 
335 /**
336  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
337  * @chan : Freescale DMA channel
338  * @enable   : 0 is disabled, 1 is enabled.
339  *
340  * The Freescale DMA channel can be controlled by the external signal DREQ#.
341  * The DMA Request Count feature should be used in addition to this feature
342  * to set the number of bytes to transfer before pausing the channel.
343  */
344 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
345 {
346         if (enable)
347                 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
348         else
349                 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
350 }
351 
352 /**
353  * fsl_chan_toggle_ext_start - Toggle channel external start status
354  * @chan : Freescale DMA channel
355  * @enable   : 0 is disabled, 1 is enabled.
356  *
357  * If enable the external start, the channel can be started by an
358  * external DMA start pin. So the dma_start() does not start the
359  * transfer immediately. The DMA channel will wait for the
360  * control pin asserted.
361  */
362 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
363 {
364         if (enable)
365                 chan->feature |= FSL_DMA_CHAN_START_EXT;
366         else
367                 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
368 }
369 
370 int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371 {
372         struct fsldma_chan *chan;
373 
374         if (!dchan)
375                 return -EINVAL;
376 
377         chan = to_fsl_chan(dchan);
378 
379         fsl_chan_toggle_ext_start(chan, enable);
380         return 0;
381 }
382 EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383 
384 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
385 {
386         struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387 
388         if (list_empty(&chan->ld_pending))
389                 goto out_splice;
390 
391         /*
392          * Add the hardware descriptor to the chain of hardware descriptors
393          * that already exists in memory.
394          *
395          * This will un-set the EOL bit of the existing transaction, and the
396          * last link in this transaction will become the EOL descriptor.
397          */
398         set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399 
400         /*
401          * Add the software descriptor and all children to the list
402          * of pending transactions
403          */
404 out_splice:
405         list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406 }
407 
408 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409 {
410         struct fsldma_chan *chan = to_fsl_chan(tx->chan);
411         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412         struct fsl_desc_sw *child;
413         dma_cookie_t cookie = -EINVAL;
414 
415         spin_lock_bh(&chan->desc_lock);
416 
417 #ifdef CONFIG_PM
418         if (unlikely(chan->pm_state != RUNNING)) {
419                 chan_dbg(chan, "cannot submit due to suspend\n");
420                 spin_unlock_bh(&chan->desc_lock);
421                 return -1;
422         }
423 #endif
424 
425         /*
426          * assign cookies to all of the software descriptors
427          * that make up this transaction
428          */
429         list_for_each_entry(child, &desc->tx_list, node) {
430                 cookie = dma_cookie_assign(&child->async_tx);
431         }
432 
433         /* put this transaction onto the tail of the pending queue */
434         append_ld_queue(chan, desc);
435 
436         spin_unlock_bh(&chan->desc_lock);
437 
438         return cookie;
439 }
440 
441 /**
442  * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443  * @chan : Freescale DMA channel
444  * @desc: descriptor to be freed
445  */
446 static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447                 struct fsl_desc_sw *desc)
448 {
449         list_del(&desc->node);
450         chan_dbg(chan, "LD %p free\n", desc);
451         dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452 }
453 
454 /**
455  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
456  * @chan : Freescale DMA channel
457  *
458  * Return - The descriptor allocated. NULL for failed.
459  */
460 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
461 {
462         struct fsl_desc_sw *desc;
463         dma_addr_t pdesc;
464 
465         desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
466         if (!desc) {
467                 chan_dbg(chan, "out of memory for link descriptor\n");
468                 return NULL;
469         }
470 
471         memset(desc, 0, sizeof(*desc));
472         INIT_LIST_HEAD(&desc->tx_list);
473         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
474         desc->async_tx.tx_submit = fsl_dma_tx_submit;
475         desc->async_tx.phys = pdesc;
476 
477         chan_dbg(chan, "LD %p allocated\n", desc);
478 
479         return desc;
480 }
481 
482 /**
483  * fsldma_clean_completed_descriptor - free all descriptors which
484  * has been completed and acked
485  * @chan: Freescale DMA channel
486  *
487  * This function is used on all completed and acked descriptors.
488  * All descriptors should only be freed in this function.
489  */
490 static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
491 {
492         struct fsl_desc_sw *desc, *_desc;
493 
494         /* Run the callback for each descriptor, in order */
495         list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
496                 if (async_tx_test_ack(&desc->async_tx))
497                         fsl_dma_free_descriptor(chan, desc);
498 }
499 
500 /**
501  * fsldma_run_tx_complete_actions - cleanup a single link descriptor
502  * @chan: Freescale DMA channel
503  * @desc: descriptor to cleanup and free
504  * @cookie: Freescale DMA transaction identifier
505  *
506  * This function is used on a descriptor which has been executed by the DMA
507  * controller. It will run any callbacks, submit any dependencies.
508  */
509 static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
510                 struct fsl_desc_sw *desc, dma_cookie_t cookie)
511 {
512         struct dma_async_tx_descriptor *txd = &desc->async_tx;
513         dma_cookie_t ret = cookie;
514 
515         BUG_ON(txd->cookie < 0);
516 
517         if (txd->cookie > 0) {
518                 ret = txd->cookie;
519 
520                 /* Run the link descriptor callback function */
521                 if (txd->callback) {
522                         chan_dbg(chan, "LD %p callback\n", desc);
523                         txd->callback(txd->callback_param);
524                 }
525 
526                 dma_descriptor_unmap(txd);
527         }
528 
529         /* Run any dependencies */
530         dma_run_dependencies(txd);
531 
532         return ret;
533 }
534 
535 /**
536  * fsldma_clean_running_descriptor - move the completed descriptor from
537  * ld_running to ld_completed
538  * @chan: Freescale DMA channel
539  * @desc: the descriptor which is completed
540  *
541  * Free the descriptor directly if acked by async_tx api, or move it to
542  * queue ld_completed.
543  */
544 static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
545                 struct fsl_desc_sw *desc)
546 {
547         /* Remove from the list of transactions */
548         list_del(&desc->node);
549 
550         /*
551          * the client is allowed to attach dependent operations
552          * until 'ack' is set
553          */
554         if (!async_tx_test_ack(&desc->async_tx)) {
555                 /*
556                  * Move this descriptor to the list of descriptors which is
557                  * completed, but still awaiting the 'ack' bit to be set.
558                  */
559                 list_add_tail(&desc->node, &chan->ld_completed);
560                 return;
561         }
562 
563         dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
564 }
565 
566 /**
567  * fsl_chan_xfer_ld_queue - transfer any pending transactions
568  * @chan : Freescale DMA channel
569  *
570  * HARDWARE STATE: idle
571  * LOCKING: must hold chan->desc_lock
572  */
573 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
574 {
575         struct fsl_desc_sw *desc;
576 
577         /*
578          * If the list of pending descriptors is empty, then we
579          * don't need to do any work at all
580          */
581         if (list_empty(&chan->ld_pending)) {
582                 chan_dbg(chan, "no pending LDs\n");
583                 return;
584         }
585 
586         /*
587          * The DMA controller is not idle, which means that the interrupt
588          * handler will start any queued transactions when it runs after
589          * this transaction finishes
590          */
591         if (!chan->idle) {
592                 chan_dbg(chan, "DMA controller still busy\n");
593                 return;
594         }
595 
596         /*
597          * If there are some link descriptors which have not been
598          * transferred, we need to start the controller
599          */
600 
601         /*
602          * Move all elements from the queue of pending transactions
603          * onto the list of running transactions
604          */
605         chan_dbg(chan, "idle, starting controller\n");
606         desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
607         list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
608 
609         /*
610          * The 85xx DMA controller doesn't clear the channel start bit
611          * automatically at the end of a transfer. Therefore we must clear
612          * it in software before starting the transfer.
613          */
614         if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
615                 u32 mode;
616 
617                 mode = get_mr(chan);
618                 mode &= ~FSL_DMA_MR_CS;
619                 set_mr(chan, mode);
620         }
621 
622         /*
623          * Program the descriptor's address into the DMA controller,
624          * then start the DMA transaction
625          */
626         set_cdar(chan, desc->async_tx.phys);
627         get_cdar(chan);
628 
629         dma_start(chan);
630         chan->idle = false;
631 }
632 
633 /**
634  * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
635  * and move them to ld_completed to free until flag 'ack' is set
636  * @chan: Freescale DMA channel
637  *
638  * This function is used on descriptors which have been executed by the DMA
639  * controller. It will run any callbacks, submit any dependencies, then
640  * free these descriptors if flag 'ack' is set.
641  */
642 static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
643 {
644         struct fsl_desc_sw *desc, *_desc;
645         dma_cookie_t cookie = 0;
646         dma_addr_t curr_phys = get_cdar(chan);
647         int seen_current = 0;
648 
649         fsldma_clean_completed_descriptor(chan);
650 
651         /* Run the callback for each descriptor, in order */
652         list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
653                 /*
654                  * do not advance past the current descriptor loaded into the
655                  * hardware channel, subsequent descriptors are either in
656                  * process or have not been submitted
657                  */
658                 if (seen_current)
659                         break;
660 
661                 /*
662                  * stop the search if we reach the current descriptor and the
663                  * channel is busy
664                  */
665                 if (desc->async_tx.phys == curr_phys) {
666                         seen_current = 1;
667                         if (!dma_is_idle(chan))
668                                 break;
669                 }
670 
671                 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
672 
673                 fsldma_clean_running_descriptor(chan, desc);
674         }
675 
676         /*
677          * Start any pending transactions automatically
678          *
679          * In the ideal case, we keep the DMA controller busy while we go
680          * ahead and free the descriptors below.
681          */
682         fsl_chan_xfer_ld_queue(chan);
683 
684         if (cookie > 0)
685                 chan->common.completed_cookie = cookie;
686 }
687 
688 /**
689  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
690  * @chan : Freescale DMA channel
691  *
692  * This function will create a dma pool for descriptor allocation.
693  *
694  * Return - The number of descriptors allocated.
695  */
696 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
697 {
698         struct fsldma_chan *chan = to_fsl_chan(dchan);
699 
700         /* Has this channel already been allocated? */
701         if (chan->desc_pool)
702                 return 1;
703 
704         /*
705          * We need the descriptor to be aligned to 32bytes
706          * for meeting FSL DMA specification requirement.
707          */
708         chan->desc_pool = dma_pool_create(chan->name, chan->dev,
709                                           sizeof(struct fsl_desc_sw),
710                                           __alignof__(struct fsl_desc_sw), 0);
711         if (!chan->desc_pool) {
712                 chan_err(chan, "unable to allocate descriptor pool\n");
713                 return -ENOMEM;
714         }
715 
716         /* there is at least one descriptor free to be allocated */
717         return 1;
718 }
719 
720 /**
721  * fsldma_free_desc_list - Free all descriptors in a queue
722  * @chan: Freescae DMA channel
723  * @list: the list to free
724  *
725  * LOCKING: must hold chan->desc_lock
726  */
727 static void fsldma_free_desc_list(struct fsldma_chan *chan,
728                                   struct list_head *list)
729 {
730         struct fsl_desc_sw *desc, *_desc;
731 
732         list_for_each_entry_safe(desc, _desc, list, node)
733                 fsl_dma_free_descriptor(chan, desc);
734 }
735 
736 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
737                                           struct list_head *list)
738 {
739         struct fsl_desc_sw *desc, *_desc;
740 
741         list_for_each_entry_safe_reverse(desc, _desc, list, node)
742                 fsl_dma_free_descriptor(chan, desc);
743 }
744 
745 /**
746  * fsl_dma_free_chan_resources - Free all resources of the channel.
747  * @chan : Freescale DMA channel
748  */
749 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
750 {
751         struct fsldma_chan *chan = to_fsl_chan(dchan);
752 
753         chan_dbg(chan, "free all channel resources\n");
754         spin_lock_bh(&chan->desc_lock);
755         fsldma_cleanup_descriptors(chan);
756         fsldma_free_desc_list(chan, &chan->ld_pending);
757         fsldma_free_desc_list(chan, &chan->ld_running);
758         fsldma_free_desc_list(chan, &chan->ld_completed);
759         spin_unlock_bh(&chan->desc_lock);
760 
761         dma_pool_destroy(chan->desc_pool);
762         chan->desc_pool = NULL;
763 }
764 
765 static struct dma_async_tx_descriptor *
766 fsl_dma_prep_memcpy(struct dma_chan *dchan,
767         dma_addr_t dma_dst, dma_addr_t dma_src,
768         size_t len, unsigned long flags)
769 {
770         struct fsldma_chan *chan;
771         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
772         size_t copy;
773 
774         if (!dchan)
775                 return NULL;
776 
777         if (!len)
778                 return NULL;
779 
780         chan = to_fsl_chan(dchan);
781 
782         do {
783 
784                 /* Allocate the link descriptor from DMA pool */
785                 new = fsl_dma_alloc_descriptor(chan);
786                 if (!new) {
787                         chan_err(chan, "%s\n", msg_ld_oom);
788                         goto fail;
789                 }
790 
791                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
792 
793                 set_desc_cnt(chan, &new->hw, copy);
794                 set_desc_src(chan, &new->hw, dma_src);
795                 set_desc_dst(chan, &new->hw, dma_dst);
796 
797                 if (!first)
798                         first = new;
799                 else
800                         set_desc_next(chan, &prev->hw, new->async_tx.phys);
801 
802                 new->async_tx.cookie = 0;
803                 async_tx_ack(&new->async_tx);
804 
805                 prev = new;
806                 len -= copy;
807                 dma_src += copy;
808                 dma_dst += copy;
809 
810                 /* Insert the link descriptor to the LD ring */
811                 list_add_tail(&new->node, &first->tx_list);
812         } while (len);
813 
814         new->async_tx.flags = flags; /* client is in control of this ack */
815         new->async_tx.cookie = -EBUSY;
816 
817         /* Set End-of-link to the last link descriptor of new list */
818         set_ld_eol(chan, new);
819 
820         return &first->async_tx;
821 
822 fail:
823         if (!first)
824                 return NULL;
825 
826         fsldma_free_desc_list_reverse(chan, &first->tx_list);
827         return NULL;
828 }
829 
830 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
831         struct scatterlist *dst_sg, unsigned int dst_nents,
832         struct scatterlist *src_sg, unsigned int src_nents,
833         unsigned long flags)
834 {
835         struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
836         struct fsldma_chan *chan = to_fsl_chan(dchan);
837         size_t dst_avail, src_avail;
838         dma_addr_t dst, src;
839         size_t len;
840 
841         /* basic sanity checks */
842         if (dst_nents == 0 || src_nents == 0)
843                 return NULL;
844 
845         if (dst_sg == NULL || src_sg == NULL)
846                 return NULL;
847 
848         /*
849          * TODO: should we check that both scatterlists have the same
850          * TODO: number of bytes in total? Is that really an error?
851          */
852 
853         /* get prepared for the loop */
854         dst_avail = sg_dma_len(dst_sg);
855         src_avail = sg_dma_len(src_sg);
856 
857         /* run until we are out of scatterlist entries */
858         while (true) {
859 
860                 /* create the largest transaction possible */
861                 len = min_t(size_t, src_avail, dst_avail);
862                 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
863                 if (len == 0)
864                         goto fetch;
865 
866                 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
867                 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
868 
869                 /* allocate and populate the descriptor */
870                 new = fsl_dma_alloc_descriptor(chan);
871                 if (!new) {
872                         chan_err(chan, "%s\n", msg_ld_oom);
873                         goto fail;
874                 }
875 
876                 set_desc_cnt(chan, &new->hw, len);
877                 set_desc_src(chan, &new->hw, src);
878                 set_desc_dst(chan, &new->hw, dst);
879 
880                 if (!first)
881                         first = new;
882                 else
883                         set_desc_next(chan, &prev->hw, new->async_tx.phys);
884 
885                 new->async_tx.cookie = 0;
886                 async_tx_ack(&new->async_tx);
887                 prev = new;
888 
889                 /* Insert the link descriptor to the LD ring */
890                 list_add_tail(&new->node, &first->tx_list);
891 
892                 /* update metadata */
893                 dst_avail -= len;
894                 src_avail -= len;
895 
896 fetch:
897                 /* fetch the next dst scatterlist entry */
898                 if (dst_avail == 0) {
899 
900                         /* no more entries: we're done */
901                         if (dst_nents == 0)
902                                 break;
903 
904                         /* fetch the next entry: if there are no more: done */
905                         dst_sg = sg_next(dst_sg);
906                         if (dst_sg == NULL)
907                                 break;
908 
909                         dst_nents--;
910                         dst_avail = sg_dma_len(dst_sg);
911                 }
912 
913                 /* fetch the next src scatterlist entry */
914                 if (src_avail == 0) {
915 
916                         /* no more entries: we're done */
917                         if (src_nents == 0)
918                                 break;
919 
920                         /* fetch the next entry: if there are no more: done */
921                         src_sg = sg_next(src_sg);
922                         if (src_sg == NULL)
923                                 break;
924 
925                         src_nents--;
926                         src_avail = sg_dma_len(src_sg);
927                 }
928         }
929 
930         new->async_tx.flags = flags; /* client is in control of this ack */
931         new->async_tx.cookie = -EBUSY;
932 
933         /* Set End-of-link to the last link descriptor of new list */
934         set_ld_eol(chan, new);
935 
936         return &first->async_tx;
937 
938 fail:
939         if (!first)
940                 return NULL;
941 
942         fsldma_free_desc_list_reverse(chan, &first->tx_list);
943         return NULL;
944 }
945 
946 static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
947 {
948         struct fsldma_chan *chan;
949 
950         if (!dchan)
951                 return -EINVAL;
952 
953         chan = to_fsl_chan(dchan);
954 
955         spin_lock_bh(&chan->desc_lock);
956 
957         /* Halt the DMA engine */
958         dma_halt(chan);
959 
960         /* Remove and free all of the descriptors in the LD queue */
961         fsldma_free_desc_list(chan, &chan->ld_pending);
962         fsldma_free_desc_list(chan, &chan->ld_running);
963         fsldma_free_desc_list(chan, &chan->ld_completed);
964         chan->idle = true;
965 
966         spin_unlock_bh(&chan->desc_lock);
967         return 0;
968 }
969 
970 static int fsl_dma_device_config(struct dma_chan *dchan,
971                                  struct dma_slave_config *config)
972 {
973         struct fsldma_chan *chan;
974         int size;
975 
976         if (!dchan)
977                 return -EINVAL;
978 
979         chan = to_fsl_chan(dchan);
980 
981         /* make sure the channel supports setting burst size */
982         if (!chan->set_request_count)
983                 return -ENXIO;
984 
985         /* we set the controller burst size depending on direction */
986         if (config->direction == DMA_MEM_TO_DEV)
987                 size = config->dst_addr_width * config->dst_maxburst;
988         else
989                 size = config->src_addr_width * config->src_maxburst;
990 
991         chan->set_request_count(chan, size);
992         return 0;
993 }
994 
995 
996 /**
997  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
998  * @chan : Freescale DMA channel
999  */
1000 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
1001 {
1002         struct fsldma_chan *chan = to_fsl_chan(dchan);
1003 
1004         spin_lock_bh(&chan->desc_lock);
1005         fsl_chan_xfer_ld_queue(chan);
1006         spin_unlock_bh(&chan->desc_lock);
1007 }
1008 
1009 /**
1010  * fsl_tx_status - Determine the DMA status
1011  * @chan : Freescale DMA channel
1012  */
1013 static enum dma_status fsl_tx_status(struct dma_chan *dchan,
1014                                         dma_cookie_t cookie,
1015                                         struct dma_tx_state *txstate)
1016 {
1017         struct fsldma_chan *chan = to_fsl_chan(dchan);
1018         enum dma_status ret;
1019 
1020         ret = dma_cookie_status(dchan, cookie, txstate);
1021         if (ret == DMA_COMPLETE)
1022                 return ret;
1023 
1024         spin_lock_bh(&chan->desc_lock);
1025         fsldma_cleanup_descriptors(chan);
1026         spin_unlock_bh(&chan->desc_lock);
1027 
1028         return dma_cookie_status(dchan, cookie, txstate);
1029 }
1030 
1031 /*----------------------------------------------------------------------------*/
1032 /* Interrupt Handling                                                         */
1033 /*----------------------------------------------------------------------------*/
1034 
1035 static irqreturn_t fsldma_chan_irq(int irq, void *data)
1036 {
1037         struct fsldma_chan *chan = data;
1038         u32 stat;
1039 
1040         /* save and clear the status register */
1041         stat = get_sr(chan);
1042         set_sr(chan, stat);
1043         chan_dbg(chan, "irq: stat = 0x%x\n", stat);
1044 
1045         /* check that this was really our device */
1046         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1047         if (!stat)
1048                 return IRQ_NONE;
1049 
1050         if (stat & FSL_DMA_SR_TE)
1051                 chan_err(chan, "Transfer Error!\n");
1052 
1053         /*
1054          * Programming Error
1055          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1056          * trigger a PE interrupt.
1057          */
1058         if (stat & FSL_DMA_SR_PE) {
1059                 chan_dbg(chan, "irq: Programming Error INT\n");
1060                 stat &= ~FSL_DMA_SR_PE;
1061                 if (get_bcr(chan) != 0)
1062                         chan_err(chan, "Programming Error!\n");
1063         }
1064 
1065         /*
1066          * For MPC8349, EOCDI event need to update cookie
1067          * and start the next transfer if it exist.
1068          */
1069         if (stat & FSL_DMA_SR_EOCDI) {
1070                 chan_dbg(chan, "irq: End-of-Chain link INT\n");
1071                 stat &= ~FSL_DMA_SR_EOCDI;
1072         }
1073 
1074         /*
1075          * If it current transfer is the end-of-transfer,
1076          * we should clear the Channel Start bit for
1077          * prepare next transfer.
1078          */
1079         if (stat & FSL_DMA_SR_EOLNI) {
1080                 chan_dbg(chan, "irq: End-of-link INT\n");
1081                 stat &= ~FSL_DMA_SR_EOLNI;
1082         }
1083 
1084         /* check that the DMA controller is really idle */
1085         if (!dma_is_idle(chan))
1086                 chan_err(chan, "irq: controller not idle!\n");
1087 
1088         /* check that we handled all of the bits */
1089         if (stat)
1090                 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1091 
1092         /*
1093          * Schedule the tasklet to handle all cleanup of the current
1094          * transaction. It will start a new transaction if there is
1095          * one pending.
1096          */
1097         tasklet_schedule(&chan->tasklet);
1098         chan_dbg(chan, "irq: Exit\n");
1099         return IRQ_HANDLED;
1100 }
1101 
1102 static void dma_do_tasklet(unsigned long data)
1103 {
1104         struct fsldma_chan *chan = (struct fsldma_chan *)data;
1105 
1106         chan_dbg(chan, "tasklet entry\n");
1107 
1108         spin_lock_bh(&chan->desc_lock);
1109 
1110         /* the hardware is now idle and ready for more */
1111         chan->idle = true;
1112 
1113         /* Run all cleanup for descriptors which have been completed */
1114         fsldma_cleanup_descriptors(chan);
1115 
1116         spin_unlock_bh(&chan->desc_lock);
1117 
1118         chan_dbg(chan, "tasklet exit\n");
1119 }
1120 
1121 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1122 {
1123         struct fsldma_device *fdev = data;
1124         struct fsldma_chan *chan;
1125         unsigned int handled = 0;
1126         u32 gsr, mask;
1127         int i;
1128 
1129         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1130                                                    : in_le32(fdev->regs);
1131         mask = 0xff000000;
1132         dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1133 
1134         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1135                 chan = fdev->chan[i];
1136                 if (!chan)
1137                         continue;
1138 
1139                 if (gsr & mask) {
1140                         dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1141                         fsldma_chan_irq(irq, chan);
1142                         handled++;
1143                 }
1144 
1145                 gsr &= ~mask;
1146                 mask >>= 8;
1147         }
1148 
1149         return IRQ_RETVAL(handled);
1150 }
1151 
1152 static void fsldma_free_irqs(struct fsldma_device *fdev)
1153 {
1154         struct fsldma_chan *chan;
1155         int i;
1156 
1157         if (fdev->irq != NO_IRQ) {
1158                 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1159                 free_irq(fdev->irq, fdev);
1160                 return;
1161         }
1162 
1163         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1164                 chan = fdev->chan[i];
1165                 if (chan && chan->irq != NO_IRQ) {
1166                         chan_dbg(chan, "free per-channel IRQ\n");
1167                         free_irq(chan->irq, chan);
1168                 }
1169         }
1170 }
1171 
1172 static int fsldma_request_irqs(struct fsldma_device *fdev)
1173 {
1174         struct fsldma_chan *chan;
1175         int ret;
1176         int i;
1177 
1178         /* if we have a per-controller IRQ, use that */
1179         if (fdev->irq != NO_IRQ) {
1180                 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1181                 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1182                                   "fsldma-controller", fdev);
1183                 return ret;
1184         }
1185 
1186         /* no per-controller IRQ, use the per-channel IRQs */
1187         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1188                 chan = fdev->chan[i];
1189                 if (!chan)
1190                         continue;
1191 
1192                 if (chan->irq == NO_IRQ) {
1193                         chan_err(chan, "interrupts property missing in device tree\n");
1194                         ret = -ENODEV;
1195                         goto out_unwind;
1196                 }
1197 
1198                 chan_dbg(chan, "request per-channel IRQ\n");
1199                 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1200                                   "fsldma-chan", chan);
1201                 if (ret) {
1202                         chan_err(chan, "unable to request per-channel IRQ\n");
1203                         goto out_unwind;
1204                 }
1205         }
1206 
1207         return 0;
1208 
1209 out_unwind:
1210         for (/* none */; i >= 0; i--) {
1211                 chan = fdev->chan[i];
1212                 if (!chan)
1213                         continue;
1214 
1215                 if (chan->irq == NO_IRQ)
1216                         continue;
1217 
1218                 free_irq(chan->irq, chan);
1219         }
1220 
1221         return ret;
1222 }
1223 
1224 /*----------------------------------------------------------------------------*/
1225 /* OpenFirmware Subsystem                                                     */
1226 /*----------------------------------------------------------------------------*/
1227 
1228 static int fsl_dma_chan_probe(struct fsldma_device *fdev,
1229         struct device_node *node, u32 feature, const char *compatible)
1230 {
1231         struct fsldma_chan *chan;
1232         struct resource res;
1233         int err;
1234 
1235         /* alloc channel */
1236         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1237         if (!chan) {
1238                 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1239                 err = -ENOMEM;
1240                 goto out_return;
1241         }
1242 
1243         /* ioremap registers for use */
1244         chan->regs = of_iomap(node, 0);
1245         if (!chan->regs) {
1246                 dev_err(fdev->dev, "unable to ioremap registers\n");
1247                 err = -ENOMEM;
1248                 goto out_free_chan;
1249         }
1250 
1251         err = of_address_to_resource(node, 0, &res);
1252         if (err) {
1253                 dev_err(fdev->dev, "unable to find 'reg' property\n");
1254                 goto out_iounmap_regs;
1255         }
1256 
1257         chan->feature = feature;
1258         if (!fdev->feature)
1259                 fdev->feature = chan->feature;
1260 
1261         /*
1262          * If the DMA device's feature is different than the feature
1263          * of its channels, report the bug
1264          */
1265         WARN_ON(fdev->feature != chan->feature);
1266 
1267         chan->dev = fdev->dev;
1268         chan->id = (res.start & 0xfff) < 0x300 ?
1269                    ((res.start - 0x100) & 0xfff) >> 7 :
1270                    ((res.start - 0x200) & 0xfff) >> 7;
1271         if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1272                 dev_err(fdev->dev, "too many channels for device\n");
1273                 err = -EINVAL;
1274                 goto out_iounmap_regs;
1275         }
1276 
1277         fdev->chan[chan->id] = chan;
1278         tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1279         snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1280 
1281         /* Initialize the channel */
1282         dma_init(chan);
1283 
1284         /* Clear cdar registers */
1285         set_cdar(chan, 0);
1286 
1287         switch (chan->feature & FSL_DMA_IP_MASK) {
1288         case FSL_DMA_IP_85XX:
1289                 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1290         case FSL_DMA_IP_83XX:
1291                 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1292                 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1293                 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1294                 chan->set_request_count = fsl_chan_set_request_count;
1295         }
1296 
1297         spin_lock_init(&chan->desc_lock);
1298         INIT_LIST_HEAD(&chan->ld_pending);
1299         INIT_LIST_HEAD(&chan->ld_running);
1300         INIT_LIST_HEAD(&chan->ld_completed);
1301         chan->idle = true;
1302 #ifdef CONFIG_PM
1303         chan->pm_state = RUNNING;
1304 #endif
1305 
1306         chan->common.device = &fdev->common;
1307         dma_cookie_init(&chan->common);
1308 
1309         /* find the IRQ line, if it exists in the device tree */
1310         chan->irq = irq_of_parse_and_map(node, 0);
1311 
1312         /* Add the channel to DMA device channel list */
1313         list_add_tail(&chan->common.device_node, &fdev->common.channels);
1314 
1315         dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1316                  chan->irq != NO_IRQ ? chan->irq : fdev->irq);
1317 
1318         return 0;
1319 
1320 out_iounmap_regs:
1321         iounmap(chan->regs);
1322 out_free_chan:
1323         kfree(chan);
1324 out_return:
1325         return err;
1326 }
1327 
1328 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1329 {
1330         irq_dispose_mapping(chan->irq);
1331         list_del(&chan->common.device_node);
1332         iounmap(chan->regs);
1333         kfree(chan);
1334 }
1335 
1336 static int fsldma_of_probe(struct platform_device *op)
1337 {
1338         struct fsldma_device *fdev;
1339         struct device_node *child;
1340         int err;
1341 
1342         fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1343         if (!fdev) {
1344                 dev_err(&op->dev, "No enough memory for 'priv'\n");
1345                 err = -ENOMEM;
1346                 goto out_return;
1347         }
1348 
1349         fdev->dev = &op->dev;
1350         INIT_LIST_HEAD(&fdev->common.channels);
1351 
1352         /* ioremap the registers for use */
1353         fdev->regs = of_iomap(op->dev.of_node, 0);
1354         if (!fdev->regs) {
1355                 dev_err(&op->dev, "unable to ioremap registers\n");
1356                 err = -ENOMEM;
1357                 goto out_free_fdev;
1358         }
1359 
1360         /* map the channel IRQ if it exists, but don't hookup the handler yet */
1361         fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1362 
1363         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1364         dma_cap_set(DMA_SG, fdev->common.cap_mask);
1365         dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1366         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1367         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1368         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1369         fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
1370         fdev->common.device_tx_status = fsl_tx_status;
1371         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1372         fdev->common.device_config = fsl_dma_device_config;
1373         fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
1374         fdev->common.dev = &op->dev;
1375 
1376         fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1377         fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1378         fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1379         fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1380 
1381         dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1382 
1383         platform_set_drvdata(op, fdev);
1384 
1385         /*
1386          * We cannot use of_platform_bus_probe() because there is no
1387          * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1388          * channel object.
1389          */
1390         for_each_child_of_node(op->dev.of_node, child) {
1391                 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1392                         fsl_dma_chan_probe(fdev, child,
1393                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1394                                 "fsl,eloplus-dma-channel");
1395                 }
1396 
1397                 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1398                         fsl_dma_chan_probe(fdev, child,
1399                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1400                                 "fsl,elo-dma-channel");
1401                 }
1402         }
1403 
1404         /*
1405          * Hookup the IRQ handler(s)
1406          *
1407          * If we have a per-controller interrupt, we prefer that to the
1408          * per-channel interrupts to reduce the number of shared interrupt
1409          * handlers on the same IRQ line
1410          */
1411         err = fsldma_request_irqs(fdev);
1412         if (err) {
1413                 dev_err(fdev->dev, "unable to request IRQs\n");
1414                 goto out_free_fdev;
1415         }
1416 
1417         dma_async_device_register(&fdev->common);
1418         return 0;
1419 
1420 out_free_fdev:
1421         irq_dispose_mapping(fdev->irq);
1422         kfree(fdev);
1423 out_return:
1424         return err;
1425 }
1426 
1427 static int fsldma_of_remove(struct platform_device *op)
1428 {
1429         struct fsldma_device *fdev;
1430         unsigned int i;
1431 
1432         fdev = platform_get_drvdata(op);
1433         dma_async_device_unregister(&fdev->common);
1434 
1435         fsldma_free_irqs(fdev);
1436 
1437         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1438                 if (fdev->chan[i])
1439                         fsl_dma_chan_remove(fdev->chan[i]);
1440         }
1441 
1442         iounmap(fdev->regs);
1443         kfree(fdev);
1444 
1445         return 0;
1446 }
1447 
1448 #ifdef CONFIG_PM
1449 static int fsldma_suspend_late(struct device *dev)
1450 {
1451         struct platform_device *pdev = to_platform_device(dev);
1452         struct fsldma_device *fdev = platform_get_drvdata(pdev);
1453         struct fsldma_chan *chan;
1454         int i;
1455 
1456         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1457                 chan = fdev->chan[i];
1458                 if (!chan)
1459                         continue;
1460 
1461                 spin_lock_bh(&chan->desc_lock);
1462                 if (unlikely(!chan->idle))
1463                         goto out;
1464                 chan->regs_save.mr = get_mr(chan);
1465                 chan->pm_state = SUSPENDED;
1466                 spin_unlock_bh(&chan->desc_lock);
1467         }
1468         return 0;
1469 
1470 out:
1471         for (; i >= 0; i--) {
1472                 chan = fdev->chan[i];
1473                 if (!chan)
1474                         continue;
1475                 chan->pm_state = RUNNING;
1476                 spin_unlock_bh(&chan->desc_lock);
1477         }
1478         return -EBUSY;
1479 }
1480 
1481 static int fsldma_resume_early(struct device *dev)
1482 {
1483         struct platform_device *pdev = to_platform_device(dev);
1484         struct fsldma_device *fdev = platform_get_drvdata(pdev);
1485         struct fsldma_chan *chan;
1486         u32 mode;
1487         int i;
1488 
1489         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1490                 chan = fdev->chan[i];
1491                 if (!chan)
1492                         continue;
1493 
1494                 spin_lock_bh(&chan->desc_lock);
1495                 mode = chan->regs_save.mr
1496                         & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1497                 set_mr(chan, mode);
1498                 chan->pm_state = RUNNING;
1499                 spin_unlock_bh(&chan->desc_lock);
1500         }
1501 
1502         return 0;
1503 }
1504 
1505 static const struct dev_pm_ops fsldma_pm_ops = {
1506         .suspend_late   = fsldma_suspend_late,
1507         .resume_early   = fsldma_resume_early,
1508 };
1509 #endif
1510 
1511 static const struct of_device_id fsldma_of_ids[] = {
1512         { .compatible = "fsl,elo3-dma", },
1513         { .compatible = "fsl,eloplus-dma", },
1514         { .compatible = "fsl,elo-dma", },
1515         {}
1516 };
1517 MODULE_DEVICE_TABLE(of, fsldma_of_ids);
1518 
1519 static struct platform_driver fsldma_of_driver = {
1520         .driver = {
1521                 .name = "fsl-elo-dma",
1522                 .of_match_table = fsldma_of_ids,
1523 #ifdef CONFIG_PM
1524                 .pm = &fsldma_pm_ops,
1525 #endif
1526         },
1527         .probe = fsldma_of_probe,
1528         .remove = fsldma_of_remove,
1529 };
1530 
1531 /*----------------------------------------------------------------------------*/
1532 /* Module Init / Exit                                                         */
1533 /*----------------------------------------------------------------------------*/
1534 
1535 static __init int fsldma_init(void)
1536 {
1537         pr_info("Freescale Elo series DMA driver\n");
1538         return platform_driver_register(&fsldma_of_driver);
1539 }
1540 
1541 static void __exit fsldma_exit(void)
1542 {
1543         platform_driver_unregister(&fsldma_of_driver);
1544 }
1545 
1546 subsys_initcall(fsldma_init);
1547 module_exit(fsldma_exit);
1548 
1549 MODULE_DESCRIPTION("Freescale Elo series DMA driver");
1550 MODULE_LICENSE("GPL");
1551 

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