Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/dma/fsldma.c

  1 /*
  2  * Freescale MPC85xx, MPC83xx DMA Engine support
  3  *
  4  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  5  *
  6  * Author:
  7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
  8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
  9  *
 10  * Description:
 11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
 12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
 13  *   The support for MPC8349 DMA controller is also added.
 14  *
 15  * This driver instructs the DMA controller to issue the PCI Read Multiple
 16  * command for PCI read operations, instead of using the default PCI Read Line
 17  * command. Please be aware that this setting may result in read pre-fetching
 18  * on some platforms.
 19  *
 20  * This is free software; you can redistribute it and/or modify
 21  * it under the terms of the GNU General Public License as published by
 22  * the Free Software Foundation; either version 2 of the License, or
 23  * (at your option) any later version.
 24  *
 25  */
 26 
 27 #include <linux/init.h>
 28 #include <linux/module.h>
 29 #include <linux/pci.h>
 30 #include <linux/slab.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/dmaengine.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/dmapool.h>
 36 #include <linux/of_address.h>
 37 #include <linux/of_irq.h>
 38 #include <linux/of_platform.h>
 39 #include <linux/fsldma.h>
 40 #include "dmaengine.h"
 41 #include "fsldma.h"
 42 
 43 #define chan_dbg(chan, fmt, arg...)                                     \
 44         dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
 45 #define chan_err(chan, fmt, arg...)                                     \
 46         dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
 47 
 48 static const char msg_ld_oom[] = "No free memory for link descriptor";
 49 
 50 /*
 51  * Register Helpers
 52  */
 53 
 54 static void set_sr(struct fsldma_chan *chan, u32 val)
 55 {
 56         DMA_OUT(chan, &chan->regs->sr, val, 32);
 57 }
 58 
 59 static u32 get_sr(struct fsldma_chan *chan)
 60 {
 61         return DMA_IN(chan, &chan->regs->sr, 32);
 62 }
 63 
 64 static void set_mr(struct fsldma_chan *chan, u32 val)
 65 {
 66         DMA_OUT(chan, &chan->regs->mr, val, 32);
 67 }
 68 
 69 static u32 get_mr(struct fsldma_chan *chan)
 70 {
 71         return DMA_IN(chan, &chan->regs->mr, 32);
 72 }
 73 
 74 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
 75 {
 76         DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
 77 }
 78 
 79 static dma_addr_t get_cdar(struct fsldma_chan *chan)
 80 {
 81         return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
 82 }
 83 
 84 static void set_bcr(struct fsldma_chan *chan, u32 val)
 85 {
 86         DMA_OUT(chan, &chan->regs->bcr, val, 32);
 87 }
 88 
 89 static u32 get_bcr(struct fsldma_chan *chan)
 90 {
 91         return DMA_IN(chan, &chan->regs->bcr, 32);
 92 }
 93 
 94 /*
 95  * Descriptor Helpers
 96  */
 97 
 98 static void set_desc_cnt(struct fsldma_chan *chan,
 99                                 struct fsl_dma_ld_hw *hw, u32 count)
100 {
101         hw->count = CPU_TO_DMA(chan, count, 32);
102 }
103 
104 static void set_desc_src(struct fsldma_chan *chan,
105                          struct fsl_dma_ld_hw *hw, dma_addr_t src)
106 {
107         u64 snoop_bits;
108 
109         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111         hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
112 }
113 
114 static void set_desc_dst(struct fsldma_chan *chan,
115                          struct fsl_dma_ld_hw *hw, dma_addr_t dst)
116 {
117         u64 snoop_bits;
118 
119         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121         hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122 }
123 
124 static void set_desc_next(struct fsldma_chan *chan,
125                           struct fsl_dma_ld_hw *hw, dma_addr_t next)
126 {
127         u64 snoop_bits;
128 
129         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130                 ? FSL_DMA_SNEN : 0;
131         hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132 }
133 
134 static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
135 {
136         u64 snoop_bits;
137 
138         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
139                 ? FSL_DMA_SNEN : 0;
140 
141         desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142                 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
143                         | snoop_bits, 64);
144 }
145 
146 /*
147  * DMA Engine Hardware Control Helpers
148  */
149 
150 static void dma_init(struct fsldma_chan *chan)
151 {
152         /* Reset the channel */
153         set_mr(chan, 0);
154 
155         switch (chan->feature & FSL_DMA_IP_MASK) {
156         case FSL_DMA_IP_85XX:
157                 /* Set the channel to below modes:
158                  * EIE - Error interrupt enable
159                  * EOLNIE - End of links interrupt enable
160                  * BWC - Bandwidth sharing among channels
161                  */
162                 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163                         | FSL_DMA_MR_EOLNIE);
164                 break;
165         case FSL_DMA_IP_83XX:
166                 /* Set the channel to below modes:
167                  * EOTIE - End-of-transfer interrupt enable
168                  * PRC_RM - PCI read multiple
169                  */
170                 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
171                 break;
172         }
173 }
174 
175 static int dma_is_idle(struct fsldma_chan *chan)
176 {
177         u32 sr = get_sr(chan);
178         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179 }
180 
181 /*
182  * Start the DMA controller
183  *
184  * Preconditions:
185  * - the CDAR register must point to the start descriptor
186  * - the MRn[CS] bit must be cleared
187  */
188 static void dma_start(struct fsldma_chan *chan)
189 {
190         u32 mode;
191 
192         mode = get_mr(chan);
193 
194         if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
195                 set_bcr(chan, 0);
196                 mode |= FSL_DMA_MR_EMP_EN;
197         } else {
198                 mode &= ~FSL_DMA_MR_EMP_EN;
199         }
200 
201         if (chan->feature & FSL_DMA_CHAN_START_EXT) {
202                 mode |= FSL_DMA_MR_EMS_EN;
203         } else {
204                 mode &= ~FSL_DMA_MR_EMS_EN;
205                 mode |= FSL_DMA_MR_CS;
206         }
207 
208         set_mr(chan, mode);
209 }
210 
211 static void dma_halt(struct fsldma_chan *chan)
212 {
213         u32 mode;
214         int i;
215 
216         /* read the mode register */
217         mode = get_mr(chan);
218 
219         /*
220          * The 85xx controller supports channel abort, which will stop
221          * the current transfer. On 83xx, this bit is the transfer error
222          * mask bit, which should not be changed.
223          */
224         if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225                 mode |= FSL_DMA_MR_CA;
226                 set_mr(chan, mode);
227 
228                 mode &= ~FSL_DMA_MR_CA;
229         }
230 
231         /* stop the DMA controller */
232         mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
233         set_mr(chan, mode);
234 
235         /* wait for the DMA controller to become idle */
236         for (i = 0; i < 100; i++) {
237                 if (dma_is_idle(chan))
238                         return;
239 
240                 udelay(10);
241         }
242 
243         if (!dma_is_idle(chan))
244                 chan_err(chan, "DMA halt timeout!\n");
245 }
246 
247 /**
248  * fsl_chan_set_src_loop_size - Set source address hold transfer size
249  * @chan : Freescale DMA channel
250  * @size     : Address loop size, 0 for disable loop
251  *
252  * The set source address hold transfer size. The source
253  * address hold or loop transfer size is when the DMA transfer
254  * data from source address (SA), if the loop size is 4, the DMA will
255  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256  * SA + 1 ... and so on.
257  */
258 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
259 {
260         u32 mode;
261 
262         mode = get_mr(chan);
263 
264         switch (size) {
265         case 0:
266                 mode &= ~FSL_DMA_MR_SAHE;
267                 break;
268         case 1:
269         case 2:
270         case 4:
271         case 8:
272                 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
273                 break;
274         }
275 
276         set_mr(chan, mode);
277 }
278 
279 /**
280  * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
281  * @chan : Freescale DMA channel
282  * @size     : Address loop size, 0 for disable loop
283  *
284  * The set destination address hold transfer size. The destination
285  * address hold or loop transfer size is when the DMA transfer
286  * data to destination address (TA), if the loop size is 4, the DMA will
287  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288  * TA + 1 ... and so on.
289  */
290 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
291 {
292         u32 mode;
293 
294         mode = get_mr(chan);
295 
296         switch (size) {
297         case 0:
298                 mode &= ~FSL_DMA_MR_DAHE;
299                 break;
300         case 1:
301         case 2:
302         case 4:
303         case 8:
304                 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
305                 break;
306         }
307 
308         set_mr(chan, mode);
309 }
310 
311 /**
312  * fsl_chan_set_request_count - Set DMA Request Count for external control
313  * @chan : Freescale DMA channel
314  * @size     : Number of bytes to transfer in a single request
315  *
316  * The Freescale DMA channel can be controlled by the external signal DREQ#.
317  * The DMA request count is how many bytes are allowed to transfer before
318  * pausing the channel, after which a new assertion of DREQ# resumes channel
319  * operation.
320  *
321  * A size of 0 disables external pause control. The maximum size is 1024.
322  */
323 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
324 {
325         u32 mode;
326 
327         BUG_ON(size > 1024);
328 
329         mode = get_mr(chan);
330         mode |= (__ilog2(size) << 24) & 0x0f000000;
331 
332         set_mr(chan, mode);
333 }
334 
335 /**
336  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
337  * @chan : Freescale DMA channel
338  * @enable   : 0 is disabled, 1 is enabled.
339  *
340  * The Freescale DMA channel can be controlled by the external signal DREQ#.
341  * The DMA Request Count feature should be used in addition to this feature
342  * to set the number of bytes to transfer before pausing the channel.
343  */
344 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
345 {
346         if (enable)
347                 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
348         else
349                 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
350 }
351 
352 /**
353  * fsl_chan_toggle_ext_start - Toggle channel external start status
354  * @chan : Freescale DMA channel
355  * @enable   : 0 is disabled, 1 is enabled.
356  *
357  * If enable the external start, the channel can be started by an
358  * external DMA start pin. So the dma_start() does not start the
359  * transfer immediately. The DMA channel will wait for the
360  * control pin asserted.
361  */
362 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
363 {
364         if (enable)
365                 chan->feature |= FSL_DMA_CHAN_START_EXT;
366         else
367                 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
368 }
369 
370 int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371 {
372         struct fsldma_chan *chan;
373 
374         if (!dchan)
375                 return -EINVAL;
376 
377         chan = to_fsl_chan(dchan);
378 
379         fsl_chan_toggle_ext_start(chan, enable);
380         return 0;
381 }
382 EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383 
384 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
385 {
386         struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387 
388         if (list_empty(&chan->ld_pending))
389                 goto out_splice;
390 
391         /*
392          * Add the hardware descriptor to the chain of hardware descriptors
393          * that already exists in memory.
394          *
395          * This will un-set the EOL bit of the existing transaction, and the
396          * last link in this transaction will become the EOL descriptor.
397          */
398         set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399 
400         /*
401          * Add the software descriptor and all children to the list
402          * of pending transactions
403          */
404 out_splice:
405         list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406 }
407 
408 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409 {
410         struct fsldma_chan *chan = to_fsl_chan(tx->chan);
411         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412         struct fsl_desc_sw *child;
413         dma_cookie_t cookie = -EINVAL;
414 
415         spin_lock_bh(&chan->desc_lock);
416 
417 #ifdef CONFIG_PM
418         if (unlikely(chan->pm_state != RUNNING)) {
419                 chan_dbg(chan, "cannot submit due to suspend\n");
420                 spin_unlock_bh(&chan->desc_lock);
421                 return -1;
422         }
423 #endif
424 
425         /*
426          * assign cookies to all of the software descriptors
427          * that make up this transaction
428          */
429         list_for_each_entry(child, &desc->tx_list, node) {
430                 cookie = dma_cookie_assign(&child->async_tx);
431         }
432 
433         /* put this transaction onto the tail of the pending queue */
434         append_ld_queue(chan, desc);
435 
436         spin_unlock_bh(&chan->desc_lock);
437 
438         return cookie;
439 }
440 
441 /**
442  * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443  * @chan : Freescale DMA channel
444  * @desc: descriptor to be freed
445  */
446 static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447                 struct fsl_desc_sw *desc)
448 {
449         list_del(&desc->node);
450         chan_dbg(chan, "LD %p free\n", desc);
451         dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452 }
453 
454 /**
455  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
456  * @chan : Freescale DMA channel
457  *
458  * Return - The descriptor allocated. NULL for failed.
459  */
460 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
461 {
462         struct fsl_desc_sw *desc;
463         dma_addr_t pdesc;
464 
465         desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
466         if (!desc) {
467                 chan_dbg(chan, "out of memory for link descriptor\n");
468                 return NULL;
469         }
470 
471         INIT_LIST_HEAD(&desc->tx_list);
472         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
473         desc->async_tx.tx_submit = fsl_dma_tx_submit;
474         desc->async_tx.phys = pdesc;
475 
476         chan_dbg(chan, "LD %p allocated\n", desc);
477 
478         return desc;
479 }
480 
481 /**
482  * fsldma_clean_completed_descriptor - free all descriptors which
483  * has been completed and acked
484  * @chan: Freescale DMA channel
485  *
486  * This function is used on all completed and acked descriptors.
487  * All descriptors should only be freed in this function.
488  */
489 static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
490 {
491         struct fsl_desc_sw *desc, *_desc;
492 
493         /* Run the callback for each descriptor, in order */
494         list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
495                 if (async_tx_test_ack(&desc->async_tx))
496                         fsl_dma_free_descriptor(chan, desc);
497 }
498 
499 /**
500  * fsldma_run_tx_complete_actions - cleanup a single link descriptor
501  * @chan: Freescale DMA channel
502  * @desc: descriptor to cleanup and free
503  * @cookie: Freescale DMA transaction identifier
504  *
505  * This function is used on a descriptor which has been executed by the DMA
506  * controller. It will run any callbacks, submit any dependencies.
507  */
508 static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
509                 struct fsl_desc_sw *desc, dma_cookie_t cookie)
510 {
511         struct dma_async_tx_descriptor *txd = &desc->async_tx;
512         dma_cookie_t ret = cookie;
513 
514         BUG_ON(txd->cookie < 0);
515 
516         if (txd->cookie > 0) {
517                 ret = txd->cookie;
518 
519                 /* Run the link descriptor callback function */
520                 if (txd->callback) {
521                         chan_dbg(chan, "LD %p callback\n", desc);
522                         txd->callback(txd->callback_param);
523                 }
524 
525                 dma_descriptor_unmap(txd);
526         }
527 
528         /* Run any dependencies */
529         dma_run_dependencies(txd);
530 
531         return ret;
532 }
533 
534 /**
535  * fsldma_clean_running_descriptor - move the completed descriptor from
536  * ld_running to ld_completed
537  * @chan: Freescale DMA channel
538  * @desc: the descriptor which is completed
539  *
540  * Free the descriptor directly if acked by async_tx api, or move it to
541  * queue ld_completed.
542  */
543 static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
544                 struct fsl_desc_sw *desc)
545 {
546         /* Remove from the list of transactions */
547         list_del(&desc->node);
548 
549         /*
550          * the client is allowed to attach dependent operations
551          * until 'ack' is set
552          */
553         if (!async_tx_test_ack(&desc->async_tx)) {
554                 /*
555                  * Move this descriptor to the list of descriptors which is
556                  * completed, but still awaiting the 'ack' bit to be set.
557                  */
558                 list_add_tail(&desc->node, &chan->ld_completed);
559                 return;
560         }
561 
562         dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
563 }
564 
565 /**
566  * fsl_chan_xfer_ld_queue - transfer any pending transactions
567  * @chan : Freescale DMA channel
568  *
569  * HARDWARE STATE: idle
570  * LOCKING: must hold chan->desc_lock
571  */
572 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
573 {
574         struct fsl_desc_sw *desc;
575 
576         /*
577          * If the list of pending descriptors is empty, then we
578          * don't need to do any work at all
579          */
580         if (list_empty(&chan->ld_pending)) {
581                 chan_dbg(chan, "no pending LDs\n");
582                 return;
583         }
584 
585         /*
586          * The DMA controller is not idle, which means that the interrupt
587          * handler will start any queued transactions when it runs after
588          * this transaction finishes
589          */
590         if (!chan->idle) {
591                 chan_dbg(chan, "DMA controller still busy\n");
592                 return;
593         }
594 
595         /*
596          * If there are some link descriptors which have not been
597          * transferred, we need to start the controller
598          */
599 
600         /*
601          * Move all elements from the queue of pending transactions
602          * onto the list of running transactions
603          */
604         chan_dbg(chan, "idle, starting controller\n");
605         desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
606         list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
607 
608         /*
609          * The 85xx DMA controller doesn't clear the channel start bit
610          * automatically at the end of a transfer. Therefore we must clear
611          * it in software before starting the transfer.
612          */
613         if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
614                 u32 mode;
615 
616                 mode = get_mr(chan);
617                 mode &= ~FSL_DMA_MR_CS;
618                 set_mr(chan, mode);
619         }
620 
621         /*
622          * Program the descriptor's address into the DMA controller,
623          * then start the DMA transaction
624          */
625         set_cdar(chan, desc->async_tx.phys);
626         get_cdar(chan);
627 
628         dma_start(chan);
629         chan->idle = false;
630 }
631 
632 /**
633  * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
634  * and move them to ld_completed to free until flag 'ack' is set
635  * @chan: Freescale DMA channel
636  *
637  * This function is used on descriptors which have been executed by the DMA
638  * controller. It will run any callbacks, submit any dependencies, then
639  * free these descriptors if flag 'ack' is set.
640  */
641 static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
642 {
643         struct fsl_desc_sw *desc, *_desc;
644         dma_cookie_t cookie = 0;
645         dma_addr_t curr_phys = get_cdar(chan);
646         int seen_current = 0;
647 
648         fsldma_clean_completed_descriptor(chan);
649 
650         /* Run the callback for each descriptor, in order */
651         list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
652                 /*
653                  * do not advance past the current descriptor loaded into the
654                  * hardware channel, subsequent descriptors are either in
655                  * process or have not been submitted
656                  */
657                 if (seen_current)
658                         break;
659 
660                 /*
661                  * stop the search if we reach the current descriptor and the
662                  * channel is busy
663                  */
664                 if (desc->async_tx.phys == curr_phys) {
665                         seen_current = 1;
666                         if (!dma_is_idle(chan))
667                                 break;
668                 }
669 
670                 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
671 
672                 fsldma_clean_running_descriptor(chan, desc);
673         }
674 
675         /*
676          * Start any pending transactions automatically
677          *
678          * In the ideal case, we keep the DMA controller busy while we go
679          * ahead and free the descriptors below.
680          */
681         fsl_chan_xfer_ld_queue(chan);
682 
683         if (cookie > 0)
684                 chan->common.completed_cookie = cookie;
685 }
686 
687 /**
688  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
689  * @chan : Freescale DMA channel
690  *
691  * This function will create a dma pool for descriptor allocation.
692  *
693  * Return - The number of descriptors allocated.
694  */
695 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
696 {
697         struct fsldma_chan *chan = to_fsl_chan(dchan);
698 
699         /* Has this channel already been allocated? */
700         if (chan->desc_pool)
701                 return 1;
702 
703         /*
704          * We need the descriptor to be aligned to 32bytes
705          * for meeting FSL DMA specification requirement.
706          */
707         chan->desc_pool = dma_pool_create(chan->name, chan->dev,
708                                           sizeof(struct fsl_desc_sw),
709                                           __alignof__(struct fsl_desc_sw), 0);
710         if (!chan->desc_pool) {
711                 chan_err(chan, "unable to allocate descriptor pool\n");
712                 return -ENOMEM;
713         }
714 
715         /* there is at least one descriptor free to be allocated */
716         return 1;
717 }
718 
719 /**
720  * fsldma_free_desc_list - Free all descriptors in a queue
721  * @chan: Freescae DMA channel
722  * @list: the list to free
723  *
724  * LOCKING: must hold chan->desc_lock
725  */
726 static void fsldma_free_desc_list(struct fsldma_chan *chan,
727                                   struct list_head *list)
728 {
729         struct fsl_desc_sw *desc, *_desc;
730 
731         list_for_each_entry_safe(desc, _desc, list, node)
732                 fsl_dma_free_descriptor(chan, desc);
733 }
734 
735 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
736                                           struct list_head *list)
737 {
738         struct fsl_desc_sw *desc, *_desc;
739 
740         list_for_each_entry_safe_reverse(desc, _desc, list, node)
741                 fsl_dma_free_descriptor(chan, desc);
742 }
743 
744 /**
745  * fsl_dma_free_chan_resources - Free all resources of the channel.
746  * @chan : Freescale DMA channel
747  */
748 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
749 {
750         struct fsldma_chan *chan = to_fsl_chan(dchan);
751 
752         chan_dbg(chan, "free all channel resources\n");
753         spin_lock_bh(&chan->desc_lock);
754         fsldma_cleanup_descriptors(chan);
755         fsldma_free_desc_list(chan, &chan->ld_pending);
756         fsldma_free_desc_list(chan, &chan->ld_running);
757         fsldma_free_desc_list(chan, &chan->ld_completed);
758         spin_unlock_bh(&chan->desc_lock);
759 
760         dma_pool_destroy(chan->desc_pool);
761         chan->desc_pool = NULL;
762 }
763 
764 static struct dma_async_tx_descriptor *
765 fsl_dma_prep_memcpy(struct dma_chan *dchan,
766         dma_addr_t dma_dst, dma_addr_t dma_src,
767         size_t len, unsigned long flags)
768 {
769         struct fsldma_chan *chan;
770         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
771         size_t copy;
772 
773         if (!dchan)
774                 return NULL;
775 
776         if (!len)
777                 return NULL;
778 
779         chan = to_fsl_chan(dchan);
780 
781         do {
782 
783                 /* Allocate the link descriptor from DMA pool */
784                 new = fsl_dma_alloc_descriptor(chan);
785                 if (!new) {
786                         chan_err(chan, "%s\n", msg_ld_oom);
787                         goto fail;
788                 }
789 
790                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
791 
792                 set_desc_cnt(chan, &new->hw, copy);
793                 set_desc_src(chan, &new->hw, dma_src);
794                 set_desc_dst(chan, &new->hw, dma_dst);
795 
796                 if (!first)
797                         first = new;
798                 else
799                         set_desc_next(chan, &prev->hw, new->async_tx.phys);
800 
801                 new->async_tx.cookie = 0;
802                 async_tx_ack(&new->async_tx);
803 
804                 prev = new;
805                 len -= copy;
806                 dma_src += copy;
807                 dma_dst += copy;
808 
809                 /* Insert the link descriptor to the LD ring */
810                 list_add_tail(&new->node, &first->tx_list);
811         } while (len);
812 
813         new->async_tx.flags = flags; /* client is in control of this ack */
814         new->async_tx.cookie = -EBUSY;
815 
816         /* Set End-of-link to the last link descriptor of new list */
817         set_ld_eol(chan, new);
818 
819         return &first->async_tx;
820 
821 fail:
822         if (!first)
823                 return NULL;
824 
825         fsldma_free_desc_list_reverse(chan, &first->tx_list);
826         return NULL;
827 }
828 
829 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
830         struct scatterlist *dst_sg, unsigned int dst_nents,
831         struct scatterlist *src_sg, unsigned int src_nents,
832         unsigned long flags)
833 {
834         struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
835         struct fsldma_chan *chan = to_fsl_chan(dchan);
836         size_t dst_avail, src_avail;
837         dma_addr_t dst, src;
838         size_t len;
839 
840         /* basic sanity checks */
841         if (dst_nents == 0 || src_nents == 0)
842                 return NULL;
843 
844         if (dst_sg == NULL || src_sg == NULL)
845                 return NULL;
846 
847         /*
848          * TODO: should we check that both scatterlists have the same
849          * TODO: number of bytes in total? Is that really an error?
850          */
851 
852         /* get prepared for the loop */
853         dst_avail = sg_dma_len(dst_sg);
854         src_avail = sg_dma_len(src_sg);
855 
856         /* run until we are out of scatterlist entries */
857         while (true) {
858 
859                 /* create the largest transaction possible */
860                 len = min_t(size_t, src_avail, dst_avail);
861                 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
862                 if (len == 0)
863                         goto fetch;
864 
865                 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
866                 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
867 
868                 /* allocate and populate the descriptor */
869                 new = fsl_dma_alloc_descriptor(chan);
870                 if (!new) {
871                         chan_err(chan, "%s\n", msg_ld_oom);
872                         goto fail;
873                 }
874 
875                 set_desc_cnt(chan, &new->hw, len);
876                 set_desc_src(chan, &new->hw, src);
877                 set_desc_dst(chan, &new->hw, dst);
878 
879                 if (!first)
880                         first = new;
881                 else
882                         set_desc_next(chan, &prev->hw, new->async_tx.phys);
883 
884                 new->async_tx.cookie = 0;
885                 async_tx_ack(&new->async_tx);
886                 prev = new;
887 
888                 /* Insert the link descriptor to the LD ring */
889                 list_add_tail(&new->node, &first->tx_list);
890 
891                 /* update metadata */
892                 dst_avail -= len;
893                 src_avail -= len;
894 
895 fetch:
896                 /* fetch the next dst scatterlist entry */
897                 if (dst_avail == 0) {
898 
899                         /* no more entries: we're done */
900                         if (dst_nents == 0)
901                                 break;
902 
903                         /* fetch the next entry: if there are no more: done */
904                         dst_sg = sg_next(dst_sg);
905                         if (dst_sg == NULL)
906                                 break;
907 
908                         dst_nents--;
909                         dst_avail = sg_dma_len(dst_sg);
910                 }
911 
912                 /* fetch the next src scatterlist entry */
913                 if (src_avail == 0) {
914 
915                         /* no more entries: we're done */
916                         if (src_nents == 0)
917                                 break;
918 
919                         /* fetch the next entry: if there are no more: done */
920                         src_sg = sg_next(src_sg);
921                         if (src_sg == NULL)
922                                 break;
923 
924                         src_nents--;
925                         src_avail = sg_dma_len(src_sg);
926                 }
927         }
928 
929         new->async_tx.flags = flags; /* client is in control of this ack */
930         new->async_tx.cookie = -EBUSY;
931 
932         /* Set End-of-link to the last link descriptor of new list */
933         set_ld_eol(chan, new);
934 
935         return &first->async_tx;
936 
937 fail:
938         if (!first)
939                 return NULL;
940 
941         fsldma_free_desc_list_reverse(chan, &first->tx_list);
942         return NULL;
943 }
944 
945 static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
946 {
947         struct fsldma_chan *chan;
948 
949         if (!dchan)
950                 return -EINVAL;
951 
952         chan = to_fsl_chan(dchan);
953 
954         spin_lock_bh(&chan->desc_lock);
955 
956         /* Halt the DMA engine */
957         dma_halt(chan);
958 
959         /* Remove and free all of the descriptors in the LD queue */
960         fsldma_free_desc_list(chan, &chan->ld_pending);
961         fsldma_free_desc_list(chan, &chan->ld_running);
962         fsldma_free_desc_list(chan, &chan->ld_completed);
963         chan->idle = true;
964 
965         spin_unlock_bh(&chan->desc_lock);
966         return 0;
967 }
968 
969 static int fsl_dma_device_config(struct dma_chan *dchan,
970                                  struct dma_slave_config *config)
971 {
972         struct fsldma_chan *chan;
973         int size;
974 
975         if (!dchan)
976                 return -EINVAL;
977 
978         chan = to_fsl_chan(dchan);
979 
980         /* make sure the channel supports setting burst size */
981         if (!chan->set_request_count)
982                 return -ENXIO;
983 
984         /* we set the controller burst size depending on direction */
985         if (config->direction == DMA_MEM_TO_DEV)
986                 size = config->dst_addr_width * config->dst_maxburst;
987         else
988                 size = config->src_addr_width * config->src_maxburst;
989 
990         chan->set_request_count(chan, size);
991         return 0;
992 }
993 
994 
995 /**
996  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
997  * @chan : Freescale DMA channel
998  */
999 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
1000 {
1001         struct fsldma_chan *chan = to_fsl_chan(dchan);
1002 
1003         spin_lock_bh(&chan->desc_lock);
1004         fsl_chan_xfer_ld_queue(chan);
1005         spin_unlock_bh(&chan->desc_lock);
1006 }
1007 
1008 /**
1009  * fsl_tx_status - Determine the DMA status
1010  * @chan : Freescale DMA channel
1011  */
1012 static enum dma_status fsl_tx_status(struct dma_chan *dchan,
1013                                         dma_cookie_t cookie,
1014                                         struct dma_tx_state *txstate)
1015 {
1016         struct fsldma_chan *chan = to_fsl_chan(dchan);
1017         enum dma_status ret;
1018 
1019         ret = dma_cookie_status(dchan, cookie, txstate);
1020         if (ret == DMA_COMPLETE)
1021                 return ret;
1022 
1023         spin_lock_bh(&chan->desc_lock);
1024         fsldma_cleanup_descriptors(chan);
1025         spin_unlock_bh(&chan->desc_lock);
1026 
1027         return dma_cookie_status(dchan, cookie, txstate);
1028 }
1029 
1030 /*----------------------------------------------------------------------------*/
1031 /* Interrupt Handling                                                         */
1032 /*----------------------------------------------------------------------------*/
1033 
1034 static irqreturn_t fsldma_chan_irq(int irq, void *data)
1035 {
1036         struct fsldma_chan *chan = data;
1037         u32 stat;
1038 
1039         /* save and clear the status register */
1040         stat = get_sr(chan);
1041         set_sr(chan, stat);
1042         chan_dbg(chan, "irq: stat = 0x%x\n", stat);
1043 
1044         /* check that this was really our device */
1045         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1046         if (!stat)
1047                 return IRQ_NONE;
1048 
1049         if (stat & FSL_DMA_SR_TE)
1050                 chan_err(chan, "Transfer Error!\n");
1051 
1052         /*
1053          * Programming Error
1054          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1055          * trigger a PE interrupt.
1056          */
1057         if (stat & FSL_DMA_SR_PE) {
1058                 chan_dbg(chan, "irq: Programming Error INT\n");
1059                 stat &= ~FSL_DMA_SR_PE;
1060                 if (get_bcr(chan) != 0)
1061                         chan_err(chan, "Programming Error!\n");
1062         }
1063 
1064         /*
1065          * For MPC8349, EOCDI event need to update cookie
1066          * and start the next transfer if it exist.
1067          */
1068         if (stat & FSL_DMA_SR_EOCDI) {
1069                 chan_dbg(chan, "irq: End-of-Chain link INT\n");
1070                 stat &= ~FSL_DMA_SR_EOCDI;
1071         }
1072 
1073         /*
1074          * If it current transfer is the end-of-transfer,
1075          * we should clear the Channel Start bit for
1076          * prepare next transfer.
1077          */
1078         if (stat & FSL_DMA_SR_EOLNI) {
1079                 chan_dbg(chan, "irq: End-of-link INT\n");
1080                 stat &= ~FSL_DMA_SR_EOLNI;
1081         }
1082 
1083         /* check that the DMA controller is really idle */
1084         if (!dma_is_idle(chan))
1085                 chan_err(chan, "irq: controller not idle!\n");
1086 
1087         /* check that we handled all of the bits */
1088         if (stat)
1089                 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1090 
1091         /*
1092          * Schedule the tasklet to handle all cleanup of the current
1093          * transaction. It will start a new transaction if there is
1094          * one pending.
1095          */
1096         tasklet_schedule(&chan->tasklet);
1097         chan_dbg(chan, "irq: Exit\n");
1098         return IRQ_HANDLED;
1099 }
1100 
1101 static void dma_do_tasklet(unsigned long data)
1102 {
1103         struct fsldma_chan *chan = (struct fsldma_chan *)data;
1104 
1105         chan_dbg(chan, "tasklet entry\n");
1106 
1107         spin_lock_bh(&chan->desc_lock);
1108 
1109         /* the hardware is now idle and ready for more */
1110         chan->idle = true;
1111 
1112         /* Run all cleanup for descriptors which have been completed */
1113         fsldma_cleanup_descriptors(chan);
1114 
1115         spin_unlock_bh(&chan->desc_lock);
1116 
1117         chan_dbg(chan, "tasklet exit\n");
1118 }
1119 
1120 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1121 {
1122         struct fsldma_device *fdev = data;
1123         struct fsldma_chan *chan;
1124         unsigned int handled = 0;
1125         u32 gsr, mask;
1126         int i;
1127 
1128         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1129                                                    : in_le32(fdev->regs);
1130         mask = 0xff000000;
1131         dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1132 
1133         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1134                 chan = fdev->chan[i];
1135                 if (!chan)
1136                         continue;
1137 
1138                 if (gsr & mask) {
1139                         dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1140                         fsldma_chan_irq(irq, chan);
1141                         handled++;
1142                 }
1143 
1144                 gsr &= ~mask;
1145                 mask >>= 8;
1146         }
1147 
1148         return IRQ_RETVAL(handled);
1149 }
1150 
1151 static void fsldma_free_irqs(struct fsldma_device *fdev)
1152 {
1153         struct fsldma_chan *chan;
1154         int i;
1155 
1156         if (fdev->irq != NO_IRQ) {
1157                 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1158                 free_irq(fdev->irq, fdev);
1159                 return;
1160         }
1161 
1162         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1163                 chan = fdev->chan[i];
1164                 if (chan && chan->irq != NO_IRQ) {
1165                         chan_dbg(chan, "free per-channel IRQ\n");
1166                         free_irq(chan->irq, chan);
1167                 }
1168         }
1169 }
1170 
1171 static int fsldma_request_irqs(struct fsldma_device *fdev)
1172 {
1173         struct fsldma_chan *chan;
1174         int ret;
1175         int i;
1176 
1177         /* if we have a per-controller IRQ, use that */
1178         if (fdev->irq != NO_IRQ) {
1179                 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1180                 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1181                                   "fsldma-controller", fdev);
1182                 return ret;
1183         }
1184 
1185         /* no per-controller IRQ, use the per-channel IRQs */
1186         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1187                 chan = fdev->chan[i];
1188                 if (!chan)
1189                         continue;
1190 
1191                 if (chan->irq == NO_IRQ) {
1192                         chan_err(chan, "interrupts property missing in device tree\n");
1193                         ret = -ENODEV;
1194                         goto out_unwind;
1195                 }
1196 
1197                 chan_dbg(chan, "request per-channel IRQ\n");
1198                 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1199                                   "fsldma-chan", chan);
1200                 if (ret) {
1201                         chan_err(chan, "unable to request per-channel IRQ\n");
1202                         goto out_unwind;
1203                 }
1204         }
1205 
1206         return 0;
1207 
1208 out_unwind:
1209         for (/* none */; i >= 0; i--) {
1210                 chan = fdev->chan[i];
1211                 if (!chan)
1212                         continue;
1213 
1214                 if (chan->irq == NO_IRQ)
1215                         continue;
1216 
1217                 free_irq(chan->irq, chan);
1218         }
1219 
1220         return ret;
1221 }
1222 
1223 /*----------------------------------------------------------------------------*/
1224 /* OpenFirmware Subsystem                                                     */
1225 /*----------------------------------------------------------------------------*/
1226 
1227 static int fsl_dma_chan_probe(struct fsldma_device *fdev,
1228         struct device_node *node, u32 feature, const char *compatible)
1229 {
1230         struct fsldma_chan *chan;
1231         struct resource res;
1232         int err;
1233 
1234         /* alloc channel */
1235         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1236         if (!chan) {
1237                 err = -ENOMEM;
1238                 goto out_return;
1239         }
1240 
1241         /* ioremap registers for use */
1242         chan->regs = of_iomap(node, 0);
1243         if (!chan->regs) {
1244                 dev_err(fdev->dev, "unable to ioremap registers\n");
1245                 err = -ENOMEM;
1246                 goto out_free_chan;
1247         }
1248 
1249         err = of_address_to_resource(node, 0, &res);
1250         if (err) {
1251                 dev_err(fdev->dev, "unable to find 'reg' property\n");
1252                 goto out_iounmap_regs;
1253         }
1254 
1255         chan->feature = feature;
1256         if (!fdev->feature)
1257                 fdev->feature = chan->feature;
1258 
1259         /*
1260          * If the DMA device's feature is different than the feature
1261          * of its channels, report the bug
1262          */
1263         WARN_ON(fdev->feature != chan->feature);
1264 
1265         chan->dev = fdev->dev;
1266         chan->id = (res.start & 0xfff) < 0x300 ?
1267                    ((res.start - 0x100) & 0xfff) >> 7 :
1268                    ((res.start - 0x200) & 0xfff) >> 7;
1269         if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1270                 dev_err(fdev->dev, "too many channels for device\n");
1271                 err = -EINVAL;
1272                 goto out_iounmap_regs;
1273         }
1274 
1275         fdev->chan[chan->id] = chan;
1276         tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1277         snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1278 
1279         /* Initialize the channel */
1280         dma_init(chan);
1281 
1282         /* Clear cdar registers */
1283         set_cdar(chan, 0);
1284 
1285         switch (chan->feature & FSL_DMA_IP_MASK) {
1286         case FSL_DMA_IP_85XX:
1287                 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1288         case FSL_DMA_IP_83XX:
1289                 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1290                 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1291                 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1292                 chan->set_request_count = fsl_chan_set_request_count;
1293         }
1294 
1295         spin_lock_init(&chan->desc_lock);
1296         INIT_LIST_HEAD(&chan->ld_pending);
1297         INIT_LIST_HEAD(&chan->ld_running);
1298         INIT_LIST_HEAD(&chan->ld_completed);
1299         chan->idle = true;
1300 #ifdef CONFIG_PM
1301         chan->pm_state = RUNNING;
1302 #endif
1303 
1304         chan->common.device = &fdev->common;
1305         dma_cookie_init(&chan->common);
1306 
1307         /* find the IRQ line, if it exists in the device tree */
1308         chan->irq = irq_of_parse_and_map(node, 0);
1309 
1310         /* Add the channel to DMA device channel list */
1311         list_add_tail(&chan->common.device_node, &fdev->common.channels);
1312 
1313         dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1314                  chan->irq != NO_IRQ ? chan->irq : fdev->irq);
1315 
1316         return 0;
1317 
1318 out_iounmap_regs:
1319         iounmap(chan->regs);
1320 out_free_chan:
1321         kfree(chan);
1322 out_return:
1323         return err;
1324 }
1325 
1326 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1327 {
1328         irq_dispose_mapping(chan->irq);
1329         list_del(&chan->common.device_node);
1330         iounmap(chan->regs);
1331         kfree(chan);
1332 }
1333 
1334 static int fsldma_of_probe(struct platform_device *op)
1335 {
1336         struct fsldma_device *fdev;
1337         struct device_node *child;
1338         int err;
1339 
1340         fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1341         if (!fdev) {
1342                 err = -ENOMEM;
1343                 goto out_return;
1344         }
1345 
1346         fdev->dev = &op->dev;
1347         INIT_LIST_HEAD(&fdev->common.channels);
1348 
1349         /* ioremap the registers for use */
1350         fdev->regs = of_iomap(op->dev.of_node, 0);
1351         if (!fdev->regs) {
1352                 dev_err(&op->dev, "unable to ioremap registers\n");
1353                 err = -ENOMEM;
1354                 goto out_free_fdev;
1355         }
1356 
1357         /* map the channel IRQ if it exists, but don't hookup the handler yet */
1358         fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1359 
1360         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1361         dma_cap_set(DMA_SG, fdev->common.cap_mask);
1362         dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1363         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1364         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1365         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1366         fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
1367         fdev->common.device_tx_status = fsl_tx_status;
1368         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1369         fdev->common.device_config = fsl_dma_device_config;
1370         fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
1371         fdev->common.dev = &op->dev;
1372 
1373         fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1374         fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1375         fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1376         fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1377 
1378         dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1379 
1380         platform_set_drvdata(op, fdev);
1381 
1382         /*
1383          * We cannot use of_platform_bus_probe() because there is no
1384          * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1385          * channel object.
1386          */
1387         for_each_child_of_node(op->dev.of_node, child) {
1388                 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1389                         fsl_dma_chan_probe(fdev, child,
1390                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1391                                 "fsl,eloplus-dma-channel");
1392                 }
1393 
1394                 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1395                         fsl_dma_chan_probe(fdev, child,
1396                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1397                                 "fsl,elo-dma-channel");
1398                 }
1399         }
1400 
1401         /*
1402          * Hookup the IRQ handler(s)
1403          *
1404          * If we have a per-controller interrupt, we prefer that to the
1405          * per-channel interrupts to reduce the number of shared interrupt
1406          * handlers on the same IRQ line
1407          */
1408         err = fsldma_request_irqs(fdev);
1409         if (err) {
1410                 dev_err(fdev->dev, "unable to request IRQs\n");
1411                 goto out_free_fdev;
1412         }
1413 
1414         dma_async_device_register(&fdev->common);
1415         return 0;
1416 
1417 out_free_fdev:
1418         irq_dispose_mapping(fdev->irq);
1419         kfree(fdev);
1420 out_return:
1421         return err;
1422 }
1423 
1424 static int fsldma_of_remove(struct platform_device *op)
1425 {
1426         struct fsldma_device *fdev;
1427         unsigned int i;
1428 
1429         fdev = platform_get_drvdata(op);
1430         dma_async_device_unregister(&fdev->common);
1431 
1432         fsldma_free_irqs(fdev);
1433 
1434         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1435                 if (fdev->chan[i])
1436                         fsl_dma_chan_remove(fdev->chan[i]);
1437         }
1438 
1439         iounmap(fdev->regs);
1440         kfree(fdev);
1441 
1442         return 0;
1443 }
1444 
1445 #ifdef CONFIG_PM
1446 static int fsldma_suspend_late(struct device *dev)
1447 {
1448         struct platform_device *pdev = to_platform_device(dev);
1449         struct fsldma_device *fdev = platform_get_drvdata(pdev);
1450         struct fsldma_chan *chan;
1451         int i;
1452 
1453         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1454                 chan = fdev->chan[i];
1455                 if (!chan)
1456                         continue;
1457 
1458                 spin_lock_bh(&chan->desc_lock);
1459                 if (unlikely(!chan->idle))
1460                         goto out;
1461                 chan->regs_save.mr = get_mr(chan);
1462                 chan->pm_state = SUSPENDED;
1463                 spin_unlock_bh(&chan->desc_lock);
1464         }
1465         return 0;
1466 
1467 out:
1468         for (; i >= 0; i--) {
1469                 chan = fdev->chan[i];
1470                 if (!chan)
1471                         continue;
1472                 chan->pm_state = RUNNING;
1473                 spin_unlock_bh(&chan->desc_lock);
1474         }
1475         return -EBUSY;
1476 }
1477 
1478 static int fsldma_resume_early(struct device *dev)
1479 {
1480         struct platform_device *pdev = to_platform_device(dev);
1481         struct fsldma_device *fdev = platform_get_drvdata(pdev);
1482         struct fsldma_chan *chan;
1483         u32 mode;
1484         int i;
1485 
1486         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1487                 chan = fdev->chan[i];
1488                 if (!chan)
1489                         continue;
1490 
1491                 spin_lock_bh(&chan->desc_lock);
1492                 mode = chan->regs_save.mr
1493                         & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1494                 set_mr(chan, mode);
1495                 chan->pm_state = RUNNING;
1496                 spin_unlock_bh(&chan->desc_lock);
1497         }
1498 
1499         return 0;
1500 }
1501 
1502 static const struct dev_pm_ops fsldma_pm_ops = {
1503         .suspend_late   = fsldma_suspend_late,
1504         .resume_early   = fsldma_resume_early,
1505 };
1506 #endif
1507 
1508 static const struct of_device_id fsldma_of_ids[] = {
1509         { .compatible = "fsl,elo3-dma", },
1510         { .compatible = "fsl,eloplus-dma", },
1511         { .compatible = "fsl,elo-dma", },
1512         {}
1513 };
1514 MODULE_DEVICE_TABLE(of, fsldma_of_ids);
1515 
1516 static struct platform_driver fsldma_of_driver = {
1517         .driver = {
1518                 .name = "fsl-elo-dma",
1519                 .of_match_table = fsldma_of_ids,
1520 #ifdef CONFIG_PM
1521                 .pm = &fsldma_pm_ops,
1522 #endif
1523         },
1524         .probe = fsldma_of_probe,
1525         .remove = fsldma_of_remove,
1526 };
1527 
1528 /*----------------------------------------------------------------------------*/
1529 /* Module Init / Exit                                                         */
1530 /*----------------------------------------------------------------------------*/
1531 
1532 static __init int fsldma_init(void)
1533 {
1534         pr_info("Freescale Elo series DMA driver\n");
1535         return platform_driver_register(&fsldma_of_driver);
1536 }
1537 
1538 static void __exit fsldma_exit(void)
1539 {
1540         platform_driver_unregister(&fsldma_of_driver);
1541 }
1542 
1543 subsys_initcall(fsldma_init);
1544 module_exit(fsldma_exit);
1545 
1546 MODULE_DESCRIPTION("Freescale Elo series DMA driver");
1547 MODULE_LICENSE("GPL");
1548 

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