Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/dma/fsldma.c

  1 /*
  2  * Freescale MPC85xx, MPC83xx DMA Engine support
  3  *
  4  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  5  *
  6  * Author:
  7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
  8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
  9  *
 10  * Description:
 11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
 12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
 13  *   The support for MPC8349 DMA controller is also added.
 14  *
 15  * This driver instructs the DMA controller to issue the PCI Read Multiple
 16  * command for PCI read operations, instead of using the default PCI Read Line
 17  * command. Please be aware that this setting may result in read pre-fetching
 18  * on some platforms.
 19  *
 20  * This is free software; you can redistribute it and/or modify
 21  * it under the terms of the GNU General Public License as published by
 22  * the Free Software Foundation; either version 2 of the License, or
 23  * (at your option) any later version.
 24  *
 25  */
 26 
 27 #include <linux/init.h>
 28 #include <linux/module.h>
 29 #include <linux/pci.h>
 30 #include <linux/slab.h>
 31 #include <linux/interrupt.h>
 32 #include <linux/dmaengine.h>
 33 #include <linux/delay.h>
 34 #include <linux/dma-mapping.h>
 35 #include <linux/dmapool.h>
 36 #include <linux/of_address.h>
 37 #include <linux/of_irq.h>
 38 #include <linux/of_platform.h>
 39 #include <linux/fsldma.h>
 40 #include "dmaengine.h"
 41 #include "fsldma.h"
 42 
 43 #define chan_dbg(chan, fmt, arg...)                                     \
 44         dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
 45 #define chan_err(chan, fmt, arg...)                                     \
 46         dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
 47 
 48 static const char msg_ld_oom[] = "No free memory for link descriptor";
 49 
 50 /*
 51  * Register Helpers
 52  */
 53 
 54 static void set_sr(struct fsldma_chan *chan, u32 val)
 55 {
 56         DMA_OUT(chan, &chan->regs->sr, val, 32);
 57 }
 58 
 59 static u32 get_sr(struct fsldma_chan *chan)
 60 {
 61         return DMA_IN(chan, &chan->regs->sr, 32);
 62 }
 63 
 64 static void set_mr(struct fsldma_chan *chan, u32 val)
 65 {
 66         DMA_OUT(chan, &chan->regs->mr, val, 32);
 67 }
 68 
 69 static u32 get_mr(struct fsldma_chan *chan)
 70 {
 71         return DMA_IN(chan, &chan->regs->mr, 32);
 72 }
 73 
 74 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
 75 {
 76         DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
 77 }
 78 
 79 static dma_addr_t get_cdar(struct fsldma_chan *chan)
 80 {
 81         return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
 82 }
 83 
 84 static void set_bcr(struct fsldma_chan *chan, u32 val)
 85 {
 86         DMA_OUT(chan, &chan->regs->bcr, val, 32);
 87 }
 88 
 89 static u32 get_bcr(struct fsldma_chan *chan)
 90 {
 91         return DMA_IN(chan, &chan->regs->bcr, 32);
 92 }
 93 
 94 /*
 95  * Descriptor Helpers
 96  */
 97 
 98 static void set_desc_cnt(struct fsldma_chan *chan,
 99                                 struct fsl_dma_ld_hw *hw, u32 count)
100 {
101         hw->count = CPU_TO_DMA(chan, count, 32);
102 }
103 
104 static void set_desc_src(struct fsldma_chan *chan,
105                          struct fsl_dma_ld_hw *hw, dma_addr_t src)
106 {
107         u64 snoop_bits;
108 
109         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111         hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
112 }
113 
114 static void set_desc_dst(struct fsldma_chan *chan,
115                          struct fsl_dma_ld_hw *hw, dma_addr_t dst)
116 {
117         u64 snoop_bits;
118 
119         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121         hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122 }
123 
124 static void set_desc_next(struct fsldma_chan *chan,
125                           struct fsl_dma_ld_hw *hw, dma_addr_t next)
126 {
127         u64 snoop_bits;
128 
129         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130                 ? FSL_DMA_SNEN : 0;
131         hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132 }
133 
134 static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
135 {
136         u64 snoop_bits;
137 
138         snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
139                 ? FSL_DMA_SNEN : 0;
140 
141         desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142                 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
143                         | snoop_bits, 64);
144 }
145 
146 /*
147  * DMA Engine Hardware Control Helpers
148  */
149 
150 static void dma_init(struct fsldma_chan *chan)
151 {
152         /* Reset the channel */
153         set_mr(chan, 0);
154 
155         switch (chan->feature & FSL_DMA_IP_MASK) {
156         case FSL_DMA_IP_85XX:
157                 /* Set the channel to below modes:
158                  * EIE - Error interrupt enable
159                  * EOLNIE - End of links interrupt enable
160                  * BWC - Bandwidth sharing among channels
161                  */
162                 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163                         | FSL_DMA_MR_EOLNIE);
164                 break;
165         case FSL_DMA_IP_83XX:
166                 /* Set the channel to below modes:
167                  * EOTIE - End-of-transfer interrupt enable
168                  * PRC_RM - PCI read multiple
169                  */
170                 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
171                 break;
172         }
173 }
174 
175 static int dma_is_idle(struct fsldma_chan *chan)
176 {
177         u32 sr = get_sr(chan);
178         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179 }
180 
181 /*
182  * Start the DMA controller
183  *
184  * Preconditions:
185  * - the CDAR register must point to the start descriptor
186  * - the MRn[CS] bit must be cleared
187  */
188 static void dma_start(struct fsldma_chan *chan)
189 {
190         u32 mode;
191 
192         mode = get_mr(chan);
193 
194         if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
195                 set_bcr(chan, 0);
196                 mode |= FSL_DMA_MR_EMP_EN;
197         } else {
198                 mode &= ~FSL_DMA_MR_EMP_EN;
199         }
200 
201         if (chan->feature & FSL_DMA_CHAN_START_EXT) {
202                 mode |= FSL_DMA_MR_EMS_EN;
203         } else {
204                 mode &= ~FSL_DMA_MR_EMS_EN;
205                 mode |= FSL_DMA_MR_CS;
206         }
207 
208         set_mr(chan, mode);
209 }
210 
211 static void dma_halt(struct fsldma_chan *chan)
212 {
213         u32 mode;
214         int i;
215 
216         /* read the mode register */
217         mode = get_mr(chan);
218 
219         /*
220          * The 85xx controller supports channel abort, which will stop
221          * the current transfer. On 83xx, this bit is the transfer error
222          * mask bit, which should not be changed.
223          */
224         if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225                 mode |= FSL_DMA_MR_CA;
226                 set_mr(chan, mode);
227 
228                 mode &= ~FSL_DMA_MR_CA;
229         }
230 
231         /* stop the DMA controller */
232         mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
233         set_mr(chan, mode);
234 
235         /* wait for the DMA controller to become idle */
236         for (i = 0; i < 100; i++) {
237                 if (dma_is_idle(chan))
238                         return;
239 
240                 udelay(10);
241         }
242 
243         if (!dma_is_idle(chan))
244                 chan_err(chan, "DMA halt timeout!\n");
245 }
246 
247 /**
248  * fsl_chan_set_src_loop_size - Set source address hold transfer size
249  * @chan : Freescale DMA channel
250  * @size     : Address loop size, 0 for disable loop
251  *
252  * The set source address hold transfer size. The source
253  * address hold or loop transfer size is when the DMA transfer
254  * data from source address (SA), if the loop size is 4, the DMA will
255  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256  * SA + 1 ... and so on.
257  */
258 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
259 {
260         u32 mode;
261 
262         mode = get_mr(chan);
263 
264         switch (size) {
265         case 0:
266                 mode &= ~FSL_DMA_MR_SAHE;
267                 break;
268         case 1:
269         case 2:
270         case 4:
271         case 8:
272                 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
273                 break;
274         }
275 
276         set_mr(chan, mode);
277 }
278 
279 /**
280  * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
281  * @chan : Freescale DMA channel
282  * @size     : Address loop size, 0 for disable loop
283  *
284  * The set destination address hold transfer size. The destination
285  * address hold or loop transfer size is when the DMA transfer
286  * data to destination address (TA), if the loop size is 4, the DMA will
287  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288  * TA + 1 ... and so on.
289  */
290 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
291 {
292         u32 mode;
293 
294         mode = get_mr(chan);
295 
296         switch (size) {
297         case 0:
298                 mode &= ~FSL_DMA_MR_DAHE;
299                 break;
300         case 1:
301         case 2:
302         case 4:
303         case 8:
304                 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
305                 break;
306         }
307 
308         set_mr(chan, mode);
309 }
310 
311 /**
312  * fsl_chan_set_request_count - Set DMA Request Count for external control
313  * @chan : Freescale DMA channel
314  * @size     : Number of bytes to transfer in a single request
315  *
316  * The Freescale DMA channel can be controlled by the external signal DREQ#.
317  * The DMA request count is how many bytes are allowed to transfer before
318  * pausing the channel, after which a new assertion of DREQ# resumes channel
319  * operation.
320  *
321  * A size of 0 disables external pause control. The maximum size is 1024.
322  */
323 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
324 {
325         u32 mode;
326 
327         BUG_ON(size > 1024);
328 
329         mode = get_mr(chan);
330         mode |= (__ilog2(size) << 24) & 0x0f000000;
331 
332         set_mr(chan, mode);
333 }
334 
335 /**
336  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
337  * @chan : Freescale DMA channel
338  * @enable   : 0 is disabled, 1 is enabled.
339  *
340  * The Freescale DMA channel can be controlled by the external signal DREQ#.
341  * The DMA Request Count feature should be used in addition to this feature
342  * to set the number of bytes to transfer before pausing the channel.
343  */
344 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
345 {
346         if (enable)
347                 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
348         else
349                 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
350 }
351 
352 /**
353  * fsl_chan_toggle_ext_start - Toggle channel external start status
354  * @chan : Freescale DMA channel
355  * @enable   : 0 is disabled, 1 is enabled.
356  *
357  * If enable the external start, the channel can be started by an
358  * external DMA start pin. So the dma_start() does not start the
359  * transfer immediately. The DMA channel will wait for the
360  * control pin asserted.
361  */
362 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
363 {
364         if (enable)
365                 chan->feature |= FSL_DMA_CHAN_START_EXT;
366         else
367                 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
368 }
369 
370 int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371 {
372         struct fsldma_chan *chan;
373 
374         if (!dchan)
375                 return -EINVAL;
376 
377         chan = to_fsl_chan(dchan);
378 
379         fsl_chan_toggle_ext_start(chan, enable);
380         return 0;
381 }
382 EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383 
384 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
385 {
386         struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387 
388         if (list_empty(&chan->ld_pending))
389                 goto out_splice;
390 
391         /*
392          * Add the hardware descriptor to the chain of hardware descriptors
393          * that already exists in memory.
394          *
395          * This will un-set the EOL bit of the existing transaction, and the
396          * last link in this transaction will become the EOL descriptor.
397          */
398         set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399 
400         /*
401          * Add the software descriptor and all children to the list
402          * of pending transactions
403          */
404 out_splice:
405         list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406 }
407 
408 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409 {
410         struct fsldma_chan *chan = to_fsl_chan(tx->chan);
411         struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412         struct fsl_desc_sw *child;
413         dma_cookie_t cookie = -EINVAL;
414 
415         spin_lock_bh(&chan->desc_lock);
416 
417 #ifdef CONFIG_PM
418         if (unlikely(chan->pm_state != RUNNING)) {
419                 chan_dbg(chan, "cannot submit due to suspend\n");
420                 spin_unlock_bh(&chan->desc_lock);
421                 return -1;
422         }
423 #endif
424 
425         /*
426          * assign cookies to all of the software descriptors
427          * that make up this transaction
428          */
429         list_for_each_entry(child, &desc->tx_list, node) {
430                 cookie = dma_cookie_assign(&child->async_tx);
431         }
432 
433         /* put this transaction onto the tail of the pending queue */
434         append_ld_queue(chan, desc);
435 
436         spin_unlock_bh(&chan->desc_lock);
437 
438         return cookie;
439 }
440 
441 /**
442  * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443  * @chan : Freescale DMA channel
444  * @desc: descriptor to be freed
445  */
446 static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447                 struct fsl_desc_sw *desc)
448 {
449         list_del(&desc->node);
450         chan_dbg(chan, "LD %p free\n", desc);
451         dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452 }
453 
454 /**
455  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
456  * @chan : Freescale DMA channel
457  *
458  * Return - The descriptor allocated. NULL for failed.
459  */
460 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
461 {
462         struct fsl_desc_sw *desc;
463         dma_addr_t pdesc;
464 
465         desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
466         if (!desc) {
467                 chan_dbg(chan, "out of memory for link descriptor\n");
468                 return NULL;
469         }
470 
471         memset(desc, 0, sizeof(*desc));
472         INIT_LIST_HEAD(&desc->tx_list);
473         dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
474         desc->async_tx.tx_submit = fsl_dma_tx_submit;
475         desc->async_tx.phys = pdesc;
476 
477         chan_dbg(chan, "LD %p allocated\n", desc);
478 
479         return desc;
480 }
481 
482 /**
483  * fsldma_clean_completed_descriptor - free all descriptors which
484  * has been completed and acked
485  * @chan: Freescale DMA channel
486  *
487  * This function is used on all completed and acked descriptors.
488  * All descriptors should only be freed in this function.
489  */
490 static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
491 {
492         struct fsl_desc_sw *desc, *_desc;
493 
494         /* Run the callback for each descriptor, in order */
495         list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
496                 if (async_tx_test_ack(&desc->async_tx))
497                         fsl_dma_free_descriptor(chan, desc);
498 }
499 
500 /**
501  * fsldma_run_tx_complete_actions - cleanup a single link descriptor
502  * @chan: Freescale DMA channel
503  * @desc: descriptor to cleanup and free
504  * @cookie: Freescale DMA transaction identifier
505  *
506  * This function is used on a descriptor which has been executed by the DMA
507  * controller. It will run any callbacks, submit any dependencies.
508  */
509 static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
510                 struct fsl_desc_sw *desc, dma_cookie_t cookie)
511 {
512         struct dma_async_tx_descriptor *txd = &desc->async_tx;
513         dma_cookie_t ret = cookie;
514 
515         BUG_ON(txd->cookie < 0);
516 
517         if (txd->cookie > 0) {
518                 ret = txd->cookie;
519 
520                 /* Run the link descriptor callback function */
521                 if (txd->callback) {
522                         chan_dbg(chan, "LD %p callback\n", desc);
523                         txd->callback(txd->callback_param);
524                 }
525         }
526 
527         /* Run any dependencies */
528         dma_run_dependencies(txd);
529 
530         return ret;
531 }
532 
533 /**
534  * fsldma_clean_running_descriptor - move the completed descriptor from
535  * ld_running to ld_completed
536  * @chan: Freescale DMA channel
537  * @desc: the descriptor which is completed
538  *
539  * Free the descriptor directly if acked by async_tx api, or move it to
540  * queue ld_completed.
541  */
542 static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
543                 struct fsl_desc_sw *desc)
544 {
545         /* Remove from the list of transactions */
546         list_del(&desc->node);
547 
548         /*
549          * the client is allowed to attach dependent operations
550          * until 'ack' is set
551          */
552         if (!async_tx_test_ack(&desc->async_tx)) {
553                 /*
554                  * Move this descriptor to the list of descriptors which is
555                  * completed, but still awaiting the 'ack' bit to be set.
556                  */
557                 list_add_tail(&desc->node, &chan->ld_completed);
558                 return;
559         }
560 
561         dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
562 }
563 
564 /**
565  * fsl_chan_xfer_ld_queue - transfer any pending transactions
566  * @chan : Freescale DMA channel
567  *
568  * HARDWARE STATE: idle
569  * LOCKING: must hold chan->desc_lock
570  */
571 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
572 {
573         struct fsl_desc_sw *desc;
574 
575         /*
576          * If the list of pending descriptors is empty, then we
577          * don't need to do any work at all
578          */
579         if (list_empty(&chan->ld_pending)) {
580                 chan_dbg(chan, "no pending LDs\n");
581                 return;
582         }
583 
584         /*
585          * The DMA controller is not idle, which means that the interrupt
586          * handler will start any queued transactions when it runs after
587          * this transaction finishes
588          */
589         if (!chan->idle) {
590                 chan_dbg(chan, "DMA controller still busy\n");
591                 return;
592         }
593 
594         /*
595          * If there are some link descriptors which have not been
596          * transferred, we need to start the controller
597          */
598 
599         /*
600          * Move all elements from the queue of pending transactions
601          * onto the list of running transactions
602          */
603         chan_dbg(chan, "idle, starting controller\n");
604         desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
605         list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
606 
607         /*
608          * The 85xx DMA controller doesn't clear the channel start bit
609          * automatically at the end of a transfer. Therefore we must clear
610          * it in software before starting the transfer.
611          */
612         if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
613                 u32 mode;
614 
615                 mode = get_mr(chan);
616                 mode &= ~FSL_DMA_MR_CS;
617                 set_mr(chan, mode);
618         }
619 
620         /*
621          * Program the descriptor's address into the DMA controller,
622          * then start the DMA transaction
623          */
624         set_cdar(chan, desc->async_tx.phys);
625         get_cdar(chan);
626 
627         dma_start(chan);
628         chan->idle = false;
629 }
630 
631 /**
632  * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
633  * and move them to ld_completed to free until flag 'ack' is set
634  * @chan: Freescale DMA channel
635  *
636  * This function is used on descriptors which have been executed by the DMA
637  * controller. It will run any callbacks, submit any dependencies, then
638  * free these descriptors if flag 'ack' is set.
639  */
640 static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
641 {
642         struct fsl_desc_sw *desc, *_desc;
643         dma_cookie_t cookie = 0;
644         dma_addr_t curr_phys = get_cdar(chan);
645         int seen_current = 0;
646 
647         fsldma_clean_completed_descriptor(chan);
648 
649         /* Run the callback for each descriptor, in order */
650         list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
651                 /*
652                  * do not advance past the current descriptor loaded into the
653                  * hardware channel, subsequent descriptors are either in
654                  * process or have not been submitted
655                  */
656                 if (seen_current)
657                         break;
658 
659                 /*
660                  * stop the search if we reach the current descriptor and the
661                  * channel is busy
662                  */
663                 if (desc->async_tx.phys == curr_phys) {
664                         seen_current = 1;
665                         if (!dma_is_idle(chan))
666                                 break;
667                 }
668 
669                 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
670 
671                 fsldma_clean_running_descriptor(chan, desc);
672         }
673 
674         /*
675          * Start any pending transactions automatically
676          *
677          * In the ideal case, we keep the DMA controller busy while we go
678          * ahead and free the descriptors below.
679          */
680         fsl_chan_xfer_ld_queue(chan);
681 
682         if (cookie > 0)
683                 chan->common.completed_cookie = cookie;
684 }
685 
686 /**
687  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
688  * @chan : Freescale DMA channel
689  *
690  * This function will create a dma pool for descriptor allocation.
691  *
692  * Return - The number of descriptors allocated.
693  */
694 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
695 {
696         struct fsldma_chan *chan = to_fsl_chan(dchan);
697 
698         /* Has this channel already been allocated? */
699         if (chan->desc_pool)
700                 return 1;
701 
702         /*
703          * We need the descriptor to be aligned to 32bytes
704          * for meeting FSL DMA specification requirement.
705          */
706         chan->desc_pool = dma_pool_create(chan->name, chan->dev,
707                                           sizeof(struct fsl_desc_sw),
708                                           __alignof__(struct fsl_desc_sw), 0);
709         if (!chan->desc_pool) {
710                 chan_err(chan, "unable to allocate descriptor pool\n");
711                 return -ENOMEM;
712         }
713 
714         /* there is at least one descriptor free to be allocated */
715         return 1;
716 }
717 
718 /**
719  * fsldma_free_desc_list - Free all descriptors in a queue
720  * @chan: Freescae DMA channel
721  * @list: the list to free
722  *
723  * LOCKING: must hold chan->desc_lock
724  */
725 static void fsldma_free_desc_list(struct fsldma_chan *chan,
726                                   struct list_head *list)
727 {
728         struct fsl_desc_sw *desc, *_desc;
729 
730         list_for_each_entry_safe(desc, _desc, list, node)
731                 fsl_dma_free_descriptor(chan, desc);
732 }
733 
734 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
735                                           struct list_head *list)
736 {
737         struct fsl_desc_sw *desc, *_desc;
738 
739         list_for_each_entry_safe_reverse(desc, _desc, list, node)
740                 fsl_dma_free_descriptor(chan, desc);
741 }
742 
743 /**
744  * fsl_dma_free_chan_resources - Free all resources of the channel.
745  * @chan : Freescale DMA channel
746  */
747 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
748 {
749         struct fsldma_chan *chan = to_fsl_chan(dchan);
750 
751         chan_dbg(chan, "free all channel resources\n");
752         spin_lock_bh(&chan->desc_lock);
753         fsldma_cleanup_descriptors(chan);
754         fsldma_free_desc_list(chan, &chan->ld_pending);
755         fsldma_free_desc_list(chan, &chan->ld_running);
756         fsldma_free_desc_list(chan, &chan->ld_completed);
757         spin_unlock_bh(&chan->desc_lock);
758 
759         dma_pool_destroy(chan->desc_pool);
760         chan->desc_pool = NULL;
761 }
762 
763 static struct dma_async_tx_descriptor *
764 fsl_dma_prep_memcpy(struct dma_chan *dchan,
765         dma_addr_t dma_dst, dma_addr_t dma_src,
766         size_t len, unsigned long flags)
767 {
768         struct fsldma_chan *chan;
769         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
770         size_t copy;
771 
772         if (!dchan)
773                 return NULL;
774 
775         if (!len)
776                 return NULL;
777 
778         chan = to_fsl_chan(dchan);
779 
780         do {
781 
782                 /* Allocate the link descriptor from DMA pool */
783                 new = fsl_dma_alloc_descriptor(chan);
784                 if (!new) {
785                         chan_err(chan, "%s\n", msg_ld_oom);
786                         goto fail;
787                 }
788 
789                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
790 
791                 set_desc_cnt(chan, &new->hw, copy);
792                 set_desc_src(chan, &new->hw, dma_src);
793                 set_desc_dst(chan, &new->hw, dma_dst);
794 
795                 if (!first)
796                         first = new;
797                 else
798                         set_desc_next(chan, &prev->hw, new->async_tx.phys);
799 
800                 new->async_tx.cookie = 0;
801                 async_tx_ack(&new->async_tx);
802 
803                 prev = new;
804                 len -= copy;
805                 dma_src += copy;
806                 dma_dst += copy;
807 
808                 /* Insert the link descriptor to the LD ring */
809                 list_add_tail(&new->node, &first->tx_list);
810         } while (len);
811 
812         new->async_tx.flags = flags; /* client is in control of this ack */
813         new->async_tx.cookie = -EBUSY;
814 
815         /* Set End-of-link to the last link descriptor of new list */
816         set_ld_eol(chan, new);
817 
818         return &first->async_tx;
819 
820 fail:
821         if (!first)
822                 return NULL;
823 
824         fsldma_free_desc_list_reverse(chan, &first->tx_list);
825         return NULL;
826 }
827 
828 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
829         struct scatterlist *dst_sg, unsigned int dst_nents,
830         struct scatterlist *src_sg, unsigned int src_nents,
831         unsigned long flags)
832 {
833         struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
834         struct fsldma_chan *chan = to_fsl_chan(dchan);
835         size_t dst_avail, src_avail;
836         dma_addr_t dst, src;
837         size_t len;
838 
839         /* basic sanity checks */
840         if (dst_nents == 0 || src_nents == 0)
841                 return NULL;
842 
843         if (dst_sg == NULL || src_sg == NULL)
844                 return NULL;
845 
846         /*
847          * TODO: should we check that both scatterlists have the same
848          * TODO: number of bytes in total? Is that really an error?
849          */
850 
851         /* get prepared for the loop */
852         dst_avail = sg_dma_len(dst_sg);
853         src_avail = sg_dma_len(src_sg);
854 
855         /* run until we are out of scatterlist entries */
856         while (true) {
857 
858                 /* create the largest transaction possible */
859                 len = min_t(size_t, src_avail, dst_avail);
860                 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
861                 if (len == 0)
862                         goto fetch;
863 
864                 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
865                 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
866 
867                 /* allocate and populate the descriptor */
868                 new = fsl_dma_alloc_descriptor(chan);
869                 if (!new) {
870                         chan_err(chan, "%s\n", msg_ld_oom);
871                         goto fail;
872                 }
873 
874                 set_desc_cnt(chan, &new->hw, len);
875                 set_desc_src(chan, &new->hw, src);
876                 set_desc_dst(chan, &new->hw, dst);
877 
878                 if (!first)
879                         first = new;
880                 else
881                         set_desc_next(chan, &prev->hw, new->async_tx.phys);
882 
883                 new->async_tx.cookie = 0;
884                 async_tx_ack(&new->async_tx);
885                 prev = new;
886 
887                 /* Insert the link descriptor to the LD ring */
888                 list_add_tail(&new->node, &first->tx_list);
889 
890                 /* update metadata */
891                 dst_avail -= len;
892                 src_avail -= len;
893 
894 fetch:
895                 /* fetch the next dst scatterlist entry */
896                 if (dst_avail == 0) {
897 
898                         /* no more entries: we're done */
899                         if (dst_nents == 0)
900                                 break;
901 
902                         /* fetch the next entry: if there are no more: done */
903                         dst_sg = sg_next(dst_sg);
904                         if (dst_sg == NULL)
905                                 break;
906 
907                         dst_nents--;
908                         dst_avail = sg_dma_len(dst_sg);
909                 }
910 
911                 /* fetch the next src scatterlist entry */
912                 if (src_avail == 0) {
913 
914                         /* no more entries: we're done */
915                         if (src_nents == 0)
916                                 break;
917 
918                         /* fetch the next entry: if there are no more: done */
919                         src_sg = sg_next(src_sg);
920                         if (src_sg == NULL)
921                                 break;
922 
923                         src_nents--;
924                         src_avail = sg_dma_len(src_sg);
925                 }
926         }
927 
928         new->async_tx.flags = flags; /* client is in control of this ack */
929         new->async_tx.cookie = -EBUSY;
930 
931         /* Set End-of-link to the last link descriptor of new list */
932         set_ld_eol(chan, new);
933 
934         return &first->async_tx;
935 
936 fail:
937         if (!first)
938                 return NULL;
939 
940         fsldma_free_desc_list_reverse(chan, &first->tx_list);
941         return NULL;
942 }
943 
944 /**
945  * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
946  * @chan: DMA channel
947  * @sgl: scatterlist to transfer to/from
948  * @sg_len: number of entries in @scatterlist
949  * @direction: DMA direction
950  * @flags: DMAEngine flags
951  * @context: transaction context (ignored)
952  *
953  * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
954  * DMA_SLAVE API, this gets the device-specific information from the
955  * chan->private variable.
956  */
957 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
958         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
959         enum dma_transfer_direction direction, unsigned long flags,
960         void *context)
961 {
962         /*
963          * This operation is not supported on the Freescale DMA controller
964          *
965          * However, we need to provide the function pointer to allow the
966          * device_control() method to work.
967          */
968         return NULL;
969 }
970 
971 static int fsl_dma_device_control(struct dma_chan *dchan,
972                                   enum dma_ctrl_cmd cmd, unsigned long arg)
973 {
974         struct dma_slave_config *config;
975         struct fsldma_chan *chan;
976         int size;
977 
978         if (!dchan)
979                 return -EINVAL;
980 
981         chan = to_fsl_chan(dchan);
982 
983         switch (cmd) {
984         case DMA_TERMINATE_ALL:
985                 spin_lock_bh(&chan->desc_lock);
986 
987                 /* Halt the DMA engine */
988                 dma_halt(chan);
989 
990                 /* Remove and free all of the descriptors in the LD queue */
991                 fsldma_free_desc_list(chan, &chan->ld_pending);
992                 fsldma_free_desc_list(chan, &chan->ld_running);
993                 fsldma_free_desc_list(chan, &chan->ld_completed);
994                 chan->idle = true;
995 
996                 spin_unlock_bh(&chan->desc_lock);
997                 return 0;
998 
999         case DMA_SLAVE_CONFIG:
1000                 config = (struct dma_slave_config *)arg;
1001 
1002                 /* make sure the channel supports setting burst size */
1003                 if (!chan->set_request_count)
1004                         return -ENXIO;
1005 
1006                 /* we set the controller burst size depending on direction */
1007                 if (config->direction == DMA_MEM_TO_DEV)
1008                         size = config->dst_addr_width * config->dst_maxburst;
1009                 else
1010                         size = config->src_addr_width * config->src_maxburst;
1011 
1012                 chan->set_request_count(chan, size);
1013                 return 0;
1014 
1015         default:
1016                 return -ENXIO;
1017         }
1018 
1019         return 0;
1020 }
1021 
1022 /**
1023  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
1024  * @chan : Freescale DMA channel
1025  */
1026 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
1027 {
1028         struct fsldma_chan *chan = to_fsl_chan(dchan);
1029 
1030         spin_lock_bh(&chan->desc_lock);
1031         fsl_chan_xfer_ld_queue(chan);
1032         spin_unlock_bh(&chan->desc_lock);
1033 }
1034 
1035 /**
1036  * fsl_tx_status - Determine the DMA status
1037  * @chan : Freescale DMA channel
1038  */
1039 static enum dma_status fsl_tx_status(struct dma_chan *dchan,
1040                                         dma_cookie_t cookie,
1041                                         struct dma_tx_state *txstate)
1042 {
1043         struct fsldma_chan *chan = to_fsl_chan(dchan);
1044         enum dma_status ret;
1045 
1046         ret = dma_cookie_status(dchan, cookie, txstate);
1047         if (ret == DMA_COMPLETE)
1048                 return ret;
1049 
1050         spin_lock_bh(&chan->desc_lock);
1051         fsldma_cleanup_descriptors(chan);
1052         spin_unlock_bh(&chan->desc_lock);
1053 
1054         return dma_cookie_status(dchan, cookie, txstate);
1055 }
1056 
1057 /*----------------------------------------------------------------------------*/
1058 /* Interrupt Handling                                                         */
1059 /*----------------------------------------------------------------------------*/
1060 
1061 static irqreturn_t fsldma_chan_irq(int irq, void *data)
1062 {
1063         struct fsldma_chan *chan = data;
1064         u32 stat;
1065 
1066         /* save and clear the status register */
1067         stat = get_sr(chan);
1068         set_sr(chan, stat);
1069         chan_dbg(chan, "irq: stat = 0x%x\n", stat);
1070 
1071         /* check that this was really our device */
1072         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1073         if (!stat)
1074                 return IRQ_NONE;
1075 
1076         if (stat & FSL_DMA_SR_TE)
1077                 chan_err(chan, "Transfer Error!\n");
1078 
1079         /*
1080          * Programming Error
1081          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1082          * trigger a PE interrupt.
1083          */
1084         if (stat & FSL_DMA_SR_PE) {
1085                 chan_dbg(chan, "irq: Programming Error INT\n");
1086                 stat &= ~FSL_DMA_SR_PE;
1087                 if (get_bcr(chan) != 0)
1088                         chan_err(chan, "Programming Error!\n");
1089         }
1090 
1091         /*
1092          * For MPC8349, EOCDI event need to update cookie
1093          * and start the next transfer if it exist.
1094          */
1095         if (stat & FSL_DMA_SR_EOCDI) {
1096                 chan_dbg(chan, "irq: End-of-Chain link INT\n");
1097                 stat &= ~FSL_DMA_SR_EOCDI;
1098         }
1099 
1100         /*
1101          * If it current transfer is the end-of-transfer,
1102          * we should clear the Channel Start bit for
1103          * prepare next transfer.
1104          */
1105         if (stat & FSL_DMA_SR_EOLNI) {
1106                 chan_dbg(chan, "irq: End-of-link INT\n");
1107                 stat &= ~FSL_DMA_SR_EOLNI;
1108         }
1109 
1110         /* check that the DMA controller is really idle */
1111         if (!dma_is_idle(chan))
1112                 chan_err(chan, "irq: controller not idle!\n");
1113 
1114         /* check that we handled all of the bits */
1115         if (stat)
1116                 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1117 
1118         /*
1119          * Schedule the tasklet to handle all cleanup of the current
1120          * transaction. It will start a new transaction if there is
1121          * one pending.
1122          */
1123         tasklet_schedule(&chan->tasklet);
1124         chan_dbg(chan, "irq: Exit\n");
1125         return IRQ_HANDLED;
1126 }
1127 
1128 static void dma_do_tasklet(unsigned long data)
1129 {
1130         struct fsldma_chan *chan = (struct fsldma_chan *)data;
1131 
1132         chan_dbg(chan, "tasklet entry\n");
1133 
1134         spin_lock_bh(&chan->desc_lock);
1135 
1136         /* the hardware is now idle and ready for more */
1137         chan->idle = true;
1138 
1139         /* Run all cleanup for descriptors which have been completed */
1140         fsldma_cleanup_descriptors(chan);
1141 
1142         spin_unlock_bh(&chan->desc_lock);
1143 
1144         chan_dbg(chan, "tasklet exit\n");
1145 }
1146 
1147 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1148 {
1149         struct fsldma_device *fdev = data;
1150         struct fsldma_chan *chan;
1151         unsigned int handled = 0;
1152         u32 gsr, mask;
1153         int i;
1154 
1155         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1156                                                    : in_le32(fdev->regs);
1157         mask = 0xff000000;
1158         dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1159 
1160         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1161                 chan = fdev->chan[i];
1162                 if (!chan)
1163                         continue;
1164 
1165                 if (gsr & mask) {
1166                         dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1167                         fsldma_chan_irq(irq, chan);
1168                         handled++;
1169                 }
1170 
1171                 gsr &= ~mask;
1172                 mask >>= 8;
1173         }
1174 
1175         return IRQ_RETVAL(handled);
1176 }
1177 
1178 static void fsldma_free_irqs(struct fsldma_device *fdev)
1179 {
1180         struct fsldma_chan *chan;
1181         int i;
1182 
1183         if (fdev->irq != NO_IRQ) {
1184                 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1185                 free_irq(fdev->irq, fdev);
1186                 return;
1187         }
1188 
1189         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1190                 chan = fdev->chan[i];
1191                 if (chan && chan->irq != NO_IRQ) {
1192                         chan_dbg(chan, "free per-channel IRQ\n");
1193                         free_irq(chan->irq, chan);
1194                 }
1195         }
1196 }
1197 
1198 static int fsldma_request_irqs(struct fsldma_device *fdev)
1199 {
1200         struct fsldma_chan *chan;
1201         int ret;
1202         int i;
1203 
1204         /* if we have a per-controller IRQ, use that */
1205         if (fdev->irq != NO_IRQ) {
1206                 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1207                 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1208                                   "fsldma-controller", fdev);
1209                 return ret;
1210         }
1211 
1212         /* no per-controller IRQ, use the per-channel IRQs */
1213         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1214                 chan = fdev->chan[i];
1215                 if (!chan)
1216                         continue;
1217 
1218                 if (chan->irq == NO_IRQ) {
1219                         chan_err(chan, "interrupts property missing in device tree\n");
1220                         ret = -ENODEV;
1221                         goto out_unwind;
1222                 }
1223 
1224                 chan_dbg(chan, "request per-channel IRQ\n");
1225                 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1226                                   "fsldma-chan", chan);
1227                 if (ret) {
1228                         chan_err(chan, "unable to request per-channel IRQ\n");
1229                         goto out_unwind;
1230                 }
1231         }
1232 
1233         return 0;
1234 
1235 out_unwind:
1236         for (/* none */; i >= 0; i--) {
1237                 chan = fdev->chan[i];
1238                 if (!chan)
1239                         continue;
1240 
1241                 if (chan->irq == NO_IRQ)
1242                         continue;
1243 
1244                 free_irq(chan->irq, chan);
1245         }
1246 
1247         return ret;
1248 }
1249 
1250 /*----------------------------------------------------------------------------*/
1251 /* OpenFirmware Subsystem                                                     */
1252 /*----------------------------------------------------------------------------*/
1253 
1254 static int fsl_dma_chan_probe(struct fsldma_device *fdev,
1255         struct device_node *node, u32 feature, const char *compatible)
1256 {
1257         struct fsldma_chan *chan;
1258         struct resource res;
1259         int err;
1260 
1261         /* alloc channel */
1262         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1263         if (!chan) {
1264                 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1265                 err = -ENOMEM;
1266                 goto out_return;
1267         }
1268 
1269         /* ioremap registers for use */
1270         chan->regs = of_iomap(node, 0);
1271         if (!chan->regs) {
1272                 dev_err(fdev->dev, "unable to ioremap registers\n");
1273                 err = -ENOMEM;
1274                 goto out_free_chan;
1275         }
1276 
1277         err = of_address_to_resource(node, 0, &res);
1278         if (err) {
1279                 dev_err(fdev->dev, "unable to find 'reg' property\n");
1280                 goto out_iounmap_regs;
1281         }
1282 
1283         chan->feature = feature;
1284         if (!fdev->feature)
1285                 fdev->feature = chan->feature;
1286 
1287         /*
1288          * If the DMA device's feature is different than the feature
1289          * of its channels, report the bug
1290          */
1291         WARN_ON(fdev->feature != chan->feature);
1292 
1293         chan->dev = fdev->dev;
1294         chan->id = (res.start & 0xfff) < 0x300 ?
1295                    ((res.start - 0x100) & 0xfff) >> 7 :
1296                    ((res.start - 0x200) & 0xfff) >> 7;
1297         if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1298                 dev_err(fdev->dev, "too many channels for device\n");
1299                 err = -EINVAL;
1300                 goto out_iounmap_regs;
1301         }
1302 
1303         fdev->chan[chan->id] = chan;
1304         tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1305         snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1306 
1307         /* Initialize the channel */
1308         dma_init(chan);
1309 
1310         /* Clear cdar registers */
1311         set_cdar(chan, 0);
1312 
1313         switch (chan->feature & FSL_DMA_IP_MASK) {
1314         case FSL_DMA_IP_85XX:
1315                 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1316         case FSL_DMA_IP_83XX:
1317                 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1318                 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1319                 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1320                 chan->set_request_count = fsl_chan_set_request_count;
1321         }
1322 
1323         spin_lock_init(&chan->desc_lock);
1324         INIT_LIST_HEAD(&chan->ld_pending);
1325         INIT_LIST_HEAD(&chan->ld_running);
1326         INIT_LIST_HEAD(&chan->ld_completed);
1327         chan->idle = true;
1328 #ifdef CONFIG_PM
1329         chan->pm_state = RUNNING;
1330 #endif
1331 
1332         chan->common.device = &fdev->common;
1333         dma_cookie_init(&chan->common);
1334 
1335         /* find the IRQ line, if it exists in the device tree */
1336         chan->irq = irq_of_parse_and_map(node, 0);
1337 
1338         /* Add the channel to DMA device channel list */
1339         list_add_tail(&chan->common.device_node, &fdev->common.channels);
1340         fdev->common.chancnt++;
1341 
1342         dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1343                  chan->irq != NO_IRQ ? chan->irq : fdev->irq);
1344 
1345         return 0;
1346 
1347 out_iounmap_regs:
1348         iounmap(chan->regs);
1349 out_free_chan:
1350         kfree(chan);
1351 out_return:
1352         return err;
1353 }
1354 
1355 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1356 {
1357         irq_dispose_mapping(chan->irq);
1358         list_del(&chan->common.device_node);
1359         iounmap(chan->regs);
1360         kfree(chan);
1361 }
1362 
1363 static int fsldma_of_probe(struct platform_device *op)
1364 {
1365         struct fsldma_device *fdev;
1366         struct device_node *child;
1367         int err;
1368 
1369         fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1370         if (!fdev) {
1371                 dev_err(&op->dev, "No enough memory for 'priv'\n");
1372                 err = -ENOMEM;
1373                 goto out_return;
1374         }
1375 
1376         fdev->dev = &op->dev;
1377         INIT_LIST_HEAD(&fdev->common.channels);
1378 
1379         /* ioremap the registers for use */
1380         fdev->regs = of_iomap(op->dev.of_node, 0);
1381         if (!fdev->regs) {
1382                 dev_err(&op->dev, "unable to ioremap registers\n");
1383                 err = -ENOMEM;
1384                 goto out_free_fdev;
1385         }
1386 
1387         /* map the channel IRQ if it exists, but don't hookup the handler yet */
1388         fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1389 
1390         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1391         dma_cap_set(DMA_SG, fdev->common.cap_mask);
1392         dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1393         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1394         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1395         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1396         fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
1397         fdev->common.device_tx_status = fsl_tx_status;
1398         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1399         fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
1400         fdev->common.device_control = fsl_dma_device_control;
1401         fdev->common.dev = &op->dev;
1402 
1403         dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1404 
1405         platform_set_drvdata(op, fdev);
1406 
1407         /*
1408          * We cannot use of_platform_bus_probe() because there is no
1409          * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1410          * channel object.
1411          */
1412         for_each_child_of_node(op->dev.of_node, child) {
1413                 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1414                         fsl_dma_chan_probe(fdev, child,
1415                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1416                                 "fsl,eloplus-dma-channel");
1417                 }
1418 
1419                 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1420                         fsl_dma_chan_probe(fdev, child,
1421                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1422                                 "fsl,elo-dma-channel");
1423                 }
1424         }
1425 
1426         /*
1427          * Hookup the IRQ handler(s)
1428          *
1429          * If we have a per-controller interrupt, we prefer that to the
1430          * per-channel interrupts to reduce the number of shared interrupt
1431          * handlers on the same IRQ line
1432          */
1433         err = fsldma_request_irqs(fdev);
1434         if (err) {
1435                 dev_err(fdev->dev, "unable to request IRQs\n");
1436                 goto out_free_fdev;
1437         }
1438 
1439         dma_async_device_register(&fdev->common);
1440         return 0;
1441 
1442 out_free_fdev:
1443         irq_dispose_mapping(fdev->irq);
1444         kfree(fdev);
1445 out_return:
1446         return err;
1447 }
1448 
1449 static int fsldma_of_remove(struct platform_device *op)
1450 {
1451         struct fsldma_device *fdev;
1452         unsigned int i;
1453 
1454         fdev = platform_get_drvdata(op);
1455         dma_async_device_unregister(&fdev->common);
1456 
1457         fsldma_free_irqs(fdev);
1458 
1459         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1460                 if (fdev->chan[i])
1461                         fsl_dma_chan_remove(fdev->chan[i]);
1462         }
1463 
1464         iounmap(fdev->regs);
1465         kfree(fdev);
1466 
1467         return 0;
1468 }
1469 
1470 #ifdef CONFIG_PM
1471 static int fsldma_suspend_late(struct device *dev)
1472 {
1473         struct platform_device *pdev = to_platform_device(dev);
1474         struct fsldma_device *fdev = platform_get_drvdata(pdev);
1475         struct fsldma_chan *chan;
1476         int i;
1477 
1478         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1479                 chan = fdev->chan[i];
1480                 if (!chan)
1481                         continue;
1482 
1483                 spin_lock_bh(&chan->desc_lock);
1484                 if (unlikely(!chan->idle))
1485                         goto out;
1486                 chan->regs_save.mr = get_mr(chan);
1487                 chan->pm_state = SUSPENDED;
1488                 spin_unlock_bh(&chan->desc_lock);
1489         }
1490         return 0;
1491 
1492 out:
1493         for (; i >= 0; i--) {
1494                 chan = fdev->chan[i];
1495                 if (!chan)
1496                         continue;
1497                 chan->pm_state = RUNNING;
1498                 spin_unlock_bh(&chan->desc_lock);
1499         }
1500         return -EBUSY;
1501 }
1502 
1503 static int fsldma_resume_early(struct device *dev)
1504 {
1505         struct platform_device *pdev = to_platform_device(dev);
1506         struct fsldma_device *fdev = platform_get_drvdata(pdev);
1507         struct fsldma_chan *chan;
1508         u32 mode;
1509         int i;
1510 
1511         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1512                 chan = fdev->chan[i];
1513                 if (!chan)
1514                         continue;
1515 
1516                 spin_lock_bh(&chan->desc_lock);
1517                 mode = chan->regs_save.mr
1518                         & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1519                 set_mr(chan, mode);
1520                 chan->pm_state = RUNNING;
1521                 spin_unlock_bh(&chan->desc_lock);
1522         }
1523 
1524         return 0;
1525 }
1526 
1527 static const struct dev_pm_ops fsldma_pm_ops = {
1528         .suspend_late   = fsldma_suspend_late,
1529         .resume_early   = fsldma_resume_early,
1530 };
1531 #endif
1532 
1533 static const struct of_device_id fsldma_of_ids[] = {
1534         { .compatible = "fsl,elo3-dma", },
1535         { .compatible = "fsl,eloplus-dma", },
1536         { .compatible = "fsl,elo-dma", },
1537         {}
1538 };
1539 
1540 static struct platform_driver fsldma_of_driver = {
1541         .driver = {
1542                 .name = "fsl-elo-dma",
1543                 .owner = THIS_MODULE,
1544                 .of_match_table = fsldma_of_ids,
1545 #ifdef CONFIG_PM
1546                 .pm = &fsldma_pm_ops,
1547 #endif
1548         },
1549         .probe = fsldma_of_probe,
1550         .remove = fsldma_of_remove,
1551 };
1552 
1553 /*----------------------------------------------------------------------------*/
1554 /* Module Init / Exit                                                         */
1555 /*----------------------------------------------------------------------------*/
1556 
1557 static __init int fsldma_init(void)
1558 {
1559         pr_info("Freescale Elo series DMA driver\n");
1560         return platform_driver_register(&fsldma_of_driver);
1561 }
1562 
1563 static void __exit fsldma_exit(void)
1564 {
1565         platform_driver_unregister(&fsldma_of_driver);
1566 }
1567 
1568 subsys_initcall(fsldma_init);
1569 module_exit(fsldma_exit);
1570 
1571 MODULE_DESCRIPTION("Freescale Elo series DMA driver");
1572 MODULE_LICENSE("GPL");
1573 

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