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Linux/drivers/dma/edma.c

  1 /*
  2  * TI EDMA DMA engine driver
  3  *
  4  * Copyright 2012 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/dmaengine.h>
 17 #include <linux/dma-mapping.h>
 18 #include <linux/edma.h>
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/list.h>
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/of.h>
 28 #include <linux/of_dma.h>
 29 #include <linux/of_irq.h>
 30 #include <linux/of_address.h>
 31 #include <linux/of_device.h>
 32 #include <linux/pm_runtime.h>
 33 
 34 #include <linux/platform_data/edma.h>
 35 
 36 #include "dmaengine.h"
 37 #include "virt-dma.h"
 38 
 39 /* Offsets matching "struct edmacc_param" */
 40 #define PARM_OPT                0x00
 41 #define PARM_SRC                0x04
 42 #define PARM_A_B_CNT            0x08
 43 #define PARM_DST                0x0c
 44 #define PARM_SRC_DST_BIDX       0x10
 45 #define PARM_LINK_BCNTRLD       0x14
 46 #define PARM_SRC_DST_CIDX       0x18
 47 #define PARM_CCNT               0x1c
 48 
 49 #define PARM_SIZE               0x20
 50 
 51 /* Offsets for EDMA CC global channel registers and their shadows */
 52 #define SH_ER                   0x00    /* 64 bits */
 53 #define SH_ECR                  0x08    /* 64 bits */
 54 #define SH_ESR                  0x10    /* 64 bits */
 55 #define SH_CER                  0x18    /* 64 bits */
 56 #define SH_EER                  0x20    /* 64 bits */
 57 #define SH_EECR                 0x28    /* 64 bits */
 58 #define SH_EESR                 0x30    /* 64 bits */
 59 #define SH_SER                  0x38    /* 64 bits */
 60 #define SH_SECR                 0x40    /* 64 bits */
 61 #define SH_IER                  0x50    /* 64 bits */
 62 #define SH_IECR                 0x58    /* 64 bits */
 63 #define SH_IESR                 0x60    /* 64 bits */
 64 #define SH_IPR                  0x68    /* 64 bits */
 65 #define SH_ICR                  0x70    /* 64 bits */
 66 #define SH_IEVAL                0x78
 67 #define SH_QER                  0x80
 68 #define SH_QEER                 0x84
 69 #define SH_QEECR                0x88
 70 #define SH_QEESR                0x8c
 71 #define SH_QSER                 0x90
 72 #define SH_QSECR                0x94
 73 #define SH_SIZE                 0x200
 74 
 75 /* Offsets for EDMA CC global registers */
 76 #define EDMA_REV                0x0000
 77 #define EDMA_CCCFG              0x0004
 78 #define EDMA_QCHMAP             0x0200  /* 8 registers */
 79 #define EDMA_DMAQNUM            0x0240  /* 8 registers (4 on OMAP-L1xx) */
 80 #define EDMA_QDMAQNUM           0x0260
 81 #define EDMA_QUETCMAP           0x0280
 82 #define EDMA_QUEPRI             0x0284
 83 #define EDMA_EMR                0x0300  /* 64 bits */
 84 #define EDMA_EMCR               0x0308  /* 64 bits */
 85 #define EDMA_QEMR               0x0310
 86 #define EDMA_QEMCR              0x0314
 87 #define EDMA_CCERR              0x0318
 88 #define EDMA_CCERRCLR           0x031c
 89 #define EDMA_EEVAL              0x0320
 90 #define EDMA_DRAE               0x0340  /* 4 x 64 bits*/
 91 #define EDMA_QRAE               0x0380  /* 4 registers */
 92 #define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
 93 #define EDMA_QSTAT              0x0600  /* 2 registers */
 94 #define EDMA_QWMTHRA            0x0620
 95 #define EDMA_QWMTHRB            0x0624
 96 #define EDMA_CCSTAT             0x0640
 97 
 98 #define EDMA_M                  0x1000  /* global channel registers */
 99 #define EDMA_ECR                0x1008
100 #define EDMA_ECRH               0x100C
101 #define EDMA_SHADOW0            0x2000  /* 4 shadow regions */
102 #define EDMA_PARM               0x4000  /* PaRAM entries */
103 
104 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
105 
106 #define EDMA_DCHMAP             0x0100  /* 64 registers */
107 
108 /* CCCFG register */
109 #define GET_NUM_DMACH(x)        (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x)       ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x)      ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x)        ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x)         ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST             BIT(24)
115 
116 /* CCSTAT register */
117 #define EDMA_CCSTAT_ACTV        BIT(4)
118 
119 /*
120  * Max of 20 segments per channel to conserve PaRAM slots
121  * Also note that MAX_NR_SG should be atleast the no.of periods
122  * that are required for ASoC, otherwise DMA prep calls will
123  * fail. Today davinci-pcm is the only user of this driver and
124  * requires atleast 17 slots, so we setup the default to 20.
125  */
126 #define MAX_NR_SG               20
127 #define EDMA_MAX_SLOTS          MAX_NR_SG
128 #define EDMA_DESCRIPTORS        16
129 
130 #define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
131 #define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
132 #define EDMA_CONT_PARAMS_ANY             1001
133 #define EDMA_CONT_PARAMS_FIXED_EXACT     1002
134 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135 
136 /* PaRAM slots are laid out like this */
137 struct edmacc_param {
138         u32 opt;
139         u32 src;
140         u32 a_b_cnt;
141         u32 dst;
142         u32 src_dst_bidx;
143         u32 link_bcntrld;
144         u32 src_dst_cidx;
145         u32 ccnt;
146 } __packed;
147 
148 /* fields in edmacc_param.opt */
149 #define SAM             BIT(0)
150 #define DAM             BIT(1)
151 #define SYNCDIM         BIT(2)
152 #define STATIC          BIT(3)
153 #define EDMA_FWID       (0x07 << 8)
154 #define TCCMODE         BIT(11)
155 #define EDMA_TCC(t)     ((t) << 12)
156 #define TCINTEN         BIT(20)
157 #define ITCINTEN        BIT(21)
158 #define TCCHEN          BIT(22)
159 #define ITCCHEN         BIT(23)
160 
161 struct edma_pset {
162         u32                             len;
163         dma_addr_t                      addr;
164         struct edmacc_param             param;
165 };
166 
167 struct edma_desc {
168         struct virt_dma_desc            vdesc;
169         struct list_head                node;
170         enum dma_transfer_direction     direction;
171         int                             cyclic;
172         int                             absync;
173         int                             pset_nr;
174         struct edma_chan                *echan;
175         int                             processed;
176 
177         /*
178          * The following 4 elements are used for residue accounting.
179          *
180          * - processed_stat: the number of SG elements we have traversed
181          * so far to cover accounting. This is updated directly to processed
182          * during edma_callback and is always <= processed, because processed
183          * refers to the number of pending transfer (programmed to EDMA
184          * controller), where as processed_stat tracks number of transfers
185          * accounted for so far.
186          *
187          * - residue: The amount of bytes we have left to transfer for this desc
188          *
189          * - residue_stat: The residue in bytes of data we have covered
190          * so far for accounting. This is updated directly to residue
191          * during callbacks to keep it current.
192          *
193          * - sg_len: Tracks the length of the current intermediate transfer,
194          * this is required to update the residue during intermediate transfer
195          * completion callback.
196          */
197         int                             processed_stat;
198         u32                             sg_len;
199         u32                             residue;
200         u32                             residue_stat;
201 
202         struct edma_pset                pset[0];
203 };
204 
205 struct edma_cc;
206 
207 struct edma_tc {
208         struct device_node              *node;
209         u16                             id;
210 };
211 
212 struct edma_chan {
213         struct virt_dma_chan            vchan;
214         struct list_head                node;
215         struct edma_desc                *edesc;
216         struct edma_cc                  *ecc;
217         struct edma_tc                  *tc;
218         int                             ch_num;
219         bool                            alloced;
220         bool                            hw_triggered;
221         int                             slot[EDMA_MAX_SLOTS];
222         int                             missed;
223         struct dma_slave_config         cfg;
224 };
225 
226 struct edma_cc {
227         struct device                   *dev;
228         struct edma_soc_info            *info;
229         void __iomem                    *base;
230         int                             id;
231         bool                            legacy_mode;
232 
233         /* eDMA3 resource information */
234         unsigned                        num_channels;
235         unsigned                        num_qchannels;
236         unsigned                        num_region;
237         unsigned                        num_slots;
238         unsigned                        num_tc;
239         bool                            chmap_exist;
240         enum dma_event_q                default_queue;
241 
242         /*
243          * The slot_inuse bit for each PaRAM slot is clear unless the slot is
244          * in use by Linux or if it is allocated to be used by DSP.
245          */
246         unsigned long *slot_inuse;
247 
248         struct dma_device               dma_slave;
249         struct dma_device               *dma_memcpy;
250         struct edma_chan                *slave_chans;
251         struct edma_tc                  *tc_list;
252         int                             dummy_slot;
253 };
254 
255 /* dummy param set used to (re)initialize parameter RAM slots */
256 static const struct edmacc_param dummy_paramset = {
257         .link_bcntrld = 0xffff,
258         .ccnt = 1,
259 };
260 
261 #define EDMA_BINDING_LEGACY     0
262 #define EDMA_BINDING_TPCC       1
263 static const struct of_device_id edma_of_ids[] = {
264         {
265                 .compatible = "ti,edma3",
266                 .data = (void *)EDMA_BINDING_LEGACY,
267         },
268         {
269                 .compatible = "ti,edma3-tpcc",
270                 .data = (void *)EDMA_BINDING_TPCC,
271         },
272         {}
273 };
274 
275 static const struct of_device_id edma_tptc_of_ids[] = {
276         { .compatible = "ti,edma3-tptc", },
277         {}
278 };
279 
280 static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
281 {
282         return (unsigned int)__raw_readl(ecc->base + offset);
283 }
284 
285 static inline void edma_write(struct edma_cc *ecc, int offset, int val)
286 {
287         __raw_writel(val, ecc->base + offset);
288 }
289 
290 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
291                                unsigned or)
292 {
293         unsigned val = edma_read(ecc, offset);
294 
295         val &= and;
296         val |= or;
297         edma_write(ecc, offset, val);
298 }
299 
300 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
301 {
302         unsigned val = edma_read(ecc, offset);
303 
304         val &= and;
305         edma_write(ecc, offset, val);
306 }
307 
308 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
309 {
310         unsigned val = edma_read(ecc, offset);
311 
312         val |= or;
313         edma_write(ecc, offset, val);
314 }
315 
316 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
317                                            int i)
318 {
319         return edma_read(ecc, offset + (i << 2));
320 }
321 
322 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
323                                     unsigned val)
324 {
325         edma_write(ecc, offset + (i << 2), val);
326 }
327 
328 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
329                                      unsigned and, unsigned or)
330 {
331         edma_modify(ecc, offset + (i << 2), and, or);
332 }
333 
334 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
335                                  unsigned or)
336 {
337         edma_or(ecc, offset + (i << 2), or);
338 }
339 
340 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
341                                   unsigned or)
342 {
343         edma_or(ecc, offset + ((i * 2 + j) << 2), or);
344 }
345 
346 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
347                                      int j, unsigned val)
348 {
349         edma_write(ecc, offset + ((i * 2 + j) << 2), val);
350 }
351 
352 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
353 {
354         return edma_read(ecc, EDMA_SHADOW0 + offset);
355 }
356 
357 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
358                                                    int offset, int i)
359 {
360         return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
361 }
362 
363 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
364                                       unsigned val)
365 {
366         edma_write(ecc, EDMA_SHADOW0 + offset, val);
367 }
368 
369 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
370                                             int i, unsigned val)
371 {
372         edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
373 }
374 
375 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
376                                            int param_no)
377 {
378         return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
379 }
380 
381 static inline void edma_param_write(struct edma_cc *ecc, int offset,
382                                     int param_no, unsigned val)
383 {
384         edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
385 }
386 
387 static inline void edma_param_modify(struct edma_cc *ecc, int offset,
388                                      int param_no, unsigned and, unsigned or)
389 {
390         edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
391 }
392 
393 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
394                                   unsigned and)
395 {
396         edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
397 }
398 
399 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
400                                  unsigned or)
401 {
402         edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
403 }
404 
405 static inline void set_bits(int offset, int len, unsigned long *p)
406 {
407         for (; len > 0; len--)
408                 set_bit(offset + (len - 1), p);
409 }
410 
411 static inline void clear_bits(int offset, int len, unsigned long *p)
412 {
413         for (; len > 0; len--)
414                 clear_bit(offset + (len - 1), p);
415 }
416 
417 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
418                                           int priority)
419 {
420         int bit = queue_no * 4;
421 
422         edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
423 }
424 
425 static void edma_set_chmap(struct edma_chan *echan, int slot)
426 {
427         struct edma_cc *ecc = echan->ecc;
428         int channel = EDMA_CHAN_SLOT(echan->ch_num);
429 
430         if (ecc->chmap_exist) {
431                 slot = EDMA_CHAN_SLOT(slot);
432                 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
433         }
434 }
435 
436 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
437 {
438         struct edma_cc *ecc = echan->ecc;
439         int channel = EDMA_CHAN_SLOT(echan->ch_num);
440 
441         if (enable) {
442                 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
443                                          BIT(channel & 0x1f));
444                 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
445                                          BIT(channel & 0x1f));
446         } else {
447                 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
448                                          BIT(channel & 0x1f));
449         }
450 }
451 
452 /*
453  * paRAM slot management functions
454  */
455 static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
456                             const struct edmacc_param *param)
457 {
458         slot = EDMA_CHAN_SLOT(slot);
459         if (slot >= ecc->num_slots)
460                 return;
461         memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
462 }
463 
464 static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
465                            struct edmacc_param *param)
466 {
467         slot = EDMA_CHAN_SLOT(slot);
468         if (slot >= ecc->num_slots)
469                 return;
470         memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
471 }
472 
473 /**
474  * edma_alloc_slot - allocate DMA parameter RAM
475  * @ecc: pointer to edma_cc struct
476  * @slot: specific slot to allocate; negative for "any unused slot"
477  *
478  * This allocates a parameter RAM slot, initializing it to hold a
479  * dummy transfer.  Slots allocated using this routine have not been
480  * mapped to a hardware DMA channel, and will normally be used by
481  * linking to them from a slot associated with a DMA channel.
482  *
483  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
484  * slots may be allocated on behalf of DSP firmware.
485  *
486  * Returns the number of the slot, else negative errno.
487  */
488 static int edma_alloc_slot(struct edma_cc *ecc, int slot)
489 {
490         if (slot >= 0) {
491                 slot = EDMA_CHAN_SLOT(slot);
492                 /* Requesting entry paRAM slot for a HW triggered channel. */
493                 if (ecc->chmap_exist && slot < ecc->num_channels)
494                         slot = EDMA_SLOT_ANY;
495         }
496 
497         if (slot < 0) {
498                 if (ecc->chmap_exist)
499                         slot = 0;
500                 else
501                         slot = ecc->num_channels;
502                 for (;;) {
503                         slot = find_next_zero_bit(ecc->slot_inuse,
504                                                   ecc->num_slots,
505                                                   slot);
506                         if (slot == ecc->num_slots)
507                                 return -ENOMEM;
508                         if (!test_and_set_bit(slot, ecc->slot_inuse))
509                                 break;
510                 }
511         } else if (slot >= ecc->num_slots) {
512                 return -EINVAL;
513         } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
514                 return -EBUSY;
515         }
516 
517         edma_write_slot(ecc, slot, &dummy_paramset);
518 
519         return EDMA_CTLR_CHAN(ecc->id, slot);
520 }
521 
522 static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
523 {
524         slot = EDMA_CHAN_SLOT(slot);
525         if (slot >= ecc->num_slots)
526                 return;
527 
528         edma_write_slot(ecc, slot, &dummy_paramset);
529         clear_bit(slot, ecc->slot_inuse);
530 }
531 
532 /**
533  * edma_link - link one parameter RAM slot to another
534  * @ecc: pointer to edma_cc struct
535  * @from: parameter RAM slot originating the link
536  * @to: parameter RAM slot which is the link target
537  *
538  * The originating slot should not be part of any active DMA transfer.
539  */
540 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
541 {
542         if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
543                 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
544 
545         from = EDMA_CHAN_SLOT(from);
546         to = EDMA_CHAN_SLOT(to);
547         if (from >= ecc->num_slots || to >= ecc->num_slots)
548                 return;
549 
550         edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
551                           PARM_OFFSET(to));
552 }
553 
554 /**
555  * edma_get_position - returns the current transfer point
556  * @ecc: pointer to edma_cc struct
557  * @slot: parameter RAM slot being examined
558  * @dst:  true selects the dest position, false the source
559  *
560  * Returns the position of the current active slot
561  */
562 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
563                                     bool dst)
564 {
565         u32 offs;
566 
567         slot = EDMA_CHAN_SLOT(slot);
568         offs = PARM_OFFSET(slot);
569         offs += dst ? PARM_DST : PARM_SRC;
570 
571         return edma_read(ecc, offs);
572 }
573 
574 /*
575  * Channels with event associations will be triggered by their hardware
576  * events, and channels without such associations will be triggered by
577  * software.  (At this writing there is no interface for using software
578  * triggers except with channels that don't support hardware triggers.)
579  */
580 static void edma_start(struct edma_chan *echan)
581 {
582         struct edma_cc *ecc = echan->ecc;
583         int channel = EDMA_CHAN_SLOT(echan->ch_num);
584         int j = (channel >> 5);
585         unsigned int mask = BIT(channel & 0x1f);
586 
587         if (!echan->hw_triggered) {
588                 /* EDMA channels without event association */
589                 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
590                         edma_shadow0_read_array(ecc, SH_ESR, j));
591                 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
592         } else {
593                 /* EDMA channel with event association */
594                 dev_dbg(ecc->dev, "ER%d %08x\n", j,
595                         edma_shadow0_read_array(ecc, SH_ER, j));
596                 /* Clear any pending event or error */
597                 edma_write_array(ecc, EDMA_ECR, j, mask);
598                 edma_write_array(ecc, EDMA_EMCR, j, mask);
599                 /* Clear any SER */
600                 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
601                 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
602                 dev_dbg(ecc->dev, "EER%d %08x\n", j,
603                         edma_shadow0_read_array(ecc, SH_EER, j));
604         }
605 }
606 
607 static void edma_stop(struct edma_chan *echan)
608 {
609         struct edma_cc *ecc = echan->ecc;
610         int channel = EDMA_CHAN_SLOT(echan->ch_num);
611         int j = (channel >> 5);
612         unsigned int mask = BIT(channel & 0x1f);
613 
614         edma_shadow0_write_array(ecc, SH_EECR, j, mask);
615         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
616         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
617         edma_write_array(ecc, EDMA_EMCR, j, mask);
618 
619         /* clear possibly pending completion interrupt */
620         edma_shadow0_write_array(ecc, SH_ICR, j, mask);
621 
622         dev_dbg(ecc->dev, "EER%d %08x\n", j,
623                 edma_shadow0_read_array(ecc, SH_EER, j));
624 
625         /* REVISIT:  consider guarding against inappropriate event
626          * chaining by overwriting with dummy_paramset.
627          */
628 }
629 
630 /*
631  * Temporarily disable EDMA hardware events on the specified channel,
632  * preventing them from triggering new transfers
633  */
634 static void edma_pause(struct edma_chan *echan)
635 {
636         int channel = EDMA_CHAN_SLOT(echan->ch_num);
637         unsigned int mask = BIT(channel & 0x1f);
638 
639         edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
640 }
641 
642 /* Re-enable EDMA hardware events on the specified channel.  */
643 static void edma_resume(struct edma_chan *echan)
644 {
645         int channel = EDMA_CHAN_SLOT(echan->ch_num);
646         unsigned int mask = BIT(channel & 0x1f);
647 
648         edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
649 }
650 
651 static void edma_trigger_channel(struct edma_chan *echan)
652 {
653         struct edma_cc *ecc = echan->ecc;
654         int channel = EDMA_CHAN_SLOT(echan->ch_num);
655         unsigned int mask = BIT(channel & 0x1f);
656 
657         edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
658 
659         dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
660                 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
661 }
662 
663 static void edma_clean_channel(struct edma_chan *echan)
664 {
665         struct edma_cc *ecc = echan->ecc;
666         int channel = EDMA_CHAN_SLOT(echan->ch_num);
667         int j = (channel >> 5);
668         unsigned int mask = BIT(channel & 0x1f);
669 
670         dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
671         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
672         /* Clear the corresponding EMR bits */
673         edma_write_array(ecc, EDMA_EMCR, j, mask);
674         /* Clear any SER */
675         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
676         edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
677 }
678 
679 /* Move channel to a specific event queue */
680 static void edma_assign_channel_eventq(struct edma_chan *echan,
681                                        enum dma_event_q eventq_no)
682 {
683         struct edma_cc *ecc = echan->ecc;
684         int channel = EDMA_CHAN_SLOT(echan->ch_num);
685         int bit = (channel & 0x7) * 4;
686 
687         /* default to low priority queue */
688         if (eventq_no == EVENTQ_DEFAULT)
689                 eventq_no = ecc->default_queue;
690         if (eventq_no >= ecc->num_tc)
691                 return;
692 
693         eventq_no &= 7;
694         edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
695                           eventq_no << bit);
696 }
697 
698 static int edma_alloc_channel(struct edma_chan *echan,
699                               enum dma_event_q eventq_no)
700 {
701         struct edma_cc *ecc = echan->ecc;
702         int channel = EDMA_CHAN_SLOT(echan->ch_num);
703 
704         /* ensure access through shadow region 0 */
705         edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
706 
707         /* ensure no events are pending */
708         edma_stop(echan);
709 
710         edma_setup_interrupt(echan, true);
711 
712         edma_assign_channel_eventq(echan, eventq_no);
713 
714         return 0;
715 }
716 
717 static void edma_free_channel(struct edma_chan *echan)
718 {
719         /* ensure no events are pending */
720         edma_stop(echan);
721         /* REVISIT should probably take out of shadow region 0 */
722         edma_setup_interrupt(echan, false);
723 }
724 
725 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
726 {
727         return container_of(d, struct edma_cc, dma_slave);
728 }
729 
730 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
731 {
732         return container_of(c, struct edma_chan, vchan.chan);
733 }
734 
735 static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
736 {
737         return container_of(tx, struct edma_desc, vdesc.tx);
738 }
739 
740 static void edma_desc_free(struct virt_dma_desc *vdesc)
741 {
742         kfree(container_of(vdesc, struct edma_desc, vdesc));
743 }
744 
745 /* Dispatch a queued descriptor to the controller (caller holds lock) */
746 static void edma_execute(struct edma_chan *echan)
747 {
748         struct edma_cc *ecc = echan->ecc;
749         struct virt_dma_desc *vdesc;
750         struct edma_desc *edesc;
751         struct device *dev = echan->vchan.chan.device->dev;
752         int i, j, left, nslots;
753 
754         if (!echan->edesc) {
755                 /* Setup is needed for the first transfer */
756                 vdesc = vchan_next_desc(&echan->vchan);
757                 if (!vdesc)
758                         return;
759                 list_del(&vdesc->node);
760                 echan->edesc = to_edma_desc(&vdesc->tx);
761         }
762 
763         edesc = echan->edesc;
764 
765         /* Find out how many left */
766         left = edesc->pset_nr - edesc->processed;
767         nslots = min(MAX_NR_SG, left);
768         edesc->sg_len = 0;
769 
770         /* Write descriptor PaRAM set(s) */
771         for (i = 0; i < nslots; i++) {
772                 j = i + edesc->processed;
773                 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
774                 edesc->sg_len += edesc->pset[j].len;
775                 dev_vdbg(dev,
776                          "\n pset[%d]:\n"
777                          "  chnum\t%d\n"
778                          "  slot\t%d\n"
779                          "  opt\t%08x\n"
780                          "  src\t%08x\n"
781                          "  dst\t%08x\n"
782                          "  abcnt\t%08x\n"
783                          "  ccnt\t%08x\n"
784                          "  bidx\t%08x\n"
785                          "  cidx\t%08x\n"
786                          "  lkrld\t%08x\n",
787                          j, echan->ch_num, echan->slot[i],
788                          edesc->pset[j].param.opt,
789                          edesc->pset[j].param.src,
790                          edesc->pset[j].param.dst,
791                          edesc->pset[j].param.a_b_cnt,
792                          edesc->pset[j].param.ccnt,
793                          edesc->pset[j].param.src_dst_bidx,
794                          edesc->pset[j].param.src_dst_cidx,
795                          edesc->pset[j].param.link_bcntrld);
796                 /* Link to the previous slot if not the last set */
797                 if (i != (nslots - 1))
798                         edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
799         }
800 
801         edesc->processed += nslots;
802 
803         /*
804          * If this is either the last set in a set of SG-list transactions
805          * then setup a link to the dummy slot, this results in all future
806          * events being absorbed and that's OK because we're done
807          */
808         if (edesc->processed == edesc->pset_nr) {
809                 if (edesc->cyclic)
810                         edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
811                 else
812                         edma_link(ecc, echan->slot[nslots - 1],
813                                   echan->ecc->dummy_slot);
814         }
815 
816         if (echan->missed) {
817                 /*
818                  * This happens due to setup times between intermediate
819                  * transfers in long SG lists which have to be broken up into
820                  * transfers of MAX_NR_SG
821                  */
822                 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
823                 edma_clean_channel(echan);
824                 edma_stop(echan);
825                 edma_start(echan);
826                 edma_trigger_channel(echan);
827                 echan->missed = 0;
828         } else if (edesc->processed <= MAX_NR_SG) {
829                 dev_dbg(dev, "first transfer starting on channel %d\n",
830                         echan->ch_num);
831                 edma_start(echan);
832         } else {
833                 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
834                         echan->ch_num, edesc->processed);
835                 edma_resume(echan);
836         }
837 }
838 
839 static int edma_terminate_all(struct dma_chan *chan)
840 {
841         struct edma_chan *echan = to_edma_chan(chan);
842         unsigned long flags;
843         LIST_HEAD(head);
844 
845         spin_lock_irqsave(&echan->vchan.lock, flags);
846 
847         /*
848          * Stop DMA activity: we assume the callback will not be called
849          * after edma_dma() returns (even if it does, it will see
850          * echan->edesc is NULL and exit.)
851          */
852         if (echan->edesc) {
853                 edma_stop(echan);
854                 /* Move the cyclic channel back to default queue */
855                 if (!echan->tc && echan->edesc->cyclic)
856                         edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
857                 /*
858                  * free the running request descriptor
859                  * since it is not in any of the vdesc lists
860                  */
861                 edma_desc_free(&echan->edesc->vdesc);
862                 echan->edesc = NULL;
863         }
864 
865         vchan_get_all_descriptors(&echan->vchan, &head);
866         spin_unlock_irqrestore(&echan->vchan.lock, flags);
867         vchan_dma_desc_free_list(&echan->vchan, &head);
868 
869         return 0;
870 }
871 
872 static void edma_synchronize(struct dma_chan *chan)
873 {
874         struct edma_chan *echan = to_edma_chan(chan);
875 
876         vchan_synchronize(&echan->vchan);
877 }
878 
879 static int edma_slave_config(struct dma_chan *chan,
880         struct dma_slave_config *cfg)
881 {
882         struct edma_chan *echan = to_edma_chan(chan);
883 
884         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
885             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
886                 return -EINVAL;
887 
888         memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
889 
890         return 0;
891 }
892 
893 static int edma_dma_pause(struct dma_chan *chan)
894 {
895         struct edma_chan *echan = to_edma_chan(chan);
896 
897         if (!echan->edesc)
898                 return -EINVAL;
899 
900         edma_pause(echan);
901         return 0;
902 }
903 
904 static int edma_dma_resume(struct dma_chan *chan)
905 {
906         struct edma_chan *echan = to_edma_chan(chan);
907 
908         edma_resume(echan);
909         return 0;
910 }
911 
912 /*
913  * A PaRAM set configuration abstraction used by other modes
914  * @chan: Channel who's PaRAM set we're configuring
915  * @pset: PaRAM set to initialize and setup.
916  * @src_addr: Source address of the DMA
917  * @dst_addr: Destination address of the DMA
918  * @burst: In units of dev_width, how much to send
919  * @dev_width: How much is the dev_width
920  * @dma_length: Total length of the DMA transfer
921  * @direction: Direction of the transfer
922  */
923 static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
924                             dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
925                             unsigned int acnt, unsigned int dma_length,
926                             enum dma_transfer_direction direction)
927 {
928         struct edma_chan *echan = to_edma_chan(chan);
929         struct device *dev = chan->device->dev;
930         struct edmacc_param *param = &epset->param;
931         int bcnt, ccnt, cidx;
932         int src_bidx, dst_bidx, src_cidx, dst_cidx;
933         int absync;
934 
935         /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
936         if (!burst)
937                 burst = 1;
938         /*
939          * If the maxburst is equal to the fifo width, use
940          * A-synced transfers. This allows for large contiguous
941          * buffer transfers using only one PaRAM set.
942          */
943         if (burst == 1) {
944                 /*
945                  * For the A-sync case, bcnt and ccnt are the remainder
946                  * and quotient respectively of the division of:
947                  * (dma_length / acnt) by (SZ_64K -1). This is so
948                  * that in case bcnt over flows, we have ccnt to use.
949                  * Note: In A-sync tranfer only, bcntrld is used, but it
950                  * only applies for sg_dma_len(sg) >= SZ_64K.
951                  * In this case, the best way adopted is- bccnt for the
952                  * first frame will be the remainder below. Then for
953                  * every successive frame, bcnt will be SZ_64K-1. This
954                  * is assured as bcntrld = 0xffff in end of function.
955                  */
956                 absync = false;
957                 ccnt = dma_length / acnt / (SZ_64K - 1);
958                 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
959                 /*
960                  * If bcnt is non-zero, we have a remainder and hence an
961                  * extra frame to transfer, so increment ccnt.
962                  */
963                 if (bcnt)
964                         ccnt++;
965                 else
966                         bcnt = SZ_64K - 1;
967                 cidx = acnt;
968         } else {
969                 /*
970                  * If maxburst is greater than the fifo address_width,
971                  * use AB-synced transfers where A count is the fifo
972                  * address_width and B count is the maxburst. In this
973                  * case, we are limited to transfers of C count frames
974                  * of (address_width * maxburst) where C count is limited
975                  * to SZ_64K-1. This places an upper bound on the length
976                  * of an SG segment that can be handled.
977                  */
978                 absync = true;
979                 bcnt = burst;
980                 ccnt = dma_length / (acnt * bcnt);
981                 if (ccnt > (SZ_64K - 1)) {
982                         dev_err(dev, "Exceeded max SG segment size\n");
983                         return -EINVAL;
984                 }
985                 cidx = acnt * bcnt;
986         }
987 
988         epset->len = dma_length;
989 
990         if (direction == DMA_MEM_TO_DEV) {
991                 src_bidx = acnt;
992                 src_cidx = cidx;
993                 dst_bidx = 0;
994                 dst_cidx = 0;
995                 epset->addr = src_addr;
996         } else if (direction == DMA_DEV_TO_MEM)  {
997                 src_bidx = 0;
998                 src_cidx = 0;
999                 dst_bidx = acnt;
1000                 dst_cidx = cidx;
1001                 epset->addr = dst_addr;
1002         } else if (direction == DMA_MEM_TO_MEM)  {
1003                 src_bidx = acnt;
1004                 src_cidx = cidx;
1005                 dst_bidx = acnt;
1006                 dst_cidx = cidx;
1007         } else {
1008                 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1009                 return -EINVAL;
1010         }
1011 
1012         param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1013         /* Configure A or AB synchronized transfers */
1014         if (absync)
1015                 param->opt |= SYNCDIM;
1016 
1017         param->src = src_addr;
1018         param->dst = dst_addr;
1019 
1020         param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1021         param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1022 
1023         param->a_b_cnt = bcnt << 16 | acnt;
1024         param->ccnt = ccnt;
1025         /*
1026          * Only time when (bcntrld) auto reload is required is for
1027          * A-sync case, and in this case, a requirement of reload value
1028          * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1029          * and then later will be populated by edma_execute.
1030          */
1031         param->link_bcntrld = 0xffffffff;
1032         return absync;
1033 }
1034 
1035 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1036         struct dma_chan *chan, struct scatterlist *sgl,
1037         unsigned int sg_len, enum dma_transfer_direction direction,
1038         unsigned long tx_flags, void *context)
1039 {
1040         struct edma_chan *echan = to_edma_chan(chan);
1041         struct device *dev = chan->device->dev;
1042         struct edma_desc *edesc;
1043         dma_addr_t src_addr = 0, dst_addr = 0;
1044         enum dma_slave_buswidth dev_width;
1045         u32 burst;
1046         struct scatterlist *sg;
1047         int i, nslots, ret;
1048 
1049         if (unlikely(!echan || !sgl || !sg_len))
1050                 return NULL;
1051 
1052         if (direction == DMA_DEV_TO_MEM) {
1053                 src_addr = echan->cfg.src_addr;
1054                 dev_width = echan->cfg.src_addr_width;
1055                 burst = echan->cfg.src_maxburst;
1056         } else if (direction == DMA_MEM_TO_DEV) {
1057                 dst_addr = echan->cfg.dst_addr;
1058                 dev_width = echan->cfg.dst_addr_width;
1059                 burst = echan->cfg.dst_maxburst;
1060         } else {
1061                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1062                 return NULL;
1063         }
1064 
1065         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1066                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1067                 return NULL;
1068         }
1069 
1070         edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1071                         GFP_ATOMIC);
1072         if (!edesc) {
1073                 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
1074                 return NULL;
1075         }
1076 
1077         edesc->pset_nr = sg_len;
1078         edesc->residue = 0;
1079         edesc->direction = direction;
1080         edesc->echan = echan;
1081 
1082         /* Allocate a PaRAM slot, if needed */
1083         nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1084 
1085         for (i = 0; i < nslots; i++) {
1086                 if (echan->slot[i] < 0) {
1087                         echan->slot[i] =
1088                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1089                         if (echan->slot[i] < 0) {
1090                                 kfree(edesc);
1091                                 dev_err(dev, "%s: Failed to allocate slot\n",
1092                                         __func__);
1093                                 return NULL;
1094                         }
1095                 }
1096         }
1097 
1098         /* Configure PaRAM sets for each SG */
1099         for_each_sg(sgl, sg, sg_len, i) {
1100                 /* Get address for each SG */
1101                 if (direction == DMA_DEV_TO_MEM)
1102                         dst_addr = sg_dma_address(sg);
1103                 else
1104                         src_addr = sg_dma_address(sg);
1105 
1106                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1107                                        dst_addr, burst, dev_width,
1108                                        sg_dma_len(sg), direction);
1109                 if (ret < 0) {
1110                         kfree(edesc);
1111                         return NULL;
1112                 }
1113 
1114                 edesc->absync = ret;
1115                 edesc->residue += sg_dma_len(sg);
1116 
1117                 /* If this is the last in a current SG set of transactions,
1118                    enable interrupts so that next set is processed */
1119                 if (!((i+1) % MAX_NR_SG))
1120                         edesc->pset[i].param.opt |= TCINTEN;
1121 
1122                 /* If this is the last set, enable completion interrupt flag */
1123                 if (i == sg_len - 1)
1124                         edesc->pset[i].param.opt |= TCINTEN;
1125         }
1126         edesc->residue_stat = edesc->residue;
1127 
1128         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1129 }
1130 
1131 static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1132         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1133         size_t len, unsigned long tx_flags)
1134 {
1135         int ret, nslots;
1136         struct edma_desc *edesc;
1137         struct device *dev = chan->device->dev;
1138         struct edma_chan *echan = to_edma_chan(chan);
1139         unsigned int width, pset_len;
1140 
1141         if (unlikely(!echan || !len))
1142                 return NULL;
1143 
1144         if (len < SZ_64K) {
1145                 /*
1146                  * Transfer size less than 64K can be handled with one paRAM
1147                  * slot and with one burst.
1148                  * ACNT = length
1149                  */
1150                 width = len;
1151                 pset_len = len;
1152                 nslots = 1;
1153         } else {
1154                 /*
1155                  * Transfer size bigger than 64K will be handled with maximum of
1156                  * two paRAM slots.
1157                  * slot1: (full_length / 32767) times 32767 bytes bursts.
1158                  *        ACNT = 32767, length1: (full_length / 32767) * 32767
1159                  * slot2: the remaining amount of data after slot1.
1160                  *        ACNT = full_length - length1, length2 = ACNT
1161                  *
1162                  * When the full_length is multibple of 32767 one slot can be
1163                  * used to complete the transfer.
1164                  */
1165                 width = SZ_32K - 1;
1166                 pset_len = rounddown(len, width);
1167                 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1168                 if (unlikely(pset_len == len))
1169                         nslots = 1;
1170                 else
1171                         nslots = 2;
1172         }
1173 
1174         edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1175                         GFP_ATOMIC);
1176         if (!edesc) {
1177                 dev_dbg(dev, "Failed to allocate a descriptor\n");
1178                 return NULL;
1179         }
1180 
1181         edesc->pset_nr = nslots;
1182         edesc->residue = edesc->residue_stat = len;
1183         edesc->direction = DMA_MEM_TO_MEM;
1184         edesc->echan = echan;
1185 
1186         ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1187                                width, pset_len, DMA_MEM_TO_MEM);
1188         if (ret < 0) {
1189                 kfree(edesc);
1190                 return NULL;
1191         }
1192 
1193         edesc->absync = ret;
1194 
1195         edesc->pset[0].param.opt |= ITCCHEN;
1196         if (nslots == 1) {
1197                 /* Enable transfer complete interrupt */
1198                 edesc->pset[0].param.opt |= TCINTEN;
1199         } else {
1200                 /* Enable transfer complete chaining for the first slot */
1201                 edesc->pset[0].param.opt |= TCCHEN;
1202 
1203                 if (echan->slot[1] < 0) {
1204                         echan->slot[1] = edma_alloc_slot(echan->ecc,
1205                                                          EDMA_SLOT_ANY);
1206                         if (echan->slot[1] < 0) {
1207                                 kfree(edesc);
1208                                 dev_err(dev, "%s: Failed to allocate slot\n",
1209                                         __func__);
1210                                 return NULL;
1211                         }
1212                 }
1213                 dest += pset_len;
1214                 src += pset_len;
1215                 pset_len = width = len % (SZ_32K - 1);
1216 
1217                 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1218                                        width, pset_len, DMA_MEM_TO_MEM);
1219                 if (ret < 0) {
1220                         kfree(edesc);
1221                         return NULL;
1222                 }
1223 
1224                 edesc->pset[1].param.opt |= ITCCHEN;
1225                 edesc->pset[1].param.opt |= TCINTEN;
1226         }
1227 
1228         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1229 }
1230 
1231 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1232         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1233         size_t period_len, enum dma_transfer_direction direction,
1234         unsigned long tx_flags)
1235 {
1236         struct edma_chan *echan = to_edma_chan(chan);
1237         struct device *dev = chan->device->dev;
1238         struct edma_desc *edesc;
1239         dma_addr_t src_addr, dst_addr;
1240         enum dma_slave_buswidth dev_width;
1241         bool use_intermediate = false;
1242         u32 burst;
1243         int i, ret, nslots;
1244 
1245         if (unlikely(!echan || !buf_len || !period_len))
1246                 return NULL;
1247 
1248         if (direction == DMA_DEV_TO_MEM) {
1249                 src_addr = echan->cfg.src_addr;
1250                 dst_addr = buf_addr;
1251                 dev_width = echan->cfg.src_addr_width;
1252                 burst = echan->cfg.src_maxburst;
1253         } else if (direction == DMA_MEM_TO_DEV) {
1254                 src_addr = buf_addr;
1255                 dst_addr = echan->cfg.dst_addr;
1256                 dev_width = echan->cfg.dst_addr_width;
1257                 burst = echan->cfg.dst_maxburst;
1258         } else {
1259                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1260                 return NULL;
1261         }
1262 
1263         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1264                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1265                 return NULL;
1266         }
1267 
1268         if (unlikely(buf_len % period_len)) {
1269                 dev_err(dev, "Period should be multiple of Buffer length\n");
1270                 return NULL;
1271         }
1272 
1273         nslots = (buf_len / period_len) + 1;
1274 
1275         /*
1276          * Cyclic DMA users such as audio cannot tolerate delays introduced
1277          * by cases where the number of periods is more than the maximum
1278          * number of SGs the EDMA driver can handle at a time. For DMA types
1279          * such as Slave SGs, such delays are tolerable and synchronized,
1280          * but the synchronization is difficult to achieve with Cyclic and
1281          * cannot be guaranteed, so we error out early.
1282          */
1283         if (nslots > MAX_NR_SG) {
1284                 /*
1285                  * If the burst and period sizes are the same, we can put
1286                  * the full buffer into a single period and activate
1287                  * intermediate interrupts. This will produce interrupts
1288                  * after each burst, which is also after each desired period.
1289                  */
1290                 if (burst == period_len) {
1291                         period_len = buf_len;
1292                         nslots = 2;
1293                         use_intermediate = true;
1294                 } else {
1295                         return NULL;
1296                 }
1297         }
1298 
1299         edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1300                         GFP_ATOMIC);
1301         if (!edesc) {
1302                 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
1303                 return NULL;
1304         }
1305 
1306         edesc->cyclic = 1;
1307         edesc->pset_nr = nslots;
1308         edesc->residue = edesc->residue_stat = buf_len;
1309         edesc->direction = direction;
1310         edesc->echan = echan;
1311 
1312         dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1313                 __func__, echan->ch_num, nslots, period_len, buf_len);
1314 
1315         for (i = 0; i < nslots; i++) {
1316                 /* Allocate a PaRAM slot, if needed */
1317                 if (echan->slot[i] < 0) {
1318                         echan->slot[i] =
1319                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1320                         if (echan->slot[i] < 0) {
1321                                 kfree(edesc);
1322                                 dev_err(dev, "%s: Failed to allocate slot\n",
1323                                         __func__);
1324                                 return NULL;
1325                         }
1326                 }
1327 
1328                 if (i == nslots - 1) {
1329                         memcpy(&edesc->pset[i], &edesc->pset[0],
1330                                sizeof(edesc->pset[0]));
1331                         break;
1332                 }
1333 
1334                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1335                                        dst_addr, burst, dev_width, period_len,
1336                                        direction);
1337                 if (ret < 0) {
1338                         kfree(edesc);
1339                         return NULL;
1340                 }
1341 
1342                 if (direction == DMA_DEV_TO_MEM)
1343                         dst_addr += period_len;
1344                 else
1345                         src_addr += period_len;
1346 
1347                 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1348                 dev_vdbg(dev,
1349                         "\n pset[%d]:\n"
1350                         "  chnum\t%d\n"
1351                         "  slot\t%d\n"
1352                         "  opt\t%08x\n"
1353                         "  src\t%08x\n"
1354                         "  dst\t%08x\n"
1355                         "  abcnt\t%08x\n"
1356                         "  ccnt\t%08x\n"
1357                         "  bidx\t%08x\n"
1358                         "  cidx\t%08x\n"
1359                         "  lkrld\t%08x\n",
1360                         i, echan->ch_num, echan->slot[i],
1361                         edesc->pset[i].param.opt,
1362                         edesc->pset[i].param.src,
1363                         edesc->pset[i].param.dst,
1364                         edesc->pset[i].param.a_b_cnt,
1365                         edesc->pset[i].param.ccnt,
1366                         edesc->pset[i].param.src_dst_bidx,
1367                         edesc->pset[i].param.src_dst_cidx,
1368                         edesc->pset[i].param.link_bcntrld);
1369 
1370                 edesc->absync = ret;
1371 
1372                 /*
1373                  * Enable period interrupt only if it is requested
1374                  */
1375                 if (tx_flags & DMA_PREP_INTERRUPT) {
1376                         edesc->pset[i].param.opt |= TCINTEN;
1377 
1378                         /* Also enable intermediate interrupts if necessary */
1379                         if (use_intermediate)
1380                                 edesc->pset[i].param.opt |= ITCINTEN;
1381                 }
1382         }
1383 
1384         /* Place the cyclic channel to highest priority queue */
1385         if (!echan->tc)
1386                 edma_assign_channel_eventq(echan, EVENTQ_0);
1387 
1388         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1389 }
1390 
1391 static void edma_completion_handler(struct edma_chan *echan)
1392 {
1393         struct device *dev = echan->vchan.chan.device->dev;
1394         struct edma_desc *edesc;
1395 
1396         spin_lock(&echan->vchan.lock);
1397         edesc = echan->edesc;
1398         if (edesc) {
1399                 if (edesc->cyclic) {
1400                         vchan_cyclic_callback(&edesc->vdesc);
1401                         spin_unlock(&echan->vchan.lock);
1402                         return;
1403                 } else if (edesc->processed == edesc->pset_nr) {
1404                         edesc->residue = 0;
1405                         edma_stop(echan);
1406                         vchan_cookie_complete(&edesc->vdesc);
1407                         echan->edesc = NULL;
1408 
1409                         dev_dbg(dev, "Transfer completed on channel %d\n",
1410                                 echan->ch_num);
1411                 } else {
1412                         dev_dbg(dev, "Sub transfer completed on channel %d\n",
1413                                 echan->ch_num);
1414 
1415                         edma_pause(echan);
1416 
1417                         /* Update statistics for tx_status */
1418                         edesc->residue -= edesc->sg_len;
1419                         edesc->residue_stat = edesc->residue;
1420                         edesc->processed_stat = edesc->processed;
1421                 }
1422                 edma_execute(echan);
1423         }
1424 
1425         spin_unlock(&echan->vchan.lock);
1426 }
1427 
1428 /* eDMA interrupt handler */
1429 static irqreturn_t dma_irq_handler(int irq, void *data)
1430 {
1431         struct edma_cc *ecc = data;
1432         int ctlr;
1433         u32 sh_ier;
1434         u32 sh_ipr;
1435         u32 bank;
1436 
1437         ctlr = ecc->id;
1438         if (ctlr < 0)
1439                 return IRQ_NONE;
1440 
1441         dev_vdbg(ecc->dev, "dma_irq_handler\n");
1442 
1443         sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1444         if (!sh_ipr) {
1445                 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1446                 if (!sh_ipr)
1447                         return IRQ_NONE;
1448                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1449                 bank = 1;
1450         } else {
1451                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1452                 bank = 0;
1453         }
1454 
1455         do {
1456                 u32 slot;
1457                 u32 channel;
1458 
1459                 slot = __ffs(sh_ipr);
1460                 sh_ipr &= ~(BIT(slot));
1461 
1462                 if (sh_ier & BIT(slot)) {
1463                         channel = (bank << 5) | slot;
1464                         /* Clear the corresponding IPR bits */
1465                         edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1466                         edma_completion_handler(&ecc->slave_chans[channel]);
1467                 }
1468         } while (sh_ipr);
1469 
1470         edma_shadow0_write(ecc, SH_IEVAL, 1);
1471         return IRQ_HANDLED;
1472 }
1473 
1474 static void edma_error_handler(struct edma_chan *echan)
1475 {
1476         struct edma_cc *ecc = echan->ecc;
1477         struct device *dev = echan->vchan.chan.device->dev;
1478         struct edmacc_param p;
1479 
1480         if (!echan->edesc)
1481                 return;
1482 
1483         spin_lock(&echan->vchan.lock);
1484 
1485         edma_read_slot(ecc, echan->slot[0], &p);
1486         /*
1487          * Issue later based on missed flag which will be sure
1488          * to happen as:
1489          * (1) we finished transmitting an intermediate slot and
1490          *     edma_execute is coming up.
1491          * (2) or we finished current transfer and issue will
1492          *     call edma_execute.
1493          *
1494          * Important note: issuing can be dangerous here and
1495          * lead to some nasty recursion when we are in a NULL
1496          * slot. So we avoid doing so and set the missed flag.
1497          */
1498         if (p.a_b_cnt == 0 && p.ccnt == 0) {
1499                 dev_dbg(dev, "Error on null slot, setting miss\n");
1500                 echan->missed = 1;
1501         } else {
1502                 /*
1503                  * The slot is already programmed but the event got
1504                  * missed, so its safe to issue it here.
1505                  */
1506                 dev_dbg(dev, "Missed event, TRIGGERING\n");
1507                 edma_clean_channel(echan);
1508                 edma_stop(echan);
1509                 edma_start(echan);
1510                 edma_trigger_channel(echan);
1511         }
1512         spin_unlock(&echan->vchan.lock);
1513 }
1514 
1515 static inline bool edma_error_pending(struct edma_cc *ecc)
1516 {
1517         if (edma_read_array(ecc, EDMA_EMR, 0) ||
1518             edma_read_array(ecc, EDMA_EMR, 1) ||
1519             edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1520                 return true;
1521 
1522         return false;
1523 }
1524 
1525 /* eDMA error interrupt handler */
1526 static irqreturn_t dma_ccerr_handler(int irq, void *data)
1527 {
1528         struct edma_cc *ecc = data;
1529         int i, j;
1530         int ctlr;
1531         unsigned int cnt = 0;
1532         unsigned int val;
1533 
1534         ctlr = ecc->id;
1535         if (ctlr < 0)
1536                 return IRQ_NONE;
1537 
1538         dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1539 
1540         if (!edma_error_pending(ecc))
1541                 return IRQ_NONE;
1542 
1543         while (1) {
1544                 /* Event missed register(s) */
1545                 for (j = 0; j < 2; j++) {
1546                         unsigned long emr;
1547 
1548                         val = edma_read_array(ecc, EDMA_EMR, j);
1549                         if (!val)
1550                                 continue;
1551 
1552                         dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1553                         emr = val;
1554                         for (i = find_next_bit(&emr, 32, 0); i < 32;
1555                              i = find_next_bit(&emr, 32, i + 1)) {
1556                                 int k = (j << 5) + i;
1557 
1558                                 /* Clear the corresponding EMR bits */
1559                                 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1560                                 /* Clear any SER */
1561                                 edma_shadow0_write_array(ecc, SH_SECR, j,
1562                                                          BIT(i));
1563                                 edma_error_handler(&ecc->slave_chans[k]);
1564                         }
1565                 }
1566 
1567                 val = edma_read(ecc, EDMA_QEMR);
1568                 if (val) {
1569                         dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1570                         /* Not reported, just clear the interrupt reason. */
1571                         edma_write(ecc, EDMA_QEMCR, val);
1572                         edma_shadow0_write(ecc, SH_QSECR, val);
1573                 }
1574 
1575                 val = edma_read(ecc, EDMA_CCERR);
1576                 if (val) {
1577                         dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1578                         /* Not reported, just clear the interrupt reason. */
1579                         edma_write(ecc, EDMA_CCERRCLR, val);
1580                 }
1581 
1582                 if (!edma_error_pending(ecc))
1583                         break;
1584                 cnt++;
1585                 if (cnt > 10)
1586                         break;
1587         }
1588         edma_write(ecc, EDMA_EEVAL, 1);
1589         return IRQ_HANDLED;
1590 }
1591 
1592 /* Alloc channel resources */
1593 static int edma_alloc_chan_resources(struct dma_chan *chan)
1594 {
1595         struct edma_chan *echan = to_edma_chan(chan);
1596         struct edma_cc *ecc = echan->ecc;
1597         struct device *dev = ecc->dev;
1598         enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1599         int ret;
1600 
1601         if (echan->tc) {
1602                 eventq_no = echan->tc->id;
1603         } else if (ecc->tc_list) {
1604                 /* memcpy channel */
1605                 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1606                 eventq_no = echan->tc->id;
1607         }
1608 
1609         ret = edma_alloc_channel(echan, eventq_no);
1610         if (ret)
1611                 return ret;
1612 
1613         echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1614         if (echan->slot[0] < 0) {
1615                 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1616                         EDMA_CHAN_SLOT(echan->ch_num));
1617                 goto err_slot;
1618         }
1619 
1620         /* Set up channel -> slot mapping for the entry slot */
1621         edma_set_chmap(echan, echan->slot[0]);
1622         echan->alloced = true;
1623 
1624         dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1625                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1626                 echan->hw_triggered ? "HW" : "SW");
1627 
1628         return 0;
1629 
1630 err_slot:
1631         edma_free_channel(echan);
1632         return ret;
1633 }
1634 
1635 /* Free channel resources */
1636 static void edma_free_chan_resources(struct dma_chan *chan)
1637 {
1638         struct edma_chan *echan = to_edma_chan(chan);
1639         struct device *dev = echan->ecc->dev;
1640         int i;
1641 
1642         /* Terminate transfers */
1643         edma_stop(echan);
1644 
1645         vchan_free_chan_resources(&echan->vchan);
1646 
1647         /* Free EDMA PaRAM slots */
1648         for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1649                 if (echan->slot[i] >= 0) {
1650                         edma_free_slot(echan->ecc, echan->slot[i]);
1651                         echan->slot[i] = -1;
1652                 }
1653         }
1654 
1655         /* Set entry slot to the dummy slot */
1656         edma_set_chmap(echan, echan->ecc->dummy_slot);
1657 
1658         /* Free EDMA channel */
1659         if (echan->alloced) {
1660                 edma_free_channel(echan);
1661                 echan->alloced = false;
1662         }
1663 
1664         echan->tc = NULL;
1665         echan->hw_triggered = false;
1666 
1667         dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1668                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1669 }
1670 
1671 /* Send pending descriptor to hardware */
1672 static void edma_issue_pending(struct dma_chan *chan)
1673 {
1674         struct edma_chan *echan = to_edma_chan(chan);
1675         unsigned long flags;
1676 
1677         spin_lock_irqsave(&echan->vchan.lock, flags);
1678         if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1679                 edma_execute(echan);
1680         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1681 }
1682 
1683 /*
1684  * This limit exists to avoid a possible infinite loop when waiting for proof
1685  * that a particular transfer is completed. This limit can be hit if there
1686  * are large bursts to/from slow devices or the CPU is never able to catch
1687  * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1688  * RX-FIFO, as many as 55 loops have been seen.
1689  */
1690 #define EDMA_MAX_TR_WAIT_LOOPS 1000
1691 
1692 static u32 edma_residue(struct edma_desc *edesc)
1693 {
1694         bool dst = edesc->direction == DMA_DEV_TO_MEM;
1695         int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1696         struct edma_chan *echan = edesc->echan;
1697         struct edma_pset *pset = edesc->pset;
1698         dma_addr_t done, pos;
1699         int i;
1700 
1701         /*
1702          * We always read the dst/src position from the first RamPar
1703          * pset. That's the one which is active now.
1704          */
1705         pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1706 
1707         /*
1708          * "pos" may represent a transfer request that is still being
1709          * processed by the EDMACC or EDMATC. We will busy wait until
1710          * any one of the situations occurs:
1711          *   1. the DMA hardware is idle
1712          *   2. a new transfer request is setup
1713          *   3. we hit the loop limit
1714          */
1715         while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
1716                 /* check if a new transfer request is setup */
1717                 if (edma_get_position(echan->ecc,
1718                                       echan->slot[0], dst) != pos) {
1719                         break;
1720                 }
1721 
1722                 if (!--loop_count) {
1723                         dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1724                                 "%s: timeout waiting for PaRAM update\n",
1725                                 __func__);
1726                         break;
1727                 }
1728 
1729                 cpu_relax();
1730         }
1731 
1732         /*
1733          * Cyclic is simple. Just subtract pset[0].addr from pos.
1734          *
1735          * We never update edesc->residue in the cyclic case, so we
1736          * can tell the remaining room to the end of the circular
1737          * buffer.
1738          */
1739         if (edesc->cyclic) {
1740                 done = pos - pset->addr;
1741                 edesc->residue_stat = edesc->residue - done;
1742                 return edesc->residue_stat;
1743         }
1744 
1745         /*
1746          * For SG operation we catch up with the last processed
1747          * status.
1748          */
1749         pset += edesc->processed_stat;
1750 
1751         for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1752                 /*
1753                  * If we are inside this pset address range, we know
1754                  * this is the active one. Get the current delta and
1755                  * stop walking the psets.
1756                  */
1757                 if (pos >= pset->addr && pos < pset->addr + pset->len)
1758                         return edesc->residue_stat - (pos - pset->addr);
1759 
1760                 /* Otherwise mark it done and update residue_stat. */
1761                 edesc->processed_stat++;
1762                 edesc->residue_stat -= pset->len;
1763         }
1764         return edesc->residue_stat;
1765 }
1766 
1767 /* Check request completion status */
1768 static enum dma_status edma_tx_status(struct dma_chan *chan,
1769                                       dma_cookie_t cookie,
1770                                       struct dma_tx_state *txstate)
1771 {
1772         struct edma_chan *echan = to_edma_chan(chan);
1773         struct virt_dma_desc *vdesc;
1774         enum dma_status ret;
1775         unsigned long flags;
1776 
1777         ret = dma_cookie_status(chan, cookie, txstate);
1778         if (ret == DMA_COMPLETE || !txstate)
1779                 return ret;
1780 
1781         spin_lock_irqsave(&echan->vchan.lock, flags);
1782         if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1783                 txstate->residue = edma_residue(echan->edesc);
1784         else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1785                 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1786         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1787 
1788         return ret;
1789 }
1790 
1791 static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1792 {
1793         if (!memcpy_channels)
1794                 return false;
1795         while (*memcpy_channels != -1) {
1796                 if (*memcpy_channels == ch_num)
1797                         return true;
1798                 memcpy_channels++;
1799         }
1800         return false;
1801 }
1802 
1803 #define EDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1804                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1805                                  BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1806                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1807 
1808 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1809 {
1810         struct dma_device *s_ddev = &ecc->dma_slave;
1811         struct dma_device *m_ddev = NULL;
1812         s32 *memcpy_channels = ecc->info->memcpy_channels;
1813         int i, j;
1814 
1815         dma_cap_zero(s_ddev->cap_mask);
1816         dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1817         dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1818         if (ecc->legacy_mode && !memcpy_channels) {
1819                 dev_warn(ecc->dev,
1820                          "Legacy memcpy is enabled, things might not work\n");
1821 
1822                 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1823                 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1824                 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1825         }
1826 
1827         s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1828         s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1829         s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1830         s_ddev->device_free_chan_resources = edma_free_chan_resources;
1831         s_ddev->device_issue_pending = edma_issue_pending;
1832         s_ddev->device_tx_status = edma_tx_status;
1833         s_ddev->device_config = edma_slave_config;
1834         s_ddev->device_pause = edma_dma_pause;
1835         s_ddev->device_resume = edma_dma_resume;
1836         s_ddev->device_terminate_all = edma_terminate_all;
1837         s_ddev->device_synchronize = edma_synchronize;
1838 
1839         s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1840         s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1841         s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1842         s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1843 
1844         s_ddev->dev = ecc->dev;
1845         INIT_LIST_HEAD(&s_ddev->channels);
1846 
1847         if (memcpy_channels) {
1848                 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1849                 ecc->dma_memcpy = m_ddev;
1850 
1851                 dma_cap_zero(m_ddev->cap_mask);
1852                 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1853 
1854                 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1855                 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1856                 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1857                 m_ddev->device_issue_pending = edma_issue_pending;
1858                 m_ddev->device_tx_status = edma_tx_status;
1859                 m_ddev->device_config = edma_slave_config;
1860                 m_ddev->device_pause = edma_dma_pause;
1861                 m_ddev->device_resume = edma_dma_resume;
1862                 m_ddev->device_terminate_all = edma_terminate_all;
1863                 m_ddev->device_synchronize = edma_synchronize;
1864 
1865                 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1866                 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1867                 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1868                 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1869 
1870                 m_ddev->dev = ecc->dev;
1871                 INIT_LIST_HEAD(&m_ddev->channels);
1872         } else if (!ecc->legacy_mode) {
1873                 dev_info(ecc->dev, "memcpy is disabled\n");
1874         }
1875 
1876         for (i = 0; i < ecc->num_channels; i++) {
1877                 struct edma_chan *echan = &ecc->slave_chans[i];
1878                 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1879                 echan->ecc = ecc;
1880                 echan->vchan.desc_free = edma_desc_free;
1881 
1882                 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1883                         vchan_init(&echan->vchan, m_ddev);
1884                 else
1885                         vchan_init(&echan->vchan, s_ddev);
1886 
1887                 INIT_LIST_HEAD(&echan->node);
1888                 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1889                         echan->slot[j] = -1;
1890         }
1891 }
1892 
1893 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1894                               struct edma_cc *ecc)
1895 {
1896         int i;
1897         u32 value, cccfg;
1898         s8 (*queue_priority_map)[2];
1899 
1900         /* Decode the eDMA3 configuration from CCCFG register */
1901         cccfg = edma_read(ecc, EDMA_CCCFG);
1902 
1903         value = GET_NUM_REGN(cccfg);
1904         ecc->num_region = BIT(value);
1905 
1906         value = GET_NUM_DMACH(cccfg);
1907         ecc->num_channels = BIT(value + 1);
1908 
1909         value = GET_NUM_QDMACH(cccfg);
1910         ecc->num_qchannels = value * 2;
1911 
1912         value = GET_NUM_PAENTRY(cccfg);
1913         ecc->num_slots = BIT(value + 4);
1914 
1915         value = GET_NUM_EVQUE(cccfg);
1916         ecc->num_tc = value + 1;
1917 
1918         ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1919 
1920         dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1921         dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1922         dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1923         dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
1924         dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1925         dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1926         dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1927 
1928         /* Nothing need to be done if queue priority is provided */
1929         if (pdata->queue_priority_mapping)
1930                 return 0;
1931 
1932         /*
1933          * Configure TC/queue priority as follows:
1934          * Q0 - priority 0
1935          * Q1 - priority 1
1936          * Q2 - priority 2
1937          * ...
1938          * The meaning of priority numbers: 0 highest priority, 7 lowest
1939          * priority. So Q0 is the highest priority queue and the last queue has
1940          * the lowest priority.
1941          */
1942         queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1943                                           GFP_KERNEL);
1944         if (!queue_priority_map)
1945                 return -ENOMEM;
1946 
1947         for (i = 0; i < ecc->num_tc; i++) {
1948                 queue_priority_map[i][0] = i;
1949                 queue_priority_map[i][1] = i;
1950         }
1951         queue_priority_map[i][0] = -1;
1952         queue_priority_map[i][1] = -1;
1953 
1954         pdata->queue_priority_mapping = queue_priority_map;
1955         /* Default queue has the lowest priority */
1956         pdata->default_queue = i - 1;
1957 
1958         return 0;
1959 }
1960 
1961 #if IS_ENABLED(CONFIG_OF)
1962 static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1963                                size_t sz)
1964 {
1965         const char pname[] = "ti,edma-xbar-event-map";
1966         struct resource res;
1967         void __iomem *xbar;
1968         s16 (*xbar_chans)[2];
1969         size_t nelm = sz / sizeof(s16);
1970         u32 shift, offset, mux;
1971         int ret, i;
1972 
1973         xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
1974         if (!xbar_chans)
1975                 return -ENOMEM;
1976 
1977         ret = of_address_to_resource(dev->of_node, 1, &res);
1978         if (ret)
1979                 return -ENOMEM;
1980 
1981         xbar = devm_ioremap(dev, res.start, resource_size(&res));
1982         if (!xbar)
1983                 return -ENOMEM;
1984 
1985         ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
1986                                          nelm);
1987         if (ret)
1988                 return -EIO;
1989 
1990         /* Invalidate last entry for the other user of this mess */
1991         nelm >>= 1;
1992         xbar_chans[nelm][0] = -1;
1993         xbar_chans[nelm][1] = -1;
1994 
1995         for (i = 0; i < nelm; i++) {
1996                 shift = (xbar_chans[i][1] & 0x03) << 3;
1997                 offset = xbar_chans[i][1] & 0xfffffffc;
1998                 mux = readl(xbar + offset);
1999                 mux &= ~(0xff << shift);
2000                 mux |= xbar_chans[i][0] << shift;
2001                 writel(mux, (xbar + offset));
2002         }
2003 
2004         pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2005         return 0;
2006 }
2007 
2008 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2009                                                      bool legacy_mode)
2010 {
2011         struct edma_soc_info *info;
2012         struct property *prop;
2013         size_t sz;
2014         int ret;
2015 
2016         info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2017         if (!info)
2018                 return ERR_PTR(-ENOMEM);
2019 
2020         if (legacy_mode) {
2021                 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
2022                                         &sz);
2023                 if (prop) {
2024                         ret = edma_xbar_event_map(dev, info, sz);
2025                         if (ret)
2026                                 return ERR_PTR(ret);
2027                 }
2028                 return info;
2029         }
2030 
2031         /* Get the list of channels allocated to be used for memcpy */
2032         prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2033         if (prop) {
2034                 const char pname[] = "ti,edma-memcpy-channels";
2035                 size_t nelm = sz / sizeof(s32);
2036                 s32 *memcpy_ch;
2037 
2038                 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2039                                          GFP_KERNEL);
2040                 if (!memcpy_ch)
2041                         return ERR_PTR(-ENOMEM);
2042 
2043                 ret = of_property_read_u32_array(dev->of_node, pname,
2044                                                  (u32 *)memcpy_ch, nelm);
2045                 if (ret)
2046                         return ERR_PTR(ret);
2047 
2048                 memcpy_ch[nelm] = -1;
2049                 info->memcpy_channels = memcpy_ch;
2050         }
2051 
2052         prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2053                                 &sz);
2054         if (prop) {
2055                 const char pname[] = "ti,edma-reserved-slot-ranges";
2056                 u32 (*tmp)[2];
2057                 s16 (*rsv_slots)[2];
2058                 size_t nelm = sz / sizeof(*tmp);
2059                 struct edma_rsv_info *rsv_info;
2060                 int i;
2061 
2062                 if (!nelm)
2063                         return info;
2064 
2065                 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2066                 if (!tmp)
2067                         return ERR_PTR(-ENOMEM);
2068 
2069                 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2070                 if (!rsv_info) {
2071                         kfree(tmp);
2072                         return ERR_PTR(-ENOMEM);
2073                 }
2074 
2075                 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2076                                          GFP_KERNEL);
2077                 if (!rsv_slots) {
2078                         kfree(tmp);
2079                         return ERR_PTR(-ENOMEM);
2080                 }
2081 
2082                 ret = of_property_read_u32_array(dev->of_node, pname,
2083                                                  (u32 *)tmp, nelm * 2);
2084                 if (ret) {
2085                         kfree(tmp);
2086                         return ERR_PTR(ret);
2087                 }
2088 
2089                 for (i = 0; i < nelm; i++) {
2090                         rsv_slots[i][0] = tmp[i][0];
2091                         rsv_slots[i][1] = tmp[i][1];
2092                 }
2093                 rsv_slots[nelm][0] = -1;
2094                 rsv_slots[nelm][1] = -1;
2095 
2096                 info->rsv = rsv_info;
2097                 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2098 
2099                 kfree(tmp);
2100         }
2101 
2102         return info;
2103 }
2104 
2105 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2106                                       struct of_dma *ofdma)
2107 {
2108         struct edma_cc *ecc = ofdma->of_dma_data;
2109         struct dma_chan *chan = NULL;
2110         struct edma_chan *echan;
2111         int i;
2112 
2113         if (!ecc || dma_spec->args_count < 1)
2114                 return NULL;
2115 
2116         for (i = 0; i < ecc->num_channels; i++) {
2117                 echan = &ecc->slave_chans[i];
2118                 if (echan->ch_num == dma_spec->args[0]) {
2119                         chan = &echan->vchan.chan;
2120                         break;
2121                 }
2122         }
2123 
2124         if (!chan)
2125                 return NULL;
2126 
2127         if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2128                 goto out;
2129 
2130         if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2131             dma_spec->args[1] < echan->ecc->num_tc) {
2132                 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2133                 goto out;
2134         }
2135 
2136         return NULL;
2137 out:
2138         /* The channel is going to be used as HW synchronized */
2139         echan->hw_triggered = true;
2140         return dma_get_slave_channel(chan);
2141 }
2142 #else
2143 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2144                                                      bool legacy_mode)
2145 {
2146         return ERR_PTR(-EINVAL);
2147 }
2148 
2149 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2150                                       struct of_dma *ofdma)
2151 {
2152         return NULL;
2153 }
2154 #endif
2155 
2156 static int edma_probe(struct platform_device *pdev)
2157 {
2158         struct edma_soc_info    *info = pdev->dev.platform_data;
2159         s8                      (*queue_priority_mapping)[2];
2160         int                     i, off, ln;
2161         const s16               (*rsv_slots)[2];
2162         const s16               (*xbar_chans)[2];
2163         int                     irq;
2164         char                    *irq_name;
2165         struct resource         *mem;
2166         struct device_node      *node = pdev->dev.of_node;
2167         struct device           *dev = &pdev->dev;
2168         struct edma_cc          *ecc;
2169         bool                    legacy_mode = true;
2170         int ret;
2171 
2172         if (node) {
2173                 const struct of_device_id *match;
2174 
2175                 match = of_match_node(edma_of_ids, node);
2176                 if (match && (u32)match->data == EDMA_BINDING_TPCC)
2177                         legacy_mode = false;
2178 
2179                 info = edma_setup_info_from_dt(dev, legacy_mode);
2180                 if (IS_ERR(info)) {
2181                         dev_err(dev, "failed to get DT data\n");
2182                         return PTR_ERR(info);
2183                 }
2184         }
2185 
2186         if (!info)
2187                 return -ENODEV;
2188 
2189         pm_runtime_enable(dev);
2190         ret = pm_runtime_get_sync(dev);
2191         if (ret < 0) {
2192                 dev_err(dev, "pm_runtime_get_sync() failed\n");
2193                 return ret;
2194         }
2195 
2196         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2197         if (ret)
2198                 return ret;
2199 
2200         ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2201         if (!ecc) {
2202                 dev_err(dev, "Can't allocate controller\n");
2203                 return -ENOMEM;
2204         }
2205 
2206         ecc->dev = dev;
2207         ecc->id = pdev->id;
2208         ecc->legacy_mode = legacy_mode;
2209         /* When booting with DT the pdev->id is -1 */
2210         if (ecc->id < 0)
2211                 ecc->id = 0;
2212 
2213         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2214         if (!mem) {
2215                 dev_dbg(dev, "mem resource not found, using index 0\n");
2216                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2217                 if (!mem) {
2218                         dev_err(dev, "no mem resource?\n");
2219                         return -ENODEV;
2220                 }
2221         }
2222         ecc->base = devm_ioremap_resource(dev, mem);
2223         if (IS_ERR(ecc->base))
2224                 return PTR_ERR(ecc->base);
2225 
2226         platform_set_drvdata(pdev, ecc);
2227 
2228         /* Get eDMA3 configuration from IP */
2229         ret = edma_setup_from_hw(dev, info, ecc);
2230         if (ret)
2231                 return ret;
2232 
2233         /* Allocate memory based on the information we got from the IP */
2234         ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2235                                         sizeof(*ecc->slave_chans), GFP_KERNEL);
2236         if (!ecc->slave_chans)
2237                 return -ENOMEM;
2238 
2239         ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2240                                        sizeof(unsigned long), GFP_KERNEL);
2241         if (!ecc->slot_inuse)
2242                 return -ENOMEM;
2243 
2244         ecc->default_queue = info->default_queue;
2245 
2246         for (i = 0; i < ecc->num_slots; i++)
2247                 edma_write_slot(ecc, i, &dummy_paramset);
2248 
2249         if (info->rsv) {
2250                 /* Set the reserved slots in inuse list */
2251                 rsv_slots = info->rsv->rsv_slots;
2252                 if (rsv_slots) {
2253                         for (i = 0; rsv_slots[i][0] != -1; i++) {
2254                                 off = rsv_slots[i][0];
2255                                 ln = rsv_slots[i][1];
2256                                 set_bits(off, ln, ecc->slot_inuse);
2257                         }
2258                 }
2259         }
2260 
2261         /* Clear the xbar mapped channels in unused list */
2262         xbar_chans = info->xbar_chans;
2263         if (xbar_chans) {
2264                 for (i = 0; xbar_chans[i][1] != -1; i++) {
2265                         off = xbar_chans[i][1];
2266                 }
2267         }
2268 
2269         irq = platform_get_irq_byname(pdev, "edma3_ccint");
2270         if (irq < 0 && node)
2271                 irq = irq_of_parse_and_map(node, 0);
2272 
2273         if (irq >= 0) {
2274                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2275                                           dev_name(dev));
2276                 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2277                                        ecc);
2278                 if (ret) {
2279                         dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2280                         return ret;
2281                 }
2282         }
2283 
2284         irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2285         if (irq < 0 && node)
2286                 irq = irq_of_parse_and_map(node, 2);
2287 
2288         if (irq >= 0) {
2289                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2290                                           dev_name(dev));
2291                 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2292                                        ecc);
2293                 if (ret) {
2294                         dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2295                         return ret;
2296                 }
2297         }
2298 
2299         ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2300         if (ecc->dummy_slot < 0) {
2301                 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2302                 return ecc->dummy_slot;
2303         }
2304 
2305         queue_priority_mapping = info->queue_priority_mapping;
2306 
2307         if (!ecc->legacy_mode) {
2308                 int lowest_priority = 0;
2309                 struct of_phandle_args tc_args;
2310 
2311                 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2312                                             sizeof(*ecc->tc_list), GFP_KERNEL);
2313                 if (!ecc->tc_list)
2314                         return -ENOMEM;
2315 
2316                 for (i = 0;; i++) {
2317                         ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2318                                                                1, i, &tc_args);
2319                         if (ret || i == ecc->num_tc)
2320                                 break;
2321 
2322                         ecc->tc_list[i].node = tc_args.np;
2323                         ecc->tc_list[i].id = i;
2324                         queue_priority_mapping[i][1] = tc_args.args[0];
2325                         if (queue_priority_mapping[i][1] > lowest_priority) {
2326                                 lowest_priority = queue_priority_mapping[i][1];
2327                                 info->default_queue = i;
2328                         }
2329                 }
2330         }
2331 
2332         /* Event queue priority mapping */
2333         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2334                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2335                                               queue_priority_mapping[i][1]);
2336 
2337         for (i = 0; i < ecc->num_region; i++) {
2338                 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2339                 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2340                 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2341         }
2342         ecc->info = info;
2343 
2344         /* Init the dma device and channels */
2345         edma_dma_init(ecc, legacy_mode);
2346 
2347         for (i = 0; i < ecc->num_channels; i++) {
2348                 /* Assign all channels to the default queue */
2349                 edma_assign_channel_eventq(&ecc->slave_chans[i],
2350                                            info->default_queue);
2351                 /* Set entry slot to the dummy slot */
2352                 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2353         }
2354 
2355         ecc->dma_slave.filter.map = info->slave_map;
2356         ecc->dma_slave.filter.mapcnt = info->slavecnt;
2357         ecc->dma_slave.filter.fn = edma_filter_fn;
2358 
2359         ret = dma_async_device_register(&ecc->dma_slave);
2360         if (ret) {
2361                 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2362                 goto err_reg1;
2363         }
2364 
2365         if (ecc->dma_memcpy) {
2366                 ret = dma_async_device_register(ecc->dma_memcpy);
2367                 if (ret) {
2368                         dev_err(dev, "memcpy ddev registration failed (%d)\n",
2369                                 ret);
2370                         dma_async_device_unregister(&ecc->dma_slave);
2371                         goto err_reg1;
2372                 }
2373         }
2374 
2375         if (node)
2376                 of_dma_controller_register(node, of_edma_xlate, ecc);
2377 
2378         dev_info(dev, "TI EDMA DMA engine driver\n");
2379 
2380         return 0;
2381 
2382 err_reg1:
2383         edma_free_slot(ecc, ecc->dummy_slot);
2384         return ret;
2385 }
2386 
2387 static int edma_remove(struct platform_device *pdev)
2388 {
2389         struct device *dev = &pdev->dev;
2390         struct edma_cc *ecc = dev_get_drvdata(dev);
2391 
2392         if (dev->of_node)
2393                 of_dma_controller_free(dev->of_node);
2394         dma_async_device_unregister(&ecc->dma_slave);
2395         if (ecc->dma_memcpy)
2396                 dma_async_device_unregister(ecc->dma_memcpy);
2397         edma_free_slot(ecc, ecc->dummy_slot);
2398 
2399         return 0;
2400 }
2401 
2402 #ifdef CONFIG_PM_SLEEP
2403 static int edma_pm_suspend(struct device *dev)
2404 {
2405         struct edma_cc *ecc = dev_get_drvdata(dev);
2406         struct edma_chan *echan = ecc->slave_chans;
2407         int i;
2408 
2409         for (i = 0; i < ecc->num_channels; i++) {
2410                 if (echan[i].alloced)
2411                         edma_setup_interrupt(&echan[i], false);
2412         }
2413 
2414         return 0;
2415 }
2416 
2417 static int edma_pm_resume(struct device *dev)
2418 {
2419         struct edma_cc *ecc = dev_get_drvdata(dev);
2420         struct edma_chan *echan = ecc->slave_chans;
2421         int i;
2422         s8 (*queue_priority_mapping)[2];
2423 
2424         queue_priority_mapping = ecc->info->queue_priority_mapping;
2425 
2426         /* Event queue priority mapping */
2427         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2428                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2429                                               queue_priority_mapping[i][1]);
2430 
2431         for (i = 0; i < ecc->num_channels; i++) {
2432                 if (echan[i].alloced) {
2433                         /* ensure access through shadow region 0 */
2434                         edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2435                                        BIT(i & 0x1f));
2436 
2437                         edma_setup_interrupt(&echan[i], true);
2438 
2439                         /* Set up channel -> slot mapping for the entry slot */
2440                         edma_set_chmap(&echan[i], echan[i].slot[0]);
2441                 }
2442         }
2443 
2444         return 0;
2445 }
2446 #endif
2447 
2448 static const struct dev_pm_ops edma_pm_ops = {
2449         SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2450 };
2451 
2452 static struct platform_driver edma_driver = {
2453         .probe          = edma_probe,
2454         .remove         = edma_remove,
2455         .driver = {
2456                 .name   = "edma",
2457                 .pm     = &edma_pm_ops,
2458                 .of_match_table = edma_of_ids,
2459         },
2460 };
2461 
2462 static int edma_tptc_probe(struct platform_device *pdev)
2463 {
2464         pm_runtime_enable(&pdev->dev);
2465         return pm_runtime_get_sync(&pdev->dev);
2466 }
2467 
2468 static struct platform_driver edma_tptc_driver = {
2469         .probe          = edma_tptc_probe,
2470         .driver = {
2471                 .name   = "edma3-tptc",
2472                 .of_match_table = edma_tptc_of_ids,
2473         },
2474 };
2475 
2476 bool edma_filter_fn(struct dma_chan *chan, void *param)
2477 {
2478         bool match = false;
2479 
2480         if (chan->device->dev->driver == &edma_driver.driver) {
2481                 struct edma_chan *echan = to_edma_chan(chan);
2482                 unsigned ch_req = *(unsigned *)param;
2483                 if (ch_req == echan->ch_num) {
2484                         /* The channel is going to be used as HW synchronized */
2485                         echan->hw_triggered = true;
2486                         match = true;
2487                 }
2488         }
2489         return match;
2490 }
2491 EXPORT_SYMBOL(edma_filter_fn);
2492 
2493 static int edma_init(void)
2494 {
2495         int ret;
2496 
2497         ret = platform_driver_register(&edma_tptc_driver);
2498         if (ret)
2499                 return ret;
2500 
2501         return platform_driver_register(&edma_driver);
2502 }
2503 subsys_initcall(edma_init);
2504 
2505 static void __exit edma_exit(void)
2506 {
2507         platform_driver_unregister(&edma_driver);
2508         platform_driver_unregister(&edma_tptc_driver);
2509 }
2510 module_exit(edma_exit);
2511 
2512 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2513 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2514 MODULE_LICENSE("GPL v2");
2515 

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