Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/dma/edma.c

  1 /*
  2  * TI EDMA DMA engine driver
  3  *
  4  * Copyright 2012 Texas Instruments
  5  *
  6  * This program is free software; you can redistribute it and/or
  7  * modify it under the terms of the GNU General Public License as
  8  * published by the Free Software Foundation version 2.
  9  *
 10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 11  * kind, whether express or implied; without even the implied warranty
 12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/dmaengine.h>
 17 #include <linux/dma-mapping.h>
 18 #include <linux/edma.h>
 19 #include <linux/err.h>
 20 #include <linux/init.h>
 21 #include <linux/interrupt.h>
 22 #include <linux/list.h>
 23 #include <linux/module.h>
 24 #include <linux/platform_device.h>
 25 #include <linux/slab.h>
 26 #include <linux/spinlock.h>
 27 #include <linux/of.h>
 28 #include <linux/of_dma.h>
 29 #include <linux/of_irq.h>
 30 #include <linux/of_address.h>
 31 #include <linux/of_device.h>
 32 #include <linux/pm_runtime.h>
 33 
 34 #include <linux/platform_data/edma.h>
 35 
 36 #include "dmaengine.h"
 37 #include "virt-dma.h"
 38 
 39 /* Offsets matching "struct edmacc_param" */
 40 #define PARM_OPT                0x00
 41 #define PARM_SRC                0x04
 42 #define PARM_A_B_CNT            0x08
 43 #define PARM_DST                0x0c
 44 #define PARM_SRC_DST_BIDX       0x10
 45 #define PARM_LINK_BCNTRLD       0x14
 46 #define PARM_SRC_DST_CIDX       0x18
 47 #define PARM_CCNT               0x1c
 48 
 49 #define PARM_SIZE               0x20
 50 
 51 /* Offsets for EDMA CC global channel registers and their shadows */
 52 #define SH_ER                   0x00    /* 64 bits */
 53 #define SH_ECR                  0x08    /* 64 bits */
 54 #define SH_ESR                  0x10    /* 64 bits */
 55 #define SH_CER                  0x18    /* 64 bits */
 56 #define SH_EER                  0x20    /* 64 bits */
 57 #define SH_EECR                 0x28    /* 64 bits */
 58 #define SH_EESR                 0x30    /* 64 bits */
 59 #define SH_SER                  0x38    /* 64 bits */
 60 #define SH_SECR                 0x40    /* 64 bits */
 61 #define SH_IER                  0x50    /* 64 bits */
 62 #define SH_IECR                 0x58    /* 64 bits */
 63 #define SH_IESR                 0x60    /* 64 bits */
 64 #define SH_IPR                  0x68    /* 64 bits */
 65 #define SH_ICR                  0x70    /* 64 bits */
 66 #define SH_IEVAL                0x78
 67 #define SH_QER                  0x80
 68 #define SH_QEER                 0x84
 69 #define SH_QEECR                0x88
 70 #define SH_QEESR                0x8c
 71 #define SH_QSER                 0x90
 72 #define SH_QSECR                0x94
 73 #define SH_SIZE                 0x200
 74 
 75 /* Offsets for EDMA CC global registers */
 76 #define EDMA_REV                0x0000
 77 #define EDMA_CCCFG              0x0004
 78 #define EDMA_QCHMAP             0x0200  /* 8 registers */
 79 #define EDMA_DMAQNUM            0x0240  /* 8 registers (4 on OMAP-L1xx) */
 80 #define EDMA_QDMAQNUM           0x0260
 81 #define EDMA_QUETCMAP           0x0280
 82 #define EDMA_QUEPRI             0x0284
 83 #define EDMA_EMR                0x0300  /* 64 bits */
 84 #define EDMA_EMCR               0x0308  /* 64 bits */
 85 #define EDMA_QEMR               0x0310
 86 #define EDMA_QEMCR              0x0314
 87 #define EDMA_CCERR              0x0318
 88 #define EDMA_CCERRCLR           0x031c
 89 #define EDMA_EEVAL              0x0320
 90 #define EDMA_DRAE               0x0340  /* 4 x 64 bits*/
 91 #define EDMA_QRAE               0x0380  /* 4 registers */
 92 #define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
 93 #define EDMA_QSTAT              0x0600  /* 2 registers */
 94 #define EDMA_QWMTHRA            0x0620
 95 #define EDMA_QWMTHRB            0x0624
 96 #define EDMA_CCSTAT             0x0640
 97 
 98 #define EDMA_M                  0x1000  /* global channel registers */
 99 #define EDMA_ECR                0x1008
100 #define EDMA_ECRH               0x100C
101 #define EDMA_SHADOW0            0x2000  /* 4 shadow regions */
102 #define EDMA_PARM               0x4000  /* PaRAM entries */
103 
104 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
105 
106 #define EDMA_DCHMAP             0x0100  /* 64 registers */
107 
108 /* CCCFG register */
109 #define GET_NUM_DMACH(x)        (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x)       ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x)      ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x)        ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x)         ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST             BIT(24)
115 
116 /* CCSTAT register */
117 #define EDMA_CCSTAT_ACTV        BIT(4)
118 
119 /*
120  * Max of 20 segments per channel to conserve PaRAM slots
121  * Also note that MAX_NR_SG should be atleast the no.of periods
122  * that are required for ASoC, otherwise DMA prep calls will
123  * fail. Today davinci-pcm is the only user of this driver and
124  * requires atleast 17 slots, so we setup the default to 20.
125  */
126 #define MAX_NR_SG               20
127 #define EDMA_MAX_SLOTS          MAX_NR_SG
128 #define EDMA_DESCRIPTORS        16
129 
130 #define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
131 #define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
132 #define EDMA_CONT_PARAMS_ANY             1001
133 #define EDMA_CONT_PARAMS_FIXED_EXACT     1002
134 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135 
136 /* PaRAM slots are laid out like this */
137 struct edmacc_param {
138         u32 opt;
139         u32 src;
140         u32 a_b_cnt;
141         u32 dst;
142         u32 src_dst_bidx;
143         u32 link_bcntrld;
144         u32 src_dst_cidx;
145         u32 ccnt;
146 } __packed;
147 
148 /* fields in edmacc_param.opt */
149 #define SAM             BIT(0)
150 #define DAM             BIT(1)
151 #define SYNCDIM         BIT(2)
152 #define STATIC          BIT(3)
153 #define EDMA_FWID       (0x07 << 8)
154 #define TCCMODE         BIT(11)
155 #define EDMA_TCC(t)     ((t) << 12)
156 #define TCINTEN         BIT(20)
157 #define ITCINTEN        BIT(21)
158 #define TCCHEN          BIT(22)
159 #define ITCCHEN         BIT(23)
160 
161 struct edma_pset {
162         u32                             len;
163         dma_addr_t                      addr;
164         struct edmacc_param             param;
165 };
166 
167 struct edma_desc {
168         struct virt_dma_desc            vdesc;
169         struct list_head                node;
170         enum dma_transfer_direction     direction;
171         int                             cyclic;
172         int                             absync;
173         int                             pset_nr;
174         struct edma_chan                *echan;
175         int                             processed;
176 
177         /*
178          * The following 4 elements are used for residue accounting.
179          *
180          * - processed_stat: the number of SG elements we have traversed
181          * so far to cover accounting. This is updated directly to processed
182          * during edma_callback and is always <= processed, because processed
183          * refers to the number of pending transfer (programmed to EDMA
184          * controller), where as processed_stat tracks number of transfers
185          * accounted for so far.
186          *
187          * - residue: The amount of bytes we have left to transfer for this desc
188          *
189          * - residue_stat: The residue in bytes of data we have covered
190          * so far for accounting. This is updated directly to residue
191          * during callbacks to keep it current.
192          *
193          * - sg_len: Tracks the length of the current intermediate transfer,
194          * this is required to update the residue during intermediate transfer
195          * completion callback.
196          */
197         int                             processed_stat;
198         u32                             sg_len;
199         u32                             residue;
200         u32                             residue_stat;
201 
202         struct edma_pset                pset[0];
203 };
204 
205 struct edma_cc;
206 
207 struct edma_tc {
208         struct device_node              *node;
209         u16                             id;
210 };
211 
212 struct edma_chan {
213         struct virt_dma_chan            vchan;
214         struct list_head                node;
215         struct edma_desc                *edesc;
216         struct edma_cc                  *ecc;
217         struct edma_tc                  *tc;
218         int                             ch_num;
219         bool                            alloced;
220         bool                            hw_triggered;
221         int                             slot[EDMA_MAX_SLOTS];
222         int                             missed;
223         struct dma_slave_config         cfg;
224 };
225 
226 struct edma_cc {
227         struct device                   *dev;
228         struct edma_soc_info            *info;
229         void __iomem                    *base;
230         int                             id;
231         bool                            legacy_mode;
232 
233         /* eDMA3 resource information */
234         unsigned                        num_channels;
235         unsigned                        num_qchannels;
236         unsigned                        num_region;
237         unsigned                        num_slots;
238         unsigned                        num_tc;
239         bool                            chmap_exist;
240         enum dma_event_q                default_queue;
241 
242         unsigned int                    ccint;
243         unsigned int                    ccerrint;
244 
245         /*
246          * The slot_inuse bit for each PaRAM slot is clear unless the slot is
247          * in use by Linux or if it is allocated to be used by DSP.
248          */
249         unsigned long *slot_inuse;
250 
251         struct dma_device               dma_slave;
252         struct dma_device               *dma_memcpy;
253         struct edma_chan                *slave_chans;
254         struct edma_tc                  *tc_list;
255         int                             dummy_slot;
256 };
257 
258 /* dummy param set used to (re)initialize parameter RAM slots */
259 static const struct edmacc_param dummy_paramset = {
260         .link_bcntrld = 0xffff,
261         .ccnt = 1,
262 };
263 
264 #define EDMA_BINDING_LEGACY     0
265 #define EDMA_BINDING_TPCC       1
266 static const struct of_device_id edma_of_ids[] = {
267         {
268                 .compatible = "ti,edma3",
269                 .data = (void *)EDMA_BINDING_LEGACY,
270         },
271         {
272                 .compatible = "ti,edma3-tpcc",
273                 .data = (void *)EDMA_BINDING_TPCC,
274         },
275         {}
276 };
277 
278 static const struct of_device_id edma_tptc_of_ids[] = {
279         { .compatible = "ti,edma3-tptc", },
280         {}
281 };
282 
283 static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
284 {
285         return (unsigned int)__raw_readl(ecc->base + offset);
286 }
287 
288 static inline void edma_write(struct edma_cc *ecc, int offset, int val)
289 {
290         __raw_writel(val, ecc->base + offset);
291 }
292 
293 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
294                                unsigned or)
295 {
296         unsigned val = edma_read(ecc, offset);
297 
298         val &= and;
299         val |= or;
300         edma_write(ecc, offset, val);
301 }
302 
303 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
304 {
305         unsigned val = edma_read(ecc, offset);
306 
307         val &= and;
308         edma_write(ecc, offset, val);
309 }
310 
311 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
312 {
313         unsigned val = edma_read(ecc, offset);
314 
315         val |= or;
316         edma_write(ecc, offset, val);
317 }
318 
319 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
320                                            int i)
321 {
322         return edma_read(ecc, offset + (i << 2));
323 }
324 
325 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
326                                     unsigned val)
327 {
328         edma_write(ecc, offset + (i << 2), val);
329 }
330 
331 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
332                                      unsigned and, unsigned or)
333 {
334         edma_modify(ecc, offset + (i << 2), and, or);
335 }
336 
337 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
338                                  unsigned or)
339 {
340         edma_or(ecc, offset + (i << 2), or);
341 }
342 
343 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
344                                   unsigned or)
345 {
346         edma_or(ecc, offset + ((i * 2 + j) << 2), or);
347 }
348 
349 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
350                                      int j, unsigned val)
351 {
352         edma_write(ecc, offset + ((i * 2 + j) << 2), val);
353 }
354 
355 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
356 {
357         return edma_read(ecc, EDMA_SHADOW0 + offset);
358 }
359 
360 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
361                                                    int offset, int i)
362 {
363         return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
364 }
365 
366 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
367                                       unsigned val)
368 {
369         edma_write(ecc, EDMA_SHADOW0 + offset, val);
370 }
371 
372 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
373                                             int i, unsigned val)
374 {
375         edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
376 }
377 
378 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
379                                            int param_no)
380 {
381         return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
382 }
383 
384 static inline void edma_param_write(struct edma_cc *ecc, int offset,
385                                     int param_no, unsigned val)
386 {
387         edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
388 }
389 
390 static inline void edma_param_modify(struct edma_cc *ecc, int offset,
391                                      int param_no, unsigned and, unsigned or)
392 {
393         edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
394 }
395 
396 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
397                                   unsigned and)
398 {
399         edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
400 }
401 
402 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
403                                  unsigned or)
404 {
405         edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
406 }
407 
408 static inline void set_bits(int offset, int len, unsigned long *p)
409 {
410         for (; len > 0; len--)
411                 set_bit(offset + (len - 1), p);
412 }
413 
414 static inline void clear_bits(int offset, int len, unsigned long *p)
415 {
416         for (; len > 0; len--)
417                 clear_bit(offset + (len - 1), p);
418 }
419 
420 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
421                                           int priority)
422 {
423         int bit = queue_no * 4;
424 
425         edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
426 }
427 
428 static void edma_set_chmap(struct edma_chan *echan, int slot)
429 {
430         struct edma_cc *ecc = echan->ecc;
431         int channel = EDMA_CHAN_SLOT(echan->ch_num);
432 
433         if (ecc->chmap_exist) {
434                 slot = EDMA_CHAN_SLOT(slot);
435                 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
436         }
437 }
438 
439 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
440 {
441         struct edma_cc *ecc = echan->ecc;
442         int channel = EDMA_CHAN_SLOT(echan->ch_num);
443 
444         if (enable) {
445                 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
446                                          BIT(channel & 0x1f));
447                 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
448                                          BIT(channel & 0x1f));
449         } else {
450                 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
451                                          BIT(channel & 0x1f));
452         }
453 }
454 
455 /*
456  * paRAM slot management functions
457  */
458 static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
459                             const struct edmacc_param *param)
460 {
461         slot = EDMA_CHAN_SLOT(slot);
462         if (slot >= ecc->num_slots)
463                 return;
464         memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
465 }
466 
467 static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
468                            struct edmacc_param *param)
469 {
470         slot = EDMA_CHAN_SLOT(slot);
471         if (slot >= ecc->num_slots)
472                 return;
473         memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
474 }
475 
476 /**
477  * edma_alloc_slot - allocate DMA parameter RAM
478  * @ecc: pointer to edma_cc struct
479  * @slot: specific slot to allocate; negative for "any unused slot"
480  *
481  * This allocates a parameter RAM slot, initializing it to hold a
482  * dummy transfer.  Slots allocated using this routine have not been
483  * mapped to a hardware DMA channel, and will normally be used by
484  * linking to them from a slot associated with a DMA channel.
485  *
486  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
487  * slots may be allocated on behalf of DSP firmware.
488  *
489  * Returns the number of the slot, else negative errno.
490  */
491 static int edma_alloc_slot(struct edma_cc *ecc, int slot)
492 {
493         if (slot >= 0) {
494                 slot = EDMA_CHAN_SLOT(slot);
495                 /* Requesting entry paRAM slot for a HW triggered channel. */
496                 if (ecc->chmap_exist && slot < ecc->num_channels)
497                         slot = EDMA_SLOT_ANY;
498         }
499 
500         if (slot < 0) {
501                 if (ecc->chmap_exist)
502                         slot = 0;
503                 else
504                         slot = ecc->num_channels;
505                 for (;;) {
506                         slot = find_next_zero_bit(ecc->slot_inuse,
507                                                   ecc->num_slots,
508                                                   slot);
509                         if (slot == ecc->num_slots)
510                                 return -ENOMEM;
511                         if (!test_and_set_bit(slot, ecc->slot_inuse))
512                                 break;
513                 }
514         } else if (slot >= ecc->num_slots) {
515                 return -EINVAL;
516         } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
517                 return -EBUSY;
518         }
519 
520         edma_write_slot(ecc, slot, &dummy_paramset);
521 
522         return EDMA_CTLR_CHAN(ecc->id, slot);
523 }
524 
525 static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
526 {
527         slot = EDMA_CHAN_SLOT(slot);
528         if (slot >= ecc->num_slots)
529                 return;
530 
531         edma_write_slot(ecc, slot, &dummy_paramset);
532         clear_bit(slot, ecc->slot_inuse);
533 }
534 
535 /**
536  * edma_link - link one parameter RAM slot to another
537  * @ecc: pointer to edma_cc struct
538  * @from: parameter RAM slot originating the link
539  * @to: parameter RAM slot which is the link target
540  *
541  * The originating slot should not be part of any active DMA transfer.
542  */
543 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
544 {
545         if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
546                 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
547 
548         from = EDMA_CHAN_SLOT(from);
549         to = EDMA_CHAN_SLOT(to);
550         if (from >= ecc->num_slots || to >= ecc->num_slots)
551                 return;
552 
553         edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
554                           PARM_OFFSET(to));
555 }
556 
557 /**
558  * edma_get_position - returns the current transfer point
559  * @ecc: pointer to edma_cc struct
560  * @slot: parameter RAM slot being examined
561  * @dst:  true selects the dest position, false the source
562  *
563  * Returns the position of the current active slot
564  */
565 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
566                                     bool dst)
567 {
568         u32 offs;
569 
570         slot = EDMA_CHAN_SLOT(slot);
571         offs = PARM_OFFSET(slot);
572         offs += dst ? PARM_DST : PARM_SRC;
573 
574         return edma_read(ecc, offs);
575 }
576 
577 /*
578  * Channels with event associations will be triggered by their hardware
579  * events, and channels without such associations will be triggered by
580  * software.  (At this writing there is no interface for using software
581  * triggers except with channels that don't support hardware triggers.)
582  */
583 static void edma_start(struct edma_chan *echan)
584 {
585         struct edma_cc *ecc = echan->ecc;
586         int channel = EDMA_CHAN_SLOT(echan->ch_num);
587         int j = (channel >> 5);
588         unsigned int mask = BIT(channel & 0x1f);
589 
590         if (!echan->hw_triggered) {
591                 /* EDMA channels without event association */
592                 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
593                         edma_shadow0_read_array(ecc, SH_ESR, j));
594                 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
595         } else {
596                 /* EDMA channel with event association */
597                 dev_dbg(ecc->dev, "ER%d %08x\n", j,
598                         edma_shadow0_read_array(ecc, SH_ER, j));
599                 /* Clear any pending event or error */
600                 edma_write_array(ecc, EDMA_ECR, j, mask);
601                 edma_write_array(ecc, EDMA_EMCR, j, mask);
602                 /* Clear any SER */
603                 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
604                 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
605                 dev_dbg(ecc->dev, "EER%d %08x\n", j,
606                         edma_shadow0_read_array(ecc, SH_EER, j));
607         }
608 }
609 
610 static void edma_stop(struct edma_chan *echan)
611 {
612         struct edma_cc *ecc = echan->ecc;
613         int channel = EDMA_CHAN_SLOT(echan->ch_num);
614         int j = (channel >> 5);
615         unsigned int mask = BIT(channel & 0x1f);
616 
617         edma_shadow0_write_array(ecc, SH_EECR, j, mask);
618         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
619         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
620         edma_write_array(ecc, EDMA_EMCR, j, mask);
621 
622         /* clear possibly pending completion interrupt */
623         edma_shadow0_write_array(ecc, SH_ICR, j, mask);
624 
625         dev_dbg(ecc->dev, "EER%d %08x\n", j,
626                 edma_shadow0_read_array(ecc, SH_EER, j));
627 
628         /* REVISIT:  consider guarding against inappropriate event
629          * chaining by overwriting with dummy_paramset.
630          */
631 }
632 
633 /*
634  * Temporarily disable EDMA hardware events on the specified channel,
635  * preventing them from triggering new transfers
636  */
637 static void edma_pause(struct edma_chan *echan)
638 {
639         int channel = EDMA_CHAN_SLOT(echan->ch_num);
640         unsigned int mask = BIT(channel & 0x1f);
641 
642         edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
643 }
644 
645 /* Re-enable EDMA hardware events on the specified channel.  */
646 static void edma_resume(struct edma_chan *echan)
647 {
648         int channel = EDMA_CHAN_SLOT(echan->ch_num);
649         unsigned int mask = BIT(channel & 0x1f);
650 
651         edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
652 }
653 
654 static void edma_trigger_channel(struct edma_chan *echan)
655 {
656         struct edma_cc *ecc = echan->ecc;
657         int channel = EDMA_CHAN_SLOT(echan->ch_num);
658         unsigned int mask = BIT(channel & 0x1f);
659 
660         edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
661 
662         dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
663                 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
664 }
665 
666 static void edma_clean_channel(struct edma_chan *echan)
667 {
668         struct edma_cc *ecc = echan->ecc;
669         int channel = EDMA_CHAN_SLOT(echan->ch_num);
670         int j = (channel >> 5);
671         unsigned int mask = BIT(channel & 0x1f);
672 
673         dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
674         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
675         /* Clear the corresponding EMR bits */
676         edma_write_array(ecc, EDMA_EMCR, j, mask);
677         /* Clear any SER */
678         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
679         edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
680 }
681 
682 /* Move channel to a specific event queue */
683 static void edma_assign_channel_eventq(struct edma_chan *echan,
684                                        enum dma_event_q eventq_no)
685 {
686         struct edma_cc *ecc = echan->ecc;
687         int channel = EDMA_CHAN_SLOT(echan->ch_num);
688         int bit = (channel & 0x7) * 4;
689 
690         /* default to low priority queue */
691         if (eventq_no == EVENTQ_DEFAULT)
692                 eventq_no = ecc->default_queue;
693         if (eventq_no >= ecc->num_tc)
694                 return;
695 
696         eventq_no &= 7;
697         edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
698                           eventq_no << bit);
699 }
700 
701 static int edma_alloc_channel(struct edma_chan *echan,
702                               enum dma_event_q eventq_no)
703 {
704         struct edma_cc *ecc = echan->ecc;
705         int channel = EDMA_CHAN_SLOT(echan->ch_num);
706 
707         /* ensure access through shadow region 0 */
708         edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
709 
710         /* ensure no events are pending */
711         edma_stop(echan);
712 
713         edma_setup_interrupt(echan, true);
714 
715         edma_assign_channel_eventq(echan, eventq_no);
716 
717         return 0;
718 }
719 
720 static void edma_free_channel(struct edma_chan *echan)
721 {
722         /* ensure no events are pending */
723         edma_stop(echan);
724         /* REVISIT should probably take out of shadow region 0 */
725         edma_setup_interrupt(echan, false);
726 }
727 
728 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
729 {
730         return container_of(d, struct edma_cc, dma_slave);
731 }
732 
733 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
734 {
735         return container_of(c, struct edma_chan, vchan.chan);
736 }
737 
738 static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
739 {
740         return container_of(tx, struct edma_desc, vdesc.tx);
741 }
742 
743 static void edma_desc_free(struct virt_dma_desc *vdesc)
744 {
745         kfree(container_of(vdesc, struct edma_desc, vdesc));
746 }
747 
748 /* Dispatch a queued descriptor to the controller (caller holds lock) */
749 static void edma_execute(struct edma_chan *echan)
750 {
751         struct edma_cc *ecc = echan->ecc;
752         struct virt_dma_desc *vdesc;
753         struct edma_desc *edesc;
754         struct device *dev = echan->vchan.chan.device->dev;
755         int i, j, left, nslots;
756 
757         if (!echan->edesc) {
758                 /* Setup is needed for the first transfer */
759                 vdesc = vchan_next_desc(&echan->vchan);
760                 if (!vdesc)
761                         return;
762                 list_del(&vdesc->node);
763                 echan->edesc = to_edma_desc(&vdesc->tx);
764         }
765 
766         edesc = echan->edesc;
767 
768         /* Find out how many left */
769         left = edesc->pset_nr - edesc->processed;
770         nslots = min(MAX_NR_SG, left);
771         edesc->sg_len = 0;
772 
773         /* Write descriptor PaRAM set(s) */
774         for (i = 0; i < nslots; i++) {
775                 j = i + edesc->processed;
776                 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
777                 edesc->sg_len += edesc->pset[j].len;
778                 dev_vdbg(dev,
779                          "\n pset[%d]:\n"
780                          "  chnum\t%d\n"
781                          "  slot\t%d\n"
782                          "  opt\t%08x\n"
783                          "  src\t%08x\n"
784                          "  dst\t%08x\n"
785                          "  abcnt\t%08x\n"
786                          "  ccnt\t%08x\n"
787                          "  bidx\t%08x\n"
788                          "  cidx\t%08x\n"
789                          "  lkrld\t%08x\n",
790                          j, echan->ch_num, echan->slot[i],
791                          edesc->pset[j].param.opt,
792                          edesc->pset[j].param.src,
793                          edesc->pset[j].param.dst,
794                          edesc->pset[j].param.a_b_cnt,
795                          edesc->pset[j].param.ccnt,
796                          edesc->pset[j].param.src_dst_bidx,
797                          edesc->pset[j].param.src_dst_cidx,
798                          edesc->pset[j].param.link_bcntrld);
799                 /* Link to the previous slot if not the last set */
800                 if (i != (nslots - 1))
801                         edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
802         }
803 
804         edesc->processed += nslots;
805 
806         /*
807          * If this is either the last set in a set of SG-list transactions
808          * then setup a link to the dummy slot, this results in all future
809          * events being absorbed and that's OK because we're done
810          */
811         if (edesc->processed == edesc->pset_nr) {
812                 if (edesc->cyclic)
813                         edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
814                 else
815                         edma_link(ecc, echan->slot[nslots - 1],
816                                   echan->ecc->dummy_slot);
817         }
818 
819         if (echan->missed) {
820                 /*
821                  * This happens due to setup times between intermediate
822                  * transfers in long SG lists which have to be broken up into
823                  * transfers of MAX_NR_SG
824                  */
825                 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
826                 edma_clean_channel(echan);
827                 edma_stop(echan);
828                 edma_start(echan);
829                 edma_trigger_channel(echan);
830                 echan->missed = 0;
831         } else if (edesc->processed <= MAX_NR_SG) {
832                 dev_dbg(dev, "first transfer starting on channel %d\n",
833                         echan->ch_num);
834                 edma_start(echan);
835         } else {
836                 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
837                         echan->ch_num, edesc->processed);
838                 edma_resume(echan);
839         }
840 }
841 
842 static int edma_terminate_all(struct dma_chan *chan)
843 {
844         struct edma_chan *echan = to_edma_chan(chan);
845         unsigned long flags;
846         LIST_HEAD(head);
847 
848         spin_lock_irqsave(&echan->vchan.lock, flags);
849 
850         /*
851          * Stop DMA activity: we assume the callback will not be called
852          * after edma_dma() returns (even if it does, it will see
853          * echan->edesc is NULL and exit.)
854          */
855         if (echan->edesc) {
856                 edma_stop(echan);
857                 /* Move the cyclic channel back to default queue */
858                 if (!echan->tc && echan->edesc->cyclic)
859                         edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
860                 /*
861                  * free the running request descriptor
862                  * since it is not in any of the vdesc lists
863                  */
864                 edma_desc_free(&echan->edesc->vdesc);
865                 echan->edesc = NULL;
866         }
867 
868         vchan_get_all_descriptors(&echan->vchan, &head);
869         spin_unlock_irqrestore(&echan->vchan.lock, flags);
870         vchan_dma_desc_free_list(&echan->vchan, &head);
871 
872         return 0;
873 }
874 
875 static void edma_synchronize(struct dma_chan *chan)
876 {
877         struct edma_chan *echan = to_edma_chan(chan);
878 
879         vchan_synchronize(&echan->vchan);
880 }
881 
882 static int edma_slave_config(struct dma_chan *chan,
883         struct dma_slave_config *cfg)
884 {
885         struct edma_chan *echan = to_edma_chan(chan);
886 
887         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
888             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
889                 return -EINVAL;
890 
891         memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
892 
893         return 0;
894 }
895 
896 static int edma_dma_pause(struct dma_chan *chan)
897 {
898         struct edma_chan *echan = to_edma_chan(chan);
899 
900         if (!echan->edesc)
901                 return -EINVAL;
902 
903         edma_pause(echan);
904         return 0;
905 }
906 
907 static int edma_dma_resume(struct dma_chan *chan)
908 {
909         struct edma_chan *echan = to_edma_chan(chan);
910 
911         edma_resume(echan);
912         return 0;
913 }
914 
915 /*
916  * A PaRAM set configuration abstraction used by other modes
917  * @chan: Channel who's PaRAM set we're configuring
918  * @pset: PaRAM set to initialize and setup.
919  * @src_addr: Source address of the DMA
920  * @dst_addr: Destination address of the DMA
921  * @burst: In units of dev_width, how much to send
922  * @dev_width: How much is the dev_width
923  * @dma_length: Total length of the DMA transfer
924  * @direction: Direction of the transfer
925  */
926 static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
927                             dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
928                             unsigned int acnt, unsigned int dma_length,
929                             enum dma_transfer_direction direction)
930 {
931         struct edma_chan *echan = to_edma_chan(chan);
932         struct device *dev = chan->device->dev;
933         struct edmacc_param *param = &epset->param;
934         int bcnt, ccnt, cidx;
935         int src_bidx, dst_bidx, src_cidx, dst_cidx;
936         int absync;
937 
938         /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
939         if (!burst)
940                 burst = 1;
941         /*
942          * If the maxburst is equal to the fifo width, use
943          * A-synced transfers. This allows for large contiguous
944          * buffer transfers using only one PaRAM set.
945          */
946         if (burst == 1) {
947                 /*
948                  * For the A-sync case, bcnt and ccnt are the remainder
949                  * and quotient respectively of the division of:
950                  * (dma_length / acnt) by (SZ_64K -1). This is so
951                  * that in case bcnt over flows, we have ccnt to use.
952                  * Note: In A-sync tranfer only, bcntrld is used, but it
953                  * only applies for sg_dma_len(sg) >= SZ_64K.
954                  * In this case, the best way adopted is- bccnt for the
955                  * first frame will be the remainder below. Then for
956                  * every successive frame, bcnt will be SZ_64K-1. This
957                  * is assured as bcntrld = 0xffff in end of function.
958                  */
959                 absync = false;
960                 ccnt = dma_length / acnt / (SZ_64K - 1);
961                 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
962                 /*
963                  * If bcnt is non-zero, we have a remainder and hence an
964                  * extra frame to transfer, so increment ccnt.
965                  */
966                 if (bcnt)
967                         ccnt++;
968                 else
969                         bcnt = SZ_64K - 1;
970                 cidx = acnt;
971         } else {
972                 /*
973                  * If maxburst is greater than the fifo address_width,
974                  * use AB-synced transfers where A count is the fifo
975                  * address_width and B count is the maxburst. In this
976                  * case, we are limited to transfers of C count frames
977                  * of (address_width * maxburst) where C count is limited
978                  * to SZ_64K-1. This places an upper bound on the length
979                  * of an SG segment that can be handled.
980                  */
981                 absync = true;
982                 bcnt = burst;
983                 ccnt = dma_length / (acnt * bcnt);
984                 if (ccnt > (SZ_64K - 1)) {
985                         dev_err(dev, "Exceeded max SG segment size\n");
986                         return -EINVAL;
987                 }
988                 cidx = acnt * bcnt;
989         }
990 
991         epset->len = dma_length;
992 
993         if (direction == DMA_MEM_TO_DEV) {
994                 src_bidx = acnt;
995                 src_cidx = cidx;
996                 dst_bidx = 0;
997                 dst_cidx = 0;
998                 epset->addr = src_addr;
999         } else if (direction == DMA_DEV_TO_MEM)  {
1000                 src_bidx = 0;
1001                 src_cidx = 0;
1002                 dst_bidx = acnt;
1003                 dst_cidx = cidx;
1004                 epset->addr = dst_addr;
1005         } else if (direction == DMA_MEM_TO_MEM)  {
1006                 src_bidx = acnt;
1007                 src_cidx = cidx;
1008                 dst_bidx = acnt;
1009                 dst_cidx = cidx;
1010         } else {
1011                 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1012                 return -EINVAL;
1013         }
1014 
1015         param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1016         /* Configure A or AB synchronized transfers */
1017         if (absync)
1018                 param->opt |= SYNCDIM;
1019 
1020         param->src = src_addr;
1021         param->dst = dst_addr;
1022 
1023         param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1024         param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1025 
1026         param->a_b_cnt = bcnt << 16 | acnt;
1027         param->ccnt = ccnt;
1028         /*
1029          * Only time when (bcntrld) auto reload is required is for
1030          * A-sync case, and in this case, a requirement of reload value
1031          * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1032          * and then later will be populated by edma_execute.
1033          */
1034         param->link_bcntrld = 0xffffffff;
1035         return absync;
1036 }
1037 
1038 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1039         struct dma_chan *chan, struct scatterlist *sgl,
1040         unsigned int sg_len, enum dma_transfer_direction direction,
1041         unsigned long tx_flags, void *context)
1042 {
1043         struct edma_chan *echan = to_edma_chan(chan);
1044         struct device *dev = chan->device->dev;
1045         struct edma_desc *edesc;
1046         dma_addr_t src_addr = 0, dst_addr = 0;
1047         enum dma_slave_buswidth dev_width;
1048         u32 burst;
1049         struct scatterlist *sg;
1050         int i, nslots, ret;
1051 
1052         if (unlikely(!echan || !sgl || !sg_len))
1053                 return NULL;
1054 
1055         if (direction == DMA_DEV_TO_MEM) {
1056                 src_addr = echan->cfg.src_addr;
1057                 dev_width = echan->cfg.src_addr_width;
1058                 burst = echan->cfg.src_maxburst;
1059         } else if (direction == DMA_MEM_TO_DEV) {
1060                 dst_addr = echan->cfg.dst_addr;
1061                 dev_width = echan->cfg.dst_addr_width;
1062                 burst = echan->cfg.dst_maxburst;
1063         } else {
1064                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1065                 return NULL;
1066         }
1067 
1068         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1069                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1070                 return NULL;
1071         }
1072 
1073         edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1074                         GFP_ATOMIC);
1075         if (!edesc)
1076                 return NULL;
1077 
1078         edesc->pset_nr = sg_len;
1079         edesc->residue = 0;
1080         edesc->direction = direction;
1081         edesc->echan = echan;
1082 
1083         /* Allocate a PaRAM slot, if needed */
1084         nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1085 
1086         for (i = 0; i < nslots; i++) {
1087                 if (echan->slot[i] < 0) {
1088                         echan->slot[i] =
1089                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1090                         if (echan->slot[i] < 0) {
1091                                 kfree(edesc);
1092                                 dev_err(dev, "%s: Failed to allocate slot\n",
1093                                         __func__);
1094                                 return NULL;
1095                         }
1096                 }
1097         }
1098 
1099         /* Configure PaRAM sets for each SG */
1100         for_each_sg(sgl, sg, sg_len, i) {
1101                 /* Get address for each SG */
1102                 if (direction == DMA_DEV_TO_MEM)
1103                         dst_addr = sg_dma_address(sg);
1104                 else
1105                         src_addr = sg_dma_address(sg);
1106 
1107                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1108                                        dst_addr, burst, dev_width,
1109                                        sg_dma_len(sg), direction);
1110                 if (ret < 0) {
1111                         kfree(edesc);
1112                         return NULL;
1113                 }
1114 
1115                 edesc->absync = ret;
1116                 edesc->residue += sg_dma_len(sg);
1117 
1118                 if (i == sg_len - 1)
1119                         /* Enable completion interrupt */
1120                         edesc->pset[i].param.opt |= TCINTEN;
1121                 else if (!((i+1) % MAX_NR_SG))
1122                         /*
1123                          * Enable early completion interrupt for the
1124                          * intermediateset. In this case the driver will be
1125                          * notified when the paRAM set is submitted to TC. This
1126                          * will allow more time to set up the next set of slots.
1127                          */
1128                         edesc->pset[i].param.opt |= (TCINTEN | TCCMODE);
1129         }
1130         edesc->residue_stat = edesc->residue;
1131 
1132         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1133 }
1134 
1135 static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1136         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1137         size_t len, unsigned long tx_flags)
1138 {
1139         int ret, nslots;
1140         struct edma_desc *edesc;
1141         struct device *dev = chan->device->dev;
1142         struct edma_chan *echan = to_edma_chan(chan);
1143         unsigned int width, pset_len;
1144 
1145         if (unlikely(!echan || !len))
1146                 return NULL;
1147 
1148         if (len < SZ_64K) {
1149                 /*
1150                  * Transfer size less than 64K can be handled with one paRAM
1151                  * slot and with one burst.
1152                  * ACNT = length
1153                  */
1154                 width = len;
1155                 pset_len = len;
1156                 nslots = 1;
1157         } else {
1158                 /*
1159                  * Transfer size bigger than 64K will be handled with maximum of
1160                  * two paRAM slots.
1161                  * slot1: (full_length / 32767) times 32767 bytes bursts.
1162                  *        ACNT = 32767, length1: (full_length / 32767) * 32767
1163                  * slot2: the remaining amount of data after slot1.
1164                  *        ACNT = full_length - length1, length2 = ACNT
1165                  *
1166                  * When the full_length is multibple of 32767 one slot can be
1167                  * used to complete the transfer.
1168                  */
1169                 width = SZ_32K - 1;
1170                 pset_len = rounddown(len, width);
1171                 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1172                 if (unlikely(pset_len == len))
1173                         nslots = 1;
1174                 else
1175                         nslots = 2;
1176         }
1177 
1178         edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1179                         GFP_ATOMIC);
1180         if (!edesc)
1181                 return NULL;
1182 
1183         edesc->pset_nr = nslots;
1184         edesc->residue = edesc->residue_stat = len;
1185         edesc->direction = DMA_MEM_TO_MEM;
1186         edesc->echan = echan;
1187 
1188         ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1189                                width, pset_len, DMA_MEM_TO_MEM);
1190         if (ret < 0) {
1191                 kfree(edesc);
1192                 return NULL;
1193         }
1194 
1195         edesc->absync = ret;
1196 
1197         edesc->pset[0].param.opt |= ITCCHEN;
1198         if (nslots == 1) {
1199                 /* Enable transfer complete interrupt */
1200                 edesc->pset[0].param.opt |= TCINTEN;
1201         } else {
1202                 /* Enable transfer complete chaining for the first slot */
1203                 edesc->pset[0].param.opt |= TCCHEN;
1204 
1205                 if (echan->slot[1] < 0) {
1206                         echan->slot[1] = edma_alloc_slot(echan->ecc,
1207                                                          EDMA_SLOT_ANY);
1208                         if (echan->slot[1] < 0) {
1209                                 kfree(edesc);
1210                                 dev_err(dev, "%s: Failed to allocate slot\n",
1211                                         __func__);
1212                                 return NULL;
1213                         }
1214                 }
1215                 dest += pset_len;
1216                 src += pset_len;
1217                 pset_len = width = len % (SZ_32K - 1);
1218 
1219                 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1220                                        width, pset_len, DMA_MEM_TO_MEM);
1221                 if (ret < 0) {
1222                         kfree(edesc);
1223                         return NULL;
1224                 }
1225 
1226                 edesc->pset[1].param.opt |= ITCCHEN;
1227                 edesc->pset[1].param.opt |= TCINTEN;
1228         }
1229 
1230         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1231 }
1232 
1233 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1234         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1235         size_t period_len, enum dma_transfer_direction direction,
1236         unsigned long tx_flags)
1237 {
1238         struct edma_chan *echan = to_edma_chan(chan);
1239         struct device *dev = chan->device->dev;
1240         struct edma_desc *edesc;
1241         dma_addr_t src_addr, dst_addr;
1242         enum dma_slave_buswidth dev_width;
1243         bool use_intermediate = false;
1244         u32 burst;
1245         int i, ret, nslots;
1246 
1247         if (unlikely(!echan || !buf_len || !period_len))
1248                 return NULL;
1249 
1250         if (direction == DMA_DEV_TO_MEM) {
1251                 src_addr = echan->cfg.src_addr;
1252                 dst_addr = buf_addr;
1253                 dev_width = echan->cfg.src_addr_width;
1254                 burst = echan->cfg.src_maxburst;
1255         } else if (direction == DMA_MEM_TO_DEV) {
1256                 src_addr = buf_addr;
1257                 dst_addr = echan->cfg.dst_addr;
1258                 dev_width = echan->cfg.dst_addr_width;
1259                 burst = echan->cfg.dst_maxburst;
1260         } else {
1261                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1262                 return NULL;
1263         }
1264 
1265         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1266                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1267                 return NULL;
1268         }
1269 
1270         if (unlikely(buf_len % period_len)) {
1271                 dev_err(dev, "Period should be multiple of Buffer length\n");
1272                 return NULL;
1273         }
1274 
1275         nslots = (buf_len / period_len) + 1;
1276 
1277         /*
1278          * Cyclic DMA users such as audio cannot tolerate delays introduced
1279          * by cases where the number of periods is more than the maximum
1280          * number of SGs the EDMA driver can handle at a time. For DMA types
1281          * such as Slave SGs, such delays are tolerable and synchronized,
1282          * but the synchronization is difficult to achieve with Cyclic and
1283          * cannot be guaranteed, so we error out early.
1284          */
1285         if (nslots > MAX_NR_SG) {
1286                 /*
1287                  * If the burst and period sizes are the same, we can put
1288                  * the full buffer into a single period and activate
1289                  * intermediate interrupts. This will produce interrupts
1290                  * after each burst, which is also after each desired period.
1291                  */
1292                 if (burst == period_len) {
1293                         period_len = buf_len;
1294                         nslots = 2;
1295                         use_intermediate = true;
1296                 } else {
1297                         return NULL;
1298                 }
1299         }
1300 
1301         edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1302                         GFP_ATOMIC);
1303         if (!edesc)
1304                 return NULL;
1305 
1306         edesc->cyclic = 1;
1307         edesc->pset_nr = nslots;
1308         edesc->residue = edesc->residue_stat = buf_len;
1309         edesc->direction = direction;
1310         edesc->echan = echan;
1311 
1312         dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1313                 __func__, echan->ch_num, nslots, period_len, buf_len);
1314 
1315         for (i = 0; i < nslots; i++) {
1316                 /* Allocate a PaRAM slot, if needed */
1317                 if (echan->slot[i] < 0) {
1318                         echan->slot[i] =
1319                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1320                         if (echan->slot[i] < 0) {
1321                                 kfree(edesc);
1322                                 dev_err(dev, "%s: Failed to allocate slot\n",
1323                                         __func__);
1324                                 return NULL;
1325                         }
1326                 }
1327 
1328                 if (i == nslots - 1) {
1329                         memcpy(&edesc->pset[i], &edesc->pset[0],
1330                                sizeof(edesc->pset[0]));
1331                         break;
1332                 }
1333 
1334                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1335                                        dst_addr, burst, dev_width, period_len,
1336                                        direction);
1337                 if (ret < 0) {
1338                         kfree(edesc);
1339                         return NULL;
1340                 }
1341 
1342                 if (direction == DMA_DEV_TO_MEM)
1343                         dst_addr += period_len;
1344                 else
1345                         src_addr += period_len;
1346 
1347                 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1348                 dev_vdbg(dev,
1349                         "\n pset[%d]:\n"
1350                         "  chnum\t%d\n"
1351                         "  slot\t%d\n"
1352                         "  opt\t%08x\n"
1353                         "  src\t%08x\n"
1354                         "  dst\t%08x\n"
1355                         "  abcnt\t%08x\n"
1356                         "  ccnt\t%08x\n"
1357                         "  bidx\t%08x\n"
1358                         "  cidx\t%08x\n"
1359                         "  lkrld\t%08x\n",
1360                         i, echan->ch_num, echan->slot[i],
1361                         edesc->pset[i].param.opt,
1362                         edesc->pset[i].param.src,
1363                         edesc->pset[i].param.dst,
1364                         edesc->pset[i].param.a_b_cnt,
1365                         edesc->pset[i].param.ccnt,
1366                         edesc->pset[i].param.src_dst_bidx,
1367                         edesc->pset[i].param.src_dst_cidx,
1368                         edesc->pset[i].param.link_bcntrld);
1369 
1370                 edesc->absync = ret;
1371 
1372                 /*
1373                  * Enable period interrupt only if it is requested
1374                  */
1375                 if (tx_flags & DMA_PREP_INTERRUPT) {
1376                         edesc->pset[i].param.opt |= TCINTEN;
1377 
1378                         /* Also enable intermediate interrupts if necessary */
1379                         if (use_intermediate)
1380                                 edesc->pset[i].param.opt |= ITCINTEN;
1381                 }
1382         }
1383 
1384         /* Place the cyclic channel to highest priority queue */
1385         if (!echan->tc)
1386                 edma_assign_channel_eventq(echan, EVENTQ_0);
1387 
1388         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1389 }
1390 
1391 static void edma_completion_handler(struct edma_chan *echan)
1392 {
1393         struct device *dev = echan->vchan.chan.device->dev;
1394         struct edma_desc *edesc;
1395 
1396         spin_lock(&echan->vchan.lock);
1397         edesc = echan->edesc;
1398         if (edesc) {
1399                 if (edesc->cyclic) {
1400                         vchan_cyclic_callback(&edesc->vdesc);
1401                         spin_unlock(&echan->vchan.lock);
1402                         return;
1403                 } else if (edesc->processed == edesc->pset_nr) {
1404                         edesc->residue = 0;
1405                         edma_stop(echan);
1406                         vchan_cookie_complete(&edesc->vdesc);
1407                         echan->edesc = NULL;
1408 
1409                         dev_dbg(dev, "Transfer completed on channel %d\n",
1410                                 echan->ch_num);
1411                 } else {
1412                         dev_dbg(dev, "Sub transfer completed on channel %d\n",
1413                                 echan->ch_num);
1414 
1415                         edma_pause(echan);
1416 
1417                         /* Update statistics for tx_status */
1418                         edesc->residue -= edesc->sg_len;
1419                         edesc->residue_stat = edesc->residue;
1420                         edesc->processed_stat = edesc->processed;
1421                 }
1422                 edma_execute(echan);
1423         }
1424 
1425         spin_unlock(&echan->vchan.lock);
1426 }
1427 
1428 /* eDMA interrupt handler */
1429 static irqreturn_t dma_irq_handler(int irq, void *data)
1430 {
1431         struct edma_cc *ecc = data;
1432         int ctlr;
1433         u32 sh_ier;
1434         u32 sh_ipr;
1435         u32 bank;
1436 
1437         ctlr = ecc->id;
1438         if (ctlr < 0)
1439                 return IRQ_NONE;
1440 
1441         dev_vdbg(ecc->dev, "dma_irq_handler\n");
1442 
1443         sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1444         if (!sh_ipr) {
1445                 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1446                 if (!sh_ipr)
1447                         return IRQ_NONE;
1448                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1449                 bank = 1;
1450         } else {
1451                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1452                 bank = 0;
1453         }
1454 
1455         do {
1456                 u32 slot;
1457                 u32 channel;
1458 
1459                 slot = __ffs(sh_ipr);
1460                 sh_ipr &= ~(BIT(slot));
1461 
1462                 if (sh_ier & BIT(slot)) {
1463                         channel = (bank << 5) | slot;
1464                         /* Clear the corresponding IPR bits */
1465                         edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1466                         edma_completion_handler(&ecc->slave_chans[channel]);
1467                 }
1468         } while (sh_ipr);
1469 
1470         edma_shadow0_write(ecc, SH_IEVAL, 1);
1471         return IRQ_HANDLED;
1472 }
1473 
1474 static void edma_error_handler(struct edma_chan *echan)
1475 {
1476         struct edma_cc *ecc = echan->ecc;
1477         struct device *dev = echan->vchan.chan.device->dev;
1478         struct edmacc_param p;
1479 
1480         if (!echan->edesc)
1481                 return;
1482 
1483         spin_lock(&echan->vchan.lock);
1484 
1485         edma_read_slot(ecc, echan->slot[0], &p);
1486         /*
1487          * Issue later based on missed flag which will be sure
1488          * to happen as:
1489          * (1) we finished transmitting an intermediate slot and
1490          *     edma_execute is coming up.
1491          * (2) or we finished current transfer and issue will
1492          *     call edma_execute.
1493          *
1494          * Important note: issuing can be dangerous here and
1495          * lead to some nasty recursion when we are in a NULL
1496          * slot. So we avoid doing so and set the missed flag.
1497          */
1498         if (p.a_b_cnt == 0 && p.ccnt == 0) {
1499                 dev_dbg(dev, "Error on null slot, setting miss\n");
1500                 echan->missed = 1;
1501         } else {
1502                 /*
1503                  * The slot is already programmed but the event got
1504                  * missed, so its safe to issue it here.
1505                  */
1506                 dev_dbg(dev, "Missed event, TRIGGERING\n");
1507                 edma_clean_channel(echan);
1508                 edma_stop(echan);
1509                 edma_start(echan);
1510                 edma_trigger_channel(echan);
1511         }
1512         spin_unlock(&echan->vchan.lock);
1513 }
1514 
1515 static inline bool edma_error_pending(struct edma_cc *ecc)
1516 {
1517         if (edma_read_array(ecc, EDMA_EMR, 0) ||
1518             edma_read_array(ecc, EDMA_EMR, 1) ||
1519             edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1520                 return true;
1521 
1522         return false;
1523 }
1524 
1525 /* eDMA error interrupt handler */
1526 static irqreturn_t dma_ccerr_handler(int irq, void *data)
1527 {
1528         struct edma_cc *ecc = data;
1529         int i, j;
1530         int ctlr;
1531         unsigned int cnt = 0;
1532         unsigned int val;
1533 
1534         ctlr = ecc->id;
1535         if (ctlr < 0)
1536                 return IRQ_NONE;
1537 
1538         dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1539 
1540         if (!edma_error_pending(ecc)) {
1541                 /*
1542                  * The registers indicate no pending error event but the irq
1543                  * handler has been called.
1544                  * Ask eDMA to re-evaluate the error registers.
1545                  */
1546                 dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
1547                         __func__);
1548                 edma_write(ecc, EDMA_EEVAL, 1);
1549                 return IRQ_NONE;
1550         }
1551 
1552         while (1) {
1553                 /* Event missed register(s) */
1554                 for (j = 0; j < 2; j++) {
1555                         unsigned long emr;
1556 
1557                         val = edma_read_array(ecc, EDMA_EMR, j);
1558                         if (!val)
1559                                 continue;
1560 
1561                         dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1562                         emr = val;
1563                         for (i = find_next_bit(&emr, 32, 0); i < 32;
1564                              i = find_next_bit(&emr, 32, i + 1)) {
1565                                 int k = (j << 5) + i;
1566 
1567                                 /* Clear the corresponding EMR bits */
1568                                 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1569                                 /* Clear any SER */
1570                                 edma_shadow0_write_array(ecc, SH_SECR, j,
1571                                                          BIT(i));
1572                                 edma_error_handler(&ecc->slave_chans[k]);
1573                         }
1574                 }
1575 
1576                 val = edma_read(ecc, EDMA_QEMR);
1577                 if (val) {
1578                         dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1579                         /* Not reported, just clear the interrupt reason. */
1580                         edma_write(ecc, EDMA_QEMCR, val);
1581                         edma_shadow0_write(ecc, SH_QSECR, val);
1582                 }
1583 
1584                 val = edma_read(ecc, EDMA_CCERR);
1585                 if (val) {
1586                         dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1587                         /* Not reported, just clear the interrupt reason. */
1588                         edma_write(ecc, EDMA_CCERRCLR, val);
1589                 }
1590 
1591                 if (!edma_error_pending(ecc))
1592                         break;
1593                 cnt++;
1594                 if (cnt > 10)
1595                         break;
1596         }
1597         edma_write(ecc, EDMA_EEVAL, 1);
1598         return IRQ_HANDLED;
1599 }
1600 
1601 /* Alloc channel resources */
1602 static int edma_alloc_chan_resources(struct dma_chan *chan)
1603 {
1604         struct edma_chan *echan = to_edma_chan(chan);
1605         struct edma_cc *ecc = echan->ecc;
1606         struct device *dev = ecc->dev;
1607         enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1608         int ret;
1609 
1610         if (echan->tc) {
1611                 eventq_no = echan->tc->id;
1612         } else if (ecc->tc_list) {
1613                 /* memcpy channel */
1614                 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1615                 eventq_no = echan->tc->id;
1616         }
1617 
1618         ret = edma_alloc_channel(echan, eventq_no);
1619         if (ret)
1620                 return ret;
1621 
1622         echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1623         if (echan->slot[0] < 0) {
1624                 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1625                         EDMA_CHAN_SLOT(echan->ch_num));
1626                 goto err_slot;
1627         }
1628 
1629         /* Set up channel -> slot mapping for the entry slot */
1630         edma_set_chmap(echan, echan->slot[0]);
1631         echan->alloced = true;
1632 
1633         dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1634                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1635                 echan->hw_triggered ? "HW" : "SW");
1636 
1637         return 0;
1638 
1639 err_slot:
1640         edma_free_channel(echan);
1641         return ret;
1642 }
1643 
1644 /* Free channel resources */
1645 static void edma_free_chan_resources(struct dma_chan *chan)
1646 {
1647         struct edma_chan *echan = to_edma_chan(chan);
1648         struct device *dev = echan->ecc->dev;
1649         int i;
1650 
1651         /* Terminate transfers */
1652         edma_stop(echan);
1653 
1654         vchan_free_chan_resources(&echan->vchan);
1655 
1656         /* Free EDMA PaRAM slots */
1657         for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1658                 if (echan->slot[i] >= 0) {
1659                         edma_free_slot(echan->ecc, echan->slot[i]);
1660                         echan->slot[i] = -1;
1661                 }
1662         }
1663 
1664         /* Set entry slot to the dummy slot */
1665         edma_set_chmap(echan, echan->ecc->dummy_slot);
1666 
1667         /* Free EDMA channel */
1668         if (echan->alloced) {
1669                 edma_free_channel(echan);
1670                 echan->alloced = false;
1671         }
1672 
1673         echan->tc = NULL;
1674         echan->hw_triggered = false;
1675 
1676         dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1677                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1678 }
1679 
1680 /* Send pending descriptor to hardware */
1681 static void edma_issue_pending(struct dma_chan *chan)
1682 {
1683         struct edma_chan *echan = to_edma_chan(chan);
1684         unsigned long flags;
1685 
1686         spin_lock_irqsave(&echan->vchan.lock, flags);
1687         if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1688                 edma_execute(echan);
1689         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1690 }
1691 
1692 /*
1693  * This limit exists to avoid a possible infinite loop when waiting for proof
1694  * that a particular transfer is completed. This limit can be hit if there
1695  * are large bursts to/from slow devices or the CPU is never able to catch
1696  * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1697  * RX-FIFO, as many as 55 loops have been seen.
1698  */
1699 #define EDMA_MAX_TR_WAIT_LOOPS 1000
1700 
1701 static u32 edma_residue(struct edma_desc *edesc)
1702 {
1703         bool dst = edesc->direction == DMA_DEV_TO_MEM;
1704         int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1705         struct edma_chan *echan = edesc->echan;
1706         struct edma_pset *pset = edesc->pset;
1707         dma_addr_t done, pos;
1708         int i;
1709 
1710         /*
1711          * We always read the dst/src position from the first RamPar
1712          * pset. That's the one which is active now.
1713          */
1714         pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1715 
1716         /*
1717          * "pos" may represent a transfer request that is still being
1718          * processed by the EDMACC or EDMATC. We will busy wait until
1719          * any one of the situations occurs:
1720          *   1. the DMA hardware is idle
1721          *   2. a new transfer request is setup
1722          *   3. we hit the loop limit
1723          */
1724         while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
1725                 /* check if a new transfer request is setup */
1726                 if (edma_get_position(echan->ecc,
1727                                       echan->slot[0], dst) != pos) {
1728                         break;
1729                 }
1730 
1731                 if (!--loop_count) {
1732                         dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1733                                 "%s: timeout waiting for PaRAM update\n",
1734                                 __func__);
1735                         break;
1736                 }
1737 
1738                 cpu_relax();
1739         }
1740 
1741         /*
1742          * Cyclic is simple. Just subtract pset[0].addr from pos.
1743          *
1744          * We never update edesc->residue in the cyclic case, so we
1745          * can tell the remaining room to the end of the circular
1746          * buffer.
1747          */
1748         if (edesc->cyclic) {
1749                 done = pos - pset->addr;
1750                 edesc->residue_stat = edesc->residue - done;
1751                 return edesc->residue_stat;
1752         }
1753 
1754         /*
1755          * For SG operation we catch up with the last processed
1756          * status.
1757          */
1758         pset += edesc->processed_stat;
1759 
1760         for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1761                 /*
1762                  * If we are inside this pset address range, we know
1763                  * this is the active one. Get the current delta and
1764                  * stop walking the psets.
1765                  */
1766                 if (pos >= pset->addr && pos < pset->addr + pset->len)
1767                         return edesc->residue_stat - (pos - pset->addr);
1768 
1769                 /* Otherwise mark it done and update residue_stat. */
1770                 edesc->processed_stat++;
1771                 edesc->residue_stat -= pset->len;
1772         }
1773         return edesc->residue_stat;
1774 }
1775 
1776 /* Check request completion status */
1777 static enum dma_status edma_tx_status(struct dma_chan *chan,
1778                                       dma_cookie_t cookie,
1779                                       struct dma_tx_state *txstate)
1780 {
1781         struct edma_chan *echan = to_edma_chan(chan);
1782         struct virt_dma_desc *vdesc;
1783         enum dma_status ret;
1784         unsigned long flags;
1785 
1786         ret = dma_cookie_status(chan, cookie, txstate);
1787         if (ret == DMA_COMPLETE || !txstate)
1788                 return ret;
1789 
1790         spin_lock_irqsave(&echan->vchan.lock, flags);
1791         if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1792                 txstate->residue = edma_residue(echan->edesc);
1793         else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1794                 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1795         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1796 
1797         return ret;
1798 }
1799 
1800 static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1801 {
1802         if (!memcpy_channels)
1803                 return false;
1804         while (*memcpy_channels != -1) {
1805                 if (*memcpy_channels == ch_num)
1806                         return true;
1807                 memcpy_channels++;
1808         }
1809         return false;
1810 }
1811 
1812 #define EDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1813                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1814                                  BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1815                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1816 
1817 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1818 {
1819         struct dma_device *s_ddev = &ecc->dma_slave;
1820         struct dma_device *m_ddev = NULL;
1821         s32 *memcpy_channels = ecc->info->memcpy_channels;
1822         int i, j;
1823 
1824         dma_cap_zero(s_ddev->cap_mask);
1825         dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1826         dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1827         if (ecc->legacy_mode && !memcpy_channels) {
1828                 dev_warn(ecc->dev,
1829                          "Legacy memcpy is enabled, things might not work\n");
1830 
1831                 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1832                 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1833                 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1834         }
1835 
1836         s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1837         s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1838         s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1839         s_ddev->device_free_chan_resources = edma_free_chan_resources;
1840         s_ddev->device_issue_pending = edma_issue_pending;
1841         s_ddev->device_tx_status = edma_tx_status;
1842         s_ddev->device_config = edma_slave_config;
1843         s_ddev->device_pause = edma_dma_pause;
1844         s_ddev->device_resume = edma_dma_resume;
1845         s_ddev->device_terminate_all = edma_terminate_all;
1846         s_ddev->device_synchronize = edma_synchronize;
1847 
1848         s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1849         s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1850         s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1851         s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1852 
1853         s_ddev->dev = ecc->dev;
1854         INIT_LIST_HEAD(&s_ddev->channels);
1855 
1856         if (memcpy_channels) {
1857                 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1858                 ecc->dma_memcpy = m_ddev;
1859 
1860                 dma_cap_zero(m_ddev->cap_mask);
1861                 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1862 
1863                 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1864                 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1865                 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1866                 m_ddev->device_issue_pending = edma_issue_pending;
1867                 m_ddev->device_tx_status = edma_tx_status;
1868                 m_ddev->device_config = edma_slave_config;
1869                 m_ddev->device_pause = edma_dma_pause;
1870                 m_ddev->device_resume = edma_dma_resume;
1871                 m_ddev->device_terminate_all = edma_terminate_all;
1872                 m_ddev->device_synchronize = edma_synchronize;
1873 
1874                 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1875                 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1876                 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1877                 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1878 
1879                 m_ddev->dev = ecc->dev;
1880                 INIT_LIST_HEAD(&m_ddev->channels);
1881         } else if (!ecc->legacy_mode) {
1882                 dev_info(ecc->dev, "memcpy is disabled\n");
1883         }
1884 
1885         for (i = 0; i < ecc->num_channels; i++) {
1886                 struct edma_chan *echan = &ecc->slave_chans[i];
1887                 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1888                 echan->ecc = ecc;
1889                 echan->vchan.desc_free = edma_desc_free;
1890 
1891                 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1892                         vchan_init(&echan->vchan, m_ddev);
1893                 else
1894                         vchan_init(&echan->vchan, s_ddev);
1895 
1896                 INIT_LIST_HEAD(&echan->node);
1897                 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1898                         echan->slot[j] = -1;
1899         }
1900 }
1901 
1902 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1903                               struct edma_cc *ecc)
1904 {
1905         int i;
1906         u32 value, cccfg;
1907         s8 (*queue_priority_map)[2];
1908 
1909         /* Decode the eDMA3 configuration from CCCFG register */
1910         cccfg = edma_read(ecc, EDMA_CCCFG);
1911 
1912         value = GET_NUM_REGN(cccfg);
1913         ecc->num_region = BIT(value);
1914 
1915         value = GET_NUM_DMACH(cccfg);
1916         ecc->num_channels = BIT(value + 1);
1917 
1918         value = GET_NUM_QDMACH(cccfg);
1919         ecc->num_qchannels = value * 2;
1920 
1921         value = GET_NUM_PAENTRY(cccfg);
1922         ecc->num_slots = BIT(value + 4);
1923 
1924         value = GET_NUM_EVQUE(cccfg);
1925         ecc->num_tc = value + 1;
1926 
1927         ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1928 
1929         dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1930         dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1931         dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1932         dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
1933         dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1934         dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1935         dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1936 
1937         /* Nothing need to be done if queue priority is provided */
1938         if (pdata->queue_priority_mapping)
1939                 return 0;
1940 
1941         /*
1942          * Configure TC/queue priority as follows:
1943          * Q0 - priority 0
1944          * Q1 - priority 1
1945          * Q2 - priority 2
1946          * ...
1947          * The meaning of priority numbers: 0 highest priority, 7 lowest
1948          * priority. So Q0 is the highest priority queue and the last queue has
1949          * the lowest priority.
1950          */
1951         queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1952                                           GFP_KERNEL);
1953         if (!queue_priority_map)
1954                 return -ENOMEM;
1955 
1956         for (i = 0; i < ecc->num_tc; i++) {
1957                 queue_priority_map[i][0] = i;
1958                 queue_priority_map[i][1] = i;
1959         }
1960         queue_priority_map[i][0] = -1;
1961         queue_priority_map[i][1] = -1;
1962 
1963         pdata->queue_priority_mapping = queue_priority_map;
1964         /* Default queue has the lowest priority */
1965         pdata->default_queue = i - 1;
1966 
1967         return 0;
1968 }
1969 
1970 #if IS_ENABLED(CONFIG_OF)
1971 static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1972                                size_t sz)
1973 {
1974         const char pname[] = "ti,edma-xbar-event-map";
1975         struct resource res;
1976         void __iomem *xbar;
1977         s16 (*xbar_chans)[2];
1978         size_t nelm = sz / sizeof(s16);
1979         u32 shift, offset, mux;
1980         int ret, i;
1981 
1982         xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
1983         if (!xbar_chans)
1984                 return -ENOMEM;
1985 
1986         ret = of_address_to_resource(dev->of_node, 1, &res);
1987         if (ret)
1988                 return -ENOMEM;
1989 
1990         xbar = devm_ioremap(dev, res.start, resource_size(&res));
1991         if (!xbar)
1992                 return -ENOMEM;
1993 
1994         ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
1995                                          nelm);
1996         if (ret)
1997                 return -EIO;
1998 
1999         /* Invalidate last entry for the other user of this mess */
2000         nelm >>= 1;
2001         xbar_chans[nelm][0] = -1;
2002         xbar_chans[nelm][1] = -1;
2003 
2004         for (i = 0; i < nelm; i++) {
2005                 shift = (xbar_chans[i][1] & 0x03) << 3;
2006                 offset = xbar_chans[i][1] & 0xfffffffc;
2007                 mux = readl(xbar + offset);
2008                 mux &= ~(0xff << shift);
2009                 mux |= xbar_chans[i][0] << shift;
2010                 writel(mux, (xbar + offset));
2011         }
2012 
2013         pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2014         return 0;
2015 }
2016 
2017 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2018                                                      bool legacy_mode)
2019 {
2020         struct edma_soc_info *info;
2021         struct property *prop;
2022         size_t sz;
2023         int ret;
2024 
2025         info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2026         if (!info)
2027                 return ERR_PTR(-ENOMEM);
2028 
2029         if (legacy_mode) {
2030                 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
2031                                         &sz);
2032                 if (prop) {
2033                         ret = edma_xbar_event_map(dev, info, sz);
2034                         if (ret)
2035                                 return ERR_PTR(ret);
2036                 }
2037                 return info;
2038         }
2039 
2040         /* Get the list of channels allocated to be used for memcpy */
2041         prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2042         if (prop) {
2043                 const char pname[] = "ti,edma-memcpy-channels";
2044                 size_t nelm = sz / sizeof(s32);
2045                 s32 *memcpy_ch;
2046 
2047                 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2048                                          GFP_KERNEL);
2049                 if (!memcpy_ch)
2050                         return ERR_PTR(-ENOMEM);
2051 
2052                 ret = of_property_read_u32_array(dev->of_node, pname,
2053                                                  (u32 *)memcpy_ch, nelm);
2054                 if (ret)
2055                         return ERR_PTR(ret);
2056 
2057                 memcpy_ch[nelm] = -1;
2058                 info->memcpy_channels = memcpy_ch;
2059         }
2060 
2061         prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2062                                 &sz);
2063         if (prop) {
2064                 const char pname[] = "ti,edma-reserved-slot-ranges";
2065                 u32 (*tmp)[2];
2066                 s16 (*rsv_slots)[2];
2067                 size_t nelm = sz / sizeof(*tmp);
2068                 struct edma_rsv_info *rsv_info;
2069                 int i;
2070 
2071                 if (!nelm)
2072                         return info;
2073 
2074                 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2075                 if (!tmp)
2076                         return ERR_PTR(-ENOMEM);
2077 
2078                 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2079                 if (!rsv_info) {
2080                         kfree(tmp);
2081                         return ERR_PTR(-ENOMEM);
2082                 }
2083 
2084                 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2085                                          GFP_KERNEL);
2086                 if (!rsv_slots) {
2087                         kfree(tmp);
2088                         return ERR_PTR(-ENOMEM);
2089                 }
2090 
2091                 ret = of_property_read_u32_array(dev->of_node, pname,
2092                                                  (u32 *)tmp, nelm * 2);
2093                 if (ret) {
2094                         kfree(tmp);
2095                         return ERR_PTR(ret);
2096                 }
2097 
2098                 for (i = 0; i < nelm; i++) {
2099                         rsv_slots[i][0] = tmp[i][0];
2100                         rsv_slots[i][1] = tmp[i][1];
2101                 }
2102                 rsv_slots[nelm][0] = -1;
2103                 rsv_slots[nelm][1] = -1;
2104 
2105                 info->rsv = rsv_info;
2106                 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2107 
2108                 kfree(tmp);
2109         }
2110 
2111         return info;
2112 }
2113 
2114 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2115                                       struct of_dma *ofdma)
2116 {
2117         struct edma_cc *ecc = ofdma->of_dma_data;
2118         struct dma_chan *chan = NULL;
2119         struct edma_chan *echan;
2120         int i;
2121 
2122         if (!ecc || dma_spec->args_count < 1)
2123                 return NULL;
2124 
2125         for (i = 0; i < ecc->num_channels; i++) {
2126                 echan = &ecc->slave_chans[i];
2127                 if (echan->ch_num == dma_spec->args[0]) {
2128                         chan = &echan->vchan.chan;
2129                         break;
2130                 }
2131         }
2132 
2133         if (!chan)
2134                 return NULL;
2135 
2136         if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2137                 goto out;
2138 
2139         if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2140             dma_spec->args[1] < echan->ecc->num_tc) {
2141                 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2142                 goto out;
2143         }
2144 
2145         return NULL;
2146 out:
2147         /* The channel is going to be used as HW synchronized */
2148         echan->hw_triggered = true;
2149         return dma_get_slave_channel(chan);
2150 }
2151 #else
2152 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2153                                                      bool legacy_mode)
2154 {
2155         return ERR_PTR(-EINVAL);
2156 }
2157 
2158 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2159                                       struct of_dma *ofdma)
2160 {
2161         return NULL;
2162 }
2163 #endif
2164 
2165 static int edma_probe(struct platform_device *pdev)
2166 {
2167         struct edma_soc_info    *info = pdev->dev.platform_data;
2168         s8                      (*queue_priority_mapping)[2];
2169         int                     i, off, ln;
2170         const s16               (*rsv_slots)[2];
2171         const s16               (*xbar_chans)[2];
2172         int                     irq;
2173         char                    *irq_name;
2174         struct resource         *mem;
2175         struct device_node      *node = pdev->dev.of_node;
2176         struct device           *dev = &pdev->dev;
2177         struct edma_cc          *ecc;
2178         bool                    legacy_mode = true;
2179         int ret;
2180 
2181         if (node) {
2182                 const struct of_device_id *match;
2183 
2184                 match = of_match_node(edma_of_ids, node);
2185                 if (match && (u32)match->data == EDMA_BINDING_TPCC)
2186                         legacy_mode = false;
2187 
2188                 info = edma_setup_info_from_dt(dev, legacy_mode);
2189                 if (IS_ERR(info)) {
2190                         dev_err(dev, "failed to get DT data\n");
2191                         return PTR_ERR(info);
2192                 }
2193         }
2194 
2195         if (!info)
2196                 return -ENODEV;
2197 
2198         pm_runtime_enable(dev);
2199         ret = pm_runtime_get_sync(dev);
2200         if (ret < 0) {
2201                 dev_err(dev, "pm_runtime_get_sync() failed\n");
2202                 return ret;
2203         }
2204 
2205         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2206         if (ret)
2207                 return ret;
2208 
2209         ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2210         if (!ecc)
2211                 return -ENOMEM;
2212 
2213         ecc->dev = dev;
2214         ecc->id = pdev->id;
2215         ecc->legacy_mode = legacy_mode;
2216         /* When booting with DT the pdev->id is -1 */
2217         if (ecc->id < 0)
2218                 ecc->id = 0;
2219 
2220         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2221         if (!mem) {
2222                 dev_dbg(dev, "mem resource not found, using index 0\n");
2223                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2224                 if (!mem) {
2225                         dev_err(dev, "no mem resource?\n");
2226                         return -ENODEV;
2227                 }
2228         }
2229         ecc->base = devm_ioremap_resource(dev, mem);
2230         if (IS_ERR(ecc->base))
2231                 return PTR_ERR(ecc->base);
2232 
2233         platform_set_drvdata(pdev, ecc);
2234 
2235         /* Get eDMA3 configuration from IP */
2236         ret = edma_setup_from_hw(dev, info, ecc);
2237         if (ret)
2238                 return ret;
2239 
2240         /* Allocate memory based on the information we got from the IP */
2241         ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2242                                         sizeof(*ecc->slave_chans), GFP_KERNEL);
2243         if (!ecc->slave_chans)
2244                 return -ENOMEM;
2245 
2246         ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2247                                        sizeof(unsigned long), GFP_KERNEL);
2248         if (!ecc->slot_inuse)
2249                 return -ENOMEM;
2250 
2251         ecc->default_queue = info->default_queue;
2252 
2253         for (i = 0; i < ecc->num_slots; i++)
2254                 edma_write_slot(ecc, i, &dummy_paramset);
2255 
2256         if (info->rsv) {
2257                 /* Set the reserved slots in inuse list */
2258                 rsv_slots = info->rsv->rsv_slots;
2259                 if (rsv_slots) {
2260                         for (i = 0; rsv_slots[i][0] != -1; i++) {
2261                                 off = rsv_slots[i][0];
2262                                 ln = rsv_slots[i][1];
2263                                 set_bits(off, ln, ecc->slot_inuse);
2264                         }
2265                 }
2266         }
2267 
2268         /* Clear the xbar mapped channels in unused list */
2269         xbar_chans = info->xbar_chans;
2270         if (xbar_chans) {
2271                 for (i = 0; xbar_chans[i][1] != -1; i++) {
2272                         off = xbar_chans[i][1];
2273                 }
2274         }
2275 
2276         irq = platform_get_irq_byname(pdev, "edma3_ccint");
2277         if (irq < 0 && node)
2278                 irq = irq_of_parse_and_map(node, 0);
2279 
2280         if (irq >= 0) {
2281                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2282                                           dev_name(dev));
2283                 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2284                                        ecc);
2285                 if (ret) {
2286                         dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2287                         return ret;
2288                 }
2289                 ecc->ccint = irq;
2290         }
2291 
2292         irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2293         if (irq < 0 && node)
2294                 irq = irq_of_parse_and_map(node, 2);
2295 
2296         if (irq >= 0) {
2297                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2298                                           dev_name(dev));
2299                 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2300                                        ecc);
2301                 if (ret) {
2302                         dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2303                         return ret;
2304                 }
2305                 ecc->ccerrint = irq;
2306         }
2307 
2308         ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2309         if (ecc->dummy_slot < 0) {
2310                 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2311                 return ecc->dummy_slot;
2312         }
2313 
2314         queue_priority_mapping = info->queue_priority_mapping;
2315 
2316         if (!ecc->legacy_mode) {
2317                 int lowest_priority = 0;
2318                 struct of_phandle_args tc_args;
2319 
2320                 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2321                                             sizeof(*ecc->tc_list), GFP_KERNEL);
2322                 if (!ecc->tc_list)
2323                         return -ENOMEM;
2324 
2325                 for (i = 0;; i++) {
2326                         ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2327                                                                1, i, &tc_args);
2328                         if (ret || i == ecc->num_tc)
2329                                 break;
2330 
2331                         ecc->tc_list[i].node = tc_args.np;
2332                         ecc->tc_list[i].id = i;
2333                         queue_priority_mapping[i][1] = tc_args.args[0];
2334                         if (queue_priority_mapping[i][1] > lowest_priority) {
2335                                 lowest_priority = queue_priority_mapping[i][1];
2336                                 info->default_queue = i;
2337                         }
2338                 }
2339         }
2340 
2341         /* Event queue priority mapping */
2342         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2343                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2344                                               queue_priority_mapping[i][1]);
2345 
2346         for (i = 0; i < ecc->num_region; i++) {
2347                 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2348                 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2349                 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2350         }
2351         ecc->info = info;
2352 
2353         /* Init the dma device and channels */
2354         edma_dma_init(ecc, legacy_mode);
2355 
2356         for (i = 0; i < ecc->num_channels; i++) {
2357                 /* Assign all channels to the default queue */
2358                 edma_assign_channel_eventq(&ecc->slave_chans[i],
2359                                            info->default_queue);
2360                 /* Set entry slot to the dummy slot */
2361                 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2362         }
2363 
2364         ecc->dma_slave.filter.map = info->slave_map;
2365         ecc->dma_slave.filter.mapcnt = info->slavecnt;
2366         ecc->dma_slave.filter.fn = edma_filter_fn;
2367 
2368         ret = dma_async_device_register(&ecc->dma_slave);
2369         if (ret) {
2370                 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2371                 goto err_reg1;
2372         }
2373 
2374         if (ecc->dma_memcpy) {
2375                 ret = dma_async_device_register(ecc->dma_memcpy);
2376                 if (ret) {
2377                         dev_err(dev, "memcpy ddev registration failed (%d)\n",
2378                                 ret);
2379                         dma_async_device_unregister(&ecc->dma_slave);
2380                         goto err_reg1;
2381                 }
2382         }
2383 
2384         if (node)
2385                 of_dma_controller_register(node, of_edma_xlate, ecc);
2386 
2387         dev_info(dev, "TI EDMA DMA engine driver\n");
2388 
2389         return 0;
2390 
2391 err_reg1:
2392         edma_free_slot(ecc, ecc->dummy_slot);
2393         return ret;
2394 }
2395 
2396 static void edma_cleanupp_vchan(struct dma_device *dmadev)
2397 {
2398         struct edma_chan *echan, *_echan;
2399 
2400         list_for_each_entry_safe(echan, _echan,
2401                         &dmadev->channels, vchan.chan.device_node) {
2402                 list_del(&echan->vchan.chan.device_node);
2403                 tasklet_kill(&echan->vchan.task);
2404         }
2405 }
2406 
2407 static int edma_remove(struct platform_device *pdev)
2408 {
2409         struct device *dev = &pdev->dev;
2410         struct edma_cc *ecc = dev_get_drvdata(dev);
2411 
2412         devm_free_irq(dev, ecc->ccint, ecc);
2413         devm_free_irq(dev, ecc->ccerrint, ecc);
2414 
2415         edma_cleanupp_vchan(&ecc->dma_slave);
2416 
2417         if (dev->of_node)
2418                 of_dma_controller_free(dev->of_node);
2419         dma_async_device_unregister(&ecc->dma_slave);
2420         if (ecc->dma_memcpy)
2421                 dma_async_device_unregister(ecc->dma_memcpy);
2422         edma_free_slot(ecc, ecc->dummy_slot);
2423 
2424         return 0;
2425 }
2426 
2427 #ifdef CONFIG_PM_SLEEP
2428 static int edma_pm_suspend(struct device *dev)
2429 {
2430         struct edma_cc *ecc = dev_get_drvdata(dev);
2431         struct edma_chan *echan = ecc->slave_chans;
2432         int i;
2433 
2434         for (i = 0; i < ecc->num_channels; i++) {
2435                 if (echan[i].alloced)
2436                         edma_setup_interrupt(&echan[i], false);
2437         }
2438 
2439         return 0;
2440 }
2441 
2442 static int edma_pm_resume(struct device *dev)
2443 {
2444         struct edma_cc *ecc = dev_get_drvdata(dev);
2445         struct edma_chan *echan = ecc->slave_chans;
2446         int i;
2447         s8 (*queue_priority_mapping)[2];
2448 
2449         queue_priority_mapping = ecc->info->queue_priority_mapping;
2450 
2451         /* Event queue priority mapping */
2452         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2453                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2454                                               queue_priority_mapping[i][1]);
2455 
2456         for (i = 0; i < ecc->num_channels; i++) {
2457                 if (echan[i].alloced) {
2458                         /* ensure access through shadow region 0 */
2459                         edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2460                                        BIT(i & 0x1f));
2461 
2462                         edma_setup_interrupt(&echan[i], true);
2463 
2464                         /* Set up channel -> slot mapping for the entry slot */
2465                         edma_set_chmap(&echan[i], echan[i].slot[0]);
2466                 }
2467         }
2468 
2469         return 0;
2470 }
2471 #endif
2472 
2473 static const struct dev_pm_ops edma_pm_ops = {
2474         SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2475 };
2476 
2477 static struct platform_driver edma_driver = {
2478         .probe          = edma_probe,
2479         .remove         = edma_remove,
2480         .driver = {
2481                 .name   = "edma",
2482                 .pm     = &edma_pm_ops,
2483                 .of_match_table = edma_of_ids,
2484         },
2485 };
2486 
2487 static int edma_tptc_probe(struct platform_device *pdev)
2488 {
2489         pm_runtime_enable(&pdev->dev);
2490         return pm_runtime_get_sync(&pdev->dev);
2491 }
2492 
2493 static struct platform_driver edma_tptc_driver = {
2494         .probe          = edma_tptc_probe,
2495         .driver = {
2496                 .name   = "edma3-tptc",
2497                 .of_match_table = edma_tptc_of_ids,
2498         },
2499 };
2500 
2501 bool edma_filter_fn(struct dma_chan *chan, void *param)
2502 {
2503         bool match = false;
2504 
2505         if (chan->device->dev->driver == &edma_driver.driver) {
2506                 struct edma_chan *echan = to_edma_chan(chan);
2507                 unsigned ch_req = *(unsigned *)param;
2508                 if (ch_req == echan->ch_num) {
2509                         /* The channel is going to be used as HW synchronized */
2510                         echan->hw_triggered = true;
2511                         match = true;
2512                 }
2513         }
2514         return match;
2515 }
2516 EXPORT_SYMBOL(edma_filter_fn);
2517 
2518 static int edma_init(void)
2519 {
2520         int ret;
2521 
2522         ret = platform_driver_register(&edma_tptc_driver);
2523         if (ret)
2524                 return ret;
2525 
2526         return platform_driver_register(&edma_driver);
2527 }
2528 subsys_initcall(edma_init);
2529 
2530 static void __exit edma_exit(void)
2531 {
2532         platform_driver_unregister(&edma_driver);
2533         platform_driver_unregister(&edma_tptc_driver);
2534 }
2535 module_exit(edma_exit);
2536 
2537 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2538 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2539 MODULE_LICENSE("GPL v2");
2540 

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