Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/dma/dma-jz4740.c

  1 /*
  2  *  Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
  3  *  JZ4740 DMAC support
  4  *
  5  *  This program is free software; you can redistribute it and/or modify it
  6  *  under  the terms of the GNU General  Public License as published by the
  7  *  Free Software Foundation;  either version 2 of the License, or (at your
  8  *  option) any later version.
  9  *
 10  */
 11 
 12 #include <linux/dmaengine.h>
 13 #include <linux/dma-mapping.h>
 14 #include <linux/err.h>
 15 #include <linux/init.h>
 16 #include <linux/list.h>
 17 #include <linux/module.h>
 18 #include <linux/platform_device.h>
 19 #include <linux/slab.h>
 20 #include <linux/spinlock.h>
 21 #include <linux/irq.h>
 22 #include <linux/clk.h>
 23 
 24 #include "virt-dma.h"
 25 
 26 #define JZ_DMA_NR_CHANS 6
 27 
 28 #define JZ_REG_DMA_SRC_ADDR(x)          (0x00 + (x) * 0x20)
 29 #define JZ_REG_DMA_DST_ADDR(x)          (0x04 + (x) * 0x20)
 30 #define JZ_REG_DMA_TRANSFER_COUNT(x)    (0x08 + (x) * 0x20)
 31 #define JZ_REG_DMA_REQ_TYPE(x)          (0x0C + (x) * 0x20)
 32 #define JZ_REG_DMA_STATUS_CTRL(x)       (0x10 + (x) * 0x20)
 33 #define JZ_REG_DMA_CMD(x)               (0x14 + (x) * 0x20)
 34 #define JZ_REG_DMA_DESC_ADDR(x)         (0x18 + (x) * 0x20)
 35 
 36 #define JZ_REG_DMA_CTRL                 0x300
 37 #define JZ_REG_DMA_IRQ                  0x304
 38 #define JZ_REG_DMA_DOORBELL             0x308
 39 #define JZ_REG_DMA_DOORBELL_SET         0x30C
 40 
 41 #define JZ_DMA_STATUS_CTRL_NO_DESC              BIT(31)
 42 #define JZ_DMA_STATUS_CTRL_DESC_INV             BIT(6)
 43 #define JZ_DMA_STATUS_CTRL_ADDR_ERR             BIT(4)
 44 #define JZ_DMA_STATUS_CTRL_TRANSFER_DONE        BIT(3)
 45 #define JZ_DMA_STATUS_CTRL_HALT                 BIT(2)
 46 #define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE      BIT(1)
 47 #define JZ_DMA_STATUS_CTRL_ENABLE               BIT(0)
 48 
 49 #define JZ_DMA_CMD_SRC_INC                      BIT(23)
 50 #define JZ_DMA_CMD_DST_INC                      BIT(22)
 51 #define JZ_DMA_CMD_RDIL_MASK                    (0xf << 16)
 52 #define JZ_DMA_CMD_SRC_WIDTH_MASK               (0x3 << 14)
 53 #define JZ_DMA_CMD_DST_WIDTH_MASK               (0x3 << 12)
 54 #define JZ_DMA_CMD_INTERVAL_LENGTH_MASK         (0x7 << 8)
 55 #define JZ_DMA_CMD_BLOCK_MODE                   BIT(7)
 56 #define JZ_DMA_CMD_DESC_VALID                   BIT(4)
 57 #define JZ_DMA_CMD_DESC_VALID_MODE              BIT(3)
 58 #define JZ_DMA_CMD_VALID_IRQ_ENABLE             BIT(2)
 59 #define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE          BIT(1)
 60 #define JZ_DMA_CMD_LINK_ENABLE                  BIT(0)
 61 
 62 #define JZ_DMA_CMD_FLAGS_OFFSET 22
 63 #define JZ_DMA_CMD_RDIL_OFFSET 16
 64 #define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
 65 #define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
 66 #define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
 67 #define JZ_DMA_CMD_MODE_OFFSET 7
 68 
 69 #define JZ_DMA_CTRL_PRIORITY_MASK               (0x3 << 8)
 70 #define JZ_DMA_CTRL_HALT                        BIT(3)
 71 #define JZ_DMA_CTRL_ADDRESS_ERROR               BIT(2)
 72 #define JZ_DMA_CTRL_ENABLE                      BIT(0)
 73 
 74 enum jz4740_dma_width {
 75         JZ4740_DMA_WIDTH_32BIT  = 0,
 76         JZ4740_DMA_WIDTH_8BIT   = 1,
 77         JZ4740_DMA_WIDTH_16BIT  = 2,
 78 };
 79 
 80 enum jz4740_dma_transfer_size {
 81         JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
 82         JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
 83         JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
 84         JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
 85         JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
 86 };
 87 
 88 enum jz4740_dma_flags {
 89         JZ4740_DMA_SRC_AUTOINC = 0x2,
 90         JZ4740_DMA_DST_AUTOINC = 0x1,
 91 };
 92 
 93 enum jz4740_dma_mode {
 94         JZ4740_DMA_MODE_SINGLE  = 0,
 95         JZ4740_DMA_MODE_BLOCK   = 1,
 96 };
 97 
 98 struct jz4740_dma_sg {
 99         dma_addr_t addr;
100         unsigned int len;
101 };
102 
103 struct jz4740_dma_desc {
104         struct virt_dma_desc vdesc;
105 
106         enum dma_transfer_direction direction;
107         bool cyclic;
108 
109         unsigned int num_sgs;
110         struct jz4740_dma_sg sg[];
111 };
112 
113 struct jz4740_dmaengine_chan {
114         struct virt_dma_chan vchan;
115         unsigned int id;
116 
117         dma_addr_t fifo_addr;
118         unsigned int transfer_shift;
119 
120         struct jz4740_dma_desc *desc;
121         unsigned int next_sg;
122 };
123 
124 struct jz4740_dma_dev {
125         struct dma_device ddev;
126         void __iomem *base;
127         struct clk *clk;
128 
129         struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
130 };
131 
132 static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
133         struct jz4740_dmaengine_chan *chan)
134 {
135         return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
136                 ddev);
137 }
138 
139 static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
140 {
141         return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
142 }
143 
144 static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
145 {
146         return container_of(vdesc, struct jz4740_dma_desc, vdesc);
147 }
148 
149 static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
150         unsigned int reg)
151 {
152         return readl(dmadev->base + reg);
153 }
154 
155 static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
156         unsigned reg, uint32_t val)
157 {
158         writel(val, dmadev->base + reg);
159 }
160 
161 static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
162         unsigned int reg, uint32_t val, uint32_t mask)
163 {
164         uint32_t tmp;
165 
166         tmp = jz4740_dma_read(dmadev, reg);
167         tmp &= ~mask;
168         tmp |= val;
169         jz4740_dma_write(dmadev, reg, tmp);
170 }
171 
172 static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
173 {
174         return kzalloc(sizeof(struct jz4740_dma_desc) +
175                 sizeof(struct jz4740_dma_sg) * num_sgs, GFP_ATOMIC);
176 }
177 
178 static enum jz4740_dma_width jz4740_dma_width(enum dma_slave_buswidth width)
179 {
180         switch (width) {
181         case DMA_SLAVE_BUSWIDTH_1_BYTE:
182                 return JZ4740_DMA_WIDTH_8BIT;
183         case DMA_SLAVE_BUSWIDTH_2_BYTES:
184                 return JZ4740_DMA_WIDTH_16BIT;
185         case DMA_SLAVE_BUSWIDTH_4_BYTES:
186                 return JZ4740_DMA_WIDTH_32BIT;
187         default:
188                 return JZ4740_DMA_WIDTH_32BIT;
189         }
190 }
191 
192 static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
193 {
194         if (maxburst <= 1)
195                 return JZ4740_DMA_TRANSFER_SIZE_1BYTE;
196         else if (maxburst <= 3)
197                 return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
198         else if (maxburst <= 15)
199                 return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
200         else if (maxburst <= 31)
201                 return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
202 
203         return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
204 }
205 
206 static int jz4740_dma_slave_config(struct dma_chan *c,
207                                    struct dma_slave_config *config)
208 {
209         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
210         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
211         enum jz4740_dma_width src_width;
212         enum jz4740_dma_width dst_width;
213         enum jz4740_dma_transfer_size transfer_size;
214         enum jz4740_dma_flags flags;
215         uint32_t cmd;
216 
217         switch (config->direction) {
218         case DMA_MEM_TO_DEV:
219                 flags = JZ4740_DMA_SRC_AUTOINC;
220                 transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
221                 chan->fifo_addr = config->dst_addr;
222                 break;
223         case DMA_DEV_TO_MEM:
224                 flags = JZ4740_DMA_DST_AUTOINC;
225                 transfer_size = jz4740_dma_maxburst(config->src_maxburst);
226                 chan->fifo_addr = config->src_addr;
227                 break;
228         default:
229                 return -EINVAL;
230         }
231 
232         src_width = jz4740_dma_width(config->src_addr_width);
233         dst_width = jz4740_dma_width(config->dst_addr_width);
234 
235         switch (transfer_size) {
236         case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
237                 chan->transfer_shift = 1;
238                 break;
239         case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
240                 chan->transfer_shift = 2;
241                 break;
242         case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
243                 chan->transfer_shift = 4;
244                 break;
245         case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
246                 chan->transfer_shift = 5;
247                 break;
248         default:
249                 chan->transfer_shift = 0;
250                 break;
251         }
252 
253         cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
254         cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
255         cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
256         cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
257         cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
258         cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
259 
260         jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
261         jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
262         jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
263                 config->slave_id);
264 
265         return 0;
266 }
267 
268 static int jz4740_dma_terminate_all(struct dma_chan *c)
269 {
270         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
271         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
272         unsigned long flags;
273         LIST_HEAD(head);
274 
275         spin_lock_irqsave(&chan->vchan.lock, flags);
276         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
277                         JZ_DMA_STATUS_CTRL_ENABLE);
278         chan->desc = NULL;
279         vchan_get_all_descriptors(&chan->vchan, &head);
280         spin_unlock_irqrestore(&chan->vchan.lock, flags);
281 
282         vchan_dma_desc_free_list(&chan->vchan, &head);
283 
284         return 0;
285 }
286 
287 static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
288 {
289         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
290         dma_addr_t src_addr, dst_addr;
291         struct virt_dma_desc *vdesc;
292         struct jz4740_dma_sg *sg;
293 
294         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
295                         JZ_DMA_STATUS_CTRL_ENABLE);
296 
297         if (!chan->desc) {
298                 vdesc = vchan_next_desc(&chan->vchan);
299                 if (!vdesc)
300                         return 0;
301                 chan->desc = to_jz4740_dma_desc(vdesc);
302                 chan->next_sg = 0;
303         }
304 
305         if (chan->next_sg == chan->desc->num_sgs)
306                 chan->next_sg = 0;
307 
308         sg = &chan->desc->sg[chan->next_sg];
309 
310         if (chan->desc->direction == DMA_MEM_TO_DEV) {
311                 src_addr = sg->addr;
312                 dst_addr = chan->fifo_addr;
313         } else {
314                 src_addr = chan->fifo_addr;
315                 dst_addr = sg->addr;
316         }
317         jz4740_dma_write(dmadev, JZ_REG_DMA_SRC_ADDR(chan->id), src_addr);
318         jz4740_dma_write(dmadev, JZ_REG_DMA_DST_ADDR(chan->id), dst_addr);
319         jz4740_dma_write(dmadev, JZ_REG_DMA_TRANSFER_COUNT(chan->id),
320                         sg->len >> chan->transfer_shift);
321 
322         chan->next_sg++;
323 
324         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id),
325                         JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
326                         JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
327                         JZ_DMA_STATUS_CTRL_ENABLE);
328 
329         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_CTRL,
330                         JZ_DMA_CTRL_ENABLE,
331                         JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
332 
333         return 0;
334 }
335 
336 static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan *chan)
337 {
338         spin_lock(&chan->vchan.lock);
339         if (chan->desc) {
340                 if (chan->desc->cyclic) {
341                         vchan_cyclic_callback(&chan->desc->vdesc);
342                 } else {
343                         if (chan->next_sg == chan->desc->num_sgs) {
344                                 list_del(&chan->desc->vdesc.node);
345                                 vchan_cookie_complete(&chan->desc->vdesc);
346                                 chan->desc = NULL;
347                         }
348                 }
349         }
350         jz4740_dma_start_transfer(chan);
351         spin_unlock(&chan->vchan.lock);
352 }
353 
354 static irqreturn_t jz4740_dma_irq(int irq, void *devid)
355 {
356         struct jz4740_dma_dev *dmadev = devid;
357         uint32_t irq_status;
358         unsigned int i;
359 
360         irq_status = readl(dmadev->base + JZ_REG_DMA_IRQ);
361 
362         for (i = 0; i < 6; ++i) {
363                 if (irq_status & (1 << i)) {
364                         jz4740_dma_write_mask(dmadev,
365                                 JZ_REG_DMA_STATUS_CTRL(i), 0,
366                                 JZ_DMA_STATUS_CTRL_ENABLE |
367                                 JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
368 
369                         jz4740_dma_chan_irq(&dmadev->chan[i]);
370                 }
371         }
372 
373         return IRQ_HANDLED;
374 }
375 
376 static void jz4740_dma_issue_pending(struct dma_chan *c)
377 {
378         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
379         unsigned long flags;
380 
381         spin_lock_irqsave(&chan->vchan.lock, flags);
382         if (vchan_issue_pending(&chan->vchan) && !chan->desc)
383                 jz4740_dma_start_transfer(chan);
384         spin_unlock_irqrestore(&chan->vchan.lock, flags);
385 }
386 
387 static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg(
388         struct dma_chan *c, struct scatterlist *sgl,
389         unsigned int sg_len, enum dma_transfer_direction direction,
390         unsigned long flags, void *context)
391 {
392         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
393         struct jz4740_dma_desc *desc;
394         struct scatterlist *sg;
395         unsigned int i;
396 
397         desc = jz4740_dma_alloc_desc(sg_len);
398         if (!desc)
399                 return NULL;
400 
401         for_each_sg(sgl, sg, sg_len, i) {
402                 desc->sg[i].addr = sg_dma_address(sg);
403                 desc->sg[i].len = sg_dma_len(sg);
404         }
405 
406         desc->num_sgs = sg_len;
407         desc->direction = direction;
408         desc->cyclic = false;
409 
410         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
411 }
412 
413 static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
414         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
415         size_t period_len, enum dma_transfer_direction direction,
416         unsigned long flags)
417 {
418         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
419         struct jz4740_dma_desc *desc;
420         unsigned int num_periods, i;
421 
422         if (buf_len % period_len)
423                 return NULL;
424 
425         num_periods = buf_len / period_len;
426 
427         desc = jz4740_dma_alloc_desc(num_periods);
428         if (!desc)
429                 return NULL;
430 
431         for (i = 0; i < num_periods; i++) {
432                 desc->sg[i].addr = buf_addr;
433                 desc->sg[i].len = period_len;
434                 buf_addr += period_len;
435         }
436 
437         desc->num_sgs = num_periods;
438         desc->direction = direction;
439         desc->cyclic = true;
440 
441         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
442 }
443 
444 static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
445         struct jz4740_dma_desc *desc, unsigned int next_sg)
446 {
447         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
448         unsigned int residue, count;
449         unsigned int i;
450 
451         residue = 0;
452 
453         for (i = next_sg; i < desc->num_sgs; i++)
454                 residue += desc->sg[i].len;
455 
456         if (next_sg != 0) {
457                 count = jz4740_dma_read(dmadev,
458                         JZ_REG_DMA_TRANSFER_COUNT(chan->id));
459                 residue += count << chan->transfer_shift;
460         }
461 
462         return residue;
463 }
464 
465 static enum dma_status jz4740_dma_tx_status(struct dma_chan *c,
466         dma_cookie_t cookie, struct dma_tx_state *state)
467 {
468         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
469         struct virt_dma_desc *vdesc;
470         enum dma_status status;
471         unsigned long flags;
472 
473         status = dma_cookie_status(c, cookie, state);
474         if (status == DMA_COMPLETE || !state)
475                 return status;
476 
477         spin_lock_irqsave(&chan->vchan.lock, flags);
478         vdesc = vchan_find_desc(&chan->vchan, cookie);
479         if (cookie == chan->desc->vdesc.tx.cookie) {
480                 state->residue = jz4740_dma_desc_residue(chan, chan->desc,
481                                 chan->next_sg);
482         } else if (vdesc) {
483                 state->residue = jz4740_dma_desc_residue(chan,
484                                 to_jz4740_dma_desc(vdesc), 0);
485         } else {
486                 state->residue = 0;
487         }
488         spin_unlock_irqrestore(&chan->vchan.lock, flags);
489 
490         return status;
491 }
492 
493 static void jz4740_dma_free_chan_resources(struct dma_chan *c)
494 {
495         vchan_free_chan_resources(to_virt_chan(c));
496 }
497 
498 static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
499 {
500         kfree(container_of(vdesc, struct jz4740_dma_desc, vdesc));
501 }
502 
503 #define JZ4740_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
504         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
505 
506 static int jz4740_dma_probe(struct platform_device *pdev)
507 {
508         struct jz4740_dmaengine_chan *chan;
509         struct jz4740_dma_dev *dmadev;
510         struct dma_device *dd;
511         unsigned int i;
512         struct resource *res;
513         int ret;
514         int irq;
515 
516         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
517         if (!dmadev)
518                 return -EINVAL;
519 
520         dd = &dmadev->ddev;
521 
522         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
523         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
524         if (IS_ERR(dmadev->base))
525                 return PTR_ERR(dmadev->base);
526 
527         dmadev->clk = clk_get(&pdev->dev, "dma");
528         if (IS_ERR(dmadev->clk))
529                 return PTR_ERR(dmadev->clk);
530 
531         clk_prepare_enable(dmadev->clk);
532 
533         dma_cap_set(DMA_SLAVE, dd->cap_mask);
534         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
535         dd->device_free_chan_resources = jz4740_dma_free_chan_resources;
536         dd->device_tx_status = jz4740_dma_tx_status;
537         dd->device_issue_pending = jz4740_dma_issue_pending;
538         dd->device_prep_slave_sg = jz4740_dma_prep_slave_sg;
539         dd->device_prep_dma_cyclic = jz4740_dma_prep_dma_cyclic;
540         dd->device_config = jz4740_dma_slave_config;
541         dd->device_terminate_all = jz4740_dma_terminate_all;
542         dd->src_addr_widths = JZ4740_DMA_BUSWIDTHS;
543         dd->dst_addr_widths = JZ4740_DMA_BUSWIDTHS;
544         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
545         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
546         dd->dev = &pdev->dev;
547         INIT_LIST_HEAD(&dd->channels);
548 
549         for (i = 0; i < JZ_DMA_NR_CHANS; i++) {
550                 chan = &dmadev->chan[i];
551                 chan->id = i;
552                 chan->vchan.desc_free = jz4740_dma_desc_free;
553                 vchan_init(&chan->vchan, dd);
554         }
555 
556         ret = dma_async_device_register(dd);
557         if (ret)
558                 return ret;
559 
560         irq = platform_get_irq(pdev, 0);
561         ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
562         if (ret)
563                 goto err_unregister;
564 
565         platform_set_drvdata(pdev, dmadev);
566 
567         return 0;
568 
569 err_unregister:
570         dma_async_device_unregister(dd);
571         return ret;
572 }
573 
574 static void jz4740_cleanup_vchan(struct dma_device *dmadev)
575 {
576         struct jz4740_dmaengine_chan *chan, *_chan;
577 
578         list_for_each_entry_safe(chan, _chan,
579                                 &dmadev->channels, vchan.chan.device_node) {
580                 list_del(&chan->vchan.chan.device_node);
581                 tasklet_kill(&chan->vchan.task);
582         }
583 }
584 
585 
586 static int jz4740_dma_remove(struct platform_device *pdev)
587 {
588         struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
589         int irq = platform_get_irq(pdev, 0);
590 
591         free_irq(irq, dmadev);
592 
593         jz4740_cleanup_vchan(&dmadev->ddev);
594         dma_async_device_unregister(&dmadev->ddev);
595         clk_disable_unprepare(dmadev->clk);
596 
597         return 0;
598 }
599 
600 static struct platform_driver jz4740_dma_driver = {
601         .probe = jz4740_dma_probe,
602         .remove = jz4740_dma_remove,
603         .driver = {
604                 .name = "jz4740-dma",
605         },
606 };
607 module_platform_driver(jz4740_dma_driver);
608 
609 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
610 MODULE_DESCRIPTION("JZ4740 DMA driver");
611 MODULE_LICENSE("GPL v2");
612 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us