Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/drivers/crypto/talitos.c

  1 /*
  2  * talitos - Freescale Integrated Security Engine (SEC) device driver
  3  *
  4  * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
  5  *
  6  * Scatterlist Crypto API glue code copied from files with the following:
  7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
  8  *
  9  * Crypto algorithm registration code copied from hifn driver:
 10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
 11  * All rights reserved.
 12  *
 13  * This program is free software; you can redistribute it and/or modify
 14  * it under the terms of the GNU General Public License as published by
 15  * the Free Software Foundation; either version 2 of the License, or
 16  * (at your option) any later version.
 17  *
 18  * This program is distributed in the hope that it will be useful,
 19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 21  * GNU General Public License for more details.
 22  *
 23  * You should have received a copy of the GNU General Public License
 24  * along with this program; if not, write to the Free Software
 25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 26  */
 27 
 28 #include <linux/kernel.h>
 29 #include <linux/module.h>
 30 #include <linux/mod_devicetable.h>
 31 #include <linux/device.h>
 32 #include <linux/interrupt.h>
 33 #include <linux/crypto.h>
 34 #include <linux/hw_random.h>
 35 #include <linux/of_address.h>
 36 #include <linux/of_irq.h>
 37 #include <linux/of_platform.h>
 38 #include <linux/dma-mapping.h>
 39 #include <linux/io.h>
 40 #include <linux/spinlock.h>
 41 #include <linux/rtnetlink.h>
 42 #include <linux/slab.h>
 43 
 44 #include <crypto/algapi.h>
 45 #include <crypto/aes.h>
 46 #include <crypto/des.h>
 47 #include <crypto/sha.h>
 48 #include <crypto/md5.h>
 49 #include <crypto/aead.h>
 50 #include <crypto/authenc.h>
 51 #include <crypto/skcipher.h>
 52 #include <crypto/hash.h>
 53 #include <crypto/internal/hash.h>
 54 #include <crypto/scatterwalk.h>
 55 
 56 #include "talitos.h"
 57 
 58 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
 59 {
 60         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
 61         talitos_ptr->eptr = upper_32_bits(dma_addr);
 62 }
 63 
 64 /*
 65  * map virtual single (contiguous) pointer to h/w descriptor pointer
 66  */
 67 static void map_single_talitos_ptr(struct device *dev,
 68                                    struct talitos_ptr *talitos_ptr,
 69                                    unsigned short len, void *data,
 70                                    unsigned char extent,
 71                                    enum dma_data_direction dir)
 72 {
 73         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
 74 
 75         talitos_ptr->len = cpu_to_be16(len);
 76         to_talitos_ptr(talitos_ptr, dma_addr);
 77         talitos_ptr->j_extent = extent;
 78 }
 79 
 80 /*
 81  * unmap bus single (contiguous) h/w descriptor pointer
 82  */
 83 static void unmap_single_talitos_ptr(struct device *dev,
 84                                      struct talitos_ptr *talitos_ptr,
 85                                      enum dma_data_direction dir)
 86 {
 87         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
 88                          be16_to_cpu(talitos_ptr->len), dir);
 89 }
 90 
 91 static int reset_channel(struct device *dev, int ch)
 92 {
 93         struct talitos_private *priv = dev_get_drvdata(dev);
 94         unsigned int timeout = TALITOS_TIMEOUT;
 95 
 96         setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
 97 
 98         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
 99                && --timeout)
100                 cpu_relax();
101 
102         if (timeout == 0) {
103                 dev_err(dev, "failed to reset channel %d\n", ch);
104                 return -EIO;
105         }
106 
107         /* set 36-bit addressing, done writeback enable and done IRQ enable */
108         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
109                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
110 
111         /* and ICCR writeback, if available */
112         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
113                 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
114                           TALITOS_CCCR_LO_IWSE);
115 
116         return 0;
117 }
118 
119 static int reset_device(struct device *dev)
120 {
121         struct talitos_private *priv = dev_get_drvdata(dev);
122         unsigned int timeout = TALITOS_TIMEOUT;
123         u32 mcr = TALITOS_MCR_SWR;
124 
125         setbits32(priv->reg + TALITOS_MCR, mcr);
126 
127         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
128                && --timeout)
129                 cpu_relax();
130 
131         if (priv->irq[1]) {
132                 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
133                 setbits32(priv->reg + TALITOS_MCR, mcr);
134         }
135 
136         if (timeout == 0) {
137                 dev_err(dev, "failed to reset device\n");
138                 return -EIO;
139         }
140 
141         return 0;
142 }
143 
144 /*
145  * Reset and initialize the device
146  */
147 static int init_device(struct device *dev)
148 {
149         struct talitos_private *priv = dev_get_drvdata(dev);
150         int ch, err;
151 
152         /*
153          * Master reset
154          * errata documentation: warning: certain SEC interrupts
155          * are not fully cleared by writing the MCR:SWR bit,
156          * set bit twice to completely reset
157          */
158         err = reset_device(dev);
159         if (err)
160                 return err;
161 
162         err = reset_device(dev);
163         if (err)
164                 return err;
165 
166         /* reset channels */
167         for (ch = 0; ch < priv->num_channels; ch++) {
168                 err = reset_channel(dev, ch);
169                 if (err)
170                         return err;
171         }
172 
173         /* enable channel done and error interrupts */
174         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
175         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
176 
177         /* disable integrity check error interrupts (use writeback instead) */
178         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
179                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
180                           TALITOS_MDEUICR_LO_ICE);
181 
182         return 0;
183 }
184 
185 /**
186  * talitos_submit - submits a descriptor to the device for processing
187  * @dev:        the SEC device to be used
188  * @ch:         the SEC device channel to be used
189  * @desc:       the descriptor to be processed by the device
190  * @callback:   whom to call when processing is complete
191  * @context:    a handle for use by caller (optional)
192  *
193  * desc must contain valid dma-mapped (bus physical) address pointers.
194  * callback must check err and feedback in descriptor header
195  * for device processing status.
196  */
197 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
198                    void (*callback)(struct device *dev,
199                                     struct talitos_desc *desc,
200                                     void *context, int error),
201                    void *context)
202 {
203         struct talitos_private *priv = dev_get_drvdata(dev);
204         struct talitos_request *request;
205         unsigned long flags;
206         int head;
207 
208         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
209 
210         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
211                 /* h/w fifo is full */
212                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
213                 return -EAGAIN;
214         }
215 
216         head = priv->chan[ch].head;
217         request = &priv->chan[ch].fifo[head];
218 
219         /* map descriptor and save caller data */
220         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
221                                            DMA_BIDIRECTIONAL);
222         request->callback = callback;
223         request->context = context;
224 
225         /* increment fifo head */
226         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
227 
228         smp_wmb();
229         request->desc = desc;
230 
231         /* GO! */
232         wmb();
233         out_be32(priv->chan[ch].reg + TALITOS_FF,
234                  upper_32_bits(request->dma_desc));
235         out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
236                  lower_32_bits(request->dma_desc));
237 
238         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
239 
240         return -EINPROGRESS;
241 }
242 EXPORT_SYMBOL(talitos_submit);
243 
244 /*
245  * process what was done, notify callback of error if not
246  */
247 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
248 {
249         struct talitos_private *priv = dev_get_drvdata(dev);
250         struct talitos_request *request, saved_req;
251         unsigned long flags;
252         int tail, status;
253 
254         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
255 
256         tail = priv->chan[ch].tail;
257         while (priv->chan[ch].fifo[tail].desc) {
258                 request = &priv->chan[ch].fifo[tail];
259 
260                 /* descriptors with their done bits set don't get the error */
261                 rmb();
262                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
263                         status = 0;
264                 else
265                         if (!error)
266                                 break;
267                         else
268                                 status = error;
269 
270                 dma_unmap_single(dev, request->dma_desc,
271                                  sizeof(struct talitos_desc),
272                                  DMA_BIDIRECTIONAL);
273 
274                 /* copy entries so we can call callback outside lock */
275                 saved_req.desc = request->desc;
276                 saved_req.callback = request->callback;
277                 saved_req.context = request->context;
278 
279                 /* release request entry in fifo */
280                 smp_wmb();
281                 request->desc = NULL;
282 
283                 /* increment fifo tail */
284                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
285 
286                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
287 
288                 atomic_dec(&priv->chan[ch].submit_count);
289 
290                 saved_req.callback(dev, saved_req.desc, saved_req.context,
291                                    status);
292                 /* channel may resume processing in single desc error case */
293                 if (error && !reset_ch && status == error)
294                         return;
295                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
296                 tail = priv->chan[ch].tail;
297         }
298 
299         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
300 }
301 
302 /*
303  * process completed requests for channels that have done status
304  */
305 #define DEF_TALITOS_DONE(name, ch_done_mask)                            \
306 static void talitos_done_##name(unsigned long data)                     \
307 {                                                                       \
308         struct device *dev = (struct device *)data;                     \
309         struct talitos_private *priv = dev_get_drvdata(dev);            \
310         unsigned long flags;                                            \
311                                                                         \
312         if (ch_done_mask & 1)                                           \
313                 flush_channel(dev, 0, 0, 0);                            \
314         if (priv->num_channels == 1)                                    \
315                 goto out;                                               \
316         if (ch_done_mask & (1 << 2))                                    \
317                 flush_channel(dev, 1, 0, 0);                            \
318         if (ch_done_mask & (1 << 4))                                    \
319                 flush_channel(dev, 2, 0, 0);                            \
320         if (ch_done_mask & (1 << 6))                                    \
321                 flush_channel(dev, 3, 0, 0);                            \
322                                                                         \
323 out:                                                                    \
324         /* At this point, all completed channels have been processed */ \
325         /* Unmask done interrupts for channels completed later on. */   \
326         spin_lock_irqsave(&priv->reg_lock, flags);                      \
327         setbits32(priv->reg + TALITOS_IMR, ch_done_mask);               \
328         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);     \
329         spin_unlock_irqrestore(&priv->reg_lock, flags);                 \
330 }
331 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
332 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
333 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
334 
335 /*
336  * locate current (offending) descriptor
337  */
338 static u32 current_desc_hdr(struct device *dev, int ch)
339 {
340         struct talitos_private *priv = dev_get_drvdata(dev);
341         int tail, iter;
342         dma_addr_t cur_desc;
343 
344         cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
345         cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
346 
347         if (!cur_desc) {
348                 dev_err(dev, "CDPR is NULL, giving up search for offending descriptor\n");
349                 return 0;
350         }
351 
352         tail = priv->chan[ch].tail;
353 
354         iter = tail;
355         while (priv->chan[ch].fifo[iter].dma_desc != cur_desc) {
356                 iter = (iter + 1) & (priv->fifo_len - 1);
357                 if (iter == tail) {
358                         dev_err(dev, "couldn't locate current descriptor\n");
359                         return 0;
360                 }
361         }
362 
363         return priv->chan[ch].fifo[iter].desc->hdr;
364 }
365 
366 /*
367  * user diagnostics; report root cause of error based on execution unit status
368  */
369 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
370 {
371         struct talitos_private *priv = dev_get_drvdata(dev);
372         int i;
373 
374         if (!desc_hdr)
375                 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
376 
377         switch (desc_hdr & DESC_HDR_SEL0_MASK) {
378         case DESC_HDR_SEL0_AFEU:
379                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
380                         in_be32(priv->reg + TALITOS_AFEUISR),
381                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
382                 break;
383         case DESC_HDR_SEL0_DEU:
384                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
385                         in_be32(priv->reg + TALITOS_DEUISR),
386                         in_be32(priv->reg + TALITOS_DEUISR_LO));
387                 break;
388         case DESC_HDR_SEL0_MDEUA:
389         case DESC_HDR_SEL0_MDEUB:
390                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
391                         in_be32(priv->reg + TALITOS_MDEUISR),
392                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
393                 break;
394         case DESC_HDR_SEL0_RNG:
395                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
396                         in_be32(priv->reg + TALITOS_RNGUISR),
397                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
398                 break;
399         case DESC_HDR_SEL0_PKEU:
400                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
401                         in_be32(priv->reg + TALITOS_PKEUISR),
402                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
403                 break;
404         case DESC_HDR_SEL0_AESU:
405                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
406                         in_be32(priv->reg + TALITOS_AESUISR),
407                         in_be32(priv->reg + TALITOS_AESUISR_LO));
408                 break;
409         case DESC_HDR_SEL0_CRCU:
410                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
411                         in_be32(priv->reg + TALITOS_CRCUISR),
412                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
413                 break;
414         case DESC_HDR_SEL0_KEU:
415                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
416                         in_be32(priv->reg + TALITOS_KEUISR),
417                         in_be32(priv->reg + TALITOS_KEUISR_LO));
418                 break;
419         }
420 
421         switch (desc_hdr & DESC_HDR_SEL1_MASK) {
422         case DESC_HDR_SEL1_MDEUA:
423         case DESC_HDR_SEL1_MDEUB:
424                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
425                         in_be32(priv->reg + TALITOS_MDEUISR),
426                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
427                 break;
428         case DESC_HDR_SEL1_CRCU:
429                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
430                         in_be32(priv->reg + TALITOS_CRCUISR),
431                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
432                 break;
433         }
434 
435         for (i = 0; i < 8; i++)
436                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
437                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
438                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
439 }
440 
441 /*
442  * recover from error interrupts
443  */
444 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
445 {
446         struct talitos_private *priv = dev_get_drvdata(dev);
447         unsigned int timeout = TALITOS_TIMEOUT;
448         int ch, error, reset_dev = 0, reset_ch = 0;
449         u32 v, v_lo;
450 
451         for (ch = 0; ch < priv->num_channels; ch++) {
452                 /* skip channels without errors */
453                 if (!(isr & (1 << (ch * 2 + 1))))
454                         continue;
455 
456                 error = -EINVAL;
457 
458                 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
459                 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
460 
461                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
462                         dev_err(dev, "double fetch fifo overflow error\n");
463                         error = -EAGAIN;
464                         reset_ch = 1;
465                 }
466                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
467                         /* h/w dropped descriptor */
468                         dev_err(dev, "single fetch fifo overflow error\n");
469                         error = -EAGAIN;
470                 }
471                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
472                         dev_err(dev, "master data transfer error\n");
473                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
474                         dev_err(dev, "s/g data length zero error\n");
475                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
476                         dev_err(dev, "fetch pointer zero error\n");
477                 if (v_lo & TALITOS_CCPSR_LO_IDH)
478                         dev_err(dev, "illegal descriptor header error\n");
479                 if (v_lo & TALITOS_CCPSR_LO_IEU)
480                         dev_err(dev, "invalid execution unit error\n");
481                 if (v_lo & TALITOS_CCPSR_LO_EU)
482                         report_eu_error(dev, ch, current_desc_hdr(dev, ch));
483                 if (v_lo & TALITOS_CCPSR_LO_GB)
484                         dev_err(dev, "gather boundary error\n");
485                 if (v_lo & TALITOS_CCPSR_LO_GRL)
486                         dev_err(dev, "gather return/length error\n");
487                 if (v_lo & TALITOS_CCPSR_LO_SB)
488                         dev_err(dev, "scatter boundary error\n");
489                 if (v_lo & TALITOS_CCPSR_LO_SRL)
490                         dev_err(dev, "scatter return/length error\n");
491 
492                 flush_channel(dev, ch, error, reset_ch);
493 
494                 if (reset_ch) {
495                         reset_channel(dev, ch);
496                 } else {
497                         setbits32(priv->chan[ch].reg + TALITOS_CCCR,
498                                   TALITOS_CCCR_CONT);
499                         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
500                         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
501                                TALITOS_CCCR_CONT) && --timeout)
502                                 cpu_relax();
503                         if (timeout == 0) {
504                                 dev_err(dev, "failed to restart channel %d\n",
505                                         ch);
506                                 reset_dev = 1;
507                         }
508                 }
509         }
510         if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
511                 dev_err(dev, "done overflow, internal time out, or rngu error: "
512                         "ISR 0x%08x_%08x\n", isr, isr_lo);
513 
514                 /* purge request queues */
515                 for (ch = 0; ch < priv->num_channels; ch++)
516                         flush_channel(dev, ch, -EIO, 1);
517 
518                 /* reset and reinitialize the device */
519                 init_device(dev);
520         }
521 }
522 
523 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)           \
524 static irqreturn_t talitos_interrupt_##name(int irq, void *data)               \
525 {                                                                              \
526         struct device *dev = data;                                             \
527         struct talitos_private *priv = dev_get_drvdata(dev);                   \
528         u32 isr, isr_lo;                                                       \
529         unsigned long flags;                                                   \
530                                                                                \
531         spin_lock_irqsave(&priv->reg_lock, flags);                             \
532         isr = in_be32(priv->reg + TALITOS_ISR);                                \
533         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);                          \
534         /* Acknowledge interrupt */                                            \
535         out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
536         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);                          \
537                                                                                \
538         if (unlikely(isr & ch_err_mask || isr_lo)) {                           \
539                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
540                 talitos_error(dev, isr & ch_err_mask, isr_lo);                 \
541         }                                                                      \
542         else {                                                                 \
543                 if (likely(isr & ch_done_mask)) {                              \
544                         /* mask further done interrupts. */                    \
545                         clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
546                         /* done_task will unmask done interrupts at exit */    \
547                         tasklet_schedule(&priv->done_task[tlet]);              \
548                 }                                                              \
549                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
550         }                                                                      \
551                                                                                \
552         return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
553                                                                 IRQ_NONE;      \
554 }
555 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
556 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
557 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
558 
559 /*
560  * hwrng
561  */
562 static int talitos_rng_data_present(struct hwrng *rng, int wait)
563 {
564         struct device *dev = (struct device *)rng->priv;
565         struct talitos_private *priv = dev_get_drvdata(dev);
566         u32 ofl;
567         int i;
568 
569         for (i = 0; i < 20; i++) {
570                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
571                       TALITOS_RNGUSR_LO_OFL;
572                 if (ofl || !wait)
573                         break;
574                 udelay(10);
575         }
576 
577         return !!ofl;
578 }
579 
580 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
581 {
582         struct device *dev = (struct device *)rng->priv;
583         struct talitos_private *priv = dev_get_drvdata(dev);
584 
585         /* rng fifo requires 64-bit accesses */
586         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
587         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
588 
589         return sizeof(u32);
590 }
591 
592 static int talitos_rng_init(struct hwrng *rng)
593 {
594         struct device *dev = (struct device *)rng->priv;
595         struct talitos_private *priv = dev_get_drvdata(dev);
596         unsigned int timeout = TALITOS_TIMEOUT;
597 
598         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
599         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
600                && --timeout)
601                 cpu_relax();
602         if (timeout == 0) {
603                 dev_err(dev, "failed to reset rng hw\n");
604                 return -ENODEV;
605         }
606 
607         /* start generating */
608         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
609 
610         return 0;
611 }
612 
613 static int talitos_register_rng(struct device *dev)
614 {
615         struct talitos_private *priv = dev_get_drvdata(dev);
616 
617         priv->rng.name          = dev_driver_string(dev),
618         priv->rng.init          = talitos_rng_init,
619         priv->rng.data_present  = talitos_rng_data_present,
620         priv->rng.data_read     = talitos_rng_data_read,
621         priv->rng.priv          = (unsigned long)dev;
622 
623         return hwrng_register(&priv->rng);
624 }
625 
626 static void talitos_unregister_rng(struct device *dev)
627 {
628         struct talitos_private *priv = dev_get_drvdata(dev);
629 
630         hwrng_unregister(&priv->rng);
631 }
632 
633 /*
634  * crypto alg
635  */
636 #define TALITOS_CRA_PRIORITY            3000
637 #define TALITOS_MAX_KEY_SIZE            96
638 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
639 
640 struct talitos_ctx {
641         struct device *dev;
642         int ch;
643         __be32 desc_hdr_template;
644         u8 key[TALITOS_MAX_KEY_SIZE];
645         u8 iv[TALITOS_MAX_IV_LENGTH];
646         unsigned int keylen;
647         unsigned int enckeylen;
648         unsigned int authkeylen;
649         unsigned int authsize;
650 };
651 
652 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
653 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
654 
655 struct talitos_ahash_req_ctx {
656         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
657         unsigned int hw_context_size;
658         u8 buf[HASH_MAX_BLOCK_SIZE];
659         u8 bufnext[HASH_MAX_BLOCK_SIZE];
660         unsigned int swinit;
661         unsigned int first;
662         unsigned int last;
663         unsigned int to_hash_later;
664         u64 nbuf;
665         struct scatterlist bufsl[2];
666         struct scatterlist *psrc;
667 };
668 
669 static int aead_setauthsize(struct crypto_aead *authenc,
670                             unsigned int authsize)
671 {
672         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
673 
674         ctx->authsize = authsize;
675 
676         return 0;
677 }
678 
679 static int aead_setkey(struct crypto_aead *authenc,
680                        const u8 *key, unsigned int keylen)
681 {
682         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
683         struct crypto_authenc_keys keys;
684 
685         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
686                 goto badkey;
687 
688         if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
689                 goto badkey;
690 
691         memcpy(ctx->key, keys.authkey, keys.authkeylen);
692         memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
693 
694         ctx->keylen = keys.authkeylen + keys.enckeylen;
695         ctx->enckeylen = keys.enckeylen;
696         ctx->authkeylen = keys.authkeylen;
697 
698         return 0;
699 
700 badkey:
701         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
702         return -EINVAL;
703 }
704 
705 /*
706  * talitos_edesc - s/w-extended descriptor
707  * @assoc_nents: number of segments in associated data scatterlist
708  * @src_nents: number of segments in input scatterlist
709  * @dst_nents: number of segments in output scatterlist
710  * @assoc_chained: whether assoc is chained or not
711  * @src_chained: whether src is chained or not
712  * @dst_chained: whether dst is chained or not
713  * @iv_dma: dma address of iv for checking continuity and link table
714  * @dma_len: length of dma mapped link_tbl space
715  * @dma_link_tbl: bus physical address of link_tbl
716  * @desc: h/w descriptor
717  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
718  *
719  * if decrypting (with authcheck), or either one of src_nents or dst_nents
720  * is greater than 1, an integrity check value is concatenated to the end
721  * of link_tbl data
722  */
723 struct talitos_edesc {
724         int assoc_nents;
725         int src_nents;
726         int dst_nents;
727         bool assoc_chained;
728         bool src_chained;
729         bool dst_chained;
730         dma_addr_t iv_dma;
731         int dma_len;
732         dma_addr_t dma_link_tbl;
733         struct talitos_desc desc;
734         struct talitos_ptr link_tbl[0];
735 };
736 
737 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
738                           unsigned int nents, enum dma_data_direction dir,
739                           bool chained)
740 {
741         if (unlikely(chained))
742                 while (sg) {
743                         dma_map_sg(dev, sg, 1, dir);
744                         sg = sg_next(sg);
745                 }
746         else
747                 dma_map_sg(dev, sg, nents, dir);
748         return nents;
749 }
750 
751 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
752                                    enum dma_data_direction dir)
753 {
754         while (sg) {
755                 dma_unmap_sg(dev, sg, 1, dir);
756                 sg = sg_next(sg);
757         }
758 }
759 
760 static void talitos_sg_unmap(struct device *dev,
761                              struct talitos_edesc *edesc,
762                              struct scatterlist *src,
763                              struct scatterlist *dst)
764 {
765         unsigned int src_nents = edesc->src_nents ? : 1;
766         unsigned int dst_nents = edesc->dst_nents ? : 1;
767 
768         if (src != dst) {
769                 if (edesc->src_chained)
770                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
771                 else
772                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
773 
774                 if (dst) {
775                         if (edesc->dst_chained)
776                                 talitos_unmap_sg_chain(dev, dst,
777                                                        DMA_FROM_DEVICE);
778                         else
779                                 dma_unmap_sg(dev, dst, dst_nents,
780                                              DMA_FROM_DEVICE);
781                 }
782         } else
783                 if (edesc->src_chained)
784                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
785                 else
786                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
787 }
788 
789 static void ipsec_esp_unmap(struct device *dev,
790                             struct talitos_edesc *edesc,
791                             struct aead_request *areq)
792 {
793         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
794         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
795         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
796         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
797 
798         if (edesc->assoc_chained)
799                 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
800         else if (areq->assoclen)
801                 /* assoc_nents counts also for IV in non-contiguous cases */
802                 dma_unmap_sg(dev, areq->assoc,
803                              edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
804                              DMA_TO_DEVICE);
805 
806         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
807 
808         if (edesc->dma_len)
809                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
810                                  DMA_BIDIRECTIONAL);
811 }
812 
813 /*
814  * ipsec_esp descriptor callbacks
815  */
816 static void ipsec_esp_encrypt_done(struct device *dev,
817                                    struct talitos_desc *desc, void *context,
818                                    int err)
819 {
820         struct aead_request *areq = context;
821         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
822         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
823         struct talitos_edesc *edesc;
824         struct scatterlist *sg;
825         void *icvdata;
826 
827         edesc = container_of(desc, struct talitos_edesc, desc);
828 
829         ipsec_esp_unmap(dev, edesc, areq);
830 
831         /* copy the generated ICV to dst */
832         if (edesc->dst_nents) {
833                 icvdata = &edesc->link_tbl[edesc->src_nents +
834                                            edesc->dst_nents + 2 +
835                                            edesc->assoc_nents];
836                 sg = sg_last(areq->dst, edesc->dst_nents);
837                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
838                        icvdata, ctx->authsize);
839         }
840 
841         kfree(edesc);
842 
843         aead_request_complete(areq, err);
844 }
845 
846 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
847                                           struct talitos_desc *desc,
848                                           void *context, int err)
849 {
850         struct aead_request *req = context;
851         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
852         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
853         struct talitos_edesc *edesc;
854         struct scatterlist *sg;
855         void *icvdata;
856 
857         edesc = container_of(desc, struct talitos_edesc, desc);
858 
859         ipsec_esp_unmap(dev, edesc, req);
860 
861         if (!err) {
862                 /* auth check */
863                 if (edesc->dma_len)
864                         icvdata = &edesc->link_tbl[edesc->src_nents +
865                                                    edesc->dst_nents + 2 +
866                                                    edesc->assoc_nents];
867                 else
868                         icvdata = &edesc->link_tbl[0];
869 
870                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
871                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
872                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
873         }
874 
875         kfree(edesc);
876 
877         aead_request_complete(req, err);
878 }
879 
880 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
881                                           struct talitos_desc *desc,
882                                           void *context, int err)
883 {
884         struct aead_request *req = context;
885         struct talitos_edesc *edesc;
886 
887         edesc = container_of(desc, struct talitos_edesc, desc);
888 
889         ipsec_esp_unmap(dev, edesc, req);
890 
891         /* check ICV auth status */
892         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
893                      DESC_HDR_LO_ICCR1_PASS))
894                 err = -EBADMSG;
895 
896         kfree(edesc);
897 
898         aead_request_complete(req, err);
899 }
900 
901 /*
902  * convert scatterlist to SEC h/w link table format
903  * stop at cryptlen bytes
904  */
905 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
906                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
907 {
908         int n_sg = sg_count;
909 
910         while (n_sg--) {
911                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
912                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
913                 link_tbl_ptr->j_extent = 0;
914                 link_tbl_ptr++;
915                 cryptlen -= sg_dma_len(sg);
916                 sg = sg_next(sg);
917         }
918 
919         /* adjust (decrease) last one (or two) entry's len to cryptlen */
920         link_tbl_ptr--;
921         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
922                 /* Empty this entry, and move to previous one */
923                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
924                 link_tbl_ptr->len = 0;
925                 sg_count--;
926                 link_tbl_ptr--;
927         }
928         be16_add_cpu(&link_tbl_ptr->len, cryptlen);
929 
930         /* tag end of link table */
931         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
932 
933         return sg_count;
934 }
935 
936 /*
937  * fill in and submit ipsec_esp descriptor
938  */
939 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
940                      u64 seq, void (*callback) (struct device *dev,
941                                                 struct talitos_desc *desc,
942                                                 void *context, int error))
943 {
944         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
945         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
946         struct device *dev = ctx->dev;
947         struct talitos_desc *desc = &edesc->desc;
948         unsigned int cryptlen = areq->cryptlen;
949         unsigned int authsize = ctx->authsize;
950         unsigned int ivsize = crypto_aead_ivsize(aead);
951         int sg_count, ret;
952         int sg_link_tbl_len;
953 
954         /* hmac key */
955         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
956                                0, DMA_TO_DEVICE);
957 
958         /* hmac data */
959         desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
960         if (edesc->assoc_nents) {
961                 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
962                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
963 
964                 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
965                                sizeof(struct talitos_ptr));
966                 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
967 
968                 /* assoc_nents - 1 entries for assoc, 1 for IV */
969                 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
970                                           areq->assoclen, tbl_ptr);
971 
972                 /* add IV to link table */
973                 tbl_ptr += sg_count - 1;
974                 tbl_ptr->j_extent = 0;
975                 tbl_ptr++;
976                 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
977                 tbl_ptr->len = cpu_to_be16(ivsize);
978                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
979 
980                 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
981                                            edesc->dma_len, DMA_BIDIRECTIONAL);
982         } else {
983                 if (areq->assoclen)
984                         to_talitos_ptr(&desc->ptr[1],
985                                        sg_dma_address(areq->assoc));
986                 else
987                         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
988                 desc->ptr[1].j_extent = 0;
989         }
990 
991         /* cipher iv */
992         to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
993         desc->ptr[2].len = cpu_to_be16(ivsize);
994         desc->ptr[2].j_extent = 0;
995         /* Sync needed for the aead_givencrypt case */
996         dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
997 
998         /* cipher key */
999         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1000                                (char *)&ctx->key + ctx->authkeylen, 0,
1001                                DMA_TO_DEVICE);
1002 
1003         /*
1004          * cipher in
1005          * map and adjust cipher len to aead request cryptlen.
1006          * extent is bytes of HMAC postpended to ciphertext,
1007          * typically 12 for ipsec
1008          */
1009         desc->ptr[4].len = cpu_to_be16(cryptlen);
1010         desc->ptr[4].j_extent = authsize;
1011 
1012         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1013                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1014                                                            : DMA_TO_DEVICE,
1015                                   edesc->src_chained);
1016 
1017         if (sg_count == 1) {
1018                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1019         } else {
1020                 sg_link_tbl_len = cryptlen;
1021 
1022                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1023                         sg_link_tbl_len = cryptlen + authsize;
1024 
1025                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1026                                           &edesc->link_tbl[0]);
1027                 if (sg_count > 1) {
1028                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1029                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1030                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1031                                                    edesc->dma_len,
1032                                                    DMA_BIDIRECTIONAL);
1033                 } else {
1034                         /* Only one segment now, so no link tbl needed */
1035                         to_talitos_ptr(&desc->ptr[4],
1036                                        sg_dma_address(areq->src));
1037                 }
1038         }
1039 
1040         /* cipher out */
1041         desc->ptr[5].len = cpu_to_be16(cryptlen);
1042         desc->ptr[5].j_extent = authsize;
1043 
1044         if (areq->src != areq->dst)
1045                 sg_count = talitos_map_sg(dev, areq->dst,
1046                                           edesc->dst_nents ? : 1,
1047                                           DMA_FROM_DEVICE, edesc->dst_chained);
1048 
1049         if (sg_count == 1) {
1050                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1051         } else {
1052                 int tbl_off = edesc->src_nents + 1;
1053                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1054 
1055                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1056                                tbl_off * sizeof(struct talitos_ptr));
1057                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1058                                           tbl_ptr);
1059 
1060                 /* Add an entry to the link table for ICV data */
1061                 tbl_ptr += sg_count - 1;
1062                 tbl_ptr->j_extent = 0;
1063                 tbl_ptr++;
1064                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1065                 tbl_ptr->len = cpu_to_be16(authsize);
1066 
1067                 /* icv data follows link tables */
1068                 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1069                                (tbl_off + edesc->dst_nents + 1 +
1070                                 edesc->assoc_nents) *
1071                                sizeof(struct talitos_ptr));
1072                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1073                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1074                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1075         }
1076 
1077         /* iv out */
1078         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1079                                DMA_FROM_DEVICE);
1080 
1081         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1082         if (ret != -EINPROGRESS) {
1083                 ipsec_esp_unmap(dev, edesc, areq);
1084                 kfree(edesc);
1085         }
1086         return ret;
1087 }
1088 
1089 /*
1090  * derive number of elements in scatterlist
1091  */
1092 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1093 {
1094         struct scatterlist *sg = sg_list;
1095         int sg_nents = 0;
1096 
1097         *chained = false;
1098         while (nbytes > 0) {
1099                 sg_nents++;
1100                 nbytes -= sg->length;
1101                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1102                         *chained = true;
1103                 sg = sg_next(sg);
1104         }
1105 
1106         return sg_nents;
1107 }
1108 
1109 /*
1110  * allocate and map the extended descriptor
1111  */
1112 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1113                                                  struct scatterlist *assoc,
1114                                                  struct scatterlist *src,
1115                                                  struct scatterlist *dst,
1116                                                  u8 *iv,
1117                                                  unsigned int assoclen,
1118                                                  unsigned int cryptlen,
1119                                                  unsigned int authsize,
1120                                                  unsigned int ivsize,
1121                                                  int icv_stashing,
1122                                                  u32 cryptoflags,
1123                                                  bool encrypt)
1124 {
1125         struct talitos_edesc *edesc;
1126         int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1127         bool assoc_chained = false, src_chained = false, dst_chained = false;
1128         dma_addr_t iv_dma = 0;
1129         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1130                       GFP_ATOMIC;
1131 
1132         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1133                 dev_err(dev, "length exceeds h/w max limit\n");
1134                 return ERR_PTR(-EINVAL);
1135         }
1136 
1137         if (ivsize)
1138                 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1139 
1140         if (assoclen) {
1141                 /*
1142                  * Currently it is assumed that iv is provided whenever assoc
1143                  * is.
1144                  */
1145                 BUG_ON(!iv);
1146 
1147                 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1148                 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1149                                assoc_chained);
1150                 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1151 
1152                 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1153                         assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1154         }
1155 
1156         if (!dst || dst == src) {
1157                 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1158                 src_nents = (src_nents == 1) ? 0 : src_nents;
1159                 dst_nents = dst ? src_nents : 0;
1160         } else { /* dst && dst != src*/
1161                 src_nents = sg_count(src, cryptlen + (encrypt ? 0 : authsize),
1162                                      &src_chained);
1163                 src_nents = (src_nents == 1) ? 0 : src_nents;
1164                 dst_nents = sg_count(dst, cryptlen + (encrypt ? authsize : 0),
1165                                      &dst_chained);
1166                 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1167         }
1168 
1169         /*
1170          * allocate space for base edesc plus the link tables,
1171          * allowing for two separate entries for ICV and generated ICV (+ 2),
1172          * and the ICV data itself
1173          */
1174         alloc_len = sizeof(struct talitos_edesc);
1175         if (assoc_nents || src_nents || dst_nents) {
1176                 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1177                           sizeof(struct talitos_ptr) + authsize;
1178                 alloc_len += dma_len;
1179         } else {
1180                 dma_len = 0;
1181                 alloc_len += icv_stashing ? authsize : 0;
1182         }
1183 
1184         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1185         if (!edesc) {
1186                 if (assoc_chained)
1187                         talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1188                 else if (assoclen)
1189                         dma_unmap_sg(dev, assoc,
1190                                      assoc_nents ? assoc_nents - 1 : 1,
1191                                      DMA_TO_DEVICE);
1192 
1193                 if (iv_dma)
1194                         dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1195 
1196                 dev_err(dev, "could not allocate edescriptor\n");
1197                 return ERR_PTR(-ENOMEM);
1198         }
1199 
1200         edesc->assoc_nents = assoc_nents;
1201         edesc->src_nents = src_nents;
1202         edesc->dst_nents = dst_nents;
1203         edesc->assoc_chained = assoc_chained;
1204         edesc->src_chained = src_chained;
1205         edesc->dst_chained = dst_chained;
1206         edesc->iv_dma = iv_dma;
1207         edesc->dma_len = dma_len;
1208         if (dma_len)
1209                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1210                                                      edesc->dma_len,
1211                                                      DMA_BIDIRECTIONAL);
1212 
1213         return edesc;
1214 }
1215 
1216 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1217                                               int icv_stashing, bool encrypt)
1218 {
1219         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1220         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1221         unsigned int ivsize = crypto_aead_ivsize(authenc);
1222 
1223         return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1224                                    iv, areq->assoclen, areq->cryptlen,
1225                                    ctx->authsize, ivsize, icv_stashing,
1226                                    areq->base.flags, encrypt);
1227 }
1228 
1229 static int aead_encrypt(struct aead_request *req)
1230 {
1231         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1232         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1233         struct talitos_edesc *edesc;
1234 
1235         /* allocate extended descriptor */
1236         edesc = aead_edesc_alloc(req, req->iv, 0, true);
1237         if (IS_ERR(edesc))
1238                 return PTR_ERR(edesc);
1239 
1240         /* set encrypt */
1241         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1242 
1243         return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1244 }
1245 
1246 static int aead_decrypt(struct aead_request *req)
1247 {
1248         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1249         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1250         unsigned int authsize = ctx->authsize;
1251         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1252         struct talitos_edesc *edesc;
1253         struct scatterlist *sg;
1254         void *icvdata;
1255 
1256         req->cryptlen -= authsize;
1257 
1258         /* allocate extended descriptor */
1259         edesc = aead_edesc_alloc(req, req->iv, 1, false);
1260         if (IS_ERR(edesc))
1261                 return PTR_ERR(edesc);
1262 
1263         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1264             ((!edesc->src_nents && !edesc->dst_nents) ||
1265              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1266 
1267                 /* decrypt and check the ICV */
1268                 edesc->desc.hdr = ctx->desc_hdr_template |
1269                                   DESC_HDR_DIR_INBOUND |
1270                                   DESC_HDR_MODE1_MDEU_CICV;
1271 
1272                 /* reset integrity check result bits */
1273                 edesc->desc.hdr_lo = 0;
1274 
1275                 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1276         }
1277 
1278         /* Have to check the ICV with software */
1279         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1280 
1281         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1282         if (edesc->dma_len)
1283                 icvdata = &edesc->link_tbl[edesc->src_nents +
1284                                            edesc->dst_nents + 2 +
1285                                            edesc->assoc_nents];
1286         else
1287                 icvdata = &edesc->link_tbl[0];
1288 
1289         sg = sg_last(req->src, edesc->src_nents ? : 1);
1290 
1291         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1292                ctx->authsize);
1293 
1294         return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1295 }
1296 
1297 static int aead_givencrypt(struct aead_givcrypt_request *req)
1298 {
1299         struct aead_request *areq = &req->areq;
1300         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1301         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1302         struct talitos_edesc *edesc;
1303 
1304         /* allocate extended descriptor */
1305         edesc = aead_edesc_alloc(areq, req->giv, 0, true);
1306         if (IS_ERR(edesc))
1307                 return PTR_ERR(edesc);
1308 
1309         /* set encrypt */
1310         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1311 
1312         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1313         /* avoid consecutive packets going out with same IV */
1314         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1315 
1316         return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1317 }
1318 
1319 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1320                              const u8 *key, unsigned int keylen)
1321 {
1322         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1323 
1324         memcpy(&ctx->key, key, keylen);
1325         ctx->keylen = keylen;
1326 
1327         return 0;
1328 }
1329 
1330 static void common_nonsnoop_unmap(struct device *dev,
1331                                   struct talitos_edesc *edesc,
1332                                   struct ablkcipher_request *areq)
1333 {
1334         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1335         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1336         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1337 
1338         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1339 
1340         if (edesc->dma_len)
1341                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1342                                  DMA_BIDIRECTIONAL);
1343 }
1344 
1345 static void ablkcipher_done(struct device *dev,
1346                             struct talitos_desc *desc, void *context,
1347                             int err)
1348 {
1349         struct ablkcipher_request *areq = context;
1350         struct talitos_edesc *edesc;
1351 
1352         edesc = container_of(desc, struct talitos_edesc, desc);
1353 
1354         common_nonsnoop_unmap(dev, edesc, areq);
1355 
1356         kfree(edesc);
1357 
1358         areq->base.complete(&areq->base, err);
1359 }
1360 
1361 static int common_nonsnoop(struct talitos_edesc *edesc,
1362                            struct ablkcipher_request *areq,
1363                            void (*callback) (struct device *dev,
1364                                              struct talitos_desc *desc,
1365                                              void *context, int error))
1366 {
1367         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1368         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1369         struct device *dev = ctx->dev;
1370         struct talitos_desc *desc = &edesc->desc;
1371         unsigned int cryptlen = areq->nbytes;
1372         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1373         int sg_count, ret;
1374 
1375         /* first DWORD empty */
1376         desc->ptr[0].len = 0;
1377         to_talitos_ptr(&desc->ptr[0], 0);
1378         desc->ptr[0].j_extent = 0;
1379 
1380         /* cipher iv */
1381         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1382         desc->ptr[1].len = cpu_to_be16(ivsize);
1383         desc->ptr[1].j_extent = 0;
1384 
1385         /* cipher key */
1386         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1387                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1388 
1389         /*
1390          * cipher in
1391          */
1392         desc->ptr[3].len = cpu_to_be16(cryptlen);
1393         desc->ptr[3].j_extent = 0;
1394 
1395         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1396                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1397                                                            : DMA_TO_DEVICE,
1398                                   edesc->src_chained);
1399 
1400         if (sg_count == 1) {
1401                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1402         } else {
1403                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1404                                           &edesc->link_tbl[0]);
1405                 if (sg_count > 1) {
1406                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1407                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1408                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1409                                                    edesc->dma_len,
1410                                                    DMA_BIDIRECTIONAL);
1411                 } else {
1412                         /* Only one segment now, so no link tbl needed */
1413                         to_talitos_ptr(&desc->ptr[3],
1414                                        sg_dma_address(areq->src));
1415                 }
1416         }
1417 
1418         /* cipher out */
1419         desc->ptr[4].len = cpu_to_be16(cryptlen);
1420         desc->ptr[4].j_extent = 0;
1421 
1422         if (areq->src != areq->dst)
1423                 sg_count = talitos_map_sg(dev, areq->dst,
1424                                           edesc->dst_nents ? : 1,
1425                                           DMA_FROM_DEVICE, edesc->dst_chained);
1426 
1427         if (sg_count == 1) {
1428                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1429         } else {
1430                 struct talitos_ptr *link_tbl_ptr =
1431                         &edesc->link_tbl[edesc->src_nents + 1];
1432 
1433                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1434                                               (edesc->src_nents + 1) *
1435                                               sizeof(struct talitos_ptr));
1436                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1437                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1438                                           link_tbl_ptr);
1439                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1440                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1441         }
1442 
1443         /* iv out */
1444         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1445                                DMA_FROM_DEVICE);
1446 
1447         /* last DWORD empty */
1448         desc->ptr[6].len = 0;
1449         to_talitos_ptr(&desc->ptr[6], 0);
1450         desc->ptr[6].j_extent = 0;
1451 
1452         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1453         if (ret != -EINPROGRESS) {
1454                 common_nonsnoop_unmap(dev, edesc, areq);
1455                 kfree(edesc);
1456         }
1457         return ret;
1458 }
1459 
1460 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1461                                                     areq, bool encrypt)
1462 {
1463         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1464         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1465         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1466 
1467         return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1468                                    areq->info, 0, areq->nbytes, 0, ivsize, 0,
1469                                    areq->base.flags, encrypt);
1470 }
1471 
1472 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1473 {
1474         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1475         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1476         struct talitos_edesc *edesc;
1477 
1478         /* allocate extended descriptor */
1479         edesc = ablkcipher_edesc_alloc(areq, true);
1480         if (IS_ERR(edesc))
1481                 return PTR_ERR(edesc);
1482 
1483         /* set encrypt */
1484         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1485 
1486         return common_nonsnoop(edesc, areq, ablkcipher_done);
1487 }
1488 
1489 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1490 {
1491         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1492         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1493         struct talitos_edesc *edesc;
1494 
1495         /* allocate extended descriptor */
1496         edesc = ablkcipher_edesc_alloc(areq, false);
1497         if (IS_ERR(edesc))
1498                 return PTR_ERR(edesc);
1499 
1500         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1501 
1502         return common_nonsnoop(edesc, areq, ablkcipher_done);
1503 }
1504 
1505 static void common_nonsnoop_hash_unmap(struct device *dev,
1506                                        struct talitos_edesc *edesc,
1507                                        struct ahash_request *areq)
1508 {
1509         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1510 
1511         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1512 
1513         /* When using hashctx-in, must unmap it. */
1514         if (edesc->desc.ptr[1].len)
1515                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1516                                          DMA_TO_DEVICE);
1517 
1518         if (edesc->desc.ptr[2].len)
1519                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1520                                          DMA_TO_DEVICE);
1521 
1522         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1523 
1524         if (edesc->dma_len)
1525                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1526                                  DMA_BIDIRECTIONAL);
1527 
1528 }
1529 
1530 static void ahash_done(struct device *dev,
1531                        struct talitos_desc *desc, void *context,
1532                        int err)
1533 {
1534         struct ahash_request *areq = context;
1535         struct talitos_edesc *edesc =
1536                  container_of(desc, struct talitos_edesc, desc);
1537         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1538 
1539         if (!req_ctx->last && req_ctx->to_hash_later) {
1540                 /* Position any partial block for next update/final/finup */
1541                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1542                 req_ctx->nbuf = req_ctx->to_hash_later;
1543         }
1544         common_nonsnoop_hash_unmap(dev, edesc, areq);
1545 
1546         kfree(edesc);
1547 
1548         areq->base.complete(&areq->base, err);
1549 }
1550 
1551 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1552                                 struct ahash_request *areq, unsigned int length,
1553                                 void (*callback) (struct device *dev,
1554                                                   struct talitos_desc *desc,
1555                                                   void *context, int error))
1556 {
1557         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1558         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1559         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1560         struct device *dev = ctx->dev;
1561         struct talitos_desc *desc = &edesc->desc;
1562         int sg_count, ret;
1563 
1564         /* first DWORD empty */
1565         desc->ptr[0] = zero_entry;
1566 
1567         /* hash context in */
1568         if (!req_ctx->first || req_ctx->swinit) {
1569                 map_single_talitos_ptr(dev, &desc->ptr[1],
1570                                        req_ctx->hw_context_size,
1571                                        (char *)req_ctx->hw_context, 0,
1572                                        DMA_TO_DEVICE);
1573                 req_ctx->swinit = 0;
1574         } else {
1575                 desc->ptr[1] = zero_entry;
1576                 /* Indicate next op is not the first. */
1577                 req_ctx->first = 0;
1578         }
1579 
1580         /* HMAC key */
1581         if (ctx->keylen)
1582                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1583                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1584         else
1585                 desc->ptr[2] = zero_entry;
1586 
1587         /*
1588          * data in
1589          */
1590         desc->ptr[3].len = cpu_to_be16(length);
1591         desc->ptr[3].j_extent = 0;
1592 
1593         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1594                                   edesc->src_nents ? : 1,
1595                                   DMA_TO_DEVICE, edesc->src_chained);
1596 
1597         if (sg_count == 1) {
1598                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1599         } else {
1600                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1601                                           &edesc->link_tbl[0]);
1602                 if (sg_count > 1) {
1603                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1604                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1605                         dma_sync_single_for_device(ctx->dev,
1606                                                    edesc->dma_link_tbl,
1607                                                    edesc->dma_len,
1608                                                    DMA_BIDIRECTIONAL);
1609                 } else {
1610                         /* Only one segment now, so no link tbl needed */
1611                         to_talitos_ptr(&desc->ptr[3],
1612                                        sg_dma_address(req_ctx->psrc));
1613                 }
1614         }
1615 
1616         /* fifth DWORD empty */
1617         desc->ptr[4] = zero_entry;
1618 
1619         /* hash/HMAC out -or- hash context out */
1620         if (req_ctx->last)
1621                 map_single_talitos_ptr(dev, &desc->ptr[5],
1622                                        crypto_ahash_digestsize(tfm),
1623                                        areq->result, 0, DMA_FROM_DEVICE);
1624         else
1625                 map_single_talitos_ptr(dev, &desc->ptr[5],
1626                                        req_ctx->hw_context_size,
1627                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1628 
1629         /* last DWORD empty */
1630         desc->ptr[6] = zero_entry;
1631 
1632         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1633         if (ret != -EINPROGRESS) {
1634                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1635                 kfree(edesc);
1636         }
1637         return ret;
1638 }
1639 
1640 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1641                                                unsigned int nbytes)
1642 {
1643         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1644         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1645         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1646 
1647         return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1648                                    nbytes, 0, 0, 0, areq->base.flags, false);
1649 }
1650 
1651 static int ahash_init(struct ahash_request *areq)
1652 {
1653         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1654         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1655 
1656         /* Initialize the context */
1657         req_ctx->nbuf = 0;
1658         req_ctx->first = 1; /* first indicates h/w must init its context */
1659         req_ctx->swinit = 0; /* assume h/w init of context */
1660         req_ctx->hw_context_size =
1661                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1662                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1663                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1664 
1665         return 0;
1666 }
1667 
1668 /*
1669  * on h/w without explicit sha224 support, we initialize h/w context
1670  * manually with sha224 constants, and tell it to run sha256.
1671  */
1672 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1673 {
1674         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1675 
1676         ahash_init(areq);
1677         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1678 
1679         req_ctx->hw_context[0] = SHA224_H0;
1680         req_ctx->hw_context[1] = SHA224_H1;
1681         req_ctx->hw_context[2] = SHA224_H2;
1682         req_ctx->hw_context[3] = SHA224_H3;
1683         req_ctx->hw_context[4] = SHA224_H4;
1684         req_ctx->hw_context[5] = SHA224_H5;
1685         req_ctx->hw_context[6] = SHA224_H6;
1686         req_ctx->hw_context[7] = SHA224_H7;
1687 
1688         /* init 64-bit count */
1689         req_ctx->hw_context[8] = 0;
1690         req_ctx->hw_context[9] = 0;
1691 
1692         return 0;
1693 }
1694 
1695 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1696 {
1697         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1698         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1699         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1700         struct talitos_edesc *edesc;
1701         unsigned int blocksize =
1702                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1703         unsigned int nbytes_to_hash;
1704         unsigned int to_hash_later;
1705         unsigned int nsg;
1706         bool chained;
1707 
1708         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1709                 /* Buffer up to one whole block */
1710                 sg_copy_to_buffer(areq->src,
1711                                   sg_count(areq->src, nbytes, &chained),
1712                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1713                 req_ctx->nbuf += nbytes;
1714                 return 0;
1715         }
1716 
1717         /* At least (blocksize + 1) bytes are available to hash */
1718         nbytes_to_hash = nbytes + req_ctx->nbuf;
1719         to_hash_later = nbytes_to_hash & (blocksize - 1);
1720 
1721         if (req_ctx->last)
1722                 to_hash_later = 0;
1723         else if (to_hash_later)
1724                 /* There is a partial block. Hash the full block(s) now */
1725                 nbytes_to_hash -= to_hash_later;
1726         else {
1727                 /* Keep one block buffered */
1728                 nbytes_to_hash -= blocksize;
1729                 to_hash_later = blocksize;
1730         }
1731 
1732         /* Chain in any previously buffered data */
1733         if (req_ctx->nbuf) {
1734                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1735                 sg_init_table(req_ctx->bufsl, nsg);
1736                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1737                 if (nsg > 1)
1738                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1739                 req_ctx->psrc = req_ctx->bufsl;
1740         } else
1741                 req_ctx->psrc = areq->src;
1742 
1743         if (to_hash_later) {
1744                 int nents = sg_count(areq->src, nbytes, &chained);
1745                 sg_pcopy_to_buffer(areq->src, nents,
1746                                       req_ctx->bufnext,
1747                                       to_hash_later,
1748                                       nbytes - to_hash_later);
1749         }
1750         req_ctx->to_hash_later = to_hash_later;
1751 
1752         /* Allocate extended descriptor */
1753         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1754         if (IS_ERR(edesc))
1755                 return PTR_ERR(edesc);
1756 
1757         edesc->desc.hdr = ctx->desc_hdr_template;
1758 
1759         /* On last one, request SEC to pad; otherwise continue */
1760         if (req_ctx->last)
1761                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1762         else
1763                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1764 
1765         /* request SEC to INIT hash. */
1766         if (req_ctx->first && !req_ctx->swinit)
1767                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1768 
1769         /* When the tfm context has a keylen, it's an HMAC.
1770          * A first or last (ie. not middle) descriptor must request HMAC.
1771          */
1772         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1773                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1774 
1775         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1776                                     ahash_done);
1777 }
1778 
1779 static int ahash_update(struct ahash_request *areq)
1780 {
1781         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1782 
1783         req_ctx->last = 0;
1784 
1785         return ahash_process_req(areq, areq->nbytes);
1786 }
1787 
1788 static int ahash_final(struct ahash_request *areq)
1789 {
1790         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1791 
1792         req_ctx->last = 1;
1793 
1794         return ahash_process_req(areq, 0);
1795 }
1796 
1797 static int ahash_finup(struct ahash_request *areq)
1798 {
1799         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1800 
1801         req_ctx->last = 1;
1802 
1803         return ahash_process_req(areq, areq->nbytes);
1804 }
1805 
1806 static int ahash_digest(struct ahash_request *areq)
1807 {
1808         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1809         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1810 
1811         ahash->init(areq);
1812         req_ctx->last = 1;
1813 
1814         return ahash_process_req(areq, areq->nbytes);
1815 }
1816 
1817 struct keyhash_result {
1818         struct completion completion;
1819         int err;
1820 };
1821 
1822 static void keyhash_complete(struct crypto_async_request *req, int err)
1823 {
1824         struct keyhash_result *res = req->data;
1825 
1826         if (err == -EINPROGRESS)
1827                 return;
1828 
1829         res->err = err;
1830         complete(&res->completion);
1831 }
1832 
1833 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1834                    u8 *hash)
1835 {
1836         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1837 
1838         struct scatterlist sg[1];
1839         struct ahash_request *req;
1840         struct keyhash_result hresult;
1841         int ret;
1842 
1843         init_completion(&hresult.completion);
1844 
1845         req = ahash_request_alloc(tfm, GFP_KERNEL);
1846         if (!req)
1847                 return -ENOMEM;
1848 
1849         /* Keep tfm keylen == 0 during hash of the long key */
1850         ctx->keylen = 0;
1851         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1852                                    keyhash_complete, &hresult);
1853 
1854         sg_init_one(&sg[0], key, keylen);
1855 
1856         ahash_request_set_crypt(req, sg, hash, keylen);
1857         ret = crypto_ahash_digest(req);
1858         switch (ret) {
1859         case 0:
1860                 break;
1861         case -EINPROGRESS:
1862         case -EBUSY:
1863                 ret = wait_for_completion_interruptible(
1864                         &hresult.completion);
1865                 if (!ret)
1866                         ret = hresult.err;
1867                 break;
1868         default:
1869                 break;
1870         }
1871         ahash_request_free(req);
1872 
1873         return ret;
1874 }
1875 
1876 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1877                         unsigned int keylen)
1878 {
1879         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1880         unsigned int blocksize =
1881                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1882         unsigned int digestsize = crypto_ahash_digestsize(tfm);
1883         unsigned int keysize = keylen;
1884         u8 hash[SHA512_DIGEST_SIZE];
1885         int ret;
1886 
1887         if (keylen <= blocksize)
1888                 memcpy(ctx->key, key, keysize);
1889         else {
1890                 /* Must get the hash of the long key */
1891                 ret = keyhash(tfm, key, keylen, hash);
1892 
1893                 if (ret) {
1894                         crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1895                         return -EINVAL;
1896                 }
1897 
1898                 keysize = digestsize;
1899                 memcpy(ctx->key, hash, digestsize);
1900         }
1901 
1902         ctx->keylen = keysize;
1903 
1904         return 0;
1905 }
1906 
1907 
1908 struct talitos_alg_template {
1909         u32 type;
1910         union {
1911                 struct crypto_alg crypto;
1912                 struct ahash_alg hash;
1913         } alg;
1914         __be32 desc_hdr_template;
1915 };
1916 
1917 static struct talitos_alg_template driver_algs[] = {
1918         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1919         {       .type = CRYPTO_ALG_TYPE_AEAD,
1920                 .alg.crypto = {
1921                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1922                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1923                         .cra_blocksize = AES_BLOCK_SIZE,
1924                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1925                         .cra_aead = {
1926                                 .ivsize = AES_BLOCK_SIZE,
1927                                 .maxauthsize = SHA1_DIGEST_SIZE,
1928                         }
1929                 },
1930                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1931                                      DESC_HDR_SEL0_AESU |
1932                                      DESC_HDR_MODE0_AESU_CBC |
1933                                      DESC_HDR_SEL1_MDEUA |
1934                                      DESC_HDR_MODE1_MDEU_INIT |
1935                                      DESC_HDR_MODE1_MDEU_PAD |
1936                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1937         },
1938         {       .type = CRYPTO_ALG_TYPE_AEAD,
1939                 .alg.crypto = {
1940                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1941                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1942                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1943                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1944                         .cra_aead = {
1945                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1946                                 .maxauthsize = SHA1_DIGEST_SIZE,
1947                         }
1948                 },
1949                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1950                                      DESC_HDR_SEL0_DEU |
1951                                      DESC_HDR_MODE0_DEU_CBC |
1952                                      DESC_HDR_MODE0_DEU_3DES |
1953                                      DESC_HDR_SEL1_MDEUA |
1954                                      DESC_HDR_MODE1_MDEU_INIT |
1955                                      DESC_HDR_MODE1_MDEU_PAD |
1956                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1957         },
1958         {       .type = CRYPTO_ALG_TYPE_AEAD,
1959                 .alg.crypto = {
1960                         .cra_name = "authenc(hmac(sha224),cbc(aes))",
1961                         .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1962                         .cra_blocksize = AES_BLOCK_SIZE,
1963                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1964                         .cra_aead = {
1965                                 .ivsize = AES_BLOCK_SIZE,
1966                                 .maxauthsize = SHA224_DIGEST_SIZE,
1967                         }
1968                 },
1969                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1970                                      DESC_HDR_SEL0_AESU |
1971                                      DESC_HDR_MODE0_AESU_CBC |
1972                                      DESC_HDR_SEL1_MDEUA |
1973                                      DESC_HDR_MODE1_MDEU_INIT |
1974                                      DESC_HDR_MODE1_MDEU_PAD |
1975                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1976         },
1977         {       .type = CRYPTO_ALG_TYPE_AEAD,
1978                 .alg.crypto = {
1979                         .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1980                         .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1981                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1982                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1983                         .cra_aead = {
1984                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1985                                 .maxauthsize = SHA224_DIGEST_SIZE,
1986                         }
1987                 },
1988                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1989                                      DESC_HDR_SEL0_DEU |
1990                                      DESC_HDR_MODE0_DEU_CBC |
1991                                      DESC_HDR_MODE0_DEU_3DES |
1992                                      DESC_HDR_SEL1_MDEUA |
1993                                      DESC_HDR_MODE1_MDEU_INIT |
1994                                      DESC_HDR_MODE1_MDEU_PAD |
1995                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1996         },
1997         {       .type = CRYPTO_ALG_TYPE_AEAD,
1998                 .alg.crypto = {
1999                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
2000                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
2001                         .cra_blocksize = AES_BLOCK_SIZE,
2002                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2003                         .cra_aead = {
2004                                 .ivsize = AES_BLOCK_SIZE,
2005                                 .maxauthsize = SHA256_DIGEST_SIZE,
2006                         }
2007                 },
2008                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2009                                      DESC_HDR_SEL0_AESU |
2010                                      DESC_HDR_MODE0_AESU_CBC |
2011                                      DESC_HDR_SEL1_MDEUA |
2012                                      DESC_HDR_MODE1_MDEU_INIT |
2013                                      DESC_HDR_MODE1_MDEU_PAD |
2014                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2015         },
2016         {       .type = CRYPTO_ALG_TYPE_AEAD,
2017                 .alg.crypto = {
2018                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2019                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2020                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2021                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2022                         .cra_aead = {
2023                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2024                                 .maxauthsize = SHA256_DIGEST_SIZE,
2025                         }
2026                 },
2027                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2028                                      DESC_HDR_SEL0_DEU |
2029                                      DESC_HDR_MODE0_DEU_CBC |
2030                                      DESC_HDR_MODE0_DEU_3DES |
2031                                      DESC_HDR_SEL1_MDEUA |
2032                                      DESC_HDR_MODE1_MDEU_INIT |
2033                                      DESC_HDR_MODE1_MDEU_PAD |
2034                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2035         },
2036         {       .type = CRYPTO_ALG_TYPE_AEAD,
2037                 .alg.crypto = {
2038                         .cra_name = "authenc(hmac(sha384),cbc(aes))",
2039                         .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2040                         .cra_blocksize = AES_BLOCK_SIZE,
2041                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2042                         .cra_aead = {
2043                                 .ivsize = AES_BLOCK_SIZE,
2044                                 .maxauthsize = SHA384_DIGEST_SIZE,
2045                         }
2046                 },
2047                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2048                                      DESC_HDR_SEL0_AESU |
2049                                      DESC_HDR_MODE0_AESU_CBC |
2050                                      DESC_HDR_SEL1_MDEUB |
2051                                      DESC_HDR_MODE1_MDEU_INIT |
2052                                      DESC_HDR_MODE1_MDEU_PAD |
2053                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2054         },
2055         {       .type = CRYPTO_ALG_TYPE_AEAD,
2056                 .alg.crypto = {
2057                         .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2058                         .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2059                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2060                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2061                         .cra_aead = {
2062                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2063                                 .maxauthsize = SHA384_DIGEST_SIZE,
2064                         }
2065                 },
2066                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2067                                      DESC_HDR_SEL0_DEU |
2068                                      DESC_HDR_MODE0_DEU_CBC |
2069                                      DESC_HDR_MODE0_DEU_3DES |
2070                                      DESC_HDR_SEL1_MDEUB |
2071                                      DESC_HDR_MODE1_MDEU_INIT |
2072                                      DESC_HDR_MODE1_MDEU_PAD |
2073                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2074         },
2075         {       .type = CRYPTO_ALG_TYPE_AEAD,
2076                 .alg.crypto = {
2077                         .cra_name = "authenc(hmac(sha512),cbc(aes))",
2078                         .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2079                         .cra_blocksize = AES_BLOCK_SIZE,
2080                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2081                         .cra_aead = {
2082                                 .ivsize = AES_BLOCK_SIZE,
2083                                 .maxauthsize = SHA512_DIGEST_SIZE,
2084                         }
2085                 },
2086                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2087                                      DESC_HDR_SEL0_AESU |
2088                                      DESC_HDR_MODE0_AESU_CBC |
2089                                      DESC_HDR_SEL1_MDEUB |
2090                                      DESC_HDR_MODE1_MDEU_INIT |
2091                                      DESC_HDR_MODE1_MDEU_PAD |
2092                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2093         },
2094         {       .type = CRYPTO_ALG_TYPE_AEAD,
2095                 .alg.crypto = {
2096                         .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2097                         .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2098                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2099                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2100                         .cra_aead = {
2101                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2102                                 .maxauthsize = SHA512_DIGEST_SIZE,
2103                         }
2104                 },
2105                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2106                                      DESC_HDR_SEL0_DEU |
2107                                      DESC_HDR_MODE0_DEU_CBC |
2108                                      DESC_HDR_MODE0_DEU_3DES |
2109                                      DESC_HDR_SEL1_MDEUB |
2110                                      DESC_HDR_MODE1_MDEU_INIT |
2111                                      DESC_HDR_MODE1_MDEU_PAD |
2112                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2113         },
2114         {       .type = CRYPTO_ALG_TYPE_AEAD,
2115                 .alg.crypto = {
2116                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2117                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2118                         .cra_blocksize = AES_BLOCK_SIZE,
2119                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2120                         .cra_aead = {
2121                                 .ivsize = AES_BLOCK_SIZE,
2122                                 .maxauthsize = MD5_DIGEST_SIZE,
2123                         }
2124                 },
2125                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2126                                      DESC_HDR_SEL0_AESU |
2127                                      DESC_HDR_MODE0_AESU_CBC |
2128                                      DESC_HDR_SEL1_MDEUA |
2129                                      DESC_HDR_MODE1_MDEU_INIT |
2130                                      DESC_HDR_MODE1_MDEU_PAD |
2131                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2132         },
2133         {       .type = CRYPTO_ALG_TYPE_AEAD,
2134                 .alg.crypto = {
2135                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2136                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2137                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2138                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2139                         .cra_aead = {
2140                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2141                                 .maxauthsize = MD5_DIGEST_SIZE,
2142                         }
2143                 },
2144                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2145                                      DESC_HDR_SEL0_DEU |
2146                                      DESC_HDR_MODE0_DEU_CBC |
2147                                      DESC_HDR_MODE0_DEU_3DES |
2148                                      DESC_HDR_SEL1_MDEUA |
2149                                      DESC_HDR_MODE1_MDEU_INIT |
2150                                      DESC_HDR_MODE1_MDEU_PAD |
2151                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2152         },
2153         /* ABLKCIPHER algorithms. */
2154         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2155                 .alg.crypto = {
2156                         .cra_name = "cbc(aes)",
2157                         .cra_driver_name = "cbc-aes-talitos",
2158                         .cra_blocksize = AES_BLOCK_SIZE,
2159                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2160                                      CRYPTO_ALG_ASYNC,
2161                         .cra_ablkcipher = {
2162                                 .min_keysize = AES_MIN_KEY_SIZE,
2163                                 .max_keysize = AES_MAX_KEY_SIZE,
2164                                 .ivsize = AES_BLOCK_SIZE,
2165                         }
2166                 },
2167                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2168                                      DESC_HDR_SEL0_AESU |
2169                                      DESC_HDR_MODE0_AESU_CBC,
2170         },
2171         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2172                 .alg.crypto = {
2173                         .cra_name = "cbc(des3_ede)",
2174                         .cra_driver_name = "cbc-3des-talitos",
2175                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2176                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2177                                      CRYPTO_ALG_ASYNC,
2178                         .cra_ablkcipher = {
2179                                 .min_keysize = DES3_EDE_KEY_SIZE,
2180                                 .max_keysize = DES3_EDE_KEY_SIZE,
2181                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2182                         }
2183                 },
2184                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2185                                      DESC_HDR_SEL0_DEU |
2186                                      DESC_HDR_MODE0_DEU_CBC |
2187                                      DESC_HDR_MODE0_DEU_3DES,
2188         },
2189         /* AHASH algorithms. */
2190         {       .type = CRYPTO_ALG_TYPE_AHASH,
2191                 .alg.hash = {
2192                         .halg.digestsize = MD5_DIGEST_SIZE,
2193                         .halg.base = {
2194                                 .cra_name = "md5",
2195                                 .cra_driver_name = "md5-talitos",
2196                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
2197                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2198                                              CRYPTO_ALG_ASYNC,
2199                         }
2200                 },
2201                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2202                                      DESC_HDR_SEL0_MDEUA |
2203                                      DESC_HDR_MODE0_MDEU_MD5,
2204         },
2205         {       .type = CRYPTO_ALG_TYPE_AHASH,
2206                 .alg.hash = {
2207                         .halg.digestsize = SHA1_DIGEST_SIZE,
2208                         .halg.base = {
2209                                 .cra_name = "sha1",
2210                                 .cra_driver_name = "sha1-talitos",
2211                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2212                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2213                                              CRYPTO_ALG_ASYNC,
2214                         }
2215                 },
2216                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2217                                      DESC_HDR_SEL0_MDEUA |
2218                                      DESC_HDR_MODE0_MDEU_SHA1,
2219         },
2220         {       .type = CRYPTO_ALG_TYPE_AHASH,
2221                 .alg.hash = {
2222                         .halg.digestsize = SHA224_DIGEST_SIZE,
2223                         .halg.base = {
2224                                 .cra_name = "sha224",
2225                                 .cra_driver_name = "sha224-talitos",
2226                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2227                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2228                                              CRYPTO_ALG_ASYNC,
2229                         }
2230                 },
2231                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2232                                      DESC_HDR_SEL0_MDEUA |
2233                                      DESC_HDR_MODE0_MDEU_SHA224,
2234         },
2235         {       .type = CRYPTO_ALG_TYPE_AHASH,
2236                 .alg.hash = {
2237                         .halg.digestsize = SHA256_DIGEST_SIZE,
2238                         .halg.base = {
2239                                 .cra_name = "sha256",
2240                                 .cra_driver_name = "sha256-talitos",
2241                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2242                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2243                                              CRYPTO_ALG_ASYNC,
2244                         }
2245                 },
2246                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2247                                      DESC_HDR_SEL0_MDEUA |
2248                                      DESC_HDR_MODE0_MDEU_SHA256,
2249         },
2250         {       .type = CRYPTO_ALG_TYPE_AHASH,
2251                 .alg.hash = {
2252                         .halg.digestsize = SHA384_DIGEST_SIZE,
2253                         .halg.base = {
2254                                 .cra_name = "sha384",
2255                                 .cra_driver_name = "sha384-talitos",
2256                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2257                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2258                                              CRYPTO_ALG_ASYNC,
2259                         }
2260                 },
2261                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2262                                      DESC_HDR_SEL0_MDEUB |
2263                                      DESC_HDR_MODE0_MDEUB_SHA384,
2264         },
2265         {       .type = CRYPTO_ALG_TYPE_AHASH,
2266                 .alg.hash = {
2267                         .halg.digestsize = SHA512_DIGEST_SIZE,
2268                         .halg.base = {
2269                                 .cra_name = "sha512",
2270                                 .cra_driver_name = "sha512-talitos",
2271                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2272                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2273                                              CRYPTO_ALG_ASYNC,
2274                         }
2275                 },
2276                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2277                                      DESC_HDR_SEL0_MDEUB |
2278                                      DESC_HDR_MODE0_MDEUB_SHA512,
2279         },
2280         {       .type = CRYPTO_ALG_TYPE_AHASH,
2281                 .alg.hash = {
2282                         .halg.digestsize = MD5_DIGEST_SIZE,
2283                         .halg.base = {
2284                                 .cra_name = "hmac(md5)",
2285                                 .cra_driver_name = "hmac-md5-talitos",
2286                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
2287                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2288                                              CRYPTO_ALG_ASYNC,
2289                         }
2290                 },
2291                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2292                                      DESC_HDR_SEL0_MDEUA |
2293                                      DESC_HDR_MODE0_MDEU_MD5,
2294         },
2295         {       .type = CRYPTO_ALG_TYPE_AHASH,
2296                 .alg.hash = {
2297                         .halg.digestsize = SHA1_DIGEST_SIZE,
2298                         .halg.base = {
2299                                 .cra_name = "hmac(sha1)",
2300                                 .cra_driver_name = "hmac-sha1-talitos",
2301                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2302                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2303                                              CRYPTO_ALG_ASYNC,
2304                         }
2305                 },
2306                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2307                                      DESC_HDR_SEL0_MDEUA |
2308                                      DESC_HDR_MODE0_MDEU_SHA1,
2309         },
2310         {       .type = CRYPTO_ALG_TYPE_AHASH,
2311                 .alg.hash = {
2312                         .halg.digestsize = SHA224_DIGEST_SIZE,
2313                         .halg.base = {
2314                                 .cra_name = "hmac(sha224)",
2315                                 .cra_driver_name = "hmac-sha224-talitos",
2316                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2317                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2318                                              CRYPTO_ALG_ASYNC,
2319                         }
2320                 },
2321                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2322                                      DESC_HDR_SEL0_MDEUA |
2323                                      DESC_HDR_MODE0_MDEU_SHA224,
2324         },
2325         {       .type = CRYPTO_ALG_TYPE_AHASH,
2326                 .alg.hash = {
2327                         .halg.digestsize = SHA256_DIGEST_SIZE,
2328                         .halg.base = {
2329                                 .cra_name = "hmac(sha256)",
2330                                 .cra_driver_name = "hmac-sha256-talitos",
2331                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2332                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2333                                              CRYPTO_ALG_ASYNC,
2334                         }
2335                 },
2336                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2337                                      DESC_HDR_SEL0_MDEUA |
2338                                      DESC_HDR_MODE0_MDEU_SHA256,
2339         },
2340         {       .type = CRYPTO_ALG_TYPE_AHASH,
2341                 .alg.hash = {
2342                         .halg.digestsize = SHA384_DIGEST_SIZE,
2343                         .halg.base = {
2344                                 .cra_name = "hmac(sha384)",
2345                                 .cra_driver_name = "hmac-sha384-talitos",
2346                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2347                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2348                                              CRYPTO_ALG_ASYNC,
2349                         }
2350                 },
2351                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2352                                      DESC_HDR_SEL0_MDEUB |
2353                                      DESC_HDR_MODE0_MDEUB_SHA384,
2354         },
2355         {       .type = CRYPTO_ALG_TYPE_AHASH,
2356                 .alg.hash = {
2357                         .halg.digestsize = SHA512_DIGEST_SIZE,
2358                         .halg.base = {
2359                                 .cra_name = "hmac(sha512)",
2360                                 .cra_driver_name = "hmac-sha512-talitos",
2361                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2362                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2363                                              CRYPTO_ALG_ASYNC,
2364                         }
2365                 },
2366                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2367                                      DESC_HDR_SEL0_MDEUB |
2368                                      DESC_HDR_MODE0_MDEUB_SHA512,
2369         }
2370 };
2371 
2372 struct talitos_crypto_alg {
2373         struct list_head entry;
2374         struct device *dev;
2375         struct talitos_alg_template algt;
2376 };
2377 
2378 static int talitos_cra_init(struct crypto_tfm *tfm)
2379 {
2380         struct crypto_alg *alg = tfm->__crt_alg;
2381         struct talitos_crypto_alg *talitos_alg;
2382         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2383         struct talitos_private *priv;
2384 
2385         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2386                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2387                                            struct talitos_crypto_alg,
2388                                            algt.alg.hash);
2389         else
2390                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2391                                            algt.alg.crypto);
2392 
2393         /* update context with ptr to dev */
2394         ctx->dev = talitos_alg->dev;
2395 
2396         /* assign SEC channel to tfm in round-robin fashion */
2397         priv = dev_get_drvdata(ctx->dev);
2398         ctx->ch = atomic_inc_return(&priv->last_chan) &
2399                   (priv->num_channels - 1);
2400 
2401         /* copy descriptor header template value */
2402         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2403 
2404         /* select done notification */
2405         ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2406 
2407         return 0;
2408 }
2409 
2410 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2411 {
2412         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2413 
2414         talitos_cra_init(tfm);
2415 
2416         /* random first IV */
2417         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2418 
2419         return 0;
2420 }
2421 
2422 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2423 {
2424         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2425 
2426         talitos_cra_init(tfm);
2427 
2428         ctx->keylen = 0;
2429         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2430                                  sizeof(struct talitos_ahash_req_ctx));
2431 
2432         return 0;
2433 }
2434 
2435 /*
2436  * given the alg's descriptor header template, determine whether descriptor
2437  * type and primary/secondary execution units required match the hw
2438  * capabilities description provided in the device tree node.
2439  */
2440 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2441 {
2442         struct talitos_private *priv = dev_get_drvdata(dev);
2443         int ret;
2444 
2445         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2446               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2447 
2448         if (SECONDARY_EU(desc_hdr_template))
2449                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2450                               & priv->exec_units);
2451 
2452         return ret;
2453 }
2454 
2455 static int talitos_remove(struct platform_device *ofdev)
2456 {
2457         struct device *dev = &ofdev->dev;
2458         struct talitos_private *priv = dev_get_drvdata(dev);
2459         struct talitos_crypto_alg *t_alg, *n;
2460         int i;
2461 
2462         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2463                 switch (t_alg->algt.type) {
2464                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2465                 case CRYPTO_ALG_TYPE_AEAD:
2466                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2467                         break;
2468                 case CRYPTO_ALG_TYPE_AHASH:
2469                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2470                         break;
2471                 }
2472                 list_del(&t_alg->entry);
2473                 kfree(t_alg);
2474         }
2475 
2476         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2477                 talitos_unregister_rng(dev);
2478 
2479         for (i = 0; i < priv->num_channels; i++)
2480                 kfree(priv->chan[i].fifo);
2481 
2482         kfree(priv->chan);
2483 
2484         for (i = 0; i < 2; i++)
2485                 if (priv->irq[i]) {
2486                         free_irq(priv->irq[i], dev);
2487                         irq_dispose_mapping(priv->irq[i]);
2488                 }
2489 
2490         tasklet_kill(&priv->done_task[0]);
2491         if (priv->irq[1])
2492                 tasklet_kill(&priv->done_task[1]);
2493 
2494         iounmap(priv->reg);
2495 
2496         kfree(priv);
2497 
2498         return 0;
2499 }
2500 
2501 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2502                                                     struct talitos_alg_template
2503                                                            *template)
2504 {
2505         struct talitos_private *priv = dev_get_drvdata(dev);
2506         struct talitos_crypto_alg *t_alg;
2507         struct crypto_alg *alg;
2508 
2509         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2510         if (!t_alg)
2511                 return ERR_PTR(-ENOMEM);
2512 
2513         t_alg->algt = *template;
2514 
2515         switch (t_alg->algt.type) {
2516         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2517                 alg = &t_alg->algt.alg.crypto;
2518                 alg->cra_init = talitos_cra_init;
2519                 alg->cra_type = &crypto_ablkcipher_type;
2520                 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2521                 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2522                 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2523                 alg->cra_ablkcipher.geniv = "eseqiv";
2524                 break;
2525         case CRYPTO_ALG_TYPE_AEAD:
2526                 alg = &t_alg->algt.alg.crypto;
2527                 alg->cra_init = talitos_cra_init_aead;
2528                 alg->cra_type = &crypto_aead_type;
2529                 alg->cra_aead.setkey = aead_setkey;
2530                 alg->cra_aead.setauthsize = aead_setauthsize;
2531                 alg->cra_aead.encrypt = aead_encrypt;
2532                 alg->cra_aead.decrypt = aead_decrypt;
2533                 alg->cra_aead.givencrypt = aead_givencrypt;
2534                 alg->cra_aead.geniv = "<built-in>";
2535                 break;
2536         case CRYPTO_ALG_TYPE_AHASH:
2537                 alg = &t_alg->algt.alg.hash.halg.base;
2538                 alg->cra_init = talitos_cra_init_ahash;
2539                 alg->cra_type = &crypto_ahash_type;
2540                 t_alg->algt.alg.hash.init = ahash_init;
2541                 t_alg->algt.alg.hash.update = ahash_update;
2542                 t_alg->algt.alg.hash.final = ahash_final;
2543                 t_alg->algt.alg.hash.finup = ahash_finup;
2544                 t_alg->algt.alg.hash.digest = ahash_digest;
2545                 t_alg->algt.alg.hash.setkey = ahash_setkey;
2546 
2547                 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2548                     !strncmp(alg->cra_name, "hmac", 4)) {
2549                         kfree(t_alg);
2550                         return ERR_PTR(-ENOTSUPP);
2551                 }
2552                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2553                     (!strcmp(alg->cra_name, "sha224") ||
2554                      !strcmp(alg->cra_name, "hmac(sha224)"))) {
2555                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2556                         t_alg->algt.desc_hdr_template =
2557                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2558                                         DESC_HDR_SEL0_MDEUA |
2559                                         DESC_HDR_MODE0_MDEU_SHA256;
2560                 }
2561                 break;
2562         default:
2563                 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2564                 return ERR_PTR(-EINVAL);
2565         }
2566 
2567         alg->cra_module = THIS_MODULE;
2568         alg->cra_priority = TALITOS_CRA_PRIORITY;
2569         alg->cra_alignmask = 0;
2570         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2571         alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2572 
2573         t_alg->dev = dev;
2574 
2575         return t_alg;
2576 }
2577 
2578 static int talitos_probe_irq(struct platform_device *ofdev)
2579 {
2580         struct device *dev = &ofdev->dev;
2581         struct device_node *np = ofdev->dev.of_node;
2582         struct talitos_private *priv = dev_get_drvdata(dev);
2583         int err;
2584 
2585         priv->irq[0] = irq_of_parse_and_map(np, 0);
2586         if (!priv->irq[0]) {
2587                 dev_err(dev, "failed to map irq\n");
2588                 return -EINVAL;
2589         }
2590 
2591         priv->irq[1] = irq_of_parse_and_map(np, 1);
2592 
2593         /* get the primary irq line */
2594         if (!priv->irq[1]) {
2595                 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2596                                   dev_driver_string(dev), dev);
2597                 goto primary_out;
2598         }
2599 
2600         err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2601                           dev_driver_string(dev), dev);
2602         if (err)
2603                 goto primary_out;
2604 
2605         /* get the secondary irq line */
2606         err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2607                           dev_driver_string(dev), dev);
2608         if (err) {
2609                 dev_err(dev, "failed to request secondary irq\n");
2610                 irq_dispose_mapping(priv->irq[1]);
2611                 priv->irq[1] = 0;
2612         }
2613 
2614         return err;
2615 
2616 primary_out:
2617         if (err) {
2618                 dev_err(dev, "failed to request primary irq\n");
2619                 irq_dispose_mapping(priv->irq[0]);
2620                 priv->irq[0] = 0;
2621         }
2622 
2623         return err;
2624 }
2625 
2626 static int talitos_probe(struct platform_device *ofdev)
2627 {
2628         struct device *dev = &ofdev->dev;
2629         struct device_node *np = ofdev->dev.of_node;
2630         struct talitos_private *priv;
2631         const unsigned int *prop;
2632         int i, err;
2633 
2634         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2635         if (!priv)
2636                 return -ENOMEM;
2637 
2638         INIT_LIST_HEAD(&priv->alg_list);
2639 
2640         dev_set_drvdata(dev, priv);
2641 
2642         priv->ofdev = ofdev;
2643 
2644         spin_lock_init(&priv->reg_lock);
2645 
2646         err = talitos_probe_irq(ofdev);
2647         if (err)
2648                 goto err_out;
2649 
2650         if (!priv->irq[1]) {
2651                 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2652                              (unsigned long)dev);
2653         } else {
2654                 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2655                              (unsigned long)dev);
2656                 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2657                              (unsigned long)dev);
2658         }
2659 
2660         priv->reg = of_iomap(np, 0);
2661         if (!priv->reg) {
2662                 dev_err(dev, "failed to of_iomap\n");
2663                 err = -ENOMEM;
2664                 goto err_out;
2665         }
2666 
2667         /* get SEC version capabilities from device tree */
2668         prop = of_get_property(np, "fsl,num-channels", NULL);
2669         if (prop)
2670                 priv->num_channels = *prop;
2671 
2672         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2673         if (prop)
2674                 priv->chfifo_len = *prop;
2675 
2676         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2677         if (prop)
2678                 priv->exec_units = *prop;
2679 
2680         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2681         if (prop)
2682                 priv->desc_types = *prop;
2683 
2684         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2685             !priv->exec_units || !priv->desc_types) {
2686                 dev_err(dev, "invalid property data in device tree node\n");
2687                 err = -EINVAL;
2688                 goto err_out;
2689         }
2690 
2691         if (of_device_is_compatible(np, "fsl,sec3.0"))
2692                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2693 
2694         if (of_device_is_compatible(np, "fsl,sec2.1"))
2695                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2696                                   TALITOS_FTR_SHA224_HWINIT |
2697                                   TALITOS_FTR_HMAC_OK;
2698 
2699         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2700                              priv->num_channels, GFP_KERNEL);
2701         if (!priv->chan) {
2702                 dev_err(dev, "failed to allocate channel management space\n");
2703                 err = -ENOMEM;
2704                 goto err_out;
2705         }
2706 
2707         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2708 
2709         for (i = 0; i < priv->num_channels; i++) {
2710                 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2711                 if (!priv->irq[1] || !(i & 1))
2712                         priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2713 
2714                 spin_lock_init(&priv->chan[i].head_lock);
2715                 spin_lock_init(&priv->chan[i].tail_lock);
2716 
2717                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2718                                              priv->fifo_len, GFP_KERNEL);
2719                 if (!priv->chan[i].fifo) {
2720                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2721                         err = -ENOMEM;
2722                         goto err_out;
2723                 }
2724 
2725                 atomic_set(&priv->chan[i].submit_count,
2726                            -(priv->chfifo_len - 1));
2727         }
2728 
2729         dma_set_mask(dev, DMA_BIT_MASK(36));
2730 
2731         /* reset and initialize the h/w */
2732         err = init_device(dev);
2733         if (err) {
2734                 dev_err(dev, "failed to initialize device\n");
2735                 goto err_out;
2736         }
2737 
2738         /* register the RNG, if available */
2739         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2740                 err = talitos_register_rng(dev);
2741                 if (err) {
2742                         dev_err(dev, "failed to register hwrng: %d\n", err);
2743                         goto err_out;
2744                 } else
2745                         dev_info(dev, "hwrng\n");
2746         }
2747 
2748         /* register crypto algorithms the device supports */
2749         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2750                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2751                         struct talitos_crypto_alg *t_alg;
2752                         char *name = NULL;
2753 
2754                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2755                         if (IS_ERR(t_alg)) {
2756                                 err = PTR_ERR(t_alg);
2757                                 if (err == -ENOTSUPP)
2758                                         continue;
2759                                 goto err_out;
2760                         }
2761 
2762                         switch (t_alg->algt.type) {
2763                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2764                         case CRYPTO_ALG_TYPE_AEAD:
2765                                 err = crypto_register_alg(
2766                                                 &t_alg->algt.alg.crypto);
2767                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2768                                 break;
2769                         case CRYPTO_ALG_TYPE_AHASH:
2770                                 err = crypto_register_ahash(
2771                                                 &t_alg->algt.alg.hash);
2772                                 name =
2773                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2774                                 break;
2775                         }
2776                         if (err) {
2777                                 dev_err(dev, "%s alg registration failed\n",
2778                                         name);
2779                                 kfree(t_alg);
2780                         } else
2781                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2782                 }
2783         }
2784         if (!list_empty(&priv->alg_list))
2785                 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2786                          (char *)of_get_property(np, "compatible", NULL));
2787 
2788         return 0;
2789 
2790 err_out:
2791         talitos_remove(ofdev);
2792 
2793         return err;
2794 }
2795 
2796 static const struct of_device_id talitos_match[] = {
2797         {
2798                 .compatible = "fsl,sec2.0",
2799         },
2800         {},
2801 };
2802 MODULE_DEVICE_TABLE(of, talitos_match);
2803 
2804 static struct platform_driver talitos_driver = {
2805         .driver = {
2806                 .name = "talitos",
2807                 .of_match_table = talitos_match,
2808         },
2809         .probe = talitos_probe,
2810         .remove = talitos_remove,
2811 };
2812 
2813 module_platform_driver(talitos_driver);
2814 
2815 MODULE_LICENSE("GPL");
2816 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2817 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
2818 

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