Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/crypto/omap-aes.c

  1 /*
  2  * Cryptographic API.
  3  *
  4  * Support for OMAP AES HW acceleration.
  5  *
  6  * Copyright (c) 2010 Nokia Corporation
  7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
  8  * Copyright (c) 2011 Texas Instruments Incorporated
  9  *
 10  * This program is free software; you can redistribute it and/or modify
 11  * it under the terms of the GNU General Public License version 2 as published
 12  * by the Free Software Foundation.
 13  *
 14  */
 15 
 16 #define pr_fmt(fmt) "%20s: " fmt, __func__
 17 #define prn(num) pr_debug(#num "=%d\n", num)
 18 #define prx(num) pr_debug(#num "=%x\n", num)
 19 
 20 #include <linux/err.h>
 21 #include <linux/module.h>
 22 #include <linux/init.h>
 23 #include <linux/errno.h>
 24 #include <linux/kernel.h>
 25 #include <linux/platform_device.h>
 26 #include <linux/scatterlist.h>
 27 #include <linux/dma-mapping.h>
 28 #include <linux/dmaengine.h>
 29 #include <linux/omap-dma.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/of.h>
 32 #include <linux/of_device.h>
 33 #include <linux/of_address.h>
 34 #include <linux/io.h>
 35 #include <linux/crypto.h>
 36 #include <linux/interrupt.h>
 37 #include <crypto/scatterwalk.h>
 38 #include <crypto/aes.h>
 39 
 40 #define DST_MAXBURST                    4
 41 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
 42 
 43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
 44 
 45 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
 46    number. For example 7:0 */
 47 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
 48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
 49 
 50 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
 51                                                 ((x ^ 0x01) * 0x04))
 52 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
 53 
 54 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
 55 #define AES_REG_CTRL_CTR_WIDTH_MASK     GENMASK(8, 7)
 56 #define AES_REG_CTRL_CTR_WIDTH_32       0
 57 #define AES_REG_CTRL_CTR_WIDTH_64       BIT(7)
 58 #define AES_REG_CTRL_CTR_WIDTH_96       BIT(8)
 59 #define AES_REG_CTRL_CTR_WIDTH_128      GENMASK(8, 7)
 60 #define AES_REG_CTRL_CTR                BIT(6)
 61 #define AES_REG_CTRL_CBC                BIT(5)
 62 #define AES_REG_CTRL_KEY_SIZE           GENMASK(4, 3)
 63 #define AES_REG_CTRL_DIRECTION          BIT(2)
 64 #define AES_REG_CTRL_INPUT_READY        BIT(1)
 65 #define AES_REG_CTRL_OUTPUT_READY       BIT(0)
 66 #define AES_REG_CTRL_MASK               GENMASK(24, 2)
 67 
 68 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
 69 
 70 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
 71 
 72 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
 73 #define AES_REG_MASK_SIDLE              BIT(6)
 74 #define AES_REG_MASK_START              BIT(5)
 75 #define AES_REG_MASK_DMA_OUT_EN         BIT(3)
 76 #define AES_REG_MASK_DMA_IN_EN          BIT(2)
 77 #define AES_REG_MASK_SOFTRESET          BIT(1)
 78 #define AES_REG_AUTOIDLE                BIT(0)
 79 
 80 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
 81 
 82 #define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
 83 #define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
 84 #define AES_REG_IRQ_DATA_IN            BIT(1)
 85 #define AES_REG_IRQ_DATA_OUT           BIT(2)
 86 #define DEFAULT_TIMEOUT         (5*HZ)
 87 
 88 #define FLAGS_MODE_MASK         0x000f
 89 #define FLAGS_ENCRYPT           BIT(0)
 90 #define FLAGS_CBC               BIT(1)
 91 #define FLAGS_GIV               BIT(2)
 92 #define FLAGS_CTR               BIT(3)
 93 
 94 #define FLAGS_INIT              BIT(4)
 95 #define FLAGS_FAST              BIT(5)
 96 #define FLAGS_BUSY              BIT(6)
 97 
 98 #define AES_BLOCK_WORDS         (AES_BLOCK_SIZE >> 2)
 99 
100 struct omap_aes_ctx {
101         struct omap_aes_dev *dd;
102 
103         int             keylen;
104         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
105         unsigned long   flags;
106 };
107 
108 struct omap_aes_reqctx {
109         unsigned long mode;
110 };
111 
112 #define OMAP_AES_QUEUE_LENGTH   1
113 #define OMAP_AES_CACHE_SIZE     0
114 
115 struct omap_aes_algs_info {
116         struct crypto_alg       *algs_list;
117         unsigned int            size;
118         unsigned int            registered;
119 };
120 
121 struct omap_aes_pdata {
122         struct omap_aes_algs_info       *algs_info;
123         unsigned int    algs_info_size;
124 
125         void            (*trigger)(struct omap_aes_dev *dd, int length);
126 
127         u32             key_ofs;
128         u32             iv_ofs;
129         u32             ctrl_ofs;
130         u32             data_ofs;
131         u32             rev_ofs;
132         u32             mask_ofs;
133         u32             irq_enable_ofs;
134         u32             irq_status_ofs;
135 
136         u32             dma_enable_in;
137         u32             dma_enable_out;
138         u32             dma_start;
139 
140         u32             major_mask;
141         u32             major_shift;
142         u32             minor_mask;
143         u32             minor_shift;
144 };
145 
146 struct omap_aes_dev {
147         struct list_head        list;
148         unsigned long           phys_base;
149         void __iomem            *io_base;
150         struct omap_aes_ctx     *ctx;
151         struct device           *dev;
152         unsigned long           flags;
153         int                     err;
154 
155         spinlock_t              lock;
156         struct crypto_queue     queue;
157 
158         struct tasklet_struct   done_task;
159         struct tasklet_struct   queue_task;
160 
161         struct ablkcipher_request       *req;
162 
163         /*
164          * total is used by PIO mode for book keeping so introduce
165          * variable total_save as need it to calc page_order
166          */
167         size_t                          total;
168         size_t                          total_save;
169 
170         struct scatterlist              *in_sg;
171         struct scatterlist              *out_sg;
172 
173         /* Buffers for copying for unaligned cases */
174         struct scatterlist              in_sgl;
175         struct scatterlist              out_sgl;
176         struct scatterlist              *orig_out;
177         int                             sgs_copied;
178 
179         struct scatter_walk             in_walk;
180         struct scatter_walk             out_walk;
181         int                     dma_in;
182         struct dma_chan         *dma_lch_in;
183         int                     dma_out;
184         struct dma_chan         *dma_lch_out;
185         int                     in_sg_len;
186         int                     out_sg_len;
187         int                     pio_only;
188         const struct omap_aes_pdata     *pdata;
189 };
190 
191 /* keep registered devices data here */
192 static LIST_HEAD(dev_list);
193 static DEFINE_SPINLOCK(list_lock);
194 
195 #ifdef DEBUG
196 #define omap_aes_read(dd, offset)                               \
197 ({                                                              \
198         int _read_ret;                                          \
199         _read_ret = __raw_readl(dd->io_base + offset);          \
200         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
201                  offset, _read_ret);                            \
202         _read_ret;                                              \
203 })
204 #else
205 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
206 {
207         return __raw_readl(dd->io_base + offset);
208 }
209 #endif
210 
211 #ifdef DEBUG
212 #define omap_aes_write(dd, offset, value)                               \
213         do {                                                            \
214                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
215                          offset, value);                                \
216                 __raw_writel(value, dd->io_base + offset);              \
217         } while (0)
218 #else
219 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
220                                   u32 value)
221 {
222         __raw_writel(value, dd->io_base + offset);
223 }
224 #endif
225 
226 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
227                                         u32 value, u32 mask)
228 {
229         u32 val;
230 
231         val = omap_aes_read(dd, offset);
232         val &= ~mask;
233         val |= value;
234         omap_aes_write(dd, offset, val);
235 }
236 
237 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
238                                         u32 *value, int count)
239 {
240         for (; count--; value++, offset += 4)
241                 omap_aes_write(dd, offset, *value);
242 }
243 
244 static int omap_aes_hw_init(struct omap_aes_dev *dd)
245 {
246         if (!(dd->flags & FLAGS_INIT)) {
247                 dd->flags |= FLAGS_INIT;
248                 dd->err = 0;
249         }
250 
251         return 0;
252 }
253 
254 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
255 {
256         unsigned int key32;
257         int i, err;
258         u32 val;
259 
260         err = omap_aes_hw_init(dd);
261         if (err)
262                 return err;
263 
264         key32 = dd->ctx->keylen / sizeof(u32);
265 
266         /* it seems a key should always be set even if it has not changed */
267         for (i = 0; i < key32; i++) {
268                 omap_aes_write(dd, AES_REG_KEY(dd, i),
269                         __le32_to_cpu(dd->ctx->key[i]));
270         }
271 
272         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
273                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
274 
275         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
276         if (dd->flags & FLAGS_CBC)
277                 val |= AES_REG_CTRL_CBC;
278         if (dd->flags & FLAGS_CTR)
279                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
280 
281         if (dd->flags & FLAGS_ENCRYPT)
282                 val |= AES_REG_CTRL_DIRECTION;
283 
284         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
285 
286         return 0;
287 }
288 
289 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
290 {
291         u32 mask, val;
292 
293         val = dd->pdata->dma_start;
294 
295         if (dd->dma_lch_out != NULL)
296                 val |= dd->pdata->dma_enable_out;
297         if (dd->dma_lch_in != NULL)
298                 val |= dd->pdata->dma_enable_in;
299 
300         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
301                dd->pdata->dma_start;
302 
303         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
304 
305 }
306 
307 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
308 {
309         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
310         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
311 
312         omap_aes_dma_trigger_omap2(dd, length);
313 }
314 
315 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
316 {
317         u32 mask;
318 
319         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
320                dd->pdata->dma_start;
321 
322         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
323 }
324 
325 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
326 {
327         struct omap_aes_dev *dd = NULL, *tmp;
328 
329         spin_lock_bh(&list_lock);
330         if (!ctx->dd) {
331                 list_for_each_entry(tmp, &dev_list, list) {
332                         /* FIXME: take fist available aes core */
333                         dd = tmp;
334                         break;
335                 }
336                 ctx->dd = dd;
337         } else {
338                 /* already found before */
339                 dd = ctx->dd;
340         }
341         spin_unlock_bh(&list_lock);
342 
343         return dd;
344 }
345 
346 static void omap_aes_dma_out_callback(void *data)
347 {
348         struct omap_aes_dev *dd = data;
349 
350         /* dma_lch_out - completed */
351         tasklet_schedule(&dd->done_task);
352 }
353 
354 static int omap_aes_dma_init(struct omap_aes_dev *dd)
355 {
356         int err = -ENOMEM;
357         dma_cap_mask_t mask;
358 
359         dd->dma_lch_out = NULL;
360         dd->dma_lch_in = NULL;
361 
362         dma_cap_zero(mask);
363         dma_cap_set(DMA_SLAVE, mask);
364 
365         dd->dma_lch_in = dma_request_slave_channel_compat(mask,
366                                                           omap_dma_filter_fn,
367                                                           &dd->dma_in,
368                                                           dd->dev, "rx");
369         if (!dd->dma_lch_in) {
370                 dev_err(dd->dev, "Unable to request in DMA channel\n");
371                 goto err_dma_in;
372         }
373 
374         dd->dma_lch_out = dma_request_slave_channel_compat(mask,
375                                                            omap_dma_filter_fn,
376                                                            &dd->dma_out,
377                                                            dd->dev, "tx");
378         if (!dd->dma_lch_out) {
379                 dev_err(dd->dev, "Unable to request out DMA channel\n");
380                 goto err_dma_out;
381         }
382 
383         return 0;
384 
385 err_dma_out:
386         dma_release_channel(dd->dma_lch_in);
387 err_dma_in:
388         if (err)
389                 pr_err("error: %d\n", err);
390         return err;
391 }
392 
393 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
394 {
395         dma_release_channel(dd->dma_lch_out);
396         dma_release_channel(dd->dma_lch_in);
397 }
398 
399 static void sg_copy_buf(void *buf, struct scatterlist *sg,
400                               unsigned int start, unsigned int nbytes, int out)
401 {
402         struct scatter_walk walk;
403 
404         if (!nbytes)
405                 return;
406 
407         scatterwalk_start(&walk, sg);
408         scatterwalk_advance(&walk, start);
409         scatterwalk_copychunks(buf, &walk, nbytes, out);
410         scatterwalk_done(&walk, out, 0);
411 }
412 
413 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
414                 struct scatterlist *in_sg, struct scatterlist *out_sg,
415                 int in_sg_len, int out_sg_len)
416 {
417         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
418         struct omap_aes_dev *dd = ctx->dd;
419         struct dma_async_tx_descriptor *tx_in, *tx_out;
420         struct dma_slave_config cfg;
421         int ret;
422 
423         if (dd->pio_only) {
424                 scatterwalk_start(&dd->in_walk, dd->in_sg);
425                 scatterwalk_start(&dd->out_walk, dd->out_sg);
426 
427                 /* Enable DATAIN interrupt and let it take
428                    care of the rest */
429                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
430                 return 0;
431         }
432 
433         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
434 
435         memset(&cfg, 0, sizeof(cfg));
436 
437         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
438         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
439         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
440         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
441         cfg.src_maxburst = DST_MAXBURST;
442         cfg.dst_maxburst = DST_MAXBURST;
443 
444         /* IN */
445         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
446         if (ret) {
447                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
448                         ret);
449                 return ret;
450         }
451 
452         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
453                                         DMA_MEM_TO_DEV,
454                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
455         if (!tx_in) {
456                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
457                 return -EINVAL;
458         }
459 
460         /* No callback necessary */
461         tx_in->callback_param = dd;
462 
463         /* OUT */
464         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
465         if (ret) {
466                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
467                         ret);
468                 return ret;
469         }
470 
471         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
472                                         DMA_DEV_TO_MEM,
473                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
474         if (!tx_out) {
475                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
476                 return -EINVAL;
477         }
478 
479         tx_out->callback = omap_aes_dma_out_callback;
480         tx_out->callback_param = dd;
481 
482         dmaengine_submit(tx_in);
483         dmaengine_submit(tx_out);
484 
485         dma_async_issue_pending(dd->dma_lch_in);
486         dma_async_issue_pending(dd->dma_lch_out);
487 
488         /* start DMA */
489         dd->pdata->trigger(dd, dd->total);
490 
491         return 0;
492 }
493 
494 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
495 {
496         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
497                                         crypto_ablkcipher_reqtfm(dd->req));
498         int err;
499 
500         pr_debug("total: %d\n", dd->total);
501 
502         if (!dd->pio_only) {
503                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
504                                  DMA_TO_DEVICE);
505                 if (!err) {
506                         dev_err(dd->dev, "dma_map_sg() error\n");
507                         return -EINVAL;
508                 }
509 
510                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
511                                  DMA_FROM_DEVICE);
512                 if (!err) {
513                         dev_err(dd->dev, "dma_map_sg() error\n");
514                         return -EINVAL;
515                 }
516         }
517 
518         err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
519                                  dd->out_sg_len);
520         if (err && !dd->pio_only) {
521                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
522                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
523                              DMA_FROM_DEVICE);
524         }
525 
526         return err;
527 }
528 
529 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
530 {
531         struct ablkcipher_request *req = dd->req;
532 
533         pr_debug("err: %d\n", err);
534 
535         dd->flags &= ~FLAGS_BUSY;
536 
537         req->base.complete(&req->base, err);
538 }
539 
540 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
541 {
542         pr_debug("total: %d\n", dd->total);
543 
544         omap_aes_dma_stop(dd);
545 
546         dmaengine_terminate_all(dd->dma_lch_in);
547         dmaengine_terminate_all(dd->dma_lch_out);
548 
549         return 0;
550 }
551 
552 static int omap_aes_check_aligned(struct scatterlist *sg, int total)
553 {
554         int len = 0;
555 
556         if (!IS_ALIGNED(total, AES_BLOCK_SIZE))
557                 return -EINVAL;
558 
559         while (sg) {
560                 if (!IS_ALIGNED(sg->offset, 4))
561                         return -1;
562                 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
563                         return -1;
564 
565                 len += sg->length;
566                 sg = sg_next(sg);
567         }
568 
569         if (len != total)
570                 return -1;
571 
572         return 0;
573 }
574 
575 static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
576 {
577         void *buf_in, *buf_out;
578         int pages, total;
579 
580         total = ALIGN(dd->total, AES_BLOCK_SIZE);
581         pages = get_order(total);
582 
583         buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
584         buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
585 
586         if (!buf_in || !buf_out) {
587                 pr_err("Couldn't allocated pages for unaligned cases.\n");
588                 return -1;
589         }
590 
591         dd->orig_out = dd->out_sg;
592 
593         sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
594 
595         sg_init_table(&dd->in_sgl, 1);
596         sg_set_buf(&dd->in_sgl, buf_in, total);
597         dd->in_sg = &dd->in_sgl;
598 
599         sg_init_table(&dd->out_sgl, 1);
600         sg_set_buf(&dd->out_sgl, buf_out, total);
601         dd->out_sg = &dd->out_sgl;
602 
603         return 0;
604 }
605 
606 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
607                                struct ablkcipher_request *req)
608 {
609         struct crypto_async_request *async_req, *backlog;
610         struct omap_aes_ctx *ctx;
611         struct omap_aes_reqctx *rctx;
612         unsigned long flags;
613         int err, ret = 0, len;
614 
615         spin_lock_irqsave(&dd->lock, flags);
616         if (req)
617                 ret = ablkcipher_enqueue_request(&dd->queue, req);
618         if (dd->flags & FLAGS_BUSY) {
619                 spin_unlock_irqrestore(&dd->lock, flags);
620                 return ret;
621         }
622         backlog = crypto_get_backlog(&dd->queue);
623         async_req = crypto_dequeue_request(&dd->queue);
624         if (async_req)
625                 dd->flags |= FLAGS_BUSY;
626         spin_unlock_irqrestore(&dd->lock, flags);
627 
628         if (!async_req)
629                 return ret;
630 
631         if (backlog)
632                 backlog->complete(backlog, -EINPROGRESS);
633 
634         req = ablkcipher_request_cast(async_req);
635 
636         /* assign new request to device */
637         dd->req = req;
638         dd->total = req->nbytes;
639         dd->total_save = req->nbytes;
640         dd->in_sg = req->src;
641         dd->out_sg = req->dst;
642 
643         if (omap_aes_check_aligned(dd->in_sg, dd->total) ||
644             omap_aes_check_aligned(dd->out_sg, dd->total)) {
645                 if (omap_aes_copy_sgs(dd))
646                         pr_err("Failed to copy SGs for unaligned cases\n");
647                 dd->sgs_copied = 1;
648         } else {
649                 dd->sgs_copied = 0;
650         }
651 
652         len = ALIGN(dd->total, AES_BLOCK_SIZE);
653         dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, len);
654         dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, len);
655         BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
656 
657         rctx = ablkcipher_request_ctx(req);
658         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
659         rctx->mode &= FLAGS_MODE_MASK;
660         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
661 
662         dd->ctx = ctx;
663         ctx->dd = dd;
664 
665         err = omap_aes_write_ctrl(dd);
666         if (!err)
667                 err = omap_aes_crypt_dma_start(dd);
668         if (err) {
669                 /* aes_task will not finish it, so do it here */
670                 omap_aes_finish_req(dd, err);
671                 tasklet_schedule(&dd->queue_task);
672         }
673 
674         return ret; /* return ret, which is enqueue return value */
675 }
676 
677 static void omap_aes_done_task(unsigned long data)
678 {
679         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
680         void *buf_in, *buf_out;
681         int pages, len;
682 
683         pr_debug("enter done_task\n");
684 
685         if (!dd->pio_only) {
686                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
687                                        DMA_FROM_DEVICE);
688                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
689                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
690                              DMA_FROM_DEVICE);
691                 omap_aes_crypt_dma_stop(dd);
692         }
693 
694         if (dd->sgs_copied) {
695                 buf_in = sg_virt(&dd->in_sgl);
696                 buf_out = sg_virt(&dd->out_sgl);
697 
698                 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
699 
700                 len = ALIGN(dd->total_save, AES_BLOCK_SIZE);
701                 pages = get_order(len);
702                 free_pages((unsigned long)buf_in, pages);
703                 free_pages((unsigned long)buf_out, pages);
704         }
705 
706         omap_aes_finish_req(dd, 0);
707         omap_aes_handle_queue(dd, NULL);
708 
709         pr_debug("exit\n");
710 }
711 
712 static void omap_aes_queue_task(unsigned long data)
713 {
714         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
715 
716         omap_aes_handle_queue(dd, NULL);
717 }
718 
719 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
720 {
721         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
722                         crypto_ablkcipher_reqtfm(req));
723         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
724         struct omap_aes_dev *dd;
725 
726         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
727                   !!(mode & FLAGS_ENCRYPT),
728                   !!(mode & FLAGS_CBC));
729 
730         dd = omap_aes_find_dev(ctx);
731         if (!dd)
732                 return -ENODEV;
733 
734         rctx->mode = mode;
735 
736         return omap_aes_handle_queue(dd, req);
737 }
738 
739 /* ********************** ALG API ************************************ */
740 
741 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
742                            unsigned int keylen)
743 {
744         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
745 
746         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
747                    keylen != AES_KEYSIZE_256)
748                 return -EINVAL;
749 
750         pr_debug("enter, keylen: %d\n", keylen);
751 
752         memcpy(ctx->key, key, keylen);
753         ctx->keylen = keylen;
754 
755         return 0;
756 }
757 
758 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
759 {
760         return omap_aes_crypt(req, FLAGS_ENCRYPT);
761 }
762 
763 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
764 {
765         return omap_aes_crypt(req, 0);
766 }
767 
768 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
769 {
770         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
771 }
772 
773 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
774 {
775         return omap_aes_crypt(req, FLAGS_CBC);
776 }
777 
778 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
779 {
780         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
781 }
782 
783 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
784 {
785         return omap_aes_crypt(req, FLAGS_CTR);
786 }
787 
788 static int omap_aes_cra_init(struct crypto_tfm *tfm)
789 {
790         struct omap_aes_dev *dd = NULL;
791         int err;
792 
793         /* Find AES device, currently picks the first device */
794         spin_lock_bh(&list_lock);
795         list_for_each_entry(dd, &dev_list, list) {
796                 break;
797         }
798         spin_unlock_bh(&list_lock);
799 
800         err = pm_runtime_get_sync(dd->dev);
801         if (err < 0) {
802                 dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
803                         __func__, err);
804                 return err;
805         }
806 
807         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
808 
809         return 0;
810 }
811 
812 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
813 {
814         struct omap_aes_dev *dd = NULL;
815 
816         /* Find AES device, currently picks the first device */
817         spin_lock_bh(&list_lock);
818         list_for_each_entry(dd, &dev_list, list) {
819                 break;
820         }
821         spin_unlock_bh(&list_lock);
822 
823         pm_runtime_put_sync(dd->dev);
824 }
825 
826 /* ********************** ALGS ************************************ */
827 
828 static struct crypto_alg algs_ecb_cbc[] = {
829 {
830         .cra_name               = "ecb(aes)",
831         .cra_driver_name        = "ecb-aes-omap",
832         .cra_priority           = 300,
833         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
834                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
835                                   CRYPTO_ALG_ASYNC,
836         .cra_blocksize          = AES_BLOCK_SIZE,
837         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
838         .cra_alignmask          = 0,
839         .cra_type               = &crypto_ablkcipher_type,
840         .cra_module             = THIS_MODULE,
841         .cra_init               = omap_aes_cra_init,
842         .cra_exit               = omap_aes_cra_exit,
843         .cra_u.ablkcipher = {
844                 .min_keysize    = AES_MIN_KEY_SIZE,
845                 .max_keysize    = AES_MAX_KEY_SIZE,
846                 .setkey         = omap_aes_setkey,
847                 .encrypt        = omap_aes_ecb_encrypt,
848                 .decrypt        = omap_aes_ecb_decrypt,
849         }
850 },
851 {
852         .cra_name               = "cbc(aes)",
853         .cra_driver_name        = "cbc-aes-omap",
854         .cra_priority           = 300,
855         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
856                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
857                                   CRYPTO_ALG_ASYNC,
858         .cra_blocksize          = AES_BLOCK_SIZE,
859         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
860         .cra_alignmask          = 0,
861         .cra_type               = &crypto_ablkcipher_type,
862         .cra_module             = THIS_MODULE,
863         .cra_init               = omap_aes_cra_init,
864         .cra_exit               = omap_aes_cra_exit,
865         .cra_u.ablkcipher = {
866                 .min_keysize    = AES_MIN_KEY_SIZE,
867                 .max_keysize    = AES_MAX_KEY_SIZE,
868                 .ivsize         = AES_BLOCK_SIZE,
869                 .setkey         = omap_aes_setkey,
870                 .encrypt        = omap_aes_cbc_encrypt,
871                 .decrypt        = omap_aes_cbc_decrypt,
872         }
873 }
874 };
875 
876 static struct crypto_alg algs_ctr[] = {
877 {
878         .cra_name               = "ctr(aes)",
879         .cra_driver_name        = "ctr-aes-omap",
880         .cra_priority           = 300,
881         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
882                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
883                                   CRYPTO_ALG_ASYNC,
884         .cra_blocksize          = AES_BLOCK_SIZE,
885         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
886         .cra_alignmask          = 0,
887         .cra_type               = &crypto_ablkcipher_type,
888         .cra_module             = THIS_MODULE,
889         .cra_init               = omap_aes_cra_init,
890         .cra_exit               = omap_aes_cra_exit,
891         .cra_u.ablkcipher = {
892                 .min_keysize    = AES_MIN_KEY_SIZE,
893                 .max_keysize    = AES_MAX_KEY_SIZE,
894                 .geniv          = "eseqiv",
895                 .ivsize         = AES_BLOCK_SIZE,
896                 .setkey         = omap_aes_setkey,
897                 .encrypt        = omap_aes_ctr_encrypt,
898                 .decrypt        = omap_aes_ctr_decrypt,
899         }
900 } ,
901 };
902 
903 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
904         {
905                 .algs_list      = algs_ecb_cbc,
906                 .size           = ARRAY_SIZE(algs_ecb_cbc),
907         },
908 };
909 
910 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
911         .algs_info      = omap_aes_algs_info_ecb_cbc,
912         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
913         .trigger        = omap_aes_dma_trigger_omap2,
914         .key_ofs        = 0x1c,
915         .iv_ofs         = 0x20,
916         .ctrl_ofs       = 0x30,
917         .data_ofs       = 0x34,
918         .rev_ofs        = 0x44,
919         .mask_ofs       = 0x48,
920         .dma_enable_in  = BIT(2),
921         .dma_enable_out = BIT(3),
922         .dma_start      = BIT(5),
923         .major_mask     = 0xf0,
924         .major_shift    = 4,
925         .minor_mask     = 0x0f,
926         .minor_shift    = 0,
927 };
928 
929 #ifdef CONFIG_OF
930 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
931         {
932                 .algs_list      = algs_ecb_cbc,
933                 .size           = ARRAY_SIZE(algs_ecb_cbc),
934         },
935         {
936                 .algs_list      = algs_ctr,
937                 .size           = ARRAY_SIZE(algs_ctr),
938         },
939 };
940 
941 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
942         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
943         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
944         .trigger        = omap_aes_dma_trigger_omap2,
945         .key_ofs        = 0x1c,
946         .iv_ofs         = 0x20,
947         .ctrl_ofs       = 0x30,
948         .data_ofs       = 0x34,
949         .rev_ofs        = 0x44,
950         .mask_ofs       = 0x48,
951         .dma_enable_in  = BIT(2),
952         .dma_enable_out = BIT(3),
953         .dma_start      = BIT(5),
954         .major_mask     = 0xf0,
955         .major_shift    = 4,
956         .minor_mask     = 0x0f,
957         .minor_shift    = 0,
958 };
959 
960 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
961         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
962         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
963         .trigger        = omap_aes_dma_trigger_omap4,
964         .key_ofs        = 0x3c,
965         .iv_ofs         = 0x40,
966         .ctrl_ofs       = 0x50,
967         .data_ofs       = 0x60,
968         .rev_ofs        = 0x80,
969         .mask_ofs       = 0x84,
970         .irq_status_ofs = 0x8c,
971         .irq_enable_ofs = 0x90,
972         .dma_enable_in  = BIT(5),
973         .dma_enable_out = BIT(6),
974         .major_mask     = 0x0700,
975         .major_shift    = 8,
976         .minor_mask     = 0x003f,
977         .minor_shift    = 0,
978 };
979 
980 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
981 {
982         struct omap_aes_dev *dd = dev_id;
983         u32 status, i;
984         u32 *src, *dst;
985 
986         status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
987         if (status & AES_REG_IRQ_DATA_IN) {
988                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
989 
990                 BUG_ON(!dd->in_sg);
991 
992                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
993 
994                 src = sg_virt(dd->in_sg) + _calc_walked(in);
995 
996                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
997                         omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
998 
999                         scatterwalk_advance(&dd->in_walk, 4);
1000                         if (dd->in_sg->length == _calc_walked(in)) {
1001                                 dd->in_sg = sg_next(dd->in_sg);
1002                                 if (dd->in_sg) {
1003                                         scatterwalk_start(&dd->in_walk,
1004                                                           dd->in_sg);
1005                                         src = sg_virt(dd->in_sg) +
1006                                               _calc_walked(in);
1007                                 }
1008                         } else {
1009                                 src++;
1010                         }
1011                 }
1012 
1013                 /* Clear IRQ status */
1014                 status &= ~AES_REG_IRQ_DATA_IN;
1015                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1016 
1017                 /* Enable DATA_OUT interrupt */
1018                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
1019 
1020         } else if (status & AES_REG_IRQ_DATA_OUT) {
1021                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
1022 
1023                 BUG_ON(!dd->out_sg);
1024 
1025                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
1026 
1027                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
1028 
1029                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
1030                         *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
1031                         scatterwalk_advance(&dd->out_walk, 4);
1032                         if (dd->out_sg->length == _calc_walked(out)) {
1033                                 dd->out_sg = sg_next(dd->out_sg);
1034                                 if (dd->out_sg) {
1035                                         scatterwalk_start(&dd->out_walk,
1036                                                           dd->out_sg);
1037                                         dst = sg_virt(dd->out_sg) +
1038                                               _calc_walked(out);
1039                                 }
1040                         } else {
1041                                 dst++;
1042                         }
1043                 }
1044 
1045                 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
1046 
1047                 /* Clear IRQ status */
1048                 status &= ~AES_REG_IRQ_DATA_OUT;
1049                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1050 
1051                 if (!dd->total)
1052                         /* All bytes read! */
1053                         tasklet_schedule(&dd->done_task);
1054                 else
1055                         /* Enable DATA_IN interrupt for next block */
1056                         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1057         }
1058 
1059         return IRQ_HANDLED;
1060 }
1061 
1062 static const struct of_device_id omap_aes_of_match[] = {
1063         {
1064                 .compatible     = "ti,omap2-aes",
1065                 .data           = &omap_aes_pdata_omap2,
1066         },
1067         {
1068                 .compatible     = "ti,omap3-aes",
1069                 .data           = &omap_aes_pdata_omap3,
1070         },
1071         {
1072                 .compatible     = "ti,omap4-aes",
1073                 .data           = &omap_aes_pdata_omap4,
1074         },
1075         {},
1076 };
1077 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1078 
1079 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1080                 struct device *dev, struct resource *res)
1081 {
1082         struct device_node *node = dev->of_node;
1083         const struct of_device_id *match;
1084         int err = 0;
1085 
1086         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1087         if (!match) {
1088                 dev_err(dev, "no compatible OF match\n");
1089                 err = -EINVAL;
1090                 goto err;
1091         }
1092 
1093         err = of_address_to_resource(node, 0, res);
1094         if (err < 0) {
1095                 dev_err(dev, "can't translate OF node address\n");
1096                 err = -EINVAL;
1097                 goto err;
1098         }
1099 
1100         dd->dma_out = -1; /* Dummy value that's unused */
1101         dd->dma_in = -1; /* Dummy value that's unused */
1102 
1103         dd->pdata = match->data;
1104 
1105 err:
1106         return err;
1107 }
1108 #else
1109 static const struct of_device_id omap_aes_of_match[] = {
1110         {},
1111 };
1112 
1113 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1114                 struct device *dev, struct resource *res)
1115 {
1116         return -EINVAL;
1117 }
1118 #endif
1119 
1120 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1121                 struct platform_device *pdev, struct resource *res)
1122 {
1123         struct device *dev = &pdev->dev;
1124         struct resource *r;
1125         int err = 0;
1126 
1127         /* Get the base address */
1128         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1129         if (!r) {
1130                 dev_err(dev, "no MEM resource info\n");
1131                 err = -ENODEV;
1132                 goto err;
1133         }
1134         memcpy(res, r, sizeof(*res));
1135 
1136         /* Get the DMA out channel */
1137         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1138         if (!r) {
1139                 dev_err(dev, "no DMA out resource info\n");
1140                 err = -ENODEV;
1141                 goto err;
1142         }
1143         dd->dma_out = r->start;
1144 
1145         /* Get the DMA in channel */
1146         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1147         if (!r) {
1148                 dev_err(dev, "no DMA in resource info\n");
1149                 err = -ENODEV;
1150                 goto err;
1151         }
1152         dd->dma_in = r->start;
1153 
1154         /* Only OMAP2/3 can be non-DT */
1155         dd->pdata = &omap_aes_pdata_omap2;
1156 
1157 err:
1158         return err;
1159 }
1160 
1161 static int omap_aes_probe(struct platform_device *pdev)
1162 {
1163         struct device *dev = &pdev->dev;
1164         struct omap_aes_dev *dd;
1165         struct crypto_alg *algp;
1166         struct resource res;
1167         int err = -ENOMEM, i, j, irq = -1;
1168         u32 reg;
1169 
1170         dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1171         if (dd == NULL) {
1172                 dev_err(dev, "unable to alloc data struct.\n");
1173                 goto err_data;
1174         }
1175         dd->dev = dev;
1176         platform_set_drvdata(pdev, dd);
1177 
1178         spin_lock_init(&dd->lock);
1179         crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
1180 
1181         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1182                                omap_aes_get_res_pdev(dd, pdev, &res);
1183         if (err)
1184                 goto err_res;
1185 
1186         dd->io_base = devm_ioremap_resource(dev, &res);
1187         if (IS_ERR(dd->io_base)) {
1188                 err = PTR_ERR(dd->io_base);
1189                 goto err_res;
1190         }
1191         dd->phys_base = res.start;
1192 
1193         pm_runtime_enable(dev);
1194         err = pm_runtime_get_sync(dev);
1195         if (err < 0) {
1196                 dev_err(dev, "%s: failed to get_sync(%d)\n",
1197                         __func__, err);
1198                 goto err_res;
1199         }
1200 
1201         omap_aes_dma_stop(dd);
1202 
1203         reg = omap_aes_read(dd, AES_REG_REV(dd));
1204 
1205         pm_runtime_put_sync(dev);
1206 
1207         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1208                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1209                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1210 
1211         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1212         tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
1213 
1214         err = omap_aes_dma_init(dd);
1215         if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1216                 dd->pio_only = 1;
1217 
1218                 irq = platform_get_irq(pdev, 0);
1219                 if (irq < 0) {
1220                         dev_err(dev, "can't get IRQ resource\n");
1221                         goto err_irq;
1222                 }
1223 
1224                 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1225                                 dev_name(dev), dd);
1226                 if (err) {
1227                         dev_err(dev, "Unable to grab omap-aes IRQ\n");
1228                         goto err_irq;
1229                 }
1230         }
1231 
1232 
1233         INIT_LIST_HEAD(&dd->list);
1234         spin_lock(&list_lock);
1235         list_add_tail(&dd->list, &dev_list);
1236         spin_unlock(&list_lock);
1237 
1238         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1239                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1240                         algp = &dd->pdata->algs_info[i].algs_list[j];
1241 
1242                         pr_debug("reg alg: %s\n", algp->cra_name);
1243                         INIT_LIST_HEAD(&algp->cra_list);
1244 
1245                         err = crypto_register_alg(algp);
1246                         if (err)
1247                                 goto err_algs;
1248 
1249                         dd->pdata->algs_info[i].registered++;
1250                 }
1251         }
1252 
1253         return 0;
1254 err_algs:
1255         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1256                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1257                         crypto_unregister_alg(
1258                                         &dd->pdata->algs_info[i].algs_list[j]);
1259         if (!dd->pio_only)
1260                 omap_aes_dma_cleanup(dd);
1261 err_irq:
1262         tasklet_kill(&dd->done_task);
1263         tasklet_kill(&dd->queue_task);
1264         pm_runtime_disable(dev);
1265 err_res:
1266         dd = NULL;
1267 err_data:
1268         dev_err(dev, "initialization failed.\n");
1269         return err;
1270 }
1271 
1272 static int omap_aes_remove(struct platform_device *pdev)
1273 {
1274         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1275         int i, j;
1276 
1277         if (!dd)
1278                 return -ENODEV;
1279 
1280         spin_lock(&list_lock);
1281         list_del(&dd->list);
1282         spin_unlock(&list_lock);
1283 
1284         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1285                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1286                         crypto_unregister_alg(
1287                                         &dd->pdata->algs_info[i].algs_list[j]);
1288 
1289         tasklet_kill(&dd->done_task);
1290         tasklet_kill(&dd->queue_task);
1291         omap_aes_dma_cleanup(dd);
1292         pm_runtime_disable(dd->dev);
1293         dd = NULL;
1294 
1295         return 0;
1296 }
1297 
1298 #ifdef CONFIG_PM_SLEEP
1299 static int omap_aes_suspend(struct device *dev)
1300 {
1301         pm_runtime_put_sync(dev);
1302         return 0;
1303 }
1304 
1305 static int omap_aes_resume(struct device *dev)
1306 {
1307         pm_runtime_get_sync(dev);
1308         return 0;
1309 }
1310 #endif
1311 
1312 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1313 
1314 static struct platform_driver omap_aes_driver = {
1315         .probe  = omap_aes_probe,
1316         .remove = omap_aes_remove,
1317         .driver = {
1318                 .name   = "omap-aes",
1319                 .pm     = &omap_aes_pm_ops,
1320                 .of_match_table = omap_aes_of_match,
1321         },
1322 };
1323 
1324 module_platform_driver(omap_aes_driver);
1325 
1326 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1327 MODULE_LICENSE("GPL v2");
1328 MODULE_AUTHOR("Dmitry Kasatkin");
1329 
1330 

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