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Linux/drivers/crypto/mxs-dcp.c

  1 /*
  2  * Freescale i.MX23/i.MX28 Data Co-Processor driver
  3  *
  4  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  5  *
  6  * The code contained herein is licensed under the GNU General Public
  7  * License. You may obtain a copy of the GNU General Public License
  8  * Version 2 or later at the following locations:
  9  *
 10  * http://www.opensource.org/licenses/gpl-license.html
 11  * http://www.gnu.org/copyleft/gpl.html
 12  */
 13 
 14 #include <linux/dma-mapping.h>
 15 #include <linux/interrupt.h>
 16 #include <linux/io.h>
 17 #include <linux/kernel.h>
 18 #include <linux/kthread.h>
 19 #include <linux/module.h>
 20 #include <linux/of.h>
 21 #include <linux/platform_device.h>
 22 #include <linux/stmp_device.h>
 23 
 24 #include <crypto/aes.h>
 25 #include <crypto/sha.h>
 26 #include <crypto/internal/hash.h>
 27 #include <crypto/internal/skcipher.h>
 28 
 29 #define DCP_MAX_CHANS   4
 30 #define DCP_BUF_SZ      PAGE_SIZE
 31 
 32 #define DCP_ALIGNMENT   64
 33 
 34 /* DCP DMA descriptor. */
 35 struct dcp_dma_desc {
 36         uint32_t        next_cmd_addr;
 37         uint32_t        control0;
 38         uint32_t        control1;
 39         uint32_t        source;
 40         uint32_t        destination;
 41         uint32_t        size;
 42         uint32_t        payload;
 43         uint32_t        status;
 44 };
 45 
 46 /* Coherent aligned block for bounce buffering. */
 47 struct dcp_coherent_block {
 48         uint8_t                 aes_in_buf[DCP_BUF_SZ];
 49         uint8_t                 aes_out_buf[DCP_BUF_SZ];
 50         uint8_t                 sha_in_buf[DCP_BUF_SZ];
 51 
 52         uint8_t                 aes_key[2 * AES_KEYSIZE_128];
 53 
 54         struct dcp_dma_desc     desc[DCP_MAX_CHANS];
 55 };
 56 
 57 struct dcp {
 58         struct device                   *dev;
 59         void __iomem                    *base;
 60 
 61         uint32_t                        caps;
 62 
 63         struct dcp_coherent_block       *coh;
 64 
 65         struct completion               completion[DCP_MAX_CHANS];
 66         struct mutex                    mutex[DCP_MAX_CHANS];
 67         struct task_struct              *thread[DCP_MAX_CHANS];
 68         struct crypto_queue             queue[DCP_MAX_CHANS];
 69 };
 70 
 71 enum dcp_chan {
 72         DCP_CHAN_HASH_SHA       = 0,
 73         DCP_CHAN_CRYPTO         = 2,
 74 };
 75 
 76 struct dcp_async_ctx {
 77         /* Common context */
 78         enum dcp_chan   chan;
 79         uint32_t        fill;
 80 
 81         /* SHA Hash-specific context */
 82         struct mutex                    mutex;
 83         uint32_t                        alg;
 84         unsigned int                    hot:1;
 85 
 86         /* Crypto-specific context */
 87         struct crypto_skcipher          *fallback;
 88         unsigned int                    key_len;
 89         uint8_t                         key[AES_KEYSIZE_128];
 90 };
 91 
 92 struct dcp_aes_req_ctx {
 93         unsigned int    enc:1;
 94         unsigned int    ecb:1;
 95 };
 96 
 97 struct dcp_sha_req_ctx {
 98         unsigned int    init:1;
 99         unsigned int    fini:1;
100 };
101 
102 /*
103  * There can even be only one instance of the MXS DCP due to the
104  * design of Linux Crypto API.
105  */
106 static struct dcp *global_sdcp;
107 
108 /* DCP register layout. */
109 #define MXS_DCP_CTRL                            0x00
110 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES     (1 << 23)
111 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING     (1 << 22)
112 
113 #define MXS_DCP_STAT                            0x10
114 #define MXS_DCP_STAT_CLR                        0x18
115 #define MXS_DCP_STAT_IRQ_MASK                   0xf
116 
117 #define MXS_DCP_CHANNELCTRL                     0x20
118 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
119 
120 #define MXS_DCP_CAPABILITY1                     0x40
121 #define MXS_DCP_CAPABILITY1_SHA256              (4 << 16)
122 #define MXS_DCP_CAPABILITY1_SHA1                (1 << 16)
123 #define MXS_DCP_CAPABILITY1_AES128              (1 << 0)
124 
125 #define MXS_DCP_CONTEXT                         0x50
126 
127 #define MXS_DCP_CH_N_CMDPTR(n)                  (0x100 + ((n) * 0x40))
128 
129 #define MXS_DCP_CH_N_SEMA(n)                    (0x110 + ((n) * 0x40))
130 
131 #define MXS_DCP_CH_N_STAT(n)                    (0x120 + ((n) * 0x40))
132 #define MXS_DCP_CH_N_STAT_CLR(n)                (0x128 + ((n) * 0x40))
133 
134 /* DMA descriptor bits. */
135 #define MXS_DCP_CONTROL0_HASH_TERM              (1 << 13)
136 #define MXS_DCP_CONTROL0_HASH_INIT              (1 << 12)
137 #define MXS_DCP_CONTROL0_PAYLOAD_KEY            (1 << 11)
138 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT         (1 << 8)
139 #define MXS_DCP_CONTROL0_CIPHER_INIT            (1 << 9)
140 #define MXS_DCP_CONTROL0_ENABLE_HASH            (1 << 6)
141 #define MXS_DCP_CONTROL0_ENABLE_CIPHER          (1 << 5)
142 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE         (1 << 1)
143 #define MXS_DCP_CONTROL0_INTERRUPT              (1 << 0)
144 
145 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256     (2 << 16)
146 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1       (0 << 16)
147 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC        (1 << 4)
148 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB        (0 << 4)
149 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128   (0 << 0)
150 
151 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
152 {
153         struct dcp *sdcp = global_sdcp;
154         const int chan = actx->chan;
155         uint32_t stat;
156         unsigned long ret;
157         struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
158 
159         dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
160                                               DMA_TO_DEVICE);
161 
162         reinit_completion(&sdcp->completion[chan]);
163 
164         /* Clear status register. */
165         writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
166 
167         /* Load the DMA descriptor. */
168         writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
169 
170         /* Increment the semaphore to start the DMA transfer. */
171         writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
172 
173         ret = wait_for_completion_timeout(&sdcp->completion[chan],
174                                           msecs_to_jiffies(1000));
175         if (!ret) {
176                 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
177                         chan, readl(sdcp->base + MXS_DCP_STAT));
178                 return -ETIMEDOUT;
179         }
180 
181         stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
182         if (stat & 0xff) {
183                 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
184                         chan, stat);
185                 return -EINVAL;
186         }
187 
188         dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
189 
190         return 0;
191 }
192 
193 /*
194  * Encryption (AES128)
195  */
196 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
197                            struct ablkcipher_request *req, int init)
198 {
199         struct dcp *sdcp = global_sdcp;
200         struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
201         struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
202         int ret;
203 
204         dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
205                                              2 * AES_KEYSIZE_128,
206                                              DMA_TO_DEVICE);
207         dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
208                                              DCP_BUF_SZ, DMA_TO_DEVICE);
209         dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
210                                              DCP_BUF_SZ, DMA_FROM_DEVICE);
211 
212         /* Fill in the DMA descriptor. */
213         desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
214                     MXS_DCP_CONTROL0_INTERRUPT |
215                     MXS_DCP_CONTROL0_ENABLE_CIPHER;
216 
217         /* Payload contains the key. */
218         desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
219 
220         if (rctx->enc)
221                 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
222         if (init)
223                 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
224 
225         desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
226 
227         if (rctx->ecb)
228                 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
229         else
230                 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
231 
232         desc->next_cmd_addr = 0;
233         desc->source = src_phys;
234         desc->destination = dst_phys;
235         desc->size = actx->fill;
236         desc->payload = key_phys;
237         desc->status = 0;
238 
239         ret = mxs_dcp_start_dma(actx);
240 
241         dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
242                          DMA_TO_DEVICE);
243         dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
244         dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
245 
246         return ret;
247 }
248 
249 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
250 {
251         struct dcp *sdcp = global_sdcp;
252 
253         struct ablkcipher_request *req = ablkcipher_request_cast(arq);
254         struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
255         struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
256 
257         struct scatterlist *dst = req->dst;
258         struct scatterlist *src = req->src;
259         const int nents = sg_nents(req->src);
260 
261         const int out_off = DCP_BUF_SZ;
262         uint8_t *in_buf = sdcp->coh->aes_in_buf;
263         uint8_t *out_buf = sdcp->coh->aes_out_buf;
264 
265         uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
266         uint32_t dst_off = 0;
267 
268         uint8_t *key = sdcp->coh->aes_key;
269 
270         int ret = 0;
271         int split = 0;
272         unsigned int i, len, clen, rem = 0;
273         int init = 0;
274 
275         actx->fill = 0;
276 
277         /* Copy the key from the temporary location. */
278         memcpy(key, actx->key, actx->key_len);
279 
280         if (!rctx->ecb) {
281                 /* Copy the CBC IV just past the key. */
282                 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
283                 /* CBC needs the INIT set. */
284                 init = 1;
285         } else {
286                 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
287         }
288 
289         for_each_sg(req->src, src, nents, i) {
290                 src_buf = sg_virt(src);
291                 len = sg_dma_len(src);
292 
293                 do {
294                         if (actx->fill + len > out_off)
295                                 clen = out_off - actx->fill;
296                         else
297                                 clen = len;
298 
299                         memcpy(in_buf + actx->fill, src_buf, clen);
300                         len -= clen;
301                         src_buf += clen;
302                         actx->fill += clen;
303 
304                         /*
305                          * If we filled the buffer or this is the last SG,
306                          * submit the buffer.
307                          */
308                         if (actx->fill == out_off || sg_is_last(src)) {
309                                 ret = mxs_dcp_run_aes(actx, req, init);
310                                 if (ret)
311                                         return ret;
312                                 init = 0;
313 
314                                 out_tmp = out_buf;
315                                 while (dst && actx->fill) {
316                                         if (!split) {
317                                                 dst_buf = sg_virt(dst);
318                                                 dst_off = 0;
319                                         }
320                                         rem = min(sg_dma_len(dst) - dst_off,
321                                                   actx->fill);
322 
323                                         memcpy(dst_buf + dst_off, out_tmp, rem);
324                                         out_tmp += rem;
325                                         dst_off += rem;
326                                         actx->fill -= rem;
327 
328                                         if (dst_off == sg_dma_len(dst)) {
329                                                 dst = sg_next(dst);
330                                                 split = 0;
331                                         } else {
332                                                 split = 1;
333                                         }
334                                 }
335                         }
336                 } while (len);
337         }
338 
339         return ret;
340 }
341 
342 static int dcp_chan_thread_aes(void *data)
343 {
344         struct dcp *sdcp = global_sdcp;
345         const int chan = DCP_CHAN_CRYPTO;
346 
347         struct crypto_async_request *backlog;
348         struct crypto_async_request *arq;
349 
350         int ret;
351 
352         do {
353                 __set_current_state(TASK_INTERRUPTIBLE);
354 
355                 mutex_lock(&sdcp->mutex[chan]);
356                 backlog = crypto_get_backlog(&sdcp->queue[chan]);
357                 arq = crypto_dequeue_request(&sdcp->queue[chan]);
358                 mutex_unlock(&sdcp->mutex[chan]);
359 
360                 if (backlog)
361                         backlog->complete(backlog, -EINPROGRESS);
362 
363                 if (arq) {
364                         ret = mxs_dcp_aes_block_crypt(arq);
365                         arq->complete(arq, ret);
366                         continue;
367                 }
368 
369                 schedule();
370         } while (!kthread_should_stop());
371 
372         return 0;
373 }
374 
375 static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
376 {
377         struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
378         struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(tfm);
379         SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
380         int ret;
381 
382         skcipher_request_set_tfm(subreq, ctx->fallback);
383         skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
384         skcipher_request_set_crypt(subreq, req->src, req->dst,
385                                    req->nbytes, req->info);
386 
387         if (enc)
388                 ret = crypto_skcipher_encrypt(subreq);
389         else
390                 ret = crypto_skcipher_decrypt(subreq);
391 
392         skcipher_request_zero(subreq);
393 
394         return ret;
395 }
396 
397 static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
398 {
399         struct dcp *sdcp = global_sdcp;
400         struct crypto_async_request *arq = &req->base;
401         struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
402         struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
403         int ret;
404 
405         if (unlikely(actx->key_len != AES_KEYSIZE_128))
406                 return mxs_dcp_block_fallback(req, enc);
407 
408         rctx->enc = enc;
409         rctx->ecb = ecb;
410         actx->chan = DCP_CHAN_CRYPTO;
411 
412         mutex_lock(&sdcp->mutex[actx->chan]);
413         ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
414         mutex_unlock(&sdcp->mutex[actx->chan]);
415 
416         wake_up_process(sdcp->thread[actx->chan]);
417 
418         return -EINPROGRESS;
419 }
420 
421 static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
422 {
423         return mxs_dcp_aes_enqueue(req, 0, 1);
424 }
425 
426 static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
427 {
428         return mxs_dcp_aes_enqueue(req, 1, 1);
429 }
430 
431 static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
432 {
433         return mxs_dcp_aes_enqueue(req, 0, 0);
434 }
435 
436 static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
437 {
438         return mxs_dcp_aes_enqueue(req, 1, 0);
439 }
440 
441 static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
442                               unsigned int len)
443 {
444         struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
445         unsigned int ret;
446 
447         /*
448          * AES 128 is supposed by the hardware, store key into temporary
449          * buffer and exit. We must use the temporary buffer here, since
450          * there can still be an operation in progress.
451          */
452         actx->key_len = len;
453         if (len == AES_KEYSIZE_128) {
454                 memcpy(actx->key, key, len);
455                 return 0;
456         }
457 
458         /*
459          * If the requested AES key size is not supported by the hardware,
460          * but is supported by in-kernel software implementation, we use
461          * software fallback.
462          */
463         crypto_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
464         crypto_skcipher_set_flags(actx->fallback,
465                                   tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
466 
467         ret = crypto_skcipher_setkey(actx->fallback, key, len);
468         if (!ret)
469                 return 0;
470 
471         tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
472         tfm->base.crt_flags |= crypto_skcipher_get_flags(actx->fallback) &
473                                CRYPTO_TFM_RES_MASK;
474 
475         return ret;
476 }
477 
478 static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
479 {
480         const char *name = crypto_tfm_alg_name(tfm);
481         const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
482         struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
483         struct crypto_skcipher *blk;
484 
485         blk = crypto_alloc_skcipher(name, 0, flags);
486         if (IS_ERR(blk))
487                 return PTR_ERR(blk);
488 
489         actx->fallback = blk;
490         tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
491         return 0;
492 }
493 
494 static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
495 {
496         struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
497 
498         crypto_free_skcipher(actx->fallback);
499 }
500 
501 /*
502  * Hashing (SHA1/SHA256)
503  */
504 static int mxs_dcp_run_sha(struct ahash_request *req)
505 {
506         struct dcp *sdcp = global_sdcp;
507         int ret;
508 
509         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
510         struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
511         struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
512         struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
513 
514         struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
515 
516         dma_addr_t digest_phys = 0;
517         dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
518                                              DCP_BUF_SZ, DMA_TO_DEVICE);
519 
520         /* Fill in the DMA descriptor. */
521         desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
522                     MXS_DCP_CONTROL0_INTERRUPT |
523                     MXS_DCP_CONTROL0_ENABLE_HASH;
524         if (rctx->init)
525                 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
526 
527         desc->control1 = actx->alg;
528         desc->next_cmd_addr = 0;
529         desc->source = buf_phys;
530         desc->destination = 0;
531         desc->size = actx->fill;
532         desc->payload = 0;
533         desc->status = 0;
534 
535         /* Set HASH_TERM bit for last transfer block. */
536         if (rctx->fini) {
537                 digest_phys = dma_map_single(sdcp->dev, req->result,
538                                              halg->digestsize, DMA_FROM_DEVICE);
539                 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
540                 desc->payload = digest_phys;
541         }
542 
543         ret = mxs_dcp_start_dma(actx);
544 
545         if (rctx->fini)
546                 dma_unmap_single(sdcp->dev, digest_phys, halg->digestsize,
547                                  DMA_FROM_DEVICE);
548 
549         dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
550 
551         return ret;
552 }
553 
554 static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
555 {
556         struct dcp *sdcp = global_sdcp;
557 
558         struct ahash_request *req = ahash_request_cast(arq);
559         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
560         struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
561         struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
562         struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
563         const int nents = sg_nents(req->src);
564 
565         uint8_t *in_buf = sdcp->coh->sha_in_buf;
566 
567         uint8_t *src_buf;
568 
569         struct scatterlist *src;
570 
571         unsigned int i, len, clen;
572         int ret;
573 
574         int fin = rctx->fini;
575         if (fin)
576                 rctx->fini = 0;
577 
578         for_each_sg(req->src, src, nents, i) {
579                 src_buf = sg_virt(src);
580                 len = sg_dma_len(src);
581 
582                 do {
583                         if (actx->fill + len > DCP_BUF_SZ)
584                                 clen = DCP_BUF_SZ - actx->fill;
585                         else
586                                 clen = len;
587 
588                         memcpy(in_buf + actx->fill, src_buf, clen);
589                         len -= clen;
590                         src_buf += clen;
591                         actx->fill += clen;
592 
593                         /*
594                          * If we filled the buffer and still have some
595                          * more data, submit the buffer.
596                          */
597                         if (len && actx->fill == DCP_BUF_SZ) {
598                                 ret = mxs_dcp_run_sha(req);
599                                 if (ret)
600                                         return ret;
601                                 actx->fill = 0;
602                                 rctx->init = 0;
603                         }
604                 } while (len);
605         }
606 
607         if (fin) {
608                 rctx->fini = 1;
609 
610                 /* Submit whatever is left. */
611                 if (!req->result)
612                         return -EINVAL;
613 
614                 ret = mxs_dcp_run_sha(req);
615                 if (ret)
616                         return ret;
617 
618                 actx->fill = 0;
619 
620                 /* For some reason, the result is flipped. */
621                 for (i = 0; i < halg->digestsize / 2; i++) {
622                         swap(req->result[i],
623                              req->result[halg->digestsize - i - 1]);
624                 }
625         }
626 
627         return 0;
628 }
629 
630 static int dcp_chan_thread_sha(void *data)
631 {
632         struct dcp *sdcp = global_sdcp;
633         const int chan = DCP_CHAN_HASH_SHA;
634 
635         struct crypto_async_request *backlog;
636         struct crypto_async_request *arq;
637 
638         struct dcp_sha_req_ctx *rctx;
639 
640         struct ahash_request *req;
641         int ret, fini;
642 
643         do {
644                 __set_current_state(TASK_INTERRUPTIBLE);
645 
646                 mutex_lock(&sdcp->mutex[chan]);
647                 backlog = crypto_get_backlog(&sdcp->queue[chan]);
648                 arq = crypto_dequeue_request(&sdcp->queue[chan]);
649                 mutex_unlock(&sdcp->mutex[chan]);
650 
651                 if (backlog)
652                         backlog->complete(backlog, -EINPROGRESS);
653 
654                 if (arq) {
655                         req = ahash_request_cast(arq);
656                         rctx = ahash_request_ctx(req);
657 
658                         ret = dcp_sha_req_to_buf(arq);
659                         fini = rctx->fini;
660                         arq->complete(arq, ret);
661                         if (!fini)
662                                 continue;
663                 }
664 
665                 schedule();
666         } while (!kthread_should_stop());
667 
668         return 0;
669 }
670 
671 static int dcp_sha_init(struct ahash_request *req)
672 {
673         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
674         struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
675 
676         struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
677 
678         /*
679          * Start hashing session. The code below only inits the
680          * hashing session context, nothing more.
681          */
682         memset(actx, 0, sizeof(*actx));
683 
684         if (strcmp(halg->base.cra_name, "sha1") == 0)
685                 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
686         else
687                 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
688 
689         actx->fill = 0;
690         actx->hot = 0;
691         actx->chan = DCP_CHAN_HASH_SHA;
692 
693         mutex_init(&actx->mutex);
694 
695         return 0;
696 }
697 
698 static int dcp_sha_update_fx(struct ahash_request *req, int fini)
699 {
700         struct dcp *sdcp = global_sdcp;
701 
702         struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
703         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
704         struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
705 
706         int ret;
707 
708         /*
709          * Ignore requests that have no data in them and are not
710          * the trailing requests in the stream of requests.
711          */
712         if (!req->nbytes && !fini)
713                 return 0;
714 
715         mutex_lock(&actx->mutex);
716 
717         rctx->fini = fini;
718 
719         if (!actx->hot) {
720                 actx->hot = 1;
721                 rctx->init = 1;
722         }
723 
724         mutex_lock(&sdcp->mutex[actx->chan]);
725         ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
726         mutex_unlock(&sdcp->mutex[actx->chan]);
727 
728         wake_up_process(sdcp->thread[actx->chan]);
729         mutex_unlock(&actx->mutex);
730 
731         return -EINPROGRESS;
732 }
733 
734 static int dcp_sha_update(struct ahash_request *req)
735 {
736         return dcp_sha_update_fx(req, 0);
737 }
738 
739 static int dcp_sha_final(struct ahash_request *req)
740 {
741         ahash_request_set_crypt(req, NULL, req->result, 0);
742         req->nbytes = 0;
743         return dcp_sha_update_fx(req, 1);
744 }
745 
746 static int dcp_sha_finup(struct ahash_request *req)
747 {
748         return dcp_sha_update_fx(req, 1);
749 }
750 
751 static int dcp_sha_digest(struct ahash_request *req)
752 {
753         int ret;
754 
755         ret = dcp_sha_init(req);
756         if (ret)
757                 return ret;
758 
759         return dcp_sha_finup(req);
760 }
761 
762 static int dcp_sha_cra_init(struct crypto_tfm *tfm)
763 {
764         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
765                                  sizeof(struct dcp_sha_req_ctx));
766         return 0;
767 }
768 
769 static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
770 {
771 }
772 
773 /* AES 128 ECB and AES 128 CBC */
774 static struct crypto_alg dcp_aes_algs[] = {
775         {
776                 .cra_name               = "ecb(aes)",
777                 .cra_driver_name        = "ecb-aes-dcp",
778                 .cra_priority           = 400,
779                 .cra_alignmask          = 15,
780                 .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
781                                           CRYPTO_ALG_ASYNC |
782                                           CRYPTO_ALG_NEED_FALLBACK,
783                 .cra_init               = mxs_dcp_aes_fallback_init,
784                 .cra_exit               = mxs_dcp_aes_fallback_exit,
785                 .cra_blocksize          = AES_BLOCK_SIZE,
786                 .cra_ctxsize            = sizeof(struct dcp_async_ctx),
787                 .cra_type               = &crypto_ablkcipher_type,
788                 .cra_module             = THIS_MODULE,
789                 .cra_u  = {
790                         .ablkcipher = {
791                                 .min_keysize    = AES_MIN_KEY_SIZE,
792                                 .max_keysize    = AES_MAX_KEY_SIZE,
793                                 .setkey         = mxs_dcp_aes_setkey,
794                                 .encrypt        = mxs_dcp_aes_ecb_encrypt,
795                                 .decrypt        = mxs_dcp_aes_ecb_decrypt
796                         },
797                 },
798         }, {
799                 .cra_name               = "cbc(aes)",
800                 .cra_driver_name        = "cbc-aes-dcp",
801                 .cra_priority           = 400,
802                 .cra_alignmask          = 15,
803                 .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
804                                           CRYPTO_ALG_ASYNC |
805                                           CRYPTO_ALG_NEED_FALLBACK,
806                 .cra_init               = mxs_dcp_aes_fallback_init,
807                 .cra_exit               = mxs_dcp_aes_fallback_exit,
808                 .cra_blocksize          = AES_BLOCK_SIZE,
809                 .cra_ctxsize            = sizeof(struct dcp_async_ctx),
810                 .cra_type               = &crypto_ablkcipher_type,
811                 .cra_module             = THIS_MODULE,
812                 .cra_u = {
813                         .ablkcipher = {
814                                 .min_keysize    = AES_MIN_KEY_SIZE,
815                                 .max_keysize    = AES_MAX_KEY_SIZE,
816                                 .setkey         = mxs_dcp_aes_setkey,
817                                 .encrypt        = mxs_dcp_aes_cbc_encrypt,
818                                 .decrypt        = mxs_dcp_aes_cbc_decrypt,
819                                 .ivsize         = AES_BLOCK_SIZE,
820                         },
821                 },
822         },
823 };
824 
825 /* SHA1 */
826 static struct ahash_alg dcp_sha1_alg = {
827         .init   = dcp_sha_init,
828         .update = dcp_sha_update,
829         .final  = dcp_sha_final,
830         .finup  = dcp_sha_finup,
831         .digest = dcp_sha_digest,
832         .halg   = {
833                 .digestsize     = SHA1_DIGEST_SIZE,
834                 .base           = {
835                         .cra_name               = "sha1",
836                         .cra_driver_name        = "sha1-dcp",
837                         .cra_priority           = 400,
838                         .cra_alignmask          = 63,
839                         .cra_flags              = CRYPTO_ALG_ASYNC,
840                         .cra_blocksize          = SHA1_BLOCK_SIZE,
841                         .cra_ctxsize            = sizeof(struct dcp_async_ctx),
842                         .cra_module             = THIS_MODULE,
843                         .cra_init               = dcp_sha_cra_init,
844                         .cra_exit               = dcp_sha_cra_exit,
845                 },
846         },
847 };
848 
849 /* SHA256 */
850 static struct ahash_alg dcp_sha256_alg = {
851         .init   = dcp_sha_init,
852         .update = dcp_sha_update,
853         .final  = dcp_sha_final,
854         .finup  = dcp_sha_finup,
855         .digest = dcp_sha_digest,
856         .halg   = {
857                 .digestsize     = SHA256_DIGEST_SIZE,
858                 .base           = {
859                         .cra_name               = "sha256",
860                         .cra_driver_name        = "sha256-dcp",
861                         .cra_priority           = 400,
862                         .cra_alignmask          = 63,
863                         .cra_flags              = CRYPTO_ALG_ASYNC,
864                         .cra_blocksize          = SHA256_BLOCK_SIZE,
865                         .cra_ctxsize            = sizeof(struct dcp_async_ctx),
866                         .cra_module             = THIS_MODULE,
867                         .cra_init               = dcp_sha_cra_init,
868                         .cra_exit               = dcp_sha_cra_exit,
869                 },
870         },
871 };
872 
873 static irqreturn_t mxs_dcp_irq(int irq, void *context)
874 {
875         struct dcp *sdcp = context;
876         uint32_t stat;
877         int i;
878 
879         stat = readl(sdcp->base + MXS_DCP_STAT);
880         stat &= MXS_DCP_STAT_IRQ_MASK;
881         if (!stat)
882                 return IRQ_NONE;
883 
884         /* Clear the interrupts. */
885         writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
886 
887         /* Complete the DMA requests that finished. */
888         for (i = 0; i < DCP_MAX_CHANS; i++)
889                 if (stat & (1 << i))
890                         complete(&sdcp->completion[i]);
891 
892         return IRQ_HANDLED;
893 }
894 
895 static int mxs_dcp_probe(struct platform_device *pdev)
896 {
897         struct device *dev = &pdev->dev;
898         struct dcp *sdcp = NULL;
899         int i, ret;
900 
901         struct resource *iores;
902         int dcp_vmi_irq, dcp_irq;
903 
904         if (global_sdcp) {
905                 dev_err(dev, "Only one DCP instance allowed!\n");
906                 return -ENODEV;
907         }
908 
909         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910         dcp_vmi_irq = platform_get_irq(pdev, 0);
911         if (dcp_vmi_irq < 0)
912                 return dcp_vmi_irq;
913 
914         dcp_irq = platform_get_irq(pdev, 1);
915         if (dcp_irq < 0)
916                 return dcp_irq;
917 
918         sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
919         if (!sdcp)
920                 return -ENOMEM;
921 
922         sdcp->dev = dev;
923         sdcp->base = devm_ioremap_resource(dev, iores);
924         if (IS_ERR(sdcp->base))
925                 return PTR_ERR(sdcp->base);
926 
927 
928         ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
929                                "dcp-vmi-irq", sdcp);
930         if (ret) {
931                 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
932                 return ret;
933         }
934 
935         ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
936                                "dcp-irq", sdcp);
937         if (ret) {
938                 dev_err(dev, "Failed to claim DCP IRQ!\n");
939                 return ret;
940         }
941 
942         /* Allocate coherent helper block. */
943         sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
944                                    GFP_KERNEL);
945         if (!sdcp->coh)
946                 return -ENOMEM;
947 
948         /* Re-align the structure so it fits the DCP constraints. */
949         sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
950 
951         /* Restart the DCP block. */
952         ret = stmp_reset_block(sdcp->base);
953         if (ret)
954                 return ret;
955 
956         /* Initialize control register. */
957         writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
958                MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
959                sdcp->base + MXS_DCP_CTRL);
960 
961         /* Enable all DCP DMA channels. */
962         writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
963                sdcp->base + MXS_DCP_CHANNELCTRL);
964 
965         /*
966          * We do not enable context switching. Give the context buffer a
967          * pointer to an illegal address so if context switching is
968          * inadvertantly enabled, the DCP will return an error instead of
969          * trashing good memory. The DCP DMA cannot access ROM, so any ROM
970          * address will do.
971          */
972         writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
973         for (i = 0; i < DCP_MAX_CHANS; i++)
974                 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
975         writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
976 
977         global_sdcp = sdcp;
978 
979         platform_set_drvdata(pdev, sdcp);
980 
981         for (i = 0; i < DCP_MAX_CHANS; i++) {
982                 mutex_init(&sdcp->mutex[i]);
983                 init_completion(&sdcp->completion[i]);
984                 crypto_init_queue(&sdcp->queue[i], 50);
985         }
986 
987         /* Create the SHA and AES handler threads. */
988         sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
989                                                       NULL, "mxs_dcp_chan/sha");
990         if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
991                 dev_err(dev, "Error starting SHA thread!\n");
992                 return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
993         }
994 
995         sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
996                                                     NULL, "mxs_dcp_chan/aes");
997         if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
998                 dev_err(dev, "Error starting SHA thread!\n");
999                 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1000                 goto err_destroy_sha_thread;
1001         }
1002 
1003         /* Register the various crypto algorithms. */
1004         sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1005 
1006         if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1007                 ret = crypto_register_algs(dcp_aes_algs,
1008                                            ARRAY_SIZE(dcp_aes_algs));
1009                 if (ret) {
1010                         /* Failed to register algorithm. */
1011                         dev_err(dev, "Failed to register AES crypto!\n");
1012                         goto err_destroy_aes_thread;
1013                 }
1014         }
1015 
1016         if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1017                 ret = crypto_register_ahash(&dcp_sha1_alg);
1018                 if (ret) {
1019                         dev_err(dev, "Failed to register %s hash!\n",
1020                                 dcp_sha1_alg.halg.base.cra_name);
1021                         goto err_unregister_aes;
1022                 }
1023         }
1024 
1025         if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1026                 ret = crypto_register_ahash(&dcp_sha256_alg);
1027                 if (ret) {
1028                         dev_err(dev, "Failed to register %s hash!\n",
1029                                 dcp_sha256_alg.halg.base.cra_name);
1030                         goto err_unregister_sha1;
1031                 }
1032         }
1033 
1034         return 0;
1035 
1036 err_unregister_sha1:
1037         if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1038                 crypto_unregister_ahash(&dcp_sha1_alg);
1039 
1040 err_unregister_aes:
1041         if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1042                 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1043 
1044 err_destroy_aes_thread:
1045         kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1046 
1047 err_destroy_sha_thread:
1048         kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1049         return ret;
1050 }
1051 
1052 static int mxs_dcp_remove(struct platform_device *pdev)
1053 {
1054         struct dcp *sdcp = platform_get_drvdata(pdev);
1055 
1056         if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1057                 crypto_unregister_ahash(&dcp_sha256_alg);
1058 
1059         if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1060                 crypto_unregister_ahash(&dcp_sha1_alg);
1061 
1062         if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1063                 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1064 
1065         kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1066         kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1067 
1068         platform_set_drvdata(pdev, NULL);
1069 
1070         global_sdcp = NULL;
1071 
1072         return 0;
1073 }
1074 
1075 static const struct of_device_id mxs_dcp_dt_ids[] = {
1076         { .compatible = "fsl,imx23-dcp", .data = NULL, },
1077         { .compatible = "fsl,imx28-dcp", .data = NULL, },
1078         { /* sentinel */ }
1079 };
1080 
1081 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1082 
1083 static struct platform_driver mxs_dcp_driver = {
1084         .probe  = mxs_dcp_probe,
1085         .remove = mxs_dcp_remove,
1086         .driver = {
1087                 .name           = "mxs-dcp",
1088                 .of_match_table = mxs_dcp_dt_ids,
1089         },
1090 };
1091 
1092 module_platform_driver(mxs_dcp_driver);
1093 
1094 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1095 MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1096 MODULE_LICENSE("GPL");
1097 MODULE_ALIAS("platform:mxs-dcp");
1098 

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