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Linux/drivers/cpufreq/intel_pstate.c

  1 /*
  2  * intel_pstate.c: Native P state management for Intel processors
  3  *
  4  * (C) Copyright 2012 Intel Corporation
  5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
  6  *
  7  * This program is free software; you can redistribute it and/or
  8  * modify it under the terms of the GNU General Public License
  9  * as published by the Free Software Foundation; version 2
 10  * of the License.
 11  */
 12 
 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/kernel_stat.h>
 17 #include <linux/module.h>
 18 #include <linux/ktime.h>
 19 #include <linux/hrtimer.h>
 20 #include <linux/tick.h>
 21 #include <linux/slab.h>
 22 #include <linux/sched.h>
 23 #include <linux/list.h>
 24 #include <linux/cpu.h>
 25 #include <linux/cpufreq.h>
 26 #include <linux/sysfs.h>
 27 #include <linux/types.h>
 28 #include <linux/fs.h>
 29 #include <linux/debugfs.h>
 30 #include <linux/acpi.h>
 31 #include <linux/vmalloc.h>
 32 #include <trace/events/power.h>
 33 
 34 #include <asm/div64.h>
 35 #include <asm/msr.h>
 36 #include <asm/cpu_device_id.h>
 37 #include <asm/cpufeature.h>
 38 #include <asm/intel-family.h>
 39 
 40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
 41 
 42 #define ATOM_RATIOS             0x66a
 43 #define ATOM_VIDS               0x66b
 44 #define ATOM_TURBO_RATIOS       0x66c
 45 #define ATOM_TURBO_VIDS         0x66d
 46 
 47 #ifdef CONFIG_ACPI
 48 #include <acpi/processor.h>
 49 #include <acpi/cppc_acpi.h>
 50 #endif
 51 
 52 #define FRAC_BITS 8
 53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
 54 #define fp_toint(X) ((X) >> FRAC_BITS)
 55 
 56 #define EXT_BITS 6
 57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
 58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
 59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
 60 
 61 static inline int32_t mul_fp(int32_t x, int32_t y)
 62 {
 63         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
 64 }
 65 
 66 static inline int32_t div_fp(s64 x, s64 y)
 67 {
 68         return div64_s64((int64_t)x << FRAC_BITS, y);
 69 }
 70 
 71 static inline int ceiling_fp(int32_t x)
 72 {
 73         int mask, ret;
 74 
 75         ret = fp_toint(x);
 76         mask = (1 << FRAC_BITS) - 1;
 77         if (x & mask)
 78                 ret += 1;
 79         return ret;
 80 }
 81 
 82 static inline u64 mul_ext_fp(u64 x, u64 y)
 83 {
 84         return (x * y) >> EXT_FRAC_BITS;
 85 }
 86 
 87 static inline u64 div_ext_fp(u64 x, u64 y)
 88 {
 89         return div64_u64(x << EXT_FRAC_BITS, y);
 90 }
 91 
 92 /**
 93  * struct sample -      Store performance sample
 94  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
 95  *                      performance during last sample period
 96  * @busy_scaled:        Scaled busy value which is used to calculate next
 97  *                      P state. This can be different than core_avg_perf
 98  *                      to account for cpu idle period
 99  * @aperf:              Difference of actual performance frequency clock count
100  *                      read from APERF MSR between last and current sample
101  * @mperf:              Difference of maximum performance frequency clock count
102  *                      read from MPERF MSR between last and current sample
103  * @tsc:                Difference of time stamp counter between last and
104  *                      current sample
105  * @time:               Current time from scheduler
106  *
107  * This structure is used in the cpudata structure to store performance sample
108  * data for choosing next P State.
109  */
110 struct sample {
111         int32_t core_avg_perf;
112         int32_t busy_scaled;
113         u64 aperf;
114         u64 mperf;
115         u64 tsc;
116         u64 time;
117 };
118 
119 /**
120  * struct pstate_data - Store P state data
121  * @current_pstate:     Current requested P state
122  * @min_pstate:         Min P state possible for this platform
123  * @max_pstate:         Max P state possible for this platform
124  * @max_pstate_physical:This is physical Max P state for a processor
125  *                      This can be higher than the max_pstate which can
126  *                      be limited by platform thermal design power limits
127  * @scaling:            Scaling factor to  convert frequency to cpufreq
128  *                      frequency units
129  * @turbo_pstate:       Max Turbo P state possible for this platform
130  * @max_freq:           @max_pstate frequency in cpufreq units
131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
132  *
133  * Stores the per cpu model P state limits and current P state.
134  */
135 struct pstate_data {
136         int     current_pstate;
137         int     min_pstate;
138         int     max_pstate;
139         int     max_pstate_physical;
140         int     scaling;
141         int     turbo_pstate;
142         unsigned int max_freq;
143         unsigned int turbo_freq;
144 };
145 
146 /**
147  * struct vid_data -    Stores voltage information data
148  * @min:                VID data for this platform corresponding to
149  *                      the lowest P state
150  * @max:                VID data corresponding to the highest P State.
151  * @turbo:              VID data for turbo P state
152  * @ratio:              Ratio of (vid max - vid min) /
153  *                      (max P state - Min P State)
154  *
155  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
156  * This data is used in Atom platforms, where in addition to target P state,
157  * the voltage data needs to be specified to select next P State.
158  */
159 struct vid_data {
160         int min;
161         int max;
162         int turbo;
163         int32_t ratio;
164 };
165 
166 /**
167  * struct _pid -        Stores PID data
168  * @setpoint:           Target set point for busyness or performance
169  * @integral:           Storage for accumulated error values
170  * @p_gain:             PID proportional gain
171  * @i_gain:             PID integral gain
172  * @d_gain:             PID derivative gain
173  * @deadband:           PID deadband
174  * @last_err:           Last error storage for integral part of PID calculation
175  *
176  * Stores PID coefficients and last error for PID controller.
177  */
178 struct _pid {
179         int setpoint;
180         int32_t integral;
181         int32_t p_gain;
182         int32_t i_gain;
183         int32_t d_gain;
184         int deadband;
185         int32_t last_err;
186 };
187 
188 /**
189  * struct perf_limits - Store user and policy limits
190  * @no_turbo:           User requested turbo state from intel_pstate sysfs
191  * @turbo_disabled:     Platform turbo status either from msr
192  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
193  *                      matches the maximum turbo pstate
194  * @max_perf_pct:       Effective maximum performance limit in percentage, this
195  *                      is minimum of either limits enforced by cpufreq policy
196  *                      or limits from user set limits via intel_pstate sysfs
197  * @min_perf_pct:       Effective minimum performance limit in percentage, this
198  *                      is maximum of either limits enforced by cpufreq policy
199  *                      or limits from user set limits via intel_pstate sysfs
200  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
201  *                      This value is used to limit max pstate
202  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
203  *                      This value is used to limit min pstate
204  * @max_policy_pct:     The maximum performance in percentage enforced by
205  *                      cpufreq setpolicy interface
206  * @max_sysfs_pct:      The maximum performance in percentage enforced by
207  *                      intel pstate sysfs interface, unused when per cpu
208  *                      controls are enforced
209  * @min_policy_pct:     The minimum performance in percentage enforced by
210  *                      cpufreq setpolicy interface
211  * @min_sysfs_pct:      The minimum performance in percentage enforced by
212  *                      intel pstate sysfs interface, unused when per cpu
213  *                      controls are enforced
214  *
215  * Storage for user and policy defined limits.
216  */
217 struct perf_limits {
218         int no_turbo;
219         int turbo_disabled;
220         int max_perf_pct;
221         int min_perf_pct;
222         int32_t max_perf;
223         int32_t min_perf;
224         int max_policy_pct;
225         int max_sysfs_pct;
226         int min_policy_pct;
227         int min_sysfs_pct;
228 };
229 
230 /**
231  * struct cpudata -     Per CPU instance data storage
232  * @cpu:                CPU number for this instance data
233  * @policy:             CPUFreq policy value
234  * @update_util:        CPUFreq utility callback information
235  * @update_util_set:    CPUFreq utility callback is set
236  * @iowait_boost:       iowait-related boost fraction
237  * @last_update:        Time of the last update.
238  * @pstate:             Stores P state limits for this CPU
239  * @vid:                Stores VID limits for this CPU
240  * @pid:                Stores PID parameters for this CPU
241  * @last_sample_time:   Last Sample time
242  * @prev_aperf:         Last APERF value read from APERF MSR
243  * @prev_mperf:         Last MPERF value read from MPERF MSR
244  * @prev_tsc:           Last timestamp counter (TSC) value
245  * @prev_cummulative_iowait: IO Wait time difference from last and
246  *                      current sample
247  * @sample:             Storage for storing last Sample data
248  * @perf_limits:        Pointer to perf_limit unique to this CPU
249  *                      Not all field in the structure are applicable
250  *                      when per cpu controls are enforced
251  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
252  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
253  * @epp_powersave:      Last saved HWP energy performance preference
254  *                      (EPP) or energy performance bias (EPB),
255  *                      when policy switched to performance
256  * @epp_policy:         Last saved policy used to set EPP/EPB
257  * @epp_default:        Power on default HWP energy performance
258  *                      preference/bias
259  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
260  *                      operation
261  *
262  * This structure stores per CPU instance data for all CPUs.
263  */
264 struct cpudata {
265         int cpu;
266 
267         unsigned int policy;
268         struct update_util_data update_util;
269         bool   update_util_set;
270 
271         struct pstate_data pstate;
272         struct vid_data vid;
273         struct _pid pid;
274 
275         u64     last_update;
276         u64     last_sample_time;
277         u64     prev_aperf;
278         u64     prev_mperf;
279         u64     prev_tsc;
280         u64     prev_cummulative_iowait;
281         struct sample sample;
282         struct perf_limits *perf_limits;
283 #ifdef CONFIG_ACPI
284         struct acpi_processor_performance acpi_perf_data;
285         bool valid_pss_table;
286 #endif
287         unsigned int iowait_boost;
288         s16 epp_powersave;
289         s16 epp_policy;
290         s16 epp_default;
291         s16 epp_saved;
292 };
293 
294 static struct cpudata **all_cpu_data;
295 
296 /**
297  * struct pstate_adjust_policy - Stores static PID configuration data
298  * @sample_rate_ms:     PID calculation sample rate in ms
299  * @sample_rate_ns:     Sample rate calculation in ns
300  * @deadband:           PID deadband
301  * @setpoint:           PID Setpoint
302  * @p_gain_pct:         PID proportional gain
303  * @i_gain_pct:         PID integral gain
304  * @d_gain_pct:         PID derivative gain
305  *
306  * Stores per CPU model static PID configuration data.
307  */
308 struct pstate_adjust_policy {
309         int sample_rate_ms;
310         s64 sample_rate_ns;
311         int deadband;
312         int setpoint;
313         int p_gain_pct;
314         int d_gain_pct;
315         int i_gain_pct;
316 };
317 
318 /**
319  * struct pstate_funcs - Per CPU model specific callbacks
320  * @get_max:            Callback to get maximum non turbo effective P state
321  * @get_max_physical:   Callback to get maximum non turbo physical P state
322  * @get_min:            Callback to get minimum P state
323  * @get_turbo:          Callback to get turbo P state
324  * @get_scaling:        Callback to get frequency scaling factor
325  * @get_val:            Callback to convert P state to actual MSR write value
326  * @get_vid:            Callback to get VID data for Atom platforms
327  * @get_target_pstate:  Callback to a function to calculate next P state to use
328  *
329  * Core and Atom CPU models have different way to get P State limits. This
330  * structure is used to store those callbacks.
331  */
332 struct pstate_funcs {
333         int (*get_max)(void);
334         int (*get_max_physical)(void);
335         int (*get_min)(void);
336         int (*get_turbo)(void);
337         int (*get_scaling)(void);
338         u64 (*get_val)(struct cpudata*, int pstate);
339         void (*get_vid)(struct cpudata *);
340         int32_t (*get_target_pstate)(struct cpudata *);
341 };
342 
343 /**
344  * struct cpu_defaults- Per CPU model default config data
345  * @pid_policy: PID config data
346  * @funcs:              Callback function data
347  */
348 struct cpu_defaults {
349         struct pstate_adjust_policy pid_policy;
350         struct pstate_funcs funcs;
351 };
352 
353 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
355 
356 static struct pstate_adjust_policy pid_params __read_mostly;
357 static struct pstate_funcs pstate_funcs __read_mostly;
358 static int hwp_active __read_mostly;
359 static bool per_cpu_limits __read_mostly;
360 
361 #ifdef CONFIG_ACPI
362 static bool acpi_ppc;
363 #endif
364 
365 static struct perf_limits performance_limits = {
366         .no_turbo = 0,
367         .turbo_disabled = 0,
368         .max_perf_pct = 100,
369         .max_perf = int_ext_tofp(1),
370         .min_perf_pct = 100,
371         .min_perf = int_ext_tofp(1),
372         .max_policy_pct = 100,
373         .max_sysfs_pct = 100,
374         .min_policy_pct = 0,
375         .min_sysfs_pct = 0,
376 };
377 
378 static struct perf_limits powersave_limits = {
379         .no_turbo = 0,
380         .turbo_disabled = 0,
381         .max_perf_pct = 100,
382         .max_perf = int_ext_tofp(1),
383         .min_perf_pct = 0,
384         .min_perf = 0,
385         .max_policy_pct = 100,
386         .max_sysfs_pct = 100,
387         .min_policy_pct = 0,
388         .min_sysfs_pct = 0,
389 };
390 
391 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
392 static struct perf_limits *limits = &performance_limits;
393 #else
394 static struct perf_limits *limits = &powersave_limits;
395 #endif
396 
397 static DEFINE_MUTEX(intel_pstate_limits_lock);
398 
399 #ifdef CONFIG_ACPI
400 
401 static bool intel_pstate_get_ppc_enable_status(void)
402 {
403         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
404             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
405                 return true;
406 
407         return acpi_ppc;
408 }
409 
410 #ifdef CONFIG_ACPI_CPPC_LIB
411 
412 /* The work item is needed to avoid CPU hotplug locking issues */
413 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
414 {
415         sched_set_itmt_support();
416 }
417 
418 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
419 
420 static void intel_pstate_set_itmt_prio(int cpu)
421 {
422         struct cppc_perf_caps cppc_perf;
423         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
424         int ret;
425 
426         ret = cppc_get_perf_caps(cpu, &cppc_perf);
427         if (ret)
428                 return;
429 
430         /*
431          * The priorities can be set regardless of whether or not
432          * sched_set_itmt_support(true) has been called and it is valid to
433          * update them at any time after it has been called.
434          */
435         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
436 
437         if (max_highest_perf <= min_highest_perf) {
438                 if (cppc_perf.highest_perf > max_highest_perf)
439                         max_highest_perf = cppc_perf.highest_perf;
440 
441                 if (cppc_perf.highest_perf < min_highest_perf)
442                         min_highest_perf = cppc_perf.highest_perf;
443 
444                 if (max_highest_perf > min_highest_perf) {
445                         /*
446                          * This code can be run during CPU online under the
447                          * CPU hotplug locks, so sched_set_itmt_support()
448                          * cannot be called from here.  Queue up a work item
449                          * to invoke it.
450                          */
451                         schedule_work(&sched_itmt_work);
452                 }
453         }
454 }
455 #else
456 static void intel_pstate_set_itmt_prio(int cpu)
457 {
458 }
459 #endif
460 
461 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
462 {
463         struct cpudata *cpu;
464         int ret;
465         int i;
466 
467         if (hwp_active) {
468                 intel_pstate_set_itmt_prio(policy->cpu);
469                 return;
470         }
471 
472         if (!intel_pstate_get_ppc_enable_status())
473                 return;
474 
475         cpu = all_cpu_data[policy->cpu];
476 
477         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
478                                                   policy->cpu);
479         if (ret)
480                 return;
481 
482         /*
483          * Check if the control value in _PSS is for PERF_CTL MSR, which should
484          * guarantee that the states returned by it map to the states in our
485          * list directly.
486          */
487         if (cpu->acpi_perf_data.control_register.space_id !=
488                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
489                 goto err;
490 
491         /*
492          * If there is only one entry _PSS, simply ignore _PSS and continue as
493          * usual without taking _PSS into account
494          */
495         if (cpu->acpi_perf_data.state_count < 2)
496                 goto err;
497 
498         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
499         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
500                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
501                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
502                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
503                          (u32) cpu->acpi_perf_data.states[i].power,
504                          (u32) cpu->acpi_perf_data.states[i].control);
505         }
506 
507         /*
508          * The _PSS table doesn't contain whole turbo frequency range.
509          * This just contains +1 MHZ above the max non turbo frequency,
510          * with control value corresponding to max turbo ratio. But
511          * when cpufreq set policy is called, it will call with this
512          * max frequency, which will cause a reduced performance as
513          * this driver uses real max turbo frequency as the max
514          * frequency. So correct this frequency in _PSS table to
515          * correct max turbo frequency based on the turbo state.
516          * Also need to convert to MHz as _PSS freq is in MHz.
517          */
518         if (!limits->turbo_disabled)
519                 cpu->acpi_perf_data.states[0].core_frequency =
520                                         policy->cpuinfo.max_freq / 1000;
521         cpu->valid_pss_table = true;
522         pr_debug("_PPC limits will be enforced\n");
523 
524         return;
525 
526  err:
527         cpu->valid_pss_table = false;
528         acpi_processor_unregister_performance(policy->cpu);
529 }
530 
531 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
532 {
533         struct cpudata *cpu;
534 
535         cpu = all_cpu_data[policy->cpu];
536         if (!cpu->valid_pss_table)
537                 return;
538 
539         acpi_processor_unregister_performance(policy->cpu);
540 }
541 
542 #else
543 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
544 {
545 }
546 
547 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
548 {
549 }
550 #endif
551 
552 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
553                              int deadband, int integral) {
554         pid->setpoint = int_tofp(setpoint);
555         pid->deadband  = int_tofp(deadband);
556         pid->integral  = int_tofp(integral);
557         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
558 }
559 
560 static inline void pid_p_gain_set(struct _pid *pid, int percent)
561 {
562         pid->p_gain = div_fp(percent, 100);
563 }
564 
565 static inline void pid_i_gain_set(struct _pid *pid, int percent)
566 {
567         pid->i_gain = div_fp(percent, 100);
568 }
569 
570 static inline void pid_d_gain_set(struct _pid *pid, int percent)
571 {
572         pid->d_gain = div_fp(percent, 100);
573 }
574 
575 static signed int pid_calc(struct _pid *pid, int32_t busy)
576 {
577         signed int result;
578         int32_t pterm, dterm, fp_error;
579         int32_t integral_limit;
580 
581         fp_error = pid->setpoint - busy;
582 
583         if (abs(fp_error) <= pid->deadband)
584                 return 0;
585 
586         pterm = mul_fp(pid->p_gain, fp_error);
587 
588         pid->integral += fp_error;
589 
590         /*
591          * We limit the integral here so that it will never
592          * get higher than 30.  This prevents it from becoming
593          * too large an input over long periods of time and allows
594          * it to get factored out sooner.
595          *
596          * The value of 30 was chosen through experimentation.
597          */
598         integral_limit = int_tofp(30);
599         if (pid->integral > integral_limit)
600                 pid->integral = integral_limit;
601         if (pid->integral < -integral_limit)
602                 pid->integral = -integral_limit;
603 
604         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
605         pid->last_err = fp_error;
606 
607         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
608         result = result + (1 << (FRAC_BITS-1));
609         return (signed int)fp_toint(result);
610 }
611 
612 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
613 {
614         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
615         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
616         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
617 
618         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
619 }
620 
621 static inline void intel_pstate_reset_all_pid(void)
622 {
623         unsigned int cpu;
624 
625         for_each_online_cpu(cpu) {
626                 if (all_cpu_data[cpu])
627                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
628         }
629 }
630 
631 static inline void update_turbo_state(void)
632 {
633         u64 misc_en;
634         struct cpudata *cpu;
635 
636         cpu = all_cpu_data[0];
637         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
638         limits->turbo_disabled =
639                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
640                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
641 }
642 
643 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
644 {
645         u64 epb;
646         int ret;
647 
648         if (!static_cpu_has(X86_FEATURE_EPB))
649                 return -ENXIO;
650 
651         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
652         if (ret)
653                 return (s16)ret;
654 
655         return (s16)(epb & 0x0f);
656 }
657 
658 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
659 {
660         s16 epp;
661 
662         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
663                 /*
664                  * When hwp_req_data is 0, means that caller didn't read
665                  * MSR_HWP_REQUEST, so need to read and get EPP.
666                  */
667                 if (!hwp_req_data) {
668                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
669                                             &hwp_req_data);
670                         if (epp)
671                                 return epp;
672                 }
673                 epp = (hwp_req_data >> 24) & 0xff;
674         } else {
675                 /* When there is no EPP present, HWP uses EPB settings */
676                 epp = intel_pstate_get_epb(cpu_data);
677         }
678 
679         return epp;
680 }
681 
682 static int intel_pstate_set_epb(int cpu, s16 pref)
683 {
684         u64 epb;
685         int ret;
686 
687         if (!static_cpu_has(X86_FEATURE_EPB))
688                 return -ENXIO;
689 
690         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
691         if (ret)
692                 return ret;
693 
694         epb = (epb & ~0x0f) | pref;
695         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
696 
697         return 0;
698 }
699 
700 /*
701  * EPP/EPB display strings corresponding to EPP index in the
702  * energy_perf_strings[]
703  *      index           String
704  *-------------------------------------
705  *      0               default
706  *      1               performance
707  *      2               balance_performance
708  *      3               balance_power
709  *      4               power
710  */
711 static const char * const energy_perf_strings[] = {
712         "default",
713         "performance",
714         "balance_performance",
715         "balance_power",
716         "power",
717         NULL
718 };
719 
720 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
721 {
722         s16 epp;
723         int index = -EINVAL;
724 
725         epp = intel_pstate_get_epp(cpu_data, 0);
726         if (epp < 0)
727                 return epp;
728 
729         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
730                 /*
731                  * Range:
732                  *      0x00-0x3F       :       Performance
733                  *      0x40-0x7F       :       Balance performance
734                  *      0x80-0xBF       :       Balance power
735                  *      0xC0-0xFF       :       Power
736                  * The EPP is a 8 bit value, but our ranges restrict the
737                  * value which can be set. Here only using top two bits
738                  * effectively.
739                  */
740                 index = (epp >> 6) + 1;
741         } else if (static_cpu_has(X86_FEATURE_EPB)) {
742                 /*
743                  * Range:
744                  *      0x00-0x03       :       Performance
745                  *      0x04-0x07       :       Balance performance
746                  *      0x08-0x0B       :       Balance power
747                  *      0x0C-0x0F       :       Power
748                  * The EPB is a 4 bit value, but our ranges restrict the
749                  * value which can be set. Here only using top two bits
750                  * effectively.
751                  */
752                 index = (epp >> 2) + 1;
753         }
754 
755         return index;
756 }
757 
758 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
759                                               int pref_index)
760 {
761         int epp = -EINVAL;
762         int ret;
763 
764         if (!pref_index)
765                 epp = cpu_data->epp_default;
766 
767         mutex_lock(&intel_pstate_limits_lock);
768 
769         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
770                 u64 value;
771 
772                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
773                 if (ret)
774                         goto return_pref;
775 
776                 value &= ~GENMASK_ULL(31, 24);
777 
778                 /*
779                  * If epp is not default, convert from index into
780                  * energy_perf_strings to epp value, by shifting 6
781                  * bits left to use only top two bits in epp.
782                  * The resultant epp need to shifted by 24 bits to
783                  * epp position in MSR_HWP_REQUEST.
784                  */
785                 if (epp == -EINVAL)
786                         epp = (pref_index - 1) << 6;
787 
788                 value |= (u64)epp << 24;
789                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
790         } else {
791                 if (epp == -EINVAL)
792                         epp = (pref_index - 1) << 2;
793                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
794         }
795 return_pref:
796         mutex_unlock(&intel_pstate_limits_lock);
797 
798         return ret;
799 }
800 
801 static ssize_t show_energy_performance_available_preferences(
802                                 struct cpufreq_policy *policy, char *buf)
803 {
804         int i = 0;
805         int ret = 0;
806 
807         while (energy_perf_strings[i] != NULL)
808                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
809 
810         ret += sprintf(&buf[ret], "\n");
811 
812         return ret;
813 }
814 
815 cpufreq_freq_attr_ro(energy_performance_available_preferences);
816 
817 static ssize_t store_energy_performance_preference(
818                 struct cpufreq_policy *policy, const char *buf, size_t count)
819 {
820         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
821         char str_preference[21];
822         int ret, i = 0;
823 
824         ret = sscanf(buf, "%20s", str_preference);
825         if (ret != 1)
826                 return -EINVAL;
827 
828         while (energy_perf_strings[i] != NULL) {
829                 if (!strcmp(str_preference, energy_perf_strings[i])) {
830                         intel_pstate_set_energy_pref_index(cpu_data, i);
831                         return count;
832                 }
833                 ++i;
834         }
835 
836         return -EINVAL;
837 }
838 
839 static ssize_t show_energy_performance_preference(
840                                 struct cpufreq_policy *policy, char *buf)
841 {
842         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
843         int preference;
844 
845         preference = intel_pstate_get_energy_pref_index(cpu_data);
846         if (preference < 0)
847                 return preference;
848 
849         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
850 }
851 
852 cpufreq_freq_attr_rw(energy_performance_preference);
853 
854 static struct freq_attr *hwp_cpufreq_attrs[] = {
855         &energy_performance_preference,
856         &energy_performance_available_preferences,
857         NULL,
858 };
859 
860 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
861 {
862         int min, hw_min, max, hw_max, cpu, range, adj_range;
863         struct perf_limits *perf_limits = limits;
864         u64 value, cap;
865 
866         for_each_cpu(cpu, policy->cpus) {
867                 int max_perf_pct, min_perf_pct;
868                 struct cpudata *cpu_data = all_cpu_data[cpu];
869                 s16 epp;
870 
871                 if (per_cpu_limits)
872                         perf_limits = all_cpu_data[cpu]->perf_limits;
873 
874                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
875                 hw_min = HWP_LOWEST_PERF(cap);
876                 hw_max = HWP_HIGHEST_PERF(cap);
877                 range = hw_max - hw_min;
878 
879                 max_perf_pct = perf_limits->max_perf_pct;
880                 min_perf_pct = perf_limits->min_perf_pct;
881 
882                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
883                 adj_range = min_perf_pct * range / 100;
884                 min = hw_min + adj_range;
885                 value &= ~HWP_MIN_PERF(~0L);
886                 value |= HWP_MIN_PERF(min);
887 
888                 adj_range = max_perf_pct * range / 100;
889                 max = hw_min + adj_range;
890                 if (limits->no_turbo) {
891                         hw_max = HWP_GUARANTEED_PERF(cap);
892                         if (hw_max < max)
893                                 max = hw_max;
894                 }
895 
896                 value &= ~HWP_MAX_PERF(~0L);
897                 value |= HWP_MAX_PERF(max);
898 
899                 if (cpu_data->epp_policy == cpu_data->policy)
900                         goto skip_epp;
901 
902                 cpu_data->epp_policy = cpu_data->policy;
903 
904                 if (cpu_data->epp_saved >= 0) {
905                         epp = cpu_data->epp_saved;
906                         cpu_data->epp_saved = -EINVAL;
907                         goto update_epp;
908                 }
909 
910                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
911                         epp = intel_pstate_get_epp(cpu_data, value);
912                         cpu_data->epp_powersave = epp;
913                         /* If EPP read was failed, then don't try to write */
914                         if (epp < 0)
915                                 goto skip_epp;
916 
917 
918                         epp = 0;
919                 } else {
920                         /* skip setting EPP, when saved value is invalid */
921                         if (cpu_data->epp_powersave < 0)
922                                 goto skip_epp;
923 
924                         /*
925                          * No need to restore EPP when it is not zero. This
926                          * means:
927                          *  - Policy is not changed
928                          *  - user has manually changed
929                          *  - Error reading EPB
930                          */
931                         epp = intel_pstate_get_epp(cpu_data, value);
932                         if (epp)
933                                 goto skip_epp;
934 
935                         epp = cpu_data->epp_powersave;
936                 }
937 update_epp:
938                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
939                         value &= ~GENMASK_ULL(31, 24);
940                         value |= (u64)epp << 24;
941                 } else {
942                         intel_pstate_set_epb(cpu, epp);
943                 }
944 skip_epp:
945                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
946         }
947 }
948 
949 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
950 {
951         if (hwp_active)
952                 intel_pstate_hwp_set(policy);
953 
954         return 0;
955 }
956 
957 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
958 {
959         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
960 
961         if (!hwp_active)
962                 return 0;
963 
964         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
965 
966         return 0;
967 }
968 
969 static int intel_pstate_resume(struct cpufreq_policy *policy)
970 {
971         int ret;
972 
973         if (!hwp_active)
974                 return 0;
975 
976         mutex_lock(&intel_pstate_limits_lock);
977 
978         all_cpu_data[policy->cpu]->epp_policy = 0;
979 
980         ret = intel_pstate_hwp_set_policy(policy);
981 
982         mutex_unlock(&intel_pstate_limits_lock);
983 
984         return ret;
985 }
986 
987 static void intel_pstate_update_policies(void)
988 {
989         int cpu;
990 
991         for_each_possible_cpu(cpu)
992                 cpufreq_update_policy(cpu);
993 }
994 
995 /************************** debugfs begin ************************/
996 static int pid_param_set(void *data, u64 val)
997 {
998         *(u32 *)data = val;
999         intel_pstate_reset_all_pid();
1000         return 0;
1001 }
1002 
1003 static int pid_param_get(void *data, u64 *val)
1004 {
1005         *val = *(u32 *)data;
1006         return 0;
1007 }
1008 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
1009 
1010 struct pid_param {
1011         char *name;
1012         void *value;
1013 };
1014 
1015 static struct pid_param pid_files[] = {
1016         {"sample_rate_ms", &pid_params.sample_rate_ms},
1017         {"d_gain_pct", &pid_params.d_gain_pct},
1018         {"i_gain_pct", &pid_params.i_gain_pct},
1019         {"deadband", &pid_params.deadband},
1020         {"setpoint", &pid_params.setpoint},
1021         {"p_gain_pct", &pid_params.p_gain_pct},
1022         {NULL, NULL}
1023 };
1024 
1025 static void __init intel_pstate_debug_expose_params(void)
1026 {
1027         struct dentry *debugfs_parent;
1028         int i = 0;
1029 
1030         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1031         if (IS_ERR_OR_NULL(debugfs_parent))
1032                 return;
1033         while (pid_files[i].name) {
1034                 debugfs_create_file(pid_files[i].name, 0660,
1035                                     debugfs_parent, pid_files[i].value,
1036                                     &fops_pid_param);
1037                 i++;
1038         }
1039 }
1040 
1041 /************************** debugfs end ************************/
1042 
1043 /************************** sysfs begin ************************/
1044 #define show_one(file_name, object)                                     \
1045         static ssize_t show_##file_name                                 \
1046         (struct kobject *kobj, struct attribute *attr, char *buf)       \
1047         {                                                               \
1048                 return sprintf(buf, "%u\n", limits->object);            \
1049         }
1050 
1051 static ssize_t show_turbo_pct(struct kobject *kobj,
1052                                 struct attribute *attr, char *buf)
1053 {
1054         struct cpudata *cpu;
1055         int total, no_turbo, turbo_pct;
1056         uint32_t turbo_fp;
1057 
1058         cpu = all_cpu_data[0];
1059 
1060         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1061         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1062         turbo_fp = div_fp(no_turbo, total);
1063         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1064         return sprintf(buf, "%u\n", turbo_pct);
1065 }
1066 
1067 static ssize_t show_num_pstates(struct kobject *kobj,
1068                                 struct attribute *attr, char *buf)
1069 {
1070         struct cpudata *cpu;
1071         int total;
1072 
1073         cpu = all_cpu_data[0];
1074         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1075         return sprintf(buf, "%u\n", total);
1076 }
1077 
1078 static ssize_t show_no_turbo(struct kobject *kobj,
1079                              struct attribute *attr, char *buf)
1080 {
1081         ssize_t ret;
1082 
1083         update_turbo_state();
1084         if (limits->turbo_disabled)
1085                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1086         else
1087                 ret = sprintf(buf, "%u\n", limits->no_turbo);
1088 
1089         return ret;
1090 }
1091 
1092 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1093                               const char *buf, size_t count)
1094 {
1095         unsigned int input;
1096         int ret;
1097 
1098         ret = sscanf(buf, "%u", &input);
1099         if (ret != 1)
1100                 return -EINVAL;
1101 
1102         mutex_lock(&intel_pstate_limits_lock);
1103 
1104         update_turbo_state();
1105         if (limits->turbo_disabled) {
1106                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1107                 mutex_unlock(&intel_pstate_limits_lock);
1108                 return -EPERM;
1109         }
1110 
1111         limits->no_turbo = clamp_t(int, input, 0, 1);
1112 
1113         mutex_unlock(&intel_pstate_limits_lock);
1114 
1115         intel_pstate_update_policies();
1116 
1117         return count;
1118 }
1119 
1120 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1121                                   const char *buf, size_t count)
1122 {
1123         unsigned int input;
1124         int ret;
1125 
1126         ret = sscanf(buf, "%u", &input);
1127         if (ret != 1)
1128                 return -EINVAL;
1129 
1130         mutex_lock(&intel_pstate_limits_lock);
1131 
1132         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1133         limits->max_perf_pct = min(limits->max_policy_pct,
1134                                    limits->max_sysfs_pct);
1135         limits->max_perf_pct = max(limits->min_policy_pct,
1136                                    limits->max_perf_pct);
1137         limits->max_perf_pct = max(limits->min_perf_pct,
1138                                    limits->max_perf_pct);
1139         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1140 
1141         mutex_unlock(&intel_pstate_limits_lock);
1142 
1143         intel_pstate_update_policies();
1144 
1145         return count;
1146 }
1147 
1148 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1149                                   const char *buf, size_t count)
1150 {
1151         unsigned int input;
1152         int ret;
1153 
1154         ret = sscanf(buf, "%u", &input);
1155         if (ret != 1)
1156                 return -EINVAL;
1157 
1158         mutex_lock(&intel_pstate_limits_lock);
1159 
1160         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1161         limits->min_perf_pct = max(limits->min_policy_pct,
1162                                    limits->min_sysfs_pct);
1163         limits->min_perf_pct = min(limits->max_policy_pct,
1164                                    limits->min_perf_pct);
1165         limits->min_perf_pct = min(limits->max_perf_pct,
1166                                    limits->min_perf_pct);
1167         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1168 
1169         mutex_unlock(&intel_pstate_limits_lock);
1170 
1171         intel_pstate_update_policies();
1172 
1173         return count;
1174 }
1175 
1176 show_one(max_perf_pct, max_perf_pct);
1177 show_one(min_perf_pct, min_perf_pct);
1178 
1179 define_one_global_rw(no_turbo);
1180 define_one_global_rw(max_perf_pct);
1181 define_one_global_rw(min_perf_pct);
1182 define_one_global_ro(turbo_pct);
1183 define_one_global_ro(num_pstates);
1184 
1185 static struct attribute *intel_pstate_attributes[] = {
1186         &no_turbo.attr,
1187         &turbo_pct.attr,
1188         &num_pstates.attr,
1189         NULL
1190 };
1191 
1192 static struct attribute_group intel_pstate_attr_group = {
1193         .attrs = intel_pstate_attributes,
1194 };
1195 
1196 static void __init intel_pstate_sysfs_expose_params(void)
1197 {
1198         struct kobject *intel_pstate_kobject;
1199         int rc;
1200 
1201         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1202                                                 &cpu_subsys.dev_root->kobj);
1203         if (WARN_ON(!intel_pstate_kobject))
1204                 return;
1205 
1206         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1207         if (WARN_ON(rc))
1208                 return;
1209 
1210         /*
1211          * If per cpu limits are enforced there are no global limits, so
1212          * return without creating max/min_perf_pct attributes
1213          */
1214         if (per_cpu_limits)
1215                 return;
1216 
1217         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1218         WARN_ON(rc);
1219 
1220         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1221         WARN_ON(rc);
1222 
1223 }
1224 /************************** sysfs end ************************/
1225 
1226 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1227 {
1228         /* First disable HWP notification interrupt as we don't process them */
1229         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1230                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1231 
1232         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1233         cpudata->epp_policy = 0;
1234         if (cpudata->epp_default == -EINVAL)
1235                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1236 }
1237 
1238 #define MSR_IA32_POWER_CTL_BIT_EE       19
1239 
1240 /* Disable energy efficiency optimization */
1241 static void intel_pstate_disable_ee(int cpu)
1242 {
1243         u64 power_ctl;
1244         int ret;
1245 
1246         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1247         if (ret)
1248                 return;
1249 
1250         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1251                 pr_info("Disabling energy efficiency optimization\n");
1252                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1253                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1254         }
1255 }
1256 
1257 static int atom_get_min_pstate(void)
1258 {
1259         u64 value;
1260 
1261         rdmsrl(ATOM_RATIOS, value);
1262         return (value >> 8) & 0x7F;
1263 }
1264 
1265 static int atom_get_max_pstate(void)
1266 {
1267         u64 value;
1268 
1269         rdmsrl(ATOM_RATIOS, value);
1270         return (value >> 16) & 0x7F;
1271 }
1272 
1273 static int atom_get_turbo_pstate(void)
1274 {
1275         u64 value;
1276 
1277         rdmsrl(ATOM_TURBO_RATIOS, value);
1278         return value & 0x7F;
1279 }
1280 
1281 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1282 {
1283         u64 val;
1284         int32_t vid_fp;
1285         u32 vid;
1286 
1287         val = (u64)pstate << 8;
1288         if (limits->no_turbo && !limits->turbo_disabled)
1289                 val |= (u64)1 << 32;
1290 
1291         vid_fp = cpudata->vid.min + mul_fp(
1292                 int_tofp(pstate - cpudata->pstate.min_pstate),
1293                 cpudata->vid.ratio);
1294 
1295         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1296         vid = ceiling_fp(vid_fp);
1297 
1298         if (pstate > cpudata->pstate.max_pstate)
1299                 vid = cpudata->vid.turbo;
1300 
1301         return val | vid;
1302 }
1303 
1304 static int silvermont_get_scaling(void)
1305 {
1306         u64 value;
1307         int i;
1308         /* Defined in Table 35-6 from SDM (Sept 2015) */
1309         static int silvermont_freq_table[] = {
1310                 83300, 100000, 133300, 116700, 80000};
1311 
1312         rdmsrl(MSR_FSB_FREQ, value);
1313         i = value & 0x7;
1314         WARN_ON(i > 4);
1315 
1316         return silvermont_freq_table[i];
1317 }
1318 
1319 static int airmont_get_scaling(void)
1320 {
1321         u64 value;
1322         int i;
1323         /* Defined in Table 35-10 from SDM (Sept 2015) */
1324         static int airmont_freq_table[] = {
1325                 83300, 100000, 133300, 116700, 80000,
1326                 93300, 90000, 88900, 87500};
1327 
1328         rdmsrl(MSR_FSB_FREQ, value);
1329         i = value & 0xF;
1330         WARN_ON(i > 8);
1331 
1332         return airmont_freq_table[i];
1333 }
1334 
1335 static void atom_get_vid(struct cpudata *cpudata)
1336 {
1337         u64 value;
1338 
1339         rdmsrl(ATOM_VIDS, value);
1340         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1341         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1342         cpudata->vid.ratio = div_fp(
1343                 cpudata->vid.max - cpudata->vid.min,
1344                 int_tofp(cpudata->pstate.max_pstate -
1345                         cpudata->pstate.min_pstate));
1346 
1347         rdmsrl(ATOM_TURBO_VIDS, value);
1348         cpudata->vid.turbo = value & 0x7f;
1349 }
1350 
1351 static int core_get_min_pstate(void)
1352 {
1353         u64 value;
1354 
1355         rdmsrl(MSR_PLATFORM_INFO, value);
1356         return (value >> 40) & 0xFF;
1357 }
1358 
1359 static int core_get_max_pstate_physical(void)
1360 {
1361         u64 value;
1362 
1363         rdmsrl(MSR_PLATFORM_INFO, value);
1364         return (value >> 8) & 0xFF;
1365 }
1366 
1367 static int core_get_max_pstate(void)
1368 {
1369         u64 tar;
1370         u64 plat_info;
1371         int max_pstate;
1372         int err;
1373 
1374         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1375         max_pstate = (plat_info >> 8) & 0xFF;
1376 
1377         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1378         if (!err) {
1379                 /* Do some sanity checking for safety */
1380                 if (plat_info & 0x600000000) {
1381                         u64 tdp_ctrl;
1382                         u64 tdp_ratio;
1383                         int tdp_msr;
1384 
1385                         err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1386                         if (err)
1387                                 goto skip_tar;
1388 
1389                         tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
1390                         err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1391                         if (err)
1392                                 goto skip_tar;
1393 
1394                         /* For level 1 and 2, bits[23:16] contain the ratio */
1395                         if (tdp_ctrl)
1396                                 tdp_ratio >>= 16;
1397 
1398                         tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1399                         if (tdp_ratio - 1 == tar) {
1400                                 max_pstate = tar;
1401                                 pr_debug("max_pstate=TAC %x\n", max_pstate);
1402                         } else {
1403                                 goto skip_tar;
1404                         }
1405                 }
1406         }
1407 
1408 skip_tar:
1409         return max_pstate;
1410 }
1411 
1412 static int core_get_turbo_pstate(void)
1413 {
1414         u64 value;
1415         int nont, ret;
1416 
1417         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1418         nont = core_get_max_pstate();
1419         ret = (value) & 255;
1420         if (ret <= nont)
1421                 ret = nont;
1422         return ret;
1423 }
1424 
1425 static inline int core_get_scaling(void)
1426 {
1427         return 100000;
1428 }
1429 
1430 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1431 {
1432         u64 val;
1433 
1434         val = (u64)pstate << 8;
1435         if (limits->no_turbo && !limits->turbo_disabled)
1436                 val |= (u64)1 << 32;
1437 
1438         return val;
1439 }
1440 
1441 static int knl_get_turbo_pstate(void)
1442 {
1443         u64 value;
1444         int nont, ret;
1445 
1446         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1447         nont = core_get_max_pstate();
1448         ret = (((value) >> 8) & 0xFF);
1449         if (ret <= nont)
1450                 ret = nont;
1451         return ret;
1452 }
1453 
1454 static struct cpu_defaults core_params = {
1455         .pid_policy = {
1456                 .sample_rate_ms = 10,
1457                 .deadband = 0,
1458                 .setpoint = 97,
1459                 .p_gain_pct = 20,
1460                 .d_gain_pct = 0,
1461                 .i_gain_pct = 0,
1462         },
1463         .funcs = {
1464                 .get_max = core_get_max_pstate,
1465                 .get_max_physical = core_get_max_pstate_physical,
1466                 .get_min = core_get_min_pstate,
1467                 .get_turbo = core_get_turbo_pstate,
1468                 .get_scaling = core_get_scaling,
1469                 .get_val = core_get_val,
1470                 .get_target_pstate = get_target_pstate_use_performance,
1471         },
1472 };
1473 
1474 static const struct cpu_defaults silvermont_params = {
1475         .pid_policy = {
1476                 .sample_rate_ms = 10,
1477                 .deadband = 0,
1478                 .setpoint = 60,
1479                 .p_gain_pct = 14,
1480                 .d_gain_pct = 0,
1481                 .i_gain_pct = 4,
1482         },
1483         .funcs = {
1484                 .get_max = atom_get_max_pstate,
1485                 .get_max_physical = atom_get_max_pstate,
1486                 .get_min = atom_get_min_pstate,
1487                 .get_turbo = atom_get_turbo_pstate,
1488                 .get_val = atom_get_val,
1489                 .get_scaling = silvermont_get_scaling,
1490                 .get_vid = atom_get_vid,
1491                 .get_target_pstate = get_target_pstate_use_cpu_load,
1492         },
1493 };
1494 
1495 static const struct cpu_defaults airmont_params = {
1496         .pid_policy = {
1497                 .sample_rate_ms = 10,
1498                 .deadband = 0,
1499                 .setpoint = 60,
1500                 .p_gain_pct = 14,
1501                 .d_gain_pct = 0,
1502                 .i_gain_pct = 4,
1503         },
1504         .funcs = {
1505                 .get_max = atom_get_max_pstate,
1506                 .get_max_physical = atom_get_max_pstate,
1507                 .get_min = atom_get_min_pstate,
1508                 .get_turbo = atom_get_turbo_pstate,
1509                 .get_val = atom_get_val,
1510                 .get_scaling = airmont_get_scaling,
1511                 .get_vid = atom_get_vid,
1512                 .get_target_pstate = get_target_pstate_use_cpu_load,
1513         },
1514 };
1515 
1516 static const struct cpu_defaults knl_params = {
1517         .pid_policy = {
1518                 .sample_rate_ms = 10,
1519                 .deadband = 0,
1520                 .setpoint = 97,
1521                 .p_gain_pct = 20,
1522                 .d_gain_pct = 0,
1523                 .i_gain_pct = 0,
1524         },
1525         .funcs = {
1526                 .get_max = core_get_max_pstate,
1527                 .get_max_physical = core_get_max_pstate_physical,
1528                 .get_min = core_get_min_pstate,
1529                 .get_turbo = knl_get_turbo_pstate,
1530                 .get_scaling = core_get_scaling,
1531                 .get_val = core_get_val,
1532                 .get_target_pstate = get_target_pstate_use_performance,
1533         },
1534 };
1535 
1536 static const struct cpu_defaults bxt_params = {
1537         .pid_policy = {
1538                 .sample_rate_ms = 10,
1539                 .deadband = 0,
1540                 .setpoint = 60,
1541                 .p_gain_pct = 14,
1542                 .d_gain_pct = 0,
1543                 .i_gain_pct = 4,
1544         },
1545         .funcs = {
1546                 .get_max = core_get_max_pstate,
1547                 .get_max_physical = core_get_max_pstate_physical,
1548                 .get_min = core_get_min_pstate,
1549                 .get_turbo = core_get_turbo_pstate,
1550                 .get_scaling = core_get_scaling,
1551                 .get_val = core_get_val,
1552                 .get_target_pstate = get_target_pstate_use_cpu_load,
1553         },
1554 };
1555 
1556 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1557 {
1558         int max_perf = cpu->pstate.turbo_pstate;
1559         int max_perf_adj;
1560         int min_perf;
1561         struct perf_limits *perf_limits = limits;
1562 
1563         if (limits->no_turbo || limits->turbo_disabled)
1564                 max_perf = cpu->pstate.max_pstate;
1565 
1566         if (per_cpu_limits)
1567                 perf_limits = cpu->perf_limits;
1568 
1569         /*
1570          * performance can be limited by user through sysfs, by cpufreq
1571          * policy, or by cpu specific default values determined through
1572          * experimentation.
1573          */
1574         max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1575         *max = clamp_t(int, max_perf_adj,
1576                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1577 
1578         min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1579         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1580 }
1581 
1582 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1583 {
1584         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1585         cpu->pstate.current_pstate = pstate;
1586         /*
1587          * Generally, there is no guarantee that this code will always run on
1588          * the CPU being updated, so force the register update to run on the
1589          * right CPU.
1590          */
1591         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1592                       pstate_funcs.get_val(cpu, pstate));
1593 }
1594 
1595 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1596 {
1597         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1598 }
1599 
1600 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1601 {
1602         int min_pstate, max_pstate;
1603 
1604         update_turbo_state();
1605         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1606         intel_pstate_set_pstate(cpu, max_pstate);
1607 }
1608 
1609 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1610 {
1611         cpu->pstate.min_pstate = pstate_funcs.get_min();
1612         cpu->pstate.max_pstate = pstate_funcs.get_max();
1613         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1614         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1615         cpu->pstate.scaling = pstate_funcs.get_scaling();
1616         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1617         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1618 
1619         if (pstate_funcs.get_vid)
1620                 pstate_funcs.get_vid(cpu);
1621 
1622         intel_pstate_set_min_pstate(cpu);
1623 }
1624 
1625 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1626 {
1627         struct sample *sample = &cpu->sample;
1628 
1629         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1630 }
1631 
1632 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1633 {
1634         u64 aperf, mperf;
1635         unsigned long flags;
1636         u64 tsc;
1637 
1638         local_irq_save(flags);
1639         rdmsrl(MSR_IA32_APERF, aperf);
1640         rdmsrl(MSR_IA32_MPERF, mperf);
1641         tsc = rdtsc();
1642         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1643                 local_irq_restore(flags);
1644                 return false;
1645         }
1646         local_irq_restore(flags);
1647 
1648         cpu->last_sample_time = cpu->sample.time;
1649         cpu->sample.time = time;
1650         cpu->sample.aperf = aperf;
1651         cpu->sample.mperf = mperf;
1652         cpu->sample.tsc =  tsc;
1653         cpu->sample.aperf -= cpu->prev_aperf;
1654         cpu->sample.mperf -= cpu->prev_mperf;
1655         cpu->sample.tsc -= cpu->prev_tsc;
1656 
1657         cpu->prev_aperf = aperf;
1658         cpu->prev_mperf = mperf;
1659         cpu->prev_tsc = tsc;
1660         /*
1661          * First time this function is invoked in a given cycle, all of the
1662          * previous sample data fields are equal to zero or stale and they must
1663          * be populated with meaningful numbers for things to work, so assume
1664          * that sample.time will always be reset before setting the utilization
1665          * update hook and make the caller skip the sample then.
1666          */
1667         return !!cpu->last_sample_time;
1668 }
1669 
1670 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1671 {
1672         return mul_ext_fp(cpu->sample.core_avg_perf,
1673                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1674 }
1675 
1676 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1677 {
1678         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1679                           cpu->sample.core_avg_perf);
1680 }
1681 
1682 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1683 {
1684         struct sample *sample = &cpu->sample;
1685         int32_t busy_frac, boost;
1686         int target, avg_pstate;
1687 
1688         busy_frac = div_fp(sample->mperf, sample->tsc);
1689 
1690         boost = cpu->iowait_boost;
1691         cpu->iowait_boost >>= 1;
1692 
1693         if (busy_frac < boost)
1694                 busy_frac = boost;
1695 
1696         sample->busy_scaled = busy_frac * 100;
1697 
1698         target = limits->no_turbo || limits->turbo_disabled ?
1699                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1700         target += target >> 2;
1701         target = mul_fp(target, busy_frac);
1702         if (target < cpu->pstate.min_pstate)
1703                 target = cpu->pstate.min_pstate;
1704 
1705         /*
1706          * If the average P-state during the previous cycle was higher than the
1707          * current target, add 50% of the difference to the target to reduce
1708          * possible performance oscillations and offset possible performance
1709          * loss related to moving the workload from one CPU to another within
1710          * a package/module.
1711          */
1712         avg_pstate = get_avg_pstate(cpu);
1713         if (avg_pstate > target)
1714                 target += (avg_pstate - target) >> 1;
1715 
1716         return target;
1717 }
1718 
1719 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1720 {
1721         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1722         u64 duration_ns;
1723 
1724         /*
1725          * perf_scaled is the ratio of the average P-state during the last
1726          * sampling period to the P-state requested last time (in percent).
1727          *
1728          * That measures the system's response to the previous P-state
1729          * selection.
1730          */
1731         max_pstate = cpu->pstate.max_pstate_physical;
1732         current_pstate = cpu->pstate.current_pstate;
1733         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1734                                div_fp(100 * max_pstate, current_pstate));
1735 
1736         /*
1737          * Since our utilization update callback will not run unless we are
1738          * in C0, check if the actual elapsed time is significantly greater (3x)
1739          * than our sample interval.  If it is, then we were idle for a long
1740          * enough period of time to adjust our performance metric.
1741          */
1742         duration_ns = cpu->sample.time - cpu->last_sample_time;
1743         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1744                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1745                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1746         } else {
1747                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1748                 if (sample_ratio < int_tofp(1))
1749                         perf_scaled = 0;
1750         }
1751 
1752         cpu->sample.busy_scaled = perf_scaled;
1753         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1754 }
1755 
1756 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1757 {
1758         int max_perf, min_perf;
1759 
1760         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1761         pstate = clamp_t(int, pstate, min_perf, max_perf);
1762         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1763         return pstate;
1764 }
1765 
1766 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1767 {
1768         pstate = intel_pstate_prepare_request(cpu, pstate);
1769         if (pstate == cpu->pstate.current_pstate)
1770                 return;
1771 
1772         cpu->pstate.current_pstate = pstate;
1773         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1774 }
1775 
1776 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1777 {
1778         int from, target_pstate;
1779         struct sample *sample;
1780 
1781         from = cpu->pstate.current_pstate;
1782 
1783         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1784                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1785 
1786         update_turbo_state();
1787 
1788         intel_pstate_update_pstate(cpu, target_pstate);
1789 
1790         sample = &cpu->sample;
1791         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1792                 fp_toint(sample->busy_scaled),
1793                 from,
1794                 cpu->pstate.current_pstate,
1795                 sample->mperf,
1796                 sample->aperf,
1797                 sample->tsc,
1798                 get_avg_frequency(cpu),
1799                 fp_toint(cpu->iowait_boost * 100));
1800 }
1801 
1802 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1803                                      unsigned int flags)
1804 {
1805         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1806         u64 delta_ns;
1807 
1808         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1809                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1810                         cpu->iowait_boost = int_tofp(1);
1811                 } else if (cpu->iowait_boost) {
1812                         /* Clear iowait_boost if the CPU may have been idle. */
1813                         delta_ns = time - cpu->last_update;
1814                         if (delta_ns > TICK_NSEC)
1815                                 cpu->iowait_boost = 0;
1816                 }
1817                 cpu->last_update = time;
1818         }
1819 
1820         delta_ns = time - cpu->sample.time;
1821         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1822                 bool sample_taken = intel_pstate_sample(cpu, time);
1823 
1824                 if (sample_taken) {
1825                         intel_pstate_calc_avg_perf(cpu);
1826                         if (!hwp_active)
1827                                 intel_pstate_adjust_busy_pstate(cpu);
1828                 }
1829         }
1830 }
1831 
1832 #define ICPU(model, policy) \
1833         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1834                         (unsigned long)&policy }
1835 
1836 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1837         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1838         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1839         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1840         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1841         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1842         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1843         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1844         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1845         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1846         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1847         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1848         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1849         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1850         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1851         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1852         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1853         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1854         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1855         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1856         {}
1857 };
1858 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1859 
1860 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1861         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1862         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1863         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1864         {}
1865 };
1866 
1867 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1868         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1869         {}
1870 };
1871 
1872 static int intel_pstate_init_cpu(unsigned int cpunum)
1873 {
1874         struct cpudata *cpu;
1875 
1876         cpu = all_cpu_data[cpunum];
1877 
1878         if (!cpu) {
1879                 unsigned int size = sizeof(struct cpudata);
1880 
1881                 if (per_cpu_limits)
1882                         size += sizeof(struct perf_limits);
1883 
1884                 cpu = kzalloc(size, GFP_KERNEL);
1885                 if (!cpu)
1886                         return -ENOMEM;
1887 
1888                 all_cpu_data[cpunum] = cpu;
1889                 if (per_cpu_limits)
1890                         cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1891 
1892                 cpu->epp_default = -EINVAL;
1893                 cpu->epp_powersave = -EINVAL;
1894                 cpu->epp_saved = -EINVAL;
1895         }
1896 
1897         cpu = all_cpu_data[cpunum];
1898 
1899         cpu->cpu = cpunum;
1900 
1901         if (hwp_active) {
1902                 const struct x86_cpu_id *id;
1903 
1904                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1905                 if (id)
1906                         intel_pstate_disable_ee(cpunum);
1907 
1908                 intel_pstate_hwp_enable(cpu);
1909                 pid_params.sample_rate_ms = 50;
1910                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1911         }
1912 
1913         intel_pstate_get_cpu_pstates(cpu);
1914 
1915         intel_pstate_busy_pid_reset(cpu);
1916 
1917         pr_debug("controlling: cpu %d\n", cpunum);
1918 
1919         return 0;
1920 }
1921 
1922 static unsigned int intel_pstate_get(unsigned int cpu_num)
1923 {
1924         struct cpudata *cpu = all_cpu_data[cpu_num];
1925 
1926         return cpu ? get_avg_frequency(cpu) : 0;
1927 }
1928 
1929 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1930 {
1931         struct cpudata *cpu = all_cpu_data[cpu_num];
1932 
1933         if (cpu->update_util_set)
1934                 return;
1935 
1936         /* Prevent intel_pstate_update_util() from using stale data. */
1937         cpu->sample.time = 0;
1938         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1939                                      intel_pstate_update_util);
1940         cpu->update_util_set = true;
1941 }
1942 
1943 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1944 {
1945         struct cpudata *cpu_data = all_cpu_data[cpu];
1946 
1947         if (!cpu_data->update_util_set)
1948                 return;
1949 
1950         cpufreq_remove_update_util_hook(cpu);
1951         cpu_data->update_util_set = false;
1952         synchronize_sched();
1953 }
1954 
1955 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1956 {
1957         limits->no_turbo = 0;
1958         limits->turbo_disabled = 0;
1959         limits->max_perf_pct = 100;
1960         limits->max_perf = int_ext_tofp(1);
1961         limits->min_perf_pct = 100;
1962         limits->min_perf = int_ext_tofp(1);
1963         limits->max_policy_pct = 100;
1964         limits->max_sysfs_pct = 100;
1965         limits->min_policy_pct = 0;
1966         limits->min_sysfs_pct = 0;
1967 }
1968 
1969 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1970                                             struct perf_limits *limits)
1971 {
1972 
1973         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1974                                               policy->cpuinfo.max_freq);
1975         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
1976         if (policy->max == policy->min) {
1977                 limits->min_policy_pct = limits->max_policy_pct;
1978         } else {
1979                 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
1980                                                       policy->cpuinfo.max_freq);
1981                 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
1982                                                  0, 100);
1983         }
1984 
1985         /* Normalize user input to [min_policy_pct, max_policy_pct] */
1986         limits->min_perf_pct = max(limits->min_policy_pct,
1987                                    limits->min_sysfs_pct);
1988         limits->min_perf_pct = min(limits->max_policy_pct,
1989                                    limits->min_perf_pct);
1990         limits->max_perf_pct = min(limits->max_policy_pct,
1991                                    limits->max_sysfs_pct);
1992         limits->max_perf_pct = max(limits->min_policy_pct,
1993                                    limits->max_perf_pct);
1994 
1995         /* Make sure min_perf_pct <= max_perf_pct */
1996         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1997 
1998         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1999         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2000         limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2001         limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2002 
2003         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2004                  limits->max_perf_pct, limits->min_perf_pct);
2005 }
2006 
2007 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2008 {
2009         struct cpudata *cpu;
2010         struct perf_limits *perf_limits = NULL;
2011 
2012         if (!policy->cpuinfo.max_freq)
2013                 return -ENODEV;
2014 
2015         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2016                  policy->cpuinfo.max_freq, policy->max);
2017 
2018         cpu = all_cpu_data[policy->cpu];
2019         cpu->policy = policy->policy;
2020 
2021         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2022             policy->max < policy->cpuinfo.max_freq &&
2023             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2024                 pr_debug("policy->max > max non turbo frequency\n");
2025                 policy->max = policy->cpuinfo.max_freq;
2026         }
2027 
2028         if (per_cpu_limits)
2029                 perf_limits = cpu->perf_limits;
2030 
2031         mutex_lock(&intel_pstate_limits_lock);
2032 
2033         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2034                 if (!perf_limits) {
2035                         limits = &performance_limits;
2036                         perf_limits = limits;
2037                 }
2038                 if (policy->max >= policy->cpuinfo.max_freq &&
2039                     !limits->no_turbo) {
2040                         pr_debug("set performance\n");
2041                         intel_pstate_set_performance_limits(perf_limits);
2042                         goto out;
2043                 }
2044         } else {
2045                 pr_debug("set powersave\n");
2046                 if (!perf_limits) {
2047                         limits = &powersave_limits;
2048                         perf_limits = limits;
2049                 }
2050 
2051         }
2052 
2053         intel_pstate_update_perf_limits(policy, perf_limits);
2054  out:
2055         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2056                 /*
2057                  * NOHZ_FULL CPUs need this as the governor callback may not
2058                  * be invoked on them.
2059                  */
2060                 intel_pstate_clear_update_util_hook(policy->cpu);
2061                 intel_pstate_max_within_limits(cpu);
2062         }
2063 
2064         intel_pstate_set_update_util_hook(policy->cpu);
2065 
2066         intel_pstate_hwp_set_policy(policy);
2067 
2068         mutex_unlock(&intel_pstate_limits_lock);
2069 
2070         return 0;
2071 }
2072 
2073 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2074 {
2075         cpufreq_verify_within_cpu_limits(policy);
2076 
2077         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2078             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2079                 return -EINVAL;
2080 
2081         /* When per-CPU limits are used, sysfs limits are not used */
2082         if (!per_cpu_limits) {
2083                 unsigned int max_freq, min_freq;
2084 
2085                 max_freq = policy->cpuinfo.max_freq *
2086                                                 limits->max_sysfs_pct / 100;
2087                 min_freq = policy->cpuinfo.max_freq *
2088                                                 limits->min_sysfs_pct / 100;
2089                 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2090         }
2091 
2092         return 0;
2093 }
2094 
2095 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2096 {
2097         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2098 }
2099 
2100 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2101 {
2102         pr_debug("CPU %d exiting\n", policy->cpu);
2103 
2104         intel_pstate_clear_update_util_hook(policy->cpu);
2105         if (hwp_active)
2106                 intel_pstate_hwp_save_state(policy);
2107         else
2108                 intel_cpufreq_stop_cpu(policy);
2109 }
2110 
2111 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2112 {
2113         intel_pstate_exit_perf_limits(policy);
2114 
2115         policy->fast_switch_possible = false;
2116 
2117         return 0;
2118 }
2119 
2120 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2121 {
2122         struct cpudata *cpu;
2123         int rc;
2124 
2125         rc = intel_pstate_init_cpu(policy->cpu);
2126         if (rc)
2127                 return rc;
2128 
2129         cpu = all_cpu_data[policy->cpu];
2130 
2131         /*
2132          * We need sane value in the cpu->perf_limits, so inherit from global
2133          * perf_limits limits, which are seeded with values based on the
2134          * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2135          */
2136         if (per_cpu_limits)
2137                 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2138 
2139         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2140         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2141 
2142         /* cpuinfo and default policy values */
2143         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2144         update_turbo_state();
2145         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2146                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2147         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2148 
2149         intel_pstate_init_acpi_perf_limits(policy);
2150         cpumask_set_cpu(policy->cpu, policy->cpus);
2151 
2152         policy->fast_switch_possible = true;
2153 
2154         return 0;
2155 }
2156 
2157 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2158 {
2159         int ret = __intel_pstate_cpu_init(policy);
2160 
2161         if (ret)
2162                 return ret;
2163 
2164         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2165         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2166                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2167         else
2168                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2169 
2170         return 0;
2171 }
2172 
2173 static struct cpufreq_driver intel_pstate = {
2174         .flags          = CPUFREQ_CONST_LOOPS,
2175         .verify         = intel_pstate_verify_policy,
2176         .setpolicy      = intel_pstate_set_policy,
2177         .suspend        = intel_pstate_hwp_save_state,
2178         .resume         = intel_pstate_resume,
2179         .get            = intel_pstate_get,
2180         .init           = intel_pstate_cpu_init,
2181         .exit           = intel_pstate_cpu_exit,
2182         .stop_cpu       = intel_pstate_stop_cpu,
2183         .name           = "intel_pstate",
2184 };
2185 
2186 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2187 {
2188         struct cpudata *cpu = all_cpu_data[policy->cpu];
2189         struct perf_limits *perf_limits = limits;
2190 
2191         update_turbo_state();
2192         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2193                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2194 
2195         cpufreq_verify_within_cpu_limits(policy);
2196 
2197         if (per_cpu_limits)
2198                 perf_limits = cpu->perf_limits;
2199 
2200         mutex_lock(&intel_pstate_limits_lock);
2201 
2202         intel_pstate_update_perf_limits(policy, perf_limits);
2203 
2204         mutex_unlock(&intel_pstate_limits_lock);
2205 
2206         return 0;
2207 }
2208 
2209 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2210                                                struct cpufreq_policy *policy,
2211                                                unsigned int target_freq)
2212 {
2213         unsigned int max_freq;
2214 
2215         update_turbo_state();
2216 
2217         max_freq = limits->no_turbo || limits->turbo_disabled ?
2218                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2219         policy->cpuinfo.max_freq = max_freq;
2220         if (policy->max > max_freq)
2221                 policy->max = max_freq;
2222 
2223         if (target_freq > max_freq)
2224                 target_freq = max_freq;
2225 
2226         return target_freq;
2227 }
2228 
2229 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2230                                 unsigned int target_freq,
2231                                 unsigned int relation)
2232 {
2233         struct cpudata *cpu = all_cpu_data[policy->cpu];
2234         struct cpufreq_freqs freqs;
2235         int target_pstate;
2236 
2237         freqs.old = policy->cur;
2238         freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2239 
2240         cpufreq_freq_transition_begin(policy, &freqs);
2241         switch (relation) {
2242         case CPUFREQ_RELATION_L:
2243                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2244                 break;
2245         case CPUFREQ_RELATION_H:
2246                 target_pstate = freqs.new / cpu->pstate.scaling;
2247                 break;
2248         default:
2249                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2250                 break;
2251         }
2252         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2253         if (target_pstate != cpu->pstate.current_pstate) {
2254                 cpu->pstate.current_pstate = target_pstate;
2255                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2256                               pstate_funcs.get_val(cpu, target_pstate));
2257         }
2258         cpufreq_freq_transition_end(policy, &freqs, false);
2259 
2260         return 0;
2261 }
2262 
2263 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2264                                               unsigned int target_freq)
2265 {
2266         struct cpudata *cpu = all_cpu_data[policy->cpu];
2267         int target_pstate;
2268 
2269         target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2270         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2271         intel_pstate_update_pstate(cpu, target_pstate);
2272         return target_freq;
2273 }
2274 
2275 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2276 {
2277         int ret = __intel_pstate_cpu_init(policy);
2278 
2279         if (ret)
2280                 return ret;
2281 
2282         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2283         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2284         policy->cur = policy->cpuinfo.min_freq;
2285 
2286         return 0;
2287 }
2288 
2289 static struct cpufreq_driver intel_cpufreq = {
2290         .flags          = CPUFREQ_CONST_LOOPS,
2291         .verify         = intel_cpufreq_verify_policy,
2292         .target         = intel_cpufreq_target,
2293         .fast_switch    = intel_cpufreq_fast_switch,
2294         .init           = intel_cpufreq_cpu_init,
2295         .exit           = intel_pstate_cpu_exit,
2296         .stop_cpu       = intel_cpufreq_stop_cpu,
2297         .name           = "intel_cpufreq",
2298 };
2299 
2300 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2301 
2302 static int no_load __initdata;
2303 static int no_hwp __initdata;
2304 static int hwp_only __initdata;
2305 static unsigned int force_load __initdata;
2306 
2307 static int __init intel_pstate_msrs_not_valid(void)
2308 {
2309         if (!pstate_funcs.get_max() ||
2310             !pstate_funcs.get_min() ||
2311             !pstate_funcs.get_turbo())
2312                 return -ENODEV;
2313 
2314         return 0;
2315 }
2316 
2317 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2318 {
2319         pid_params.sample_rate_ms = policy->sample_rate_ms;
2320         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2321         pid_params.p_gain_pct = policy->p_gain_pct;
2322         pid_params.i_gain_pct = policy->i_gain_pct;
2323         pid_params.d_gain_pct = policy->d_gain_pct;
2324         pid_params.deadband = policy->deadband;
2325         pid_params.setpoint = policy->setpoint;
2326 }
2327 
2328 #ifdef CONFIG_ACPI
2329 static void intel_pstate_use_acpi_profile(void)
2330 {
2331         if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2332                 pstate_funcs.get_target_pstate =
2333                                 get_target_pstate_use_cpu_load;
2334 }
2335 #else
2336 static void intel_pstate_use_acpi_profile(void)
2337 {
2338 }
2339 #endif
2340 
2341 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2342 {
2343         pstate_funcs.get_max   = funcs->get_max;
2344         pstate_funcs.get_max_physical = funcs->get_max_physical;
2345         pstate_funcs.get_min   = funcs->get_min;
2346         pstate_funcs.get_turbo = funcs->get_turbo;
2347         pstate_funcs.get_scaling = funcs->get_scaling;
2348         pstate_funcs.get_val   = funcs->get_val;
2349         pstate_funcs.get_vid   = funcs->get_vid;
2350         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2351 
2352         intel_pstate_use_acpi_profile();
2353 }
2354 
2355 #ifdef CONFIG_ACPI
2356 
2357 static bool __init intel_pstate_no_acpi_pss(void)
2358 {
2359         int i;
2360 
2361         for_each_possible_cpu(i) {
2362                 acpi_status status;
2363                 union acpi_object *pss;
2364                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2365                 struct acpi_processor *pr = per_cpu(processors, i);
2366 
2367                 if (!pr)
2368                         continue;
2369 
2370                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2371                 if (ACPI_FAILURE(status))
2372                         continue;
2373 
2374                 pss = buffer.pointer;
2375                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2376                         kfree(pss);
2377                         return false;
2378                 }
2379 
2380                 kfree(pss);
2381         }
2382 
2383         return true;
2384 }
2385 
2386 static bool __init intel_pstate_has_acpi_ppc(void)
2387 {
2388         int i;
2389 
2390         for_each_possible_cpu(i) {
2391                 struct acpi_processor *pr = per_cpu(processors, i);
2392 
2393                 if (!pr)
2394                         continue;
2395                 if (acpi_has_method(pr->handle, "_PPC"))
2396                         return true;
2397         }
2398         return false;
2399 }
2400 
2401 enum {
2402         PSS,
2403         PPC,
2404 };
2405 
2406 struct hw_vendor_info {
2407         u16  valid;
2408         char oem_id[ACPI_OEM_ID_SIZE];
2409         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2410         int  oem_pwr_table;
2411 };
2412 
2413 /* Hardware vendor-specific info that has its own power management modes */
2414 static struct hw_vendor_info vendor_info[] __initdata = {
2415         {1, "HP    ", "ProLiant", PSS},
2416         {1, "ORACLE", "X4-2    ", PPC},
2417         {1, "ORACLE", "X4-2L   ", PPC},
2418         {1, "ORACLE", "X4-2B   ", PPC},
2419         {1, "ORACLE", "X3-2    ", PPC},
2420         {1, "ORACLE", "X3-2L   ", PPC},
2421         {1, "ORACLE", "X3-2B   ", PPC},
2422         {1, "ORACLE", "X4470M2 ", PPC},
2423         {1, "ORACLE", "X4270M3 ", PPC},
2424         {1, "ORACLE", "X4270M2 ", PPC},
2425         {1, "ORACLE", "X4170M2 ", PPC},
2426         {1, "ORACLE", "X4170 M3", PPC},
2427         {1, "ORACLE", "X4275 M3", PPC},
2428         {1, "ORACLE", "X6-2    ", PPC},
2429         {1, "ORACLE", "Sudbury ", PPC},
2430         {0, "", ""},
2431 };
2432 
2433 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2434 {
2435         struct acpi_table_header hdr;
2436         struct hw_vendor_info *v_info;
2437         const struct x86_cpu_id *id;
2438         u64 misc_pwr;
2439 
2440         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2441         if (id) {
2442                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2443                 if ( misc_pwr & (1 << 8))
2444                         return true;
2445         }
2446 
2447         if (acpi_disabled ||
2448             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2449                 return false;
2450 
2451         for (v_info = vendor_info; v_info->valid; v_info++) {
2452                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2453                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2454                                                 ACPI_OEM_TABLE_ID_SIZE))
2455                         switch (v_info->oem_pwr_table) {
2456                         case PSS:
2457                                 return intel_pstate_no_acpi_pss();
2458                         case PPC:
2459                                 return intel_pstate_has_acpi_ppc() &&
2460                                         (!force_load);
2461                         }
2462         }
2463 
2464         return false;
2465 }
2466 
2467 static void intel_pstate_request_control_from_smm(void)
2468 {
2469         /*
2470          * It may be unsafe to request P-states control from SMM if _PPC support
2471          * has not been enabled.
2472          */
2473         if (acpi_ppc)
2474                 acpi_processor_pstate_control();
2475 }
2476 #else /* CONFIG_ACPI not enabled */
2477 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2478 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2479 static inline void intel_pstate_request_control_from_smm(void) {}
2480 #endif /* CONFIG_ACPI */
2481 
2482 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2483         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2484         {}
2485 };
2486 
2487 static int __init intel_pstate_init(void)
2488 {
2489         int cpu, rc = 0;
2490         const struct x86_cpu_id *id;
2491         struct cpu_defaults *cpu_def;
2492 
2493         if (no_load)
2494                 return -ENODEV;
2495 
2496         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2497                 copy_cpu_funcs(&core_params.funcs);
2498                 hwp_active++;
2499                 intel_pstate.attr = hwp_cpufreq_attrs;
2500                 goto hwp_cpu_matched;
2501         }
2502 
2503         id = x86_match_cpu(intel_pstate_cpu_ids);
2504         if (!id)
2505                 return -ENODEV;
2506 
2507         cpu_def = (struct cpu_defaults *)id->driver_data;
2508 
2509         copy_pid_params(&cpu_def->pid_policy);
2510         copy_cpu_funcs(&cpu_def->funcs);
2511 
2512         if (intel_pstate_msrs_not_valid())
2513                 return -ENODEV;
2514 
2515 hwp_cpu_matched:
2516         /*
2517          * The Intel pstate driver will be ignored if the platform
2518          * firmware has its own power management modes.
2519          */
2520         if (intel_pstate_platform_pwr_mgmt_exists())
2521                 return -ENODEV;
2522 
2523         pr_info("Intel P-state driver initializing\n");
2524 
2525         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2526         if (!all_cpu_data)
2527                 return -ENOMEM;
2528 
2529         if (!hwp_active && hwp_only)
2530                 goto out;
2531 
2532         intel_pstate_request_control_from_smm();
2533 
2534         rc = cpufreq_register_driver(intel_pstate_driver);
2535         if (rc)
2536                 goto out;
2537 
2538         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2539             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2540                 intel_pstate_debug_expose_params();
2541 
2542         intel_pstate_sysfs_expose_params();
2543 
2544         if (hwp_active)
2545                 pr_info("HWP enabled\n");
2546 
2547         return rc;
2548 out:
2549         get_online_cpus();
2550         for_each_online_cpu(cpu) {
2551                 if (all_cpu_data[cpu]) {
2552                         if (intel_pstate_driver == &intel_pstate)
2553                                 intel_pstate_clear_update_util_hook(cpu);
2554 
2555                         kfree(all_cpu_data[cpu]);
2556                 }
2557         }
2558 
2559         put_online_cpus();
2560         vfree(all_cpu_data);
2561         return -ENODEV;
2562 }
2563 device_initcall(intel_pstate_init);
2564 
2565 static int __init intel_pstate_setup(char *str)
2566 {
2567         if (!str)
2568                 return -EINVAL;
2569 
2570         if (!strcmp(str, "disable")) {
2571                 no_load = 1;
2572         } else if (!strcmp(str, "passive")) {
2573                 pr_info("Passive mode enabled\n");
2574                 intel_pstate_driver = &intel_cpufreq;
2575                 no_hwp = 1;
2576         }
2577         if (!strcmp(str, "no_hwp")) {
2578                 pr_info("HWP disabled\n");
2579                 no_hwp = 1;
2580         }
2581         if (!strcmp(str, "force"))
2582                 force_load = 1;
2583         if (!strcmp(str, "hwp_only"))
2584                 hwp_only = 1;
2585         if (!strcmp(str, "per_cpu_perf_limits"))
2586                 per_cpu_limits = true;
2587 
2588 #ifdef CONFIG_ACPI
2589         if (!strcmp(str, "support_acpi_ppc"))
2590                 acpi_ppc = true;
2591 #endif
2592 
2593         return 0;
2594 }
2595 early_param("intel_pstate", intel_pstate_setup);
2596 
2597 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2598 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2599 MODULE_LICENSE("GPL");
2600 

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