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Linux/drivers/cpufreq/imx6q-cpufreq.c

  1 /*
  2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  */
  8 
  9 #include <linux/clk.h>
 10 #include <linux/cpu.h>
 11 #include <linux/cpufreq.h>
 12 #include <linux/delay.h>
 13 #include <linux/err.h>
 14 #include <linux/module.h>
 15 #include <linux/of.h>
 16 #include <linux/pm_opp.h>
 17 #include <linux/platform_device.h>
 18 #include <linux/regulator/consumer.h>
 19 
 20 #define PU_SOC_VOLTAGE_NORMAL   1250000
 21 #define PU_SOC_VOLTAGE_HIGH     1275000
 22 #define FREQ_1P2_GHZ            1200000000
 23 
 24 static struct regulator *arm_reg;
 25 static struct regulator *pu_reg;
 26 static struct regulator *soc_reg;
 27 
 28 static struct clk *arm_clk;
 29 static struct clk *pll1_sys_clk;
 30 static struct clk *pll1_sw_clk;
 31 static struct clk *step_clk;
 32 static struct clk *pll2_pfd2_396m_clk;
 33 
 34 static struct device *cpu_dev;
 35 static struct cpufreq_frequency_table *freq_table;
 36 static unsigned int transition_latency;
 37 
 38 static u32 *imx6_soc_volt;
 39 static u32 soc_opp_count;
 40 
 41 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
 42 {
 43         struct dev_pm_opp *opp;
 44         unsigned long freq_hz, volt, volt_old;
 45         unsigned int old_freq, new_freq;
 46         int ret;
 47 
 48         new_freq = freq_table[index].frequency;
 49         freq_hz = new_freq * 1000;
 50         old_freq = clk_get_rate(arm_clk) / 1000;
 51 
 52         rcu_read_lock();
 53         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
 54         if (IS_ERR(opp)) {
 55                 rcu_read_unlock();
 56                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
 57                 return PTR_ERR(opp);
 58         }
 59 
 60         volt = dev_pm_opp_get_voltage(opp);
 61         rcu_read_unlock();
 62         volt_old = regulator_get_voltage(arm_reg);
 63 
 64         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
 65                 old_freq / 1000, volt_old / 1000,
 66                 new_freq / 1000, volt / 1000);
 67 
 68         /* scaling up?  scale voltage before frequency */
 69         if (new_freq > old_freq) {
 70                 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 71                 if (ret) {
 72                         dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
 73                         return ret;
 74                 }
 75                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 76                 if (ret) {
 77                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
 78                         return ret;
 79                 }
 80                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 81                 if (ret) {
 82                         dev_err(cpu_dev,
 83                                 "failed to scale vddarm up: %d\n", ret);
 84                         return ret;
 85                 }
 86         }
 87 
 88         /*
 89          * The setpoints are selected per PLL/PDF frequencies, so we need to
 90          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 91          * PLL1 is as below.
 92          *
 93          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 94          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 95          *  - Disable pll2_pfd2_396m_clk
 96          */
 97         clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 98         clk_set_parent(pll1_sw_clk, step_clk);
 99         if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
100                 clk_set_rate(pll1_sys_clk, new_freq * 1000);
101                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
102         }
103 
104         /* Ensure the arm clock divider is what we expect */
105         ret = clk_set_rate(arm_clk, new_freq * 1000);
106         if (ret) {
107                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
108                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
109                 return ret;
110         }
111 
112         /* scaling down?  scale voltage after frequency */
113         if (new_freq < old_freq) {
114                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
115                 if (ret) {
116                         dev_warn(cpu_dev,
117                                  "failed to scale vddarm down: %d\n", ret);
118                         ret = 0;
119                 }
120                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
121                 if (ret) {
122                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
123                         ret = 0;
124                 }
125                 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
126                 if (ret) {
127                         dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
128                         ret = 0;
129                 }
130         }
131 
132         return 0;
133 }
134 
135 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
136 {
137         policy->clk = arm_clk;
138         return cpufreq_generic_init(policy, freq_table, transition_latency);
139 }
140 
141 static struct cpufreq_driver imx6q_cpufreq_driver = {
142         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
143         .verify = cpufreq_generic_frequency_table_verify,
144         .target_index = imx6q_set_target,
145         .get = cpufreq_generic_get,
146         .init = imx6q_cpufreq_init,
147         .name = "imx6q-cpufreq",
148         .attr = cpufreq_generic_attr,
149 };
150 
151 static int imx6q_cpufreq_probe(struct platform_device *pdev)
152 {
153         struct device_node *np;
154         struct dev_pm_opp *opp;
155         unsigned long min_volt, max_volt;
156         int num, ret;
157         const struct property *prop;
158         const __be32 *val;
159         u32 nr, i, j;
160 
161         cpu_dev = get_cpu_device(0);
162         if (!cpu_dev) {
163                 pr_err("failed to get cpu0 device\n");
164                 return -ENODEV;
165         }
166 
167         np = of_node_get(cpu_dev->of_node);
168         if (!np) {
169                 dev_err(cpu_dev, "failed to find cpu0 node\n");
170                 return -ENOENT;
171         }
172 
173         arm_clk = devm_clk_get(cpu_dev, "arm");
174         pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
175         pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
176         step_clk = devm_clk_get(cpu_dev, "step");
177         pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
178         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
179             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
180                 dev_err(cpu_dev, "failed to get clocks\n");
181                 ret = -ENOENT;
182                 goto put_node;
183         }
184 
185         arm_reg = devm_regulator_get(cpu_dev, "arm");
186         pu_reg = devm_regulator_get(cpu_dev, "pu");
187         soc_reg = devm_regulator_get(cpu_dev, "soc");
188         if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
189                 dev_err(cpu_dev, "failed to get regulators\n");
190                 ret = -ENOENT;
191                 goto put_node;
192         }
193 
194         /*
195          * We expect an OPP table supplied by platform.
196          * Just, incase the platform did not supply the OPP
197          * table, it will try to get it.
198          */
199         num = dev_pm_opp_get_opp_count(cpu_dev);
200         if (num < 0) {
201                 ret = of_init_opp_table(cpu_dev);
202                 if (ret < 0) {
203                         dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
204                         goto put_node;
205                 }
206 
207                 num = dev_pm_opp_get_opp_count(cpu_dev);
208                 if (num < 0) {
209                         ret = num;
210                         dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
211                         goto put_node;
212                 }
213         }
214 
215         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
216         if (ret) {
217                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
218                 goto put_node;
219         }
220 
221         /* Make imx6_soc_volt array's size same as arm opp number */
222         imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
223         if (imx6_soc_volt == NULL) {
224                 ret = -ENOMEM;
225                 goto free_freq_table;
226         }
227 
228         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
229         if (!prop || !prop->value)
230                 goto soc_opp_out;
231 
232         /*
233          * Each OPP is a set of tuples consisting of frequency and
234          * voltage like <freq-kHz vol-uV>.
235          */
236         nr = prop->length / sizeof(u32);
237         if (nr % 2 || (nr / 2) < num)
238                 goto soc_opp_out;
239 
240         for (j = 0; j < num; j++) {
241                 val = prop->value;
242                 for (i = 0; i < nr / 2; i++) {
243                         unsigned long freq = be32_to_cpup(val++);
244                         unsigned long volt = be32_to_cpup(val++);
245                         if (freq_table[j].frequency == freq) {
246                                 imx6_soc_volt[soc_opp_count++] = volt;
247                                 break;
248                         }
249                 }
250         }
251 
252 soc_opp_out:
253         /* use fixed soc opp volt if no valid soc opp info found in dtb */
254         if (soc_opp_count != num) {
255                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
256                 for (j = 0; j < num; j++)
257                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
258                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
259                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
260         }
261 
262         if (of_property_read_u32(np, "clock-latency", &transition_latency))
263                 transition_latency = CPUFREQ_ETERNAL;
264 
265         /*
266          * Calculate the ramp time for max voltage change in the
267          * VDDSOC and VDDPU regulators.
268          */
269         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
270         if (ret > 0)
271                 transition_latency += ret * 1000;
272         ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
273         if (ret > 0)
274                 transition_latency += ret * 1000;
275 
276         /*
277          * OPP is maintained in order of increasing frequency, and
278          * freq_table initialised from OPP is therefore sorted in the
279          * same order.
280          */
281         rcu_read_lock();
282         opp = dev_pm_opp_find_freq_exact(cpu_dev,
283                                   freq_table[0].frequency * 1000, true);
284         min_volt = dev_pm_opp_get_voltage(opp);
285         opp = dev_pm_opp_find_freq_exact(cpu_dev,
286                                   freq_table[--num].frequency * 1000, true);
287         max_volt = dev_pm_opp_get_voltage(opp);
288         rcu_read_unlock();
289         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
290         if (ret > 0)
291                 transition_latency += ret * 1000;
292 
293         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
294         if (ret) {
295                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
296                 goto free_freq_table;
297         }
298 
299         of_node_put(np);
300         return 0;
301 
302 free_freq_table:
303         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
304 put_node:
305         of_node_put(np);
306         return ret;
307 }
308 
309 static int imx6q_cpufreq_remove(struct platform_device *pdev)
310 {
311         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
312         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
313 
314         return 0;
315 }
316 
317 static struct platform_driver imx6q_cpufreq_platdrv = {
318         .driver = {
319                 .name   = "imx6q-cpufreq",
320                 .owner  = THIS_MODULE,
321         },
322         .probe          = imx6q_cpufreq_probe,
323         .remove         = imx6q_cpufreq_remove,
324 };
325 module_platform_driver(imx6q_cpufreq_platdrv);
326 
327 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
328 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
329 MODULE_LICENSE("GPL");
330 

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