Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/cpufreq/imx6q-cpufreq.c

  1 /*
  2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3  *
  4  * This program is free software; you can redistribute it and/or modify
  5  * it under the terms of the GNU General Public License version 2 as
  6  * published by the Free Software Foundation.
  7  */
  8 
  9 #include <linux/clk.h>
 10 #include <linux/cpu.h>
 11 #include <linux/cpufreq.h>
 12 #include <linux/err.h>
 13 #include <linux/module.h>
 14 #include <linux/of.h>
 15 #include <linux/pm_opp.h>
 16 #include <linux/platform_device.h>
 17 #include <linux/regulator/consumer.h>
 18 
 19 #define PU_SOC_VOLTAGE_NORMAL   1250000
 20 #define PU_SOC_VOLTAGE_HIGH     1275000
 21 #define FREQ_1P2_GHZ            1200000000
 22 
 23 static struct regulator *arm_reg;
 24 static struct regulator *pu_reg;
 25 static struct regulator *soc_reg;
 26 
 27 static struct clk *arm_clk;
 28 static struct clk *pll1_sys_clk;
 29 static struct clk *pll1_sw_clk;
 30 static struct clk *step_clk;
 31 static struct clk *pll2_pfd2_396m_clk;
 32 
 33 /* clk used by i.MX6UL */
 34 static struct clk *pll2_bus_clk;
 35 static struct clk *secondary_sel_clk;
 36 
 37 static struct device *cpu_dev;
 38 static bool free_opp;
 39 static struct cpufreq_frequency_table *freq_table;
 40 static unsigned int transition_latency;
 41 
 42 static u32 *imx6_soc_volt;
 43 static u32 soc_opp_count;
 44 
 45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
 46 {
 47         struct dev_pm_opp *opp;
 48         unsigned long freq_hz, volt, volt_old;
 49         unsigned int old_freq, new_freq;
 50         int ret;
 51 
 52         new_freq = freq_table[index].frequency;
 53         freq_hz = new_freq * 1000;
 54         old_freq = clk_get_rate(arm_clk) / 1000;
 55 
 56         rcu_read_lock();
 57         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
 58         if (IS_ERR(opp)) {
 59                 rcu_read_unlock();
 60                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
 61                 return PTR_ERR(opp);
 62         }
 63 
 64         volt = dev_pm_opp_get_voltage(opp);
 65         rcu_read_unlock();
 66         volt_old = regulator_get_voltage(arm_reg);
 67 
 68         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
 69                 old_freq / 1000, volt_old / 1000,
 70                 new_freq / 1000, volt / 1000);
 71 
 72         /* scaling up?  scale voltage before frequency */
 73         if (new_freq > old_freq) {
 74                 if (!IS_ERR(pu_reg)) {
 75                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
 76                         if (ret) {
 77                                 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
 78                                 return ret;
 79                         }
 80                 }
 81                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
 82                 if (ret) {
 83                         dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
 84                         return ret;
 85                 }
 86                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 87                 if (ret) {
 88                         dev_err(cpu_dev,
 89                                 "failed to scale vddarm up: %d\n", ret);
 90                         return ret;
 91                 }
 92         }
 93 
 94         /*
 95          * The setpoints are selected per PLL/PDF frequencies, so we need to
 96          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 97          * PLL1 is as below.
 98          * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
 99          * flow is slightly different from other i.MX6 OSC.
100          * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
101          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
102          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
103          *  - Disable pll2_pfd2_396m_clk
104          */
105         if (of_machine_is_compatible("fsl,imx6ul")) {
106                 /*
107                  * When changing pll1_sw_clk's parent to pll1_sys_clk,
108                  * CPU may run at higher than 528MHz, this will lead to
109                  * the system unstable if the voltage is lower than the
110                  * voltage of 528MHz, so lower the CPU frequency to one
111                  * half before changing CPU frequency.
112                  */
113                 clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
114                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
115                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
116                         clk_set_parent(secondary_sel_clk, pll2_bus_clk);
117                 else
118                         clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
119                 clk_set_parent(step_clk, secondary_sel_clk);
120                 clk_set_parent(pll1_sw_clk, step_clk);
121         } else {
122                 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
123                 clk_set_parent(pll1_sw_clk, step_clk);
124                 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
125                         clk_set_rate(pll1_sys_clk, new_freq * 1000);
126                         clk_set_parent(pll1_sw_clk, pll1_sys_clk);
127                 }
128         }
129 
130         /* Ensure the arm clock divider is what we expect */
131         ret = clk_set_rate(arm_clk, new_freq * 1000);
132         if (ret) {
133                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
134                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
135                 return ret;
136         }
137 
138         /* scaling down?  scale voltage after frequency */
139         if (new_freq < old_freq) {
140                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
141                 if (ret) {
142                         dev_warn(cpu_dev,
143                                  "failed to scale vddarm down: %d\n", ret);
144                         ret = 0;
145                 }
146                 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
147                 if (ret) {
148                         dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
149                         ret = 0;
150                 }
151                 if (!IS_ERR(pu_reg)) {
152                         ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
153                         if (ret) {
154                                 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
155                                 ret = 0;
156                         }
157                 }
158         }
159 
160         return 0;
161 }
162 
163 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
164 {
165         policy->clk = arm_clk;
166         return cpufreq_generic_init(policy, freq_table, transition_latency);
167 }
168 
169 static struct cpufreq_driver imx6q_cpufreq_driver = {
170         .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
171         .verify = cpufreq_generic_frequency_table_verify,
172         .target_index = imx6q_set_target,
173         .get = cpufreq_generic_get,
174         .init = imx6q_cpufreq_init,
175         .name = "imx6q-cpufreq",
176         .attr = cpufreq_generic_attr,
177 };
178 
179 static int imx6q_cpufreq_probe(struct platform_device *pdev)
180 {
181         struct device_node *np;
182         struct dev_pm_opp *opp;
183         unsigned long min_volt, max_volt;
184         int num, ret;
185         const struct property *prop;
186         const __be32 *val;
187         u32 nr, i, j;
188 
189         cpu_dev = get_cpu_device(0);
190         if (!cpu_dev) {
191                 pr_err("failed to get cpu0 device\n");
192                 return -ENODEV;
193         }
194 
195         np = of_node_get(cpu_dev->of_node);
196         if (!np) {
197                 dev_err(cpu_dev, "failed to find cpu0 node\n");
198                 return -ENOENT;
199         }
200 
201         arm_clk = clk_get(cpu_dev, "arm");
202         pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
203         pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
204         step_clk = clk_get(cpu_dev, "step");
205         pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
206         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
207             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
208                 dev_err(cpu_dev, "failed to get clocks\n");
209                 ret = -ENOENT;
210                 goto put_clk;
211         }
212 
213         if (of_machine_is_compatible("fsl,imx6ul")) {
214                 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus");
215                 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel");
216                 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) {
217                         dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n");
218                         ret = -ENOENT;
219                         goto put_clk;
220                 }
221         }
222 
223         arm_reg = regulator_get(cpu_dev, "arm");
224         pu_reg = regulator_get_optional(cpu_dev, "pu");
225         soc_reg = regulator_get(cpu_dev, "soc");
226         if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
227                 dev_err(cpu_dev, "failed to get regulators\n");
228                 ret = -ENOENT;
229                 goto put_reg;
230         }
231 
232         /*
233          * We expect an OPP table supplied by platform.
234          * Just, incase the platform did not supply the OPP
235          * table, it will try to get it.
236          */
237         num = dev_pm_opp_get_opp_count(cpu_dev);
238         if (num < 0) {
239                 ret = dev_pm_opp_of_add_table(cpu_dev);
240                 if (ret < 0) {
241                         dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
242                         goto put_reg;
243                 }
244 
245                 /* Because we have added the OPPs here, we must free them */
246                 free_opp = true;
247 
248                 num = dev_pm_opp_get_opp_count(cpu_dev);
249                 if (num < 0) {
250                         ret = num;
251                         dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
252                         goto out_free_opp;
253                 }
254         }
255 
256         ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
257         if (ret) {
258                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
259                 goto put_reg;
260         }
261 
262         /* Make imx6_soc_volt array's size same as arm opp number */
263         imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
264         if (imx6_soc_volt == NULL) {
265                 ret = -ENOMEM;
266                 goto free_freq_table;
267         }
268 
269         prop = of_find_property(np, "fsl,soc-operating-points", NULL);
270         if (!prop || !prop->value)
271                 goto soc_opp_out;
272 
273         /*
274          * Each OPP is a set of tuples consisting of frequency and
275          * voltage like <freq-kHz vol-uV>.
276          */
277         nr = prop->length / sizeof(u32);
278         if (nr % 2 || (nr / 2) < num)
279                 goto soc_opp_out;
280 
281         for (j = 0; j < num; j++) {
282                 val = prop->value;
283                 for (i = 0; i < nr / 2; i++) {
284                         unsigned long freq = be32_to_cpup(val++);
285                         unsigned long volt = be32_to_cpup(val++);
286                         if (freq_table[j].frequency == freq) {
287                                 imx6_soc_volt[soc_opp_count++] = volt;
288                                 break;
289                         }
290                 }
291         }
292 
293 soc_opp_out:
294         /* use fixed soc opp volt if no valid soc opp info found in dtb */
295         if (soc_opp_count != num) {
296                 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
297                 for (j = 0; j < num; j++)
298                         imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
299                 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
300                         imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
301         }
302 
303         if (of_property_read_u32(np, "clock-latency", &transition_latency))
304                 transition_latency = CPUFREQ_ETERNAL;
305 
306         /*
307          * Calculate the ramp time for max voltage change in the
308          * VDDSOC and VDDPU regulators.
309          */
310         ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
311         if (ret > 0)
312                 transition_latency += ret * 1000;
313         if (!IS_ERR(pu_reg)) {
314                 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
315                 if (ret > 0)
316                         transition_latency += ret * 1000;
317         }
318 
319         /*
320          * OPP is maintained in order of increasing frequency, and
321          * freq_table initialised from OPP is therefore sorted in the
322          * same order.
323          */
324         rcu_read_lock();
325         opp = dev_pm_opp_find_freq_exact(cpu_dev,
326                                   freq_table[0].frequency * 1000, true);
327         min_volt = dev_pm_opp_get_voltage(opp);
328         opp = dev_pm_opp_find_freq_exact(cpu_dev,
329                                   freq_table[--num].frequency * 1000, true);
330         max_volt = dev_pm_opp_get_voltage(opp);
331         rcu_read_unlock();
332         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
333         if (ret > 0)
334                 transition_latency += ret * 1000;
335 
336         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
337         if (ret) {
338                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
339                 goto free_freq_table;
340         }
341 
342         of_node_put(np);
343         return 0;
344 
345 free_freq_table:
346         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
347 out_free_opp:
348         if (free_opp)
349                 dev_pm_opp_of_remove_table(cpu_dev);
350 put_reg:
351         if (!IS_ERR(arm_reg))
352                 regulator_put(arm_reg);
353         if (!IS_ERR(pu_reg))
354                 regulator_put(pu_reg);
355         if (!IS_ERR(soc_reg))
356                 regulator_put(soc_reg);
357 put_clk:
358         if (!IS_ERR(arm_clk))
359                 clk_put(arm_clk);
360         if (!IS_ERR(pll1_sys_clk))
361                 clk_put(pll1_sys_clk);
362         if (!IS_ERR(pll1_sw_clk))
363                 clk_put(pll1_sw_clk);
364         if (!IS_ERR(step_clk))
365                 clk_put(step_clk);
366         if (!IS_ERR(pll2_pfd2_396m_clk))
367                 clk_put(pll2_pfd2_396m_clk);
368         if (!IS_ERR(pll2_bus_clk))
369                 clk_put(pll2_bus_clk);
370         if (!IS_ERR(secondary_sel_clk))
371                 clk_put(secondary_sel_clk);
372         of_node_put(np);
373         return ret;
374 }
375 
376 static int imx6q_cpufreq_remove(struct platform_device *pdev)
377 {
378         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
379         dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
380         if (free_opp)
381                 dev_pm_opp_of_remove_table(cpu_dev);
382         regulator_put(arm_reg);
383         if (!IS_ERR(pu_reg))
384                 regulator_put(pu_reg);
385         regulator_put(soc_reg);
386         clk_put(arm_clk);
387         clk_put(pll1_sys_clk);
388         clk_put(pll1_sw_clk);
389         clk_put(step_clk);
390         clk_put(pll2_pfd2_396m_clk);
391         clk_put(pll2_bus_clk);
392         clk_put(secondary_sel_clk);
393 
394         return 0;
395 }
396 
397 static struct platform_driver imx6q_cpufreq_platdrv = {
398         .driver = {
399                 .name   = "imx6q-cpufreq",
400         },
401         .probe          = imx6q_cpufreq_probe,
402         .remove         = imx6q_cpufreq_remove,
403 };
404 module_platform_driver(imx6q_cpufreq_platdrv);
405 
406 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
407 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
408 MODULE_LICENSE("GPL");
409 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us