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Linux/drivers/clocksource/sh_cmt.c

  1 /*
  2  * SuperH Timer Support - CMT
  3  *
  4  *  Copyright (C) 2008 Magnus Damm
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License
  9  *
 10  * This program is distributed in the hope that it will be useful,
 11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13  * GNU General Public License for more details.
 14  */
 15 
 16 #include <linux/clk.h>
 17 #include <linux/clockchips.h>
 18 #include <linux/clocksource.h>
 19 #include <linux/delay.h>
 20 #include <linux/err.h>
 21 #include <linux/init.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/io.h>
 24 #include <linux/ioport.h>
 25 #include <linux/irq.h>
 26 #include <linux/module.h>
 27 #include <linux/of.h>
 28 #include <linux/platform_device.h>
 29 #include <linux/pm_domain.h>
 30 #include <linux/pm_runtime.h>
 31 #include <linux/sh_timer.h>
 32 #include <linux/slab.h>
 33 #include <linux/spinlock.h>
 34 
 35 struct sh_cmt_device;
 36 
 37 /*
 38  * The CMT comes in 5 different identified flavours, depending not only on the
 39  * SoC but also on the particular instance. The following table lists the main
 40  * characteristics of those flavours.
 41  *
 42  *                      16B     32B     32B-F   48B     48B-2
 43  * -----------------------------------------------------------------------------
 44  * Channels             2       1/4     1       6       2/8
 45  * Control Width        16      16      16      16      32
 46  * Counter Width        16      32      32      32/48   32/48
 47  * Shared Start/Stop    Y       Y       Y       Y       N
 48  *
 49  * The 48-bit gen2 version has a per-channel start/stop register located in the
 50  * channel registers block. All other versions have a shared start/stop register
 51  * located in the global space.
 52  *
 53  * Channels are indexed from 0 to N-1 in the documentation. The channel index
 54  * infers the start/stop bit position in the control register and the channel
 55  * registers block address. Some CMT instances have a subset of channels
 56  * available, in which case the index in the documentation doesn't match the
 57  * "real" index as implemented in hardware. This is for instance the case with
 58  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
 59  * in the documentation but using start/stop bit 5 and having its registers
 60  * block at 0x60.
 61  *
 62  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
 63  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
 64  */
 65 
 66 enum sh_cmt_model {
 67         SH_CMT_16BIT,
 68         SH_CMT_32BIT,
 69         SH_CMT_32BIT_FAST,
 70         SH_CMT_48BIT,
 71         SH_CMT_48BIT_GEN2,
 72 };
 73 
 74 struct sh_cmt_info {
 75         enum sh_cmt_model model;
 76 
 77         unsigned long width; /* 16 or 32 bit version of hardware block */
 78         unsigned long overflow_bit;
 79         unsigned long clear_bits;
 80 
 81         /* callbacks for CMSTR and CMCSR access */
 82         unsigned long (*read_control)(void __iomem *base, unsigned long offs);
 83         void (*write_control)(void __iomem *base, unsigned long offs,
 84                               unsigned long value);
 85 
 86         /* callbacks for CMCNT and CMCOR access */
 87         unsigned long (*read_count)(void __iomem *base, unsigned long offs);
 88         void (*write_count)(void __iomem *base, unsigned long offs,
 89                             unsigned long value);
 90 };
 91 
 92 struct sh_cmt_channel {
 93         struct sh_cmt_device *cmt;
 94 
 95         unsigned int index;     /* Index in the documentation */
 96         unsigned int hwidx;     /* Real hardware index */
 97 
 98         void __iomem *iostart;
 99         void __iomem *ioctrl;
100 
101         unsigned int timer_bit;
102         unsigned long flags;
103         unsigned long match_value;
104         unsigned long next_match_value;
105         unsigned long max_match_value;
106         unsigned long rate;
107         raw_spinlock_t lock;
108         struct clock_event_device ced;
109         struct clocksource cs;
110         unsigned long total_cycles;
111         bool cs_enabled;
112 };