Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/clocksource/arm_arch_timer.c

  1 /*
  2  *  linux/drivers/clocksource/arm_arch_timer.c
  3  *
  4  *  Copyright (C) 2011 ARM Ltd.
  5  *  All Rights Reserved
  6  *
  7  * This program is free software; you can redistribute it and/or modify
  8  * it under the terms of the GNU General Public License version 2 as
  9  * published by the Free Software Foundation.
 10  */
 11 #include <linux/init.h>
 12 #include <linux/kernel.h>
 13 #include <linux/device.h>
 14 #include <linux/smp.h>
 15 #include <linux/cpu.h>
 16 #include <linux/cpu_pm.h>
 17 #include <linux/clockchips.h>
 18 #include <linux/interrupt.h>
 19 #include <linux/of_irq.h>
 20 #include <linux/of_address.h>
 21 #include <linux/io.h>
 22 #include <linux/slab.h>
 23 #include <linux/sched_clock.h>
 24 
 25 #include <asm/arch_timer.h>
 26 #include <asm/virt.h>
 27 
 28 #include <clocksource/arm_arch_timer.h>
 29 
 30 #define CNTTIDR         0x08
 31 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
 32 
 33 #define CNTVCT_LO       0x08
 34 #define CNTVCT_HI       0x0c
 35 #define CNTFRQ          0x10
 36 #define CNTP_TVAL       0x28
 37 #define CNTP_CTL        0x2c
 38 #define CNTV_TVAL       0x38
 39 #define CNTV_CTL        0x3c
 40 
 41 #define ARCH_CP15_TIMER BIT(0)
 42 #define ARCH_MEM_TIMER  BIT(1)
 43 static unsigned arch_timers_present __initdata;
 44 
 45 static void __iomem *arch_counter_base;
 46 
 47 struct arch_timer {
 48         void __iomem *base;
 49         struct clock_event_device evt;
 50 };
 51 
 52 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
 53 
 54 static u32 arch_timer_rate;
 55 
 56 enum ppi_nr {
 57         PHYS_SECURE_PPI,
 58         PHYS_NONSECURE_PPI,
 59         VIRT_PPI,
 60         HYP_PPI,
 61         MAX_TIMER_PPI
 62 };
 63 
 64 static int arch_timer_ppi[MAX_TIMER_PPI];
 65 
 66 static struct clock_event_device __percpu *arch_timer_evt;
 67 
 68 static bool arch_timer_use_virtual = true;
 69 static bool arch_timer_c3stop;
 70 static bool arch_timer_mem_use_virtual;
 71 
 72 /*
 73  * Architected system timer support.
 74  */
 75 
 76 static __always_inline
 77 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
 78                           struct clock_event_device *clk)
 79 {
 80         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 81                 struct arch_timer *timer = to_arch_timer(clk);
 82                 switch (reg) {
 83                 case ARCH_TIMER_REG_CTRL:
 84                         writel_relaxed(val, timer->base + CNTP_CTL);
 85                         break;
 86                 case ARCH_TIMER_REG_TVAL:
 87                         writel_relaxed(val, timer->base + CNTP_TVAL);
 88                         break;
 89                 }
 90         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 91                 struct arch_timer *timer = to_arch_timer(clk);
 92                 switch (reg) {
 93                 case ARCH_TIMER_REG_CTRL:
 94                         writel_relaxed(val, timer->base + CNTV_CTL);
 95                         break;
 96                 case ARCH_TIMER_REG_TVAL:
 97                         writel_relaxed(val, timer->base + CNTV_TVAL);
 98                         break;
 99                 }
100         } else {
101                 arch_timer_reg_write_cp15(access, reg, val);
102         }
103 }
104 
105 static __always_inline
106 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
107                         struct clock_event_device *clk)
108 {
109         u32 val;
110 
111         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
112                 struct arch_timer *timer = to_arch_timer(clk);
113                 switch (reg) {
114                 case ARCH_TIMER_REG_CTRL:
115                         val = readl_relaxed(timer->base + CNTP_CTL);
116                         break;
117                 case ARCH_TIMER_REG_TVAL:
118                         val = readl_relaxed(timer->base + CNTP_TVAL);
119                         break;
120                 }
121         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
122                 struct arch_timer *timer = to_arch_timer(clk);
123                 switch (reg) {
124                 case ARCH_TIMER_REG_CTRL:
125                         val = readl_relaxed(timer->base + CNTV_CTL);
126                         break;
127                 case ARCH_TIMER_REG_TVAL:
128                         val = readl_relaxed(timer->base + CNTV_TVAL);
129                         break;
130                 }
131         } else {
132                 val = arch_timer_reg_read_cp15(access, reg);
133         }
134 
135         return val;
136 }
137 
138 static __always_inline irqreturn_t timer_handler(const int access,
139                                         struct clock_event_device *evt)
140 {
141         unsigned long ctrl;
142 
143         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
144         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
145                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
146                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
147                 evt->event_handler(evt);
148                 return IRQ_HANDLED;
149         }
150 
151         return IRQ_NONE;
152 }
153 
154 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
155 {
156         struct clock_event_device *evt = dev_id;
157 
158         return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
159 }
160 
161 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
162 {
163         struct clock_event_device *evt = dev_id;
164 
165         return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
166 }
167 
168 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
169 {
170         struct clock_event_device *evt = dev_id;
171 
172         return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
173 }
174 
175 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
176 {
177         struct clock_event_device *evt = dev_id;
178 
179         return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
180 }
181 
182 static __always_inline void timer_set_mode(const int access, int mode,
183                                   struct clock_event_device *clk)
184 {
185         unsigned long ctrl;
186         switch (mode) {
187         case CLOCK_EVT_MODE_UNUSED:
188         case CLOCK_EVT_MODE_SHUTDOWN:
189                 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
190                 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
191                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
192                 break;
193         default:
194                 break;
195         }
196 }
197 
198 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
199                                      struct clock_event_device *clk)
200 {
201         timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
202 }
203 
204 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
205                                      struct clock_event_device *clk)
206 {
207         timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
208 }
209 
210 static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
211                                          struct clock_event_device *clk)
212 {
213         timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
214 }
215 
216 static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
217                                          struct clock_event_device *clk)
218 {
219         timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
220 }
221 
222 static __always_inline void set_next_event(const int access, unsigned long evt,
223                                            struct clock_event_device *clk)
224 {
225         unsigned long ctrl;
226         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
227         ctrl |= ARCH_TIMER_CTRL_ENABLE;
228         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
229         arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
230         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
231 }
232 
233 static int arch_timer_set_next_event_virt(unsigned long evt,
234                                           struct clock_event_device *clk)
235 {
236         set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
237         return 0;
238 }
239 
240 static int arch_timer_set_next_event_phys(unsigned long evt,
241                                           struct clock_event_device *clk)
242 {
243         set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
244         return 0;
245 }
246 
247 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
248                                               struct clock_event_device *clk)
249 {
250         set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
251         return 0;
252 }
253 
254 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
255                                               struct clock_event_device *clk)
256 {
257         set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
258         return 0;
259 }
260 
261 static void __arch_timer_setup(unsigned type,
262                                struct clock_event_device *clk)
263 {
264         clk->features = CLOCK_EVT_FEAT_ONESHOT;
265 
266         if (type == ARCH_CP15_TIMER) {
267                 if (arch_timer_c3stop)
268                         clk->features |= CLOCK_EVT_FEAT_C3STOP;
269                 clk->name = "arch_sys_timer";
270                 clk->rating = 450;
271                 clk->cpumask = cpumask_of(smp_processor_id());
272                 if (arch_timer_use_virtual) {
273                         clk->irq = arch_timer_ppi[VIRT_PPI];
274                         clk->set_mode = arch_timer_set_mode_virt;
275                         clk->set_next_event = arch_timer_set_next_event_virt;
276                 } else {
277                         clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
278                         clk->set_mode = arch_timer_set_mode_phys;
279                         clk->set_next_event = arch_timer_set_next_event_phys;
280                 }
281         } else {
282                 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
283                 clk->name = "arch_mem_timer";
284                 clk->rating = 400;
285                 clk->cpumask = cpu_all_mask;
286                 if (arch_timer_mem_use_virtual) {
287                         clk->set_mode = arch_timer_set_mode_virt_mem;
288                         clk->set_next_event =
289                                 arch_timer_set_next_event_virt_mem;
290                 } else {
291                         clk->set_mode = arch_timer_set_mode_phys_mem;
292                         clk->set_next_event =
293                                 arch_timer_set_next_event_phys_mem;
294                 }
295         }
296 
297         clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
298 
299         clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
300 }
301 
302 static void arch_timer_configure_evtstream(void)
303 {
304         int evt_stream_div, pos;
305 
306         /* Find the closest power of two to the divisor */
307         evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
308         pos = fls(evt_stream_div);
309         if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
310                 pos--;
311         /* enable event stream */
312         arch_timer_evtstrm_enable(min(pos, 15));
313 }
314 
315 static int arch_timer_setup(struct clock_event_device *clk)
316 {
317         __arch_timer_setup(ARCH_CP15_TIMER, clk);
318 
319         if (arch_timer_use_virtual)
320                 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
321         else {
322                 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
323                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
324                         enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
325         }
326 
327         arch_counter_set_user_access();
328         if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
329                 arch_timer_configure_evtstream();
330 
331         return 0;
332 }
333 
334 static void
335 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
336 {
337         /* Who has more than one independent system counter? */
338         if (arch_timer_rate)
339                 return;
340 
341         /* Try to determine the frequency from the device tree or CNTFRQ */
342         if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
343                 if (cntbase)
344                         arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
345                 else
346                         arch_timer_rate = arch_timer_get_cntfrq();
347         }
348 
349         /* Check the timer frequency. */
350         if (arch_timer_rate == 0)
351                 pr_warn("Architected timer frequency not available\n");
352 }
353 
354 static void arch_timer_banner(unsigned type)
355 {
356         pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
357                      type & ARCH_CP15_TIMER ? "cp15" : "",
358                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  " and " : "",
359                      type & ARCH_MEM_TIMER ? "mmio" : "",
360                      (unsigned long)arch_timer_rate / 1000000,
361                      (unsigned long)(arch_timer_rate / 10000) % 100,
362                      type & ARCH_CP15_TIMER ?
363                         arch_timer_use_virtual ? "virt" : "phys" :
364                         "",
365                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  "/" : "",
366                      type & ARCH_MEM_TIMER ?
367                         arch_timer_mem_use_virtual ? "virt" : "phys" :
368                         "");
369 }
370 
371 u32 arch_timer_get_rate(void)
372 {
373         return arch_timer_rate;
374 }
375 
376 static u64 arch_counter_get_cntvct_mem(void)
377 {
378         u32 vct_lo, vct_hi, tmp_hi;
379 
380         do {
381                 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
382                 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
383                 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
384         } while (vct_hi != tmp_hi);
385 
386         return ((u64) vct_hi << 32) | vct_lo;
387 }
388 
389 /*
390  * Default to cp15 based access because arm64 uses this function for
391  * sched_clock() before DT is probed and the cp15 method is guaranteed
392  * to exist on arm64. arm doesn't use this before DT is probed so even
393  * if we don't have the cp15 accessors we won't have a problem.
394  */
395 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
396 
397 static cycle_t arch_counter_read(struct clocksource *cs)
398 {
399         return arch_timer_read_counter();
400 }
401 
402 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
403 {
404         return arch_timer_read_counter();
405 }
406 
407 static struct clocksource clocksource_counter = {
408         .name   = "arch_sys_counter",
409         .rating = 400,
410         .read   = arch_counter_read,
411         .mask   = CLOCKSOURCE_MASK(56),
412         .flags  = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
413 };
414 
415 static struct cyclecounter cyclecounter = {
416         .read   = arch_counter_read_cc,
417         .mask   = CLOCKSOURCE_MASK(56),
418 };
419 
420 static struct timecounter timecounter;
421 
422 struct timecounter *arch_timer_get_timecounter(void)
423 {
424         return &timecounter;
425 }
426 
427 static void __init arch_counter_register(unsigned type)
428 {
429         u64 start_count;
430 
431         /* Register the CP15 based counter if we have one */
432         if (type & ARCH_CP15_TIMER)
433                 arch_timer_read_counter = arch_counter_get_cntvct;
434         else
435                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
436 
437         start_count = arch_timer_read_counter();
438         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
439         cyclecounter.mult = clocksource_counter.mult;
440         cyclecounter.shift = clocksource_counter.shift;
441         timecounter_init(&timecounter, &cyclecounter, start_count);
442 
443         /* 56 bits minimum, so we assume worst case rollover */
444         sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
445 }
446 
447 static void arch_timer_stop(struct clock_event_device *clk)
448 {
449         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
450                  clk->irq, smp_processor_id());
451 
452         if (arch_timer_use_virtual)
453                 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
454         else {
455                 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
456                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
457                         disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
458         }
459 
460         clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
461 }
462 
463 static int arch_timer_cpu_notify(struct notifier_block *self,
464                                            unsigned long action, void *hcpu)
465 {
466         /*
467          * Grab cpu pointer in each case to avoid spurious
468          * preemptible warnings
469          */
470         switch (action & ~CPU_TASKS_FROZEN) {
471         case CPU_STARTING:
472                 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
473                 break;
474         case CPU_DYING:
475                 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
476                 break;
477         }
478 
479         return NOTIFY_OK;
480 }
481 
482 static struct notifier_block arch_timer_cpu_nb = {
483         .notifier_call = arch_timer_cpu_notify,
484 };
485 
486 #ifdef CONFIG_CPU_PM
487 static unsigned int saved_cntkctl;
488 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
489                                     unsigned long action, void *hcpu)
490 {
491         if (action == CPU_PM_ENTER)
492                 saved_cntkctl = arch_timer_get_cntkctl();
493         else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
494                 arch_timer_set_cntkctl(saved_cntkctl);
495         return NOTIFY_OK;
496 }
497 
498 static struct notifier_block arch_timer_cpu_pm_notifier = {
499         .notifier_call = arch_timer_cpu_pm_notify,
500 };
501 
502 static int __init arch_timer_cpu_pm_init(void)
503 {
504         return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
505 }
506 #else
507 static int __init arch_timer_cpu_pm_init(void)
508 {
509         return 0;
510 }
511 #endif
512 
513 static int __init arch_timer_register(void)
514 {
515         int err;
516         int ppi;
517 
518         arch_timer_evt = alloc_percpu(struct clock_event_device);
519         if (!arch_timer_evt) {
520                 err = -ENOMEM;
521                 goto out;
522         }
523 
524         if (arch_timer_use_virtual) {
525                 ppi = arch_timer_ppi[VIRT_PPI];
526                 err = request_percpu_irq(ppi, arch_timer_handler_virt,
527                                          "arch_timer", arch_timer_evt);
528         } else {
529                 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
530                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
531                                          "arch_timer", arch_timer_evt);
532                 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
533                         ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
534                         err = request_percpu_irq(ppi, arch_timer_handler_phys,
535                                                  "arch_timer", arch_timer_evt);
536                         if (err)
537                                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
538                                                 arch_timer_evt);
539                 }
540         }
541 
542         if (err) {
543                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
544                        ppi, err);
545                 goto out_free;
546         }
547 
548         err = register_cpu_notifier(&arch_timer_cpu_nb);
549         if (err)
550                 goto out_free_irq;
551 
552         err = arch_timer_cpu_pm_init();
553         if (err)
554                 goto out_unreg_notify;
555 
556         /* Immediately configure the timer on the boot CPU */
557         arch_timer_setup(this_cpu_ptr(arch_timer_evt));
558 
559         return 0;
560 
561 out_unreg_notify:
562         unregister_cpu_notifier(&arch_timer_cpu_nb);
563 out_free_irq:
564         if (arch_timer_use_virtual)
565                 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
566         else {
567                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
568                                 arch_timer_evt);
569                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
570                         free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
571                                         arch_timer_evt);
572         }
573 
574 out_free:
575         free_percpu(arch_timer_evt);
576 out:
577         return err;
578 }
579 
580 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
581 {
582         int ret;
583         irq_handler_t func;
584         struct arch_timer *t;
585 
586         t = kzalloc(sizeof(*t), GFP_KERNEL);
587         if (!t)
588                 return -ENOMEM;
589 
590         t->base = base;
591         t->evt.irq = irq;
592         __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
593 
594         if (arch_timer_mem_use_virtual)
595                 func = arch_timer_handler_virt_mem;
596         else
597                 func = arch_timer_handler_phys_mem;
598 
599         ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
600         if (ret) {
601                 pr_err("arch_timer: Failed to request mem timer irq\n");
602                 kfree(t);
603         }
604 
605         return ret;
606 }
607 
608 static const struct of_device_id arch_timer_of_match[] __initconst = {
609         { .compatible   = "arm,armv7-timer",    },
610         { .compatible   = "arm,armv8-timer",    },
611         {},
612 };
613 
614 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
615         { .compatible   = "arm,armv7-timer-mem", },
616         {},
617 };
618 
619 static void __init arch_timer_common_init(void)
620 {
621         unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
622 
623         /* Wait until both nodes are probed if we have two timers */
624         if ((arch_timers_present & mask) != mask) {
625                 if (of_find_matching_node(NULL, arch_timer_mem_of_match) &&
626                                 !(arch_timers_present & ARCH_MEM_TIMER))
627                         return;
628                 if (of_find_matching_node(NULL, arch_timer_of_match) &&
629                                 !(arch_timers_present & ARCH_CP15_TIMER))
630                         return;
631         }
632 
633         arch_timer_banner(arch_timers_present);
634         arch_counter_register(arch_timers_present);
635         arch_timer_arch_init();
636 }
637 
638 static void __init arch_timer_init(struct device_node *np)
639 {
640         int i;
641 
642         if (arch_timers_present & ARCH_CP15_TIMER) {
643                 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
644                 return;
645         }
646 
647         arch_timers_present |= ARCH_CP15_TIMER;
648         for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
649                 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
650         arch_timer_detect_rate(NULL, np);
651 
652         /*
653          * If HYP mode is available, we know that the physical timer
654          * has been configured to be accessible from PL1. Use it, so
655          * that a guest can use the virtual timer instead.
656          *
657          * If no interrupt provided for virtual timer, we'll have to
658          * stick to the physical timer. It'd better be accessible...
659          */
660         if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
661                 arch_timer_use_virtual = false;
662 
663                 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
664                     !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
665                         pr_warn("arch_timer: No interrupt available, giving up\n");
666                         return;
667                 }
668         }
669 
670         arch_timer_c3stop = !of_property_read_bool(np, "always-on");
671 
672         arch_timer_register();
673         arch_timer_common_init();
674 }
675 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
676 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
677 
678 static void __init arch_timer_mem_init(struct device_node *np)
679 {
680         struct device_node *frame, *best_frame = NULL;
681         void __iomem *cntctlbase, *base;
682         unsigned int irq;
683         u32 cnttidr;
684 
685         arch_timers_present |= ARCH_MEM_TIMER;
686         cntctlbase = of_iomap(np, 0);
687         if (!cntctlbase) {
688                 pr_err("arch_timer: Can't find CNTCTLBase\n");
689                 return;
690         }
691 
692         cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
693         iounmap(cntctlbase);
694 
695         /*
696          * Try to find a virtual capable frame. Otherwise fall back to a
697          * physical capable frame.
698          */
699         for_each_available_child_of_node(np, frame) {
700                 int n;
701 
702                 if (of_property_read_u32(frame, "frame-number", &n)) {
703                         pr_err("arch_timer: Missing frame-number\n");
704                         of_node_put(best_frame);
705                         of_node_put(frame);
706                         return;
707                 }
708 
709                 if (cnttidr & CNTTIDR_VIRT(n)) {
710                         of_node_put(best_frame);
711                         best_frame = frame;
712                         arch_timer_mem_use_virtual = true;
713                         break;
714                 }
715                 of_node_put(best_frame);
716                 best_frame = of_node_get(frame);
717         }
718 
719         base = arch_counter_base = of_iomap(best_frame, 0);
720         if (!base) {
721                 pr_err("arch_timer: Can't map frame's registers\n");
722                 of_node_put(best_frame);
723                 return;
724         }
725 
726         if (arch_timer_mem_use_virtual)
727                 irq = irq_of_parse_and_map(best_frame, 1);
728         else
729                 irq = irq_of_parse_and_map(best_frame, 0);
730         of_node_put(best_frame);
731         if (!irq) {
732                 pr_err("arch_timer: Frame missing %s irq",
733                        arch_timer_mem_use_virtual ? "virt" : "phys");
734                 return;
735         }
736 
737         arch_timer_detect_rate(base, np);
738         arch_timer_mem_register(base, irq);
739         arch_timer_common_init();
740 }
741 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
742                        arch_timer_mem_init);
743 

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