Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/clk/tegra/clk-tegra30.c

  1 /*
  2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/delay.h>
 19 #include <linux/clk.h>
 20 #include <linux/clk-provider.h>
 21 #include <linux/clkdev.h>
 22 #include <linux/of.h>
 23 #include <linux/of_address.h>
 24 #include <linux/clk/tegra.h>
 25 
 26 #include <soc/tegra/pmc.h>
 27 
 28 #include <dt-bindings/clock/tegra30-car.h>
 29 
 30 #include "clk.h"
 31 #include "clk-id.h"
 32 
 33 #define OSC_CTRL                        0x50
 34 #define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
 35 #define OSC_CTRL_OSC_FREQ_13MHZ         (0X0<<28)
 36 #define OSC_CTRL_OSC_FREQ_19_2MHZ       (0X4<<28)
 37 #define OSC_CTRL_OSC_FREQ_12MHZ         (0X8<<28)
 38 #define OSC_CTRL_OSC_FREQ_26MHZ         (0XC<<28)
 39 #define OSC_CTRL_OSC_FREQ_16_8MHZ       (0X1<<28)
 40 #define OSC_CTRL_OSC_FREQ_38_4MHZ       (0X5<<28)
 41 #define OSC_CTRL_OSC_FREQ_48MHZ         (0X9<<28)
 42 #define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
 43 
 44 #define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
 45 #define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
 46 #define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
 47 #define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
 48 
 49 #define OSC_FREQ_DET                    0x58
 50 #define OSC_FREQ_DET_TRIG               BIT(31)
 51 
 52 #define OSC_FREQ_DET_STATUS             0x5c
 53 #define OSC_FREQ_DET_BUSY               BIT(31)
 54 #define OSC_FREQ_DET_CNT_MASK           0xffff
 55 
 56 #define CCLKG_BURST_POLICY 0x368
 57 #define SUPER_CCLKG_DIVIDER 0x36c
 58 #define CCLKLP_BURST_POLICY 0x370
 59 #define SUPER_CCLKLP_DIVIDER 0x374
 60 #define SCLK_BURST_POLICY 0x028
 61 #define SUPER_SCLK_DIVIDER 0x02c
 62 
 63 #define SYSTEM_CLK_RATE 0x030
 64 
 65 #define TEGRA30_CLK_PERIPH_BANKS        5
 66 
 67 #define PLLC_BASE 0x80
 68 #define PLLC_MISC 0x8c
 69 #define PLLM_BASE 0x90
 70 #define PLLM_MISC 0x9c
 71 #define PLLP_BASE 0xa0
 72 #define PLLP_MISC 0xac
 73 #define PLLX_BASE 0xe0
 74 #define PLLX_MISC 0xe4
 75 #define PLLD_BASE 0xd0
 76 #define PLLD_MISC 0xdc
 77 #define PLLD2_BASE 0x4b8
 78 #define PLLD2_MISC 0x4bc
 79 #define PLLE_BASE 0xe8
 80 #define PLLE_MISC 0xec
 81 #define PLLA_BASE 0xb0
 82 #define PLLA_MISC 0xbc
 83 #define PLLU_BASE 0xc0
 84 #define PLLU_MISC 0xcc
 85 
 86 #define PLL_MISC_LOCK_ENABLE 18
 87 #define PLLDU_MISC_LOCK_ENABLE 22
 88 #define PLLE_MISC_LOCK_ENABLE 9
 89 
 90 #define PLL_BASE_LOCK BIT(27)
 91 #define PLLE_MISC_LOCK BIT(11)
 92 
 93 #define PLLE_AUX 0x48c
 94 #define PLLC_OUT 0x84
 95 #define PLLM_OUT 0x94
 96 #define PLLP_OUTA 0xa4
 97 #define PLLP_OUTB 0xa8
 98 #define PLLA_OUT 0xb4
 99 
100 #define AUDIO_SYNC_CLK_I2S0 0x4a0
101 #define AUDIO_SYNC_CLK_I2S1 0x4a4
102 #define AUDIO_SYNC_CLK_I2S2 0x4a8
103 #define AUDIO_SYNC_CLK_I2S3 0x4ac
104 #define AUDIO_SYNC_CLK_I2S4 0x4b0
105 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
106 
107 #define CLK_SOURCE_SPDIF_OUT 0x108
108 #define CLK_SOURCE_PWM 0x110
109 #define CLK_SOURCE_D_AUDIO 0x3d0
110 #define CLK_SOURCE_DAM0 0x3d8
111 #define CLK_SOURCE_DAM1 0x3dc
112 #define CLK_SOURCE_DAM2 0x3e0
113 #define CLK_SOURCE_3D2 0x3b0
114 #define CLK_SOURCE_2D 0x15c
115 #define CLK_SOURCE_HDMI 0x18c
116 #define CLK_SOURCE_DSIB 0xd0
117 #define CLK_SOURCE_SE 0x42c
118 #define CLK_SOURCE_EMC 0x19c
119 
120 #define AUDIO_SYNC_DOUBLER 0x49c
121 
122 #define UTMIP_PLL_CFG2 0x488
123 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
124 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
125 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
126 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
127 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
128 
129 #define UTMIP_PLL_CFG1 0x484
130 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
131 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
132 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
133 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
134 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
135 
136 /* Tegra CPU clock and reset control regs */
137 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
138 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
139 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
140 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
141 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
142 
143 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
144 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
145 
146 #define CLK_RESET_CCLK_BURST    0x20
147 #define CLK_RESET_CCLK_DIVIDER  0x24
148 #define CLK_RESET_PLLX_BASE     0xe0
149 #define CLK_RESET_PLLX_MISC     0xe4
150 
151 #define CLK_RESET_SOURCE_CSITE  0x1d4
152 
153 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
154 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
155 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
156 #define CLK_RESET_CCLK_IDLE_POLICY              1
157 #define CLK_RESET_CCLK_RUN_POLICY               2
158 #define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
159 
160 /* PLLM override registers */
161 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
162 
163 #ifdef CONFIG_PM_SLEEP
164 static struct cpu_clk_suspend_context {
165         u32 pllx_misc;
166         u32 pllx_base;
167 
168         u32 cpu_burst;
169         u32 clk_csite_src;
170         u32 cclk_divider;
171 } tegra30_cpu_clk_sctx;
172 #endif
173 
174 static void __iomem *clk_base;
175 static void __iomem *pmc_base;
176 static unsigned long input_freq;
177 
178 static DEFINE_SPINLOCK(cml_lock);
179 static DEFINE_SPINLOCK(pll_d_lock);
180 static DEFINE_SPINLOCK(emc_lock);
181 
182 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,   \
183                             _clk_num, _gate_flags, _clk_id)     \
184         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
185                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
186                         _clk_num, _gate_flags, _clk_id)
187 
188 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
189                              _clk_num, _gate_flags, _clk_id)    \
190         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
191                         29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
192                         _clk_num, _gate_flags, _clk_id)
193 
194 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset,   \
195                             _clk_num, _gate_flags, _clk_id)     \
196         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
197                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT |          \
198                         TEGRA_DIVIDER_ROUND_UP, _clk_num,       \
199                         _gate_flags, _clk_id)
200 
201 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
202                               _mux_shift, _mux_width, _clk_num, \
203                               _gate_flags, _clk_id)                     \
204         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
205                         _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
206                         _clk_num, _gate_flags,  \
207                         _clk_id)
208 
209 static struct clk **clks;
210 
211 /*
212  * Structure defining the fields for USB UTMI clocks Parameters.
213  */
214 struct utmi_clk_param {
215         /* Oscillator Frequency in KHz */
216         u32 osc_frequency;
217         /* UTMIP PLL Enable Delay Count  */
218         u8 enable_delay_count;
219         /* UTMIP PLL Stable count */
220         u8 stable_count;
221         /*  UTMIP PLL Active delay count */
222         u8 active_delay_count;
223         /* UTMIP PLL Xtal frequency count */
224         u8 xtal_freq_count;
225 };
226 
227 static const struct utmi_clk_param utmi_parameters[] = {
228 /*      OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
229         {13000000,     0x02,       0x33,       0x05,       0x7F},
230         {19200000,     0x03,       0x4B,       0x06,       0xBB},
231         {12000000,     0x02,       0x2F,       0x04,       0x76},
232         {26000000,     0x04,       0x66,       0x09,       0xFE},
233         {16800000,     0x03,       0x41,       0x0A,       0xA4},
234 };
235 
236 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
237         { 12000000, 1040000000, 520,  6, 0, 8},
238         { 13000000, 1040000000, 480,  6, 0, 8},
239         { 16800000, 1040000000, 495,  8, 0, 8}, /* actual: 1039.5 MHz */
240         { 19200000, 1040000000, 325,  6, 0, 6},
241         { 26000000, 1040000000, 520, 13, 0, 8},
242 
243         { 12000000, 832000000, 416,  6, 0, 8},
244         { 13000000, 832000000, 832, 13, 0, 8},
245         { 16800000, 832000000, 396,  8, 0, 8},  /* actual: 831.6 MHz */
246         { 19200000, 832000000, 260,  6, 0, 8},
247         { 26000000, 832000000, 416, 13, 0, 8},
248 
249         { 12000000, 624000000, 624, 12, 0, 8},
250         { 13000000, 624000000, 624, 13, 0, 8},
251         { 16800000, 600000000, 520, 14, 0, 8},
252         { 19200000, 624000000, 520, 16, 0, 8},
253         { 26000000, 624000000, 624, 26, 0, 8},
254 
255         { 12000000, 600000000, 600, 12, 0, 8},
256         { 13000000, 600000000, 600, 13, 0, 8},
257         { 16800000, 600000000, 500, 14, 0, 8},
258         { 19200000, 600000000, 375, 12, 0, 6},
259         { 26000000, 600000000, 600, 26, 0, 8},
260 
261         { 12000000, 520000000, 520, 12, 0, 8},
262         { 13000000, 520000000, 520, 13, 0, 8},
263         { 16800000, 520000000, 495, 16, 0, 8},  /* actual: 519.75 MHz */
264         { 19200000, 520000000, 325, 12, 0, 6},
265         { 26000000, 520000000, 520, 26, 0, 8},
266 
267         { 12000000, 416000000, 416, 12, 0, 8},
268         { 13000000, 416000000, 416, 13, 0, 8},
269         { 16800000, 416000000, 396, 16, 0, 8},  /* actual: 415.8 MHz */
270         { 19200000, 416000000, 260, 12, 0, 6},
271         { 26000000, 416000000, 416, 26, 0, 8},
272         { 0, 0, 0, 0, 0, 0 },
273 };
274 
275 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
276         { 12000000, 666000000, 666, 12, 0, 8},
277         { 13000000, 666000000, 666, 13, 0, 8},
278         { 16800000, 666000000, 555, 14, 0, 8},
279         { 19200000, 666000000, 555, 16, 0, 8},
280         { 26000000, 666000000, 666, 26, 0, 8},
281         { 12000000, 600000000, 600, 12, 0, 8},
282         { 13000000, 600000000, 600, 13, 0, 8},
283         { 16800000, 600000000, 500, 14, 0, 8},
284         { 19200000, 600000000, 375, 12, 0, 6},
285         { 26000000, 600000000, 600, 26, 0, 8},
286         { 0, 0, 0, 0, 0, 0 },
287 };
288 
289 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
290         { 12000000, 216000000, 432, 12, 1, 8},
291         { 13000000, 216000000, 432, 13, 1, 8},
292         { 16800000, 216000000, 360, 14, 1, 8},
293         { 19200000, 216000000, 360, 16, 1, 8},
294         { 26000000, 216000000, 432, 26, 1, 8},
295         { 0, 0, 0, 0, 0, 0 },
296 };
297 
298 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
299         { 9600000, 564480000, 294, 5, 0, 4},
300         { 9600000, 552960000, 288, 5, 0, 4},
301         { 9600000, 24000000,  5,   2, 0, 1},
302 
303         { 28800000, 56448000, 49, 25, 0, 1},
304         { 28800000, 73728000, 64, 25, 0, 1},
305         { 28800000, 24000000,  5,  6, 0, 1},
306         { 0, 0, 0, 0, 0, 0 },
307 };
308 
309 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
310         { 12000000, 216000000, 216, 12, 0, 4},
311         { 13000000, 216000000, 216, 13, 0, 4},
312         { 16800000, 216000000, 180, 14, 0, 4},
313         { 19200000, 216000000, 180, 16, 0, 4},
314         { 26000000, 216000000, 216, 26, 0, 4},
315 
316         { 12000000, 594000000, 594, 12, 0, 8},
317         { 13000000, 594000000, 594, 13, 0, 8},
318         { 16800000, 594000000, 495, 14, 0, 8},
319         { 19200000, 594000000, 495, 16, 0, 8},
320         { 26000000, 594000000, 594, 26, 0, 8},
321 
322         { 12000000, 1000000000, 1000, 12, 0, 12},
323         { 13000000, 1000000000, 1000, 13, 0, 12},
324         { 19200000, 1000000000, 625,  12, 0, 8},
325         { 26000000, 1000000000, 1000, 26, 0, 12},
326 
327         { 0, 0, 0, 0, 0, 0 },
328 };
329 
330 static struct pdiv_map pllu_p[] = {
331         { .pdiv = 1, .hw_val = 1 },
332         { .pdiv = 2, .hw_val = 0 },
333         { .pdiv = 0, .hw_val = 0 },
334 };
335 
336 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
337         { 12000000, 480000000, 960, 12, 0, 12},
338         { 13000000, 480000000, 960, 13, 0, 12},
339         { 16800000, 480000000, 400, 7,  0, 5},
340         { 19200000, 480000000, 200, 4,  0, 3},
341         { 26000000, 480000000, 960, 26, 0, 12},
342         { 0, 0, 0, 0, 0, 0 },
343 };
344 
345 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
346         /* 1.7 GHz */
347         { 12000000, 1700000000, 850,  6,  0, 8},
348         { 13000000, 1700000000, 915,  7,  0, 8},        /* actual: 1699.2 MHz */
349         { 16800000, 1700000000, 708,  7,  0, 8},        /* actual: 1699.2 MHz */
350         { 19200000, 1700000000, 885,  10, 0, 8},        /* actual: 1699.2 MHz */
351         { 26000000, 1700000000, 850,  13, 0, 8},
352 
353         /* 1.6 GHz */
354         { 12000000, 1600000000, 800,  6,  0, 8},
355         { 13000000, 1600000000, 738,  6,  0, 8},        /* actual: 1599.0 MHz */
356         { 16800000, 1600000000, 857,  9,  0, 8},        /* actual: 1599.7 MHz */
357         { 19200000, 1600000000, 500,  6,  0, 8},
358         { 26000000, 1600000000, 800,  13, 0, 8},
359 
360         /* 1.5 GHz */
361         { 12000000, 1500000000, 750,  6,  0, 8},
362         { 13000000, 1500000000, 923,  8,  0, 8},        /* actual: 1499.8 MHz */
363         { 16800000, 1500000000, 625,  7,  0, 8},
364         { 19200000, 1500000000, 625,  8,  0, 8},
365         { 26000000, 1500000000, 750,  13, 0, 8},
366 
367         /* 1.4 GHz */
368         { 12000000, 1400000000, 700,  6,  0, 8},
369         { 13000000, 1400000000, 969,  9,  0, 8},        /* actual: 1399.7 MHz */
370         { 16800000, 1400000000, 1000, 12, 0, 8},
371         { 19200000, 1400000000, 875,  12, 0, 8},
372         { 26000000, 1400000000, 700,  13, 0, 8},
373 
374         /* 1.3 GHz */
375         { 12000000, 1300000000, 975,  9,  0, 8},
376         { 13000000, 1300000000, 1000, 10, 0, 8},
377         { 16800000, 1300000000, 928,  12, 0, 8},        /* actual: 1299.2 MHz */
378         { 19200000, 1300000000, 812,  12, 0, 8},        /* actual: 1299.2 MHz */
379         { 26000000, 1300000000, 650,  13, 0, 8},
380 
381         /* 1.2 GHz */
382         { 12000000, 1200000000, 1000, 10, 0, 8},
383         { 13000000, 1200000000, 923,  10, 0, 8},        /* actual: 1199.9 MHz */
384         { 16800000, 1200000000, 1000, 14, 0, 8},
385         { 19200000, 1200000000, 1000, 16, 0, 8},
386         { 26000000, 1200000000, 600,  13, 0, 8},
387 
388         /* 1.1 GHz */
389         { 12000000, 1100000000, 825,  9,  0, 8},
390         { 13000000, 1100000000, 846,  10, 0, 8},        /* actual: 1099.8 MHz */
391         { 16800000, 1100000000, 982,  15, 0, 8},        /* actual: 1099.8 MHz */
392         { 19200000, 1100000000, 859,  15, 0, 8},        /* actual: 1099.5 MHz */
393         { 26000000, 1100000000, 550,  13, 0, 8},
394 
395         /* 1 GHz */
396         { 12000000, 1000000000, 1000, 12, 0, 8},
397         { 13000000, 1000000000, 1000, 13, 0, 8},
398         { 16800000, 1000000000, 833,  14, 0, 8},        /* actual: 999.6 MHz */
399         { 19200000, 1000000000, 625,  12, 0, 8},
400         { 26000000, 1000000000, 1000, 26, 0, 8},
401 
402         { 0, 0, 0, 0, 0, 0 },
403 };
404 
405 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
406         /* PLLE special case: use cpcon field to store cml divider value */
407         { 12000000,  100000000, 150, 1,  18, 11},
408         { 216000000, 100000000, 200, 18, 24, 13},
409         { 0, 0, 0, 0, 0, 0 },
410 };
411 
412 /* PLL parameters */
413 static struct tegra_clk_pll_params pll_c_params = {
414         .input_min = 2000000,
415         .input_max = 31000000,
416         .cf_min = 1000000,
417         .cf_max = 6000000,
418         .vco_min = 20000000,
419         .vco_max = 1400000000,
420         .base_reg = PLLC_BASE,
421         .misc_reg = PLLC_MISC,
422         .lock_mask = PLL_BASE_LOCK,
423         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
424         .lock_delay = 300,
425         .freq_table = pll_c_freq_table,
426         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
427 };
428 
429 static struct div_nmp pllm_nmp = {
430         .divn_shift = 8,
431         .divn_width = 10,
432         .override_divn_shift = 5,
433         .divm_shift = 0,
434         .divm_width = 5,
435         .override_divm_shift = 0,
436         .divp_shift = 20,
437         .divp_width = 3,
438         .override_divp_shift = 15,
439 };
440 
441 static struct tegra_clk_pll_params pll_m_params = {
442         .input_min = 2000000,
443         .input_max = 31000000,
444         .cf_min = 1000000,
445         .cf_max = 6000000,
446         .vco_min = 20000000,
447         .vco_max = 1200000000,
448         .base_reg = PLLM_BASE,
449         .misc_reg = PLLM_MISC,
450         .lock_mask = PLL_BASE_LOCK,
451         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
452         .lock_delay = 300,
453         .div_nmp = &pllm_nmp,
454         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
455         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
456         .freq_table = pll_m_freq_table,
457         .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
458                  TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
459 };
460 
461 static struct tegra_clk_pll_params pll_p_params = {
462         .input_min = 2000000,
463         .input_max = 31000000,
464         .cf_min = 1000000,
465         .cf_max = 6000000,
466         .vco_min = 20000000,
467         .vco_max = 1400000000,
468         .base_reg = PLLP_BASE,
469         .misc_reg = PLLP_MISC,
470         .lock_mask = PLL_BASE_LOCK,
471         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
472         .lock_delay = 300,
473         .freq_table = pll_p_freq_table,
474         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
475         .fixed_rate = 408000000,
476 };
477 
478 static struct tegra_clk_pll_params pll_a_params = {
479         .input_min = 2000000,
480         .input_max = 31000000,
481         .cf_min = 1000000,
482         .cf_max = 6000000,
483         .vco_min = 20000000,
484         .vco_max = 1400000000,
485         .base_reg = PLLA_BASE,
486         .misc_reg = PLLA_MISC,
487         .lock_mask = PLL_BASE_LOCK,
488         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
489         .lock_delay = 300,
490         .freq_table = pll_a_freq_table,
491         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
492 };
493 
494 static struct tegra_clk_pll_params pll_d_params = {
495         .input_min = 2000000,
496         .input_max = 40000000,
497         .cf_min = 1000000,
498         .cf_max = 6000000,
499         .vco_min = 40000000,
500         .vco_max = 1000000000,
501         .base_reg = PLLD_BASE,
502         .misc_reg = PLLD_MISC,
503         .lock_mask = PLL_BASE_LOCK,
504         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
505         .lock_delay = 1000,
506         .freq_table = pll_d_freq_table,
507         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
508                  TEGRA_PLL_USE_LOCK,
509 
510 };
511 
512 static struct tegra_clk_pll_params pll_d2_params = {
513         .input_min = 2000000,
514         .input_max = 40000000,
515         .cf_min = 1000000,
516         .cf_max = 6000000,
517         .vco_min = 40000000,
518         .vco_max = 1000000000,
519         .base_reg = PLLD2_BASE,
520         .misc_reg = PLLD2_MISC,
521         .lock_mask = PLL_BASE_LOCK,
522         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
523         .lock_delay = 1000,
524         .freq_table = pll_d_freq_table,
525         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
526                  TEGRA_PLL_USE_LOCK,
527 };
528 
529 static struct tegra_clk_pll_params pll_u_params = {
530         .input_min = 2000000,
531         .input_max = 40000000,
532         .cf_min = 1000000,
533         .cf_max = 6000000,
534         .vco_min = 48000000,
535         .vco_max = 960000000,
536         .base_reg = PLLU_BASE,
537         .misc_reg = PLLU_MISC,
538         .lock_mask = PLL_BASE_LOCK,
539         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
540         .lock_delay = 1000,
541         .pdiv_tohw = pllu_p,
542         .freq_table = pll_u_freq_table,
543         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
544 };
545 
546 static struct tegra_clk_pll_params pll_x_params = {
547         .input_min = 2000000,
548         .input_max = 31000000,
549         .cf_min = 1000000,
550         .cf_max = 6000000,
551         .vco_min = 20000000,
552         .vco_max = 1700000000,
553         .base_reg = PLLX_BASE,
554         .misc_reg = PLLX_MISC,
555         .lock_mask = PLL_BASE_LOCK,
556         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
557         .lock_delay = 300,
558         .freq_table = pll_x_freq_table,
559         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
560                  TEGRA_PLL_USE_LOCK,
561 };
562 
563 static struct tegra_clk_pll_params pll_e_params = {
564         .input_min = 12000000,
565         .input_max = 216000000,
566         .cf_min = 12000000,
567         .cf_max = 12000000,
568         .vco_min = 1200000000,
569         .vco_max = 2400000000U,
570         .base_reg = PLLE_BASE,
571         .misc_reg = PLLE_MISC,
572         .lock_mask = PLLE_MISC_LOCK,
573         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
574         .lock_delay = 300,
575         .freq_table = pll_e_freq_table,
576         .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
577         .fixed_rate = 100000000,
578 };
579 
580 static unsigned long tegra30_input_freq[] = {
581         [0] = 13000000,
582         [1] = 16800000,
583         [4] = 19200000,
584         [5] = 38400000,
585         [8] = 12000000,
586         [9] = 48000000,
587         [12] = 260000000,
588 };
589 
590 static struct tegra_devclk devclks[] __initdata = {
591         { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
592         { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
593         { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
594         { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
595         { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
596         { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
597         { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
598         { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
599         { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
600         { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
601         { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
602         { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
603         { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
604         { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
605         { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
606         { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
607         { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
608         { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
609         { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
610         { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
611         { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
612         { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
613         { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
614         { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
615         { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
616         { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
617         { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
618         { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
619         { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
620         { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
621         { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
622         { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
623         { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
624         { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
625         { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
626         { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
627         { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
628         { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
629         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
630         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
631         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
632         { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
633         { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
634         { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
635         { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
636         { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
637         { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
638         { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
639         { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
640         { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
641         { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
642         { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
643         { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
644         { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
645         { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
646         { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
647         { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
648         { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
649         { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
650         { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
651         { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
652         { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
653         { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
654         { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
655         { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
656         { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
657         { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
658         { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
659         { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
660         { .dev_id =  "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
661         { .dev_id =  "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
662         { .dev_id =  "timer", .dt_id = TEGRA30_CLK_TIMER },
663         { .dev_id =  "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
664         { .dev_id =  "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
665         { .dev_id =  "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
666         { .dev_id =  "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
667         { .dev_id =  "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
668         { .dev_id =  "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
669         { .dev_id =  "dtv", .dt_id = TEGRA30_CLK_DTV },
670         { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
671         { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
672         { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
673         { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
674         { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
675         { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
676         { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
677         { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
678         { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
679         { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
680         { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
681         { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
682         { .con_id = "hda2codec", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
683         { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
684         { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
685         { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
686         { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
687         { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
688         { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
689         { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
690         { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
691         { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
692         { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
693         { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
694         { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
695         { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
696         { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
697         { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
698         { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
699         { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
700         { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
701         { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
702         { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
703         { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
704         { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
705         { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
706         { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
707         { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
708         { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
709         { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
710         { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
711         { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
712         { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
713         { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
714         { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
715         { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
716         { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
717         { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
718         { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
719         { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
720         { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
721         { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
722         { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
723         { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
724         { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
725         { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
726         { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
727         { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
728         { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
729         { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
730         { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
731         { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
732         { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
733         { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
734         { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
735         { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
736         { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
737         { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
738 };
739 
740 static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
741         [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
742         [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
743         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
744         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
745         [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
746         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
747         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
748         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
749         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
750         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
751         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
752         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
753         [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
754         [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
755         [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
756         [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
757         [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
758         [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
759         [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
760         [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
761         [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
762         [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
763         [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
764         [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
765         [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
766         [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
767         [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
768         [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
769         [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
770         [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
771         [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
772         [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
773         [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
774         [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
775         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
776         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
777         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
778         [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
779         [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
780         [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
781         [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
782         [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
783         [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
784         [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
785         [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
786         [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
787         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
788         [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
789         [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
790         [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
791         [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
792         [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
793         [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
794         [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
795         [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
796         [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
797         [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
798         [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
799         [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
800         [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
801         [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
802         [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
803         [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
804         [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
805         [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
806         [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
807         [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
808         [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
809         [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
810         [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
811         [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
812         [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
813         [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
814         [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
815         [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
816         [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
817         [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
818         [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
819         [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
820         [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
821         [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
822         [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
823         [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
824         [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
825         [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
826         [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
827         [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
828         [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
829         [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
830         [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
831         [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
832         [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
833         [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
834         [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
835         [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
836         [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
837         [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
838         [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
839         [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
840         [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
841         [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
842         [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
843         [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
844         [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
845         [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
846         [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
847         [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
848         [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
849         [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
850         [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
851         [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
852         [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
853         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
854         [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
855         [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
856         [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
857         [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
858         [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
859         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
860         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
861         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
862         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
863         [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
864         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
865 
866 };
867 
868 static void tegra30_utmi_param_configure(void)
869 {
870         u32 reg;
871         int i;
872 
873         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
874                 if (input_freq == utmi_parameters[i].osc_frequency)
875                         break;
876         }
877 
878         if (i >= ARRAY_SIZE(utmi_parameters)) {
879                 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
880                 return;
881         }
882 
883         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
884 
885         /* Program UTMIP PLL stable and active counts */
886         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
887         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
888                         utmi_parameters[i].stable_count);
889 
890         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
891 
892         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
893                         utmi_parameters[i].active_delay_count);
894 
895         /* Remove power downs from UTMIP PLL control bits */
896         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
897         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
898         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
899 
900         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
901 
902         /* Program UTMIP PLL delay and oscillator frequency counts */
903         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
904         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
905 
906         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
907                 utmi_parameters[i].enable_delay_count);
908 
909         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
910         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
911                 utmi_parameters[i].xtal_freq_count);
912 
913         /* Remove power downs from UTMIP PLL control bits */
914         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
915         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
916         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
917 
918         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
919 }
920 
921 static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
922 
923 static void __init tegra30_pll_init(void)
924 {
925         struct clk *clk;
926 
927         /* PLLC */
928         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
929                                 &pll_c_params, NULL);
930         clks[TEGRA30_CLK_PLL_C] = clk;
931 
932         /* PLLC_OUT1 */
933         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
934                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
935                                 8, 8, 1, NULL);
936         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
937                                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
938                                 0, NULL);
939         clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
940 
941         /* PLLM */
942         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
943                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
944                             &pll_m_params, NULL);
945         clks[TEGRA30_CLK_PLL_M] = clk;
946 
947         /* PLLM_OUT1 */
948         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
949                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
950                                 8, 8, 1, NULL);
951         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
952                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
953                                 CLK_SET_RATE_PARENT, 0, NULL);
954         clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
955 
956         /* PLLX */
957         clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
958                             &pll_x_params, NULL);
959         clks[TEGRA30_CLK_PLL_X] = clk;
960 
961         /* PLLX_OUT0 */
962         clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
963                                         CLK_SET_RATE_PARENT, 1, 2);
964         clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
965 
966         /* PLLU */
967         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
968                             &pll_u_params, NULL);
969         clks[TEGRA30_CLK_PLL_U] = clk;
970 
971         tegra30_utmi_param_configure();
972 
973         /* PLLD */
974         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
975                             &pll_d_params, &pll_d_lock);
976         clks[TEGRA30_CLK_PLL_D] = clk;
977 
978         /* PLLD_OUT0 */
979         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
980                                         CLK_SET_RATE_PARENT, 1, 2);
981         clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
982 
983         /* PLLD2 */
984         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
985                             &pll_d2_params, NULL);
986         clks[TEGRA30_CLK_PLL_D2] = clk;
987 
988         /* PLLD2_OUT0 */
989         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
990                                         CLK_SET_RATE_PARENT, 1, 2);
991         clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
992 
993         /* PLLE */
994         clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
995                                ARRAY_SIZE(pll_e_parents),
996                                CLK_SET_RATE_NO_REPARENT,
997                                clk_base + PLLE_AUX, 2, 1, 0, NULL);
998         clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
999                              CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1000         clks[TEGRA30_CLK_PLL_E] = clk;
1001 }
1002 
1003 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1004                                         "pll_p_cclkg", "pll_p_out4_cclkg",
1005                                         "pll_p_out3_cclkg", "unused", "pll_x" };
1006 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1007                                          "pll_p_cclklp", "pll_p_out4_cclklp",
1008                                          "pll_p_out3_cclklp", "unused", "pll_x",
1009                                          "pll_x_out0" };
1010 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1011                                       "pll_p_out3", "pll_p_out2", "unused",
1012                                       "clk_32k", "pll_m_out1" };
1013 
1014 static void __init tegra30_super_clk_init(void)
1015 {
1016         struct clk *clk;
1017 
1018         /*
1019          * Clock input to cclk_g divided from pll_p using
1020          * U71 divider of cclk_g.
1021          */
1022         clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1023                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1024                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1025         clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1026 
1027         /*
1028          * Clock input to cclk_g divided from pll_p_out3 using
1029          * U71 divider of cclk_g.
1030          */
1031         clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1032                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1033                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1034         clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1035 
1036         /*
1037          * Clock input to cclk_g divided from pll_p_out4 using
1038          * U71 divider of cclk_g.
1039          */
1040         clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1041                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1042                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1043         clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1044 
1045         /* CCLKG */
1046         clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1047                                   ARRAY_SIZE(cclk_g_parents),
1048                                   CLK_SET_RATE_PARENT,
1049                                   clk_base + CCLKG_BURST_POLICY,
1050                                   0, 4, 0, 0, NULL);
1051         clks[TEGRA30_CLK_CCLK_G] = clk;
1052 
1053         /*
1054          * Clock input to cclk_lp divided from pll_p using
1055          * U71 divider of cclk_lp.
1056          */
1057         clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1058                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1059                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1060         clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1061 
1062         /*
1063          * Clock input to cclk_lp divided from pll_p_out3 using
1064          * U71 divider of cclk_lp.
1065          */
1066         clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1067                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1068                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1069         clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1070 
1071         /*
1072          * Clock input to cclk_lp divided from pll_p_out4 using
1073          * U71 divider of cclk_lp.
1074          */
1075         clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1076                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1077                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1078         clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1079 
1080         /* CCLKLP */
1081         clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1082                                   ARRAY_SIZE(cclk_lp_parents),
1083                                   CLK_SET_RATE_PARENT,
1084                                   clk_base + CCLKLP_BURST_POLICY,
1085                                   TEGRA_DIVIDER_2, 4, 8, 9,
1086                               NULL);
1087         clks[TEGRA30_CLK_CCLK_LP] = clk;
1088 
1089         /* SCLK */
1090         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1091                                   ARRAY_SIZE(sclk_parents),
1092                                   CLK_SET_RATE_PARENT,
1093                                   clk_base + SCLK_BURST_POLICY,
1094                                   0, 4, 0, 0, NULL);
1095         clks[TEGRA30_CLK_SCLK] = clk;
1096 
1097         /* twd */
1098         clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1099                                         CLK_SET_RATE_PARENT, 1, 2);
1100         clks[TEGRA30_CLK_TWD] = clk;
1101 
1102         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1103 }
1104 
1105 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1106                                          "clk_m" };
1107 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1108 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1109 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1110                                            "clk_m" };
1111 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1112 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1113                                              "pll_a_out0", "pll_c",
1114                                              "pll_d2_out0", "clk_m" };
1115 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1116                                                   "pll_d2_out0" };
1117 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1118 
1119 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1120         TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1121         TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1122         TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1123         TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1124         TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1125         TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1126         TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1127         TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1128         TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
1129 };
1130 
1131 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1132         TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1133 };
1134 
1135 static void __init tegra30_periph_clk_init(void)
1136 {
1137         struct tegra_periph_init_data *data;
1138         struct clk *clk;
1139         int i;
1140 
1141         /* dsia */
1142         clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1143                                     0, 48, periph_clk_enb_refcnt);
1144         clks[TEGRA30_CLK_DSIA] = clk;
1145 
1146         /* pcie */
1147         clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1148                                     70, periph_clk_enb_refcnt);
1149         clks[TEGRA30_CLK_PCIE] = clk;
1150 
1151         /* afi */
1152         clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1153                                     periph_clk_enb_refcnt);
1154         clks[TEGRA30_CLK_AFI] = clk;
1155 
1156         /* emc */
1157         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1158                                ARRAY_SIZE(mux_pllmcp_clkm),
1159                                CLK_SET_RATE_NO_REPARENT,
1160                                clk_base + CLK_SOURCE_EMC,
1161                                30, 2, 0, &emc_lock);
1162         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1163                                     57, periph_clk_enb_refcnt);
1164         clks[TEGRA30_CLK_EMC] = clk;
1165 
1166         clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1167                                     &emc_lock);
1168         clks[TEGRA30_CLK_MC] = clk;
1169 
1170         /* cml0 */
1171         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1172                                 0, 0, &cml_lock);
1173         clks[TEGRA30_CLK_CML0] = clk;
1174 
1175         /* cml1 */
1176         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1177                                 1, 0, &cml_lock);
1178         clks[TEGRA30_CLK_CML1] = clk;
1179 
1180         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1181                 data = &tegra_periph_clk_list[i];
1182                 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1183                                 data->num_parents, &data->periph,
1184                                 clk_base, data->offset, data->flags);
1185                 clks[data->clk_id] = clk;
1186         }
1187 
1188         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1189                 data = &tegra_periph_nodiv_clk_list[i];
1190                 clk = tegra_clk_register_periph_nodiv(data->name,
1191                                         data->p.parent_names,
1192                                         data->num_parents, &data->periph,
1193                                         clk_base, data->offset);
1194                 clks[data->clk_id] = clk;
1195         }
1196 
1197         tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1198 }
1199 
1200 /* Tegra30 CPU clock and reset control functions */
1201 static void tegra30_wait_cpu_in_reset(u32 cpu)
1202 {
1203         unsigned int reg;
1204 
1205         do {
1206                 reg = readl(clk_base +
1207                             TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1208                 cpu_relax();
1209         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1210 
1211         return;
1212 }
1213 
1214 static void tegra30_put_cpu_in_reset(u32 cpu)
1215 {
1216         writel(CPU_RESET(cpu),
1217                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1218         dmb();
1219 }
1220 
1221 static void tegra30_cpu_out_of_reset(u32 cpu)
1222 {
1223         writel(CPU_RESET(cpu),
1224                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1225         wmb();
1226 }
1227 
1228 
1229 static void tegra30_enable_cpu_clock(u32 cpu)
1230 {
1231         unsigned int reg;
1232 
1233         writel(CPU_CLOCK(cpu),
1234                clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1235         reg = readl(clk_base +
1236                     TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1237 }
1238 
1239 static void tegra30_disable_cpu_clock(u32 cpu)
1240 {
1241 
1242         unsigned int reg;
1243 
1244         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1245         writel(reg | CPU_CLOCK(cpu),
1246                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1247 }
1248 
1249 #ifdef CONFIG_PM_SLEEP
1250 static bool tegra30_cpu_rail_off_ready(void)
1251 {
1252         unsigned int cpu_rst_status;
1253         int cpu_pwr_status;
1254 
1255         cpu_rst_status = readl(clk_base +
1256                                 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1257         cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1258                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1259                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1260 
1261         if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1262                 return false;
1263 
1264         return true;
1265 }
1266 
1267 static void tegra30_cpu_clock_suspend(void)
1268 {
1269         /* switch coresite to clk_m, save off original source */
1270         tegra30_cpu_clk_sctx.clk_csite_src =
1271                                 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1272         writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1273 
1274         tegra30_cpu_clk_sctx.cpu_burst =
1275                                 readl(clk_base + CLK_RESET_CCLK_BURST);
1276         tegra30_cpu_clk_sctx.pllx_base =
1277                                 readl(clk_base + CLK_RESET_PLLX_BASE);
1278         tegra30_cpu_clk_sctx.pllx_misc =
1279                                 readl(clk_base + CLK_RESET_PLLX_MISC);
1280         tegra30_cpu_clk_sctx.cclk_divider =
1281                                 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1282 }
1283 
1284 static void tegra30_cpu_clock_resume(void)
1285 {
1286         unsigned int reg, policy;
1287 
1288         /* Is CPU complex already running on PLLX? */
1289         reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1290         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1291 
1292         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1293                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1294         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1295                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1296         else
1297                 BUG();
1298 
1299         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1300                 /* restore PLLX settings if CPU is on different PLL */
1301                 writel(tegra30_cpu_clk_sctx.pllx_misc,
1302                                         clk_base + CLK_RESET_PLLX_MISC);
1303                 writel(tegra30_cpu_clk_sctx.pllx_base,
1304                                         clk_base + CLK_RESET_PLLX_BASE);
1305 
1306                 /* wait for PLL stabilization if PLLX was enabled */
1307                 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1308                         udelay(300);
1309         }
1310 
1311         /*
1312          * Restore original burst policy setting for calls resulting from CPU
1313          * LP2 in idle or system suspend.
1314          */
1315         writel(tegra30_cpu_clk_sctx.cclk_divider,
1316                                         clk_base + CLK_RESET_CCLK_DIVIDER);
1317         writel(tegra30_cpu_clk_sctx.cpu_burst,
1318                                         clk_base + CLK_RESET_CCLK_BURST);
1319 
1320         writel(tegra30_cpu_clk_sctx.clk_csite_src,
1321                                         clk_base + CLK_RESET_SOURCE_CSITE);
1322 }
1323 #endif
1324 
1325 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1326         .wait_for_reset = tegra30_wait_cpu_in_reset,
1327         .put_in_reset   = tegra30_put_cpu_in_reset,
1328         .out_of_reset   = tegra30_cpu_out_of_reset,
1329         .enable_clock   = tegra30_enable_cpu_clock,
1330         .disable_clock  = tegra30_disable_cpu_clock,
1331 #ifdef CONFIG_PM_SLEEP
1332         .rail_off_ready = tegra30_cpu_rail_off_ready,
1333         .suspend        = tegra30_cpu_clock_suspend,
1334         .resume         = tegra30_cpu_clock_resume,
1335 #endif
1336 };
1337 
1338 static struct tegra_clk_init_table init_table[] __initdata = {
1339         {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1340         {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1341         {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1342         {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1343         {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1344         {TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
1345         {TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
1346         {TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
1347         {TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
1348         {TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
1349         {TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
1350         {TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1351         {TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1352         {TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1353         {TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1354         {TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1355         {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1356         {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1357         {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1358         {TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
1359         {TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
1360         {TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
1361         {TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
1362         {TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
1363         {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1364         {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1365         {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1366         {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1367         {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1368         {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1369         {TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
1370         {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1371         {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
1372         {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1373         {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1374         {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1375         {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
1376         {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1377 };
1378 
1379 static void __init tegra30_clock_apply_init_table(void)
1380 {
1381         tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1382 }
1383 
1384 /*
1385  * Some clocks may be used by different drivers depending on the board
1386  * configuration.  List those here to register them twice in the clock lookup
1387  * table under two names.
1388  */
1389 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1390         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1391         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1392         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1393         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1394         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1395         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1396         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1397         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1398         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1399         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1400         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1401         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
1402 };
1403 
1404 static const struct of_device_id pmc_match[] __initconst = {
1405         { .compatible = "nvidia,tegra30-pmc" },
1406         {},
1407 };
1408 
1409 static void __init tegra30_clock_init(struct device_node *np)
1410 {
1411         struct device_node *node;
1412 
1413         clk_base = of_iomap(np, 0);
1414         if (!clk_base) {
1415                 pr_err("ioremap tegra30 CAR failed\n");
1416                 return;
1417         }
1418 
1419         node = of_find_matching_node(NULL, pmc_match);
1420         if (!node) {
1421                 pr_err("Failed to find pmc node\n");
1422                 BUG();
1423         }
1424 
1425         pmc_base = of_iomap(node, 0);
1426         if (!pmc_base) {
1427                 pr_err("Can't map pmc registers\n");
1428                 BUG();
1429         }
1430 
1431         clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1432                                 TEGRA30_CLK_PERIPH_BANKS);
1433         if (!clks)
1434                 return;
1435 
1436         if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1437                 ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0)
1438                 return;
1439 
1440 
1441         tegra_fixed_clk_init(tegra30_clks);
1442         tegra30_pll_init();
1443         tegra30_super_clk_init();
1444         tegra30_periph_clk_init();
1445         tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
1446         tegra_pmc_clk_init(pmc_base, tegra30_clks);
1447 
1448         tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1449 
1450         tegra_add_of_provider(np);
1451         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1452 
1453         tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1454 
1455         tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1456 }
1457 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1458 

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