Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/clk/tegra/clk-tegra20.c

  1 /*
  2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk-provider.h>
 19 #include <linux/clkdev.h>
 20 #include <linux/of.h>
 21 #include <linux/of_address.h>
 22 #include <linux/clk/tegra.h>
 23 #include <linux/delay.h>
 24 #include <dt-bindings/clock/tegra20-car.h>
 25 
 26 #include "clk.h"
 27 #include "clk-id.h"
 28 
 29 #define OSC_CTRL 0x50
 30 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
 31 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
 32 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
 33 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
 34 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
 35 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
 36 
 37 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
 38 #define OSC_CTRL_PLL_REF_DIV_1          (0<<28)
 39 #define OSC_CTRL_PLL_REF_DIV_2          (1<<28)
 40 #define OSC_CTRL_PLL_REF_DIV_4          (2<<28)
 41 
 42 #define OSC_FREQ_DET 0x58
 43 #define OSC_FREQ_DET_TRIG (1<<31)
 44 
 45 #define OSC_FREQ_DET_STATUS 0x5c
 46 #define OSC_FREQ_DET_BUSY (1<<31)
 47 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
 48 
 49 #define TEGRA20_CLK_PERIPH_BANKS        3
 50 
 51 #define PLLS_BASE 0xf0
 52 #define PLLS_MISC 0xf4
 53 #define PLLC_BASE 0x80
 54 #define PLLC_MISC 0x8c
 55 #define PLLM_BASE 0x90
 56 #define PLLM_MISC 0x9c
 57 #define PLLP_BASE 0xa0
 58 #define PLLP_MISC 0xac
 59 #define PLLA_BASE 0xb0
 60 #define PLLA_MISC 0xbc
 61 #define PLLU_BASE 0xc0
 62 #define PLLU_MISC 0xcc
 63 #define PLLD_BASE 0xd0
 64 #define PLLD_MISC 0xdc
 65 #define PLLX_BASE 0xe0
 66 #define PLLX_MISC 0xe4
 67 #define PLLE_BASE 0xe8
 68 #define PLLE_MISC 0xec
 69 
 70 #define PLL_BASE_LOCK BIT(27)
 71 #define PLLE_MISC_LOCK BIT(11)
 72 
 73 #define PLL_MISC_LOCK_ENABLE 18
 74 #define PLLDU_MISC_LOCK_ENABLE 22
 75 #define PLLE_MISC_LOCK_ENABLE 9
 76 
 77 #define PLLC_OUT 0x84
 78 #define PLLM_OUT 0x94
 79 #define PLLP_OUTA 0xa4
 80 #define PLLP_OUTB 0xa8
 81 #define PLLA_OUT 0xb4
 82 
 83 #define CCLK_BURST_POLICY 0x20
 84 #define SUPER_CCLK_DIVIDER 0x24
 85 #define SCLK_BURST_POLICY 0x28
 86 #define SUPER_SCLK_DIVIDER 0x2c
 87 #define CLK_SYSTEM_RATE 0x30
 88 
 89 #define CCLK_BURST_POLICY_SHIFT 28
 90 #define CCLK_RUN_POLICY_SHIFT   4
 91 #define CCLK_IDLE_POLICY_SHIFT  0
 92 #define CCLK_IDLE_POLICY        1
 93 #define CCLK_RUN_POLICY         2
 94 #define CCLK_BURST_POLICY_PLLX  8
 95 
 96 #define CLK_SOURCE_I2S1 0x100
 97 #define CLK_SOURCE_I2S2 0x104
 98 #define CLK_SOURCE_PWM 0x110
 99 #define CLK_SOURCE_SPI 0x114
100 #define CLK_SOURCE_XIO 0x120
101 #define CLK_SOURCE_TWC 0x12c
102 #define CLK_SOURCE_IDE 0x144
103 #define CLK_SOURCE_HDMI 0x18c
104 #define CLK_SOURCE_DISP1 0x138
105 #define CLK_SOURCE_DISP2 0x13c
106 #define CLK_SOURCE_CSITE 0x1d4
107 #define CLK_SOURCE_I2C1 0x124
108 #define CLK_SOURCE_I2C2 0x198
109 #define CLK_SOURCE_I2C3 0x1b8
110 #define CLK_SOURCE_DVC 0x128
111 #define CLK_SOURCE_UARTA 0x178
112 #define CLK_SOURCE_UARTB 0x17c
113 #define CLK_SOURCE_UARTC 0x1a0
114 #define CLK_SOURCE_UARTD 0x1c0
115 #define CLK_SOURCE_UARTE 0x1c4
116 #define CLK_SOURCE_EMC 0x19c
117 
118 #define AUDIO_SYNC_CLK 0x38
119 
120 /* Tegra CPU clock and reset control regs */
121 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
122 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
123 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
124 
125 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
126 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
127 
128 #ifdef CONFIG_PM_SLEEP
129 static struct cpu_clk_suspend_context {
130         u32 pllx_misc;
131         u32 pllx_base;
132 
133         u32 cpu_burst;
134         u32 clk_csite_src;
135         u32 cclk_divider;
136 } tegra20_cpu_clk_sctx;
137 #endif
138 
139 static void __iomem *clk_base;
140 static void __iomem *pmc_base;
141 
142 static DEFINE_SPINLOCK(emc_lock);
143 
144 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,   \
145                             _clk_num, _gate_flags, _clk_id)     \
146         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
147                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,      \
148                         _clk_num, \
149                         _gate_flags, _clk_id)
150 
151 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
152                               _clk_num, _gate_flags, _clk_id)   \
153         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
154                         30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
155                         _clk_num, _gate_flags,  \
156                         _clk_id)
157 
158 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
159                               _mux_shift, _mux_width, _clk_num, \
160                               _gate_flags, _clk_id)                     \
161         TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
162                         _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
163                         _clk_num, _gate_flags,  \
164                         _clk_id)
165 
166 static struct clk **clks;
167 
168 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
169         { 12000000, 600000000, 600, 12, 0, 8 },
170         { 13000000, 600000000, 600, 13, 0, 8 },
171         { 19200000, 600000000, 500, 16, 0, 6 },
172         { 26000000, 600000000, 600, 26, 0, 8 },
173         { 0, 0, 0, 0, 0, 0 },
174 };
175 
176 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
177         { 12000000, 666000000, 666, 12, 0, 8},
178         { 13000000, 666000000, 666, 13, 0, 8},
179         { 19200000, 666000000, 555, 16, 0, 8},
180         { 26000000, 666000000, 666, 26, 0, 8},
181         { 12000000, 600000000, 600, 12, 0, 8},
182         { 13000000, 600000000, 600, 13, 0, 8},
183         { 19200000, 600000000, 375, 12, 0, 6},
184         { 26000000, 600000000, 600, 26, 0, 8},
185         { 0, 0, 0, 0, 0, 0 },
186 };
187 
188 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
189         { 12000000, 216000000, 432, 12, 1, 8},
190         { 13000000, 216000000, 432, 13, 1, 8},
191         { 19200000, 216000000, 90,   4, 1, 1},
192         { 26000000, 216000000, 432, 26, 1, 8},
193         { 12000000, 432000000, 432, 12, 0, 8},
194         { 13000000, 432000000, 432, 13, 0, 8},
195         { 19200000, 432000000, 90,   4, 0, 1},
196         { 26000000, 432000000, 432, 26, 0, 8},
197         { 0, 0, 0, 0, 0, 0 },
198 };
199 
200 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
201         { 28800000, 56448000, 49, 25, 0, 1},
202         { 28800000, 73728000, 64, 25, 0, 1},
203         { 28800000, 24000000,  5,  6, 0, 1},
204         { 0, 0, 0, 0, 0, 0 },
205 };
206 
207 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
208         { 12000000, 216000000, 216, 12, 0, 4},
209         { 13000000, 216000000, 216, 13, 0, 4},
210         { 19200000, 216000000, 135, 12, 0, 3},
211         { 26000000, 216000000, 216, 26, 0, 4},
212 
213         { 12000000, 594000000, 594, 12, 0, 8},
214         { 13000000, 594000000, 594, 13, 0, 8},
215         { 19200000, 594000000, 495, 16, 0, 8},
216         { 26000000, 594000000, 594, 26, 0, 8},
217 
218         { 12000000, 1000000000, 1000, 12, 0, 12},
219         { 13000000, 1000000000, 1000, 13, 0, 12},
220         { 19200000, 1000000000, 625,  12, 0, 8},
221         { 26000000, 1000000000, 1000, 26, 0, 12},
222 
223         { 0, 0, 0, 0, 0, 0 },
224 };
225 
226 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
227         { 12000000, 480000000, 960, 12, 0, 0},
228         { 13000000, 480000000, 960, 13, 0, 0},
229         { 19200000, 480000000, 200, 4,  0, 0},
230         { 26000000, 480000000, 960, 26, 0, 0},
231         { 0, 0, 0, 0, 0, 0 },
232 };
233 
234 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
235         /* 1 GHz */
236         { 12000000, 1000000000, 1000, 12, 0, 12},
237         { 13000000, 1000000000, 1000, 13, 0, 12},
238         { 19200000, 1000000000, 625,  12, 0, 8},
239         { 26000000, 1000000000, 1000, 26, 0, 12},
240 
241         /* 912 MHz */
242         { 12000000, 912000000,  912,  12, 0, 12},
243         { 13000000, 912000000,  912,  13, 0, 12},
244         { 19200000, 912000000,  760,  16, 0, 8},
245         { 26000000, 912000000,  912,  26, 0, 12},
246 
247         /* 816 MHz */
248         { 12000000, 816000000,  816,  12, 0, 12},
249         { 13000000, 816000000,  816,  13, 0, 12},
250         { 19200000, 816000000,  680,  16, 0, 8},
251         { 26000000, 816000000,  816,  26, 0, 12},
252 
253         /* 760 MHz */
254         { 12000000, 760000000,  760,  12, 0, 12},
255         { 13000000, 760000000,  760,  13, 0, 12},
256         { 19200000, 760000000,  950,  24, 0, 8},
257         { 26000000, 760000000,  760,  26, 0, 12},
258 
259         /* 750 MHz */
260         { 12000000, 750000000,  750,  12, 0, 12},
261         { 13000000, 750000000,  750,  13, 0, 12},
262         { 19200000, 750000000,  625,  16, 0, 8},
263         { 26000000, 750000000,  750,  26, 0, 12},
264 
265         /* 608 MHz */
266         { 12000000, 608000000,  608,  12, 0, 12},
267         { 13000000, 608000000,  608,  13, 0, 12},
268         { 19200000, 608000000,  380,  12, 0, 8},
269         { 26000000, 608000000,  608,  26, 0, 12},
270 
271         /* 456 MHz */
272         { 12000000, 456000000,  456,  12, 0, 12},
273         { 13000000, 456000000,  456,  13, 0, 12},
274         { 19200000, 456000000,  380,  16, 0, 8},
275         { 26000000, 456000000,  456,  26, 0, 12},
276 
277         /* 312 MHz */
278         { 12000000, 312000000,  312,  12, 0, 12},
279         { 13000000, 312000000,  312,  13, 0, 12},
280         { 19200000, 312000000,  260,  16, 0, 8},
281         { 26000000, 312000000,  312,  26, 0, 12},
282 
283         { 0, 0, 0, 0, 0, 0 },
284 };
285 
286 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
287         { 12000000, 100000000,  200,  24, 0, 0 },
288         { 0, 0, 0, 0, 0, 0 },
289 };
290 
291 /* PLL parameters */
292 static struct tegra_clk_pll_params pll_c_params = {
293         .input_min = 2000000,
294         .input_max = 31000000,
295         .cf_min = 1000000,
296         .cf_max = 6000000,
297         .vco_min = 20000000,
298         .vco_max = 1400000000,
299         .base_reg = PLLC_BASE,
300         .misc_reg = PLLC_MISC,
301         .lock_mask = PLL_BASE_LOCK,
302         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
303         .lock_delay = 300,
304         .freq_table = pll_c_freq_table,
305         .flags = TEGRA_PLL_HAS_CPCON,
306 };
307 
308 static struct tegra_clk_pll_params pll_m_params = {
309         .input_min = 2000000,
310         .input_max = 31000000,
311         .cf_min = 1000000,
312         .cf_max = 6000000,
313         .vco_min = 20000000,
314         .vco_max = 1200000000,
315         .base_reg = PLLM_BASE,
316         .misc_reg = PLLM_MISC,
317         .lock_mask = PLL_BASE_LOCK,
318         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
319         .lock_delay = 300,
320         .freq_table = pll_m_freq_table,
321         .flags = TEGRA_PLL_HAS_CPCON,
322 };
323 
324 static struct tegra_clk_pll_params pll_p_params = {
325         .input_min = 2000000,
326         .input_max = 31000000,
327         .cf_min = 1000000,
328         .cf_max = 6000000,
329         .vco_min = 20000000,
330         .vco_max = 1400000000,
331         .base_reg = PLLP_BASE,
332         .misc_reg = PLLP_MISC,
333         .lock_mask = PLL_BASE_LOCK,
334         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
335         .lock_delay = 300,
336         .freq_table = pll_p_freq_table,
337         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
338         .fixed_rate =  216000000,
339 };
340 
341 static struct tegra_clk_pll_params pll_a_params = {
342         .input_min = 2000000,
343         .input_max = 31000000,
344         .cf_min = 1000000,
345         .cf_max = 6000000,
346         .vco_min = 20000000,
347         .vco_max = 1400000000,
348         .base_reg = PLLA_BASE,
349         .misc_reg = PLLA_MISC,
350         .lock_mask = PLL_BASE_LOCK,
351         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
352         .lock_delay = 300,
353         .freq_table = pll_a_freq_table,
354         .flags = TEGRA_PLL_HAS_CPCON,
355 };
356 
357 static struct tegra_clk_pll_params pll_d_params = {
358         .input_min = 2000000,
359         .input_max = 40000000,
360         .cf_min = 1000000,
361         .cf_max = 6000000,
362         .vco_min = 40000000,
363         .vco_max = 1000000000,
364         .base_reg = PLLD_BASE,
365         .misc_reg = PLLD_MISC,
366         .lock_mask = PLL_BASE_LOCK,
367         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
368         .lock_delay = 1000,
369         .freq_table = pll_d_freq_table,
370         .flags = TEGRA_PLL_HAS_CPCON,
371 };
372 
373 static struct pdiv_map pllu_p[] = {
374         { .pdiv = 1, .hw_val = 1 },
375         { .pdiv = 2, .hw_val = 0 },
376         { .pdiv = 0, .hw_val = 0 },
377 };
378 
379 static struct tegra_clk_pll_params pll_u_params = {
380         .input_min = 2000000,
381         .input_max = 40000000,
382         .cf_min = 1000000,
383         .cf_max = 6000000,
384         .vco_min = 48000000,
385         .vco_max = 960000000,
386         .base_reg = PLLU_BASE,
387         .misc_reg = PLLU_MISC,
388         .lock_mask = PLL_BASE_LOCK,
389         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
390         .lock_delay = 1000,
391         .pdiv_tohw = pllu_p,
392         .freq_table = pll_u_freq_table,
393         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
394 };
395 
396 static struct tegra_clk_pll_params pll_x_params = {
397         .input_min = 2000000,
398         .input_max = 31000000,
399         .cf_min = 1000000,
400         .cf_max = 6000000,
401         .vco_min = 20000000,
402         .vco_max = 1200000000,
403         .base_reg = PLLX_BASE,
404         .misc_reg = PLLX_MISC,
405         .lock_mask = PLL_BASE_LOCK,
406         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
407         .lock_delay = 300,
408         .freq_table = pll_x_freq_table,
409         .flags = TEGRA_PLL_HAS_CPCON,
410 };
411 
412 static struct tegra_clk_pll_params pll_e_params = {
413         .input_min = 12000000,
414         .input_max = 12000000,
415         .cf_min = 0,
416         .cf_max = 0,
417         .vco_min = 0,
418         .vco_max = 0,
419         .base_reg = PLLE_BASE,
420         .misc_reg = PLLE_MISC,
421         .lock_mask = PLLE_MISC_LOCK,
422         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
423         .lock_delay = 0,
424         .freq_table = pll_e_freq_table,
425         .flags = TEGRA_PLL_FIXED,
426         .fixed_rate = 100000000,
427 };
428 
429 static struct tegra_devclk devclks[] __initdata = {
430         { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
431         { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
432         { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
433         { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
434         { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
435         { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
436         { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
437         { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
438         { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
439         { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
440         { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
441         { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
442         { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
443         { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
444         { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
445         { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
446         { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
447         { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
448         { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
449         { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
450         { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
451         { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
452         { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
453         { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
454         { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
455         { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
456         { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
457         { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
458         { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
459         { .con_id = "csus", .dev_id =  "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
460         { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
461         { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
462         { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
463         { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
464         { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
465         { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
466         { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
467         { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
468         { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
469         { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
470         { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
471         { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
472         { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
473         { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
474         { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
475         { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
476         { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
477         { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
478         { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
479         { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
480         { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
481         { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
482         { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
483         { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
484         { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
485         { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
486         { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
487         { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
488         { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
489         { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
490         { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
491         { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
492         { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
493         { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
494         { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
495         { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
496         { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
497         { .con_id = "vi", .dev_id =  "tegra_camera", .dt_id = TEGRA20_CLK_VI },
498         { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
499         { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
500         { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
501         { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
502         { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
503         { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
504         { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
505         { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
506         { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
507         { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
508         { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
509         { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
510         { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
511         { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
512         { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
513         { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
514         { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
515         { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
516         { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
517         { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
518         { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
519         { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
520         { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
521         { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
522         { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
523         { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
524         { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
525 };
526 
527 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
528         [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
529         [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
530         [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
531         [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
532         [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
533         [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
534         [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
535         [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
536         [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
537         [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
538         [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
539         [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
540         [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
541         [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
542         [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
543         [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
544         [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
545         [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
546         [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
547         [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
548         [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
549         [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
550         [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
551         [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
552         [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
553         [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
554         [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
555         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
556         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
557         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
558         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
559         [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
560         [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
561         [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
562         [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
563         [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
564         [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
565         [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
566         [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
567         [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
568         [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
569         [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
570         [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
571         [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
572         [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
573         [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
574         [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
575         [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
576         [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
577         [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
578         [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
579         [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
580 };
581 
582 static unsigned long tegra20_clk_measure_input_freq(void)
583 {
584         u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
585         u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
586         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
587         unsigned long input_freq;
588 
589         switch (auto_clk_control) {
590         case OSC_CTRL_OSC_FREQ_12MHZ:
591                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
592                 input_freq = 12000000;
593                 break;
594         case OSC_CTRL_OSC_FREQ_13MHZ:
595                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
596                 input_freq = 13000000;
597                 break;
598         case OSC_CTRL_OSC_FREQ_19_2MHZ:
599                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
600                 input_freq = 19200000;
601                 break;
602         case OSC_CTRL_OSC_FREQ_26MHZ:
603                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
604                 input_freq = 26000000;
605                 break;
606         default:
607                 pr_err("Unexpected clock autodetect value %d",
608                        auto_clk_control);
609                 BUG();
610                 return 0;
611         }
612 
613         return input_freq;
614 }
615 
616 static unsigned int tegra20_get_pll_ref_div(void)
617 {
618         u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
619                 OSC_CTRL_PLL_REF_DIV_MASK;
620 
621         switch (pll_ref_div) {
622         case OSC_CTRL_PLL_REF_DIV_1:
623                 return 1;
624         case OSC_CTRL_PLL_REF_DIV_2:
625                 return 2;
626         case OSC_CTRL_PLL_REF_DIV_4:
627                 return 4;
628         default:
629                 pr_err("Invalied pll ref divider %d\n", pll_ref_div);
630                 BUG();
631         }
632         return 0;
633 }
634 
635 static void tegra20_pll_init(void)
636 {
637         struct clk *clk;
638 
639         /* PLLC */
640         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
641                             &pll_c_params, NULL);
642         clks[TEGRA20_CLK_PLL_C] = clk;
643 
644         /* PLLC_OUT1 */
645         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
646                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
647                                 8, 8, 1, NULL);
648         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
649                                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
650                                 0, NULL);
651         clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
652 
653         /* PLLM */
654         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
655                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
656                             &pll_m_params, NULL);
657         clks[TEGRA20_CLK_PLL_M] = clk;
658 
659         /* PLLM_OUT1 */
660         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
661                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
662                                 8, 8, 1, NULL);
663         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
664                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
665                                 CLK_SET_RATE_PARENT, 0, NULL);
666         clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
667 
668         /* PLLX */
669         clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
670                             &pll_x_params, NULL);
671         clks[TEGRA20_CLK_PLL_X] = clk;
672 
673         /* PLLU */
674         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
675                             &pll_u_params, NULL);
676         clks[TEGRA20_CLK_PLL_U] = clk;
677 
678         /* PLLD */
679         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
680                             &pll_d_params, NULL);
681         clks[TEGRA20_CLK_PLL_D] = clk;
682 
683         /* PLLD_OUT0 */
684         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
685                                         CLK_SET_RATE_PARENT, 1, 2);
686         clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
687 
688         /* PLLA */
689         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
690                             &pll_a_params, NULL);
691         clks[TEGRA20_CLK_PLL_A] = clk;
692 
693         /* PLLA_OUT0 */
694         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
695                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
696                                 8, 8, 1, NULL);
697         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
698                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
699                                 CLK_SET_RATE_PARENT, 0, NULL);
700         clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
701 
702         /* PLLE */
703         clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
704                              0, &pll_e_params, NULL);
705         clks[TEGRA20_CLK_PLL_E] = clk;
706 }
707 
708 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
709                                       "pll_p", "pll_p_out4",
710                                       "pll_p_out3", "clk_d", "pll_x" };
711 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
712                                       "pll_p_out3", "pll_p_out2", "clk_d",
713                                       "clk_32k", "pll_m_out1" };
714 
715 static void tegra20_super_clk_init(void)
716 {
717         struct clk *clk;
718 
719         /* CCLK */
720         clk = tegra_clk_register_super_mux("cclk", cclk_parents,
721                               ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
722                               clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
723         clks[TEGRA20_CLK_CCLK] = clk;
724 
725         /* SCLK */
726         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
727                               ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
728                               clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
729         clks[TEGRA20_CLK_SCLK] = clk;
730 
731         /* twd */
732         clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
733         clks[TEGRA20_CLK_TWD] = clk;
734 }
735 
736 static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
737                                       "pll_a_out0", "unused", "unused",
738                                       "unused"};
739 
740 static void __init tegra20_audio_clk_init(void)
741 {
742         struct clk *clk;
743 
744         /* audio */
745         clk = clk_register_mux(NULL, "audio_mux", audio_parents,
746                                 ARRAY_SIZE(audio_parents),
747                                 CLK_SET_RATE_NO_REPARENT,
748                                 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
749         clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
750                                 clk_base + AUDIO_SYNC_CLK, 4,
751                                 CLK_GATE_SET_TO_DISABLE, NULL);
752         clks[TEGRA20_CLK_AUDIO] = clk;
753 
754         /* audio_2x */
755         clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
756                                         CLK_SET_RATE_PARENT, 2, 1);
757         clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
758                                     TEGRA_PERIPH_NO_RESET, clk_base,
759                                     CLK_SET_RATE_PARENT, 89,
760                                     periph_clk_enb_refcnt);
761         clks[TEGRA20_CLK_AUDIO_2X] = clk;
762 
763 }
764 
765 static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
766                                      "clk_m"};
767 static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
768                                      "clk_m"};
769 static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
770                                     "clk_32k"};
771 static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
772 static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
773                                         "clk_m"};
774 static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
775 
776 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
777         TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents,     CLK_SOURCE_I2S1,   11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
778         TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents,     CLK_SOURCE_I2S2,   18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
779         TEGRA_INIT_DATA_MUX("spi",   mux_pllpcm_clkm,   CLK_SOURCE_SPI,   43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
780         TEGRA_INIT_DATA_MUX("xio",   mux_pllpcm_clkm,   CLK_SOURCE_XIO,   45, 0, TEGRA20_CLK_XIO),
781         TEGRA_INIT_DATA_MUX("twc",   mux_pllpcm_clkm,   CLK_SOURCE_TWC,   16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
782         TEGRA_INIT_DATA_MUX("ide",   mux_pllpcm_clkm,   CLK_SOURCE_XIO,   25, 0, TEGRA20_CLK_IDE),
783         TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm,   CLK_SOURCE_DVC,   47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
784         TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm,   CLK_SOURCE_I2C1,   12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
785         TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm,   CLK_SOURCE_I2C2,   54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
786         TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm,   CLK_SOURCE_I2C3,   67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
787         TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm,   CLK_SOURCE_HDMI,   51, 0, TEGRA20_CLK_HDMI),
788         TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents,     CLK_SOURCE_PWM,   28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
789 };
790 
791 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
792         TEGRA_INIT_DATA_NODIV("uarta",  mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6,   TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
793         TEGRA_INIT_DATA_NODIV("uartb",  mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7,   TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
794         TEGRA_INIT_DATA_NODIV("uartc",  mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
795         TEGRA_INIT_DATA_NODIV("uartd",  mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
796         TEGRA_INIT_DATA_NODIV("uarte",  mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
797         TEGRA_INIT_DATA_NODIV("disp1",  mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27,  0, TEGRA20_CLK_DISP1),
798         TEGRA_INIT_DATA_NODIV("disp2",  mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26,  0, TEGRA20_CLK_DISP2),
799 };
800 
801 static void __init tegra20_periph_clk_init(void)
802 {
803         struct tegra_periph_init_data *data;
804         struct clk *clk;
805         int i;
806 
807         /* ac97 */
808         clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
809                                     TEGRA_PERIPH_ON_APB,
810                                     clk_base, 0, 3, periph_clk_enb_refcnt);
811         clks[TEGRA20_CLK_AC97] = clk;
812 
813         /* apbdma */
814         clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
815                                     0, 34, periph_clk_enb_refcnt);
816         clks[TEGRA20_CLK_APBDMA] = clk;
817 
818         /* emc */
819         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
820                                ARRAY_SIZE(mux_pllmcp_clkm),
821                                CLK_SET_RATE_NO_REPARENT,
822                                clk_base + CLK_SOURCE_EMC,
823                                30, 2, 0, &emc_lock);
824         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
825                                     57, periph_clk_enb_refcnt);
826         clks[TEGRA20_CLK_EMC] = clk;
827 
828         clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
829                                     &emc_lock);
830         clks[TEGRA20_CLK_MC] = clk;
831 
832         /* dsi */
833         clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
834                                     48, periph_clk_enb_refcnt);
835         clk_register_clkdev(clk, NULL, "dsi");
836         clks[TEGRA20_CLK_DSI] = clk;
837 
838         /* pex */
839         clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
840                                     periph_clk_enb_refcnt);
841         clks[TEGRA20_CLK_PEX] = clk;
842 
843         /* cdev1 */
844         clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
845                                       26000000);
846         clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
847                                     clk_base, 0, 94, periph_clk_enb_refcnt);
848         clks[TEGRA20_CLK_CDEV1] = clk;
849 
850         /* cdev2 */
851         clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
852                                       26000000);
853         clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
854                                     clk_base, 0, 93, periph_clk_enb_refcnt);
855         clks[TEGRA20_CLK_CDEV2] = clk;
856 
857         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
858                 data = &tegra_periph_clk_list[i];
859                 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
860                                 data->num_parents, &data->periph,
861                                 clk_base, data->offset, data->flags);
862                 clks[data->clk_id] = clk;
863         }
864 
865         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
866                 data = &tegra_periph_nodiv_clk_list[i];
867                 clk = tegra_clk_register_periph_nodiv(data->name,
868                                         data->p.parent_names,
869                                         data->num_parents, &data->periph,
870                                         clk_base, data->offset);
871                 clks[data->clk_id] = clk;
872         }
873 
874         tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
875 }
876 
877 static void __init tegra20_osc_clk_init(void)
878 {
879         struct clk *clk;
880         unsigned long input_freq;
881         unsigned int pll_ref_div;
882 
883         input_freq = tegra20_clk_measure_input_freq();
884 
885         /* clk_m */
886         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
887                                       CLK_IGNORE_UNUSED, input_freq);
888         clks[TEGRA20_CLK_CLK_M] = clk;
889 
890         /* pll_ref */
891         pll_ref_div = tegra20_get_pll_ref_div();
892         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
893                                         CLK_SET_RATE_PARENT, 1, pll_ref_div);
894         clks[TEGRA20_CLK_PLL_REF] = clk;
895 }
896 
897 /* Tegra20 CPU clock and reset control functions */
898 static void tegra20_wait_cpu_in_reset(u32 cpu)
899 {
900         unsigned int reg;
901 
902         do {
903                 reg = readl(clk_base +
904                             TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
905                 cpu_relax();
906         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
907 
908         return;
909 }
910 
911 static void tegra20_put_cpu_in_reset(u32 cpu)
912 {
913         writel(CPU_RESET(cpu),
914                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
915         dmb();
916 }
917 
918 static void tegra20_cpu_out_of_reset(u32 cpu)
919 {
920         writel(CPU_RESET(cpu),
921                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
922         wmb();
923 }
924 
925 static void tegra20_enable_cpu_clock(u32 cpu)
926 {
927         unsigned int reg;
928 
929         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
930         writel(reg & ~CPU_CLOCK(cpu),
931                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
932         barrier();
933         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
934 }
935 
936 static void tegra20_disable_cpu_clock(u32 cpu)
937 {
938         unsigned int reg;
939 
940         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
941         writel(reg | CPU_CLOCK(cpu),
942                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
943 }
944 
945 #ifdef CONFIG_PM_SLEEP
946 static bool tegra20_cpu_rail_off_ready(void)
947 {
948         unsigned int cpu_rst_status;
949 
950         cpu_rst_status = readl(clk_base +
951                                TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
952 
953         return !!(cpu_rst_status & 0x2);
954 }
955 
956 static void tegra20_cpu_clock_suspend(void)
957 {
958         /* switch coresite to clk_m, save off original source */
959         tegra20_cpu_clk_sctx.clk_csite_src =
960                                 readl(clk_base + CLK_SOURCE_CSITE);
961         writel(3<<30, clk_base + CLK_SOURCE_CSITE);
962 
963         tegra20_cpu_clk_sctx.cpu_burst =
964                                 readl(clk_base + CCLK_BURST_POLICY);
965         tegra20_cpu_clk_sctx.pllx_base =
966                                 readl(clk_base + PLLX_BASE);
967         tegra20_cpu_clk_sctx.pllx_misc =
968                                 readl(clk_base + PLLX_MISC);
969         tegra20_cpu_clk_sctx.cclk_divider =
970                                 readl(clk_base + SUPER_CCLK_DIVIDER);
971 }
972 
973 static void tegra20_cpu_clock_resume(void)
974 {
975         unsigned int reg, policy;
976 
977         /* Is CPU complex already running on PLLX? */
978         reg = readl(clk_base + CCLK_BURST_POLICY);
979         policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
980 
981         if (policy == CCLK_IDLE_POLICY)
982                 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
983         else if (policy == CCLK_RUN_POLICY)
984                 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
985         else
986                 BUG();
987 
988         if (reg != CCLK_BURST_POLICY_PLLX) {
989                 /* restore PLLX settings if CPU is on different PLL */
990                 writel(tegra20_cpu_clk_sctx.pllx_misc,
991                                         clk_base + PLLX_MISC);
992                 writel(tegra20_cpu_clk_sctx.pllx_base,
993                                         clk_base + PLLX_BASE);
994 
995                 /* wait for PLL stabilization if PLLX was enabled */
996                 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
997                         udelay(300);
998         }
999 
1000         /*
1001          * Restore original burst policy setting for calls resulting from CPU
1002          * LP2 in idle or system suspend.
1003          */
1004         writel(tegra20_cpu_clk_sctx.cclk_divider,
1005                                         clk_base + SUPER_CCLK_DIVIDER);
1006         writel(tegra20_cpu_clk_sctx.cpu_burst,
1007                                         clk_base + CCLK_BURST_POLICY);
1008 
1009         writel(tegra20_cpu_clk_sctx.clk_csite_src,
1010                                         clk_base + CLK_SOURCE_CSITE);
1011 }
1012 #endif
1013 
1014 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1015         .wait_for_reset = tegra20_wait_cpu_in_reset,
1016         .put_in_reset   = tegra20_put_cpu_in_reset,
1017         .out_of_reset   = tegra20_cpu_out_of_reset,
1018         .enable_clock   = tegra20_enable_cpu_clock,
1019         .disable_clock  = tegra20_disable_cpu_clock,
1020 #ifdef CONFIG_PM_SLEEP
1021         .rail_off_ready = tegra20_cpu_rail_off_ready,
1022         .suspend        = tegra20_cpu_clock_suspend,
1023         .resume         = tegra20_cpu_clock_resume,
1024 #endif
1025 };
1026 
1027 static struct tegra_clk_init_table init_table[] __initdata = {
1028         {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
1029         {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
1030         {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
1031         {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
1032         {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
1033         {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
1034         {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
1035         {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
1036         {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1037         {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
1038         {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
1039         {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
1040         {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1041         {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
1042         {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
1043         {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
1044         {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
1045         {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
1046         {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
1047         {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
1048         {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
1049         {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
1050         {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1051         {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1052         {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
1053         {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
1054         {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
1055         {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
1056         {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
1057         {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
1058         {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
1059         {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
1060         {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
1061         {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
1062         {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
1063         {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
1064         {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
1065         {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
1066 };
1067 
1068 static void __init tegra20_clock_apply_init_table(void)
1069 {
1070         tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1071 }
1072 
1073 /*
1074  * Some clocks may be used by different drivers depending on the board
1075  * configuration.  List those here to register them twice in the clock lookup
1076  * table under two names.
1077  */
1078 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1079         TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,   "utmip-pad",    NULL),
1080         TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,   "tegra-ehci.0", NULL),
1081         TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,   "tegra-otg",    NULL),
1082         TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK,   NULL,           "cpu"),
1083         TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
1084 };
1085 
1086 static const struct of_device_id pmc_match[] __initconst = {
1087         { .compatible = "nvidia,tegra20-pmc" },
1088         {},
1089 };
1090 
1091 static void __init tegra20_clock_init(struct device_node *np)
1092 {
1093         struct device_node *node;
1094 
1095         clk_base = of_iomap(np, 0);
1096         if (!clk_base) {
1097                 pr_err("Can't map CAR registers\n");
1098                 BUG();
1099         }
1100 
1101         node = of_find_matching_node(NULL, pmc_match);
1102         if (!node) {
1103                 pr_err("Failed to find pmc node\n");
1104                 BUG();
1105         }
1106 
1107         pmc_base = of_iomap(node, 0);
1108         if (!pmc_base) {
1109                 pr_err("Can't map pmc registers\n");
1110                 BUG();
1111         }
1112 
1113         clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1114                                 TEGRA20_CLK_PERIPH_BANKS);
1115         if (!clks)
1116                 return;
1117 
1118         tegra20_osc_clk_init();
1119         tegra_fixed_clk_init(tegra20_clks);
1120         tegra20_pll_init();
1121         tegra20_super_clk_init();
1122         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1123         tegra20_periph_clk_init();
1124         tegra20_audio_clk_init();
1125         tegra_pmc_clk_init(pmc_base, tegra20_clks);
1126 
1127         tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1128 
1129         tegra_add_of_provider(np);
1130         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1131 
1132         tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1133 
1134         tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1135 }
1136 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1137 

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