Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/drivers/clk/tegra/clk-tegra124.c

  1 /*
  2  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/clk-provider.h>
 20 #include <linux/clkdev.h>
 21 #include <linux/of.h>
 22 #include <linux/of_address.h>
 23 #include <linux/delay.h>
 24 #include <linux/export.h>
 25 #include <linux/clk/tegra.h>
 26 #include <dt-bindings/clock/tegra124-car.h>
 27 
 28 #include "clk.h"
 29 #include "clk-id.h"
 30 
 31 /*
 32  * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
 33  * banks present in the Tegra124/132 CAR IP block.  The banks are
 34  * identified by single letters, e.g.: L, H, U, V, W, X.  See
 35  * periph_regs[] in drivers/clk/tegra/clk.c
 36  */
 37 #define TEGRA124_CAR_BANK_COUNT                 6
 38 
 39 #define CLK_SOURCE_CSITE 0x1d4
 40 #define CLK_SOURCE_EMC 0x19c
 41 
 42 #define PLLC_BASE 0x80
 43 #define PLLC_OUT 0x84
 44 #define PLLC_MISC2 0x88
 45 #define PLLC_MISC 0x8c
 46 #define PLLC2_BASE 0x4e8
 47 #define PLLC2_MISC 0x4ec
 48 #define PLLC3_BASE 0x4fc
 49 #define PLLC3_MISC 0x500
 50 #define PLLM_BASE 0x90
 51 #define PLLM_OUT 0x94
 52 #define PLLM_MISC 0x9c
 53 #define PLLP_BASE 0xa0
 54 #define PLLP_MISC 0xac
 55 #define PLLA_BASE 0xb0
 56 #define PLLA_MISC 0xbc
 57 #define PLLD_BASE 0xd0
 58 #define PLLD_MISC 0xdc
 59 #define PLLU_BASE 0xc0
 60 #define PLLU_MISC 0xcc
 61 #define PLLX_BASE 0xe0
 62 #define PLLX_MISC 0xe4
 63 #define PLLX_MISC2 0x514
 64 #define PLLX_MISC3 0x518
 65 #define PLLE_BASE 0xe8
 66 #define PLLE_MISC 0xec
 67 #define PLLD2_BASE 0x4b8
 68 #define PLLD2_MISC 0x4bc
 69 #define PLLE_AUX 0x48c
 70 #define PLLRE_BASE 0x4c4
 71 #define PLLRE_MISC 0x4c8
 72 #define PLLDP_BASE 0x590
 73 #define PLLDP_MISC 0x594
 74 #define PLLC4_BASE 0x5a4
 75 #define PLLC4_MISC 0x5a8
 76 
 77 #define PLLC_IDDQ_BIT 26
 78 #define PLLRE_IDDQ_BIT 16
 79 #define PLLSS_IDDQ_BIT 19
 80 
 81 #define PLL_BASE_LOCK BIT(27)
 82 #define PLLE_MISC_LOCK BIT(11)
 83 #define PLLRE_MISC_LOCK BIT(24)
 84 
 85 #define PLL_MISC_LOCK_ENABLE 18
 86 #define PLLC_MISC_LOCK_ENABLE 24
 87 #define PLLDU_MISC_LOCK_ENABLE 22
 88 #define PLLE_MISC_LOCK_ENABLE 9
 89 #define PLLRE_MISC_LOCK_ENABLE 30
 90 #define PLLSS_MISC_LOCK_ENABLE 30
 91 
 92 #define PLLXC_SW_MAX_P 6
 93 
 94 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 95 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 96 
 97 #define UTMIP_PLL_CFG2 0x488
 98 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 99 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
100 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
101 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
102 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
103 
104 #define UTMIP_PLL_CFG1 0x484
105 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
106 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
107 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
108 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
109 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
110 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
111 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
112 
113 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
114 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
115 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
116 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
117 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
118 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
119 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
120 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
121 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
122 
123 /* Tegra CPU clock and reset control regs */
124 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
125 
126 #ifdef CONFIG_PM_SLEEP
127 static struct cpu_clk_suspend_context {
128         u32 clk_csite_src;
129 } tegra124_cpu_clk_sctx;
130 #endif
131 
132 static void __iomem *clk_base;
133 static void __iomem *pmc_base;
134 
135 static unsigned long osc_freq;
136 static unsigned long pll_ref_freq;
137 
138 static DEFINE_SPINLOCK(pll_d_lock);
139 static DEFINE_SPINLOCK(pll_e_lock);
140 static DEFINE_SPINLOCK(pll_re_lock);
141 static DEFINE_SPINLOCK(pll_u_lock);
142 static DEFINE_SPINLOCK(emc_lock);
143 
144 /* possible OSC frequencies in Hz */
145 static unsigned long tegra124_input_freq[] = {
146         [0] = 13000000,
147         [1] = 16800000,
148         [4] = 19200000,
149         [5] = 38400000,
150         [8] = 12000000,
151         [9] = 48000000,
152         [12] = 260000000,
153 };
154 
155 static struct div_nmp pllxc_nmp = {
156         .divm_shift = 0,
157         .divm_width = 8,
158         .divn_shift = 8,
159         .divn_width = 8,
160         .divp_shift = 20,
161         .divp_width = 4,
162 };
163 
164 static struct pdiv_map pllxc_p[] = {
165         { .pdiv = 1, .hw_val = 0 },
166         { .pdiv = 2, .hw_val = 1 },
167         { .pdiv = 3, .hw_val = 2 },
168         { .pdiv = 4, .hw_val = 3 },
169         { .pdiv = 5, .hw_val = 4 },
170         { .pdiv = 6, .hw_val = 5 },
171         { .pdiv = 8, .hw_val = 6 },
172         { .pdiv = 10, .hw_val = 7 },
173         { .pdiv = 12, .hw_val = 8 },
174         { .pdiv = 16, .hw_val = 9 },
175         { .pdiv = 12, .hw_val = 10 },
176         { .pdiv = 16, .hw_val = 11 },
177         { .pdiv = 20, .hw_val = 12 },
178         { .pdiv = 24, .hw_val = 13 },
179         { .pdiv = 32, .hw_val = 14 },
180         { .pdiv = 0, .hw_val = 0 },
181 };
182 
183 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
184         /* 1 GHz */
185         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
186         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
187         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
188         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
189         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
190         {0, 0, 0, 0, 0, 0},
191 };
192 
193 static struct tegra_clk_pll_params pll_x_params = {
194         .input_min = 12000000,
195         .input_max = 800000000,
196         .cf_min = 12000000,
197         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
198         .vco_min = 700000000,
199         .vco_max = 3000000000UL,
200         .base_reg = PLLX_BASE,
201         .misc_reg = PLLX_MISC,
202         .lock_mask = PLL_BASE_LOCK,
203         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
204         .lock_delay = 300,
205         .iddq_reg = PLLX_MISC3,
206         .iddq_bit_idx = 3,
207         .max_p = 6,
208         .dyn_ramp_reg = PLLX_MISC2,
209         .stepa_shift = 16,
210         .stepb_shift = 24,
211         .pdiv_tohw = pllxc_p,
212         .div_nmp = &pllxc_nmp,
213         .freq_table = pll_x_freq_table,
214         .flags = TEGRA_PLL_USE_LOCK,
215 };
216 
217 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
218         { 12000000, 624000000, 104, 1, 2},
219         { 12000000, 600000000, 100, 1, 2},
220         { 13000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
221         { 16800000, 600000000,  71, 1, 2},      /* actual: 596.4 MHz */
222         { 19200000, 600000000,  62, 1, 2},      /* actual: 595.2 MHz */
223         { 26000000, 600000000,  92, 2, 2},      /* actual: 598.0 MHz */
224         { 0, 0, 0, 0, 0, 0 },
225 };
226 
227 static struct tegra_clk_pll_params pll_c_params = {
228         .input_min = 12000000,
229         .input_max = 800000000,
230         .cf_min = 12000000,
231         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
232         .vco_min = 600000000,
233         .vco_max = 1400000000,
234         .base_reg = PLLC_BASE,
235         .misc_reg = PLLC_MISC,
236         .lock_mask = PLL_BASE_LOCK,
237         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
238         .lock_delay = 300,
239         .iddq_reg = PLLC_MISC,
240         .iddq_bit_idx = PLLC_IDDQ_BIT,
241         .max_p = PLLXC_SW_MAX_P,
242         .dyn_ramp_reg = PLLC_MISC2,
243         .stepa_shift = 17,
244         .stepb_shift = 9,
245         .pdiv_tohw = pllxc_p,
246         .div_nmp = &pllxc_nmp,
247         .freq_table = pll_c_freq_table,
248         .flags = TEGRA_PLL_USE_LOCK,
249 };
250 
251 static struct div_nmp pllcx_nmp = {
252         .divm_shift = 0,
253         .divm_width = 2,
254         .divn_shift = 8,
255         .divn_width = 8,
256         .divp_shift = 20,
257         .divp_width = 3,
258 };
259 
260 static struct pdiv_map pllc_p[] = {
261         { .pdiv = 1, .hw_val = 0 },
262         { .pdiv = 2, .hw_val = 1 },
263         { .pdiv = 3, .hw_val = 2 },
264         { .pdiv = 4, .hw_val = 3 },
265         { .pdiv = 6, .hw_val = 4 },
266         { .pdiv = 8, .hw_val = 5 },
267         { .pdiv = 12, .hw_val = 6 },
268         { .pdiv = 16, .hw_val = 7 },
269         { .pdiv = 0, .hw_val = 0 },
270 };
271 
272 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
273         {12000000, 600000000, 100, 1, 2},
274         {13000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
275         {16800000, 600000000, 71, 1, 2},        /* actual: 596.4 MHz */
276         {19200000, 600000000, 62, 1, 2},        /* actual: 595.2 MHz */
277         {26000000, 600000000, 92, 2, 2},        /* actual: 598.0 MHz */
278         {0, 0, 0, 0, 0, 0},
279 };
280 
281 static struct tegra_clk_pll_params pll_c2_params = {
282         .input_min = 12000000,
283         .input_max = 48000000,
284         .cf_min = 12000000,
285         .cf_max = 19200000,
286         .vco_min = 600000000,
287         .vco_max = 1200000000,
288         .base_reg = PLLC2_BASE,
289         .misc_reg = PLLC2_MISC,
290         .lock_mask = PLL_BASE_LOCK,
291         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
292         .lock_delay = 300,
293         .pdiv_tohw = pllc_p,
294         .div_nmp = &pllcx_nmp,
295         .max_p = 7,
296         .ext_misc_reg[0] = 0x4f0,
297         .ext_misc_reg[1] = 0x4f4,
298         .ext_misc_reg[2] = 0x4f8,
299         .freq_table = pll_cx_freq_table,
300         .flags = TEGRA_PLL_USE_LOCK,
301 };
302 
303 static struct tegra_clk_pll_params pll_c3_params = {
304         .input_min = 12000000,
305         .input_max = 48000000,
306         .cf_min = 12000000,
307         .cf_max = 19200000,
308         .vco_min = 600000000,
309         .vco_max = 1200000000,
310         .base_reg = PLLC3_BASE,
311         .misc_reg = PLLC3_MISC,
312         .lock_mask = PLL_BASE_LOCK,
313         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
314         .lock_delay = 300,
315         .pdiv_tohw = pllc_p,
316         .div_nmp = &pllcx_nmp,
317         .max_p = 7,
318         .ext_misc_reg[0] = 0x504,
319         .ext_misc_reg[1] = 0x508,
320         .ext_misc_reg[2] = 0x50c,
321         .freq_table = pll_cx_freq_table,
322         .flags = TEGRA_PLL_USE_LOCK,
323 };
324 
325 static struct div_nmp pllss_nmp = {
326         .divm_shift = 0,
327         .divm_width = 8,
328         .divn_shift = 8,
329         .divn_width = 8,
330         .divp_shift = 20,
331         .divp_width = 4,
332 };
333 
334 static struct pdiv_map pll12g_ssd_esd_p[] = {
335         { .pdiv = 1, .hw_val = 0 },
336         { .pdiv = 2, .hw_val = 1 },
337         { .pdiv = 3, .hw_val = 2 },
338         { .pdiv = 4, .hw_val = 3 },
339         { .pdiv = 5, .hw_val = 4 },
340         { .pdiv = 6, .hw_val = 5 },
341         { .pdiv = 8, .hw_val = 6 },
342         { .pdiv = 10, .hw_val = 7 },
343         { .pdiv = 12, .hw_val = 8 },
344         { .pdiv = 16, .hw_val = 9 },
345         { .pdiv = 12, .hw_val = 10 },
346         { .pdiv = 16, .hw_val = 11 },
347         { .pdiv = 20, .hw_val = 12 },
348         { .pdiv = 24, .hw_val = 13 },
349         { .pdiv = 32, .hw_val = 14 },
350         { .pdiv = 0, .hw_val = 0 },
351 };
352 
353 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
354         { 12000000, 600000000, 100, 1, 1},
355         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
356         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
357         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
358         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
359         { 0, 0, 0, 0, 0, 0 },
360 };
361 
362 static struct tegra_clk_pll_params pll_c4_params = {
363         .input_min = 12000000,
364         .input_max = 1000000000,
365         .cf_min = 12000000,
366         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
367         .vco_min = 600000000,
368         .vco_max = 1200000000,
369         .base_reg = PLLC4_BASE,
370         .misc_reg = PLLC4_MISC,
371         .lock_mask = PLL_BASE_LOCK,
372         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
373         .lock_delay = 300,
374         .iddq_reg = PLLC4_BASE,
375         .iddq_bit_idx = PLLSS_IDDQ_BIT,
376         .pdiv_tohw = pll12g_ssd_esd_p,
377         .div_nmp = &pllss_nmp,
378         .ext_misc_reg[0] = 0x5ac,
379         .ext_misc_reg[1] = 0x5b0,
380         .ext_misc_reg[2] = 0x5b4,
381         .freq_table = pll_c4_freq_table,
382 };
383 
384 static struct pdiv_map pllm_p[] = {
385         { .pdiv = 1, .hw_val = 0 },
386         { .pdiv = 2, .hw_val = 1 },
387         { .pdiv = 0, .hw_val = 0 },
388 };
389 
390 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
391         {12000000, 800000000, 66, 1, 1},        /* actual: 792.0 MHz */
392         {13000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
393         {16800000, 800000000, 47, 1, 1},        /* actual: 789.6 MHz */
394         {19200000, 800000000, 41, 1, 1},        /* actual: 787.2 MHz */
395         {26000000, 800000000, 61, 2, 1},        /* actual: 793.0 MHz */
396         {0, 0, 0, 0, 0, 0},
397 };
398 
399 static struct div_nmp pllm_nmp = {
400         .divm_shift = 0,
401         .divm_width = 8,
402         .override_divm_shift = 0,
403         .divn_shift = 8,
404         .divn_width = 8,
405         .override_divn_shift = 8,
406         .divp_shift = 20,
407         .divp_width = 1,
408         .override_divp_shift = 27,
409 };
410 
411 static struct tegra_clk_pll_params pll_m_params = {
412         .input_min = 12000000,
413         .input_max = 500000000,
414         .cf_min = 12000000,
415         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
416         .vco_min = 400000000,
417         .vco_max = 1066000000,
418         .base_reg = PLLM_BASE,
419         .misc_reg = PLLM_MISC,
420         .lock_mask = PLL_BASE_LOCK,
421         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
422         .lock_delay = 300,
423         .max_p = 2,
424         .pdiv_tohw = pllm_p,
425         .div_nmp = &pllm_nmp,
426         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
427         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
428         .freq_table = pll_m_freq_table,
429         .flags = TEGRA_PLL_USE_LOCK,
430 };
431 
432 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
433         /* PLLE special case: use cpcon field to store cml divider value */
434         {336000000, 100000000, 100, 21, 16, 11},
435         {312000000, 100000000, 200, 26, 24, 13},
436         {13000000,  100000000, 200, 1,  26, 13},
437         {12000000,  100000000, 200, 1,  24, 13},
438         {0, 0, 0, 0, 0, 0},
439 };
440 
441 static struct div_nmp plle_nmp = {
442         .divm_shift = 0,
443         .divm_width = 8,
444         .divn_shift = 8,
445         .divn_width = 8,
446         .divp_shift = 24,
447         .divp_width = 4,
448 };
449 
450 static struct tegra_clk_pll_params pll_e_params = {
451         .input_min = 12000000,
452         .input_max = 1000000000,
453         .cf_min = 12000000,
454         .cf_max = 75000000,
455         .vco_min = 1600000000,
456         .vco_max = 2400000000U,
457         .base_reg = PLLE_BASE,
458         .misc_reg = PLLE_MISC,
459         .aux_reg = PLLE_AUX,
460         .lock_mask = PLLE_MISC_LOCK,
461         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
462         .lock_delay = 300,
463         .div_nmp = &plle_nmp,
464         .freq_table = pll_e_freq_table,
465         .flags = TEGRA_PLL_FIXED,
466         .fixed_rate = 100000000,
467 };
468 
469 static const struct clk_div_table pll_re_div_table[] = {
470         { .val = 0, .div = 1 },
471         { .val = 1, .div = 2 },
472         { .val = 2, .div = 3 },
473         { .val = 3, .div = 4 },
474         { .val = 4, .div = 5 },
475         { .val = 5, .div = 6 },
476         { .val = 0, .div = 0 },
477 };
478 
479 static struct div_nmp pllre_nmp = {
480         .divm_shift = 0,
481         .divm_width = 8,
482         .divn_shift = 8,
483         .divn_width = 8,
484         .divp_shift = 16,
485         .divp_width = 4,
486 };
487 
488 static struct tegra_clk_pll_params pll_re_vco_params = {
489         .input_min = 12000000,
490         .input_max = 1000000000,
491         .cf_min = 12000000,
492         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
493         .vco_min = 300000000,
494         .vco_max = 600000000,
495         .base_reg = PLLRE_BASE,
496         .misc_reg = PLLRE_MISC,
497         .lock_mask = PLLRE_MISC_LOCK,
498         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
499         .lock_delay = 300,
500         .iddq_reg = PLLRE_MISC,
501         .iddq_bit_idx = PLLRE_IDDQ_BIT,
502         .div_nmp = &pllre_nmp,
503         .flags = TEGRA_PLL_USE_LOCK,
504 };
505 
506 static struct div_nmp pllp_nmp = {
507         .divm_shift = 0,
508         .divm_width = 5,
509         .divn_shift = 8,
510         .divn_width = 10,
511         .divp_shift = 20,
512         .divp_width = 3,
513 };
514 
515 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
516         {12000000, 408000000, 408, 12, 0, 8},
517         {13000000, 408000000, 408, 13, 0, 8},
518         {16800000, 408000000, 340, 14, 0, 8},
519         {19200000, 408000000, 340, 16, 0, 8},
520         {26000000, 408000000, 408, 26, 0, 8},
521         {0, 0, 0, 0, 0, 0},
522 };
523 
524 static struct tegra_clk_pll_params pll_p_params = {
525         .input_min = 2000000,
526         .input_max = 31000000,
527         .cf_min = 1000000,
528         .cf_max = 6000000,
529         .vco_min = 200000000,
530         .vco_max = 700000000,
531         .base_reg = PLLP_BASE,
532         .misc_reg = PLLP_MISC,
533         .lock_mask = PLL_BASE_LOCK,
534         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
535         .lock_delay = 300,
536         .div_nmp = &pllp_nmp,
537         .freq_table = pll_p_freq_table,
538         .fixed_rate = 408000000,
539         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
540 };
541 
542 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
543         {9600000, 282240000, 147, 5, 0, 4},
544         {9600000, 368640000, 192, 5, 0, 4},
545         {9600000, 240000000, 200, 8, 0, 8},
546 
547         {28800000, 282240000, 245, 25, 0, 8},
548         {28800000, 368640000, 320, 25, 0, 8},
549         {28800000, 240000000, 200, 24, 0, 8},
550         {0, 0, 0, 0, 0, 0},
551 };
552 
553 static struct tegra_clk_pll_params pll_a_params = {
554         .input_min = 2000000,
555         .input_max = 31000000,
556         .cf_min = 1000000,
557         .cf_max = 6000000,
558         .vco_min = 200000000,
559         .vco_max = 700000000,
560         .base_reg = PLLA_BASE,
561         .misc_reg = PLLA_MISC,
562         .lock_mask = PLL_BASE_LOCK,
563         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
564         .lock_delay = 300,
565         .div_nmp = &pllp_nmp,
566         .freq_table = pll_a_freq_table,
567         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
568 };
569 
570 static struct div_nmp plld_nmp = {
571         .divm_shift = 0,
572         .divm_width = 5,
573         .divn_shift = 8,
574         .divn_width = 11,
575         .divp_shift = 20,
576         .divp_width = 3,
577 };
578 
579 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
580         {12000000, 216000000, 864, 12, 4, 12},
581         {13000000, 216000000, 864, 13, 4, 12},
582         {16800000, 216000000, 720, 14, 4, 12},
583         {19200000, 216000000, 720, 16, 4, 12},
584         {26000000, 216000000, 864, 26, 4, 12},
585 
586         {12000000, 594000000, 594, 12, 1, 12},
587         {13000000, 594000000, 594, 13, 1, 12},
588         {16800000, 594000000, 495, 14, 1, 12},
589         {19200000, 594000000, 495, 16, 1, 12},
590         {26000000, 594000000, 594, 26, 1, 12},
591 
592         {12000000, 1000000000, 1000, 12, 1, 12},
593         {13000000, 1000000000, 1000, 13, 1, 12},
594         {19200000, 1000000000, 625, 12, 1, 12},
595         {26000000, 1000000000, 1000, 26, 1, 12},
596 
597         {0, 0, 0, 0, 0, 0},
598 };
599 
600 static struct tegra_clk_pll_params pll_d_params = {
601         .input_min = 2000000,
602         .input_max = 40000000,
603         .cf_min = 1000000,
604         .cf_max = 6000000,
605         .vco_min = 500000000,
606         .vco_max = 1000000000,
607         .base_reg = PLLD_BASE,
608         .misc_reg = PLLD_MISC,
609         .lock_mask = PLL_BASE_LOCK,
610         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
611         .lock_delay = 1000,
612         .div_nmp = &plld_nmp,
613         .freq_table = pll_d_freq_table,
614         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
615                  TEGRA_PLL_USE_LOCK,
616 };
617 
618 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
619         { 12000000, 594000000,  99, 1, 2},
620         { 13000000, 594000000,  91, 1, 2},      /* actual: 591.5 MHz */
621         { 16800000, 594000000,  71, 1, 2},      /* actual: 596.4 MHz */
622         { 19200000, 594000000,  62, 1, 2},      /* actual: 595.2 MHz */
623         { 26000000, 594000000,  91, 2, 2},      /* actual: 591.5 MHz */
624         { 0, 0, 0, 0, 0, 0 },
625 };
626 
627 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
628         .input_min = 12000000,
629         .input_max = 1000000000,
630         .cf_min = 12000000,
631         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
632         .vco_min = 600000000,
633         .vco_max = 1200000000,
634         .base_reg = PLLD2_BASE,
635         .misc_reg = PLLD2_MISC,
636         .lock_mask = PLL_BASE_LOCK,
637         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
638         .lock_delay = 300,
639         .iddq_reg = PLLD2_BASE,
640         .iddq_bit_idx = PLLSS_IDDQ_BIT,
641         .pdiv_tohw = pll12g_ssd_esd_p,
642         .div_nmp = &pllss_nmp,
643         .ext_misc_reg[0] = 0x570,
644         .ext_misc_reg[1] = 0x574,
645         .ext_misc_reg[2] = 0x578,
646         .max_p = 15,
647         .freq_table = tegra124_pll_d2_freq_table,
648 };
649 
650 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
651         { 12000000, 600000000, 100, 1, 1},
652         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
653         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
654         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
655         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
656         { 0, 0, 0, 0, 0, 0 },
657 };
658 
659 static struct tegra_clk_pll_params pll_dp_params = {
660         .input_min = 12000000,
661         .input_max = 1000000000,
662         .cf_min = 12000000,
663         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
664         .vco_min = 600000000,
665         .vco_max = 1200000000,
666         .base_reg = PLLDP_BASE,
667         .misc_reg = PLLDP_MISC,
668         .lock_mask = PLL_BASE_LOCK,
669         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
670         .lock_delay = 300,
671         .iddq_reg = PLLDP_BASE,
672         .iddq_bit_idx = PLLSS_IDDQ_BIT,
673         .pdiv_tohw = pll12g_ssd_esd_p,
674         .div_nmp = &pllss_nmp,
675         .ext_misc_reg[0] = 0x598,
676         .ext_misc_reg[1] = 0x59c,
677         .ext_misc_reg[2] = 0x5a0,
678         .max_p = 5,
679         .freq_table = pll_dp_freq_table,
680 };
681 
682 static struct pdiv_map pllu_p[] = {
683         { .pdiv = 1, .hw_val = 1 },
684         { .pdiv = 2, .hw_val = 0 },
685         { .pdiv = 0, .hw_val = 0 },
686 };
687 
688 static struct div_nmp pllu_nmp = {
689         .divm_shift = 0,
690         .divm_width = 5,
691         .divn_shift = 8,
692         .divn_width = 10,
693         .divp_shift = 20,
694         .divp_width = 1,
695 };
696 
697 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
698         {12000000, 480000000, 960, 12, 2, 12},
699         {13000000, 480000000, 960, 13, 2, 12},
700         {16800000, 480000000, 400, 7, 2, 5},
701         {19200000, 480000000, 200, 4, 2, 3},
702         {26000000, 480000000, 960, 26, 2, 12},
703         {0, 0, 0, 0, 0, 0},
704 };
705 
706 static struct tegra_clk_pll_params pll_u_params = {
707         .input_min = 2000000,
708         .input_max = 40000000,
709         .cf_min = 1000000,
710         .cf_max = 6000000,
711         .vco_min = 480000000,
712         .vco_max = 960000000,
713         .base_reg = PLLU_BASE,
714         .misc_reg = PLLU_MISC,
715         .lock_mask = PLL_BASE_LOCK,
716         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
717         .lock_delay = 1000,
718         .pdiv_tohw = pllu_p,
719         .div_nmp = &pllu_nmp,
720         .freq_table = pll_u_freq_table,
721         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
722                  TEGRA_PLL_USE_LOCK,
723 };
724 
725 struct utmi_clk_param {
726         /* Oscillator Frequency in KHz */
727         u32 osc_frequency;
728         /* UTMIP PLL Enable Delay Count  */
729         u8 enable_delay_count;
730         /* UTMIP PLL Stable count */
731         u8 stable_count;
732         /*  UTMIP PLL Active delay count */
733         u8 active_delay_count;
734         /* UTMIP PLL Xtal frequency count */
735         u8 xtal_freq_count;
736 };
737 
738 static const struct utmi_clk_param utmi_parameters[] = {
739         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
740          .stable_count = 0x33, .active_delay_count = 0x05,
741          .xtal_freq_count = 0x7F},
742         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
743          .stable_count = 0x4B, .active_delay_count = 0x06,
744          .xtal_freq_count = 0xBB},
745         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
746          .stable_count = 0x2F, .active_delay_count = 0x04,
747          .xtal_freq_count = 0x76},
748         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
749          .stable_count = 0x66, .active_delay_count = 0x09,
750          .xtal_freq_count = 0xFE},
751         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
752          .stable_count = 0x41, .active_delay_count = 0x0A,
753          .xtal_freq_count = 0xA4},
754 };
755 
756 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
757         [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
758         [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
759         [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
760         [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
761         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
762         [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
763         [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
764         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
765         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
766         [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
767         [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
768         [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
769         [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
770         [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
771         [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
772         [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
773         [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
774         [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
775         [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
776         [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
777         [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
778         [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
779         [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
780         [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
781         [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
782         [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
783         [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
784         [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
785         [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
786         [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
787         [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
788         [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
789         [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
790         [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
791         [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
792         [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
793         [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
794         [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
795         [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
796         [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
797         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
798         [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
799         [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
800         [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
801         [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
802         [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
803         [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
804         [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
805         [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
806         [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
807         [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
808         [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
809         [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
810         [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
811         [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
812         [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
813         [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
814         [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
815         [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
816         [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
817         [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
818         [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
819         [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
820         [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
821         [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
822         [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
823         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
824         [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
825         [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
826         [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
827         [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
828         [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
829         [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
830         [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
831         [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
832         [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
833         [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
834         [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
835         [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
836         [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
837         [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
838         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
839         [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
840         [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
841         [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
842         [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
843         [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
844         [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
845         [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
846         [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
847         [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
848         [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
849         [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
850         [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
851         [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
852         [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
853         [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
854         [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
855         [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
856         [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
857         [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
858         [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
859         [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
860         [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
861         [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
862         [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
863         [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
864         [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
865         [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
866         [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
867         [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
868         [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
869         [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
870         [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
871         [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
872         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
873         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
874         [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
875         [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
876         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
877         [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
878         [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
879         [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
880         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
881         [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
882         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
883         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
884         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
885         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
886         [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
887         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
888         [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
889         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
890         [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
891         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
892         [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
893         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
894         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
895         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
896         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
897         [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
898         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
899         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
900         [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
901         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
902         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
903         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
904         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
905         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
906         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
907         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
908         [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
909         [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
910         [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
911         [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
912         [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
913         [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
914         [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
915         [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
916         [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
917         [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
918         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
919         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
920         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
921         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
922         [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
923         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
924         [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
925         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
926         [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
927         [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
928         [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
929         [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
930         [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
931         [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
932         [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
933         [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
934         [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
935         [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
936         [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
937         [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
938         [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
939         [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
940         [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
941         [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
942         [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
943         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
944         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
945         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
946 };
947 
948 static struct tegra_devclk devclks[] __initdata = {
949         { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
950         { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
951         { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
952         { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
953         { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
954         { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
955         { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
956         { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
957         { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
958         { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
959         { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
960         { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
961         { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
962         { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
963         { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
964         { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
965         { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
966         { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
967         { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
968         { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
969         { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
970         { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
971         { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
972         { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
973         { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
974         { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
975         { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
976         { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
977         { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
978         { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
979         { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
980         { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
981         { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
982         { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
983         { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
984         { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
985         { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
986         { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
987         { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
988         { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
989         { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
990         { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
991         { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
992         { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
993         { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
994         { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
995         { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
996         { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
997         { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
998         { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
999         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1000         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1001         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1002         { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1003         { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1004         { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1005         { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1006         { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1007         { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1008         { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1009         { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1010         { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1011         { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
1012         { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
1013         { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
1014 };
1015 
1016 static struct clk **clks;
1017 
1018 static void tegra124_utmi_param_configure(void __iomem *clk_base)
1019 {
1020         u32 reg;
1021         int i;
1022 
1023         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1024                 if (osc_freq == utmi_parameters[i].osc_frequency)
1025                         break;
1026         }
1027 
1028         if (i >= ARRAY_SIZE(utmi_parameters)) {
1029                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1030                        osc_freq);
1031                 return;
1032         }
1033 
1034         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1035 
1036         /* Program UTMIP PLL stable and active counts */
1037         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1038         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1039         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1040 
1041         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1042 
1043         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1044                                             active_delay_count);
1045 
1046         /* Remove power downs from UTMIP PLL control bits */
1047         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1048         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1049         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1050 
1051         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1052 
1053         /* Program UTMIP PLL delay and oscillator frequency counts */
1054         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1055         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1056 
1057         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1058                                             enable_delay_count);
1059 
1060         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1061         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1062                                            xtal_freq_count);
1063 
1064         /* Remove power downs from UTMIP PLL control bits */
1065         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1066         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1067         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1068         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1069         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1070 
1071         /* Setup HW control of UTMIPLL */
1072         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1073         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1074         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1075         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1076         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1077 
1078         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1079         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1080         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1081         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1082 
1083         udelay(1);
1084 
1085         /* Setup SW override of UTMIPLL assuming USB2.0
1086            ports are assigned to USB2 */
1087         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1088         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1089         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1090         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1091 
1092         udelay(1);
1093 
1094         /* Enable HW control UTMIPLL */
1095         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1096         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1097         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1098 }
1099 
1100 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1101                                             void __iomem *pmc_base)
1102 {
1103         struct clk *clk;
1104 
1105         /* xusb_ss_div2 */
1106         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1107                                         1, 2);
1108         clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1109 
1110         clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
1111                                 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1112         clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1113 
1114         clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
1115                                              clk_base, 0, 48,
1116                                              periph_clk_enb_refcnt);
1117         clks[TEGRA124_CLK_DSIA] = clk;
1118 
1119         clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
1120                                              clk_base, 0, 82,
1121                                              periph_clk_enb_refcnt);
1122         clks[TEGRA124_CLK_DSIB] = clk;
1123 
1124         clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1125                                     &emc_lock);
1126         clks[TEGRA124_CLK_MC] = clk;
1127 
1128         /* cml0 */
1129         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1130                                 0, 0, &pll_e_lock);
1131         clk_register_clkdev(clk, "cml0", NULL);
1132         clks[TEGRA124_CLK_CML0] = clk;
1133 
1134         /* cml1 */
1135         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1136                                 1, 0, &pll_e_lock);
1137         clk_register_clkdev(clk, "cml1", NULL);
1138         clks[TEGRA124_CLK_CML1] = clk;
1139 
1140         tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1141 }
1142 
1143 static void __init tegra124_pll_init(void __iomem *clk_base,
1144                                      void __iomem *pmc)
1145 {
1146         u32 val;
1147         struct clk *clk;
1148 
1149         /* PLLC */
1150         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1151                         pmc, 0, &pll_c_params, NULL);
1152         clk_register_clkdev(clk, "pll_c", NULL);
1153         clks[TEGRA124_CLK_PLL_C] = clk;
1154 
1155         /* PLLC_OUT1 */
1156         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1157                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1158                         8, 8, 1, NULL);
1159         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1160                                 clk_base + PLLC_OUT, 1, 0,
1161                                 CLK_SET_RATE_PARENT, 0, NULL);
1162         clk_register_clkdev(clk, "pll_c_out1", NULL);
1163         clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1164 
1165         /* PLLC_UD */
1166         clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
1167                                         CLK_SET_RATE_PARENT, 1, 1);
1168         clk_register_clkdev(clk, "pll_c_ud", NULL);
1169         clks[TEGRA124_CLK_PLL_C_UD] = clk;
1170 
1171         /* PLLC2 */
1172         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1173                              &pll_c2_params, NULL);
1174         clk_register_clkdev(clk, "pll_c2", NULL);
1175         clks[TEGRA124_CLK_PLL_C2] = clk;
1176 
1177         /* PLLC3 */
1178         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1179                              &pll_c3_params, NULL);
1180         clk_register_clkdev(clk, "pll_c3", NULL);
1181         clks[TEGRA124_CLK_PLL_C3] = clk;
1182 
1183         /* PLLM */
1184         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1185                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1186                              &pll_m_params, NULL);
1187         clk_register_clkdev(clk, "pll_m", NULL);
1188         clks[TEGRA124_CLK_PLL_M] = clk;
1189 
1190         /* PLLM_OUT1 */
1191         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1192                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1193                                 8, 8, 1, NULL);
1194         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1195                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1196                                 CLK_SET_RATE_PARENT, 0, NULL);
1197         clk_register_clkdev(clk, "pll_m_out1", NULL);
1198         clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1199 
1200         /* PLLM_UD */
1201         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1202                                         CLK_SET_RATE_PARENT, 1, 1);
1203         clk_register_clkdev(clk, "pll_m_ud", NULL);
1204         clks[TEGRA124_CLK_PLL_M_UD] = clk;
1205 
1206         /* PLLU */
1207         val = readl(clk_base + pll_u_params.base_reg);
1208         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1209         writel(val, clk_base + pll_u_params.base_reg);
1210 
1211         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1212                             &pll_u_params, &pll_u_lock);
1213         clk_register_clkdev(clk, "pll_u", NULL);
1214         clks[TEGRA124_CLK_PLL_U] = clk;
1215 
1216         tegra124_utmi_param_configure(clk_base);
1217 
1218         /* PLLU_480M */
1219         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1220                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1221                                 22, 0, &pll_u_lock);
1222         clk_register_clkdev(clk, "pll_u_480M", NULL);
1223         clks[TEGRA124_CLK_PLL_U_480M] = clk;
1224 
1225         /* PLLU_60M */
1226         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1227                                         CLK_SET_RATE_PARENT, 1, 8);
1228         clk_register_clkdev(clk, "pll_u_60M", NULL);
1229         clks[TEGRA124_CLK_PLL_U_60M] = clk;
1230 
1231         /* PLLU_48M */
1232         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1233                                         CLK_SET_RATE_PARENT, 1, 10);
1234         clk_register_clkdev(clk, "pll_u_48M", NULL);
1235         clks[TEGRA124_CLK_PLL_U_48M] = clk;
1236 
1237         /* PLLU_12M */
1238         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1239                                         CLK_SET_RATE_PARENT, 1, 40);
1240         clk_register_clkdev(clk, "pll_u_12M", NULL);
1241         clks[TEGRA124_CLK_PLL_U_12M] = clk;
1242 
1243         /* PLLD */
1244         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1245                             &pll_d_params, &pll_d_lock);
1246         clk_register_clkdev(clk, "pll_d", NULL);
1247         clks[TEGRA124_CLK_PLL_D] = clk;
1248 
1249         /* PLLD_OUT0 */
1250         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1251                                         CLK_SET_RATE_PARENT, 1, 2);
1252         clk_register_clkdev(clk, "pll_d_out0", NULL);
1253         clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1254 
1255         /* PLLRE */
1256         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1257                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1258         clk_register_clkdev(clk, "pll_re_vco", NULL);
1259         clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1260 
1261         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1262                                          clk_base + PLLRE_BASE, 16, 4, 0,
1263                                          pll_re_div_table, &pll_re_lock);
1264         clk_register_clkdev(clk, "pll_re_out", NULL);
1265         clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1266 
1267         /* PLLE */
1268         clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1269                                       clk_base, 0, &pll_e_params, NULL);
1270         clk_register_clkdev(clk, "pll_e", NULL);
1271         clks[TEGRA124_CLK_PLL_E] = clk;
1272 
1273         /* PLLC4 */
1274         clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1275                                         &pll_c4_params, NULL);
1276         clk_register_clkdev(clk, "pll_c4", NULL);
1277         clks[TEGRA124_CLK_PLL_C4] = clk;
1278 
1279         /* PLLDP */
1280         clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1281                                         &pll_dp_params, NULL);
1282         clk_register_clkdev(clk, "pll_dp", NULL);
1283         clks[TEGRA124_CLK_PLL_DP] = clk;
1284 
1285         /* PLLD2 */
1286         clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1287                                         &tegra124_pll_d2_params, NULL);
1288         clk_register_clkdev(clk, "pll_d2", NULL);
1289         clks[TEGRA124_CLK_PLL_D2] = clk;
1290 
1291         /* PLLD2_OUT0 */
1292         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1293                                         CLK_SET_RATE_PARENT, 1, 1);
1294         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1295         clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1296 
1297 }
1298 
1299 /* Tegra124 CPU clock and reset control functions */
1300 static void tegra124_wait_cpu_in_reset(u32 cpu)
1301 {
1302         unsigned int reg;
1303 
1304         do {
1305                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1306                 cpu_relax();
1307         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1308 }
1309 
1310 static void tegra124_disable_cpu_clock(u32 cpu)
1311 {
1312         /* flow controller would take care in the power sequence. */
1313 }
1314 
1315 #ifdef CONFIG_PM_SLEEP
1316 static void tegra124_cpu_clock_suspend(void)
1317 {
1318         /* switch coresite to clk_m, save off original source */
1319         tegra124_cpu_clk_sctx.clk_csite_src =
1320                                 readl(clk_base + CLK_SOURCE_CSITE);
1321         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1322 }
1323 
1324 static void tegra124_cpu_clock_resume(void)
1325 {
1326         writel(tegra124_cpu_clk_sctx.clk_csite_src,
1327                                 clk_base + CLK_SOURCE_CSITE);
1328 }
1329 #endif
1330 
1331 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1332         .wait_for_reset = tegra124_wait_cpu_in_reset,
1333         .disable_clock  = tegra124_disable_cpu_clock,
1334 #ifdef CONFIG_PM_SLEEP
1335         .suspend        = tegra124_cpu_clock_suspend,
1336         .resume         = tegra124_cpu_clock_resume,
1337 #endif
1338 };
1339 
1340 static const struct of_device_id pmc_match[] __initconst = {
1341         { .compatible = "nvidia,tegra124-pmc" },
1342         {},
1343 };
1344 
1345 static struct tegra_clk_init_table common_init_table[] __initdata = {
1346         {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1347         {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1348         {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1349         {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1350         {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1351         {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1352         {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
1353         {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
1354         {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1355         {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1356         {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1357         {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1358         {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1359         {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1360         {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1361         {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1362         {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
1363         {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
1364         {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1365         {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1366         {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1367         {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1368         {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1369         {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1370         {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1371         {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1372         {TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
1373         {TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0},
1374         {TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0},
1375         {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
1376         {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
1377         {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
1378         {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1379         {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1380         {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1381         {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1382         {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
1383         /* This MUST be the last entry. */
1384         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1385 };
1386 
1387 static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1388         {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1389         {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1390         {TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
1391         {TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
1392         /* This MUST be the last entry. */
1393         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1394 };
1395 
1396 /* Tegra132 requires the SOC_THERM clock to remain active */
1397 static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1398         {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
1399         /* This MUST be the last entry. */
1400         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1401 };
1402 
1403 /**
1404  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1405  *
1406  * Program an initial clock rate and enable or disable clocks needed
1407  * by the rest of the kernel, for Tegra124 SoCs.  It is intended to be
1408  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1409  * this will be called as an arch_initcall.  No return value.
1410  */
1411 static void __init tegra124_clock_apply_init_table(void)
1412 {
1413         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1414         tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1415 }
1416 
1417 /**
1418  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1419  *
1420  * Program an initial clock rate and enable or disable clocks needed
1421  * by the rest of the kernel, for Tegra132 SoCs.  It is intended to be
1422  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1423  * this will be called as an arch_initcall.  No return value.
1424  */
1425 static void __init tegra132_clock_apply_init_table(void)
1426 {
1427         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1428         tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1429 }
1430 
1431 /**
1432  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1433  * @np: struct device_node * of the DT node for the SoC CAR IP block
1434  *
1435  * Register most of the clocks controlled by the CAR IP block, along
1436  * with a few clocks controlled by the PMC IP block.  Everything in
1437  * this function should be common to Tegra124 and Tegra132.  XXX The
1438  * PMC clock initialization should probably be moved to PMC-specific
1439  * driver code.  No return value.
1440  */
1441 static void __init tegra124_132_clock_init_pre(struct device_node *np)
1442 {
1443         struct device_node *node;
1444         u32 plld_base;
1445 
1446         clk_base = of_iomap(np, 0);
1447         if (!clk_base) {
1448                 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1449                 return;
1450         }
1451 
1452         node = of_find_matching_node(NULL, pmc_match);
1453         if (!node) {
1454                 pr_err("Failed to find pmc node\n");
1455                 WARN_ON(1);
1456                 return;
1457         }
1458 
1459         pmc_base = of_iomap(node, 0);
1460         if (!pmc_base) {
1461                 pr_err("Can't map pmc registers\n");
1462                 WARN_ON(1);
1463                 return;
1464         }
1465 
1466         clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1467                               TEGRA124_CAR_BANK_COUNT);
1468         if (!clks)
1469                 return;
1470 
1471         if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1472                                ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
1473                                &pll_ref_freq) < 0)
1474                 return;
1475 
1476         tegra_fixed_clk_init(tegra124_clks);
1477         tegra124_pll_init(clk_base, pmc_base);
1478         tegra124_periph_clk_init(clk_base, pmc_base);
1479         tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1480         tegra_pmc_clk_init(pmc_base, tegra124_clks);
1481 
1482         /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1483         plld_base = clk_readl(clk_base + PLLD_BASE);
1484         plld_base &= ~BIT(25);
1485         clk_writel(plld_base, clk_base + PLLD_BASE);
1486 }
1487 
1488 /**
1489  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1490  * @np: struct device_node * of the DT node for the SoC CAR IP block
1491  *
1492  * Register most of the along with a few clocks controlled by the PMC
1493  * IP block.  Everything in this function should be common to Tegra124
1494  * and Tegra132.  This function must be called after
1495  * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1496  * not be set.  No return value.
1497  */
1498 static void __init tegra124_132_clock_init_post(struct device_node *np)
1499 {
1500         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1501                                   &pll_x_params);
1502         tegra_add_of_provider(np);
1503 
1504         clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
1505                                                         &emc_lock);
1506 
1507         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1508 
1509         tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1510 }
1511 
1512 /**
1513  * tegra124_clock_init - Tegra124-specific clock initialization
1514  * @np: struct device_node * of the DT node for the SoC CAR IP block
1515  *
1516  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1517  * this code is shared between the Tegra124 and Tegra132 SoCs,
1518  * although some of the initial clock settings and CPU clocks differ.
1519  * Intended to be called by the OF init code when a DT node with the
1520  * "nvidia,tegra124-car" string is encountered, and declared with
1521  * CLK_OF_DECLARE.  No return value.
1522  */
1523 static void __init tegra124_clock_init(struct device_node *np)
1524 {
1525         tegra124_132_clock_init_pre(np);
1526         tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1527         tegra124_132_clock_init_post(np);
1528 }
1529 
1530 /**
1531  * tegra132_clock_init - Tegra132-specific clock initialization
1532  * @np: struct device_node * of the DT node for the SoC CAR IP block
1533  *
1534  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1535  * this code is shared between the Tegra124 and Tegra132 SoCs,
1536  * although some of the initial clock settings and CPU clocks differ.
1537  * Intended to be called by the OF init code when a DT node with the
1538  * "nvidia,tegra132-car" string is encountered, and declared with
1539  * CLK_OF_DECLARE.  No return value.
1540  */
1541 static void __init tegra132_clock_init(struct device_node *np)
1542 {
1543         tegra124_132_clock_init_pre(np);
1544 
1545         /*
1546          * On Tegra132, these clocks are controlled by the
1547          * CLUSTER_clocks IP block, located in the CPU complex
1548          */
1549         tegra124_clks[tegra_clk_cclk_g].present = false;
1550         tegra124_clks[tegra_clk_cclk_lp].present = false;
1551         tegra124_clks[tegra_clk_pll_x].present = false;
1552         tegra124_clks[tegra_clk_pll_x_out0].present = false;
1553 
1554         tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1555         tegra124_132_clock_init_post(np);
1556 }
1557 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1558 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
1559 

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