Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/drivers/clk/tegra/clk-tegra124.c

  1 /*
  2  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk-provider.h>
 19 #include <linux/clkdev.h>
 20 #include <linux/of.h>
 21 #include <linux/of_address.h>
 22 #include <linux/delay.h>
 23 #include <linux/export.h>
 24 #include <linux/clk/tegra.h>
 25 #include <dt-bindings/clock/tegra124-car.h>
 26 #include <dt-bindings/reset/tegra124-car.h>
 27 
 28 #include "clk.h"
 29 #include "clk-id.h"
 30 
 31 /*
 32  * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
 33  * banks present in the Tegra124/132 CAR IP block.  The banks are
 34  * identified by single letters, e.g.: L, H, U, V, W, X.  See
 35  * periph_regs[] in drivers/clk/tegra/clk.c
 36  */
 37 #define TEGRA124_CAR_BANK_COUNT                 6
 38 
 39 #define CLK_SOURCE_CSITE 0x1d4
 40 #define CLK_SOURCE_EMC 0x19c
 41 
 42 #define RST_DFLL_DVCO                   0x2f4
 43 #define DVFS_DFLL_RESET_SHIFT           0
 44 
 45 #define PLLC_BASE 0x80
 46 #define PLLC_OUT 0x84
 47 #define PLLC_MISC2 0x88
 48 #define PLLC_MISC 0x8c
 49 #define PLLC2_BASE 0x4e8
 50 #define PLLC2_MISC 0x4ec
 51 #define PLLC3_BASE 0x4fc
 52 #define PLLC3_MISC 0x500
 53 #define PLLM_BASE 0x90
 54 #define PLLM_OUT 0x94
 55 #define PLLM_MISC 0x9c
 56 #define PLLP_BASE 0xa0
 57 #define PLLP_MISC 0xac
 58 #define PLLA_BASE 0xb0
 59 #define PLLA_MISC 0xbc
 60 #define PLLD_BASE 0xd0
 61 #define PLLD_MISC 0xdc
 62 #define PLLU_BASE 0xc0
 63 #define PLLU_MISC 0xcc
 64 #define PLLX_BASE 0xe0
 65 #define PLLX_MISC 0xe4
 66 #define PLLX_MISC2 0x514
 67 #define PLLX_MISC3 0x518
 68 #define PLLE_BASE 0xe8
 69 #define PLLE_MISC 0xec
 70 #define PLLD2_BASE 0x4b8
 71 #define PLLD2_MISC 0x4bc
 72 #define PLLE_AUX 0x48c
 73 #define PLLRE_BASE 0x4c4
 74 #define PLLRE_MISC 0x4c8
 75 #define PLLDP_BASE 0x590
 76 #define PLLDP_MISC 0x594
 77 #define PLLC4_BASE 0x5a4
 78 #define PLLC4_MISC 0x5a8
 79 
 80 #define PLLC_IDDQ_BIT 26
 81 #define PLLRE_IDDQ_BIT 16
 82 #define PLLSS_IDDQ_BIT 19
 83 
 84 #define PLL_BASE_LOCK BIT(27)
 85 #define PLLE_MISC_LOCK BIT(11)
 86 #define PLLRE_MISC_LOCK BIT(24)
 87 
 88 #define PLL_MISC_LOCK_ENABLE 18
 89 #define PLLC_MISC_LOCK_ENABLE 24
 90 #define PLLDU_MISC_LOCK_ENABLE 22
 91 #define PLLE_MISC_LOCK_ENABLE 9
 92 #define PLLRE_MISC_LOCK_ENABLE 30
 93 #define PLLSS_MISC_LOCK_ENABLE 30
 94 
 95 #define PLLXC_SW_MAX_P 6
 96 
 97 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 98 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 99 
100 #define CCLKG_BURST_POLICY 0x368
101 
102 #define UTMIP_PLL_CFG2 0x488
103 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
104 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
105 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
106 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
107 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
108 
109 #define UTMIP_PLL_CFG1 0x484
110 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
111 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
112 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
113 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
114 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
115 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
116 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
117 
118 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
119 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
120 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
121 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
122 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
123 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
124 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
125 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
126 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
127 
128 /* Tegra CPU clock and reset control regs */
129 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
130 
131 #ifdef CONFIG_PM_SLEEP
132 static struct cpu_clk_suspend_context {
133         u32 clk_csite_src;
134         u32 cclkg_burst;
135         u32 cclkg_divider;
136 } tegra124_cpu_clk_sctx;
137 #endif
138 
139 static void __iomem *clk_base;
140 static void __iomem *pmc_base;
141 
142 static unsigned long osc_freq;
143 static unsigned long pll_ref_freq;
144 
145 static DEFINE_SPINLOCK(pll_d_lock);
146 static DEFINE_SPINLOCK(pll_e_lock);
147 static DEFINE_SPINLOCK(pll_re_lock);
148 static DEFINE_SPINLOCK(pll_u_lock);
149 static DEFINE_SPINLOCK(emc_lock);
150 
151 /* possible OSC frequencies in Hz */
152 static unsigned long tegra124_input_freq[] = {
153         [0] = 13000000,
154         [1] = 16800000,
155         [4] = 19200000,
156         [5] = 38400000,
157         [8] = 12000000,
158         [9] = 48000000,
159         [12] = 260000000,
160 };
161 
162 static struct div_nmp pllxc_nmp = {
163         .divm_shift = 0,
164         .divm_width = 8,
165         .divn_shift = 8,
166         .divn_width = 8,
167         .divp_shift = 20,
168         .divp_width = 4,
169 };
170 
171 static struct pdiv_map pllxc_p[] = {
172         { .pdiv = 1, .hw_val = 0 },
173         { .pdiv = 2, .hw_val = 1 },
174         { .pdiv = 3, .hw_val = 2 },
175         { .pdiv = 4, .hw_val = 3 },
176         { .pdiv = 5, .hw_val = 4 },
177         { .pdiv = 6, .hw_val = 5 },
178         { .pdiv = 8, .hw_val = 6 },
179         { .pdiv = 10, .hw_val = 7 },
180         { .pdiv = 12, .hw_val = 8 },
181         { .pdiv = 16, .hw_val = 9 },
182         { .pdiv = 12, .hw_val = 10 },
183         { .pdiv = 16, .hw_val = 11 },
184         { .pdiv = 20, .hw_val = 12 },
185         { .pdiv = 24, .hw_val = 13 },
186         { .pdiv = 32, .hw_val = 14 },
187         { .pdiv = 0, .hw_val = 0 },
188 };
189 
190 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
191         /* 1 GHz */
192         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
193         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
194         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
195         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
196         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
197         {0, 0, 0, 0, 0, 0},
198 };
199 
200 static struct tegra_clk_pll_params pll_x_params = {
201         .input_min = 12000000,
202         .input_max = 800000000,
203         .cf_min = 12000000,
204         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
205         .vco_min = 700000000,
206         .vco_max = 3000000000UL,
207         .base_reg = PLLX_BASE,
208         .misc_reg = PLLX_MISC,
209         .lock_mask = PLL_BASE_LOCK,
210         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
211         .lock_delay = 300,
212         .iddq_reg = PLLX_MISC3,
213         .iddq_bit_idx = 3,
214         .max_p = 6,
215         .dyn_ramp_reg = PLLX_MISC2,
216         .stepa_shift = 16,
217         .stepb_shift = 24,
218         .pdiv_tohw = pllxc_p,
219         .div_nmp = &pllxc_nmp,
220         .freq_table = pll_x_freq_table,
221         .flags = TEGRA_PLL_USE_LOCK,
222 };
223 
224 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
225         { 12000000, 624000000, 104, 1, 2},
226         { 12000000, 600000000, 100, 1, 2},
227         { 13000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
228         { 16800000, 600000000,  71, 1, 2},      /* actual: 596.4 MHz */
229         { 19200000, 600000000,  62, 1, 2},      /* actual: 595.2 MHz */
230         { 26000000, 600000000,  92, 2, 2},      /* actual: 598.0 MHz */
231         { 0, 0, 0, 0, 0, 0 },
232 };
233 
234 static struct tegra_clk_pll_params pll_c_params = {
235         .input_min = 12000000,
236         .input_max = 800000000,
237         .cf_min = 12000000,
238         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
239         .vco_min = 600000000,
240         .vco_max = 1400000000,
241         .base_reg = PLLC_BASE,
242         .misc_reg = PLLC_MISC,
243         .lock_mask = PLL_BASE_LOCK,
244         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
245         .lock_delay = 300,
246         .iddq_reg = PLLC_MISC,
247         .iddq_bit_idx = PLLC_IDDQ_BIT,
248         .max_p = PLLXC_SW_MAX_P,
249         .dyn_ramp_reg = PLLC_MISC2,
250         .stepa_shift = 17,
251         .stepb_shift = 9,
252         .pdiv_tohw = pllxc_p,
253         .div_nmp = &pllxc_nmp,
254         .freq_table = pll_c_freq_table,
255         .flags = TEGRA_PLL_USE_LOCK,
256 };
257 
258 static struct div_nmp pllcx_nmp = {
259         .divm_shift = 0,
260         .divm_width = 2,
261         .divn_shift = 8,
262         .divn_width = 8,
263         .divp_shift = 20,
264         .divp_width = 3,
265 };
266 
267 static struct pdiv_map pllc_p[] = {
268         { .pdiv = 1, .hw_val = 0 },
269         { .pdiv = 2, .hw_val = 1 },
270         { .pdiv = 3, .hw_val = 2 },
271         { .pdiv = 4, .hw_val = 3 },
272         { .pdiv = 6, .hw_val = 4 },
273         { .pdiv = 8, .hw_val = 5 },
274         { .pdiv = 12, .hw_val = 6 },
275         { .pdiv = 16, .hw_val = 7 },
276         { .pdiv = 0, .hw_val = 0 },
277 };
278 
279 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
280         {12000000, 600000000, 100, 1, 2},
281         {13000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
282         {16800000, 600000000, 71, 1, 2},        /* actual: 596.4 MHz */
283         {19200000, 600000000, 62, 1, 2},        /* actual: 595.2 MHz */
284         {26000000, 600000000, 92, 2, 2},        /* actual: 598.0 MHz */
285         {0, 0, 0, 0, 0, 0},
286 };
287 
288 static struct tegra_clk_pll_params pll_c2_params = {
289         .input_min = 12000000,
290         .input_max = 48000000,
291         .cf_min = 12000000,
292         .cf_max = 19200000,
293         .vco_min = 600000000,
294         .vco_max = 1200000000,
295         .base_reg = PLLC2_BASE,
296         .misc_reg = PLLC2_MISC,
297         .lock_mask = PLL_BASE_LOCK,
298         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
299         .lock_delay = 300,
300         .pdiv_tohw = pllc_p,
301         .div_nmp = &pllcx_nmp,
302         .max_p = 7,
303         .ext_misc_reg[0] = 0x4f0,
304         .ext_misc_reg[1] = 0x4f4,
305         .ext_misc_reg[2] = 0x4f8,
306         .freq_table = pll_cx_freq_table,
307         .flags = TEGRA_PLL_USE_LOCK,
308 };
309 
310 static struct tegra_clk_pll_params pll_c3_params = {
311         .input_min = 12000000,
312         .input_max = 48000000,
313         .cf_min = 12000000,
314         .cf_max = 19200000,
315         .vco_min = 600000000,
316         .vco_max = 1200000000,
317         .base_reg = PLLC3_BASE,
318         .misc_reg = PLLC3_MISC,
319         .lock_mask = PLL_BASE_LOCK,
320         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
321         .lock_delay = 300,
322         .pdiv_tohw = pllc_p,
323         .div_nmp = &pllcx_nmp,
324         .max_p = 7,
325         .ext_misc_reg[0] = 0x504,
326         .ext_misc_reg[1] = 0x508,
327         .ext_misc_reg[2] = 0x50c,
328         .freq_table = pll_cx_freq_table,
329         .flags = TEGRA_PLL_USE_LOCK,
330 };
331 
332 static struct div_nmp pllss_nmp = {
333         .divm_shift = 0,
334         .divm_width = 8,
335         .divn_shift = 8,
336         .divn_width = 8,
337         .divp_shift = 20,
338         .divp_width = 4,
339 };
340 
341 static struct pdiv_map pll12g_ssd_esd_p[] = {
342         { .pdiv = 1, .hw_val = 0 },
343         { .pdiv = 2, .hw_val = 1 },
344         { .pdiv = 3, .hw_val = 2 },
345         { .pdiv = 4, .hw_val = 3 },
346         { .pdiv = 5, .hw_val = 4 },
347         { .pdiv = 6, .hw_val = 5 },
348         { .pdiv = 8, .hw_val = 6 },
349         { .pdiv = 10, .hw_val = 7 },
350         { .pdiv = 12, .hw_val = 8 },
351         { .pdiv = 16, .hw_val = 9 },
352         { .pdiv = 12, .hw_val = 10 },
353         { .pdiv = 16, .hw_val = 11 },
354         { .pdiv = 20, .hw_val = 12 },
355         { .pdiv = 24, .hw_val = 13 },
356         { .pdiv = 32, .hw_val = 14 },
357         { .pdiv = 0, .hw_val = 0 },
358 };
359 
360 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
361         { 12000000, 600000000, 100, 1, 1},
362         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
363         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
364         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
365         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
366         { 0, 0, 0, 0, 0, 0 },
367 };
368 
369 static struct tegra_clk_pll_params pll_c4_params = {
370         .input_min = 12000000,
371         .input_max = 1000000000,
372         .cf_min = 12000000,
373         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
374         .vco_min = 600000000,
375         .vco_max = 1200000000,
376         .base_reg = PLLC4_BASE,
377         .misc_reg = PLLC4_MISC,
378         .lock_mask = PLL_BASE_LOCK,
379         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
380         .lock_delay = 300,
381         .iddq_reg = PLLC4_BASE,
382         .iddq_bit_idx = PLLSS_IDDQ_BIT,
383         .pdiv_tohw = pll12g_ssd_esd_p,
384         .div_nmp = &pllss_nmp,
385         .ext_misc_reg[0] = 0x5ac,
386         .ext_misc_reg[1] = 0x5b0,
387         .ext_misc_reg[2] = 0x5b4,
388         .freq_table = pll_c4_freq_table,
389 };
390 
391 static struct pdiv_map pllm_p[] = {
392         { .pdiv = 1, .hw_val = 0 },
393         { .pdiv = 2, .hw_val = 1 },
394         { .pdiv = 0, .hw_val = 0 },
395 };
396 
397 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
398         {12000000, 800000000, 66, 1, 1},        /* actual: 792.0 MHz */
399         {13000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
400         {16800000, 800000000, 47, 1, 1},        /* actual: 789.6 MHz */
401         {19200000, 800000000, 41, 1, 1},        /* actual: 787.2 MHz */
402         {26000000, 800000000, 61, 2, 1},        /* actual: 793.0 MHz */
403         {0, 0, 0, 0, 0, 0},
404 };
405 
406 static struct div_nmp pllm_nmp = {
407         .divm_shift = 0,
408         .divm_width = 8,
409         .override_divm_shift = 0,
410         .divn_shift = 8,
411         .divn_width = 8,
412         .override_divn_shift = 8,
413         .divp_shift = 20,
414         .divp_width = 1,
415         .override_divp_shift = 27,
416 };
417 
418 static struct tegra_clk_pll_params pll_m_params = {
419         .input_min = 12000000,
420         .input_max = 500000000,
421         .cf_min = 12000000,
422         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
423         .vco_min = 400000000,
424         .vco_max = 1066000000,
425         .base_reg = PLLM_BASE,
426         .misc_reg = PLLM_MISC,
427         .lock_mask = PLL_BASE_LOCK,
428         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
429         .lock_delay = 300,
430         .max_p = 2,
431         .pdiv_tohw = pllm_p,
432         .div_nmp = &pllm_nmp,
433         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
434         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
435         .freq_table = pll_m_freq_table,
436         .flags = TEGRA_PLL_USE_LOCK,
437 };
438 
439 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
440         /* PLLE special case: use cpcon field to store cml divider value */
441         {336000000, 100000000, 100, 21, 16, 11},
442         {312000000, 100000000, 200, 26, 24, 13},
443         {13000000,  100000000, 200, 1,  26, 13},
444         {12000000,  100000000, 200, 1,  24, 13},
445         {0, 0, 0, 0, 0, 0},
446 };
447 
448 static struct div_nmp plle_nmp = {
449         .divm_shift = 0,
450         .divm_width = 8,
451         .divn_shift = 8,
452         .divn_width = 8,
453         .divp_shift = 24,
454         .divp_width = 4,
455 };
456 
457 static struct tegra_clk_pll_params pll_e_params = {
458         .input_min = 12000000,
459         .input_max = 1000000000,
460         .cf_min = 12000000,
461         .cf_max = 75000000,
462         .vco_min = 1600000000,
463         .vco_max = 2400000000U,
464         .base_reg = PLLE_BASE,
465         .misc_reg = PLLE_MISC,
466         .aux_reg = PLLE_AUX,
467         .lock_mask = PLLE_MISC_LOCK,
468         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
469         .lock_delay = 300,
470         .div_nmp = &plle_nmp,
471         .freq_table = pll_e_freq_table,
472         .flags = TEGRA_PLL_FIXED,
473         .fixed_rate = 100000000,
474 };
475 
476 static const struct clk_div_table pll_re_div_table[] = {
477         { .val = 0, .div = 1 },
478         { .val = 1, .div = 2 },
479         { .val = 2, .div = 3 },
480         { .val = 3, .div = 4 },
481         { .val = 4, .div = 5 },
482         { .val = 5, .div = 6 },
483         { .val = 0, .div = 0 },
484 };
485 
486 static struct div_nmp pllre_nmp = {
487         .divm_shift = 0,
488         .divm_width = 8,
489         .divn_shift = 8,
490         .divn_width = 8,
491         .divp_shift = 16,
492         .divp_width = 4,
493 };
494 
495 static struct tegra_clk_pll_params pll_re_vco_params = {
496         .input_min = 12000000,
497         .input_max = 1000000000,
498         .cf_min = 12000000,
499         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
500         .vco_min = 300000000,
501         .vco_max = 600000000,
502         .base_reg = PLLRE_BASE,
503         .misc_reg = PLLRE_MISC,
504         .lock_mask = PLLRE_MISC_LOCK,
505         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
506         .lock_delay = 300,
507         .iddq_reg = PLLRE_MISC,
508         .iddq_bit_idx = PLLRE_IDDQ_BIT,
509         .div_nmp = &pllre_nmp,
510         .flags = TEGRA_PLL_USE_LOCK,
511 };
512 
513 static struct div_nmp pllp_nmp = {
514         .divm_shift = 0,
515         .divm_width = 5,
516         .divn_shift = 8,
517         .divn_width = 10,
518         .divp_shift = 20,
519         .divp_width = 3,
520 };
521 
522 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
523         {12000000, 408000000, 408, 12, 0, 8},
524         {13000000, 408000000, 408, 13, 0, 8},
525         {16800000, 408000000, 340, 14, 0, 8},
526         {19200000, 408000000, 340, 16, 0, 8},
527         {26000000, 408000000, 408, 26, 0, 8},
528         {0, 0, 0, 0, 0, 0},
529 };
530 
531 static struct tegra_clk_pll_params pll_p_params = {
532         .input_min = 2000000,
533         .input_max = 31000000,
534         .cf_min = 1000000,
535         .cf_max = 6000000,
536         .vco_min = 200000000,
537         .vco_max = 700000000,
538         .base_reg = PLLP_BASE,
539         .misc_reg = PLLP_MISC,
540         .lock_mask = PLL_BASE_LOCK,
541         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
542         .lock_delay = 300,
543         .div_nmp = &pllp_nmp,
544         .freq_table = pll_p_freq_table,
545         .fixed_rate = 408000000,
546         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
547 };
548 
549 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
550         {9600000, 282240000, 147, 5, 0, 4},
551         {9600000, 368640000, 192, 5, 0, 4},
552         {9600000, 240000000, 200, 8, 0, 8},
553 
554         {28800000, 282240000, 245, 25, 0, 8},
555         {28800000, 368640000, 320, 25, 0, 8},
556         {28800000, 240000000, 200, 24, 0, 8},
557         {0, 0, 0, 0, 0, 0},
558 };
559 
560 static struct tegra_clk_pll_params pll_a_params = {
561         .input_min = 2000000,
562         .input_max = 31000000,
563         .cf_min = 1000000,
564         .cf_max = 6000000,
565         .vco_min = 200000000,
566         .vco_max = 700000000,
567         .base_reg = PLLA_BASE,
568         .misc_reg = PLLA_MISC,
569         .lock_mask = PLL_BASE_LOCK,
570         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
571         .lock_delay = 300,
572         .div_nmp = &pllp_nmp,
573         .freq_table = pll_a_freq_table,
574         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
575 };
576 
577 static struct div_nmp plld_nmp = {
578         .divm_shift = 0,
579         .divm_width = 5,
580         .divn_shift = 8,
581         .divn_width = 11,
582         .divp_shift = 20,
583         .divp_width = 3,
584 };
585 
586 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
587         {12000000, 216000000, 864, 12, 4, 12},
588         {13000000, 216000000, 864, 13, 4, 12},
589         {16800000, 216000000, 720, 14, 4, 12},
590         {19200000, 216000000, 720, 16, 4, 12},
591         {26000000, 216000000, 864, 26, 4, 12},
592 
593         {12000000, 594000000, 594, 12, 1, 12},
594         {13000000, 594000000, 594, 13, 1, 12},
595         {16800000, 594000000, 495, 14, 1, 12},
596         {19200000, 594000000, 495, 16, 1, 12},
597         {26000000, 594000000, 594, 26, 1, 12},
598 
599         {12000000, 1000000000, 1000, 12, 1, 12},
600         {13000000, 1000000000, 1000, 13, 1, 12},
601         {19200000, 1000000000, 625, 12, 1, 12},
602         {26000000, 1000000000, 1000, 26, 1, 12},
603 
604         {0, 0, 0, 0, 0, 0},
605 };
606 
607 static struct tegra_clk_pll_params pll_d_params = {
608         .input_min = 2000000,
609         .input_max = 40000000,
610         .cf_min = 1000000,
611         .cf_max = 6000000,
612         .vco_min = 500000000,
613         .vco_max = 1000000000,
614         .base_reg = PLLD_BASE,
615         .misc_reg = PLLD_MISC,
616         .lock_mask = PLL_BASE_LOCK,
617         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
618         .lock_delay = 1000,
619         .div_nmp = &plld_nmp,
620         .freq_table = pll_d_freq_table,
621         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
622                  TEGRA_PLL_USE_LOCK,
623 };
624 
625 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
626         { 12000000, 594000000,  99, 1, 2},
627         { 13000000, 594000000,  91, 1, 2},      /* actual: 591.5 MHz */
628         { 16800000, 594000000,  71, 1, 2},      /* actual: 596.4 MHz */
629         { 19200000, 594000000,  62, 1, 2},      /* actual: 595.2 MHz */
630         { 26000000, 594000000,  91, 2, 2},      /* actual: 591.5 MHz */
631         { 0, 0, 0, 0, 0, 0 },
632 };
633 
634 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
635         .input_min = 12000000,
636         .input_max = 1000000000,
637         .cf_min = 12000000,
638         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
639         .vco_min = 600000000,
640         .vco_max = 1200000000,
641         .base_reg = PLLD2_BASE,
642         .misc_reg = PLLD2_MISC,
643         .lock_mask = PLL_BASE_LOCK,
644         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
645         .lock_delay = 300,
646         .iddq_reg = PLLD2_BASE,
647         .iddq_bit_idx = PLLSS_IDDQ_BIT,
648         .pdiv_tohw = pll12g_ssd_esd_p,
649         .div_nmp = &pllss_nmp,
650         .ext_misc_reg[0] = 0x570,
651         .ext_misc_reg[1] = 0x574,
652         .ext_misc_reg[2] = 0x578,
653         .max_p = 15,
654         .freq_table = tegra124_pll_d2_freq_table,
655 };
656 
657 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
658         { 12000000, 600000000, 100, 1, 1},
659         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
660         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
661         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
662         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
663         { 0, 0, 0, 0, 0, 0 },
664 };
665 
666 static struct tegra_clk_pll_params pll_dp_params = {
667         .input_min = 12000000,
668         .input_max = 1000000000,
669         .cf_min = 12000000,
670         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
671         .vco_min = 600000000,
672         .vco_max = 1200000000,
673         .base_reg = PLLDP_BASE,
674         .misc_reg = PLLDP_MISC,
675         .lock_mask = PLL_BASE_LOCK,
676         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
677         .lock_delay = 300,
678         .iddq_reg = PLLDP_BASE,
679         .iddq_bit_idx = PLLSS_IDDQ_BIT,
680         .pdiv_tohw = pll12g_ssd_esd_p,
681         .div_nmp = &pllss_nmp,
682         .ext_misc_reg[0] = 0x598,
683         .ext_misc_reg[1] = 0x59c,
684         .ext_misc_reg[2] = 0x5a0,
685         .max_p = 5,
686         .freq_table = pll_dp_freq_table,
687 };
688 
689 static struct pdiv_map pllu_p[] = {
690         { .pdiv = 1, .hw_val = 1 },
691         { .pdiv = 2, .hw_val = 0 },
692         { .pdiv = 0, .hw_val = 0 },
693 };
694 
695 static struct div_nmp pllu_nmp = {
696         .divm_shift = 0,
697         .divm_width = 5,
698         .divn_shift = 8,
699         .divn_width = 10,
700         .divp_shift = 20,
701         .divp_width = 1,
702 };
703 
704 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
705         {12000000, 480000000, 960, 12, 2, 12},
706         {13000000, 480000000, 960, 13, 2, 12},
707         {16800000, 480000000, 400, 7, 2, 5},
708         {19200000, 480000000, 200, 4, 2, 3},
709         {26000000, 480000000, 960, 26, 2, 12},
710         {0, 0, 0, 0, 0, 0},
711 };
712 
713 static struct tegra_clk_pll_params pll_u_params = {
714         .input_min = 2000000,
715         .input_max = 40000000,
716         .cf_min = 1000000,
717         .cf_max = 6000000,
718         .vco_min = 480000000,
719         .vco_max = 960000000,
720         .base_reg = PLLU_BASE,
721         .misc_reg = PLLU_MISC,
722         .lock_mask = PLL_BASE_LOCK,
723         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
724         .lock_delay = 1000,
725         .pdiv_tohw = pllu_p,
726         .div_nmp = &pllu_nmp,
727         .freq_table = pll_u_freq_table,
728         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
729                  TEGRA_PLL_USE_LOCK,
730 };
731 
732 struct utmi_clk_param {
733         /* Oscillator Frequency in KHz */
734         u32 osc_frequency;
735         /* UTMIP PLL Enable Delay Count  */
736         u8 enable_delay_count;
737         /* UTMIP PLL Stable count */
738         u8 stable_count;
739         /*  UTMIP PLL Active delay count */
740         u8 active_delay_count;
741         /* UTMIP PLL Xtal frequency count */
742         u8 xtal_freq_count;
743 };
744 
745 static const struct utmi_clk_param utmi_parameters[] = {
746         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
747          .stable_count = 0x33, .active_delay_count = 0x05,
748          .xtal_freq_count = 0x7F},
749         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
750          .stable_count = 0x4B, .active_delay_count = 0x06,
751          .xtal_freq_count = 0xBB},
752         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
753          .stable_count = 0x2F, .active_delay_count = 0x04,
754          .xtal_freq_count = 0x76},
755         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
756          .stable_count = 0x66, .active_delay_count = 0x09,
757          .xtal_freq_count = 0xFE},
758         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
759          .stable_count = 0x41, .active_delay_count = 0x0A,
760          .xtal_freq_count = 0xA4},
761 };
762 
763 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
764         [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
765         [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
766         [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
767         [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
768         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
769         [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
770         [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
771         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
772         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
773         [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
774         [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
775         [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
776         [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
777         [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
778         [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
779         [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
780         [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
781         [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
782         [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
783         [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
784         [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
785         [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
786         [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
787         [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
788         [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
789         [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
790         [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
791         [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
792         [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
793         [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
794         [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
795         [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
796         [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
797         [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
798         [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
799         [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
800         [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
801         [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
802         [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
803         [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
804         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
805         [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
806         [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
807         [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
808         [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
809         [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
810         [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
811         [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
812         [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
813         [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
814         [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
815         [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
816         [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
817         [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
818         [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
819         [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
820         [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
821         [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
822         [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
823         [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
824         [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
825         [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
826         [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
827         [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
828         [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
829         [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
830         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
831         [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
832         [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
833         [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
834         [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
835         [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
836         [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
837         [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
838         [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
839         [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
840         [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
841         [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
842         [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
843         [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
844         [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
845         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
846         [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
847         [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
848         [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
849         [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
850         [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
851         [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
852         [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
853         [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
854         [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
855         [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
856         [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
857         [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
858         [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
859         [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
860         [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
861         [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
862         [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
863         [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
864         [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
865         [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
866         [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
867         [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
868         [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
869         [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
870         [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
871         [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
872         [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
873         [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
874         [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
875         [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
876         [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
877         [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
878         [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
879         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
880         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
881         [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
882         [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
883         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
884         [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
885         [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
886         [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
887         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
888         [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
889         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
890         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
891         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
892         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
893         [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
894         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
895         [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
896         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
897         [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
898         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
899         [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
900         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
901         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
902         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
903         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
904         [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
905         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
906         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
907         [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
908         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
909         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
910         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
911         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
912         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
913         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
914         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
915         [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
916         [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
917         [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
918         [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
919         [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
920         [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
921         [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
922         [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
923         [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
924         [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
925         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
926         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
927         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
928         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
929         [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
930         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
931         [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
932         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
933         [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
934         [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
935         [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
936         [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
937         [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
938         [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
939         [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
940         [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
941         [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
942         [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
943         [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
944         [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
945         [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
946         [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
947         [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
948         [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
949         [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
950         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
951         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
952         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
953 };
954 
955 static struct tegra_devclk devclks[] __initdata = {
956         { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
957         { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
958         { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
959         { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
960         { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
961         { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
962         { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
963         { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
964         { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
965         { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
966         { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
967         { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
968         { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
969         { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
970         { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
971         { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
972         { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
973         { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
974         { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
975         { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
976         { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
977         { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
978         { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
979         { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
980         { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
981         { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
982         { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
983         { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
984         { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
985         { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
986         { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
987         { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
988         { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
989         { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
990         { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
991         { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
992         { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
993         { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
994         { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
995         { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
996         { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
997         { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
998         { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
999         { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
1000         { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
1001         { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
1002         { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
1003         { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
1004         { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
1005         { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
1006         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1007         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1008         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1009         { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1010         { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1011         { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1012         { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1013         { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1014         { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1015         { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1016         { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1017         { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1018         { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
1019         { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
1020         { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
1021 };
1022 
1023 static struct clk **clks;
1024 
1025 static void tegra124_utmi_param_configure(void __iomem *clk_base)
1026 {
1027         u32 reg;
1028         int i;
1029 
1030         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1031                 if (osc_freq == utmi_parameters[i].osc_frequency)
1032                         break;
1033         }
1034 
1035         if (i >= ARRAY_SIZE(utmi_parameters)) {
1036                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1037                        osc_freq);
1038                 return;
1039         }
1040 
1041         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1042 
1043         /* Program UTMIP PLL stable and active counts */
1044         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1045         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1046         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1047 
1048         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1049 
1050         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1051                                             active_delay_count);
1052 
1053         /* Remove power downs from UTMIP PLL control bits */
1054         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1055         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1056         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1057 
1058         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1059 
1060         /* Program UTMIP PLL delay and oscillator frequency counts */
1061         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1062         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1063 
1064         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1065                                             enable_delay_count);
1066 
1067         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1068         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1069                                            xtal_freq_count);
1070 
1071         /* Remove power downs from UTMIP PLL control bits */
1072         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1073         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1074         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1075         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1076         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1077 
1078         /* Setup HW control of UTMIPLL */
1079         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1080         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1081         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1082         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1083         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1084 
1085         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1086         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1087         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1088         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1089 
1090         udelay(1);
1091 
1092         /* Setup SW override of UTMIPLL assuming USB2.0
1093            ports are assigned to USB2 */
1094         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1095         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1096         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1097         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1098 
1099         udelay(1);
1100 
1101         /* Enable HW control UTMIPLL */
1102         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1103         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1104         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1105 }
1106 
1107 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1108                                             void __iomem *pmc_base)
1109 {
1110         struct clk *clk;
1111 
1112         /* xusb_ss_div2 */
1113         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1114                                         1, 2);
1115         clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1116 
1117         clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
1118                                 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1119         clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1120 
1121         clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
1122                                              clk_base, 0, 48,
1123                                              periph_clk_enb_refcnt);
1124         clks[TEGRA124_CLK_DSIA] = clk;
1125 
1126         clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
1127                                              clk_base, 0, 82,
1128                                              periph_clk_enb_refcnt);
1129         clks[TEGRA124_CLK_DSIB] = clk;
1130 
1131         clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1132                                     &emc_lock);
1133         clks[TEGRA124_CLK_MC] = clk;
1134 
1135         /* cml0 */
1136         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1137                                 0, 0, &pll_e_lock);
1138         clk_register_clkdev(clk, "cml0", NULL);
1139         clks[TEGRA124_CLK_CML0] = clk;
1140 
1141         /* cml1 */
1142         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1143                                 1, 0, &pll_e_lock);
1144         clk_register_clkdev(clk, "cml1", NULL);
1145         clks[TEGRA124_CLK_CML1] = clk;
1146 
1147         tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1148 }
1149 
1150 static void __init tegra124_pll_init(void __iomem *clk_base,
1151                                      void __iomem *pmc)
1152 {
1153         u32 val;
1154         struct clk *clk;
1155 
1156         /* PLLC */
1157         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1158                         pmc, 0, &pll_c_params, NULL);
1159         clk_register_clkdev(clk, "pll_c", NULL);
1160         clks[TEGRA124_CLK_PLL_C] = clk;
1161 
1162         /* PLLC_OUT1 */
1163         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1164                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1165                         8, 8, 1, NULL);
1166         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1167                                 clk_base + PLLC_OUT, 1, 0,
1168                                 CLK_SET_RATE_PARENT, 0, NULL);
1169         clk_register_clkdev(clk, "pll_c_out1", NULL);
1170         clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1171 
1172         /* PLLC_UD */
1173         clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
1174                                         CLK_SET_RATE_PARENT, 1, 1);
1175         clk_register_clkdev(clk, "pll_c_ud", NULL);
1176         clks[TEGRA124_CLK_PLL_C_UD] = clk;
1177 
1178         /* PLLC2 */
1179         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1180                              &pll_c2_params, NULL);
1181         clk_register_clkdev(clk, "pll_c2", NULL);
1182         clks[TEGRA124_CLK_PLL_C2] = clk;
1183 
1184         /* PLLC3 */
1185         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1186                              &pll_c3_params, NULL);
1187         clk_register_clkdev(clk, "pll_c3", NULL);
1188         clks[TEGRA124_CLK_PLL_C3] = clk;
1189 
1190         /* PLLM */
1191         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1192                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1193                              &pll_m_params, NULL);
1194         clk_register_clkdev(clk, "pll_m", NULL);
1195         clks[TEGRA124_CLK_PLL_M] = clk;
1196 
1197         /* PLLM_OUT1 */
1198         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1199                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1200                                 8, 8, 1, NULL);
1201         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1202                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1203                                 CLK_SET_RATE_PARENT, 0, NULL);
1204         clk_register_clkdev(clk, "pll_m_out1", NULL);
1205         clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1206 
1207         /* PLLM_UD */
1208         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1209                                         CLK_SET_RATE_PARENT, 1, 1);
1210         clk_register_clkdev(clk, "pll_m_ud", NULL);
1211         clks[TEGRA124_CLK_PLL_M_UD] = clk;
1212 
1213         /* PLLU */
1214         val = readl(clk_base + pll_u_params.base_reg);
1215         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1216         writel(val, clk_base + pll_u_params.base_reg);
1217 
1218         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1219                             &pll_u_params, &pll_u_lock);
1220         clk_register_clkdev(clk, "pll_u", NULL);
1221         clks[TEGRA124_CLK_PLL_U] = clk;
1222 
1223         tegra124_utmi_param_configure(clk_base);
1224 
1225         /* PLLU_480M */
1226         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1227                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1228                                 22, 0, &pll_u_lock);
1229         clk_register_clkdev(clk, "pll_u_480M", NULL);
1230         clks[TEGRA124_CLK_PLL_U_480M] = clk;
1231 
1232         /* PLLU_60M */
1233         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1234                                         CLK_SET_RATE_PARENT, 1, 8);
1235         clk_register_clkdev(clk, "pll_u_60M", NULL);
1236         clks[TEGRA124_CLK_PLL_U_60M] = clk;
1237 
1238         /* PLLU_48M */
1239         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1240                                         CLK_SET_RATE_PARENT, 1, 10);
1241         clk_register_clkdev(clk, "pll_u_48M", NULL);
1242         clks[TEGRA124_CLK_PLL_U_48M] = clk;
1243 
1244         /* PLLU_12M */
1245         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1246                                         CLK_SET_RATE_PARENT, 1, 40);
1247         clk_register_clkdev(clk, "pll_u_12M", NULL);
1248         clks[TEGRA124_CLK_PLL_U_12M] = clk;
1249 
1250         /* PLLD */
1251         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1252                             &pll_d_params, &pll_d_lock);
1253         clk_register_clkdev(clk, "pll_d", NULL);
1254         clks[TEGRA124_CLK_PLL_D] = clk;
1255 
1256         /* PLLD_OUT0 */
1257         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1258                                         CLK_SET_RATE_PARENT, 1, 2);
1259         clk_register_clkdev(clk, "pll_d_out0", NULL);
1260         clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1261 
1262         /* PLLRE */
1263         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1264                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1265         clk_register_clkdev(clk, "pll_re_vco", NULL);
1266         clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1267 
1268         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1269                                          clk_base + PLLRE_BASE, 16, 4, 0,
1270                                          pll_re_div_table, &pll_re_lock);
1271         clk_register_clkdev(clk, "pll_re_out", NULL);
1272         clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1273 
1274         /* PLLE */
1275         clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1276                                       clk_base, 0, &pll_e_params, NULL);
1277         clk_register_clkdev(clk, "pll_e", NULL);
1278         clks[TEGRA124_CLK_PLL_E] = clk;
1279 
1280         /* PLLC4 */
1281         clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1282                                         &pll_c4_params, NULL);
1283         clk_register_clkdev(clk, "pll_c4", NULL);
1284         clks[TEGRA124_CLK_PLL_C4] = clk;
1285 
1286         /* PLLDP */
1287         clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1288                                         &pll_dp_params, NULL);
1289         clk_register_clkdev(clk, "pll_dp", NULL);
1290         clks[TEGRA124_CLK_PLL_DP] = clk;
1291 
1292         /* PLLD2 */
1293         clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1294                                         &tegra124_pll_d2_params, NULL);
1295         clk_register_clkdev(clk, "pll_d2", NULL);
1296         clks[TEGRA124_CLK_PLL_D2] = clk;
1297 
1298         /* PLLD2_OUT0 */
1299         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1300                                         CLK_SET_RATE_PARENT, 1, 1);
1301         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1302         clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1303 
1304 }
1305 
1306 /* Tegra124 CPU clock and reset control functions */
1307 static void tegra124_wait_cpu_in_reset(u32 cpu)
1308 {
1309         unsigned int reg;
1310 
1311         do {
1312                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1313                 cpu_relax();
1314         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1315 }
1316 
1317 static void tegra124_disable_cpu_clock(u32 cpu)
1318 {
1319         /* flow controller would take care in the power sequence. */
1320 }
1321 
1322 #ifdef CONFIG_PM_SLEEP
1323 static void tegra124_cpu_clock_suspend(void)
1324 {
1325         /* switch coresite to clk_m, save off original source */
1326         tegra124_cpu_clk_sctx.clk_csite_src =
1327                                 readl(clk_base + CLK_SOURCE_CSITE);
1328         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1329 
1330         tegra124_cpu_clk_sctx.cclkg_burst =
1331                                 readl(clk_base + CCLKG_BURST_POLICY);
1332         tegra124_cpu_clk_sctx.cclkg_divider =
1333                                 readl(clk_base + CCLKG_BURST_POLICY + 4);
1334 }
1335 
1336 static void tegra124_cpu_clock_resume(void)
1337 {
1338         writel(tegra124_cpu_clk_sctx.clk_csite_src,
1339                                 clk_base + CLK_SOURCE_CSITE);
1340 
1341         writel(tegra124_cpu_clk_sctx.cclkg_burst,
1342                                         clk_base + CCLKG_BURST_POLICY);
1343         writel(tegra124_cpu_clk_sctx.cclkg_divider,
1344                                         clk_base + CCLKG_BURST_POLICY + 4);
1345 }
1346 #endif
1347 
1348 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1349         .wait_for_reset = tegra124_wait_cpu_in_reset,
1350         .disable_clock  = tegra124_disable_cpu_clock,
1351 #ifdef CONFIG_PM_SLEEP
1352         .suspend        = tegra124_cpu_clock_suspend,
1353         .resume         = tegra124_cpu_clock_resume,
1354 #endif
1355 };
1356 
1357 static const struct of_device_id pmc_match[] __initconst = {
1358         { .compatible = "nvidia,tegra124-pmc" },
1359         {},
1360 };
1361 
1362 static struct tegra_clk_init_table common_init_table[] __initdata = {
1363         {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1364         {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1365         {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1366         {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1367         {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1368         {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1369         {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
1370         {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
1371         {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1372         {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1373         {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1374         {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1375         {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1376         {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1377         {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1378         {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1379         {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
1380         {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
1381         {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1382         {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1383         {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1384         {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1385         {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1386         {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1387         {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1388         {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1389         {TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
1390         {TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0},
1391         {TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0},
1392         {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
1393         {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
1394         {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
1395         {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1396         {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1397         {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1398         {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1399         {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
1400         /* This MUST be the last entry. */
1401         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1402 };
1403 
1404 static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1405         {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1406         {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1407         {TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
1408         {TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
1409         /* This MUST be the last entry. */
1410         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1411 };
1412 
1413 /* Tegra132 requires the SOC_THERM clock to remain active */
1414 static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1415         {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
1416         /* This MUST be the last entry. */
1417         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1418 };
1419 
1420 static struct tegra_audio_clk_info tegra124_audio_plls[] = {
1421         { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1422 };
1423 
1424 /**
1425  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1426  *
1427  * Program an initial clock rate and enable or disable clocks needed
1428  * by the rest of the kernel, for Tegra124 SoCs.  It is intended to be
1429  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1430  * this will be called as an arch_initcall.  No return value.
1431  */
1432 static void __init tegra124_clock_apply_init_table(void)
1433 {
1434         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1435         tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1436 }
1437 
1438 /**
1439  * tegra124_car_barrier - wait for pending writes to the CAR to complete
1440  *
1441  * Wait for any outstanding writes to the CAR MMIO space from this CPU
1442  * to complete before continuing execution.  No return value.
1443  */
1444 static void tegra124_car_barrier(void)
1445 {
1446         readl_relaxed(clk_base + RST_DFLL_DVCO);
1447 }
1448 
1449 /**
1450  * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1451  *
1452  * Assert the reset line of the DFLL's DVCO.  No return value.
1453  */
1454 static void tegra124_clock_assert_dfll_dvco_reset(void)
1455 {
1456         u32 v;
1457 
1458         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1459         v |= (1 << DVFS_DFLL_RESET_SHIFT);
1460         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1461         tegra124_car_barrier();
1462 }
1463 
1464 /**
1465  * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1466  *
1467  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1468  * operate.  No return value.
1469  */
1470 static void tegra124_clock_deassert_dfll_dvco_reset(void)
1471 {
1472         u32 v;
1473 
1474         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1475         v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1476         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1477         tegra124_car_barrier();
1478 }
1479 
1480 static int tegra124_reset_assert(unsigned long id)
1481 {
1482         if (id == TEGRA124_RST_DFLL_DVCO)
1483                 tegra124_clock_assert_dfll_dvco_reset();
1484         else
1485                 return -EINVAL;
1486 
1487         return 0;
1488 }
1489 
1490 static int tegra124_reset_deassert(unsigned long id)
1491 {
1492         if (id == TEGRA124_RST_DFLL_DVCO)
1493                 tegra124_clock_deassert_dfll_dvco_reset();
1494         else
1495                 return -EINVAL;
1496 
1497         return 0;
1498 }
1499 
1500 /**
1501  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1502  *
1503  * Program an initial clock rate and enable or disable clocks needed
1504  * by the rest of the kernel, for Tegra132 SoCs.  It is intended to be
1505  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1506  * this will be called as an arch_initcall.  No return value.
1507  */
1508 static void __init tegra132_clock_apply_init_table(void)
1509 {
1510         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1511         tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1512 }
1513 
1514 /**
1515  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1516  * @np: struct device_node * of the DT node for the SoC CAR IP block
1517  *
1518  * Register most of the clocks controlled by the CAR IP block, along
1519  * with a few clocks controlled by the PMC IP block.  Everything in
1520  * this function should be common to Tegra124 and Tegra132.  XXX The
1521  * PMC clock initialization should probably be moved to PMC-specific
1522  * driver code.  No return value.
1523  */
1524 static void __init tegra124_132_clock_init_pre(struct device_node *np)
1525 {
1526         struct device_node *node;
1527         u32 plld_base;
1528 
1529         clk_base = of_iomap(np, 0);
1530         if (!clk_base) {
1531                 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1532                 return;
1533         }
1534 
1535         node = of_find_matching_node(NULL, pmc_match);
1536         if (!node) {
1537                 pr_err("Failed to find pmc node\n");
1538                 WARN_ON(1);
1539                 return;
1540         }
1541 
1542         pmc_base = of_iomap(node, 0);
1543         if (!pmc_base) {
1544                 pr_err("Can't map pmc registers\n");
1545                 WARN_ON(1);
1546                 return;
1547         }
1548 
1549         clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1550                               TEGRA124_CAR_BANK_COUNT);
1551         if (!clks)
1552                 return;
1553 
1554         if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1555                                ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
1556                                &pll_ref_freq) < 0)
1557                 return;
1558 
1559         tegra_fixed_clk_init(tegra124_clks);
1560         tegra124_pll_init(clk_base, pmc_base);
1561         tegra124_periph_clk_init(clk_base, pmc_base);
1562         tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
1563                              tegra124_audio_plls,
1564                              ARRAY_SIZE(tegra124_audio_plls));
1565         tegra_pmc_clk_init(pmc_base, tegra124_clks);
1566 
1567         /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1568         plld_base = clk_readl(clk_base + PLLD_BASE);
1569         plld_base &= ~BIT(25);
1570         clk_writel(plld_base, clk_base + PLLD_BASE);
1571 }
1572 
1573 /**
1574  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1575  * @np: struct device_node * of the DT node for the SoC CAR IP block
1576  *
1577  * Register most of the along with a few clocks controlled by the PMC
1578  * IP block.  Everything in this function should be common to Tegra124
1579  * and Tegra132.  This function must be called after
1580  * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1581  * not be set.  No return value.
1582  */
1583 static void __init tegra124_132_clock_init_post(struct device_node *np)
1584 {
1585         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1586                                   &pll_x_params);
1587         tegra_init_special_resets(1, tegra124_reset_assert,
1588                                   tegra124_reset_deassert);
1589         tegra_add_of_provider(np);
1590 
1591         clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
1592                                                         &emc_lock);
1593 
1594         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1595 
1596         tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1597 }
1598 
1599 /**
1600  * tegra124_clock_init - Tegra124-specific clock initialization
1601  * @np: struct device_node * of the DT node for the SoC CAR IP block
1602  *
1603  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1604  * this code is shared between the Tegra124 and Tegra132 SoCs,
1605  * although some of the initial clock settings and CPU clocks differ.
1606  * Intended to be called by the OF init code when a DT node with the
1607  * "nvidia,tegra124-car" string is encountered, and declared with
1608  * CLK_OF_DECLARE.  No return value.
1609  */
1610 static void __init tegra124_clock_init(struct device_node *np)
1611 {
1612         tegra124_132_clock_init_pre(np);
1613         tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1614         tegra124_132_clock_init_post(np);
1615 }
1616 
1617 /**
1618  * tegra132_clock_init - Tegra132-specific clock initialization
1619  * @np: struct device_node * of the DT node for the SoC CAR IP block
1620  *
1621  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1622  * this code is shared between the Tegra124 and Tegra132 SoCs,
1623  * although some of the initial clock settings and CPU clocks differ.
1624  * Intended to be called by the OF init code when a DT node with the
1625  * "nvidia,tegra132-car" string is encountered, and declared with
1626  * CLK_OF_DECLARE.  No return value.
1627  */
1628 static void __init tegra132_clock_init(struct device_node *np)
1629 {
1630         tegra124_132_clock_init_pre(np);
1631 
1632         /*
1633          * On Tegra132, these clocks are controlled by the
1634          * CLUSTER_clocks IP block, located in the CPU complex
1635          */
1636         tegra124_clks[tegra_clk_cclk_g].present = false;
1637         tegra124_clks[tegra_clk_cclk_lp].present = false;
1638         tegra124_clks[tegra_clk_pll_x].present = false;
1639         tegra124_clks[tegra_clk_pll_x_out0].present = false;
1640 
1641         tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1642         tegra124_132_clock_init_post(np);
1643 }
1644 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1645 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
1646 

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