Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/clk/tegra/clk-tegra124.c

  1 /*
  2  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk-provider.h>
 19 #include <linux/clkdev.h>
 20 #include <linux/of.h>
 21 #include <linux/of_address.h>
 22 #include <linux/delay.h>
 23 #include <linux/export.h>
 24 #include <linux/clk/tegra.h>
 25 #include <dt-bindings/clock/tegra124-car.h>
 26 #include <dt-bindings/reset/tegra124-car.h>
 27 
 28 #include "clk.h"
 29 #include "clk-id.h"
 30 
 31 /*
 32  * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
 33  * banks present in the Tegra124/132 CAR IP block.  The banks are
 34  * identified by single letters, e.g.: L, H, U, V, W, X.  See
 35  * periph_regs[] in drivers/clk/tegra/clk.c
 36  */
 37 #define TEGRA124_CAR_BANK_COUNT                 6
 38 
 39 #define CLK_SOURCE_CSITE 0x1d4
 40 #define CLK_SOURCE_EMC 0x19c
 41 
 42 #define RST_DFLL_DVCO                   0x2f4
 43 #define DVFS_DFLL_RESET_SHIFT           0
 44 
 45 #define PLLC_BASE 0x80
 46 #define PLLC_OUT 0x84
 47 #define PLLC_MISC2 0x88
 48 #define PLLC_MISC 0x8c
 49 #define PLLC2_BASE 0x4e8
 50 #define PLLC2_MISC 0x4ec
 51 #define PLLC3_BASE 0x4fc
 52 #define PLLC3_MISC 0x500
 53 #define PLLM_BASE 0x90
 54 #define PLLM_OUT 0x94
 55 #define PLLM_MISC 0x9c
 56 #define PLLP_BASE 0xa0
 57 #define PLLP_MISC 0xac
 58 #define PLLA_BASE 0xb0
 59 #define PLLA_MISC 0xbc
 60 #define PLLD_BASE 0xd0
 61 #define PLLD_MISC 0xdc
 62 #define PLLU_BASE 0xc0
 63 #define PLLU_MISC 0xcc
 64 #define PLLX_BASE 0xe0
 65 #define PLLX_MISC 0xe4
 66 #define PLLX_MISC2 0x514
 67 #define PLLX_MISC3 0x518
 68 #define PLLE_BASE 0xe8
 69 #define PLLE_MISC 0xec
 70 #define PLLD2_BASE 0x4b8
 71 #define PLLD2_MISC 0x4bc
 72 #define PLLE_AUX 0x48c
 73 #define PLLRE_BASE 0x4c4
 74 #define PLLRE_MISC 0x4c8
 75 #define PLLDP_BASE 0x590
 76 #define PLLDP_MISC 0x594
 77 #define PLLC4_BASE 0x5a4
 78 #define PLLC4_MISC 0x5a8
 79 
 80 #define PLLC_IDDQ_BIT 26
 81 #define PLLRE_IDDQ_BIT 16
 82 #define PLLSS_IDDQ_BIT 19
 83 
 84 #define PLL_BASE_LOCK BIT(27)
 85 #define PLLE_MISC_LOCK BIT(11)
 86 #define PLLRE_MISC_LOCK BIT(24)
 87 
 88 #define PLL_MISC_LOCK_ENABLE 18
 89 #define PLLC_MISC_LOCK_ENABLE 24
 90 #define PLLDU_MISC_LOCK_ENABLE 22
 91 #define PLLE_MISC_LOCK_ENABLE 9
 92 #define PLLRE_MISC_LOCK_ENABLE 30
 93 #define PLLSS_MISC_LOCK_ENABLE 30
 94 
 95 #define PLLXC_SW_MAX_P 6
 96 
 97 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 98 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 99 
100 #define CCLKG_BURST_POLICY 0x368
101 
102 /* Tegra CPU clock and reset control regs */
103 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
104 
105 #ifdef CONFIG_PM_SLEEP
106 static struct cpu_clk_suspend_context {
107         u32 clk_csite_src;
108         u32 cclkg_burst;
109         u32 cclkg_divider;
110 } tegra124_cpu_clk_sctx;
111 #endif
112 
113 static void __iomem *clk_base;
114 static void __iomem *pmc_base;
115 
116 static unsigned long osc_freq;
117 static unsigned long pll_ref_freq;
118 
119 static DEFINE_SPINLOCK(pll_d_lock);
120 static DEFINE_SPINLOCK(pll_e_lock);
121 static DEFINE_SPINLOCK(pll_re_lock);
122 static DEFINE_SPINLOCK(pll_u_lock);
123 static DEFINE_SPINLOCK(emc_lock);
124 
125 /* possible OSC frequencies in Hz */
126 static unsigned long tegra124_input_freq[] = {
127         [ 0] = 13000000,
128         [ 1] = 16800000,
129         [ 4] = 19200000,
130         [ 5] = 38400000,
131         [ 8] = 12000000,
132         [ 9] = 48000000,
133         [12] = 26000000,
134 };
135 
136 static struct div_nmp pllxc_nmp = {
137         .divm_shift = 0,
138         .divm_width = 8,
139         .divn_shift = 8,
140         .divn_width = 8,
141         .divp_shift = 20,
142         .divp_width = 4,
143 };
144 
145 static const struct pdiv_map pllxc_p[] = {
146         { .pdiv =  1, .hw_val =  0 },
147         { .pdiv =  2, .hw_val =  1 },
148         { .pdiv =  3, .hw_val =  2 },
149         { .pdiv =  4, .hw_val =  3 },
150         { .pdiv =  5, .hw_val =  4 },
151         { .pdiv =  6, .hw_val =  5 },
152         { .pdiv =  8, .hw_val =  6 },
153         { .pdiv = 10, .hw_val =  7 },
154         { .pdiv = 12, .hw_val =  8 },
155         { .pdiv = 16, .hw_val =  9 },
156         { .pdiv = 12, .hw_val = 10 },
157         { .pdiv = 16, .hw_val = 11 },
158         { .pdiv = 20, .hw_val = 12 },
159         { .pdiv = 24, .hw_val = 13 },
160         { .pdiv = 32, .hw_val = 14 },
161         { .pdiv =  0, .hw_val =  0 },
162 };
163 
164 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
165         /* 1 GHz */
166         { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
167         { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
168         { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
169         { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
170         { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
171         {        0,          0,  0, 0, 0, 0 },
172 };
173 
174 static struct tegra_clk_pll_params pll_x_params = {
175         .input_min = 12000000,
176         .input_max = 800000000,
177         .cf_min = 12000000,
178         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
179         .vco_min = 700000000,
180         .vco_max = 3000000000UL,
181         .base_reg = PLLX_BASE,
182         .misc_reg = PLLX_MISC,
183         .lock_mask = PLL_BASE_LOCK,
184         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
185         .lock_delay = 300,
186         .iddq_reg = PLLX_MISC3,
187         .iddq_bit_idx = 3,
188         .max_p = 6,
189         .dyn_ramp_reg = PLLX_MISC2,
190         .stepa_shift = 16,
191         .stepb_shift = 24,
192         .pdiv_tohw = pllxc_p,
193         .div_nmp = &pllxc_nmp,
194         .freq_table = pll_x_freq_table,
195         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
196 };
197 
198 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
199         { 12000000, 624000000, 104, 1, 2, 0 },
200         { 12000000, 600000000, 100, 1, 2, 0 },
201         { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
202         { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
203         { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
204         { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
205         {        0,         0,   0, 0, 0, 0 },
206 };
207 
208 static struct tegra_clk_pll_params pll_c_params = {
209         .input_min = 12000000,
210         .input_max = 800000000,
211         .cf_min = 12000000,
212         .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
213         .vco_min = 600000000,
214         .vco_max = 1400000000,
215         .base_reg = PLLC_BASE,
216         .misc_reg = PLLC_MISC,
217         .lock_mask = PLL_BASE_LOCK,
218         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
219         .lock_delay = 300,
220         .iddq_reg = PLLC_MISC,
221         .iddq_bit_idx = PLLC_IDDQ_BIT,
222         .max_p = PLLXC_SW_MAX_P,
223         .dyn_ramp_reg = PLLC_MISC2,
224         .stepa_shift = 17,
225         .stepb_shift = 9,
226         .pdiv_tohw = pllxc_p,
227         .div_nmp = &pllxc_nmp,
228         .freq_table = pll_c_freq_table,
229         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
230 };
231 
232 static struct div_nmp pllcx_nmp = {
233         .divm_shift = 0,
234         .divm_width = 2,
235         .divn_shift = 8,
236         .divn_width = 8,
237         .divp_shift = 20,
238         .divp_width = 3,
239 };
240 
241 static const struct pdiv_map pllc_p[] = {
242         { .pdiv =  1, .hw_val = 0 },
243         { .pdiv =  2, .hw_val = 1 },
244         { .pdiv =  3, .hw_val = 2 },
245         { .pdiv =  4, .hw_val = 3 },
246         { .pdiv =  6, .hw_val = 4 },
247         { .pdiv =  8, .hw_val = 5 },
248         { .pdiv = 12, .hw_val = 6 },
249         { .pdiv = 16, .hw_val = 7 },
250         { .pdiv =  0, .hw_val = 0 },
251 };
252 
253 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
254         { 12000000, 600000000, 100, 1, 2, 0 },
255         { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
256         { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
257         { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
258         { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
259         {        0,         0,   0, 0, 0, 0 },
260 };
261 
262 static struct tegra_clk_pll_params pll_c2_params = {
263         .input_min = 12000000,
264         .input_max = 48000000,
265         .cf_min = 12000000,
266         .cf_max = 19200000,
267         .vco_min = 600000000,
268         .vco_max = 1200000000,
269         .base_reg = PLLC2_BASE,
270         .misc_reg = PLLC2_MISC,
271         .lock_mask = PLL_BASE_LOCK,
272         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
273         .lock_delay = 300,
274         .pdiv_tohw = pllc_p,
275         .div_nmp = &pllcx_nmp,
276         .max_p = 7,
277         .ext_misc_reg[0] = 0x4f0,
278         .ext_misc_reg[1] = 0x4f4,
279         .ext_misc_reg[2] = 0x4f8,
280         .freq_table = pll_cx_freq_table,
281         .flags = TEGRA_PLL_USE_LOCK,
282 };
283 
284 static struct tegra_clk_pll_params pll_c3_params = {
285         .input_min = 12000000,
286         .input_max = 48000000,
287         .cf_min = 12000000,
288         .cf_max = 19200000,
289         .vco_min = 600000000,
290         .vco_max = 1200000000,
291         .base_reg = PLLC3_BASE,
292         .misc_reg = PLLC3_MISC,
293         .lock_mask = PLL_BASE_LOCK,
294         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
295         .lock_delay = 300,
296         .pdiv_tohw = pllc_p,
297         .div_nmp = &pllcx_nmp,
298         .max_p = 7,
299         .ext_misc_reg[0] = 0x504,
300         .ext_misc_reg[1] = 0x508,
301         .ext_misc_reg[2] = 0x50c,
302         .freq_table = pll_cx_freq_table,
303         .flags = TEGRA_PLL_USE_LOCK,
304 };
305 
306 static struct div_nmp pllss_nmp = {
307         .divm_shift = 0,
308         .divm_width = 8,
309         .divn_shift = 8,
310         .divn_width = 8,
311         .divp_shift = 20,
312         .divp_width = 4,
313 };
314 
315 static const struct pdiv_map pll12g_ssd_esd_p[] = {
316         { .pdiv =  1, .hw_val =  0 },
317         { .pdiv =  2, .hw_val =  1 },
318         { .pdiv =  3, .hw_val =  2 },
319         { .pdiv =  4, .hw_val =  3 },
320         { .pdiv =  5, .hw_val =  4 },
321         { .pdiv =  6, .hw_val =  5 },
322         { .pdiv =  8, .hw_val =  6 },
323         { .pdiv = 10, .hw_val =  7 },
324         { .pdiv = 12, .hw_val =  8 },
325         { .pdiv = 16, .hw_val =  9 },
326         { .pdiv = 12, .hw_val = 10 },
327         { .pdiv = 16, .hw_val = 11 },
328         { .pdiv = 20, .hw_val = 12 },
329         { .pdiv = 24, .hw_val = 13 },
330         { .pdiv = 32, .hw_val = 14 },
331         { .pdiv =  0, .hw_val =  0 },
332 };
333 
334 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
335         { 12000000, 600000000, 100, 1, 2, 0 },
336         { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
337         { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
338         { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
339         { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
340         {        0,         0,   0, 0, 0, 0 },
341 };
342 
343 static struct tegra_clk_pll_params pll_c4_params = {
344         .input_min = 12000000,
345         .input_max = 1000000000,
346         .cf_min = 12000000,
347         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
348         .vco_min = 600000000,
349         .vco_max = 1200000000,
350         .base_reg = PLLC4_BASE,
351         .misc_reg = PLLC4_MISC,
352         .lock_mask = PLL_BASE_LOCK,
353         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
354         .lock_delay = 300,
355         .iddq_reg = PLLC4_BASE,
356         .iddq_bit_idx = PLLSS_IDDQ_BIT,
357         .pdiv_tohw = pll12g_ssd_esd_p,
358         .div_nmp = &pllss_nmp,
359         .ext_misc_reg[0] = 0x5ac,
360         .ext_misc_reg[1] = 0x5b0,
361         .ext_misc_reg[2] = 0x5b4,
362         .freq_table = pll_c4_freq_table,
363         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
364 };
365 
366 static const struct pdiv_map pllm_p[] = {
367         { .pdiv =  1, .hw_val =  0 },
368         { .pdiv =  2, .hw_val =  1 },
369         { .pdiv =  3, .hw_val =  2 },
370         { .pdiv =  4, .hw_val =  3 },
371         { .pdiv =  5, .hw_val =  4 },
372         { .pdiv =  6, .hw_val =  5 },
373         { .pdiv =  8, .hw_val =  6 },
374         { .pdiv = 10, .hw_val =  7 },
375         { .pdiv = 12, .hw_val =  8 },
376         { .pdiv = 16, .hw_val =  9 },
377         { .pdiv = 12, .hw_val = 10 },
378         { .pdiv = 16, .hw_val = 11 },
379         { .pdiv = 20, .hw_val = 12 },
380         { .pdiv = 24, .hw_val = 13 },
381         { .pdiv = 32, .hw_val = 14 },
382         { .pdiv =  0, .hw_val =  0 },
383 };
384 
385 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
386         { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
387         { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
388         { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
389         { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
390         { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
391         {        0,         0,  0, 0, 0, 0},
392 };
393 
394 static struct div_nmp pllm_nmp = {
395         .divm_shift = 0,
396         .divm_width = 8,
397         .override_divm_shift = 0,
398         .divn_shift = 8,
399         .divn_width = 8,
400         .override_divn_shift = 8,
401         .divp_shift = 20,
402         .divp_width = 1,
403         .override_divp_shift = 27,
404 };
405 
406 static struct tegra_clk_pll_params pll_m_params = {
407         .input_min = 12000000,
408         .input_max = 500000000,
409         .cf_min = 12000000,
410         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
411         .vco_min = 400000000,
412         .vco_max = 1066000000,
413         .base_reg = PLLM_BASE,
414         .misc_reg = PLLM_MISC,
415         .lock_mask = PLL_BASE_LOCK,
416         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
417         .lock_delay = 300,
418         .max_p = 5,
419         .pdiv_tohw = pllm_p,
420         .div_nmp = &pllm_nmp,
421         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
422         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
423         .freq_table = pll_m_freq_table,
424         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
425 };
426 
427 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
428         /* PLLE special case: use cpcon field to store cml divider value */
429         { 336000000, 100000000, 100, 21, 16, 11 },
430         { 312000000, 100000000, 200, 26, 24, 13 },
431         {  13000000, 100000000, 200,  1, 26, 13 },
432         {  12000000, 100000000, 200,  1, 24, 13 },
433         {         0,         0,   0,  0,  0,  0 },
434 };
435 
436 static const struct pdiv_map plle_p[] = {
437         { .pdiv =  1, .hw_val =  0 },
438         { .pdiv =  2, .hw_val =  1 },
439         { .pdiv =  3, .hw_val =  2 },
440         { .pdiv =  4, .hw_val =  3 },
441         { .pdiv =  5, .hw_val =  4 },
442         { .pdiv =  6, .hw_val =  5 },
443         { .pdiv =  8, .hw_val =  6 },
444         { .pdiv = 10, .hw_val =  7 },
445         { .pdiv = 12, .hw_val =  8 },
446         { .pdiv = 16, .hw_val =  9 },
447         { .pdiv = 12, .hw_val = 10 },
448         { .pdiv = 16, .hw_val = 11 },
449         { .pdiv = 20, .hw_val = 12 },
450         { .pdiv = 24, .hw_val = 13 },
451         { .pdiv = 32, .hw_val = 14 },
452         { .pdiv =  1, .hw_val =  0 },
453 };
454 
455 static struct div_nmp plle_nmp = {
456         .divm_shift = 0,
457         .divm_width = 8,
458         .divn_shift = 8,
459         .divn_width = 8,
460         .divp_shift = 24,
461         .divp_width = 4,
462 };
463 
464 static struct tegra_clk_pll_params pll_e_params = {
465         .input_min = 12000000,
466         .input_max = 1000000000,
467         .cf_min = 12000000,
468         .cf_max = 75000000,
469         .vco_min = 1600000000,
470         .vco_max = 2400000000U,
471         .base_reg = PLLE_BASE,
472         .misc_reg = PLLE_MISC,
473         .aux_reg = PLLE_AUX,
474         .lock_mask = PLLE_MISC_LOCK,
475         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
476         .lock_delay = 300,
477         .pdiv_tohw = plle_p,
478         .div_nmp = &plle_nmp,
479         .freq_table = pll_e_freq_table,
480         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
481         .fixed_rate = 100000000,
482 };
483 
484 static const struct clk_div_table pll_re_div_table[] = {
485         { .val = 0, .div = 1 },
486         { .val = 1, .div = 2 },
487         { .val = 2, .div = 3 },
488         { .val = 3, .div = 4 },
489         { .val = 4, .div = 5 },
490         { .val = 5, .div = 6 },
491         { .val = 0, .div = 0 },
492 };
493 
494 static struct div_nmp pllre_nmp = {
495         .divm_shift = 0,
496         .divm_width = 8,
497         .divn_shift = 8,
498         .divn_width = 8,
499         .divp_shift = 16,
500         .divp_width = 4,
501 };
502 
503 static struct tegra_clk_pll_params pll_re_vco_params = {
504         .input_min = 12000000,
505         .input_max = 1000000000,
506         .cf_min = 12000000,
507         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
508         .vco_min = 300000000,
509         .vco_max = 600000000,
510         .base_reg = PLLRE_BASE,
511         .misc_reg = PLLRE_MISC,
512         .lock_mask = PLLRE_MISC_LOCK,
513         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
514         .lock_delay = 300,
515         .iddq_reg = PLLRE_MISC,
516         .iddq_bit_idx = PLLRE_IDDQ_BIT,
517         .div_nmp = &pllre_nmp,
518         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
519                  TEGRA_PLL_LOCK_MISC,
520 };
521 
522 static struct div_nmp pllp_nmp = {
523         .divm_shift = 0,
524         .divm_width = 5,
525         .divn_shift = 8,
526         .divn_width = 10,
527         .divp_shift = 20,
528         .divp_width = 3,
529 };
530 
531 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
532         { 12000000, 408000000, 408, 12, 1, 8 },
533         { 13000000, 408000000, 408, 13, 1, 8 },
534         { 16800000, 408000000, 340, 14, 1, 8 },
535         { 19200000, 408000000, 340, 16, 1, 8 },
536         { 26000000, 408000000, 408, 26, 1, 8 },
537         {        0,         0,   0,  0, 0, 0 },
538 };
539 
540 static struct tegra_clk_pll_params pll_p_params = {
541         .input_min = 2000000,
542         .input_max = 31000000,
543         .cf_min = 1000000,
544         .cf_max = 6000000,
545         .vco_min = 200000000,
546         .vco_max = 700000000,
547         .base_reg = PLLP_BASE,
548         .misc_reg = PLLP_MISC,
549         .lock_mask = PLL_BASE_LOCK,
550         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
551         .lock_delay = 300,
552         .div_nmp = &pllp_nmp,
553         .freq_table = pll_p_freq_table,
554         .fixed_rate = 408000000,
555         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
556                  TEGRA_PLL_HAS_LOCK_ENABLE,
557 };
558 
559 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
560         {  9600000, 282240000, 147,  5, 1, 4 },
561         {  9600000, 368640000, 192,  5, 1, 4 },
562         {  9600000, 240000000, 200,  8, 1, 8 },
563         { 28800000, 282240000, 245, 25, 1, 8 },
564         { 28800000, 368640000, 320, 25, 1, 8 },
565         { 28800000, 240000000, 200, 24, 1, 8 },
566         {        0,         0,   0,  0, 0, 0 },
567 };
568 
569 static struct tegra_clk_pll_params pll_a_params = {
570         .input_min = 2000000,
571         .input_max = 31000000,
572         .cf_min = 1000000,
573         .cf_max = 6000000,
574         .vco_min = 200000000,
575         .vco_max = 700000000,
576         .base_reg = PLLA_BASE,
577         .misc_reg = PLLA_MISC,
578         .lock_mask = PLL_BASE_LOCK,
579         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
580         .lock_delay = 300,
581         .div_nmp = &pllp_nmp,
582         .freq_table = pll_a_freq_table,
583         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
584                  TEGRA_PLL_HAS_LOCK_ENABLE,
585 };
586 
587 static struct div_nmp plld_nmp = {
588         .divm_shift = 0,
589         .divm_width = 5,
590         .divn_shift = 8,
591         .divn_width = 11,
592         .divp_shift = 20,
593         .divp_width = 3,
594 };
595 
596 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
597         { 12000000,  216000000,  864, 12, 4, 12 },
598         { 13000000,  216000000,  864, 13, 4, 12 },
599         { 16800000,  216000000,  720, 14, 4, 12 },
600         { 19200000,  216000000,  720, 16, 4, 12 },
601         { 26000000,  216000000,  864, 26, 4, 12 },
602         { 12000000,  594000000,  594, 12, 1, 12 },
603         { 13000000,  594000000,  594, 13, 1, 12 },
604         { 16800000,  594000000,  495, 14, 1, 12 },
605         { 19200000,  594000000,  495, 16, 1, 12 },
606         { 26000000,  594000000,  594, 26, 1, 12 },
607         { 12000000, 1000000000, 1000, 12, 1, 12 },
608         { 13000000, 1000000000, 1000, 13, 1, 12 },
609         { 19200000, 1000000000,  625, 12, 1, 12 },
610         { 26000000, 1000000000, 1000, 26, 1, 12 },
611         {        0,          0,    0,  0, 0,  0 },
612 };
613 
614 static struct tegra_clk_pll_params pll_d_params = {
615         .input_min = 2000000,
616         .input_max = 40000000,
617         .cf_min = 1000000,
618         .cf_max = 6000000,
619         .vco_min = 500000000,
620         .vco_max = 1000000000,
621         .base_reg = PLLD_BASE,
622         .misc_reg = PLLD_MISC,
623         .lock_mask = PLL_BASE_LOCK,
624         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
625         .lock_delay = 1000,
626         .div_nmp = &plld_nmp,
627         .freq_table = pll_d_freq_table,
628         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
629                  TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
630 };
631 
632 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
633         { 12000000, 594000000, 99, 1, 2, 0 },
634         { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
635         { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
636         { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
637         { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
638         {        0,         0,  0, 0, 0, 0 },
639 };
640 
641 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
642         .input_min = 12000000,
643         .input_max = 1000000000,
644         .cf_min = 12000000,
645         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
646         .vco_min = 600000000,
647         .vco_max = 1200000000,
648         .base_reg = PLLD2_BASE,
649         .misc_reg = PLLD2_MISC,
650         .lock_mask = PLL_BASE_LOCK,
651         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
652         .lock_delay = 300,
653         .iddq_reg = PLLD2_BASE,
654         .iddq_bit_idx = PLLSS_IDDQ_BIT,
655         .pdiv_tohw = pll12g_ssd_esd_p,
656         .div_nmp = &pllss_nmp,
657         .ext_misc_reg[0] = 0x570,
658         .ext_misc_reg[1] = 0x574,
659         .ext_misc_reg[2] = 0x578,
660         .max_p = 15,
661         .freq_table = tegra124_pll_d2_freq_table,
662         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
663 };
664 
665 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
666         { 12000000, 600000000, 100, 1, 2, 0 },
667         { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
668         { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
669         { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
670         { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
671         {        0,         0,   0, 0, 0, 0 },
672 };
673 
674 static struct tegra_clk_pll_params pll_dp_params = {
675         .input_min = 12000000,
676         .input_max = 1000000000,
677         .cf_min = 12000000,
678         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
679         .vco_min = 600000000,
680         .vco_max = 1200000000,
681         .base_reg = PLLDP_BASE,
682         .misc_reg = PLLDP_MISC,
683         .lock_mask = PLL_BASE_LOCK,
684         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
685         .lock_delay = 300,
686         .iddq_reg = PLLDP_BASE,
687         .iddq_bit_idx = PLLSS_IDDQ_BIT,
688         .pdiv_tohw = pll12g_ssd_esd_p,
689         .div_nmp = &pllss_nmp,
690         .ext_misc_reg[0] = 0x598,
691         .ext_misc_reg[1] = 0x59c,
692         .ext_misc_reg[2] = 0x5a0,
693         .max_p = 5,
694         .freq_table = pll_dp_freq_table,
695         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
696 };
697 
698 static const struct pdiv_map pllu_p[] = {
699         { .pdiv = 1, .hw_val = 1 },
700         { .pdiv = 2, .hw_val = 0 },
701         { .pdiv = 0, .hw_val = 0 },
702 };
703 
704 static struct div_nmp pllu_nmp = {
705         .divm_shift = 0,
706         .divm_width = 5,
707         .divn_shift = 8,
708         .divn_width = 10,
709         .divp_shift = 20,
710         .divp_width = 1,
711 };
712 
713 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
714         { 12000000, 480000000, 960, 12, 2, 12 },
715         { 13000000, 480000000, 960, 13, 2, 12 },
716         { 16800000, 480000000, 400,  7, 2,  5 },
717         { 19200000, 480000000, 200,  4, 2,  3 },
718         { 26000000, 480000000, 960, 26, 2, 12 },
719         {        0,         0,   0,  0, 0,  0 },
720 };
721 
722 static struct tegra_clk_pll_params pll_u_params = {
723         .input_min = 2000000,
724         .input_max = 40000000,
725         .cf_min = 1000000,
726         .cf_max = 6000000,
727         .vco_min = 480000000,
728         .vco_max = 960000000,
729         .base_reg = PLLU_BASE,
730         .misc_reg = PLLU_MISC,
731         .lock_mask = PLL_BASE_LOCK,
732         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
733         .lock_delay = 1000,
734         .pdiv_tohw = pllu_p,
735         .div_nmp = &pllu_nmp,
736         .freq_table = pll_u_freq_table,
737         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
738                  TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
739 };
740 
741 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
742         [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
743         [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
744         [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
745         [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
746         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
747         [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
748         [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
749         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
750         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
751         [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
752         [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
753         [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
754         [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
755         [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
756         [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
757         [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
758         [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
759         [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
760         [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
761         [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
762         [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
763         [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
764         [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
765         [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
766         [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
767         [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
768         [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
769         [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
770         [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
771         [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
772         [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
773         [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
774         [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
775         [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
776         [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
777         [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
778         [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
779         [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
780         [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
781         [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
782         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
783         [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
784         [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
785         [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
786         [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
787         [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
788         [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
789         [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
790         [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
791         [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
792         [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
793         [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
794         [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
795         [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
796         [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
797         [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
798         [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
799         [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
800         [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
801         [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
802         [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
803         [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
804         [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
805         [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
806         [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
807         [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
808         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
809         [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
810         [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
811         [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
812         [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
813         [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
814         [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
815         [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
816         [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
817         [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
818         [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
819         [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
820         [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
821         [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
822         [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
823         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
824         [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
825         [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
826         [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
827         [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
828         [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
829         [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
830         [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
831         [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
832         [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
833         [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
834         [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
835         [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
836         [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
837         [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
838         [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
839         [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
840         [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
841         [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
842         [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
843         [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
844         [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
845         [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
846         [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
847         [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
848         [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
849         [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
850         [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
851         [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
852         [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
853         [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
854         [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
855         [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
856         [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
857         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
858         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
859         [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
860         [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
861         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
862         [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
863         [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
864         [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
865         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
866         [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
867         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
868         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
869         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
870         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
871         [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
872         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
873         [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
874         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
875         [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
876         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
877         [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
878         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
879         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
880         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
881         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
882         [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
883         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
884         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
885         [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
886         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
887         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
888         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
889         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
890         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
891         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
892         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
893         [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
894         [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
895         [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
896         [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
897         [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
898         [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
899         [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
900         [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
901         [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
902         [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
903         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
904         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
905         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
906         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
907         [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
908         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
909         [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
910         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
911         [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
912         [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
913         [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
914         [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
915         [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
916         [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
917         [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
918         [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
919         [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
920         [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
921         [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
922         [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
923         [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
924         [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
925         [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
926         [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
927         [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
928         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
929         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
930         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
931 };
932 
933 static struct tegra_devclk devclks[] __initdata = {
934         { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
935         { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
936         { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
937         { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
938         { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
939         { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
940         { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
941         { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
942         { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
943         { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
944         { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
945         { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
946         { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
947         { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
948         { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
949         { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
950         { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
951         { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
952         { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
953         { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
954         { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
955         { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
956         { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
957         { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
958         { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
959         { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
960         { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
961         { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
962         { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
963         { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
964         { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
965         { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
966         { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
967         { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
968         { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
969         { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
970         { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
971         { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
972         { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
973         { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
974         { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
975         { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
976         { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
977         { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
978         { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
979         { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
980         { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
981         { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
982         { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
983         { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
984         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
985         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
986         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
987         { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
988         { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
989         { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
990         { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
991         { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
992         { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
993         { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
994         { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
995         { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
996         { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
997         { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
998         { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
999 };
1000 
1001 static struct clk **clks;
1002 
1003 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1004                                             void __iomem *pmc_base)
1005 {
1006         struct clk *clk;
1007 
1008         /* xusb_ss_div2 */
1009         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1010                                         1, 2);
1011         clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1012 
1013         clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
1014                                               1, 17, 181);
1015         clks[TEGRA124_CLK_DPAUX] = clk;
1016 
1017         clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
1018                                 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1019         clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1020 
1021         clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
1022                                              clk_base, 0, 48,
1023                                              periph_clk_enb_refcnt);
1024         clks[TEGRA124_CLK_DSIA] = clk;
1025 
1026         clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
1027                                              clk_base, 0, 82,
1028                                              periph_clk_enb_refcnt);
1029         clks[TEGRA124_CLK_DSIB] = clk;
1030 
1031         clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1032                                     &emc_lock);
1033         clks[TEGRA124_CLK_MC] = clk;
1034 
1035         /* cml0 */
1036         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1037                                 0, 0, &pll_e_lock);
1038         clk_register_clkdev(clk, "cml0", NULL);
1039         clks[TEGRA124_CLK_CML0] = clk;
1040 
1041         /* cml1 */
1042         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1043                                 1, 0, &pll_e_lock);
1044         clk_register_clkdev(clk, "cml1", NULL);
1045         clks[TEGRA124_CLK_CML1] = clk;
1046 
1047         tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1048 }
1049 
1050 static void __init tegra124_pll_init(void __iomem *clk_base,
1051                                      void __iomem *pmc)
1052 {
1053         struct clk *clk;
1054 
1055         /* PLLC */
1056         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1057                         pmc, 0, &pll_c_params, NULL);
1058         clk_register_clkdev(clk, "pll_c", NULL);
1059         clks[TEGRA124_CLK_PLL_C] = clk;
1060 
1061         /* PLLC_OUT1 */
1062         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1063                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1064                         8, 8, 1, NULL);
1065         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1066                                 clk_base + PLLC_OUT, 1, 0,
1067                                 CLK_SET_RATE_PARENT, 0, NULL);
1068         clk_register_clkdev(clk, "pll_c_out1", NULL);
1069         clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1070 
1071         /* PLLC_UD */
1072         clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
1073                                         CLK_SET_RATE_PARENT, 1, 1);
1074         clk_register_clkdev(clk, "pll_c_ud", NULL);
1075         clks[TEGRA124_CLK_PLL_C_UD] = clk;
1076 
1077         /* PLLC2 */
1078         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1079                              &pll_c2_params, NULL);
1080         clk_register_clkdev(clk, "pll_c2", NULL);
1081         clks[TEGRA124_CLK_PLL_C2] = clk;
1082 
1083         /* PLLC3 */
1084         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1085                              &pll_c3_params, NULL);
1086         clk_register_clkdev(clk, "pll_c3", NULL);
1087         clks[TEGRA124_CLK_PLL_C3] = clk;
1088 
1089         /* PLLM */
1090         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1091                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1092                              &pll_m_params, NULL);
1093         clk_register_clkdev(clk, "pll_m", NULL);
1094         clks[TEGRA124_CLK_PLL_M] = clk;
1095 
1096         /* PLLM_OUT1 */
1097         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1098                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1099                                 8, 8, 1, NULL);
1100         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1101                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1102                                 CLK_SET_RATE_PARENT, 0, NULL);
1103         clk_register_clkdev(clk, "pll_m_out1", NULL);
1104         clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1105 
1106         /* PLLM_UD */
1107         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1108                                         CLK_SET_RATE_PARENT, 1, 1);
1109         clk_register_clkdev(clk, "pll_m_ud", NULL);
1110         clks[TEGRA124_CLK_PLL_M_UD] = clk;
1111 
1112         /* PLLU */
1113         clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
1114                                                &pll_u_params, &pll_u_lock);
1115         clk_register_clkdev(clk, "pll_u", NULL);
1116         clks[TEGRA124_CLK_PLL_U] = clk;
1117 
1118         /* PLLU_480M */
1119         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1120                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1121                                 22, 0, &pll_u_lock);
1122         clk_register_clkdev(clk, "pll_u_480M", NULL);
1123         clks[TEGRA124_CLK_PLL_U_480M] = clk;
1124 
1125         /* PLLU_60M */
1126         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1127                                         CLK_SET_RATE_PARENT, 1, 8);
1128         clk_register_clkdev(clk, "pll_u_60M", NULL);
1129         clks[TEGRA124_CLK_PLL_U_60M] = clk;
1130 
1131         /* PLLU_48M */
1132         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1133                                         CLK_SET_RATE_PARENT, 1, 10);
1134         clk_register_clkdev(clk, "pll_u_48M", NULL);
1135         clks[TEGRA124_CLK_PLL_U_48M] = clk;
1136 
1137         /* PLLU_12M */
1138         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1139                                         CLK_SET_RATE_PARENT, 1, 40);
1140         clk_register_clkdev(clk, "pll_u_12M", NULL);
1141         clks[TEGRA124_CLK_PLL_U_12M] = clk;
1142 
1143         /* PLLD */
1144         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1145                             &pll_d_params, &pll_d_lock);
1146         clk_register_clkdev(clk, "pll_d", NULL);
1147         clks[TEGRA124_CLK_PLL_D] = clk;
1148 
1149         /* PLLD_OUT0 */
1150         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1151                                         CLK_SET_RATE_PARENT, 1, 2);
1152         clk_register_clkdev(clk, "pll_d_out0", NULL);
1153         clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1154 
1155         /* PLLRE */
1156         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1157                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1158         clk_register_clkdev(clk, "pll_re_vco", NULL);
1159         clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1160 
1161         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1162                                          clk_base + PLLRE_BASE, 16, 4, 0,
1163                                          pll_re_div_table, &pll_re_lock);
1164         clk_register_clkdev(clk, "pll_re_out", NULL);
1165         clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1166 
1167         /* PLLE */
1168         clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1169                                       clk_base, 0, &pll_e_params, NULL);
1170         clk_register_clkdev(clk, "pll_e", NULL);
1171         clks[TEGRA124_CLK_PLL_E] = clk;
1172 
1173         /* PLLC4 */
1174         clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1175                                         &pll_c4_params, NULL);
1176         clk_register_clkdev(clk, "pll_c4", NULL);
1177         clks[TEGRA124_CLK_PLL_C4] = clk;
1178 
1179         /* PLLDP */
1180         clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1181                                         &pll_dp_params, NULL);
1182         clk_register_clkdev(clk, "pll_dp", NULL);
1183         clks[TEGRA124_CLK_PLL_DP] = clk;
1184 
1185         /* PLLD2 */
1186         clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1187                                         &tegra124_pll_d2_params, NULL);
1188         clk_register_clkdev(clk, "pll_d2", NULL);
1189         clks[TEGRA124_CLK_PLL_D2] = clk;
1190 
1191         /* PLLD2_OUT0 */
1192         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1193                                         CLK_SET_RATE_PARENT, 1, 1);
1194         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1195         clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1196 
1197 }
1198 
1199 /* Tegra124 CPU clock and reset control functions */
1200 static void tegra124_wait_cpu_in_reset(u32 cpu)
1201 {
1202         unsigned int reg;
1203 
1204         do {
1205                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1206                 cpu_relax();
1207         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1208 }
1209 
1210 static void tegra124_disable_cpu_clock(u32 cpu)
1211 {
1212         /* flow controller would take care in the power sequence. */
1213 }
1214 
1215 #ifdef CONFIG_PM_SLEEP
1216 static void tegra124_cpu_clock_suspend(void)
1217 {
1218         /* switch coresite to clk_m, save off original source */
1219         tegra124_cpu_clk_sctx.clk_csite_src =
1220                                 readl(clk_base + CLK_SOURCE_CSITE);
1221         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1222 
1223         tegra124_cpu_clk_sctx.cclkg_burst =
1224                                 readl(clk_base + CCLKG_BURST_POLICY);
1225         tegra124_cpu_clk_sctx.cclkg_divider =
1226                                 readl(clk_base + CCLKG_BURST_POLICY + 4);
1227 }
1228 
1229 static void tegra124_cpu_clock_resume(void)
1230 {
1231         writel(tegra124_cpu_clk_sctx.clk_csite_src,
1232                                 clk_base + CLK_SOURCE_CSITE);
1233 
1234         writel(tegra124_cpu_clk_sctx.cclkg_burst,
1235                                         clk_base + CCLKG_BURST_POLICY);
1236         writel(tegra124_cpu_clk_sctx.cclkg_divider,
1237                                         clk_base + CCLKG_BURST_POLICY + 4);
1238 }
1239 #endif
1240 
1241 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1242         .wait_for_reset = tegra124_wait_cpu_in_reset,
1243         .disable_clock  = tegra124_disable_cpu_clock,
1244 #ifdef CONFIG_PM_SLEEP
1245         .suspend        = tegra124_cpu_clock_suspend,
1246         .resume         = tegra124_cpu_clock_resume,
1247 #endif
1248 };
1249 
1250 static const struct of_device_id pmc_match[] __initconst = {
1251         { .compatible = "nvidia,tegra124-pmc" },
1252         { },
1253 };
1254 
1255 static struct tegra_clk_init_table common_init_table[] __initdata = {
1256         { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
1257         { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
1258         { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
1259         { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
1260         { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
1261         { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
1262         { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
1263         { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
1264         { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
1265         { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1266         { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1267         { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1268         { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1269         { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1270         { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
1271         { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
1272         { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1273         { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1274         { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
1275         { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
1276         { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
1277         { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
1278         { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
1279         { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
1280         { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
1281         { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
1282         { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
1283         { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
1284         { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
1285         { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
1286         { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
1287         { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
1288         { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
1289         { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
1290         { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
1291         { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
1292         { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
1293         /* must be the last entry */
1294         { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1295 };
1296 
1297 static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1298         { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
1299         { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
1300         { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
1301         { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
1302         /* must be the last entry */
1303         { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1304 };
1305 
1306 /* Tegra132 requires the SOC_THERM clock to remain active */
1307 static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1308         { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
1309         /* must be the last entry */
1310         { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1311 };
1312 
1313 static struct tegra_audio_clk_info tegra124_audio_plls[] = {
1314         { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1315 };
1316 
1317 /**
1318  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1319  *
1320  * Program an initial clock rate and enable or disable clocks needed
1321  * by the rest of the kernel, for Tegra124 SoCs.  It is intended to be
1322  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1323  * this will be called as an arch_initcall.  No return value.
1324  */
1325 static void __init tegra124_clock_apply_init_table(void)
1326 {
1327         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1328         tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1329 }
1330 
1331 /**
1332  * tegra124_car_barrier - wait for pending writes to the CAR to complete
1333  *
1334  * Wait for any outstanding writes to the CAR MMIO space from this CPU
1335  * to complete before continuing execution.  No return value.
1336  */
1337 static void tegra124_car_barrier(void)
1338 {
1339         readl_relaxed(clk_base + RST_DFLL_DVCO);
1340 }
1341 
1342 /**
1343  * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1344  *
1345  * Assert the reset line of the DFLL's DVCO.  No return value.
1346  */
1347 static void tegra124_clock_assert_dfll_dvco_reset(void)
1348 {
1349         u32 v;
1350 
1351         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1352         v |= (1 << DVFS_DFLL_RESET_SHIFT);
1353         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1354         tegra124_car_barrier();
1355 }
1356 
1357 /**
1358  * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1359  *
1360  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1361  * operate.  No return value.
1362  */
1363 static void tegra124_clock_deassert_dfll_dvco_reset(void)
1364 {
1365         u32 v;
1366 
1367         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1368         v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1369         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1370         tegra124_car_barrier();
1371 }
1372 
1373 static int tegra124_reset_assert(unsigned long id)
1374 {
1375         if (id == TEGRA124_RST_DFLL_DVCO)
1376                 tegra124_clock_assert_dfll_dvco_reset();
1377         else
1378                 return -EINVAL;
1379 
1380         return 0;
1381 }
1382 
1383 static int tegra124_reset_deassert(unsigned long id)
1384 {
1385         if (id == TEGRA124_RST_DFLL_DVCO)
1386                 tegra124_clock_deassert_dfll_dvco_reset();
1387         else
1388                 return -EINVAL;
1389 
1390         return 0;
1391 }
1392 
1393 /**
1394  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1395  *
1396  * Program an initial clock rate and enable or disable clocks needed
1397  * by the rest of the kernel, for Tegra132 SoCs.  It is intended to be
1398  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1399  * this will be called as an arch_initcall.  No return value.
1400  */
1401 static void __init tegra132_clock_apply_init_table(void)
1402 {
1403         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1404         tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1405 }
1406 
1407 /**
1408  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1409  * @np: struct device_node * of the DT node for the SoC CAR IP block
1410  *
1411  * Register most of the clocks controlled by the CAR IP block, along
1412  * with a few clocks controlled by the PMC IP block.  Everything in
1413  * this function should be common to Tegra124 and Tegra132.  XXX The
1414  * PMC clock initialization should probably be moved to PMC-specific
1415  * driver code.  No return value.
1416  */
1417 static void __init tegra124_132_clock_init_pre(struct device_node *np)
1418 {
1419         struct device_node *node;
1420         u32 plld_base;
1421 
1422         clk_base = of_iomap(np, 0);
1423         if (!clk_base) {
1424                 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1425                 return;
1426         }
1427 
1428         node = of_find_matching_node(NULL, pmc_match);
1429         if (!node) {
1430                 pr_err("Failed to find pmc node\n");
1431                 WARN_ON(1);
1432                 return;
1433         }
1434 
1435         pmc_base = of_iomap(node, 0);
1436         if (!pmc_base) {
1437                 pr_err("Can't map pmc registers\n");
1438                 WARN_ON(1);
1439                 return;
1440         }
1441 
1442         clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1443                               TEGRA124_CAR_BANK_COUNT);
1444         if (!clks)
1445                 return;
1446 
1447         if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1448                                ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
1449                                &pll_ref_freq) < 0)
1450                 return;
1451 
1452         tegra_fixed_clk_init(tegra124_clks);
1453         tegra124_pll_init(clk_base, pmc_base);
1454         tegra124_periph_clk_init(clk_base, pmc_base);
1455         tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
1456                              tegra124_audio_plls,
1457                              ARRAY_SIZE(tegra124_audio_plls));
1458         tegra_pmc_clk_init(pmc_base, tegra124_clks);
1459 
1460         /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1461         plld_base = clk_readl(clk_base + PLLD_BASE);
1462         plld_base &= ~BIT(25);
1463         clk_writel(plld_base, clk_base + PLLD_BASE);
1464 }
1465 
1466 /**
1467  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1468  * @np: struct device_node * of the DT node for the SoC CAR IP block
1469  *
1470  * Register most of the along with a few clocks controlled by the PMC
1471  * IP block.  Everything in this function should be common to Tegra124
1472  * and Tegra132.  This function must be called after
1473  * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1474  * not be set.  No return value.
1475  */
1476 static void __init tegra124_132_clock_init_post(struct device_node *np)
1477 {
1478         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1479                                   &pll_x_params);
1480         tegra_init_special_resets(1, tegra124_reset_assert,
1481                                   tegra124_reset_deassert);
1482         tegra_add_of_provider(np);
1483 
1484         clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
1485                                                         &emc_lock);
1486 
1487         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1488 
1489         tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1490 }
1491 
1492 /**
1493  * tegra124_clock_init - Tegra124-specific clock initialization
1494  * @np: struct device_node * of the DT node for the SoC CAR IP block
1495  *
1496  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1497  * this code is shared between the Tegra124 and Tegra132 SoCs,
1498  * although some of the initial clock settings and CPU clocks differ.
1499  * Intended to be called by the OF init code when a DT node with the
1500  * "nvidia,tegra124-car" string is encountered, and declared with
1501  * CLK_OF_DECLARE.  No return value.
1502  */
1503 static void __init tegra124_clock_init(struct device_node *np)
1504 {
1505         tegra124_132_clock_init_pre(np);
1506         tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1507         tegra124_132_clock_init_post(np);
1508 }
1509 
1510 /**
1511  * tegra132_clock_init - Tegra132-specific clock initialization
1512  * @np: struct device_node * of the DT node for the SoC CAR IP block
1513  *
1514  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1515  * this code is shared between the Tegra124 and Tegra132 SoCs,
1516  * although some of the initial clock settings and CPU clocks differ.
1517  * Intended to be called by the OF init code when a DT node with the
1518  * "nvidia,tegra132-car" string is encountered, and declared with
1519  * CLK_OF_DECLARE.  No return value.
1520  */
1521 static void __init tegra132_clock_init(struct device_node *np)
1522 {
1523         tegra124_132_clock_init_pre(np);
1524 
1525         /*
1526          * On Tegra132, these clocks are controlled by the
1527          * CLUSTER_clocks IP block, located in the CPU complex
1528          */
1529         tegra124_clks[tegra_clk_cclk_g].present = false;
1530         tegra124_clks[tegra_clk_cclk_lp].present = false;
1531         tegra124_clks[tegra_clk_pll_x].present = false;
1532         tegra124_clks[tegra_clk_pll_x_out0].present = false;
1533 
1534         tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1535         tegra124_132_clock_init_post(np);
1536 }
1537 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1538 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
1539 

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