Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/clk/tegra/clk-tegra124.c

  1 /*
  2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/clk-provider.h>
 20 #include <linux/clkdev.h>
 21 #include <linux/of.h>
 22 #include <linux/of_address.h>
 23 #include <linux/delay.h>
 24 #include <linux/export.h>
 25 #include <linux/clk/tegra.h>
 26 #include <dt-bindings/clock/tegra124-car.h>
 27 
 28 #include "clk.h"
 29 #include "clk-id.h"
 30 
 31 #define CLK_SOURCE_CSITE 0x1d4
 32 #define CLK_SOURCE_EMC 0x19c
 33 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 34 
 35 #define PLLC_BASE 0x80
 36 #define PLLC_OUT 0x84
 37 #define PLLC_MISC2 0x88
 38 #define PLLC_MISC 0x8c
 39 #define PLLC2_BASE 0x4e8
 40 #define PLLC2_MISC 0x4ec
 41 #define PLLC3_BASE 0x4fc
 42 #define PLLC3_MISC 0x500
 43 #define PLLM_BASE 0x90
 44 #define PLLM_OUT 0x94
 45 #define PLLM_MISC 0x9c
 46 #define PLLP_BASE 0xa0
 47 #define PLLP_MISC 0xac
 48 #define PLLA_BASE 0xb0
 49 #define PLLA_MISC 0xbc
 50 #define PLLD_BASE 0xd0
 51 #define PLLD_MISC 0xdc
 52 #define PLLU_BASE 0xc0
 53 #define PLLU_MISC 0xcc
 54 #define PLLX_BASE 0xe0
 55 #define PLLX_MISC 0xe4
 56 #define PLLX_MISC2 0x514
 57 #define PLLX_MISC3 0x518
 58 #define PLLE_BASE 0xe8
 59 #define PLLE_MISC 0xec
 60 #define PLLD2_BASE 0x4b8
 61 #define PLLD2_MISC 0x4bc
 62 #define PLLE_AUX 0x48c
 63 #define PLLRE_BASE 0x4c4
 64 #define PLLRE_MISC 0x4c8
 65 #define PLLDP_BASE 0x590
 66 #define PLLDP_MISC 0x594
 67 #define PLLC4_BASE 0x5a4
 68 #define PLLC4_MISC 0x5a8
 69 
 70 #define PLLC_IDDQ_BIT 26
 71 #define PLLRE_IDDQ_BIT 16
 72 #define PLLSS_IDDQ_BIT 19
 73 
 74 #define PLL_BASE_LOCK BIT(27)
 75 #define PLLE_MISC_LOCK BIT(11)
 76 #define PLLRE_MISC_LOCK BIT(24)
 77 
 78 #define PLL_MISC_LOCK_ENABLE 18
 79 #define PLLC_MISC_LOCK_ENABLE 24
 80 #define PLLDU_MISC_LOCK_ENABLE 22
 81 #define PLLE_MISC_LOCK_ENABLE 9
 82 #define PLLRE_MISC_LOCK_ENABLE 30
 83 #define PLLSS_MISC_LOCK_ENABLE 30
 84 
 85 #define PLLXC_SW_MAX_P 6
 86 
 87 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 88 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 89 
 90 #define UTMIP_PLL_CFG2 0x488
 91 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 92 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 93 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 94 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 95 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 96 
 97 #define UTMIP_PLL_CFG1 0x484
 98 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
 99 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
100 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
101 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
102 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
103 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
104 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
105 
106 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
107 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
108 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
109 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
110 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
111 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
112 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
113 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
114 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
115 
116 /* Tegra CPU clock and reset control regs */
117 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
118 
119 #ifdef CONFIG_PM_SLEEP
120 static struct cpu_clk_suspend_context {
121         u32 clk_csite_src;
122 } tegra124_cpu_clk_sctx;
123 #endif
124 
125 static void __iomem *clk_base;
126 static void __iomem *pmc_base;
127 
128 static unsigned long osc_freq;
129 static unsigned long pll_ref_freq;
130 
131 static DEFINE_SPINLOCK(pll_d_lock);
132 static DEFINE_SPINLOCK(pll_d2_lock);
133 static DEFINE_SPINLOCK(pll_e_lock);
134 static DEFINE_SPINLOCK(pll_re_lock);
135 static DEFINE_SPINLOCK(pll_u_lock);
136 
137 /* possible OSC frequencies in Hz */
138 static unsigned long tegra124_input_freq[] = {
139         [0] = 13000000,
140         [1] = 16800000,
141         [4] = 19200000,
142         [5] = 38400000,
143         [8] = 12000000,
144         [9] = 48000000,
145         [12] = 260000000,
146 };
147 
148 static const char *mux_plld_out0_plld2_out0[] = {
149         "pll_d_out0", "pll_d2_out0",
150 };
151 #define mux_plld_out0_plld2_out0_idx NULL
152 
153 static const char *mux_pllmcp_clkm[] = {
154         "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
155 };
156 #define mux_pllmcp_clkm_idx NULL
157 
158 static struct div_nmp pllxc_nmp = {
159         .divm_shift = 0,
160         .divm_width = 8,
161         .divn_shift = 8,
162         .divn_width = 8,
163         .divp_shift = 20,
164         .divp_width = 4,
165 };
166 
167 static struct pdiv_map pllxc_p[] = {
168         { .pdiv = 1, .hw_val = 0 },
169         { .pdiv = 2, .hw_val = 1 },
170         { .pdiv = 3, .hw_val = 2 },
171         { .pdiv = 4, .hw_val = 3 },
172         { .pdiv = 5, .hw_val = 4 },
173         { .pdiv = 6, .hw_val = 5 },
174         { .pdiv = 8, .hw_val = 6 },
175         { .pdiv = 10, .hw_val = 7 },
176         { .pdiv = 12, .hw_val = 8 },
177         { .pdiv = 16, .hw_val = 9 },
178         { .pdiv = 12, .hw_val = 10 },
179         { .pdiv = 16, .hw_val = 11 },
180         { .pdiv = 20, .hw_val = 12 },
181         { .pdiv = 24, .hw_val = 13 },
182         { .pdiv = 32, .hw_val = 14 },
183         { .pdiv = 0, .hw_val = 0 },
184 };
185 
186 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
187         /* 1 GHz */
188         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
189         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
190         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
191         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
192         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
193         {0, 0, 0, 0, 0, 0},
194 };
195 
196 static struct tegra_clk_pll_params pll_x_params = {
197         .input_min = 12000000,
198         .input_max = 800000000,
199         .cf_min = 12000000,
200         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
201         .vco_min = 700000000,
202         .vco_max = 3000000000UL,
203         .base_reg = PLLX_BASE,
204         .misc_reg = PLLX_MISC,
205         .lock_mask = PLL_BASE_LOCK,
206         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
207         .lock_delay = 300,
208         .iddq_reg = PLLX_MISC3,
209         .iddq_bit_idx = 3,
210         .max_p = 6,
211         .dyn_ramp_reg = PLLX_MISC2,
212         .stepa_shift = 16,
213         .stepb_shift = 24,
214         .pdiv_tohw = pllxc_p,
215         .div_nmp = &pllxc_nmp,
216         .freq_table = pll_x_freq_table,
217         .flags = TEGRA_PLL_USE_LOCK,
218 };
219 
220 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
221         { 12000000, 624000000, 104, 1, 2},
222         { 12000000, 600000000, 100, 1, 2},
223         { 13000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
224         { 16800000, 600000000,  71, 1, 2},      /* actual: 596.4 MHz */
225         { 19200000, 600000000,  62, 1, 2},      /* actual: 595.2 MHz */
226         { 26000000, 600000000,  92, 2, 2},      /* actual: 598.0 MHz */
227         { 0, 0, 0, 0, 0, 0 },
228 };
229 
230 static struct tegra_clk_pll_params pll_c_params = {
231         .input_min = 12000000,
232         .input_max = 800000000,
233         .cf_min = 12000000,
234         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
235         .vco_min = 600000000,
236         .vco_max = 1400000000,
237         .base_reg = PLLC_BASE,
238         .misc_reg = PLLC_MISC,
239         .lock_mask = PLL_BASE_LOCK,
240         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
241         .lock_delay = 300,
242         .iddq_reg = PLLC_MISC,
243         .iddq_bit_idx = PLLC_IDDQ_BIT,
244         .max_p = PLLXC_SW_MAX_P,
245         .dyn_ramp_reg = PLLC_MISC2,
246         .stepa_shift = 17,
247         .stepb_shift = 9,
248         .pdiv_tohw = pllxc_p,
249         .div_nmp = &pllxc_nmp,
250         .freq_table = pll_c_freq_table,
251         .flags = TEGRA_PLL_USE_LOCK,
252 };
253 
254 static struct div_nmp pllcx_nmp = {
255         .divm_shift = 0,
256         .divm_width = 2,
257         .divn_shift = 8,
258         .divn_width = 8,
259         .divp_shift = 20,
260         .divp_width = 3,
261 };
262 
263 static struct pdiv_map pllc_p[] = {
264         { .pdiv = 1, .hw_val = 0 },
265         { .pdiv = 2, .hw_val = 1 },
266         { .pdiv = 3, .hw_val = 2 },
267         { .pdiv = 4, .hw_val = 3 },
268         { .pdiv = 6, .hw_val = 4 },
269         { .pdiv = 8, .hw_val = 5 },
270         { .pdiv = 12, .hw_val = 6 },
271         { .pdiv = 16, .hw_val = 7 },
272         { .pdiv = 0, .hw_val = 0 },
273 };
274 
275 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
276         {12000000, 600000000, 100, 1, 2},
277         {13000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
278         {16800000, 600000000, 71, 1, 2},        /* actual: 596.4 MHz */
279         {19200000, 600000000, 62, 1, 2},        /* actual: 595.2 MHz */
280         {26000000, 600000000, 92, 2, 2},        /* actual: 598.0 MHz */
281         {0, 0, 0, 0, 0, 0},
282 };
283 
284 static struct tegra_clk_pll_params pll_c2_params = {
285         .input_min = 12000000,
286         .input_max = 48000000,
287         .cf_min = 12000000,
288         .cf_max = 19200000,
289         .vco_min = 600000000,
290         .vco_max = 1200000000,
291         .base_reg = PLLC2_BASE,
292         .misc_reg = PLLC2_MISC,
293         .lock_mask = PLL_BASE_LOCK,
294         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
295         .lock_delay = 300,
296         .pdiv_tohw = pllc_p,
297         .div_nmp = &pllcx_nmp,
298         .max_p = 7,
299         .ext_misc_reg[0] = 0x4f0,
300         .ext_misc_reg[1] = 0x4f4,
301         .ext_misc_reg[2] = 0x4f8,
302         .freq_table = pll_cx_freq_table,
303         .flags = TEGRA_PLL_USE_LOCK,
304 };
305 
306 static struct tegra_clk_pll_params pll_c3_params = {
307         .input_min = 12000000,
308         .input_max = 48000000,
309         .cf_min = 12000000,
310         .cf_max = 19200000,
311         .vco_min = 600000000,
312         .vco_max = 1200000000,
313         .base_reg = PLLC3_BASE,
314         .misc_reg = PLLC3_MISC,
315         .lock_mask = PLL_BASE_LOCK,
316         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
317         .lock_delay = 300,
318         .pdiv_tohw = pllc_p,
319         .div_nmp = &pllcx_nmp,
320         .max_p = 7,
321         .ext_misc_reg[0] = 0x504,
322         .ext_misc_reg[1] = 0x508,
323         .ext_misc_reg[2] = 0x50c,
324         .freq_table = pll_cx_freq_table,
325         .flags = TEGRA_PLL_USE_LOCK,
326 };
327 
328 static struct div_nmp pllss_nmp = {
329         .divm_shift = 0,
330         .divm_width = 8,
331         .divn_shift = 8,
332         .divn_width = 8,
333         .divp_shift = 20,
334         .divp_width = 4,
335 };
336 
337 static struct pdiv_map pll12g_ssd_esd_p[] = {
338         { .pdiv = 1, .hw_val = 0 },
339         { .pdiv = 2, .hw_val = 1 },
340         { .pdiv = 3, .hw_val = 2 },
341         { .pdiv = 4, .hw_val = 3 },
342         { .pdiv = 5, .hw_val = 4 },
343         { .pdiv = 6, .hw_val = 5 },
344         { .pdiv = 8, .hw_val = 6 },
345         { .pdiv = 10, .hw_val = 7 },
346         { .pdiv = 12, .hw_val = 8 },
347         { .pdiv = 16, .hw_val = 9 },
348         { .pdiv = 12, .hw_val = 10 },
349         { .pdiv = 16, .hw_val = 11 },
350         { .pdiv = 20, .hw_val = 12 },
351         { .pdiv = 24, .hw_val = 13 },
352         { .pdiv = 32, .hw_val = 14 },
353         { .pdiv = 0, .hw_val = 0 },
354 };
355 
356 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
357         { 12000000, 600000000, 100, 1, 1},
358         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
359         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
360         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
361         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
362         { 0, 0, 0, 0, 0, 0 },
363 };
364 
365 static struct tegra_clk_pll_params pll_c4_params = {
366         .input_min = 12000000,
367         .input_max = 1000000000,
368         .cf_min = 12000000,
369         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
370         .vco_min = 600000000,
371         .vco_max = 1200000000,
372         .base_reg = PLLC4_BASE,
373         .misc_reg = PLLC4_MISC,
374         .lock_mask = PLL_BASE_LOCK,
375         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
376         .lock_delay = 300,
377         .iddq_reg = PLLC4_BASE,
378         .iddq_bit_idx = PLLSS_IDDQ_BIT,
379         .pdiv_tohw = pll12g_ssd_esd_p,
380         .div_nmp = &pllss_nmp,
381         .ext_misc_reg[0] = 0x5ac,
382         .ext_misc_reg[1] = 0x5b0,
383         .ext_misc_reg[2] = 0x5b4,
384         .freq_table = pll_c4_freq_table,
385 };
386 
387 static struct pdiv_map pllm_p[] = {
388         { .pdiv = 1, .hw_val = 0 },
389         { .pdiv = 2, .hw_val = 1 },
390         { .pdiv = 0, .hw_val = 0 },
391 };
392 
393 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
394         {12000000, 800000000, 66, 1, 1},        /* actual: 792.0 MHz */
395         {13000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
396         {16800000, 800000000, 47, 1, 1},        /* actual: 789.6 MHz */
397         {19200000, 800000000, 41, 1, 1},        /* actual: 787.2 MHz */
398         {26000000, 800000000, 61, 2, 1},        /* actual: 793.0 MHz */
399         {0, 0, 0, 0, 0, 0},
400 };
401 
402 static struct div_nmp pllm_nmp = {
403         .divm_shift = 0,
404         .divm_width = 8,
405         .override_divm_shift = 0,
406         .divn_shift = 8,
407         .divn_width = 8,
408         .override_divn_shift = 8,
409         .divp_shift = 20,
410         .divp_width = 1,
411         .override_divp_shift = 27,
412 };
413 
414 static struct tegra_clk_pll_params pll_m_params = {
415         .input_min = 12000000,
416         .input_max = 500000000,
417         .cf_min = 12000000,
418         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
419         .vco_min = 400000000,
420         .vco_max = 1066000000,
421         .base_reg = PLLM_BASE,
422         .misc_reg = PLLM_MISC,
423         .lock_mask = PLL_BASE_LOCK,
424         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
425         .lock_delay = 300,
426         .max_p = 2,
427         .pdiv_tohw = pllm_p,
428         .div_nmp = &pllm_nmp,
429         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
430         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
431         .freq_table = pll_m_freq_table,
432         .flags = TEGRA_PLL_USE_LOCK,
433 };
434 
435 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
436         /* PLLE special case: use cpcon field to store cml divider value */
437         {336000000, 100000000, 100, 21, 16, 11},
438         {312000000, 100000000, 200, 26, 24, 13},
439         {13000000,  100000000, 200, 1,  26, 13},
440         {12000000,  100000000, 200, 1,  24, 13},
441         {0, 0, 0, 0, 0, 0},
442 };
443 
444 static struct div_nmp plle_nmp = {
445         .divm_shift = 0,
446         .divm_width = 8,
447         .divn_shift = 8,
448         .divn_width = 8,
449         .divp_shift = 24,
450         .divp_width = 4,
451 };
452 
453 static struct tegra_clk_pll_params pll_e_params = {
454         .input_min = 12000000,
455         .input_max = 1000000000,
456         .cf_min = 12000000,
457         .cf_max = 75000000,
458         .vco_min = 1600000000,
459         .vco_max = 2400000000U,
460         .base_reg = PLLE_BASE,
461         .misc_reg = PLLE_MISC,
462         .aux_reg = PLLE_AUX,
463         .lock_mask = PLLE_MISC_LOCK,
464         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
465         .lock_delay = 300,
466         .div_nmp = &plle_nmp,
467         .freq_table = pll_e_freq_table,
468         .flags = TEGRA_PLL_FIXED,
469         .fixed_rate = 100000000,
470 };
471 
472 static const struct clk_div_table pll_re_div_table[] = {
473         { .val = 0, .div = 1 },
474         { .val = 1, .div = 2 },
475         { .val = 2, .div = 3 },
476         { .val = 3, .div = 4 },
477         { .val = 4, .div = 5 },
478         { .val = 5, .div = 6 },
479         { .val = 0, .div = 0 },
480 };
481 
482 static struct div_nmp pllre_nmp = {
483         .divm_shift = 0,
484         .divm_width = 8,
485         .divn_shift = 8,
486         .divn_width = 8,
487         .divp_shift = 16,
488         .divp_width = 4,
489 };
490 
491 static struct tegra_clk_pll_params pll_re_vco_params = {
492         .input_min = 12000000,
493         .input_max = 1000000000,
494         .cf_min = 12000000,
495         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
496         .vco_min = 300000000,
497         .vco_max = 600000000,
498         .base_reg = PLLRE_BASE,
499         .misc_reg = PLLRE_MISC,
500         .lock_mask = PLLRE_MISC_LOCK,
501         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
502         .lock_delay = 300,
503         .iddq_reg = PLLRE_MISC,
504         .iddq_bit_idx = PLLRE_IDDQ_BIT,
505         .div_nmp = &pllre_nmp,
506         .flags = TEGRA_PLL_USE_LOCK,
507 };
508 
509 static struct div_nmp pllp_nmp = {
510         .divm_shift = 0,
511         .divm_width = 5,
512         .divn_shift = 8,
513         .divn_width = 10,
514         .divp_shift = 20,
515         .divp_width = 3,
516 };
517 
518 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
519         {12000000, 408000000, 408, 12, 0, 8},
520         {13000000, 408000000, 408, 13, 0, 8},
521         {16800000, 408000000, 340, 14, 0, 8},
522         {19200000, 408000000, 340, 16, 0, 8},
523         {26000000, 408000000, 408, 26, 0, 8},
524         {0, 0, 0, 0, 0, 0},
525 };
526 
527 static struct tegra_clk_pll_params pll_p_params = {
528         .input_min = 2000000,
529         .input_max = 31000000,
530         .cf_min = 1000000,
531         .cf_max = 6000000,
532         .vco_min = 200000000,
533         .vco_max = 700000000,
534         .base_reg = PLLP_BASE,
535         .misc_reg = PLLP_MISC,
536         .lock_mask = PLL_BASE_LOCK,
537         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
538         .lock_delay = 300,
539         .div_nmp = &pllp_nmp,
540         .freq_table = pll_p_freq_table,
541         .fixed_rate = 408000000,
542         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
543 };
544 
545 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
546         {9600000, 282240000, 147, 5, 0, 4},
547         {9600000, 368640000, 192, 5, 0, 4},
548         {9600000, 240000000, 200, 8, 0, 8},
549 
550         {28800000, 282240000, 245, 25, 0, 8},
551         {28800000, 368640000, 320, 25, 0, 8},
552         {28800000, 240000000, 200, 24, 0, 8},
553         {0, 0, 0, 0, 0, 0},
554 };
555 
556 static struct tegra_clk_pll_params pll_a_params = {
557         .input_min = 2000000,
558         .input_max = 31000000,
559         .cf_min = 1000000,
560         .cf_max = 6000000,
561         .vco_min = 200000000,
562         .vco_max = 700000000,
563         .base_reg = PLLA_BASE,
564         .misc_reg = PLLA_MISC,
565         .lock_mask = PLL_BASE_LOCK,
566         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
567         .lock_delay = 300,
568         .div_nmp = &pllp_nmp,
569         .freq_table = pll_a_freq_table,
570         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
571 };
572 
573 static struct div_nmp plld_nmp = {
574         .divm_shift = 0,
575         .divm_width = 5,
576         .divn_shift = 8,
577         .divn_width = 11,
578         .divp_shift = 20,
579         .divp_width = 3,
580 };
581 
582 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
583         {12000000, 216000000, 864, 12, 4, 12},
584         {13000000, 216000000, 864, 13, 4, 12},
585         {16800000, 216000000, 720, 14, 4, 12},
586         {19200000, 216000000, 720, 16, 4, 12},
587         {26000000, 216000000, 864, 26, 4, 12},
588 
589         {12000000, 594000000, 594, 12, 1, 12},
590         {13000000, 594000000, 594, 13, 1, 12},
591         {16800000, 594000000, 495, 14, 1, 12},
592         {19200000, 594000000, 495, 16, 1, 12},
593         {26000000, 594000000, 594, 26, 1, 12},
594 
595         {12000000, 1000000000, 1000, 12, 1, 12},
596         {13000000, 1000000000, 1000, 13, 1, 12},
597         {19200000, 1000000000, 625, 12, 1, 12},
598         {26000000, 1000000000, 1000, 26, 1, 12},
599 
600         {0, 0, 0, 0, 0, 0},
601 };
602 
603 static struct tegra_clk_pll_params pll_d_params = {
604         .input_min = 2000000,
605         .input_max = 40000000,
606         .cf_min = 1000000,
607         .cf_max = 6000000,
608         .vco_min = 500000000,
609         .vco_max = 1000000000,
610         .base_reg = PLLD_BASE,
611         .misc_reg = PLLD_MISC,
612         .lock_mask = PLL_BASE_LOCK,
613         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
614         .lock_delay = 1000,
615         .div_nmp = &plld_nmp,
616         .freq_table = pll_d_freq_table,
617         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
618                  TEGRA_PLL_USE_LOCK,
619 };
620 
621 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
622         { 12000000, 594000000,  99, 1, 2},
623         { 13000000, 594000000,  91, 1, 2},      /* actual: 591.5 MHz */
624         { 16800000, 594000000,  71, 1, 2},      /* actual: 596.4 MHz */
625         { 19200000, 594000000,  62, 1, 2},      /* actual: 595.2 MHz */
626         { 26000000, 594000000,  91, 2, 2},      /* actual: 591.5 MHz */
627         { 0, 0, 0, 0, 0, 0 },
628 };
629 
630 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
631         .input_min = 12000000,
632         .input_max = 1000000000,
633         .cf_min = 12000000,
634         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
635         .vco_min = 600000000,
636         .vco_max = 1200000000,
637         .base_reg = PLLD2_BASE,
638         .misc_reg = PLLD2_MISC,
639         .lock_mask = PLL_BASE_LOCK,
640         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
641         .lock_delay = 300,
642         .iddq_reg = PLLD2_BASE,
643         .iddq_bit_idx = PLLSS_IDDQ_BIT,
644         .pdiv_tohw = pll12g_ssd_esd_p,
645         .div_nmp = &pllss_nmp,
646         .ext_misc_reg[0] = 0x570,
647         .ext_misc_reg[1] = 0x574,
648         .ext_misc_reg[2] = 0x578,
649         .max_p = 15,
650         .freq_table = tegra124_pll_d2_freq_table,
651 };
652 
653 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
654         { 12000000, 600000000, 100, 1, 1},
655         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
656         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
657         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
658         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
659         { 0, 0, 0, 0, 0, 0 },
660 };
661 
662 static struct tegra_clk_pll_params pll_dp_params = {
663         .input_min = 12000000,
664         .input_max = 1000000000,
665         .cf_min = 12000000,
666         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
667         .vco_min = 600000000,
668         .vco_max = 1200000000,
669         .base_reg = PLLDP_BASE,
670         .misc_reg = PLLDP_MISC,
671         .lock_mask = PLL_BASE_LOCK,
672         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
673         .lock_delay = 300,
674         .iddq_reg = PLLDP_BASE,
675         .iddq_bit_idx = PLLSS_IDDQ_BIT,
676         .pdiv_tohw = pll12g_ssd_esd_p,
677         .div_nmp = &pllss_nmp,
678         .ext_misc_reg[0] = 0x598,
679         .ext_misc_reg[1] = 0x59c,
680         .ext_misc_reg[2] = 0x5a0,
681         .max_p = 5,
682         .freq_table = pll_dp_freq_table,
683 };
684 
685 static struct pdiv_map pllu_p[] = {
686         { .pdiv = 1, .hw_val = 1 },
687         { .pdiv = 2, .hw_val = 0 },
688         { .pdiv = 0, .hw_val = 0 },
689 };
690 
691 static struct div_nmp pllu_nmp = {
692         .divm_shift = 0,
693         .divm_width = 5,
694         .divn_shift = 8,
695         .divn_width = 10,
696         .divp_shift = 20,
697         .divp_width = 1,
698 };
699 
700 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
701         {12000000, 480000000, 960, 12, 2, 12},
702         {13000000, 480000000, 960, 13, 2, 12},
703         {16800000, 480000000, 400, 7, 2, 5},
704         {19200000, 480000000, 200, 4, 2, 3},
705         {26000000, 480000000, 960, 26, 2, 12},
706         {0, 0, 0, 0, 0, 0},
707 };
708 
709 static struct tegra_clk_pll_params pll_u_params = {
710         .input_min = 2000000,
711         .input_max = 40000000,
712         .cf_min = 1000000,
713         .cf_max = 6000000,
714         .vco_min = 480000000,
715         .vco_max = 960000000,
716         .base_reg = PLLU_BASE,
717         .misc_reg = PLLU_MISC,
718         .lock_mask = PLL_BASE_LOCK,
719         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
720         .lock_delay = 1000,
721         .pdiv_tohw = pllu_p,
722         .div_nmp = &pllu_nmp,
723         .freq_table = pll_u_freq_table,
724         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
725                  TEGRA_PLL_USE_LOCK,
726 };
727 
728 struct utmi_clk_param {
729         /* Oscillator Frequency in KHz */
730         u32 osc_frequency;
731         /* UTMIP PLL Enable Delay Count  */
732         u8 enable_delay_count;
733         /* UTMIP PLL Stable count */
734         u8 stable_count;
735         /*  UTMIP PLL Active delay count */
736         u8 active_delay_count;
737         /* UTMIP PLL Xtal frequency count */
738         u8 xtal_freq_count;
739 };
740 
741 static const struct utmi_clk_param utmi_parameters[] = {
742         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
743          .stable_count = 0x33, .active_delay_count = 0x05,
744          .xtal_freq_count = 0x7F},
745         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
746          .stable_count = 0x4B, .active_delay_count = 0x06,
747          .xtal_freq_count = 0xBB},
748         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
749          .stable_count = 0x2F, .active_delay_count = 0x04,
750          .xtal_freq_count = 0x76},
751         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
752          .stable_count = 0x66, .active_delay_count = 0x09,
753          .xtal_freq_count = 0xFE},
754         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
755          .stable_count = 0x41, .active_delay_count = 0x0A,
756          .xtal_freq_count = 0xA4},
757 };
758 
759 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
760         [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
761         [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
762         [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
763         [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
764         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
765         [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
766         [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
767         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
768         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
769         [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
770         [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
771         [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
772         [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
773         [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
774         [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
775         [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
776         [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
777         [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
778         [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
779         [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
780         [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
781         [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
782         [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
783         [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
784         [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
785         [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
786         [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
787         [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
788         [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
789         [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
790         [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
791         [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
792         [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
793         [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
794         [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
795         [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
796         [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
797         [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
798         [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
799         [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
800         [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
801         [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
802         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
803         [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
804         [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
805         [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
806         [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
807         [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
808         [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
809         [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
810         [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
811         [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
812         [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
813         [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
814         [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
815         [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
816         [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
817         [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
818         [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
819         [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
820         [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
821         [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
822         [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
823         [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
824         [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
825         [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
826         [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
827         [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
828         [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
829         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
830         [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
831         [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
832         [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
833         [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
834         [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
835         [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
836         [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
837         [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
838         [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
839         [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
840         [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
841         [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
842         [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
843         [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
844         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
845         [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
846         [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
847         [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
848         [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
849         [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
850         [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
851         [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
852         [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
853         [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
854         [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
855         [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
856         [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
857         [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
858         [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
859         [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
860         [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
861         [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
862         [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
863         [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
864         [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
865         [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
866         [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
867         [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
868         [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
869         [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
870         [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
871         [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
872         [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
873         [tegra_clk_vi_sensor] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
874         [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
875         [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
876         [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
877         [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
878         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
879         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
880         [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
881         [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
882         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
883         [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
884         [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
885         [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
886         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
887         [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
888         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
889         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
890         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
891         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
892         [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
893         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
894         [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
895         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
896         [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
897         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
898         [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
899         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
900         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
901         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
902         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
903         [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
904         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
905         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
906         [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
907         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
908         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
909         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
910         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
911         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
912         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
913         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
914         [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
915         [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
916         [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
917         [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
918         [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
919         [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
920         [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
921         [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
922         [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
923         [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
924         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
925         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
926         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
927         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
928         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
929         [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
930         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
931         [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
932         [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
933         [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
934         [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
935         [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
936         [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
937         [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
938         [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
939         [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
940         [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
941         [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
942         [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
943         [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
944         [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
945         [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
946         [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
947         [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
948         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
949         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
950         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
951         [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
952         [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
953 };
954 
955 static struct tegra_devclk devclks[] __initdata = {
956         { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
957         { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
958         { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
959         { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
960         { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
961         { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
962         { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
963         { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
964         { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
965         { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
966         { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
967         { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
968         { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
969         { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
970         { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
971         { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
972         { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
973         { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
974         { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
975         { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
976         { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
977         { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
978         { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
979         { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
980         { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
981         { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
982         { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
983         { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
984         { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
985         { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
986         { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
987         { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
988         { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
989         { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
990         { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
991         { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
992         { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
993         { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
994         { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
995         { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
996         { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
997         { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
998         { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
999         { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
1000         { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
1001         { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
1002         { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
1003         { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
1004         { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
1005         { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
1006         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1007         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1008         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1009         { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1010         { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1011         { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1012         { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1013         { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1014         { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1015         { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1016         { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1017         { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1018 };
1019 
1020 static struct clk **clks;
1021 
1022 static void tegra124_utmi_param_configure(void __iomem *clk_base)
1023 {
1024         u32 reg;
1025         int i;
1026 
1027         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1028                 if (osc_freq == utmi_parameters[i].osc_frequency)
1029                         break;
1030         }
1031 
1032         if (i >= ARRAY_SIZE(utmi_parameters)) {
1033                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1034                        osc_freq);
1035                 return;
1036         }
1037 
1038         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1039 
1040         /* Program UTMIP PLL stable and active counts */
1041         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1042         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1043         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1044 
1045         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1046 
1047         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1048                                             active_delay_count);
1049 
1050         /* Remove power downs from UTMIP PLL control bits */
1051         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1052         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1053         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1054 
1055         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1056 
1057         /* Program UTMIP PLL delay and oscillator frequency counts */
1058         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1059         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1060 
1061         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1062                                             enable_delay_count);
1063 
1064         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1065         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1066                                            xtal_freq_count);
1067 
1068         /* Remove power downs from UTMIP PLL control bits */
1069         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1070         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1071         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1072         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1073         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1074 
1075         /* Setup HW control of UTMIPLL */
1076         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1077         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1078         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1079         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1080         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1081 
1082         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1083         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1084         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1085         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1086 
1087         udelay(1);
1088 
1089         /* Setup SW override of UTMIPLL assuming USB2.0
1090            ports are assigned to USB2 */
1091         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1092         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1093         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1094         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1095 
1096         udelay(1);
1097 
1098         /* Enable HW control UTMIPLL */
1099         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1100         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1101         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1102 }
1103 
1104 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1105                                             void __iomem *pmc_base)
1106 {
1107         struct clk *clk;
1108         u32 val;
1109 
1110         /* xusb_hs_src */
1111         val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1112         val |= BIT(25); /* always select PLLU_60M */
1113         writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1114 
1115         clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1116                                         1, 1);
1117         clks[TEGRA124_CLK_XUSB_HS_SRC] = clk;
1118 
1119         /* dsia mux */
1120         clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1121                                ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1122                                clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1123         clks[TEGRA124_CLK_DSIA_MUX] = clk;
1124 
1125         /* dsib mux */
1126         clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1127                                ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1128                                clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1129         clks[TEGRA124_CLK_DSIB_MUX] = clk;
1130 
1131         /* emc mux */
1132         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1133                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
1134                                clk_base + CLK_SOURCE_EMC,
1135                                29, 3, 0, NULL);
1136 
1137         /* cml0 */
1138         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1139                                 0, 0, &pll_e_lock);
1140         clk_register_clkdev(clk, "cml0", NULL);
1141         clks[TEGRA124_CLK_CML0] = clk;
1142 
1143         /* cml1 */
1144         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1145                                 1, 0, &pll_e_lock);
1146         clk_register_clkdev(clk, "cml1", NULL);
1147         clks[TEGRA124_CLK_CML1] = clk;
1148 
1149         tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1150 }
1151 
1152 static void __init tegra124_pll_init(void __iomem *clk_base,
1153                                      void __iomem *pmc)
1154 {
1155         u32 val;
1156         struct clk *clk;
1157 
1158         /* PLLC */
1159         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1160                         pmc, 0, &pll_c_params, NULL);
1161         clk_register_clkdev(clk, "pll_c", NULL);
1162         clks[TEGRA124_CLK_PLL_C] = clk;
1163 
1164         /* PLLC_OUT1 */
1165         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1166                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1167                         8, 8, 1, NULL);
1168         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1169                                 clk_base + PLLC_OUT, 1, 0,
1170                                 CLK_SET_RATE_PARENT, 0, NULL);
1171         clk_register_clkdev(clk, "pll_c_out1", NULL);
1172         clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1173 
1174         /* PLLC2 */
1175         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1176                              &pll_c2_params, NULL);
1177         clk_register_clkdev(clk, "pll_c2", NULL);
1178         clks[TEGRA124_CLK_PLL_C2] = clk;
1179 
1180         /* PLLC3 */
1181         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1182                              &pll_c3_params, NULL);
1183         clk_register_clkdev(clk, "pll_c3", NULL);
1184         clks[TEGRA124_CLK_PLL_C3] = clk;
1185 
1186         /* PLLM */
1187         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1188                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1189                              &pll_m_params, NULL);
1190         clk_register_clkdev(clk, "pll_m", NULL);
1191         clks[TEGRA124_CLK_PLL_M] = clk;
1192 
1193         /* PLLM_OUT1 */
1194         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1195                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1196                                 8, 8, 1, NULL);
1197         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1198                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1199                                 CLK_SET_RATE_PARENT, 0, NULL);
1200         clk_register_clkdev(clk, "pll_m_out1", NULL);
1201         clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1202 
1203         /* PLLM_UD */
1204         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1205                                         CLK_SET_RATE_PARENT, 1, 1);
1206 
1207         /* PLLU */
1208         val = readl(clk_base + pll_u_params.base_reg);
1209         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1210         writel(val, clk_base + pll_u_params.base_reg);
1211 
1212         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1213                             &pll_u_params, &pll_u_lock);
1214         clk_register_clkdev(clk, "pll_u", NULL);
1215         clks[TEGRA124_CLK_PLL_U] = clk;
1216 
1217         tegra124_utmi_param_configure(clk_base);
1218 
1219         /* PLLU_480M */
1220         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1221                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1222                                 22, 0, &pll_u_lock);
1223         clk_register_clkdev(clk, "pll_u_480M", NULL);
1224         clks[TEGRA124_CLK_PLL_U_480M] = clk;
1225 
1226         /* PLLU_60M */
1227         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1228                                         CLK_SET_RATE_PARENT, 1, 8);
1229         clk_register_clkdev(clk, "pll_u_60M", NULL);
1230         clks[TEGRA124_CLK_PLL_U_60M] = clk;
1231 
1232         /* PLLU_48M */
1233         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1234                                         CLK_SET_RATE_PARENT, 1, 10);
1235         clk_register_clkdev(clk, "pll_u_48M", NULL);
1236         clks[TEGRA124_CLK_PLL_U_48M] = clk;
1237 
1238         /* PLLU_12M */
1239         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1240                                         CLK_SET_RATE_PARENT, 1, 40);
1241         clk_register_clkdev(clk, "pll_u_12M", NULL);
1242         clks[TEGRA124_CLK_PLL_U_12M] = clk;
1243 
1244         /* PLLD */
1245         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1246                             &pll_d_params, &pll_d_lock);
1247         clk_register_clkdev(clk, "pll_d", NULL);
1248         clks[TEGRA124_CLK_PLL_D] = clk;
1249 
1250         /* PLLD_OUT0 */
1251         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1252                                         CLK_SET_RATE_PARENT, 1, 2);
1253         clk_register_clkdev(clk, "pll_d_out0", NULL);
1254         clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1255 
1256         /* PLLRE */
1257         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1258                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1259         clk_register_clkdev(clk, "pll_re_vco", NULL);
1260         clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1261 
1262         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1263                                          clk_base + PLLRE_BASE, 16, 4, 0,
1264                                          pll_re_div_table, &pll_re_lock);
1265         clk_register_clkdev(clk, "pll_re_out", NULL);
1266         clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1267 
1268         /* PLLE */
1269         clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1270                                       clk_base, 0, &pll_e_params, NULL);
1271         clk_register_clkdev(clk, "pll_e", NULL);
1272         clks[TEGRA124_CLK_PLL_E] = clk;
1273 
1274         /* PLLC4 */
1275         clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1276                                         &pll_c4_params, NULL);
1277         clk_register_clkdev(clk, "pll_c4", NULL);
1278         clks[TEGRA124_CLK_PLL_C4] = clk;
1279 
1280         /* PLLDP */
1281         clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1282                                         &pll_dp_params, NULL);
1283         clk_register_clkdev(clk, "pll_dp", NULL);
1284         clks[TEGRA124_CLK_PLL_DP] = clk;
1285 
1286         /* PLLD2 */
1287         clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1288                                         &tegra124_pll_d2_params, NULL);
1289         clk_register_clkdev(clk, "pll_d2", NULL);
1290         clks[TEGRA124_CLK_PLL_D2] = clk;
1291 
1292         /* PLLD2_OUT0 */
1293         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1294                                         CLK_SET_RATE_PARENT, 1, 1);
1295         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1296         clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1297 
1298 }
1299 
1300 /* Tegra124 CPU clock and reset control functions */
1301 static void tegra124_wait_cpu_in_reset(u32 cpu)
1302 {
1303         unsigned int reg;
1304 
1305         do {
1306                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1307                 cpu_relax();
1308         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1309 }
1310 
1311 static void tegra124_disable_cpu_clock(u32 cpu)
1312 {
1313         /* flow controller would take care in the power sequence. */
1314 }
1315 
1316 #ifdef CONFIG_PM_SLEEP
1317 static void tegra124_cpu_clock_suspend(void)
1318 {
1319         /* switch coresite to clk_m, save off original source */
1320         tegra124_cpu_clk_sctx.clk_csite_src =
1321                                 readl(clk_base + CLK_SOURCE_CSITE);
1322         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1323 }
1324 
1325 static void tegra124_cpu_clock_resume(void)
1326 {
1327         writel(tegra124_cpu_clk_sctx.clk_csite_src,
1328                                 clk_base + CLK_SOURCE_CSITE);
1329 }
1330 #endif
1331 
1332 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1333         .wait_for_reset = tegra124_wait_cpu_in_reset,
1334         .disable_clock  = tegra124_disable_cpu_clock,
1335 #ifdef CONFIG_PM_SLEEP
1336         .suspend        = tegra124_cpu_clock_suspend,
1337         .resume         = tegra124_cpu_clock_resume,
1338 #endif
1339 };
1340 
1341 static const struct of_device_id pmc_match[] __initconst = {
1342         { .compatible = "nvidia,tegra124-pmc" },
1343         {},
1344 };
1345 
1346 static struct tegra_clk_init_table init_table[] __initdata = {
1347         {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1348         {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1349         {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1350         {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1351         {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1352         {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1353         {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
1354         {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
1355         {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1356         {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1357         {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1358         {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1359         {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1360         {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1361         {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1362         {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1363         {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1364         {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1365         {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1366         {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1367         {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1368         {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1369         {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1370         {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1371         /* This MUST be the last entry. */
1372         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1373 };
1374 
1375 static void __init tegra124_clock_apply_init_table(void)
1376 {
1377         tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX);
1378 }
1379 
1380 static void __init tegra124_clock_init(struct device_node *np)
1381 {
1382         struct device_node *node;
1383 
1384         clk_base = of_iomap(np, 0);
1385         if (!clk_base) {
1386                 pr_err("ioremap tegra124 CAR failed\n");
1387                 return;
1388         }
1389 
1390         node = of_find_matching_node(NULL, pmc_match);
1391         if (!node) {
1392                 pr_err("Failed to find pmc node\n");
1393                 WARN_ON(1);
1394                 return;
1395         }
1396 
1397         pmc_base = of_iomap(node, 0);
1398         if (!pmc_base) {
1399                 pr_err("Can't map pmc registers\n");
1400                 WARN_ON(1);
1401                 return;
1402         }
1403 
1404         clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
1405         if (!clks)
1406                 return;
1407 
1408         if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1409                 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
1410                 return;
1411 
1412         tegra_fixed_clk_init(tegra124_clks);
1413         tegra124_pll_init(clk_base, pmc_base);
1414         tegra124_periph_clk_init(clk_base, pmc_base);
1415         tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1416         tegra_pmc_clk_init(pmc_base, tegra124_clks);
1417 
1418         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1419                                         &pll_x_params);
1420         tegra_add_of_provider(np);
1421         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1422 
1423         tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1424 
1425         tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1426 }
1427 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1428 

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