Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/clk/tegra/clk-tegra124.c

  1 /*
  2  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/clk-provider.h>
 20 #include <linux/clkdev.h>
 21 #include <linux/of.h>
 22 #include <linux/of_address.h>
 23 #include <linux/delay.h>
 24 #include <linux/export.h>
 25 #include <linux/clk/tegra.h>
 26 #include <dt-bindings/clock/tegra124-car.h>
 27 
 28 #include "clk.h"
 29 #include "clk-id.h"
 30 
 31 /*
 32  * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
 33  * banks present in the Tegra124/132 CAR IP block.  The banks are
 34  * identified by single letters, e.g.: L, H, U, V, W, X.  See
 35  * periph_regs[] in drivers/clk/tegra/clk.c
 36  */
 37 #define TEGRA124_CAR_BANK_COUNT                 6
 38 
 39 #define CLK_SOURCE_CSITE 0x1d4
 40 #define CLK_SOURCE_EMC 0x19c
 41 
 42 #define PLLC_BASE 0x80
 43 #define PLLC_OUT 0x84
 44 #define PLLC_MISC2 0x88
 45 #define PLLC_MISC 0x8c
 46 #define PLLC2_BASE 0x4e8
 47 #define PLLC2_MISC 0x4ec
 48 #define PLLC3_BASE 0x4fc
 49 #define PLLC3_MISC 0x500
 50 #define PLLM_BASE 0x90
 51 #define PLLM_OUT 0x94
 52 #define PLLM_MISC 0x9c
 53 #define PLLP_BASE 0xa0
 54 #define PLLP_MISC 0xac
 55 #define PLLA_BASE 0xb0
 56 #define PLLA_MISC 0xbc
 57 #define PLLD_BASE 0xd0
 58 #define PLLD_MISC 0xdc
 59 #define PLLU_BASE 0xc0
 60 #define PLLU_MISC 0xcc
 61 #define PLLX_BASE 0xe0
 62 #define PLLX_MISC 0xe4
 63 #define PLLX_MISC2 0x514
 64 #define PLLX_MISC3 0x518
 65 #define PLLE_BASE 0xe8
 66 #define PLLE_MISC 0xec
 67 #define PLLD2_BASE 0x4b8
 68 #define PLLD2_MISC 0x4bc
 69 #define PLLE_AUX 0x48c
 70 #define PLLRE_BASE 0x4c4
 71 #define PLLRE_MISC 0x4c8
 72 #define PLLDP_BASE 0x590
 73 #define PLLDP_MISC 0x594
 74 #define PLLC4_BASE 0x5a4
 75 #define PLLC4_MISC 0x5a8
 76 
 77 #define PLLC_IDDQ_BIT 26
 78 #define PLLRE_IDDQ_BIT 16
 79 #define PLLSS_IDDQ_BIT 19
 80 
 81 #define PLL_BASE_LOCK BIT(27)
 82 #define PLLE_MISC_LOCK BIT(11)
 83 #define PLLRE_MISC_LOCK BIT(24)
 84 
 85 #define PLL_MISC_LOCK_ENABLE 18
 86 #define PLLC_MISC_LOCK_ENABLE 24
 87 #define PLLDU_MISC_LOCK_ENABLE 22
 88 #define PLLE_MISC_LOCK_ENABLE 9
 89 #define PLLRE_MISC_LOCK_ENABLE 30
 90 #define PLLSS_MISC_LOCK_ENABLE 30
 91 
 92 #define PLLXC_SW_MAX_P 6
 93 
 94 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 95 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 96 
 97 #define UTMIP_PLL_CFG2 0x488
 98 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 99 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
100 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
101 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
102 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
103 
104 #define UTMIP_PLL_CFG1 0x484
105 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
106 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
107 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
108 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
109 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
110 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
111 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
112 
113 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
114 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
115 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
116 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
117 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
118 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
119 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
120 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
121 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
122 
123 /* Tegra CPU clock and reset control regs */
124 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
125 
126 #ifdef CONFIG_PM_SLEEP
127 static struct cpu_clk_suspend_context {
128         u32 clk_csite_src;
129 } tegra124_cpu_clk_sctx;
130 #endif
131 
132 static void __iomem *clk_base;
133 static void __iomem *pmc_base;
134 
135 static unsigned long osc_freq;
136 static unsigned long pll_ref_freq;
137 
138 static DEFINE_SPINLOCK(pll_d_lock);
139 static DEFINE_SPINLOCK(pll_e_lock);
140 static DEFINE_SPINLOCK(pll_re_lock);
141 static DEFINE_SPINLOCK(pll_u_lock);
142 static DEFINE_SPINLOCK(emc_lock);
143 
144 /* possible OSC frequencies in Hz */
145 static unsigned long tegra124_input_freq[] = {
146         [0] = 13000000,
147         [1] = 16800000,
148         [4] = 19200000,
149         [5] = 38400000,
150         [8] = 12000000,
151         [9] = 48000000,
152         [12] = 260000000,
153 };
154 
155 static const char *mux_pllmcp_clkm[] = {
156         "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
157 };
158 #define mux_pllmcp_clkm_idx NULL
159 
160 static struct div_nmp pllxc_nmp = {
161         .divm_shift = 0,
162         .divm_width = 8,
163         .divn_shift = 8,
164         .divn_width = 8,
165         .divp_shift = 20,
166         .divp_width = 4,
167 };
168 
169 static struct pdiv_map pllxc_p[] = {
170         { .pdiv = 1, .hw_val = 0 },
171         { .pdiv = 2, .hw_val = 1 },
172         { .pdiv = 3, .hw_val = 2 },
173         { .pdiv = 4, .hw_val = 3 },
174         { .pdiv = 5, .hw_val = 4 },
175         { .pdiv = 6, .hw_val = 5 },
176         { .pdiv = 8, .hw_val = 6 },
177         { .pdiv = 10, .hw_val = 7 },
178         { .pdiv = 12, .hw_val = 8 },
179         { .pdiv = 16, .hw_val = 9 },
180         { .pdiv = 12, .hw_val = 10 },
181         { .pdiv = 16, .hw_val = 11 },
182         { .pdiv = 20, .hw_val = 12 },
183         { .pdiv = 24, .hw_val = 13 },
184         { .pdiv = 32, .hw_val = 14 },
185         { .pdiv = 0, .hw_val = 0 },
186 };
187 
188 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
189         /* 1 GHz */
190         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
191         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
192         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
193         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
194         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
195         {0, 0, 0, 0, 0, 0},
196 };
197 
198 static struct tegra_clk_pll_params pll_x_params = {
199         .input_min = 12000000,
200         .input_max = 800000000,
201         .cf_min = 12000000,
202         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
203         .vco_min = 700000000,
204         .vco_max = 3000000000UL,
205         .base_reg = PLLX_BASE,
206         .misc_reg = PLLX_MISC,
207         .lock_mask = PLL_BASE_LOCK,
208         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
209         .lock_delay = 300,
210         .iddq_reg = PLLX_MISC3,
211         .iddq_bit_idx = 3,
212         .max_p = 6,
213         .dyn_ramp_reg = PLLX_MISC2,
214         .stepa_shift = 16,
215         .stepb_shift = 24,
216         .pdiv_tohw = pllxc_p,
217         .div_nmp = &pllxc_nmp,
218         .freq_table = pll_x_freq_table,
219         .flags = TEGRA_PLL_USE_LOCK,
220 };
221 
222 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
223         { 12000000, 624000000, 104, 1, 2},
224         { 12000000, 600000000, 100, 1, 2},
225         { 13000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
226         { 16800000, 600000000,  71, 1, 2},      /* actual: 596.4 MHz */
227         { 19200000, 600000000,  62, 1, 2},      /* actual: 595.2 MHz */
228         { 26000000, 600000000,  92, 2, 2},      /* actual: 598.0 MHz */
229         { 0, 0, 0, 0, 0, 0 },
230 };
231 
232 static struct tegra_clk_pll_params pll_c_params = {
233         .input_min = 12000000,
234         .input_max = 800000000,
235         .cf_min = 12000000,
236         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
237         .vco_min = 600000000,
238         .vco_max = 1400000000,
239         .base_reg = PLLC_BASE,
240         .misc_reg = PLLC_MISC,
241         .lock_mask = PLL_BASE_LOCK,
242         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
243         .lock_delay = 300,
244         .iddq_reg = PLLC_MISC,
245         .iddq_bit_idx = PLLC_IDDQ_BIT,
246         .max_p = PLLXC_SW_MAX_P,
247         .dyn_ramp_reg = PLLC_MISC2,
248         .stepa_shift = 17,
249         .stepb_shift = 9,
250         .pdiv_tohw = pllxc_p,
251         .div_nmp = &pllxc_nmp,
252         .freq_table = pll_c_freq_table,
253         .flags = TEGRA_PLL_USE_LOCK,
254 };
255 
256 static struct div_nmp pllcx_nmp = {
257         .divm_shift = 0,
258         .divm_width = 2,
259         .divn_shift = 8,
260         .divn_width = 8,
261         .divp_shift = 20,
262         .divp_width = 3,
263 };
264 
265 static struct pdiv_map pllc_p[] = {
266         { .pdiv = 1, .hw_val = 0 },
267         { .pdiv = 2, .hw_val = 1 },
268         { .pdiv = 3, .hw_val = 2 },
269         { .pdiv = 4, .hw_val = 3 },
270         { .pdiv = 6, .hw_val = 4 },
271         { .pdiv = 8, .hw_val = 5 },
272         { .pdiv = 12, .hw_val = 6 },
273         { .pdiv = 16, .hw_val = 7 },
274         { .pdiv = 0, .hw_val = 0 },
275 };
276 
277 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
278         {12000000, 600000000, 100, 1, 2},
279         {13000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
280         {16800000, 600000000, 71, 1, 2},        /* actual: 596.4 MHz */
281         {19200000, 600000000, 62, 1, 2},        /* actual: 595.2 MHz */
282         {26000000, 600000000, 92, 2, 2},        /* actual: 598.0 MHz */
283         {0, 0, 0, 0, 0, 0},
284 };
285 
286 static struct tegra_clk_pll_params pll_c2_params = {
287         .input_min = 12000000,
288         .input_max = 48000000,
289         .cf_min = 12000000,
290         .cf_max = 19200000,
291         .vco_min = 600000000,
292         .vco_max = 1200000000,
293         .base_reg = PLLC2_BASE,
294         .misc_reg = PLLC2_MISC,
295         .lock_mask = PLL_BASE_LOCK,
296         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
297         .lock_delay = 300,
298         .pdiv_tohw = pllc_p,
299         .div_nmp = &pllcx_nmp,
300         .max_p = 7,
301         .ext_misc_reg[0] = 0x4f0,
302         .ext_misc_reg[1] = 0x4f4,
303         .ext_misc_reg[2] = 0x4f8,
304         .freq_table = pll_cx_freq_table,
305         .flags = TEGRA_PLL_USE_LOCK,
306 };
307 
308 static struct tegra_clk_pll_params pll_c3_params = {
309         .input_min = 12000000,
310         .input_max = 48000000,
311         .cf_min = 12000000,
312         .cf_max = 19200000,
313         .vco_min = 600000000,
314         .vco_max = 1200000000,
315         .base_reg = PLLC3_BASE,
316         .misc_reg = PLLC3_MISC,
317         .lock_mask = PLL_BASE_LOCK,
318         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
319         .lock_delay = 300,
320         .pdiv_tohw = pllc_p,
321         .div_nmp = &pllcx_nmp,
322         .max_p = 7,
323         .ext_misc_reg[0] = 0x504,
324         .ext_misc_reg[1] = 0x508,
325         .ext_misc_reg[2] = 0x50c,
326         .freq_table = pll_cx_freq_table,
327         .flags = TEGRA_PLL_USE_LOCK,
328 };
329 
330 static struct div_nmp pllss_nmp = {
331         .divm_shift = 0,
332         .divm_width = 8,
333         .divn_shift = 8,
334         .divn_width = 8,
335         .divp_shift = 20,
336         .divp_width = 4,
337 };
338 
339 static struct pdiv_map pll12g_ssd_esd_p[] = {
340         { .pdiv = 1, .hw_val = 0 },
341         { .pdiv = 2, .hw_val = 1 },
342         { .pdiv = 3, .hw_val = 2 },
343         { .pdiv = 4, .hw_val = 3 },
344         { .pdiv = 5, .hw_val = 4 },
345         { .pdiv = 6, .hw_val = 5 },
346         { .pdiv = 8, .hw_val = 6 },
347         { .pdiv = 10, .hw_val = 7 },
348         { .pdiv = 12, .hw_val = 8 },
349         { .pdiv = 16, .hw_val = 9 },
350         { .pdiv = 12, .hw_val = 10 },
351         { .pdiv = 16, .hw_val = 11 },
352         { .pdiv = 20, .hw_val = 12 },
353         { .pdiv = 24, .hw_val = 13 },
354         { .pdiv = 32, .hw_val = 14 },
355         { .pdiv = 0, .hw_val = 0 },
356 };
357 
358 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
359         { 12000000, 600000000, 100, 1, 1},
360         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
361         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
362         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
363         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
364         { 0, 0, 0, 0, 0, 0 },
365 };
366 
367 static struct tegra_clk_pll_params pll_c4_params = {
368         .input_min = 12000000,
369         .input_max = 1000000000,
370         .cf_min = 12000000,
371         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
372         .vco_min = 600000000,
373         .vco_max = 1200000000,
374         .base_reg = PLLC4_BASE,
375         .misc_reg = PLLC4_MISC,
376         .lock_mask = PLL_BASE_LOCK,
377         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
378         .lock_delay = 300,
379         .iddq_reg = PLLC4_BASE,
380         .iddq_bit_idx = PLLSS_IDDQ_BIT,
381         .pdiv_tohw = pll12g_ssd_esd_p,
382         .div_nmp = &pllss_nmp,
383         .ext_misc_reg[0] = 0x5ac,
384         .ext_misc_reg[1] = 0x5b0,
385         .ext_misc_reg[2] = 0x5b4,
386         .freq_table = pll_c4_freq_table,
387 };
388 
389 static struct pdiv_map pllm_p[] = {
390         { .pdiv = 1, .hw_val = 0 },
391         { .pdiv = 2, .hw_val = 1 },
392         { .pdiv = 0, .hw_val = 0 },
393 };
394 
395 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
396         {12000000, 800000000, 66, 1, 1},        /* actual: 792.0 MHz */
397         {13000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
398         {16800000, 800000000, 47, 1, 1},        /* actual: 789.6 MHz */
399         {19200000, 800000000, 41, 1, 1},        /* actual: 787.2 MHz */
400         {26000000, 800000000, 61, 2, 1},        /* actual: 793.0 MHz */
401         {0, 0, 0, 0, 0, 0},
402 };
403 
404 static struct div_nmp pllm_nmp = {
405         .divm_shift = 0,
406         .divm_width = 8,
407         .override_divm_shift = 0,
408         .divn_shift = 8,
409         .divn_width = 8,
410         .override_divn_shift = 8,
411         .divp_shift = 20,
412         .divp_width = 1,
413         .override_divp_shift = 27,
414 };
415 
416 static struct tegra_clk_pll_params pll_m_params = {
417         .input_min = 12000000,
418         .input_max = 500000000,
419         .cf_min = 12000000,
420         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
421         .vco_min = 400000000,
422         .vco_max = 1066000000,
423         .base_reg = PLLM_BASE,
424         .misc_reg = PLLM_MISC,
425         .lock_mask = PLL_BASE_LOCK,
426         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
427         .lock_delay = 300,
428         .max_p = 2,
429         .pdiv_tohw = pllm_p,
430         .div_nmp = &pllm_nmp,
431         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
432         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
433         .freq_table = pll_m_freq_table,
434         .flags = TEGRA_PLL_USE_LOCK,
435 };
436 
437 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
438         /* PLLE special case: use cpcon field to store cml divider value */
439         {336000000, 100000000, 100, 21, 16, 11},
440         {312000000, 100000000, 200, 26, 24, 13},
441         {13000000,  100000000, 200, 1,  26, 13},
442         {12000000,  100000000, 200, 1,  24, 13},
443         {0, 0, 0, 0, 0, 0},
444 };
445 
446 static struct div_nmp plle_nmp = {
447         .divm_shift = 0,
448         .divm_width = 8,
449         .divn_shift = 8,
450         .divn_width = 8,
451         .divp_shift = 24,
452         .divp_width = 4,
453 };
454 
455 static struct tegra_clk_pll_params pll_e_params = {
456         .input_min = 12000000,
457         .input_max = 1000000000,
458         .cf_min = 12000000,
459         .cf_max = 75000000,
460         .vco_min = 1600000000,
461         .vco_max = 2400000000U,
462         .base_reg = PLLE_BASE,
463         .misc_reg = PLLE_MISC,
464         .aux_reg = PLLE_AUX,
465         .lock_mask = PLLE_MISC_LOCK,
466         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
467         .lock_delay = 300,
468         .div_nmp = &plle_nmp,
469         .freq_table = pll_e_freq_table,
470         .flags = TEGRA_PLL_FIXED,
471         .fixed_rate = 100000000,
472 };
473 
474 static const struct clk_div_table pll_re_div_table[] = {
475         { .val = 0, .div = 1 },
476         { .val = 1, .div = 2 },
477         { .val = 2, .div = 3 },
478         { .val = 3, .div = 4 },
479         { .val = 4, .div = 5 },
480         { .val = 5, .div = 6 },
481         { .val = 0, .div = 0 },
482 };
483 
484 static struct div_nmp pllre_nmp = {
485         .divm_shift = 0,
486         .divm_width = 8,
487         .divn_shift = 8,
488         .divn_width = 8,
489         .divp_shift = 16,
490         .divp_width = 4,
491 };
492 
493 static struct tegra_clk_pll_params pll_re_vco_params = {
494         .input_min = 12000000,
495         .input_max = 1000000000,
496         .cf_min = 12000000,
497         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
498         .vco_min = 300000000,
499         .vco_max = 600000000,
500         .base_reg = PLLRE_BASE,
501         .misc_reg = PLLRE_MISC,
502         .lock_mask = PLLRE_MISC_LOCK,
503         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
504         .lock_delay = 300,
505         .iddq_reg = PLLRE_MISC,
506         .iddq_bit_idx = PLLRE_IDDQ_BIT,
507         .div_nmp = &pllre_nmp,
508         .flags = TEGRA_PLL_USE_LOCK,
509 };
510 
511 static struct div_nmp pllp_nmp = {
512         .divm_shift = 0,
513         .divm_width = 5,
514         .divn_shift = 8,
515         .divn_width = 10,
516         .divp_shift = 20,
517         .divp_width = 3,
518 };
519 
520 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
521         {12000000, 408000000, 408, 12, 0, 8},
522         {13000000, 408000000, 408, 13, 0, 8},
523         {16800000, 408000000, 340, 14, 0, 8},
524         {19200000, 408000000, 340, 16, 0, 8},
525         {26000000, 408000000, 408, 26, 0, 8},
526         {0, 0, 0, 0, 0, 0},
527 };
528 
529 static struct tegra_clk_pll_params pll_p_params = {
530         .input_min = 2000000,
531         .input_max = 31000000,
532         .cf_min = 1000000,
533         .cf_max = 6000000,
534         .vco_min = 200000000,
535         .vco_max = 700000000,
536         .base_reg = PLLP_BASE,
537         .misc_reg = PLLP_MISC,
538         .lock_mask = PLL_BASE_LOCK,
539         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
540         .lock_delay = 300,
541         .div_nmp = &pllp_nmp,
542         .freq_table = pll_p_freq_table,
543         .fixed_rate = 408000000,
544         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
545 };
546 
547 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
548         {9600000, 282240000, 147, 5, 0, 4},
549         {9600000, 368640000, 192, 5, 0, 4},
550         {9600000, 240000000, 200, 8, 0, 8},
551 
552         {28800000, 282240000, 245, 25, 0, 8},
553         {28800000, 368640000, 320, 25, 0, 8},
554         {28800000, 240000000, 200, 24, 0, 8},
555         {0, 0, 0, 0, 0, 0},
556 };
557 
558 static struct tegra_clk_pll_params pll_a_params = {
559         .input_min = 2000000,
560         .input_max = 31000000,
561         .cf_min = 1000000,
562         .cf_max = 6000000,
563         .vco_min = 200000000,
564         .vco_max = 700000000,
565         .base_reg = PLLA_BASE,
566         .misc_reg = PLLA_MISC,
567         .lock_mask = PLL_BASE_LOCK,
568         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
569         .lock_delay = 300,
570         .div_nmp = &pllp_nmp,
571         .freq_table = pll_a_freq_table,
572         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
573 };
574 
575 static struct div_nmp plld_nmp = {
576         .divm_shift = 0,
577         .divm_width = 5,
578         .divn_shift = 8,
579         .divn_width = 11,
580         .divp_shift = 20,
581         .divp_width = 3,
582 };
583 
584 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
585         {12000000, 216000000, 864, 12, 4, 12},
586         {13000000, 216000000, 864, 13, 4, 12},
587         {16800000, 216000000, 720, 14, 4, 12},
588         {19200000, 216000000, 720, 16, 4, 12},
589         {26000000, 216000000, 864, 26, 4, 12},
590 
591         {12000000, 594000000, 594, 12, 1, 12},
592         {13000000, 594000000, 594, 13, 1, 12},
593         {16800000, 594000000, 495, 14, 1, 12},
594         {19200000, 594000000, 495, 16, 1, 12},
595         {26000000, 594000000, 594, 26, 1, 12},
596 
597         {12000000, 1000000000, 1000, 12, 1, 12},
598         {13000000, 1000000000, 1000, 13, 1, 12},
599         {19200000, 1000000000, 625, 12, 1, 12},
600         {26000000, 1000000000, 1000, 26, 1, 12},
601 
602         {0, 0, 0, 0, 0, 0},
603 };
604 
605 static struct tegra_clk_pll_params pll_d_params = {
606         .input_min = 2000000,
607         .input_max = 40000000,
608         .cf_min = 1000000,
609         .cf_max = 6000000,
610         .vco_min = 500000000,
611         .vco_max = 1000000000,
612         .base_reg = PLLD_BASE,
613         .misc_reg = PLLD_MISC,
614         .lock_mask = PLL_BASE_LOCK,
615         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
616         .lock_delay = 1000,
617         .div_nmp = &plld_nmp,
618         .freq_table = pll_d_freq_table,
619         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
620                  TEGRA_PLL_USE_LOCK,
621 };
622 
623 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
624         { 12000000, 594000000,  99, 1, 2},
625         { 13000000, 594000000,  91, 1, 2},      /* actual: 591.5 MHz */
626         { 16800000, 594000000,  71, 1, 2},      /* actual: 596.4 MHz */
627         { 19200000, 594000000,  62, 1, 2},      /* actual: 595.2 MHz */
628         { 26000000, 594000000,  91, 2, 2},      /* actual: 591.5 MHz */
629         { 0, 0, 0, 0, 0, 0 },
630 };
631 
632 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
633         .input_min = 12000000,
634         .input_max = 1000000000,
635         .cf_min = 12000000,
636         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
637         .vco_min = 600000000,
638         .vco_max = 1200000000,
639         .base_reg = PLLD2_BASE,
640         .misc_reg = PLLD2_MISC,
641         .lock_mask = PLL_BASE_LOCK,
642         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
643         .lock_delay = 300,
644         .iddq_reg = PLLD2_BASE,
645         .iddq_bit_idx = PLLSS_IDDQ_BIT,
646         .pdiv_tohw = pll12g_ssd_esd_p,
647         .div_nmp = &pllss_nmp,
648         .ext_misc_reg[0] = 0x570,
649         .ext_misc_reg[1] = 0x574,
650         .ext_misc_reg[2] = 0x578,
651         .max_p = 15,
652         .freq_table = tegra124_pll_d2_freq_table,
653 };
654 
655 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
656         { 12000000, 600000000, 100, 1, 1},
657         { 13000000, 600000000,  92, 1, 1},      /* actual: 598.0 MHz */
658         { 16800000, 600000000,  71, 1, 1},      /* actual: 596.4 MHz */
659         { 19200000, 600000000,  62, 1, 1},      /* actual: 595.2 MHz */
660         { 26000000, 600000000,  92, 2, 1},      /* actual: 598.0 MHz */
661         { 0, 0, 0, 0, 0, 0 },
662 };
663 
664 static struct tegra_clk_pll_params pll_dp_params = {
665         .input_min = 12000000,
666         .input_max = 1000000000,
667         .cf_min = 12000000,
668         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
669         .vco_min = 600000000,
670         .vco_max = 1200000000,
671         .base_reg = PLLDP_BASE,
672         .misc_reg = PLLDP_MISC,
673         .lock_mask = PLL_BASE_LOCK,
674         .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
675         .lock_delay = 300,
676         .iddq_reg = PLLDP_BASE,
677         .iddq_bit_idx = PLLSS_IDDQ_BIT,
678         .pdiv_tohw = pll12g_ssd_esd_p,
679         .div_nmp = &pllss_nmp,
680         .ext_misc_reg[0] = 0x598,
681         .ext_misc_reg[1] = 0x59c,
682         .ext_misc_reg[2] = 0x5a0,
683         .max_p = 5,
684         .freq_table = pll_dp_freq_table,
685 };
686 
687 static struct pdiv_map pllu_p[] = {
688         { .pdiv = 1, .hw_val = 1 },
689         { .pdiv = 2, .hw_val = 0 },
690         { .pdiv = 0, .hw_val = 0 },
691 };
692 
693 static struct div_nmp pllu_nmp = {
694         .divm_shift = 0,
695         .divm_width = 5,
696         .divn_shift = 8,
697         .divn_width = 10,
698         .divp_shift = 20,
699         .divp_width = 1,
700 };
701 
702 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
703         {12000000, 480000000, 960, 12, 2, 12},
704         {13000000, 480000000, 960, 13, 2, 12},
705         {16800000, 480000000, 400, 7, 2, 5},
706         {19200000, 480000000, 200, 4, 2, 3},
707         {26000000, 480000000, 960, 26, 2, 12},
708         {0, 0, 0, 0, 0, 0},
709 };
710 
711 static struct tegra_clk_pll_params pll_u_params = {
712         .input_min = 2000000,
713         .input_max = 40000000,
714         .cf_min = 1000000,
715         .cf_max = 6000000,
716         .vco_min = 480000000,
717         .vco_max = 960000000,
718         .base_reg = PLLU_BASE,
719         .misc_reg = PLLU_MISC,
720         .lock_mask = PLL_BASE_LOCK,
721         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
722         .lock_delay = 1000,
723         .pdiv_tohw = pllu_p,
724         .div_nmp = &pllu_nmp,
725         .freq_table = pll_u_freq_table,
726         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
727                  TEGRA_PLL_USE_LOCK,
728 };
729 
730 struct utmi_clk_param {
731         /* Oscillator Frequency in KHz */
732         u32 osc_frequency;
733         /* UTMIP PLL Enable Delay Count  */
734         u8 enable_delay_count;
735         /* UTMIP PLL Stable count */
736         u8 stable_count;
737         /*  UTMIP PLL Active delay count */
738         u8 active_delay_count;
739         /* UTMIP PLL Xtal frequency count */
740         u8 xtal_freq_count;
741 };
742 
743 static const struct utmi_clk_param utmi_parameters[] = {
744         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
745          .stable_count = 0x33, .active_delay_count = 0x05,
746          .xtal_freq_count = 0x7F},
747         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
748          .stable_count = 0x4B, .active_delay_count = 0x06,
749          .xtal_freq_count = 0xBB},
750         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
751          .stable_count = 0x2F, .active_delay_count = 0x04,
752          .xtal_freq_count = 0x76},
753         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
754          .stable_count = 0x66, .active_delay_count = 0x09,
755          .xtal_freq_count = 0xFE},
756         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
757          .stable_count = 0x41, .active_delay_count = 0x0A,
758          .xtal_freq_count = 0xA4},
759 };
760 
761 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
762         [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
763         [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
764         [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
765         [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
766         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
767         [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
768         [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
769         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
770         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
771         [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
772         [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
773         [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
774         [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
775         [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
776         [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
777         [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
778         [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
779         [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
780         [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
781         [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
782         [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
783         [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
784         [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
785         [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
786         [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
787         [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
788         [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
789         [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
790         [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
791         [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
792         [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
793         [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
794         [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
795         [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
796         [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
797         [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
798         [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
799         [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
800         [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
801         [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
802         [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
803         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
804         [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
805         [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
806         [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
807         [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
808         [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
809         [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
810         [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
811         [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
812         [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
813         [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
814         [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
815         [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
816         [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
817         [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
818         [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
819         [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
820         [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
821         [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
822         [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
823         [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
824         [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
825         [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
826         [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
827         [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
828         [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
829         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
830         [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
831         [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
832         [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
833         [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
834         [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
835         [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
836         [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
837         [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
838         [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
839         [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
840         [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
841         [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
842         [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
843         [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
844         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
845         [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
846         [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
847         [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
848         [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
849         [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
850         [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
851         [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
852         [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
853         [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
854         [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
855         [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
856         [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
857         [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
858         [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
859         [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
860         [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
861         [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
862         [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
863         [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
864         [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
865         [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
866         [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
867         [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
868         [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
869         [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
870         [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
871         [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
872         [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
873         [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
874         [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
875         [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
876         [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
877         [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
878         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
879         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
880         [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
881         [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
882         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
883         [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
884         [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
885         [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
886         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
887         [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
888         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
889         [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
890         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
891         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
892         [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
893         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
894         [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
895         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
896         [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
897         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
898         [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
899         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
900         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
901         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
902         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
903         [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
904         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
905         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
906         [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
907         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
908         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
909         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
910         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
911         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
912         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
913         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
914         [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
915         [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
916         [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
917         [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
918         [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
919         [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
920         [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
921         [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
922         [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
923         [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
924         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
925         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
926         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
927         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
928         [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
929         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
930         [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
931         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
932         [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
933         [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
934         [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
935         [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
936         [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
937         [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
938         [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
939         [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
940         [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
941         [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
942         [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
943         [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
944         [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
945         [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
946         [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
947         [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
948         [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
949         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
950         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
951         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
952 };
953 
954 static struct tegra_devclk devclks[] __initdata = {
955         { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
956         { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
957         { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
958         { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
959         { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
960         { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
961         { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
962         { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
963         { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
964         { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
965         { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
966         { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
967         { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
968         { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
969         { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
970         { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
971         { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
972         { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
973         { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
974         { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
975         { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
976         { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
977         { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
978         { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
979         { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
980         { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
981         { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
982         { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
983         { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
984         { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
985         { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
986         { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
987         { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
988         { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
989         { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
990         { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
991         { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
992         { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
993         { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
994         { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
995         { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
996         { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
997         { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
998         { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
999         { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
1000         { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
1001         { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
1002         { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
1003         { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
1004         { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
1005         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1006         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1007         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1008         { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1009         { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1010         { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1011         { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1012         { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1013         { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1014         { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1015         { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1016         { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1017 };
1018 
1019 static struct clk **clks;
1020 
1021 static void tegra124_utmi_param_configure(void __iomem *clk_base)
1022 {
1023         u32 reg;
1024         int i;
1025 
1026         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1027                 if (osc_freq == utmi_parameters[i].osc_frequency)
1028                         break;
1029         }
1030 
1031         if (i >= ARRAY_SIZE(utmi_parameters)) {
1032                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1033                        osc_freq);
1034                 return;
1035         }
1036 
1037         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1038 
1039         /* Program UTMIP PLL stable and active counts */
1040         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1041         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1042         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1043 
1044         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1045 
1046         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1047                                             active_delay_count);
1048 
1049         /* Remove power downs from UTMIP PLL control bits */
1050         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1051         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1052         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1053 
1054         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1055 
1056         /* Program UTMIP PLL delay and oscillator frequency counts */
1057         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1058         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1059 
1060         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1061                                             enable_delay_count);
1062 
1063         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1064         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1065                                            xtal_freq_count);
1066 
1067         /* Remove power downs from UTMIP PLL control bits */
1068         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1069         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1070         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1071         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1072         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1073 
1074         /* Setup HW control of UTMIPLL */
1075         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1076         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1077         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1078         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1079         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1080 
1081         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1082         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1083         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1084         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1085 
1086         udelay(1);
1087 
1088         /* Setup SW override of UTMIPLL assuming USB2.0
1089            ports are assigned to USB2 */
1090         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1091         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1092         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1093         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1094 
1095         udelay(1);
1096 
1097         /* Enable HW control UTMIPLL */
1098         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1099         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1100         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1101 }
1102 
1103 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1104                                             void __iomem *pmc_base)
1105 {
1106         struct clk *clk;
1107 
1108         /* xusb_ss_div2 */
1109         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1110                                         1, 2);
1111         clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1112 
1113         clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
1114                                 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1115         clks[TEGRA124_CLK_PLLD_DSI] = clk;
1116 
1117         clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
1118                                              0, 48, periph_clk_enb_refcnt);
1119         clks[TEGRA124_CLK_DSIA] = clk;
1120 
1121         clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
1122                                              0, 82, periph_clk_enb_refcnt);
1123         clks[TEGRA124_CLK_DSIB] = clk;
1124 
1125         /* emc mux */
1126         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1127                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
1128                                clk_base + CLK_SOURCE_EMC,
1129                                29, 3, 0, &emc_lock);
1130 
1131         clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1132                                     &emc_lock);
1133         clks[TEGRA124_CLK_MC] = clk;
1134 
1135         /* cml0 */
1136         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1137                                 0, 0, &pll_e_lock);
1138         clk_register_clkdev(clk, "cml0", NULL);
1139         clks[TEGRA124_CLK_CML0] = clk;
1140 
1141         /* cml1 */
1142         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1143                                 1, 0, &pll_e_lock);
1144         clk_register_clkdev(clk, "cml1", NULL);
1145         clks[TEGRA124_CLK_CML1] = clk;
1146 
1147         tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1148 }
1149 
1150 static void __init tegra124_pll_init(void __iomem *clk_base,
1151                                      void __iomem *pmc)
1152 {
1153         u32 val;
1154         struct clk *clk;
1155 
1156         /* PLLC */
1157         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1158                         pmc, 0, &pll_c_params, NULL);
1159         clk_register_clkdev(clk, "pll_c", NULL);
1160         clks[TEGRA124_CLK_PLL_C] = clk;
1161 
1162         /* PLLC_OUT1 */
1163         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1164                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1165                         8, 8, 1, NULL);
1166         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1167                                 clk_base + PLLC_OUT, 1, 0,
1168                                 CLK_SET_RATE_PARENT, 0, NULL);
1169         clk_register_clkdev(clk, "pll_c_out1", NULL);
1170         clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1171 
1172         /* PLLC_UD */
1173         clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
1174                                         CLK_SET_RATE_PARENT, 1, 1);
1175         clk_register_clkdev(clk, "pll_c_ud", NULL);
1176         clks[TEGRA124_CLK_PLL_C_UD] = clk;
1177 
1178         /* PLLC2 */
1179         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1180                              &pll_c2_params, NULL);
1181         clk_register_clkdev(clk, "pll_c2", NULL);
1182         clks[TEGRA124_CLK_PLL_C2] = clk;
1183 
1184         /* PLLC3 */
1185         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1186                              &pll_c3_params, NULL);
1187         clk_register_clkdev(clk, "pll_c3", NULL);
1188         clks[TEGRA124_CLK_PLL_C3] = clk;
1189 
1190         /* PLLM */
1191         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1192                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1193                              &pll_m_params, NULL);
1194         clk_register_clkdev(clk, "pll_m", NULL);
1195         clks[TEGRA124_CLK_PLL_M] = clk;
1196 
1197         /* PLLM_OUT1 */
1198         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1199                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1200                                 8, 8, 1, NULL);
1201         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1202                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1203                                 CLK_SET_RATE_PARENT, 0, NULL);
1204         clk_register_clkdev(clk, "pll_m_out1", NULL);
1205         clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1206 
1207         /* PLLM_UD */
1208         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1209                                         CLK_SET_RATE_PARENT, 1, 1);
1210         clk_register_clkdev(clk, "pll_m_ud", NULL);
1211         clks[TEGRA124_CLK_PLL_M_UD] = clk;
1212 
1213         /* PLLU */
1214         val = readl(clk_base + pll_u_params.base_reg);
1215         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1216         writel(val, clk_base + pll_u_params.base_reg);
1217 
1218         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1219                             &pll_u_params, &pll_u_lock);
1220         clk_register_clkdev(clk, "pll_u", NULL);
1221         clks[TEGRA124_CLK_PLL_U] = clk;
1222 
1223         tegra124_utmi_param_configure(clk_base);
1224 
1225         /* PLLU_480M */
1226         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1227                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1228                                 22, 0, &pll_u_lock);
1229         clk_register_clkdev(clk, "pll_u_480M", NULL);
1230         clks[TEGRA124_CLK_PLL_U_480M] = clk;
1231 
1232         /* PLLU_60M */
1233         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1234                                         CLK_SET_RATE_PARENT, 1, 8);
1235         clk_register_clkdev(clk, "pll_u_60M", NULL);
1236         clks[TEGRA124_CLK_PLL_U_60M] = clk;
1237 
1238         /* PLLU_48M */
1239         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1240                                         CLK_SET_RATE_PARENT, 1, 10);
1241         clk_register_clkdev(clk, "pll_u_48M", NULL);
1242         clks[TEGRA124_CLK_PLL_U_48M] = clk;
1243 
1244         /* PLLU_12M */
1245         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1246                                         CLK_SET_RATE_PARENT, 1, 40);
1247         clk_register_clkdev(clk, "pll_u_12M", NULL);
1248         clks[TEGRA124_CLK_PLL_U_12M] = clk;
1249 
1250         /* PLLD */
1251         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1252                             &pll_d_params, &pll_d_lock);
1253         clk_register_clkdev(clk, "pll_d", NULL);
1254         clks[TEGRA124_CLK_PLL_D] = clk;
1255 
1256         /* PLLD_OUT0 */
1257         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1258                                         CLK_SET_RATE_PARENT, 1, 2);
1259         clk_register_clkdev(clk, "pll_d_out0", NULL);
1260         clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1261 
1262         /* PLLRE */
1263         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1264                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1265         clk_register_clkdev(clk, "pll_re_vco", NULL);
1266         clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1267 
1268         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1269                                          clk_base + PLLRE_BASE, 16, 4, 0,
1270                                          pll_re_div_table, &pll_re_lock);
1271         clk_register_clkdev(clk, "pll_re_out", NULL);
1272         clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1273 
1274         /* PLLE */
1275         clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1276                                       clk_base, 0, &pll_e_params, NULL);
1277         clk_register_clkdev(clk, "pll_e", NULL);
1278         clks[TEGRA124_CLK_PLL_E] = clk;
1279 
1280         /* PLLC4 */
1281         clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1282                                         &pll_c4_params, NULL);
1283         clk_register_clkdev(clk, "pll_c4", NULL);
1284         clks[TEGRA124_CLK_PLL_C4] = clk;
1285 
1286         /* PLLDP */
1287         clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1288                                         &pll_dp_params, NULL);
1289         clk_register_clkdev(clk, "pll_dp", NULL);
1290         clks[TEGRA124_CLK_PLL_DP] = clk;
1291 
1292         /* PLLD2 */
1293         clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1294                                         &tegra124_pll_d2_params, NULL);
1295         clk_register_clkdev(clk, "pll_d2", NULL);
1296         clks[TEGRA124_CLK_PLL_D2] = clk;
1297 
1298         /* PLLD2_OUT0 */
1299         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1300                                         CLK_SET_RATE_PARENT, 1, 1);
1301         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1302         clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1303 
1304 }
1305 
1306 /* Tegra124 CPU clock and reset control functions */
1307 static void tegra124_wait_cpu_in_reset(u32 cpu)
1308 {
1309         unsigned int reg;
1310 
1311         do {
1312                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1313                 cpu_relax();
1314         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1315 }
1316 
1317 static void tegra124_disable_cpu_clock(u32 cpu)
1318 {
1319         /* flow controller would take care in the power sequence. */
1320 }
1321 
1322 #ifdef CONFIG_PM_SLEEP
1323 static void tegra124_cpu_clock_suspend(void)
1324 {
1325         /* switch coresite to clk_m, save off original source */
1326         tegra124_cpu_clk_sctx.clk_csite_src =
1327                                 readl(clk_base + CLK_SOURCE_CSITE);
1328         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1329 }
1330 
1331 static void tegra124_cpu_clock_resume(void)
1332 {
1333         writel(tegra124_cpu_clk_sctx.clk_csite_src,
1334                                 clk_base + CLK_SOURCE_CSITE);
1335 }
1336 #endif
1337 
1338 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1339         .wait_for_reset = tegra124_wait_cpu_in_reset,
1340         .disable_clock  = tegra124_disable_cpu_clock,
1341 #ifdef CONFIG_PM_SLEEP
1342         .suspend        = tegra124_cpu_clock_suspend,
1343         .resume         = tegra124_cpu_clock_resume,
1344 #endif
1345 };
1346 
1347 static const struct of_device_id pmc_match[] __initconst = {
1348         { .compatible = "nvidia,tegra124-pmc" },
1349         {},
1350 };
1351 
1352 static struct tegra_clk_init_table common_init_table[] __initdata = {
1353         {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1354         {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1355         {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1356         {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1357         {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1358         {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1359         {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
1360         {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
1361         {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1362         {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1363         {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1364         {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1365         {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1366         {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1367         {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1368         {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1369         {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
1370         {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
1371         {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1372         {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1373         {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1374         {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1375         {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1376         {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1377         {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1378         {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1379         {TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
1380         {TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0},
1381         {TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0},
1382         {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
1383         {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
1384         {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
1385         {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1386         {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1387         {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
1388         {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1389         {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1390         {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
1391         /* This MUST be the last entry. */
1392         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1393 };
1394 
1395 static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1396         {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1397         {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1398         /* This MUST be the last entry. */
1399         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1400 };
1401 
1402 /* Tegra132 requires the SOC_THERM clock to remain active */
1403 static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1404         {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
1405         /* This MUST be the last entry. */
1406         {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1407 };
1408 
1409 /**
1410  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1411  *
1412  * Program an initial clock rate and enable or disable clocks needed
1413  * by the rest of the kernel, for Tegra124 SoCs.  It is intended to be
1414  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1415  * this will be called as an arch_initcall.  No return value.
1416  */
1417 static void __init tegra124_clock_apply_init_table(void)
1418 {
1419         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1420         tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1421 }
1422 
1423 /**
1424  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1425  *
1426  * Program an initial clock rate and enable or disable clocks needed
1427  * by the rest of the kernel, for Tegra132 SoCs.  It is intended to be
1428  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1429  * this will be called as an arch_initcall.  No return value.
1430  */
1431 static void __init tegra132_clock_apply_init_table(void)
1432 {
1433         tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1434         tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1435 }
1436 
1437 /**
1438  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1439  * @np: struct device_node * of the DT node for the SoC CAR IP block
1440  *
1441  * Register most of the clocks controlled by the CAR IP block, along
1442  * with a few clocks controlled by the PMC IP block.  Everything in
1443  * this function should be common to Tegra124 and Tegra132.  XXX The
1444  * PMC clock initialization should probably be moved to PMC-specific
1445  * driver code.  No return value.
1446  */
1447 static void __init tegra124_132_clock_init_pre(struct device_node *np)
1448 {
1449         struct device_node *node;
1450         u32 plld_base;
1451 
1452         clk_base = of_iomap(np, 0);
1453         if (!clk_base) {
1454                 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1455                 return;
1456         }
1457 
1458         node = of_find_matching_node(NULL, pmc_match);
1459         if (!node) {
1460                 pr_err("Failed to find pmc node\n");
1461                 WARN_ON(1);
1462                 return;
1463         }
1464 
1465         pmc_base = of_iomap(node, 0);
1466         if (!pmc_base) {
1467                 pr_err("Can't map pmc registers\n");
1468                 WARN_ON(1);
1469                 return;
1470         }
1471 
1472         clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1473                               TEGRA124_CAR_BANK_COUNT);
1474         if (!clks)
1475                 return;
1476 
1477         if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1478                 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
1479                 return;
1480 
1481         tegra_fixed_clk_init(tegra124_clks);
1482         tegra124_pll_init(clk_base, pmc_base);
1483         tegra124_periph_clk_init(clk_base, pmc_base);
1484         tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1485         tegra_pmc_clk_init(pmc_base, tegra124_clks);
1486 
1487         /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1488         plld_base = clk_readl(clk_base + PLLD_BASE);
1489         plld_base &= ~BIT(25);
1490         clk_writel(plld_base, clk_base + PLLD_BASE);
1491 }
1492 
1493 /**
1494  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1495  * @np: struct device_node * of the DT node for the SoC CAR IP block
1496  *
1497  * Register most of the along with a few clocks controlled by the PMC
1498  * IP block.  Everything in this function should be common to Tegra124
1499  * and Tegra132.  This function must be called after
1500  * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1501  * not be set.  No return value.
1502  */
1503 static void __init tegra124_132_clock_init_post(struct device_node *np)
1504 {
1505         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1506                                   &pll_x_params);
1507         tegra_add_of_provider(np);
1508         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1509 
1510         tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1511 }
1512 
1513 /**
1514  * tegra124_clock_init - Tegra124-specific clock initialization
1515  * @np: struct device_node * of the DT node for the SoC CAR IP block
1516  *
1517  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1518  * this code is shared between the Tegra124 and Tegra132 SoCs,
1519  * although some of the initial clock settings and CPU clocks differ.
1520  * Intended to be called by the OF init code when a DT node with the
1521  * "nvidia,tegra124-car" string is encountered, and declared with
1522  * CLK_OF_DECLARE.  No return value.
1523  */
1524 static void __init tegra124_clock_init(struct device_node *np)
1525 {
1526         tegra124_132_clock_init_pre(np);
1527         tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1528         tegra124_132_clock_init_post(np);
1529 }
1530 
1531 /**
1532  * tegra132_clock_init - Tegra132-specific clock initialization
1533  * @np: struct device_node * of the DT node for the SoC CAR IP block
1534  *
1535  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1536  * this code is shared between the Tegra124 and Tegra132 SoCs,
1537  * although some of the initial clock settings and CPU clocks differ.
1538  * Intended to be called by the OF init code when a DT node with the
1539  * "nvidia,tegra132-car" string is encountered, and declared with
1540  * CLK_OF_DECLARE.  No return value.
1541  */
1542 static void __init tegra132_clock_init(struct device_node *np)
1543 {
1544         tegra124_132_clock_init_pre(np);
1545 
1546         /*
1547          * On Tegra132, these clocks are controlled by the
1548          * CLUSTER_clocks IP block, located in the CPU complex
1549          */
1550         tegra124_clks[tegra_clk_cclk_g].present = false;
1551         tegra124_clks[tegra_clk_cclk_lp].present = false;
1552         tegra124_clks[tegra_clk_pll_x].present = false;
1553         tegra124_clks[tegra_clk_pll_x_out0].present = false;
1554 
1555         tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1556         tegra124_132_clock_init_post(np);
1557 }
1558 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1559 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
1560 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us