Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/clk/tegra/clk-tegra114.c

  1 /*
  2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk.h>
 19 #include <linux/clk-provider.h>
 20 #include <linux/clkdev.h>
 21 #include <linux/of.h>
 22 #include <linux/of_address.h>
 23 #include <linux/delay.h>
 24 #include <linux/export.h>
 25 #include <linux/clk/tegra.h>
 26 #include <dt-bindings/clock/tegra114-car.h>
 27 
 28 #include "clk.h"
 29 #include "clk-id.h"
 30 
 31 #define RST_DFLL_DVCO                   0x2F4
 32 #define CPU_FINETRIM_SELECT             0x4d4   /* override default prop dlys */
 33 #define CPU_FINETRIM_DR                 0x4d8   /* rise->rise prop dly A */
 34 #define CPU_FINETRIM_R                  0x4e4   /* rise->rise prop dly inc A */
 35 
 36 /* RST_DFLL_DVCO bitfields */
 37 #define DVFS_DFLL_RESET_SHIFT           0
 38 
 39 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
 40 #define CPU_FINETRIM_1_FCPU_1           BIT(0)  /* fcpu0 */
 41 #define CPU_FINETRIM_1_FCPU_2           BIT(1)  /* fcpu1 */
 42 #define CPU_FINETRIM_1_FCPU_3           BIT(2)  /* fcpu2 */
 43 #define CPU_FINETRIM_1_FCPU_4           BIT(3)  /* fcpu3 */
 44 #define CPU_FINETRIM_1_FCPU_5           BIT(4)  /* fl2 */
 45 #define CPU_FINETRIM_1_FCPU_6           BIT(5)  /* ftop */
 46 
 47 /* CPU_FINETRIM_R bitfields */
 48 #define CPU_FINETRIM_R_FCPU_1_SHIFT     0               /* fcpu0 */
 49 #define CPU_FINETRIM_R_FCPU_1_MASK      (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
 50 #define CPU_FINETRIM_R_FCPU_2_SHIFT     2               /* fcpu1 */
 51 #define CPU_FINETRIM_R_FCPU_2_MASK      (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
 52 #define CPU_FINETRIM_R_FCPU_3_SHIFT     4               /* fcpu2 */
 53 #define CPU_FINETRIM_R_FCPU_3_MASK      (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
 54 #define CPU_FINETRIM_R_FCPU_4_SHIFT     6               /* fcpu3 */
 55 #define CPU_FINETRIM_R_FCPU_4_MASK      (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
 56 #define CPU_FINETRIM_R_FCPU_5_SHIFT     8               /* fl2 */
 57 #define CPU_FINETRIM_R_FCPU_5_MASK      (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
 58 #define CPU_FINETRIM_R_FCPU_6_SHIFT     10              /* ftop */
 59 #define CPU_FINETRIM_R_FCPU_6_MASK      (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
 60 
 61 #define TEGRA114_CLK_PERIPH_BANKS       5
 62 
 63 #define PLLC_BASE 0x80
 64 #define PLLC_MISC2 0x88
 65 #define PLLC_MISC 0x8c
 66 #define PLLC2_BASE 0x4e8
 67 #define PLLC2_MISC 0x4ec
 68 #define PLLC3_BASE 0x4fc
 69 #define PLLC3_MISC 0x500
 70 #define PLLM_BASE 0x90
 71 #define PLLM_MISC 0x9c
 72 #define PLLP_BASE 0xa0
 73 #define PLLP_MISC 0xac
 74 #define PLLX_BASE 0xe0
 75 #define PLLX_MISC 0xe4
 76 #define PLLX_MISC2 0x514
 77 #define PLLX_MISC3 0x518
 78 #define PLLD_BASE 0xd0
 79 #define PLLD_MISC 0xdc
 80 #define PLLD2_BASE 0x4b8
 81 #define PLLD2_MISC 0x4bc
 82 #define PLLE_BASE 0xe8
 83 #define PLLE_MISC 0xec
 84 #define PLLA_BASE 0xb0
 85 #define PLLA_MISC 0xbc
 86 #define PLLU_BASE 0xc0
 87 #define PLLU_MISC 0xcc
 88 #define PLLRE_BASE 0x4c4
 89 #define PLLRE_MISC 0x4c8
 90 
 91 #define PLL_MISC_LOCK_ENABLE 18
 92 #define PLLC_MISC_LOCK_ENABLE 24
 93 #define PLLDU_MISC_LOCK_ENABLE 22
 94 #define PLLE_MISC_LOCK_ENABLE 9
 95 #define PLLRE_MISC_LOCK_ENABLE 30
 96 
 97 #define PLLC_IDDQ_BIT 26
 98 #define PLLX_IDDQ_BIT 3
 99 #define PLLRE_IDDQ_BIT 16
100 
101 #define PLL_BASE_LOCK BIT(27)
102 #define PLLE_MISC_LOCK BIT(11)
103 #define PLLRE_MISC_LOCK BIT(24)
104 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
105 
106 #define PLLE_AUX 0x48c
107 #define PLLC_OUT 0x84
108 #define PLLM_OUT 0x94
109 
110 #define OSC_CTRL                        0x50
111 #define OSC_CTRL_OSC_FREQ_SHIFT         28
112 #define OSC_CTRL_PLL_REF_DIV_SHIFT      26
113 
114 #define PLLXC_SW_MAX_P                  6
115 
116 #define CCLKG_BURST_POLICY 0x368
117 
118 #define UTMIP_PLL_CFG2 0x488
119 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
120 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
121 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
122 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
123 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
124 
125 #define UTMIP_PLL_CFG1 0x484
126 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
127 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
128 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
129 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
130 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
131 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133 
134 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
135 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
136 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
137 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
138 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
139 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
140 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
141 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
142 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
143 
144 #define CLK_SOURCE_CSITE 0x1d4
145 #define CLK_SOURCE_EMC 0x19c
146 
147 /* PLLM override registers */
148 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
149 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
150 
151 /* Tegra CPU clock and reset control regs */
152 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
153 
154 #define MUX8(_name, _parents, _offset, \
155                              _clk_num, _gate_flags, _clk_id)    \
156         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
157                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
158                         _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
159                         NULL)
160 
161 #ifdef CONFIG_PM_SLEEP
162 static struct cpu_clk_suspend_context {
163         u32 clk_csite_src;
164         u32 cclkg_burst;
165         u32 cclkg_divider;
166 } tegra114_cpu_clk_sctx;
167 #endif
168 
169 static void __iomem *clk_base;
170 static void __iomem *pmc_base;
171 
172 static DEFINE_SPINLOCK(pll_d_lock);
173 static DEFINE_SPINLOCK(pll_d2_lock);
174 static DEFINE_SPINLOCK(pll_u_lock);
175 static DEFINE_SPINLOCK(pll_re_lock);
176 
177 static struct div_nmp pllxc_nmp = {
178         .divm_shift = 0,
179         .divm_width = 8,
180         .divn_shift = 8,
181         .divn_width = 8,
182         .divp_shift = 20,
183         .divp_width = 4,
184 };
185 
186 static struct pdiv_map pllxc_p[] = {
187         { .pdiv = 1, .hw_val = 0 },
188         { .pdiv = 2, .hw_val = 1 },
189         { .pdiv = 3, .hw_val = 2 },
190         { .pdiv = 4, .hw_val = 3 },
191         { .pdiv = 5, .hw_val = 4 },
192         { .pdiv = 6, .hw_val = 5 },
193         { .pdiv = 8, .hw_val = 6 },
194         { .pdiv = 10, .hw_val = 7 },
195         { .pdiv = 12, .hw_val = 8 },
196         { .pdiv = 16, .hw_val = 9 },
197         { .pdiv = 12, .hw_val = 10 },
198         { .pdiv = 16, .hw_val = 11 },
199         { .pdiv = 20, .hw_val = 12 },
200         { .pdiv = 24, .hw_val = 13 },
201         { .pdiv = 32, .hw_val = 14 },
202         { .pdiv = 0, .hw_val = 0 },
203 };
204 
205 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
206         { 12000000, 624000000, 104, 0, 2},
207         { 12000000, 600000000, 100, 0, 2},
208         { 13000000, 600000000,  92, 0, 2},      /* actual: 598.0 MHz */
209         { 16800000, 600000000,  71, 0, 2},      /* actual: 596.4 MHz */
210         { 19200000, 600000000,  62, 0, 2},      /* actual: 595.2 MHz */
211         { 26000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
212         { 0, 0, 0, 0, 0, 0 },
213 };
214 
215 static struct tegra_clk_pll_params pll_c_params = {
216         .input_min = 12000000,
217         .input_max = 800000000,
218         .cf_min = 12000000,
219         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
220         .vco_min = 600000000,
221         .vco_max = 1400000000,
222         .base_reg = PLLC_BASE,
223         .misc_reg = PLLC_MISC,
224         .lock_mask = PLL_BASE_LOCK,
225         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
226         .lock_delay = 300,
227         .iddq_reg = PLLC_MISC,
228         .iddq_bit_idx = PLLC_IDDQ_BIT,
229         .max_p = PLLXC_SW_MAX_P,
230         .dyn_ramp_reg = PLLC_MISC2,
231         .stepa_shift = 17,
232         .stepb_shift = 9,
233         .pdiv_tohw = pllxc_p,
234         .div_nmp = &pllxc_nmp,
235         .freq_table = pll_c_freq_table,
236         .flags = TEGRA_PLL_USE_LOCK,
237 };
238 
239 static struct div_nmp pllcx_nmp = {
240         .divm_shift = 0,
241         .divm_width = 2,
242         .divn_shift = 8,
243         .divn_width = 8,
244         .divp_shift = 20,
245         .divp_width = 3,
246 };
247 
248 static struct pdiv_map pllc_p[] = {
249         { .pdiv = 1, .hw_val = 0 },
250         { .pdiv = 2, .hw_val = 1 },
251         { .pdiv = 4, .hw_val = 3 },
252         { .pdiv = 8, .hw_val = 5 },
253         { .pdiv = 16, .hw_val = 7 },
254         { .pdiv = 0, .hw_val = 0 },
255 };
256 
257 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
258         {12000000, 600000000, 100, 0, 2},
259         {13000000, 600000000, 92, 0, 2},        /* actual: 598.0 MHz */
260         {16800000, 600000000, 71, 0, 2},        /* actual: 596.4 MHz */
261         {19200000, 600000000, 62, 0, 2},        /* actual: 595.2 MHz */
262         {26000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
263         {0, 0, 0, 0, 0, 0},
264 };
265 
266 static struct tegra_clk_pll_params pll_c2_params = {
267         .input_min = 12000000,
268         .input_max = 48000000,
269         .cf_min = 12000000,
270         .cf_max = 19200000,
271         .vco_min = 600000000,
272         .vco_max = 1200000000,
273         .base_reg = PLLC2_BASE,
274         .misc_reg = PLLC2_MISC,
275         .lock_mask = PLL_BASE_LOCK,
276         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
277         .lock_delay = 300,
278         .pdiv_tohw = pllc_p,
279         .div_nmp = &pllcx_nmp,
280         .max_p = 7,
281         .ext_misc_reg[0] = 0x4f0,
282         .ext_misc_reg[1] = 0x4f4,
283         .ext_misc_reg[2] = 0x4f8,
284         .freq_table = pll_cx_freq_table,
285         .flags = TEGRA_PLL_USE_LOCK,
286 };
287 
288 static struct tegra_clk_pll_params pll_c3_params = {
289         .input_min = 12000000,
290         .input_max = 48000000,
291         .cf_min = 12000000,
292         .cf_max = 19200000,
293         .vco_min = 600000000,
294         .vco_max = 1200000000,
295         .base_reg = PLLC3_BASE,
296         .misc_reg = PLLC3_MISC,
297         .lock_mask = PLL_BASE_LOCK,
298         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
299         .lock_delay = 300,
300         .pdiv_tohw = pllc_p,
301         .div_nmp = &pllcx_nmp,
302         .max_p = 7,
303         .ext_misc_reg[0] = 0x504,
304         .ext_misc_reg[1] = 0x508,
305         .ext_misc_reg[2] = 0x50c,
306         .freq_table = pll_cx_freq_table,
307         .flags = TEGRA_PLL_USE_LOCK,
308 };
309 
310 static struct div_nmp pllm_nmp = {
311         .divm_shift = 0,
312         .divm_width = 8,
313         .override_divm_shift = 0,
314         .divn_shift = 8,
315         .divn_width = 8,
316         .override_divn_shift = 8,
317         .divp_shift = 20,
318         .divp_width = 1,
319         .override_divp_shift = 27,
320 };
321 
322 static struct pdiv_map pllm_p[] = {
323         { .pdiv = 1, .hw_val = 0 },
324         { .pdiv = 2, .hw_val = 1 },
325         { .pdiv = 0, .hw_val = 0 },
326 };
327 
328 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
329         {12000000, 800000000, 66, 0, 1},        /* actual: 792.0 MHz */
330         {13000000, 800000000, 61, 0, 1},        /* actual: 793.0 MHz */
331         {16800000, 800000000, 47, 0, 1},        /* actual: 789.6 MHz */
332         {19200000, 800000000, 41, 0, 1},        /* actual: 787.2 MHz */
333         {26000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
334         {0, 0, 0, 0, 0, 0},
335 };
336 
337 static struct tegra_clk_pll_params pll_m_params = {
338         .input_min = 12000000,
339         .input_max = 500000000,
340         .cf_min = 12000000,
341         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
342         .vco_min = 400000000,
343         .vco_max = 1066000000,
344         .base_reg = PLLM_BASE,
345         .misc_reg = PLLM_MISC,
346         .lock_mask = PLL_BASE_LOCK,
347         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
348         .lock_delay = 300,
349         .max_p = 2,
350         .pdiv_tohw = pllm_p,
351         .div_nmp = &pllm_nmp,
352         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
353         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
354         .freq_table = pll_m_freq_table,
355         .flags = TEGRA_PLL_USE_LOCK,
356 };
357 
358 static struct div_nmp pllp_nmp = {
359         .divm_shift = 0,
360         .divm_width = 5,
361         .divn_shift = 8,
362         .divn_width = 10,
363         .divp_shift = 20,
364         .divp_width = 3,
365 };
366 
367 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
368         {12000000, 216000000, 432, 12, 1, 8},
369         {13000000, 216000000, 432, 13, 1, 8},
370         {16800000, 216000000, 360, 14, 1, 8},
371         {19200000, 216000000, 360, 16, 1, 8},
372         {26000000, 216000000, 432, 26, 1, 8},
373         {0, 0, 0, 0, 0, 0},
374 };
375 
376 static struct tegra_clk_pll_params pll_p_params = {
377         .input_min = 2000000,
378         .input_max = 31000000,
379         .cf_min = 1000000,
380         .cf_max = 6000000,
381         .vco_min = 200000000,
382         .vco_max = 700000000,
383         .base_reg = PLLP_BASE,
384         .misc_reg = PLLP_MISC,
385         .lock_mask = PLL_BASE_LOCK,
386         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
387         .lock_delay = 300,
388         .div_nmp = &pllp_nmp,
389         .freq_table = pll_p_freq_table,
390         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
391         .fixed_rate = 408000000,
392 };
393 
394 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
395         {9600000, 282240000, 147, 5, 0, 4},
396         {9600000, 368640000, 192, 5, 0, 4},
397         {9600000, 240000000, 200, 8, 0, 8},
398 
399         {28800000, 282240000, 245, 25, 0, 8},
400         {28800000, 368640000, 320, 25, 0, 8},
401         {28800000, 240000000, 200, 24, 0, 8},
402         {0, 0, 0, 0, 0, 0},
403 };
404 
405 
406 static struct tegra_clk_pll_params pll_a_params = {
407         .input_min = 2000000,
408         .input_max = 31000000,
409         .cf_min = 1000000,
410         .cf_max = 6000000,
411         .vco_min = 200000000,
412         .vco_max = 700000000,
413         .base_reg = PLLA_BASE,
414         .misc_reg = PLLA_MISC,
415         .lock_mask = PLL_BASE_LOCK,
416         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
417         .lock_delay = 300,
418         .div_nmp = &pllp_nmp,
419         .freq_table = pll_a_freq_table,
420         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
421 };
422 
423 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
424         {12000000, 216000000, 864, 12, 2, 12},
425         {13000000, 216000000, 864, 13, 2, 12},
426         {16800000, 216000000, 720, 14, 2, 12},
427         {19200000, 216000000, 720, 16, 2, 12},
428         {26000000, 216000000, 864, 26, 2, 12},
429 
430         {12000000, 594000000, 594, 12, 0, 12},
431         {13000000, 594000000, 594, 13, 0, 12},
432         {16800000, 594000000, 495, 14, 0, 12},
433         {19200000, 594000000, 495, 16, 0, 12},
434         {26000000, 594000000, 594, 26, 0, 12},
435 
436         {12000000, 1000000000, 1000, 12, 0, 12},
437         {13000000, 1000000000, 1000, 13, 0, 12},
438         {19200000, 1000000000, 625, 12, 0, 12},
439         {26000000, 1000000000, 1000, 26, 0, 12},
440 
441         {0, 0, 0, 0, 0, 0},
442 };
443 
444 static struct tegra_clk_pll_params pll_d_params = {
445         .input_min = 2000000,
446         .input_max = 40000000,
447         .cf_min = 1000000,
448         .cf_max = 6000000,
449         .vco_min = 500000000,
450         .vco_max = 1000000000,
451         .base_reg = PLLD_BASE,
452         .misc_reg = PLLD_MISC,
453         .lock_mask = PLL_BASE_LOCK,
454         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
455         .lock_delay = 1000,
456         .div_nmp = &pllp_nmp,
457         .freq_table = pll_d_freq_table,
458         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
459                  TEGRA_PLL_USE_LOCK,
460 };
461 
462 static struct tegra_clk_pll_params pll_d2_params = {
463         .input_min = 2000000,
464         .input_max = 40000000,
465         .cf_min = 1000000,
466         .cf_max = 6000000,
467         .vco_min = 500000000,
468         .vco_max = 1000000000,
469         .base_reg = PLLD2_BASE,
470         .misc_reg = PLLD2_MISC,
471         .lock_mask = PLL_BASE_LOCK,
472         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
473         .lock_delay = 1000,
474         .div_nmp = &pllp_nmp,
475         .freq_table = pll_d_freq_table,
476         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
477                  TEGRA_PLL_USE_LOCK,
478 };
479 
480 static struct pdiv_map pllu_p[] = {
481         { .pdiv = 1, .hw_val = 1 },
482         { .pdiv = 2, .hw_val = 0 },
483         { .pdiv = 0, .hw_val = 0 },
484 };
485 
486 static struct div_nmp pllu_nmp = {
487         .divm_shift = 0,
488         .divm_width = 5,
489         .divn_shift = 8,
490         .divn_width = 10,
491         .divp_shift = 20,
492         .divp_width = 1,
493 };
494 
495 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
496         {12000000, 480000000, 960, 12, 0, 12},
497         {13000000, 480000000, 960, 13, 0, 12},
498         {16800000, 480000000, 400, 7, 0, 5},
499         {19200000, 480000000, 200, 4, 0, 3},
500         {26000000, 480000000, 960, 26, 0, 12},
501         {0, 0, 0, 0, 0, 0},
502 };
503 
504 static struct tegra_clk_pll_params pll_u_params = {
505         .input_min = 2000000,
506         .input_max = 40000000,
507         .cf_min = 1000000,
508         .cf_max = 6000000,
509         .vco_min = 480000000,
510         .vco_max = 960000000,
511         .base_reg = PLLU_BASE,
512         .misc_reg = PLLU_MISC,
513         .lock_mask = PLL_BASE_LOCK,
514         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
515         .lock_delay = 1000,
516         .pdiv_tohw = pllu_p,
517         .div_nmp = &pllu_nmp,
518         .freq_table = pll_u_freq_table,
519         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
520                  TEGRA_PLL_USE_LOCK,
521 };
522 
523 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
524         /* 1 GHz */
525         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
526         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
527         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
528         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
529         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
530 
531         {0, 0, 0, 0, 0, 0},
532 };
533 
534 static struct tegra_clk_pll_params pll_x_params = {
535         .input_min = 12000000,
536         .input_max = 800000000,
537         .cf_min = 12000000,
538         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
539         .vco_min = 700000000,
540         .vco_max = 2400000000U,
541         .base_reg = PLLX_BASE,
542         .misc_reg = PLLX_MISC,
543         .lock_mask = PLL_BASE_LOCK,
544         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
545         .lock_delay = 300,
546         .iddq_reg = PLLX_MISC3,
547         .iddq_bit_idx = PLLX_IDDQ_BIT,
548         .max_p = PLLXC_SW_MAX_P,
549         .dyn_ramp_reg = PLLX_MISC2,
550         .stepa_shift = 16,
551         .stepb_shift = 24,
552         .pdiv_tohw = pllxc_p,
553         .div_nmp = &pllxc_nmp,
554         .freq_table = pll_x_freq_table,
555         .flags = TEGRA_PLL_USE_LOCK,
556 };
557 
558 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
559         /* PLLE special case: use cpcon field to store cml divider value */
560         {336000000, 100000000, 100, 21, 16, 11},
561         {312000000, 100000000, 200, 26, 24, 13},
562         {12000000, 100000000, 200,  1,  24, 13},
563         {0, 0, 0, 0, 0, 0},
564 };
565 
566 static struct div_nmp plle_nmp = {
567         .divm_shift = 0,
568         .divm_width = 8,
569         .divn_shift = 8,
570         .divn_width = 8,
571         .divp_shift = 24,
572         .divp_width = 4,
573 };
574 
575 static struct tegra_clk_pll_params pll_e_params = {
576         .input_min = 12000000,
577         .input_max = 1000000000,
578         .cf_min = 12000000,
579         .cf_max = 75000000,
580         .vco_min = 1600000000,
581         .vco_max = 2400000000U,
582         .base_reg = PLLE_BASE,
583         .misc_reg = PLLE_MISC,
584         .aux_reg = PLLE_AUX,
585         .lock_mask = PLLE_MISC_LOCK,
586         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
587         .lock_delay = 300,
588         .div_nmp = &plle_nmp,
589         .freq_table = pll_e_freq_table,
590         .flags = TEGRA_PLL_FIXED,
591         .fixed_rate = 100000000,
592 };
593 
594 static struct div_nmp pllre_nmp = {
595         .divm_shift = 0,
596         .divm_width = 8,
597         .divn_shift = 8,
598         .divn_width = 8,
599         .divp_shift = 16,
600         .divp_width = 4,
601 };
602 
603 static struct tegra_clk_pll_params pll_re_vco_params = {
604         .input_min = 12000000,
605         .input_max = 1000000000,
606         .cf_min = 12000000,
607         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
608         .vco_min = 300000000,
609         .vco_max = 600000000,
610         .base_reg = PLLRE_BASE,
611         .misc_reg = PLLRE_MISC,
612         .lock_mask = PLLRE_MISC_LOCK,
613         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
614         .lock_delay = 300,
615         .iddq_reg = PLLRE_MISC,
616         .iddq_bit_idx = PLLRE_IDDQ_BIT,
617         .div_nmp = &pllre_nmp,
618         .flags = TEGRA_PLL_USE_LOCK,
619 };
620 
621 /* possible OSC frequencies in Hz */
622 static unsigned long tegra114_input_freq[] = {
623         [0] = 13000000,
624         [1] = 16800000,
625         [4] = 19200000,
626         [5] = 38400000,
627         [8] = 12000000,
628         [9] = 48000000,
629         [12] = 260000000,
630 };
631 
632 #define MASK(x) (BIT(x) - 1)
633 
634 struct utmi_clk_param {
635         /* Oscillator Frequency in KHz */
636         u32 osc_frequency;
637         /* UTMIP PLL Enable Delay Count  */
638         u8 enable_delay_count;
639         /* UTMIP PLL Stable count */
640         u8 stable_count;
641         /*  UTMIP PLL Active delay count */
642         u8 active_delay_count;
643         /* UTMIP PLL Xtal frequency count */
644         u8 xtal_freq_count;
645 };
646 
647 static const struct utmi_clk_param utmi_parameters[] = {
648         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
649          .stable_count = 0x33, .active_delay_count = 0x05,
650          .xtal_freq_count = 0x7F},
651         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
652          .stable_count = 0x4B, .active_delay_count = 0x06,
653          .xtal_freq_count = 0xBB},
654         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
655          .stable_count = 0x2F, .active_delay_count = 0x04,
656          .xtal_freq_count = 0x76},
657         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
658          .stable_count = 0x66, .active_delay_count = 0x09,
659          .xtal_freq_count = 0xFE},
660         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
661          .stable_count = 0x41, .active_delay_count = 0x0A,
662          .xtal_freq_count = 0xA4},
663 };
664 
665 /* peripheral mux definitions */
666 
667 static const char *mux_plld_out0_plld2_out0[] = {
668         "pll_d_out0", "pll_d2_out0",
669 };
670 #define mux_plld_out0_plld2_out0_idx NULL
671 
672 static const char *mux_pllmcp_clkm[] = {
673         "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
674 };
675 
676 static const struct clk_div_table pll_re_div_table[] = {
677         { .val = 0, .div = 1 },
678         { .val = 1, .div = 2 },
679         { .val = 2, .div = 3 },
680         { .val = 3, .div = 4 },
681         { .val = 4, .div = 5 },
682         { .val = 5, .div = 6 },
683         { .val = 0, .div = 0 },
684 };
685 
686 static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
687         [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
688         [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
689         [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
690         [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
691         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
692         [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
693         [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
694         [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
695         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
696         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
697         [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
698         [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
699         [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
700         [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
701         [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
702         [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
703         [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
704         [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
705         [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
706         [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
707         [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
708         [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
709         [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
710         [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
711         [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
712         [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
713         [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
714         [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
715         [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
716         [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
717         [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
718         [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
719         [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
720         [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
721         [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
722         [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
723         [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
724         [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
725         [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
726         [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
727         [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
728         [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
729         [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
730         [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
731         [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
732         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
733         [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
734         [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
735         [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
736         [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
737         [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
738         [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
739         [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
740         [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
741         [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
742         [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
743         [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
744         [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
745         [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
746         [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
747         [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
748         [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
749         [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
750         [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
751         [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
752         [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
753         [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
754         [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
755         [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
756         [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
757         [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
758         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
759         [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
760         [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
761         [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
762         [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
763         [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
764         [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
765         [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
766         [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
767         [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
768         [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
769         [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
770         [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
771         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
772         [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
773         [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
774         [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
775         [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
776         [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
777         [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
778         [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
779         [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
780         [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
781         [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
782         [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
783         [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
784         [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
785         [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
786         [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
787         [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
788         [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
789         [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
790         [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
791         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
792         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
793         [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
794         [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
795         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
796         [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
797         [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
798         [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
799         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
800         [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
801         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
802         [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
803         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
804         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
805         [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
806         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
807         [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
808         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
809         [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
810         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
811         [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
812         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
813         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
814         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
815         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
816         [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
817         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
818         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
819         [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
820         [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
821         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
822         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
823         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
824         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
825         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
826         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
827         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
828         [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
829         [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
830         [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
831         [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
832         [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
833         [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
834         [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
835         [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
836         [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
837         [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
838         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
839         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
840         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
841         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
842         [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
843         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
844         [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
845         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
846         [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
847         [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
848         [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
849         [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
850         [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
851         [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
852         [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
853         [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
854         [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
855         [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
856         [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
857         [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
858         [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
859         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
860         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
861         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
862         [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
863         [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
864 };
865 
866 static struct tegra_devclk devclks[] __initdata = {
867         { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
868         { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
869         { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
870         { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
871         { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
872         { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
873         { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
874         { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
875         { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
876         { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
877         { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
878         { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
879         { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
880         { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
881         { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
882         { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
883         { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
884         { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
885         { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
886         { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
887         { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
888         { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
889         { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
890         { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
891         { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
892         { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
893         { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
894         { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
895         { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
896         { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
897         { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
898         { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
899         { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
900         { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
901         { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
902         { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
903         { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
904         { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
905         { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
906         { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
907         { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
908         { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
909         { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
910         { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
911         { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
912         { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
913         { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
914         { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
915         { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
916         { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
917         { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
918         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
919         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
920         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
921         { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
922         { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
923         { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
924         { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
925         { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
926         { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
927         { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
928         { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
929         { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
930 };
931 
932 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
933         "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
934 };
935 static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
936         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
937 };
938 
939 static struct clk **clks;
940 
941 static unsigned long osc_freq;
942 static unsigned long pll_ref_freq;
943 
944 static int __init tegra114_osc_clk_init(void __iomem *clk_base)
945 {
946         struct clk *clk;
947         u32 val, pll_ref_div;
948 
949         val = readl_relaxed(clk_base + OSC_CTRL);
950 
951         osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
952         if (!osc_freq) {
953                 WARN_ON(1);
954                 return -EINVAL;
955         }
956 
957         /* clk_m */
958         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
959                                       osc_freq);
960         clks[TEGRA114_CLK_CLK_M] = clk;
961 
962         /* pll_ref */
963         val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
964         pll_ref_div = 1 << val;
965         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
966                                         CLK_SET_RATE_PARENT, 1, pll_ref_div);
967         clks[TEGRA114_CLK_PLL_REF] = clk;
968 
969         pll_ref_freq = osc_freq / pll_ref_div;
970 
971         return 0;
972 }
973 
974 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
975 {
976         struct clk *clk;
977 
978         /* clk_32k */
979         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
980                                       32768);
981         clks[TEGRA114_CLK_CLK_32K] = clk;
982 
983         /* clk_m_div2 */
984         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
985                                         CLK_SET_RATE_PARENT, 1, 2);
986         clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
987 
988         /* clk_m_div4 */
989         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
990                                         CLK_SET_RATE_PARENT, 1, 4);
991         clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
992 
993 }
994 
995 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
996 {
997         u32 reg;
998         int i;
999 
1000         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1001                 if (osc_freq == utmi_parameters[i].osc_frequency)
1002                         break;
1003         }
1004 
1005         if (i >= ARRAY_SIZE(utmi_parameters)) {
1006                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1007                        osc_freq);
1008                 return;
1009         }
1010 
1011         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1012 
1013         /* Program UTMIP PLL stable and active counts */
1014         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1015         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1016         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1017 
1018         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1019 
1020         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1021                                             active_delay_count);
1022 
1023         /* Remove power downs from UTMIP PLL control bits */
1024         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1025         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1026         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1027 
1028         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1029 
1030         /* Program UTMIP PLL delay and oscillator frequency counts */
1031         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1032         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1033 
1034         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1035                                             enable_delay_count);
1036 
1037         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1038         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1039                                            xtal_freq_count);
1040 
1041         /* Remove power downs from UTMIP PLL control bits */
1042         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1043         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1044         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1045         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1046         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1047 
1048         /* Setup HW control of UTMIPLL */
1049         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1050         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1051         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1052         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1053         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1054 
1055         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1056         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1057         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1058         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1059 
1060         udelay(1);
1061 
1062         /* Setup SW override of UTMIPLL assuming USB2.0
1063            ports are assigned to USB2 */
1064         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1065         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1066         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1067         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1068 
1069         udelay(1);
1070 
1071         /* Enable HW control UTMIPLL */
1072         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1073         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1074         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1075 }
1076 
1077 static void __init tegra114_pll_init(void __iomem *clk_base,
1078                                      void __iomem *pmc)
1079 {
1080         u32 val;
1081         struct clk *clk;
1082 
1083         /* PLLC */
1084         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1085                         pmc, 0, &pll_c_params, NULL);
1086         clks[TEGRA114_CLK_PLL_C] = clk;
1087 
1088         /* PLLC_OUT1 */
1089         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1090                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1091                         8, 8, 1, NULL);
1092         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1093                                 clk_base + PLLC_OUT, 1, 0,
1094                                 CLK_SET_RATE_PARENT, 0, NULL);
1095         clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
1096 
1097         /* PLLC2 */
1098         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1099                              &pll_c2_params, NULL);
1100         clks[TEGRA114_CLK_PLL_C2] = clk;
1101 
1102         /* PLLC3 */
1103         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1104                              &pll_c3_params, NULL);
1105         clks[TEGRA114_CLK_PLL_C3] = clk;
1106 
1107         /* PLLM */
1108         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1109                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1110                              &pll_m_params, NULL);
1111         clks[TEGRA114_CLK_PLL_M] = clk;
1112 
1113         /* PLLM_OUT1 */
1114         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1115                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1116                                 8, 8, 1, NULL);
1117         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1118                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1119                                 CLK_SET_RATE_PARENT, 0, NULL);
1120         clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
1121 
1122         /* PLLM_UD */
1123         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1124                                         CLK_SET_RATE_PARENT, 1, 1);
1125 
1126         /* PLLU */
1127         val = readl(clk_base + pll_u_params.base_reg);
1128         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1129         writel(val, clk_base + pll_u_params.base_reg);
1130 
1131         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1132                             &pll_u_params, &pll_u_lock);
1133         clks[TEGRA114_CLK_PLL_U] = clk;
1134 
1135         tegra114_utmi_param_configure(clk_base);
1136 
1137         /* PLLU_480M */
1138         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1139                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1140                                 22, 0, &pll_u_lock);
1141         clks[TEGRA114_CLK_PLL_U_480M] = clk;
1142 
1143         /* PLLU_60M */
1144         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1145                                         CLK_SET_RATE_PARENT, 1, 8);
1146         clks[TEGRA114_CLK_PLL_U_60M] = clk;
1147 
1148         /* PLLU_48M */
1149         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1150                                         CLK_SET_RATE_PARENT, 1, 10);
1151         clks[TEGRA114_CLK_PLL_U_48M] = clk;
1152 
1153         /* PLLU_12M */
1154         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1155                                         CLK_SET_RATE_PARENT, 1, 40);
1156         clks[TEGRA114_CLK_PLL_U_12M] = clk;
1157 
1158         /* PLLD */
1159         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1160                             &pll_d_params, &pll_d_lock);
1161         clks[TEGRA114_CLK_PLL_D] = clk;
1162 
1163         /* PLLD_OUT0 */
1164         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1165                                         CLK_SET_RATE_PARENT, 1, 2);
1166         clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
1167 
1168         /* PLLD2 */
1169         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1170                             &pll_d2_params, &pll_d2_lock);
1171         clks[TEGRA114_CLK_PLL_D2] = clk;
1172 
1173         /* PLLD2_OUT0 */
1174         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1175                                         CLK_SET_RATE_PARENT, 1, 2);
1176         clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1177 
1178         /* PLLRE */
1179         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1180                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1181         clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
1182 
1183         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1184                                          clk_base + PLLRE_BASE, 16, 4, 0,
1185                                          pll_re_div_table, &pll_re_lock);
1186         clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1187 
1188         /* PLLE */
1189         clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1190                                       clk_base, 0, &pll_e_params, NULL);
1191         clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1192 }
1193 
1194 #define CLK_SOURCE_VI_SENSOR 0x1a8
1195 
1196 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1197         MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1198 };
1199 
1200 static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1201                                             void __iomem *pmc_base)
1202 {
1203         struct clk *clk;
1204         struct tegra_periph_init_data *data;
1205         int i;
1206 
1207         /* xusb_ss_div2 */
1208         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1209                                         1, 2);
1210         clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1211 
1212         /* dsia mux */
1213         clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1214                                ARRAY_SIZE(mux_plld_out0_plld2_out0),
1215                                CLK_SET_RATE_NO_REPARENT,
1216                                clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1217         clks[TEGRA114_CLK_DSIA_MUX] = clk;
1218 
1219         /* dsib mux */
1220         clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1221                                ARRAY_SIZE(mux_plld_out0_plld2_out0),
1222                                CLK_SET_RATE_NO_REPARENT,
1223                                clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1224         clks[TEGRA114_CLK_DSIB_MUX] = clk;
1225 
1226         /* emc mux */
1227         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1228                                ARRAY_SIZE(mux_pllmcp_clkm),
1229                                CLK_SET_RATE_NO_REPARENT,
1230                                clk_base + CLK_SOURCE_EMC,
1231                                29, 3, 0, NULL);
1232 
1233         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1234                 data = &tegra_periph_clk_list[i];
1235                 clk = tegra_clk_register_periph(data->name,
1236                         data->p.parent_names, data->num_parents,
1237                         &data->periph, clk_base, data->offset, data->flags);
1238                 clks[data->clk_id] = clk;
1239         }
1240 
1241         tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1242                                 &pll_p_params);
1243 }
1244 
1245 /* Tegra114 CPU clock and reset control functions */
1246 static void tegra114_wait_cpu_in_reset(u32 cpu)
1247 {
1248         unsigned int reg;
1249 
1250         do {
1251                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1252                 cpu_relax();
1253         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1254 }
1255 static void tegra114_disable_cpu_clock(u32 cpu)
1256 {
1257         /* flow controller would take care in the power sequence. */
1258 }
1259 
1260 #ifdef CONFIG_PM_SLEEP
1261 static void tegra114_cpu_clock_suspend(void)
1262 {
1263         /* switch coresite to clk_m, save off original source */
1264         tegra114_cpu_clk_sctx.clk_csite_src =
1265                                 readl(clk_base + CLK_SOURCE_CSITE);
1266         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1267 
1268         tegra114_cpu_clk_sctx.cclkg_burst =
1269                                 readl(clk_base + CCLKG_BURST_POLICY);
1270         tegra114_cpu_clk_sctx.cclkg_divider =
1271                                 readl(clk_base + CCLKG_BURST_POLICY + 4);
1272 }
1273 
1274 static void tegra114_cpu_clock_resume(void)
1275 {
1276         writel(tegra114_cpu_clk_sctx.clk_csite_src,
1277                                         clk_base + CLK_SOURCE_CSITE);
1278 
1279         writel(tegra114_cpu_clk_sctx.cclkg_burst,
1280                                         clk_base + CCLKG_BURST_POLICY);
1281         writel(tegra114_cpu_clk_sctx.cclkg_divider,
1282                                         clk_base + CCLKG_BURST_POLICY + 4);
1283 }
1284 #endif
1285 
1286 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1287         .wait_for_reset = tegra114_wait_cpu_in_reset,
1288         .disable_clock  = tegra114_disable_cpu_clock,
1289 #ifdef CONFIG_PM_SLEEP
1290         .suspend        = tegra114_cpu_clock_suspend,
1291         .resume         = tegra114_cpu_clock_resume,
1292 #endif
1293 };
1294 
1295 static const struct of_device_id pmc_match[] __initconst = {
1296         { .compatible = "nvidia,tegra114-pmc" },
1297         {},
1298 };
1299 
1300 /*
1301  * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1302  * breaks
1303  */
1304 static struct tegra_clk_init_table init_table[] __initdata = {
1305         {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
1306         {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
1307         {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
1308         {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
1309         {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
1310         {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
1311         {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
1312         {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
1313         {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
1314         {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1315         {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1316         {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1317         {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1318         {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1319         {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
1320         {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
1321         {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
1322         {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1323         {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
1324         {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1325         {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1326         {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1327         {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
1328         {TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0},
1329         {TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0},
1330         {TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0},
1331         {TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0},
1332         {TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
1333         {TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},
1334         /* This MUST be the last entry. */
1335         {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
1336 };
1337 
1338 static void __init tegra114_clock_apply_init_table(void)
1339 {
1340         tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1341 }
1342 
1343 
1344 /**
1345  * tegra114_car_barrier - wait for pending writes to the CAR to complete
1346  *
1347  * Wait for any outstanding writes to the CAR MMIO space from this CPU
1348  * to complete before continuing execution.  No return value.
1349  */
1350 static void tegra114_car_barrier(void)
1351 {
1352         wmb();          /* probably unnecessary */
1353         readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1354 }
1355 
1356 /**
1357  * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1358  *
1359  * When the CPU rail voltage is in the high-voltage range, use the
1360  * built-in hardwired clock propagation delays in the CPU clock
1361  * shaper.  No return value.
1362  */
1363 void tegra114_clock_tune_cpu_trimmers_high(void)
1364 {
1365         u32 select = 0;
1366 
1367         /* Use hardwired rise->rise & fall->fall clock propagation delays */
1368         select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1369                     CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1370                     CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1371         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1372 
1373         tegra114_car_barrier();
1374 }
1375 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1376 
1377 /**
1378  * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1379  *
1380  * When the CPU rail voltage is in the low-voltage range, use the
1381  * extended clock propagation delays set by
1382  * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
1383  * maintain the input clock duty cycle that the FCPU subsystem
1384  * expects.  No return value.
1385  */
1386 void tegra114_clock_tune_cpu_trimmers_low(void)
1387 {
1388         u32 select = 0;
1389 
1390         /*
1391          * Use software-specified rise->rise & fall->fall clock
1392          * propagation delays (from
1393          * tegra114_clock_tune_cpu_trimmers_init()
1394          */
1395         select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1396                    CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1397                    CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1398         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1399 
1400         tegra114_car_barrier();
1401 }
1402 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1403 
1404 /**
1405  * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1406  *
1407  * Program extended clock propagation delays into the FCPU clock
1408  * shaper and enable them.  XXX Define the purpose - peak current
1409  * reduction?  No return value.
1410  */
1411 /* XXX Initial voltage rail state assumption issues? */
1412 void tegra114_clock_tune_cpu_trimmers_init(void)
1413 {
1414         u32 dr = 0, r = 0;
1415 
1416         /* Increment the rise->rise clock delay by four steps */
1417         r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1418               CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1419               CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1420         writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1421 
1422         /*
1423          * Use the rise->rise clock propagation delay specified in the
1424          * r field
1425          */
1426         dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1427                CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1428                CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1429         writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1430 
1431         tegra114_clock_tune_cpu_trimmers_low();
1432 }
1433 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1434 
1435 /**
1436  * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1437  *
1438  * Assert the reset line of the DFLL's DVCO.  No return value.
1439  */
1440 void tegra114_clock_assert_dfll_dvco_reset(void)
1441 {
1442         u32 v;
1443 
1444         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1445         v |= (1 << DVFS_DFLL_RESET_SHIFT);
1446         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1447         tegra114_car_barrier();
1448 }
1449 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1450 
1451 /**
1452  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1453  *
1454  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1455  * operate.  No return value.
1456  */
1457 void tegra114_clock_deassert_dfll_dvco_reset(void)
1458 {
1459         u32 v;
1460 
1461         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1462         v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1463         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1464         tegra114_car_barrier();
1465 }
1466 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1467 
1468 static void __init tegra114_clock_init(struct device_node *np)
1469 {
1470         struct device_node *node;
1471 
1472         clk_base = of_iomap(np, 0);
1473         if (!clk_base) {
1474                 pr_err("ioremap tegra114 CAR failed\n");
1475                 return;
1476         }
1477 
1478         node = of_find_matching_node(NULL, pmc_match);
1479         if (!node) {
1480                 pr_err("Failed to find pmc node\n");
1481                 WARN_ON(1);
1482                 return;
1483         }
1484 
1485         pmc_base = of_iomap(node, 0);
1486         if (!pmc_base) {
1487                 pr_err("Can't map pmc registers\n");
1488                 WARN_ON(1);
1489                 return;
1490         }
1491 
1492         clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1493                                 TEGRA114_CLK_PERIPH_BANKS);
1494         if (!clks)
1495                 return;
1496 
1497         if (tegra114_osc_clk_init(clk_base) < 0)
1498                 return;
1499 
1500         tegra114_fixed_clk_init(clk_base);
1501         tegra114_pll_init(clk_base, pmc_base);
1502         tegra114_periph_clk_init(clk_base, pmc_base);
1503         tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
1504         tegra_pmc_clk_init(pmc_base, tegra114_clks);
1505         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1506                                         &pll_x_params);
1507 
1508         tegra_add_of_provider(np);
1509         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1510 
1511         tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1512 
1513         tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1514 }
1515 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
1516 

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