Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/clk/tegra/clk-tegra114.c

  1 /*
  2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
  3  *
  4  * This program is free software; you can redistribute it and/or modify it
  5  * under the terms and conditions of the GNU General Public License,
  6  * version 2, as published by the Free Software Foundation.
  7  *
  8  * This program is distributed in the hope it will be useful, but WITHOUT
  9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 11  * more details.
 12  *
 13  * You should have received a copy of the GNU General Public License
 14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 15  */
 16 
 17 #include <linux/io.h>
 18 #include <linux/clk-provider.h>
 19 #include <linux/of.h>
 20 #include <linux/of_address.h>
 21 #include <linux/delay.h>
 22 #include <linux/export.h>
 23 #include <linux/clk/tegra.h>
 24 #include <dt-bindings/clock/tegra114-car.h>
 25 
 26 #include "clk.h"
 27 #include "clk-id.h"
 28 
 29 #define RST_DFLL_DVCO                   0x2F4
 30 #define CPU_FINETRIM_SELECT             0x4d4   /* override default prop dlys */
 31 #define CPU_FINETRIM_DR                 0x4d8   /* rise->rise prop dly A */
 32 #define CPU_FINETRIM_R                  0x4e4   /* rise->rise prop dly inc A */
 33 
 34 /* RST_DFLL_DVCO bitfields */
 35 #define DVFS_DFLL_RESET_SHIFT           0
 36 
 37 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
 38 #define CPU_FINETRIM_1_FCPU_1           BIT(0)  /* fcpu0 */
 39 #define CPU_FINETRIM_1_FCPU_2           BIT(1)  /* fcpu1 */
 40 #define CPU_FINETRIM_1_FCPU_3           BIT(2)  /* fcpu2 */
 41 #define CPU_FINETRIM_1_FCPU_4           BIT(3)  /* fcpu3 */
 42 #define CPU_FINETRIM_1_FCPU_5           BIT(4)  /* fl2 */
 43 #define CPU_FINETRIM_1_FCPU_6           BIT(5)  /* ftop */
 44 
 45 /* CPU_FINETRIM_R bitfields */
 46 #define CPU_FINETRIM_R_FCPU_1_SHIFT     0               /* fcpu0 */
 47 #define CPU_FINETRIM_R_FCPU_1_MASK      (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
 48 #define CPU_FINETRIM_R_FCPU_2_SHIFT     2               /* fcpu1 */
 49 #define CPU_FINETRIM_R_FCPU_2_MASK      (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
 50 #define CPU_FINETRIM_R_FCPU_3_SHIFT     4               /* fcpu2 */
 51 #define CPU_FINETRIM_R_FCPU_3_MASK      (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
 52 #define CPU_FINETRIM_R_FCPU_4_SHIFT     6               /* fcpu3 */
 53 #define CPU_FINETRIM_R_FCPU_4_MASK      (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
 54 #define CPU_FINETRIM_R_FCPU_5_SHIFT     8               /* fl2 */
 55 #define CPU_FINETRIM_R_FCPU_5_MASK      (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
 56 #define CPU_FINETRIM_R_FCPU_6_SHIFT     10              /* ftop */
 57 #define CPU_FINETRIM_R_FCPU_6_MASK      (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
 58 
 59 #define TEGRA114_CLK_PERIPH_BANKS       5
 60 
 61 #define PLLC_BASE 0x80
 62 #define PLLC_MISC2 0x88
 63 #define PLLC_MISC 0x8c
 64 #define PLLC2_BASE 0x4e8
 65 #define PLLC2_MISC 0x4ec
 66 #define PLLC3_BASE 0x4fc
 67 #define PLLC3_MISC 0x500
 68 #define PLLM_BASE 0x90
 69 #define PLLM_MISC 0x9c
 70 #define PLLP_BASE 0xa0
 71 #define PLLP_MISC 0xac
 72 #define PLLX_BASE 0xe0
 73 #define PLLX_MISC 0xe4
 74 #define PLLX_MISC2 0x514
 75 #define PLLX_MISC3 0x518
 76 #define PLLD_BASE 0xd0
 77 #define PLLD_MISC 0xdc
 78 #define PLLD2_BASE 0x4b8
 79 #define PLLD2_MISC 0x4bc
 80 #define PLLE_BASE 0xe8
 81 #define PLLE_MISC 0xec
 82 #define PLLA_BASE 0xb0
 83 #define PLLA_MISC 0xbc
 84 #define PLLU_BASE 0xc0
 85 #define PLLU_MISC 0xcc
 86 #define PLLRE_BASE 0x4c4
 87 #define PLLRE_MISC 0x4c8
 88 
 89 #define PLL_MISC_LOCK_ENABLE 18
 90 #define PLLC_MISC_LOCK_ENABLE 24
 91 #define PLLDU_MISC_LOCK_ENABLE 22
 92 #define PLLE_MISC_LOCK_ENABLE 9
 93 #define PLLRE_MISC_LOCK_ENABLE 30
 94 
 95 #define PLLC_IDDQ_BIT 26
 96 #define PLLX_IDDQ_BIT 3
 97 #define PLLRE_IDDQ_BIT 16
 98 
 99 #define PLL_BASE_LOCK BIT(27)
100 #define PLLE_MISC_LOCK BIT(11)
101 #define PLLRE_MISC_LOCK BIT(24)
102 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
103 
104 #define PLLE_AUX 0x48c
105 #define PLLC_OUT 0x84
106 #define PLLM_OUT 0x94
107 
108 #define OSC_CTRL                        0x50
109 #define OSC_CTRL_OSC_FREQ_SHIFT         28
110 #define OSC_CTRL_PLL_REF_DIV_SHIFT      26
111 
112 #define PLLXC_SW_MAX_P                  6
113 
114 #define CCLKG_BURST_POLICY 0x368
115 
116 #define UTMIP_PLL_CFG2 0x488
117 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
118 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
119 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
120 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
121 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
122 
123 #define UTMIP_PLL_CFG1 0x484
124 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
125 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
126 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
127 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
128 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
129 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
130 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
131 
132 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
133 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
134 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
135 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
136 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
137 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
138 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
139 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
140 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
141 
142 #define CLK_SOURCE_CSITE 0x1d4
143 #define CLK_SOURCE_EMC 0x19c
144 
145 /* PLLM override registers */
146 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
147 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
148 
149 /* Tegra CPU clock and reset control regs */
150 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
151 
152 #define MUX8(_name, _parents, _offset, \
153                              _clk_num, _gate_flags, _clk_id)    \
154         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
155                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
156                         _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
157                         NULL)
158 
159 #ifdef CONFIG_PM_SLEEP
160 static struct cpu_clk_suspend_context {
161         u32 clk_csite_src;
162         u32 cclkg_burst;
163         u32 cclkg_divider;
164 } tegra114_cpu_clk_sctx;
165 #endif
166 
167 static void __iomem *clk_base;
168 static void __iomem *pmc_base;
169 
170 static DEFINE_SPINLOCK(pll_d_lock);
171 static DEFINE_SPINLOCK(pll_d2_lock);
172 static DEFINE_SPINLOCK(pll_u_lock);
173 static DEFINE_SPINLOCK(pll_re_lock);
174 static DEFINE_SPINLOCK(emc_lock);
175 
176 static struct div_nmp pllxc_nmp = {
177         .divm_shift = 0,
178         .divm_width = 8,
179         .divn_shift = 8,
180         .divn_width = 8,
181         .divp_shift = 20,
182         .divp_width = 4,
183 };
184 
185 static const struct pdiv_map pllxc_p[] = {
186         { .pdiv =  1, .hw_val =  0 },
187         { .pdiv =  2, .hw_val =  1 },
188         { .pdiv =  3, .hw_val =  2 },
189         { .pdiv =  4, .hw_val =  3 },
190         { .pdiv =  5, .hw_val =  4 },
191         { .pdiv =  6, .hw_val =  5 },
192         { .pdiv =  8, .hw_val =  6 },
193         { .pdiv = 10, .hw_val =  7 },
194         { .pdiv = 12, .hw_val =  8 },
195         { .pdiv = 16, .hw_val =  9 },
196         { .pdiv = 12, .hw_val = 10 },
197         { .pdiv = 16, .hw_val = 11 },
198         { .pdiv = 20, .hw_val = 12 },
199         { .pdiv = 24, .hw_val = 13 },
200         { .pdiv = 32, .hw_val = 14 },
201         { .pdiv =  0, .hw_val =  0 },
202 };
203 
204 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
205         { 12000000, 624000000, 104, 1, 2, 0 },
206         { 12000000, 600000000, 100, 1, 2, 0 },
207         { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
208         { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
209         { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
210         { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
211         {        0,         0,   0, 0, 0, 0 },
212 };
213 
214 static struct tegra_clk_pll_params pll_c_params = {
215         .input_min = 12000000,
216         .input_max = 800000000,
217         .cf_min = 12000000,
218         .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
219         .vco_min = 600000000,
220         .vco_max = 1400000000,
221         .base_reg = PLLC_BASE,
222         .misc_reg = PLLC_MISC,
223         .lock_mask = PLL_BASE_LOCK,
224         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
225         .lock_delay = 300,
226         .iddq_reg = PLLC_MISC,
227         .iddq_bit_idx = PLLC_IDDQ_BIT,
228         .max_p = PLLXC_SW_MAX_P,
229         .dyn_ramp_reg = PLLC_MISC2,
230         .stepa_shift = 17,
231         .stepb_shift = 9,
232         .pdiv_tohw = pllxc_p,
233         .div_nmp = &pllxc_nmp,
234         .freq_table = pll_c_freq_table,
235         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
236 };
237 
238 static struct div_nmp pllcx_nmp = {
239         .divm_shift = 0,
240         .divm_width = 2,
241         .divn_shift = 8,
242         .divn_width = 8,
243         .divp_shift = 20,
244         .divp_width = 3,
245 };
246 
247 static const struct pdiv_map pllc_p[] = {
248         { .pdiv =  1, .hw_val = 0 },
249         { .pdiv =  2, .hw_val = 1 },
250         { .pdiv =  4, .hw_val = 3 },
251         { .pdiv =  8, .hw_val = 5 },
252         { .pdiv = 16, .hw_val = 7 },
253         { .pdiv =  0, .hw_val = 0 },
254 };
255 
256 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
257         { 12000000, 600000000, 100, 1, 2, 0 },
258         { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
259         { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
260         { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
261         { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
262         {        0,         0,   0, 0, 0, 0 },
263 };
264 
265 static struct tegra_clk_pll_params pll_c2_params = {
266         .input_min = 12000000,
267         .input_max = 48000000,
268         .cf_min = 12000000,
269         .cf_max = 19200000,
270         .vco_min = 600000000,
271         .vco_max = 1200000000,
272         .base_reg = PLLC2_BASE,
273         .misc_reg = PLLC2_MISC,
274         .lock_mask = PLL_BASE_LOCK,
275         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
276         .lock_delay = 300,
277         .pdiv_tohw = pllc_p,
278         .div_nmp = &pllcx_nmp,
279         .max_p = 7,
280         .ext_misc_reg[0] = 0x4f0,
281         .ext_misc_reg[1] = 0x4f4,
282         .ext_misc_reg[2] = 0x4f8,
283         .freq_table = pll_cx_freq_table,
284         .flags = TEGRA_PLL_USE_LOCK,
285 };
286 
287 static struct tegra_clk_pll_params pll_c3_params = {
288         .input_min = 12000000,
289         .input_max = 48000000,
290         .cf_min = 12000000,
291         .cf_max = 19200000,
292         .vco_min = 600000000,
293         .vco_max = 1200000000,
294         .base_reg = PLLC3_BASE,
295         .misc_reg = PLLC3_MISC,
296         .lock_mask = PLL_BASE_LOCK,
297         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
298         .lock_delay = 300,
299         .pdiv_tohw = pllc_p,
300         .div_nmp = &pllcx_nmp,
301         .max_p = 7,
302         .ext_misc_reg[0] = 0x504,
303         .ext_misc_reg[1] = 0x508,
304         .ext_misc_reg[2] = 0x50c,
305         .freq_table = pll_cx_freq_table,
306         .flags = TEGRA_PLL_USE_LOCK,
307 };
308 
309 static struct div_nmp pllm_nmp = {
310         .divm_shift = 0,
311         .divm_width = 8,
312         .override_divm_shift = 0,
313         .divn_shift = 8,
314         .divn_width = 8,
315         .override_divn_shift = 8,
316         .divp_shift = 20,
317         .divp_width = 1,
318         .override_divp_shift = 27,
319 };
320 
321 static const struct pdiv_map pllm_p[] = {
322         { .pdiv = 1, .hw_val = 0 },
323         { .pdiv = 2, .hw_val = 1 },
324         { .pdiv = 0, .hw_val = 0 },
325 };
326 
327 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
328         { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
329         { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
330         { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
331         { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
332         { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
333         {        0,         0,  0, 0, 0, 0 },
334 };
335 
336 static struct tegra_clk_pll_params pll_m_params = {
337         .input_min = 12000000,
338         .input_max = 500000000,
339         .cf_min = 12000000,
340         .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
341         .vco_min = 400000000,
342         .vco_max = 1066000000,
343         .base_reg = PLLM_BASE,
344         .misc_reg = PLLM_MISC,
345         .lock_mask = PLL_BASE_LOCK,
346         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
347         .lock_delay = 300,
348         .max_p = 2,
349         .pdiv_tohw = pllm_p,
350         .div_nmp = &pllm_nmp,
351         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
352         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
353         .freq_table = pll_m_freq_table,
354         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
355                  TEGRA_PLL_FIXED,
356 };
357 
358 static struct div_nmp pllp_nmp = {
359         .divm_shift = 0,
360         .divm_width = 5,
361         .divn_shift = 8,
362         .divn_width = 10,
363         .divp_shift = 20,
364         .divp_width = 3,
365 };
366 
367 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
368         { 12000000, 216000000, 432, 12, 2, 8 },
369         { 13000000, 216000000, 432, 13, 2, 8 },
370         { 16800000, 216000000, 360, 14, 2, 8 },
371         { 19200000, 216000000, 360, 16, 2, 8 },
372         { 26000000, 216000000, 432, 26, 2, 8 },
373         {        0,         0,   0,  0, 0, 0 },
374 };
375 
376 static struct tegra_clk_pll_params pll_p_params = {
377         .input_min = 2000000,
378         .input_max = 31000000,
379         .cf_min = 1000000,
380         .cf_max = 6000000,
381         .vco_min = 200000000,
382         .vco_max = 700000000,
383         .base_reg = PLLP_BASE,
384         .misc_reg = PLLP_MISC,
385         .lock_mask = PLL_BASE_LOCK,
386         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
387         .lock_delay = 300,
388         .div_nmp = &pllp_nmp,
389         .freq_table = pll_p_freq_table,
390         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
391                  TEGRA_PLL_HAS_LOCK_ENABLE,
392         .fixed_rate = 408000000,
393 };
394 
395 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
396         {  9600000, 282240000, 147,  5, 1, 4 },
397         {  9600000, 368640000, 192,  5, 1, 4 },
398         {  9600000, 240000000, 200,  8, 1, 8 },
399         { 28800000, 282240000, 245, 25, 1, 8 },
400         { 28800000, 368640000, 320, 25, 1, 8 },
401         { 28800000, 240000000, 200, 24, 1, 8 },
402         {        0,         0,   0,  0, 0, 0 },
403 };
404 
405 
406 static struct tegra_clk_pll_params pll_a_params = {
407         .input_min = 2000000,
408         .input_max = 31000000,
409         .cf_min = 1000000,
410         .cf_max = 6000000,
411         .vco_min = 200000000,
412         .vco_max = 700000000,
413         .base_reg = PLLA_BASE,
414         .misc_reg = PLLA_MISC,
415         .lock_mask = PLL_BASE_LOCK,
416         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
417         .lock_delay = 300,
418         .div_nmp = &pllp_nmp,
419         .freq_table = pll_a_freq_table,
420         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
421                  TEGRA_PLL_HAS_LOCK_ENABLE,
422 };
423 
424 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
425         { 12000000,  216000000,  864, 12, 4, 12 },
426         { 13000000,  216000000,  864, 13, 4, 12 },
427         { 16800000,  216000000,  720, 14, 4, 12 },
428         { 19200000,  216000000,  720, 16, 4, 12 },
429         { 26000000,  216000000,  864, 26, 4, 12 },
430         { 12000000,  594000000,  594, 12, 1, 12 },
431         { 13000000,  594000000,  594, 13, 1, 12 },
432         { 16800000,  594000000,  495, 14, 1, 12 },
433         { 19200000,  594000000,  495, 16, 1, 12 },
434         { 26000000,  594000000,  594, 26, 1, 12 },
435         { 12000000, 1000000000, 1000, 12, 1, 12 },
436         { 13000000, 1000000000, 1000, 13, 1, 12 },
437         { 19200000, 1000000000,  625, 12, 1, 12 },
438         { 26000000, 1000000000, 1000, 26, 1, 12 },
439         {        0,          0,    0,  0, 0,  0 },
440 };
441 
442 static struct tegra_clk_pll_params pll_d_params = {
443         .input_min = 2000000,
444         .input_max = 40000000,
445         .cf_min = 1000000,
446         .cf_max = 6000000,
447         .vco_min = 500000000,
448         .vco_max = 1000000000,
449         .base_reg = PLLD_BASE,
450         .misc_reg = PLLD_MISC,
451         .lock_mask = PLL_BASE_LOCK,
452         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
453         .lock_delay = 1000,
454         .div_nmp = &pllp_nmp,
455         .freq_table = pll_d_freq_table,
456         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
457                  TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
458 };
459 
460 static struct tegra_clk_pll_params pll_d2_params = {
461         .input_min = 2000000,
462         .input_max = 40000000,
463         .cf_min = 1000000,
464         .cf_max = 6000000,
465         .vco_min = 500000000,
466         .vco_max = 1000000000,
467         .base_reg = PLLD2_BASE,
468         .misc_reg = PLLD2_MISC,
469         .lock_mask = PLL_BASE_LOCK,
470         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
471         .lock_delay = 1000,
472         .div_nmp = &pllp_nmp,
473         .freq_table = pll_d_freq_table,
474         .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
475                  TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
476 };
477 
478 static const struct pdiv_map pllu_p[] = {
479         { .pdiv = 1, .hw_val = 1 },
480         { .pdiv = 2, .hw_val = 0 },
481         { .pdiv = 0, .hw_val = 0 },
482 };
483 
484 static struct div_nmp pllu_nmp = {
485         .divm_shift = 0,
486         .divm_width = 5,
487         .divn_shift = 8,
488         .divn_width = 10,
489         .divp_shift = 20,
490         .divp_width = 1,
491 };
492 
493 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
494         { 12000000, 480000000, 960, 12, 2, 12 },
495         { 13000000, 480000000, 960, 13, 2, 12 },
496         { 16800000, 480000000, 400,  7, 2,  5 },
497         { 19200000, 480000000, 200,  4, 2,  3 },
498         { 26000000, 480000000, 960, 26, 2, 12 },
499         {        0,         0,   0,  0, 0,  0 },
500 };
501 
502 static struct tegra_clk_pll_params pll_u_params = {
503         .input_min = 2000000,
504         .input_max = 40000000,
505         .cf_min = 1000000,
506         .cf_max = 6000000,
507         .vco_min = 480000000,
508         .vco_max = 960000000,
509         .base_reg = PLLU_BASE,
510         .misc_reg = PLLU_MISC,
511         .lock_mask = PLL_BASE_LOCK,
512         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
513         .lock_delay = 1000,
514         .pdiv_tohw = pllu_p,
515         .div_nmp = &pllu_nmp,
516         .freq_table = pll_u_freq_table,
517         .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
518                  TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
519 };
520 
521 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
522         /* 1 GHz */
523         { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
524         { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
525         { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
526         { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
527         { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
528         {        0,          0,  0, 0, 0, 0 },
529 };
530 
531 static struct tegra_clk_pll_params pll_x_params = {
532         .input_min = 12000000,
533         .input_max = 800000000,
534         .cf_min = 12000000,
535         .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
536         .vco_min = 700000000,
537         .vco_max = 2400000000U,
538         .base_reg = PLLX_BASE,
539         .misc_reg = PLLX_MISC,
540         .lock_mask = PLL_BASE_LOCK,
541         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
542         .lock_delay = 300,
543         .iddq_reg = PLLX_MISC3,
544         .iddq_bit_idx = PLLX_IDDQ_BIT,
545         .max_p = PLLXC_SW_MAX_P,
546         .dyn_ramp_reg = PLLX_MISC2,
547         .stepa_shift = 16,
548         .stepb_shift = 24,
549         .pdiv_tohw = pllxc_p,
550         .div_nmp = &pllxc_nmp,
551         .freq_table = pll_x_freq_table,
552         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
553 };
554 
555 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
556         /* PLLE special case: use cpcon field to store cml divider value */
557         { 336000000, 100000000, 100, 21, 16, 11 },
558         { 312000000, 100000000, 200, 26, 24, 13 },
559         {  12000000, 100000000, 200,  1, 24, 13 },
560         {         0,         0,   0,  0,  0,  0 },
561 };
562 
563 static const struct pdiv_map plle_p[] = {
564         { .pdiv =  1, .hw_val =  0 },
565         { .pdiv =  2, .hw_val =  1 },
566         { .pdiv =  3, .hw_val =  2 },
567         { .pdiv =  4, .hw_val =  3 },
568         { .pdiv =  5, .hw_val =  4 },
569         { .pdiv =  6, .hw_val =  5 },
570         { .pdiv =  8, .hw_val =  6 },
571         { .pdiv = 10, .hw_val =  7 },
572         { .pdiv = 12, .hw_val =  8 },
573         { .pdiv = 16, .hw_val =  9 },
574         { .pdiv = 12, .hw_val = 10 },
575         { .pdiv = 16, .hw_val = 11 },
576         { .pdiv = 20, .hw_val = 12 },
577         { .pdiv = 24, .hw_val = 13 },
578         { .pdiv = 32, .hw_val = 14 },
579         { .pdiv =  0, .hw_val =  0 }
580 };
581 
582 static struct div_nmp plle_nmp = {
583         .divm_shift = 0,
584         .divm_width = 8,
585         .divn_shift = 8,
586         .divn_width = 8,
587         .divp_shift = 24,
588         .divp_width = 4,
589 };
590 
591 static struct tegra_clk_pll_params pll_e_params = {
592         .input_min = 12000000,
593         .input_max = 1000000000,
594         .cf_min = 12000000,
595         .cf_max = 75000000,
596         .vco_min = 1600000000,
597         .vco_max = 2400000000U,
598         .base_reg = PLLE_BASE,
599         .misc_reg = PLLE_MISC,
600         .aux_reg = PLLE_AUX,
601         .lock_mask = PLLE_MISC_LOCK,
602         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
603         .lock_delay = 300,
604         .pdiv_tohw = plle_p,
605         .div_nmp = &plle_nmp,
606         .freq_table = pll_e_freq_table,
607         .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
608         .fixed_rate = 100000000,
609 };
610 
611 static struct div_nmp pllre_nmp = {
612         .divm_shift = 0,
613         .divm_width = 8,
614         .divn_shift = 8,
615         .divn_width = 8,
616         .divp_shift = 16,
617         .divp_width = 4,
618 };
619 
620 static struct tegra_clk_pll_params pll_re_vco_params = {
621         .input_min = 12000000,
622         .input_max = 1000000000,
623         .cf_min = 12000000,
624         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
625         .vco_min = 300000000,
626         .vco_max = 600000000,
627         .base_reg = PLLRE_BASE,
628         .misc_reg = PLLRE_MISC,
629         .lock_mask = PLLRE_MISC_LOCK,
630         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
631         .lock_delay = 300,
632         .iddq_reg = PLLRE_MISC,
633         .iddq_bit_idx = PLLRE_IDDQ_BIT,
634         .div_nmp = &pllre_nmp,
635         .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
636                  TEGRA_PLL_LOCK_MISC,
637 };
638 
639 /* possible OSC frequencies in Hz */
640 static unsigned long tegra114_input_freq[] = {
641         [ 0] = 13000000,
642         [ 1] = 16800000,
643         [ 4] = 19200000,
644         [ 5] = 38400000,
645         [ 8] = 12000000,
646         [ 9] = 48000000,
647         [12] = 26000000,
648 };
649 
650 #define MASK(x) (BIT(x) - 1)
651 
652 struct utmi_clk_param {
653         /* Oscillator Frequency in KHz */
654         u32 osc_frequency;
655         /* UTMIP PLL Enable Delay Count  */
656         u8 enable_delay_count;
657         /* UTMIP PLL Stable count */
658         u8 stable_count;
659         /*  UTMIP PLL Active delay count */
660         u8 active_delay_count;
661         /* UTMIP PLL Xtal frequency count */
662         u8 xtal_freq_count;
663 };
664 
665 static const struct utmi_clk_param utmi_parameters[] = {
666         {
667                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
668                 .stable_count = 0x33, .active_delay_count = 0x05,
669                 .xtal_freq_count = 0x7f
670         }, {
671                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
672                 .stable_count = 0x4b, .active_delay_count = 0x06,
673                 .xtal_freq_count = 0xbb
674         }, {
675                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
676                 .stable_count = 0x2f, .active_delay_count = 0x04,
677                 .xtal_freq_count = 0x76
678         }, {
679                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
680                 .stable_count = 0x66, .active_delay_count = 0x09,
681                 .xtal_freq_count = 0xfe
682         }, {
683                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
684                 .stable_count = 0x41, .active_delay_count = 0x0a,
685                 .xtal_freq_count = 0xa4
686         },
687 };
688 
689 /* peripheral mux definitions */
690 
691 static const char *mux_plld_out0_plld2_out0[] = {
692         "pll_d_out0", "pll_d2_out0",
693 };
694 #define mux_plld_out0_plld2_out0_idx NULL
695 
696 static const char *mux_pllmcp_clkm[] = {
697         "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
698 };
699 
700 static const struct clk_div_table pll_re_div_table[] = {
701         { .val = 0, .div = 1 },
702         { .val = 1, .div = 2 },
703         { .val = 2, .div = 3 },
704         { .val = 3, .div = 4 },
705         { .val = 4, .div = 5 },
706         { .val = 5, .div = 6 },
707         { .val = 0, .div = 0 },
708 };
709 
710 static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
711         [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
712         [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
713         [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
714         [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
715         [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
716         [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
717         [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
718         [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
719         [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
720         [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
721         [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
722         [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
723         [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
724         [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
725         [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
726         [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
727         [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
728         [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
729         [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
730         [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
731         [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
732         [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
733         [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
734         [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
735         [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
736         [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
737         [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
738         [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
739         [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
740         [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
741         [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
742         [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
743         [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
744         [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
745         [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
746         [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
747         [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
748         [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
749         [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
750         [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
751         [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
752         [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
753         [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
754         [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
755         [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
756         [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
757         [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
758         [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
759         [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
760         [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
761         [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
762         [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
763         [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
764         [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
765         [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
766         [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
767         [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
768         [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
769         [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
770         [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
771         [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
772         [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
773         [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
774         [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
775         [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
776         [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
777         [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
778         [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
779         [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
780         [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
781         [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
782         [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
783         [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
784         [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
785         [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
786         [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
787         [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
788         [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
789         [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
790         [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
791         [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
792         [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
793         [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
794         [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
795         [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
796         [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
797         [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
798         [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
799         [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
800         [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
801         [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
802         [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
803         [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
804         [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
805         [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
806         [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
807         [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
808         [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
809         [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
810         [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
811         [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
812         [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
813         [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
814         [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
815         [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
816         [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
817         [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
818         [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
819         [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
820         [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
821         [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
822         [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
823         [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
824         [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
825         [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
826         [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
827         [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
828         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
829         [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
830         [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
831         [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
832         [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
833         [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
834         [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
835         [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
836         [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
837         [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
838         [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
839         [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
840         [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
841         [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
842         [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
843         [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
844         [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
845         [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
846         [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
847         [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
848         [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
849         [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
850         [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
851         [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
852         [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
853         [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
854         [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
855         [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
856         [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
857         [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
858         [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
859         [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
860         [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
861         [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
862         [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
863         [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
864         [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
865         [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
866         [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
867         [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
868         [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
869         [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
870         [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
871         [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
872         [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
873         [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
874         [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
875         [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
876         [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
877         [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
878         [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
879         [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
880         [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
881         [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
882         [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
883         [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
884         [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
885         [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
886 };
887 
888 static struct tegra_devclk devclks[] __initdata = {
889         { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
890         { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
891         { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
892         { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
893         { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
894         { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
895         { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
896         { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
897         { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
898         { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
899         { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
900         { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
901         { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
902         { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
903         { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
904         { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
905         { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
906         { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
907         { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
908         { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
909         { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
910         { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
911         { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
912         { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
913         { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
914         { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
915         { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
916         { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
917         { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
918         { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
919         { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
920         { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
921         { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
922         { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
923         { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
924         { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
925         { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
926         { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
927         { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
928         { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
929         { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
930         { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
931         { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
932         { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
933         { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
934         { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
935         { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
936         { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
937         { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
938         { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
939         { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
940         { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
941         { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
942         { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
943         { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
944         { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
945         { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
946         { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
947         { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
948         { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
949         { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
950         { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
951         { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
952 };
953 
954 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
955         "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
956 };
957 static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
958         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
959 };
960 
961 static struct tegra_audio_clk_info tegra114_audio_plls[] = {
962         { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
963 };
964 
965 static struct clk **clks;
966 
967 static unsigned long osc_freq;
968 static unsigned long pll_ref_freq;
969 
970 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
971 {
972         struct clk *clk;
973 
974         /* clk_32k */
975         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
976                                       32768);
977         clks[TEGRA114_CLK_CLK_32K] = clk;
978 
979         /* clk_m_div2 */
980         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
981                                         CLK_SET_RATE_PARENT, 1, 2);
982         clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
983 
984         /* clk_m_div4 */
985         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
986                                         CLK_SET_RATE_PARENT, 1, 4);
987         clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
988 
989 }
990 
991 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
992 {
993         unsigned int i;
994         u32 reg;
995 
996         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
997                 if (osc_freq == utmi_parameters[i].osc_frequency)
998                         break;
999         }
1000 
1001         if (i >= ARRAY_SIZE(utmi_parameters)) {
1002                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1003                        osc_freq);
1004                 return;
1005         }
1006 
1007         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1008 
1009         /* Program UTMIP PLL stable and active counts */
1010         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1011         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1012         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1013 
1014         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1015 
1016         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1017                                             active_delay_count);
1018 
1019         /* Remove power downs from UTMIP PLL control bits */
1020         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1021         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1022         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1023 
1024         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1025 
1026         /* Program UTMIP PLL delay and oscillator frequency counts */
1027         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1028         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1029 
1030         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1031                                             enable_delay_count);
1032 
1033         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1034         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1035                                            xtal_freq_count);
1036 
1037         /* Remove power downs from UTMIP PLL control bits */
1038         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1039         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1040         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1041         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1042         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1043 
1044         /* Setup HW control of UTMIPLL */
1045         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1046         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1047         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1048         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1049         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1050 
1051         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1052         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1053         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1054         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1055 
1056         udelay(1);
1057 
1058         /* Setup SW override of UTMIPLL assuming USB2.0
1059            ports are assigned to USB2 */
1060         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1061         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1062         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1063         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1064 
1065         udelay(1);
1066 
1067         /* Enable HW control UTMIPLL */
1068         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1069         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1070         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1071 }
1072 
1073 static void __init tegra114_pll_init(void __iomem *clk_base,
1074                                      void __iomem *pmc)
1075 {
1076         u32 val;
1077         struct clk *clk;
1078 
1079         /* PLLC */
1080         clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1081                         pmc, 0, &pll_c_params, NULL);
1082         clks[TEGRA114_CLK_PLL_C] = clk;
1083 
1084         /* PLLC_OUT1 */
1085         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1086                         clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1087                         8, 8, 1, NULL);
1088         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1089                                 clk_base + PLLC_OUT, 1, 0,
1090                                 CLK_SET_RATE_PARENT, 0, NULL);
1091         clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
1092 
1093         /* PLLC2 */
1094         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1095                              &pll_c2_params, NULL);
1096         clks[TEGRA114_CLK_PLL_C2] = clk;
1097 
1098         /* PLLC3 */
1099         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1100                              &pll_c3_params, NULL);
1101         clks[TEGRA114_CLK_PLL_C3] = clk;
1102 
1103         /* PLLM */
1104         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1105                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1106                              &pll_m_params, NULL);
1107         clks[TEGRA114_CLK_PLL_M] = clk;
1108 
1109         /* PLLM_OUT1 */
1110         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1111                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1112                                 8, 8, 1, NULL);
1113         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1114                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1115                                 CLK_SET_RATE_PARENT, 0, NULL);
1116         clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
1117 
1118         /* PLLM_UD */
1119         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1120                                         CLK_SET_RATE_PARENT, 1, 1);
1121 
1122         /* PLLU */
1123         val = readl(clk_base + pll_u_params.base_reg);
1124         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1125         writel(val, clk_base + pll_u_params.base_reg);
1126 
1127         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1128                             &pll_u_params, &pll_u_lock);
1129         clks[TEGRA114_CLK_PLL_U] = clk;
1130 
1131         tegra114_utmi_param_configure(clk_base);
1132 
1133         /* PLLU_480M */
1134         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1135                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1136                                 22, 0, &pll_u_lock);
1137         clks[TEGRA114_CLK_PLL_U_480M] = clk;
1138 
1139         /* PLLU_60M */
1140         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1141                                         CLK_SET_RATE_PARENT, 1, 8);
1142         clks[TEGRA114_CLK_PLL_U_60M] = clk;
1143 
1144         /* PLLU_48M */
1145         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1146                                         CLK_SET_RATE_PARENT, 1, 10);
1147         clks[TEGRA114_CLK_PLL_U_48M] = clk;
1148 
1149         /* PLLU_12M */
1150         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1151                                         CLK_SET_RATE_PARENT, 1, 40);
1152         clks[TEGRA114_CLK_PLL_U_12M] = clk;
1153 
1154         /* PLLD */
1155         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1156                             &pll_d_params, &pll_d_lock);
1157         clks[TEGRA114_CLK_PLL_D] = clk;
1158 
1159         /* PLLD_OUT0 */
1160         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1161                                         CLK_SET_RATE_PARENT, 1, 2);
1162         clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
1163 
1164         /* PLLD2 */
1165         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1166                             &pll_d2_params, &pll_d2_lock);
1167         clks[TEGRA114_CLK_PLL_D2] = clk;
1168 
1169         /* PLLD2_OUT0 */
1170         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1171                                         CLK_SET_RATE_PARENT, 1, 2);
1172         clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1173 
1174         /* PLLRE */
1175         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1176                              0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1177         clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
1178 
1179         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1180                                          clk_base + PLLRE_BASE, 16, 4, 0,
1181                                          pll_re_div_table, &pll_re_lock);
1182         clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1183 
1184         /* PLLE */
1185         clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1186                                       clk_base, 0, &pll_e_params, NULL);
1187         clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1188 }
1189 
1190 #define CLK_SOURCE_VI_SENSOR 0x1a8
1191 
1192 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1193         MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1194 };
1195 
1196 static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1197                                             void __iomem *pmc_base)
1198 {
1199         struct clk *clk;
1200         struct tegra_periph_init_data *data;
1201         unsigned int i;
1202 
1203         /* xusb_ss_div2 */
1204         clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1205                                         1, 2);
1206         clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1207 
1208         /* dsia mux */
1209         clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1210                                ARRAY_SIZE(mux_plld_out0_plld2_out0),
1211                                CLK_SET_RATE_NO_REPARENT,
1212                                clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1213         clks[TEGRA114_CLK_DSIA_MUX] = clk;
1214 
1215         /* dsib mux */
1216         clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1217                                ARRAY_SIZE(mux_plld_out0_plld2_out0),
1218                                CLK_SET_RATE_NO_REPARENT,
1219                                clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1220         clks[TEGRA114_CLK_DSIB_MUX] = clk;
1221 
1222         clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1223                                              0, 48, periph_clk_enb_refcnt);
1224         clks[TEGRA114_CLK_DSIA] = clk;
1225 
1226         clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1227                                              0, 82, periph_clk_enb_refcnt);
1228         clks[TEGRA114_CLK_DSIB] = clk;
1229 
1230         /* emc mux */
1231         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1232                                ARRAY_SIZE(mux_pllmcp_clkm),
1233                                CLK_SET_RATE_NO_REPARENT,
1234                                clk_base + CLK_SOURCE_EMC,
1235                                29, 3, 0, &emc_lock);
1236 
1237         clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1238                                     &emc_lock);
1239         clks[TEGRA114_CLK_MC] = clk;
1240 
1241         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1242                 data = &tegra_periph_clk_list[i];
1243                 clk = tegra_clk_register_periph(data->name,
1244                         data->p.parent_names, data->num_parents,
1245                         &data->periph, clk_base, data->offset, data->flags);
1246                 clks[data->clk_id] = clk;
1247         }
1248 
1249         tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1250                                 &pll_p_params);
1251 }
1252 
1253 /* Tegra114 CPU clock and reset control functions */
1254 static void tegra114_wait_cpu_in_reset(u32 cpu)
1255 {
1256         unsigned int reg;
1257 
1258         do {
1259                 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1260                 cpu_relax();
1261         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1262 }
1263 
1264 static void tegra114_disable_cpu_clock(u32 cpu)
1265 {
1266         /* flow controller would take care in the power sequence. */
1267 }
1268 
1269 #ifdef CONFIG_PM_SLEEP
1270 static void tegra114_cpu_clock_suspend(void)
1271 {
1272         /* switch coresite to clk_m, save off original source */
1273         tegra114_cpu_clk_sctx.clk_csite_src =
1274                                 readl(clk_base + CLK_SOURCE_CSITE);
1275         writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1276 
1277         tegra114_cpu_clk_sctx.cclkg_burst =
1278                                 readl(clk_base + CCLKG_BURST_POLICY);
1279         tegra114_cpu_clk_sctx.cclkg_divider =
1280                                 readl(clk_base + CCLKG_BURST_POLICY + 4);
1281 }
1282 
1283 static void tegra114_cpu_clock_resume(void)
1284 {
1285         writel(tegra114_cpu_clk_sctx.clk_csite_src,
1286                                         clk_base + CLK_SOURCE_CSITE);
1287 
1288         writel(tegra114_cpu_clk_sctx.cclkg_burst,
1289                                         clk_base + CCLKG_BURST_POLICY);
1290         writel(tegra114_cpu_clk_sctx.cclkg_divider,
1291                                         clk_base + CCLKG_BURST_POLICY + 4);
1292 }
1293 #endif
1294 
1295 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1296         .wait_for_reset = tegra114_wait_cpu_in_reset,
1297         .disable_clock  = tegra114_disable_cpu_clock,
1298 #ifdef CONFIG_PM_SLEEP
1299         .suspend        = tegra114_cpu_clock_suspend,
1300         .resume         = tegra114_cpu_clock_resume,
1301 #endif
1302 };
1303 
1304 static const struct of_device_id pmc_match[] __initconst = {
1305         { .compatible = "nvidia,tegra114-pmc" },
1306         { },
1307 };
1308 
1309 /*
1310  * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1311  * breaks
1312  */
1313 static struct tegra_clk_init_table init_table[] __initdata = {
1314         { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1315         { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1316         { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1317         { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1318         { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
1319         { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
1320         { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
1321         { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
1322         { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
1323         { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1324         { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1325         { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1326         { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1327         { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1328         { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1329         { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
1330         { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
1331         { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1332         { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1333         { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1334         { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1335         { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1336         { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1337         { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1338         { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1339         { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1340         { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1341         { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1342         { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1343         /* must be the last entry */
1344         { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1345 };
1346 
1347 static void __init tegra114_clock_apply_init_table(void)
1348 {
1349         tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1350 }
1351 
1352 /**
1353  * tegra114_car_barrier - wait for pending writes to the CAR to complete
1354  *
1355  * Wait for any outstanding writes to the CAR MMIO space from this CPU
1356  * to complete before continuing execution.  No return value.
1357  */
1358 static void tegra114_car_barrier(void)
1359 {
1360         wmb();          /* probably unnecessary */
1361         readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1362 }
1363 
1364 /**
1365  * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1366  *
1367  * When the CPU rail voltage is in the high-voltage range, use the
1368  * built-in hardwired clock propagation delays in the CPU clock
1369  * shaper.  No return value.
1370  */
1371 void tegra114_clock_tune_cpu_trimmers_high(void)
1372 {
1373         u32 select = 0;
1374 
1375         /* Use hardwired rise->rise & fall->fall clock propagation delays */
1376         select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1377                     CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1378                     CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1379         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1380 
1381         tegra114_car_barrier();
1382 }
1383 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1384 
1385 /**
1386  * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1387  *
1388  * When the CPU rail voltage is in the low-voltage range, use the
1389  * extended clock propagation delays set by
1390  * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
1391  * maintain the input clock duty cycle that the FCPU subsystem
1392  * expects.  No return value.
1393  */
1394 void tegra114_clock_tune_cpu_trimmers_low(void)
1395 {
1396         u32 select = 0;
1397 
1398         /*
1399          * Use software-specified rise->rise & fall->fall clock
1400          * propagation delays (from
1401          * tegra114_clock_tune_cpu_trimmers_init()
1402          */
1403         select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1404                    CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1405                    CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1406         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1407 
1408         tegra114_car_barrier();
1409 }
1410 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1411 
1412 /**
1413  * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1414  *
1415  * Program extended clock propagation delays into the FCPU clock
1416  * shaper and enable them.  XXX Define the purpose - peak current
1417  * reduction?  No return value.
1418  */
1419 /* XXX Initial voltage rail state assumption issues? */
1420 void tegra114_clock_tune_cpu_trimmers_init(void)
1421 {
1422         u32 dr = 0, r = 0;
1423 
1424         /* Increment the rise->rise clock delay by four steps */
1425         r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1426               CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1427               CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1428         writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1429 
1430         /*
1431          * Use the rise->rise clock propagation delay specified in the
1432          * r field
1433          */
1434         dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1435                CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1436                CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1437         writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1438 
1439         tegra114_clock_tune_cpu_trimmers_low();
1440 }
1441 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1442 
1443 /**
1444  * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1445  *
1446  * Assert the reset line of the DFLL's DVCO.  No return value.
1447  */
1448 void tegra114_clock_assert_dfll_dvco_reset(void)
1449 {
1450         u32 v;
1451 
1452         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1453         v |= (1 << DVFS_DFLL_RESET_SHIFT);
1454         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1455         tegra114_car_barrier();
1456 }
1457 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1458 
1459 /**
1460  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1461  *
1462  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1463  * operate.  No return value.
1464  */
1465 void tegra114_clock_deassert_dfll_dvco_reset(void)
1466 {
1467         u32 v;
1468 
1469         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1470         v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1471         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1472         tegra114_car_barrier();
1473 }
1474 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1475 
1476 static void __init tegra114_clock_init(struct device_node *np)
1477 {
1478         struct device_node *node;
1479 
1480         clk_base = of_iomap(np, 0);
1481         if (!clk_base) {
1482                 pr_err("ioremap tegra114 CAR failed\n");
1483                 return;
1484         }
1485 
1486         node = of_find_matching_node(NULL, pmc_match);
1487         if (!node) {
1488                 pr_err("Failed to find pmc node\n");
1489                 WARN_ON(1);
1490                 return;
1491         }
1492 
1493         pmc_base = of_iomap(node, 0);
1494         if (!pmc_base) {
1495                 pr_err("Can't map pmc registers\n");
1496                 WARN_ON(1);
1497                 return;
1498         }
1499 
1500         clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1501                                 TEGRA114_CLK_PERIPH_BANKS);
1502         if (!clks)
1503                 return;
1504 
1505         if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1506                                ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
1507                                &pll_ref_freq) < 0)
1508                 return;
1509 
1510         tegra114_fixed_clk_init(clk_base);
1511         tegra114_pll_init(clk_base, pmc_base);
1512         tegra114_periph_clk_init(clk_base, pmc_base);
1513         tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1514                              tegra114_audio_plls,
1515                              ARRAY_SIZE(tegra114_audio_plls));
1516         tegra_pmc_clk_init(pmc_base, tegra114_clks);
1517         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1518                                         &pll_x_params);
1519 
1520         tegra_add_of_provider(np);
1521         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1522 
1523         tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1524 
1525         tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1526 }
1527 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
1528 

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