Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/clk/sunxi/clk-sunxi.c

  1 /*
  2  * Copyright 2013 Emilio López
  3  *
  4  * Emilio López <emilio@elopez.com.ar>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/clk.h>
 18 #include <linux/clk-provider.h>
 19 #include <linux/clkdev.h>
 20 #include <linux/of.h>
 21 #include <linux/of_address.h>
 22 #include <linux/reset-controller.h>
 23 #include <linux/slab.h>
 24 #include <linux/spinlock.h>
 25 #include <linux/log2.h>
 26 
 27 #include "clk-factors.h"
 28 
 29 static DEFINE_SPINLOCK(clk_lock);
 30 
 31 /* Maximum number of parents our clocks have */
 32 #define SUNXI_MAX_PARENTS       5
 33 
 34 /**
 35  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
 36  * PLL1 rate is calculated as follows
 37  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
 38  * parent_rate is always 24Mhz
 39  */
 40 
 41 static void sun4i_get_pll1_factors(struct factors_request *req)
 42 {
 43         u8 div;
 44 
 45         /* Normalize value to a 6M multiple */
 46         div = req->rate / 6000000;
 47         req->rate = 6000000 * div;
 48 
 49         /* m is always zero for pll1 */
 50         req->m = 0;
 51 
 52         /* k is 1 only on these cases */
 53         if (req->rate >= 768000000 || req->rate == 42000000 ||
 54                         req->rate == 54000000)
 55                 req->k = 1;
 56         else
 57                 req->k = 0;
 58 
 59         /* p will be 3 for divs under 10 */
 60         if (div < 10)
 61                 req->p = 3;
 62 
 63         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
 64         else if (div < 20 || (div < 32 && (div & 1)))
 65                 req->p = 2;
 66 
 67         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 68          * of divs between 40-62 */
 69         else if (div < 40 || (div < 64 && (div & 2)))
 70                 req->p = 1;
 71 
 72         /* any other entries have p = 0 */
 73         else
 74                 req->p = 0;
 75 
 76         /* calculate a suitable n based on k and p */
 77         div <<= req->p;
 78         div /= (req->k + 1);
 79         req->n = div / 4;
 80 }
 81 
 82 /**
 83  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
 84  * PLL1 rate is calculated as follows
 85  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
 86  * parent_rate should always be 24MHz
 87  */
 88 static void sun6i_a31_get_pll1_factors(struct factors_request *req)
 89 {
 90         /*
 91          * We can operate only on MHz, this will make our life easier
 92          * later.
 93          */
 94         u32 freq_mhz = req->rate / 1000000;
 95         u32 parent_freq_mhz = req->parent_rate / 1000000;
 96 
 97         /*
 98          * Round down the frequency to the closest multiple of either
 99          * 6 or 16
100          */
101         u32 round_freq_6 = round_down(freq_mhz, 6);
102         u32 round_freq_16 = round_down(freq_mhz, 16);
103 
104         if (round_freq_6 > round_freq_16)
105                 freq_mhz = round_freq_6;
106         else
107                 freq_mhz = round_freq_16;
108 
109         req->rate = freq_mhz * 1000000;
110 
111         /* If the frequency is a multiple of 32 MHz, k is always 3 */
112         if (!(freq_mhz % 32))
113                 req->k = 3;
114         /* If the frequency is a multiple of 9 MHz, k is always 2 */
115         else if (!(freq_mhz % 9))
116                 req->k = 2;
117         /* If the frequency is a multiple of 8 MHz, k is always 1 */
118         else if (!(freq_mhz % 8))
119                 req->k = 1;
120         /* Otherwise, we don't use the k factor */
121         else
122                 req->k = 0;
123 
124         /*
125          * If the frequency is a multiple of 2 but not a multiple of
126          * 3, m is 3. This is the first time we use 6 here, yet we
127          * will use it on several other places.
128          * We use this number because it's the lowest frequency we can
129          * generate (with n = 0, k = 0, m = 3), so every other frequency
130          * somehow relates to this frequency.
131          */
132         if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
133                 req->m = 2;
134         /*
135          * If the frequency is a multiple of 6MHz, but the factor is
136          * odd, m will be 3
137          */
138         else if ((freq_mhz / 6) & 1)
139                 req->m = 3;
140         /* Otherwise, we end up with m = 1 */
141         else
142                 req->m = 1;
143 
144         /* Calculate n thanks to the above factors we already got */
145         req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
146                  - 1;
147 
148         /*
149          * If n end up being outbound, and that we can still decrease
150          * m, do it.
151          */
152         if ((req->n + 1) > 31 && (req->m + 1) > 1) {
153                 req->n = (req->n + 1) / 2 - 1;
154                 req->m = (req->m + 1) / 2 - 1;
155         }
156 }
157 
158 /**
159  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
160  * PLL1 rate is calculated as follows
161  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
162  * parent_rate is always 24Mhz
163  */
164 
165 static void sun8i_a23_get_pll1_factors(struct factors_request *req)
166 {
167         u8 div;
168 
169         /* Normalize value to a 6M multiple */
170         div = req->rate / 6000000;
171         req->rate = 6000000 * div;
172 
173         /* m is always zero for pll1 */
174         req->m = 0;
175 
176         /* k is 1 only on these cases */
177         if (req->rate >= 768000000 || req->rate == 42000000 ||
178                         req->rate == 54000000)
179                 req->k = 1;
180         else
181                 req->k = 0;
182 
183         /* p will be 2 for divs under 20 and odd divs under 32 */
184         if (div < 20 || (div < 32 && (div & 1)))
185                 req->p = 2;
186 
187         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
188          * of divs between 40-62 */
189         else if (div < 40 || (div < 64 && (div & 2)))
190                 req->p = 1;
191 
192         /* any other entries have p = 0 */
193         else
194                 req->p = 0;
195 
196         /* calculate a suitable n based on k and p */
197         div <<= req->p;
198         div /= (req->k + 1);
199         req->n = div / 4 - 1;
200 }
201 
202 /**
203  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
204  * PLL5 rate is calculated as follows
205  * rate = parent_rate * n * (k + 1)
206  * parent_rate is always 24Mhz
207  */
208 
209 static void sun4i_get_pll5_factors(struct factors_request *req)
210 {
211         u8 div;
212 
213         /* Normalize value to a parent_rate multiple (24M) */
214         div = req->rate / req->parent_rate;
215         req->rate = req->parent_rate * div;
216 
217         if (div < 31)
218                 req->k = 0;
219         else if (div / 2 < 31)
220                 req->k = 1;
221         else if (div / 3 < 31)
222                 req->k = 2;
223         else
224                 req->k = 3;
225 
226         req->n = DIV_ROUND_UP(div, (req->k + 1));
227 }
228 
229 /**
230  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
231  * PLL6x2 rate is calculated as follows
232  * rate = parent_rate * (n + 1) * (k + 1)
233  * parent_rate is always 24Mhz
234  */
235 
236 static void sun6i_a31_get_pll6_factors(struct factors_request *req)
237 {
238         u8 div;
239 
240         /* Normalize value to a parent_rate multiple (24M) */
241         div = req->rate / req->parent_rate;
242         req->rate = req->parent_rate * div;
243 
244         req->k = div / 32;
245         if (req->k > 3)
246                 req->k = 3;
247 
248         req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
249 }
250 
251 /**
252  * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
253  * AHB rate is calculated as follows
254  * rate = parent_rate >> p
255  */
256 
257 static void sun5i_a13_get_ahb_factors(struct factors_request *req)
258 {
259         u32 div;
260 
261         /* divide only */
262         if (req->parent_rate < req->rate)
263                 req->rate = req->parent_rate;
264 
265         /*
266          * user manual says valid speed is 8k ~ 276M, but tests show it
267          * can work at speeds up to 300M, just after reparenting to pll6
268          */
269         if (req->rate < 8000)
270                 req->rate = 8000;
271         if (req->rate > 300000000)
272                 req->rate = 300000000;
273 
274         div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
275 
276         /* p = 0 ~ 3 */
277         if (div > 3)
278                 div = 3;
279 
280         req->rate = req->parent_rate >> div;
281 
282         req->p = div;
283 }
284 
285 #define SUN6I_AHB1_PARENT_PLL6  3
286 
287 /**
288  * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
289  * AHB rate is calculated as follows
290  * rate = parent_rate >> p
291  *
292  * if parent is pll6, then
293  * parent_rate = pll6 rate / (m + 1)
294  */
295 
296 static void sun6i_get_ahb1_factors(struct factors_request *req)
297 {
298         u8 div, calcp, calcm = 1;
299 
300         /*
301          * clock can only divide, so we will never be able to achieve
302          * frequencies higher than the parent frequency
303          */
304         if (req->parent_rate && req->rate > req->parent_rate)
305                 req->rate = req->parent_rate;
306 
307         div = DIV_ROUND_UP(req->parent_rate, req->rate);
308 
309         /* calculate pre-divider if parent is pll6 */
310         if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
311                 if (div < 4)
312                         calcp = 0;
313                 else if (div / 2 < 4)
314                         calcp = 1;
315                 else if (div / 4 < 4)
316                         calcp = 2;
317                 else
318                         calcp = 3;
319 
320                 calcm = DIV_ROUND_UP(div, 1 << calcp);
321         } else {
322                 calcp = __roundup_pow_of_two(div);
323                 calcp = calcp > 3 ? 3 : calcp;
324         }
325 
326         req->rate = (req->parent_rate / calcm) >> calcp;
327         req->p = calcp;
328         req->m = calcm - 1;
329 }
330 
331 /**
332  * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
333  *                       parent index
334  */
335 static void sun6i_ahb1_recalc(struct factors_request *req)
336 {
337         req->rate = req->parent_rate;
338 
339         /* apply pre-divider first if parent is pll6 */
340         if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
341                 req->rate /= req->m + 1;
342 
343         /* clk divider */
344         req->rate >>= req->p;
345 }
346 
347 /**
348  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
349  * APB1 rate is calculated as follows
350  * rate = (parent_rate >> p) / (m + 1);
351  */
352 
353 static void sun4i_get_apb1_factors(struct factors_request *req)
354 {
355         u8 calcm, calcp;
356         int div;
357 
358         if (req->parent_rate < req->rate)
359                 req->rate = req->parent_rate;
360 
361         div = DIV_ROUND_UP(req->parent_rate, req->rate);
362 
363         /* Invalid rate! */
364         if (div > 32)
365                 return;
366 
367         if (div <= 4)
368                 calcp = 0;
369         else if (div <= 8)
370                 calcp = 1;
371         else if (div <= 16)
372                 calcp = 2;
373         else
374                 calcp = 3;
375 
376         calcm = (req->parent_rate >> calcp) - 1;
377 
378         req->rate = (req->parent_rate >> calcp) / (calcm + 1);
379         req->m = calcm;
380         req->p = calcp;
381 }
382 
383 
384 
385 
386 /**
387  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
388  * CLK_OUT rate is calculated as follows
389  * rate = (parent_rate >> p) / (m + 1);
390  */
391 
392 static void sun7i_a20_get_out_factors(struct factors_request *req)
393 {
394         u8 div, calcm, calcp;
395 
396         /* These clocks can only divide, so we will never be able to achieve
397          * frequencies higher than the parent frequency */
398         if (req->rate > req->parent_rate)
399                 req->rate = req->parent_rate;
400 
401         div = DIV_ROUND_UP(req->parent_rate, req->rate);
402 
403         if (div < 32)
404                 calcp = 0;
405         else if (div / 2 < 32)
406                 calcp = 1;
407         else if (div / 4 < 32)
408                 calcp = 2;
409         else
410                 calcp = 3;
411 
412         calcm = DIV_ROUND_UP(div, 1 << calcp);
413 
414         req->rate = (req->parent_rate >> calcp) / calcm;
415         req->m = calcm - 1;
416         req->p = calcp;
417 }
418 
419 /**
420  * sunxi_factors_clk_setup() - Setup function for factor clocks
421  */
422 
423 static const struct clk_factors_config sun4i_pll1_config = {
424         .nshift = 8,
425         .nwidth = 5,
426         .kshift = 4,
427         .kwidth = 2,
428         .mshift = 0,
429         .mwidth = 2,
430         .pshift = 16,
431         .pwidth = 2,
432 };
433 
434 static const struct clk_factors_config sun6i_a31_pll1_config = {
435         .nshift = 8,
436         .nwidth = 5,
437         .kshift = 4,
438         .kwidth = 2,
439         .mshift = 0,
440         .mwidth = 2,
441         .n_start = 1,
442 };
443 
444 static const struct clk_factors_config sun8i_a23_pll1_config = {
445         .nshift = 8,
446         .nwidth = 5,
447         .kshift = 4,
448         .kwidth = 2,
449         .mshift = 0,
450         .mwidth = 2,
451         .pshift = 16,
452         .pwidth = 2,
453         .n_start = 1,
454 };
455 
456 static const struct clk_factors_config sun4i_pll5_config = {
457         .nshift = 8,
458         .nwidth = 5,
459         .kshift = 4,
460         .kwidth = 2,
461 };
462 
463 static const struct clk_factors_config sun6i_a31_pll6_config = {
464         .nshift = 8,
465         .nwidth = 5,
466         .kshift = 4,
467         .kwidth = 2,
468         .n_start = 1,
469 };
470 
471 static const struct clk_factors_config sun5i_a13_ahb_config = {
472         .pshift = 4,
473         .pwidth = 2,
474 };
475 
476 static const struct clk_factors_config sun6i_ahb1_config = {
477         .mshift = 6,
478         .mwidth = 2,
479         .pshift = 4,
480         .pwidth = 2,
481 };
482 
483 static const struct clk_factors_config sun4i_apb1_config = {
484         .mshift = 0,
485         .mwidth = 5,
486         .pshift = 16,
487         .pwidth = 2,
488 };
489 
490 /* user manual says "n" but it's really "p" */
491 static const struct clk_factors_config sun7i_a20_out_config = {
492         .mshift = 8,
493         .mwidth = 5,
494         .pshift = 20,
495         .pwidth = 2,
496 };
497 
498 static const struct factors_data sun4i_pll1_data __initconst = {
499         .enable = 31,
500         .table = &sun4i_pll1_config,
501         .getter = sun4i_get_pll1_factors,
502 };
503 
504 static const struct factors_data sun6i_a31_pll1_data __initconst = {
505         .enable = 31,
506         .table = &sun6i_a31_pll1_config,
507         .getter = sun6i_a31_get_pll1_factors,
508 };
509 
510 static const struct factors_data sun8i_a23_pll1_data __initconst = {
511         .enable = 31,
512         .table = &sun8i_a23_pll1_config,
513         .getter = sun8i_a23_get_pll1_factors,
514 };
515 
516 static const struct factors_data sun7i_a20_pll4_data __initconst = {
517         .enable = 31,
518         .table = &sun4i_pll5_config,
519         .getter = sun4i_get_pll5_factors,
520 };
521 
522 static const struct factors_data sun4i_pll5_data __initconst = {
523         .enable = 31,
524         .table = &sun4i_pll5_config,
525         .getter = sun4i_get_pll5_factors,
526         .name = "pll5",
527 };
528 
529 static const struct factors_data sun4i_pll6_data __initconst = {
530         .enable = 31,
531         .table = &sun4i_pll5_config,
532         .getter = sun4i_get_pll5_factors,
533         .name = "pll6",
534 };
535 
536 static const struct factors_data sun6i_a31_pll6_data __initconst = {
537         .enable = 31,
538         .table = &sun6i_a31_pll6_config,
539         .getter = sun6i_a31_get_pll6_factors,
540         .name = "pll6x2",
541 };
542 
543 static const struct factors_data sun5i_a13_ahb_data __initconst = {
544         .mux = 6,
545         .muxmask = BIT(1) | BIT(0),
546         .table = &sun5i_a13_ahb_config,
547         .getter = sun5i_a13_get_ahb_factors,
548 };
549 
550 static const struct factors_data sun6i_ahb1_data __initconst = {
551         .mux = 12,
552         .muxmask = BIT(1) | BIT(0),
553         .table = &sun6i_ahb1_config,
554         .getter = sun6i_get_ahb1_factors,
555         .recalc = sun6i_ahb1_recalc,
556 };
557 
558 static const struct factors_data sun4i_apb1_data __initconst = {
559         .mux = 24,
560         .muxmask = BIT(1) | BIT(0),
561         .table = &sun4i_apb1_config,
562         .getter = sun4i_get_apb1_factors,
563 };
564 
565 static const struct factors_data sun7i_a20_out_data __initconst = {
566         .enable = 31,
567         .mux = 24,
568         .muxmask = BIT(1) | BIT(0),
569         .table = &sun7i_a20_out_config,
570         .getter = sun7i_a20_get_out_factors,
571 };
572 
573 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
574                                                    const struct factors_data *data)
575 {
576         void __iomem *reg;
577 
578         reg = of_iomap(node, 0);
579         if (!reg) {
580                 pr_err("Could not get registers for factors-clk: %s\n",
581                        node->name);
582                 return NULL;
583         }
584 
585         return sunxi_factors_register(node, data, &clk_lock, reg);
586 }
587 
588 static void __init sun4i_pll1_clk_setup(struct device_node *node)
589 {
590         sunxi_factors_clk_setup(node, &sun4i_pll1_data);
591 }
592 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
593                sun4i_pll1_clk_setup);
594 
595 static void __init sun6i_pll1_clk_setup(struct device_node *node)
596 {
597         sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
598 }
599 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
600                sun6i_pll1_clk_setup);
601 
602 static void __init sun8i_pll1_clk_setup(struct device_node *node)
603 {
604         sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
605 }
606 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
607                sun8i_pll1_clk_setup);
608 
609 static void __init sun7i_pll4_clk_setup(struct device_node *node)
610 {
611         sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
612 }
613 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
614                sun7i_pll4_clk_setup);
615 
616 static void __init sun5i_ahb_clk_setup(struct device_node *node)
617 {
618         sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
619 }
620 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
621                sun5i_ahb_clk_setup);
622 
623 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
624 {
625         sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
626 }
627 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
628                sun6i_ahb1_clk_setup);
629 
630 static void __init sun4i_apb1_clk_setup(struct device_node *node)
631 {
632         sunxi_factors_clk_setup(node, &sun4i_apb1_data);
633 }
634 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
635                sun4i_apb1_clk_setup);
636 
637 static void __init sun7i_out_clk_setup(struct device_node *node)
638 {
639         sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
640 }
641 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
642                sun7i_out_clk_setup);
643 
644 
645 /**
646  * sunxi_mux_clk_setup() - Setup function for muxes
647  */
648 
649 #define SUNXI_MUX_GATE_WIDTH    2
650 
651 struct mux_data {
652         u8 shift;
653 };
654 
655 static const struct mux_data sun4i_cpu_mux_data __initconst = {
656         .shift = 16,
657 };
658 
659 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
660         .shift = 12,
661 };
662 
663 static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
664         .shift = 0,
665 };
666 
667 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
668                                                const struct mux_data *data)
669 {
670         struct clk *clk;
671         const char *clk_name = node->name;
672         const char *parents[SUNXI_MAX_PARENTS];
673         void __iomem *reg;
674         int i;
675 
676         reg = of_iomap(node, 0);
677         if (!reg) {
678                 pr_err("Could not map registers for mux-clk: %s\n",
679                        of_node_full_name(node));
680                 return NULL;
681         }
682 
683         i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
684         if (of_property_read_string(node, "clock-output-names", &clk_name)) {
685                 pr_err("%s: could not read clock-output-names from \"%s\"\n",
686                        __func__, of_node_full_name(node));
687                 goto out_unmap;
688         }
689 
690         clk = clk_register_mux(NULL, clk_name, parents, i,
691                                CLK_SET_RATE_PARENT, reg,
692                                data->shift, SUNXI_MUX_GATE_WIDTH,
693                                0, &clk_lock);
694 
695         if (IS_ERR(clk)) {
696                 pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
697                        clk_name, PTR_ERR(clk));
698                 goto out_unmap;
699         }
700 
701         if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
702                 pr_err("%s: failed to add clock provider for %s\n",
703                        __func__, clk_name);
704                 clk_unregister_divider(clk);
705                 goto out_unmap;
706         }
707 
708         return clk;
709 out_unmap:
710         iounmap(reg);
711         return NULL;
712 }
713 
714 static void __init sun4i_cpu_clk_setup(struct device_node *node)
715 {
716         struct clk *clk;
717 
718         clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
719         if (!clk)
720                 return;
721 
722         /* Protect CPU clock */
723         __clk_get(clk);
724         clk_prepare_enable(clk);
725 }
726 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
727                sun4i_cpu_clk_setup);
728 
729 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
730 {
731         sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
732 }
733 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
734                sun6i_ahb1_mux_clk_setup);
735 
736 static void __init sun8i_ahb2_clk_setup(struct device_node *node)
737 {
738         sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
739 }
740 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
741                sun8i_ahb2_clk_setup);
742 
743 
744 /**
745  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
746  */
747 
748 struct div_data {
749         u8      shift;
750         u8      pow;
751         u8      width;
752         const struct clk_div_table *table;
753 };
754 
755 static const struct div_data sun4i_axi_data __initconst = {
756         .shift  = 0,
757         .pow    = 0,
758         .width  = 2,
759 };
760 
761 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
762         { .val = 0, .div = 1 },
763         { .val = 1, .div = 2 },
764         { .val = 2, .div = 3 },
765         { .val = 3, .div = 4 },
766         { .val = 4, .div = 4 },
767         { .val = 5, .div = 4 },
768         { .val = 6, .div = 4 },
769         { .val = 7, .div = 4 },
770         { } /* sentinel */
771 };
772 
773 static const struct div_data sun8i_a23_axi_data __initconst = {
774         .width  = 3,
775         .table  = sun8i_a23_axi_table,
776 };
777 
778 static const struct div_data sun4i_ahb_data __initconst = {
779         .shift  = 4,
780         .pow    = 1,
781         .width  = 2,
782 };
783 
784 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
785         { .val = 0, .div = 2 },
786         { .val = 1, .div = 2 },
787         { .val = 2, .div = 4 },
788         { .val = 3, .div = 8 },
789         { } /* sentinel */
790 };
791 
792 static const struct div_data sun4i_apb0_data __initconst = {
793         .shift  = 8,
794         .pow    = 1,
795         .width  = 2,
796         .table  = sun4i_apb0_table,
797 };
798 
799 static void __init sunxi_divider_clk_setup(struct device_node *node,
800                                            const struct div_data *data)
801 {
802         struct clk *clk;
803         const char *clk_name = node->name;
804         const char *clk_parent;
805         void __iomem *reg;
806 
807         reg = of_iomap(node, 0);
808         if (!reg) {
809                 pr_err("Could not map registers for mux-clk: %s\n",
810                        of_node_full_name(node));
811                 return;
812         }
813 
814         clk_parent = of_clk_get_parent_name(node, 0);
815 
816         if (of_property_read_string(node, "clock-output-names", &clk_name)) {
817                 pr_err("%s: could not read clock-output-names from \"%s\"\n",
818                        __func__, of_node_full_name(node));
819                 goto out_unmap;
820         }
821 
822         clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
823                                          reg, data->shift, data->width,
824                                          data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
825                                          data->table, &clk_lock);
826         if (IS_ERR(clk)) {
827                 pr_err("%s: failed to register divider clock %s: %ld\n",
828                        __func__, clk_name, PTR_ERR(clk));
829                 goto out_unmap;
830         }
831 
832         if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
833                 pr_err("%s: failed to add clock provider for %s\n",
834                        __func__, clk_name);
835                 goto out_unregister;
836         }
837 
838         if (clk_register_clkdev(clk, clk_name, NULL)) {
839                 of_clk_del_provider(node);
840                 goto out_unregister;
841         }
842 
843         return;
844 out_unregister:
845         clk_unregister_divider(clk);
846 
847 out_unmap:
848         iounmap(reg);
849 }
850 
851 static void __init sun4i_ahb_clk_setup(struct device_node *node)
852 {
853         sunxi_divider_clk_setup(node, &sun4i_ahb_data);
854 }
855 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
856                sun4i_ahb_clk_setup);
857 
858 static void __init sun4i_apb0_clk_setup(struct device_node *node)
859 {
860         sunxi_divider_clk_setup(node, &sun4i_apb0_data);
861 }
862 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
863                sun4i_apb0_clk_setup);
864 
865 static void __init sun4i_axi_clk_setup(struct device_node *node)
866 {
867         sunxi_divider_clk_setup(node, &sun4i_axi_data);
868 }
869 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
870                sun4i_axi_clk_setup);
871 
872 static void __init sun8i_axi_clk_setup(struct device_node *node)
873 {
874         sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
875 }
876 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
877                sun8i_axi_clk_setup);
878 
879 
880 
881 /**
882  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
883  */
884 
885 #define SUNXI_GATES_MAX_SIZE    64
886 
887 struct gates_data {
888         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
889 };
890 
891 /**
892  * sunxi_divs_clk_setup() helper data
893  */
894 
895 #define SUNXI_DIVS_MAX_QTY      4
896 #define SUNXI_DIVISOR_WIDTH     2
897 
898 struct divs_data {
899         const struct factors_data *factors; /* data for the factor clock */
900         int ndivs; /* number of outputs */
901         /*
902          * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
903          * self or base factor clock refers to the output from the pll
904          * itself. The remaining refer to fixed or configurable divider
905          * outputs.
906          */
907         struct {
908                 u8 self; /* is it the base factor clock? (only one) */
909                 u8 fixed; /* is it a fixed divisor? if not... */
910                 struct clk_div_table *table; /* is it a table based divisor? */
911                 u8 shift; /* otherwise it's a normal divisor with this shift */
912                 u8 pow;   /* is it power-of-two based? */
913                 u8 gate;  /* is it independently gateable? */
914         } div[SUNXI_DIVS_MAX_QTY];
915 };
916 
917 static struct clk_div_table pll6_sata_tbl[] = {
918         { .val = 0, .div = 6, },
919         { .val = 1, .div = 12, },
920         { .val = 2, .div = 18, },
921         { .val = 3, .div = 24, },
922         { } /* sentinel */
923 };
924 
925 static const struct divs_data pll5_divs_data __initconst = {
926         .factors = &sun4i_pll5_data,
927         .ndivs = 2,
928         .div = {
929                 { .shift = 0, .pow = 0, }, /* M, DDR */
930                 { .shift = 16, .pow = 1, }, /* P, other */
931                 /* No output for the base factor clock */
932         }
933 };
934 
935 static const struct divs_data pll6_divs_data __initconst = {
936         .factors = &sun4i_pll6_data,
937         .ndivs = 4,
938         .div = {
939                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
940                 { .fixed = 2 }, /* P, other */
941                 { .self = 1 }, /* base factor clock, 2x */
942                 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
943         }
944 };
945 
946 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
947         .factors = &sun6i_a31_pll6_data,
948         .ndivs = 2,
949         .div = {
950                 { .fixed = 2 }, /* normal output */
951                 { .self = 1 }, /* base factor clock, 2x */
952         }
953 };
954 
955 /**
956  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
957  *
958  * These clocks look something like this
959  *            ________________________
960  *           |         ___divisor 1---|----> to consumer
961  * parent >--|  pll___/___divisor 2---|----> to consumer
962  *           |        \_______________|____> to consumer
963  *           |________________________|
964  */
965 
966 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
967                                                  const struct divs_data *data)
968 {
969         struct clk_onecell_data *clk_data;
970         const char *parent;
971         const char *clk_name;
972         struct clk **clks, *pclk;
973         struct clk_hw *gate_hw, *rate_hw;
974         const struct clk_ops *rate_ops;
975         struct clk_gate *gate = NULL;
976         struct clk_fixed_factor *fix_factor;
977         struct clk_divider *divider;
978         void __iomem *reg;
979         int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
980         int flags, clkflags;
981 
982         /* if number of children known, use it */
983         if (data->ndivs)
984                 ndivs = data->ndivs;
985 
986         /* Set up factor clock that we will be dividing */
987         pclk = sunxi_factors_clk_setup(node, data->factors);
988         if (!pclk)
989                 return NULL;
990         parent = __clk_get_name(pclk);
991 
992         reg = of_iomap(node, 0);
993         if (!reg) {
994                 pr_err("Could not map registers for divs-clk: %s\n",
995                        of_node_full_name(node));
996                 return NULL;
997         }
998 
999         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1000         if (!clk_data)
1001                 goto out_unmap;
1002 
1003         clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1004         if (!clks)
1005                 goto free_clkdata;
1006 
1007         clk_data->clks = clks;
1008 
1009         /* It's not a good idea to have automatic reparenting changing
1010          * our RAM clock! */
1011         clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1012 
1013         for (i = 0; i < ndivs; i++) {
1014                 if (of_property_read_string_index(node, "clock-output-names",
1015                                                   i, &clk_name) != 0)
1016                         break;
1017 
1018                 /* If this is the base factor clock, only update clks */
1019                 if (data->div[i].self) {
1020                         clk_data->clks[i] = pclk;
1021                         continue;
1022                 }
1023 
1024                 gate_hw = NULL;
1025                 rate_hw = NULL;
1026                 rate_ops = NULL;
1027 
1028                 /* If this leaf clock can be gated, create a gate */
1029                 if (data->div[i].gate) {
1030                         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1031                         if (!gate)
1032                                 goto free_clks;
1033 
1034                         gate->reg = reg;
1035                         gate->bit_idx = data->div[i].gate;
1036                         gate->lock = &clk_lock;
1037 
1038                         gate_hw = &gate->hw;
1039                 }
1040 
1041                 /* Leaves can be fixed or configurable divisors */
1042                 if (data->div[i].fixed) {
1043                         fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1044                         if (!fix_factor)
1045                                 goto free_gate;
1046 
1047                         fix_factor->mult = 1;
1048                         fix_factor->div = data->div[i].fixed;
1049 
1050                         rate_hw = &fix_factor->hw;
1051                         rate_ops = &clk_fixed_factor_ops;
1052                 } else {
1053                         divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1054                         if (!divider)
1055                                 goto free_gate;
1056 
1057                         flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1058 
1059                         divider->reg = reg;
1060                         divider->shift = data->div[i].shift;
1061                         divider->width = SUNXI_DIVISOR_WIDTH;
1062                         divider->flags = flags;
1063                         divider->lock = &clk_lock;
1064                         divider->table = data->div[i].table;
1065 
1066                         rate_hw = &divider->hw;
1067                         rate_ops = &clk_divider_ops;
1068                 }
1069 
1070                 /* Wrap the (potential) gate and the divisor on a composite
1071                  * clock to unify them */
1072                 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1073                                                  NULL, NULL,
1074                                                  rate_hw, rate_ops,
1075                                                  gate_hw, &clk_gate_ops,
1076                                                  clkflags);
1077 
1078                 WARN_ON(IS_ERR(clk_data->clks[i]));
1079         }
1080 
1081         /* Adjust to the real max */
1082         clk_data->clk_num = i;
1083 
1084         if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
1085                 pr_err("%s: failed to add clock provider for %s\n",
1086                        __func__, clk_name);
1087                 goto free_gate;
1088         }
1089 
1090         return clks;
1091 free_gate:
1092         kfree(gate);
1093 free_clks:
1094         kfree(clks);
1095 free_clkdata:
1096         kfree(clk_data);
1097 out_unmap:
1098         iounmap(reg);
1099         return NULL;
1100 }
1101 
1102 static void __init sun4i_pll5_clk_setup(struct device_node *node)
1103 {
1104         struct clk **clks;
1105 
1106         clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
1107         if (!clks)
1108                 return;
1109 
1110         /* Protect PLL5_DDR */
1111         __clk_get(clks[0]);
1112         clk_prepare_enable(clks[0]);
1113 }
1114 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1115                sun4i_pll5_clk_setup);
1116 
1117 static void __init sun4i_pll6_clk_setup(struct device_node *node)
1118 {
1119         sunxi_divs_clk_setup(node, &pll6_divs_data);
1120 }
1121 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1122                sun4i_pll6_clk_setup);
1123 
1124 static void __init sun6i_pll6_clk_setup(struct device_node *node)
1125 {
1126         sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
1127 }
1128 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1129                sun6i_pll6_clk_setup);
1130 

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