Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/clk/sunxi/clk-sunxi.c

  1 /*
  2  * Copyright 2013 Emilio López
  3  *
  4  * Emilio López <emilio@elopez.com.ar>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/clk-provider.h>
 18 #include <linux/clkdev.h>
 19 #include <linux/of.h>
 20 #include <linux/of_address.h>
 21 #include <linux/reset-controller.h>
 22 #include <linux/spinlock.h>
 23 
 24 #include "clk-factors.h"
 25 
 26 static DEFINE_SPINLOCK(clk_lock);
 27 
 28 /* Maximum number of parents our clocks have */
 29 #define SUNXI_MAX_PARENTS       5
 30 
 31 /**
 32  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
 33  * PLL1 rate is calculated as follows
 34  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
 35  * parent_rate is always 24Mhz
 36  */
 37 
 38 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
 39                                    u8 *n, u8 *k, u8 *m, u8 *p)
 40 {
 41         u8 div;
 42 
 43         /* Normalize value to a 6M multiple */
 44         div = *freq / 6000000;
 45         *freq = 6000000 * div;
 46 
 47         /* we were called to round the frequency, we can now return */
 48         if (n == NULL)
 49                 return;
 50 
 51         /* m is always zero for pll1 */
 52         *m = 0;
 53 
 54         /* k is 1 only on these cases */
 55         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
 56                 *k = 1;
 57         else
 58                 *k = 0;
 59 
 60         /* p will be 3 for divs under 10 */
 61         if (div < 10)
 62                 *p = 3;
 63 
 64         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
 65         else if (div < 20 || (div < 32 && (div & 1)))
 66                 *p = 2;
 67 
 68         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 69          * of divs between 40-62 */
 70         else if (div < 40 || (div < 64 && (div & 2)))
 71                 *p = 1;
 72 
 73         /* any other entries have p = 0 */
 74         else
 75                 *p = 0;
 76 
 77         /* calculate a suitable n based on k and p */
 78         div <<= *p;
 79         div /= (*k + 1);
 80         *n = div / 4;
 81 }
 82 
 83 /**
 84  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
 85  * PLL1 rate is calculated as follows
 86  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
 87  * parent_rate should always be 24MHz
 88  */
 89 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
 90                                        u8 *n, u8 *k, u8 *m, u8 *p)
 91 {
 92         /*
 93          * We can operate only on MHz, this will make our life easier
 94          * later.
 95          */
 96         u32 freq_mhz = *freq / 1000000;
 97         u32 parent_freq_mhz = parent_rate / 1000000;
 98 
 99         /*
100          * Round down the frequency to the closest multiple of either
101          * 6 or 16
102          */
103         u32 round_freq_6 = round_down(freq_mhz, 6);
104         u32 round_freq_16 = round_down(freq_mhz, 16);
105 
106         if (round_freq_6 > round_freq_16)
107                 freq_mhz = round_freq_6;
108         else
109                 freq_mhz = round_freq_16;
110 
111         *freq = freq_mhz * 1000000;
112 
113         /*
114          * If the factors pointer are null, we were just called to
115          * round down the frequency.
116          * Exit.
117          */
118         if (n == NULL)
119                 return;
120 
121         /* If the frequency is a multiple of 32 MHz, k is always 3 */
122         if (!(freq_mhz % 32))
123                 *k = 3;
124         /* If the frequency is a multiple of 9 MHz, k is always 2 */
125         else if (!(freq_mhz % 9))
126                 *k = 2;
127         /* If the frequency is a multiple of 8 MHz, k is always 1 */
128         else if (!(freq_mhz % 8))
129                 *k = 1;
130         /* Otherwise, we don't use the k factor */
131         else
132                 *k = 0;
133 
134         /*
135          * If the frequency is a multiple of 2 but not a multiple of
136          * 3, m is 3. This is the first time we use 6 here, yet we
137          * will use it on several other places.
138          * We use this number because it's the lowest frequency we can
139          * generate (with n = 0, k = 0, m = 3), so every other frequency
140          * somehow relates to this frequency.
141          */
142         if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
143                 *m = 2;
144         /*
145          * If the frequency is a multiple of 6MHz, but the factor is
146          * odd, m will be 3
147          */
148         else if ((freq_mhz / 6) & 1)
149                 *m = 3;
150         /* Otherwise, we end up with m = 1 */
151         else
152                 *m = 1;
153 
154         /* Calculate n thanks to the above factors we already got */
155         *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
156 
157         /*
158          * If n end up being outbound, and that we can still decrease
159          * m, do it.
160          */
161         if ((*n + 1) > 31 && (*m + 1) > 1) {
162                 *n = (*n + 1) / 2 - 1;
163                 *m = (*m + 1) / 2 - 1;
164         }
165 }
166 
167 /**
168  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
169  * PLL1 rate is calculated as follows
170  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
171  * parent_rate is always 24Mhz
172  */
173 
174 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
175                                    u8 *n, u8 *k, u8 *m, u8 *p)
176 {
177         u8 div;
178 
179         /* Normalize value to a 6M multiple */
180         div = *freq / 6000000;
181         *freq = 6000000 * div;
182 
183         /* we were called to round the frequency, we can now return */
184         if (n == NULL)
185                 return;
186 
187         /* m is always zero for pll1 */
188         *m = 0;
189 
190         /* k is 1 only on these cases */
191         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
192                 *k = 1;
193         else
194                 *k = 0;
195 
196         /* p will be 2 for divs under 20 and odd divs under 32 */
197         if (div < 20 || (div < 32 && (div & 1)))
198                 *p = 2;
199 
200         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
201          * of divs between 40-62 */
202         else if (div < 40 || (div < 64 && (div & 2)))
203                 *p = 1;
204 
205         /* any other entries have p = 0 */
206         else
207                 *p = 0;
208 
209         /* calculate a suitable n based on k and p */
210         div <<= *p;
211         div /= (*k + 1);
212         *n = div / 4 - 1;
213 }
214 
215 /**
216  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
217  * PLL5 rate is calculated as follows
218  * rate = parent_rate * n * (k + 1)
219  * parent_rate is always 24Mhz
220  */
221 
222 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
223                                    u8 *n, u8 *k, u8 *m, u8 *p)
224 {
225         u8 div;
226 
227         /* Normalize value to a parent_rate multiple (24M) */
228         div = *freq / parent_rate;
229         *freq = parent_rate * div;
230 
231         /* we were called to round the frequency, we can now return */
232         if (n == NULL)
233                 return;
234 
235         if (div < 31)
236                 *k = 0;
237         else if (div / 2 < 31)
238                 *k = 1;
239         else if (div / 3 < 31)
240                 *k = 2;
241         else
242                 *k = 3;
243 
244         *n = DIV_ROUND_UP(div, (*k+1));
245 }
246 
247 /**
248  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
249  * PLL6x2 rate is calculated as follows
250  * rate = parent_rate * (n + 1) * (k + 1)
251  * parent_rate is always 24Mhz
252  */
253 
254 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
255                                        u8 *n, u8 *k, u8 *m, u8 *p)
256 {
257         u8 div;
258 
259         /* Normalize value to a parent_rate multiple (24M) */
260         div = *freq / parent_rate;
261         *freq = parent_rate * div;
262 
263         /* we were called to round the frequency, we can now return */
264         if (n == NULL)
265                 return;
266 
267         *k = div / 32;
268         if (*k > 3)
269                 *k = 3;
270 
271         *n = DIV_ROUND_UP(div, (*k+1)) - 1;
272 }
273 
274 /**
275  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
276  * APB1 rate is calculated as follows
277  * rate = (parent_rate >> p) / (m + 1);
278  */
279 
280 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
281                                    u8 *n, u8 *k, u8 *m, u8 *p)
282 {
283         u8 calcm, calcp;
284 
285         if (parent_rate < *freq)
286                 *freq = parent_rate;
287 
288         parent_rate = DIV_ROUND_UP(parent_rate, *freq);
289 
290         /* Invalid rate! */
291         if (parent_rate > 32)
292                 return;
293 
294         if (parent_rate <= 4)
295                 calcp = 0;
296         else if (parent_rate <= 8)
297                 calcp = 1;
298         else if (parent_rate <= 16)
299                 calcp = 2;
300         else
301                 calcp = 3;
302 
303         calcm = (parent_rate >> calcp) - 1;
304 
305         *freq = (parent_rate >> calcp) / (calcm + 1);
306 
307         /* we were called to round the frequency, we can now return */
308         if (n == NULL)
309                 return;
310 
311         *m = calcm;
312         *p = calcp;
313 }
314 
315 
316 
317 
318 /**
319  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
320  * CLK_OUT rate is calculated as follows
321  * rate = (parent_rate >> p) / (m + 1);
322  */
323 
324 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
325                                       u8 *n, u8 *k, u8 *m, u8 *p)
326 {
327         u8 div, calcm, calcp;
328 
329         /* These clocks can only divide, so we will never be able to achieve
330          * frequencies higher than the parent frequency */
331         if (*freq > parent_rate)
332                 *freq = parent_rate;
333 
334         div = DIV_ROUND_UP(parent_rate, *freq);
335 
336         if (div < 32)
337                 calcp = 0;
338         else if (div / 2 < 32)
339                 calcp = 1;
340         else if (div / 4 < 32)
341                 calcp = 2;
342         else
343                 calcp = 3;
344 
345         calcm = DIV_ROUND_UP(div, 1 << calcp);
346 
347         *freq = (parent_rate >> calcp) / calcm;
348 
349         /* we were called to round the frequency, we can now return */
350         if (n == NULL)
351                 return;
352 
353         *m = calcm - 1;
354         *p = calcp;
355 }
356 
357 /**
358  * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
359  */
360 
361 void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
362 {
363         #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
364         #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
365 
366         struct clk_hw *hw = __clk_get_hw(clk);
367         struct clk_composite *composite = to_clk_composite(hw);
368         struct clk_hw *rate_hw = composite->rate_hw;
369         struct clk_factors *factors = to_clk_factors(rate_hw);
370         unsigned long flags = 0;
371         u32 reg;
372 
373         if (factors->lock)
374                 spin_lock_irqsave(factors->lock, flags);
375 
376         reg = readl(factors->reg);
377 
378         /* set sample clock phase control */
379         reg &= ~(0x7 << 20);
380         reg |= ((sample & 0x7) << 20);
381 
382         /* set output clock phase control */
383         reg &= ~(0x7 << 8);
384         reg |= ((output & 0x7) << 8);
385 
386         writel(reg, factors->reg);
387 
388         if (factors->lock)
389                 spin_unlock_irqrestore(factors->lock, flags);
390 }
391 EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
392 
393 
394 /**
395  * sunxi_factors_clk_setup() - Setup function for factor clocks
396  */
397 
398 static struct clk_factors_config sun4i_pll1_config = {
399         .nshift = 8,
400         .nwidth = 5,
401         .kshift = 4,
402         .kwidth = 2,
403         .mshift = 0,
404         .mwidth = 2,
405         .pshift = 16,
406         .pwidth = 2,
407 };
408 
409 static struct clk_factors_config sun6i_a31_pll1_config = {
410         .nshift = 8,
411         .nwidth = 5,
412         .kshift = 4,
413         .kwidth = 2,
414         .mshift = 0,
415         .mwidth = 2,
416 };
417 
418 static struct clk_factors_config sun8i_a23_pll1_config = {
419         .nshift = 8,
420         .nwidth = 5,
421         .kshift = 4,
422         .kwidth = 2,
423         .mshift = 0,
424         .mwidth = 2,
425         .pshift = 16,
426         .pwidth = 2,
427         .n_start = 1,
428 };
429 
430 static struct clk_factors_config sun4i_pll5_config = {
431         .nshift = 8,
432         .nwidth = 5,
433         .kshift = 4,
434         .kwidth = 2,
435 };
436 
437 static struct clk_factors_config sun6i_a31_pll6_config = {
438         .nshift = 8,
439         .nwidth = 5,
440         .kshift = 4,
441         .kwidth = 2,
442         .n_start = 1,
443 };
444 
445 static struct clk_factors_config sun4i_apb1_config = {
446         .mshift = 0,
447         .mwidth = 5,
448         .pshift = 16,
449         .pwidth = 2,
450 };
451 
452 /* user manual says "n" but it's really "p" */
453 static struct clk_factors_config sun7i_a20_out_config = {
454         .mshift = 8,
455         .mwidth = 5,
456         .pshift = 20,
457         .pwidth = 2,
458 };
459 
460 static const struct factors_data sun4i_pll1_data __initconst = {
461         .enable = 31,
462         .table = &sun4i_pll1_config,
463         .getter = sun4i_get_pll1_factors,
464 };
465 
466 static const struct factors_data sun6i_a31_pll1_data __initconst = {
467         .enable = 31,
468         .table = &sun6i_a31_pll1_config,
469         .getter = sun6i_a31_get_pll1_factors,
470 };
471 
472 static const struct factors_data sun8i_a23_pll1_data __initconst = {
473         .enable = 31,
474         .table = &sun8i_a23_pll1_config,
475         .getter = sun8i_a23_get_pll1_factors,
476 };
477 
478 static const struct factors_data sun7i_a20_pll4_data __initconst = {
479         .enable = 31,
480         .table = &sun4i_pll5_config,
481         .getter = sun4i_get_pll5_factors,
482 };
483 
484 static const struct factors_data sun4i_pll5_data __initconst = {
485         .enable = 31,
486         .table = &sun4i_pll5_config,
487         .getter = sun4i_get_pll5_factors,
488         .name = "pll5",
489 };
490 
491 static const struct factors_data sun4i_pll6_data __initconst = {
492         .enable = 31,
493         .table = &sun4i_pll5_config,
494         .getter = sun4i_get_pll5_factors,
495         .name = "pll6",
496 };
497 
498 static const struct factors_data sun6i_a31_pll6_data __initconst = {
499         .enable = 31,
500         .table = &sun6i_a31_pll6_config,
501         .getter = sun6i_a31_get_pll6_factors,
502         .name = "pll6x2",
503 };
504 
505 static const struct factors_data sun4i_apb1_data __initconst = {
506         .mux = 24,
507         .muxmask = BIT(1) | BIT(0),
508         .table = &sun4i_apb1_config,
509         .getter = sun4i_get_apb1_factors,
510 };
511 
512 static const struct factors_data sun7i_a20_out_data __initconst = {
513         .enable = 31,
514         .mux = 24,
515         .muxmask = BIT(1) | BIT(0),
516         .table = &sun7i_a20_out_config,
517         .getter = sun7i_a20_get_out_factors,
518 };
519 
520 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
521                                                    const struct factors_data *data)
522 {
523         return sunxi_factors_register(node, data, &clk_lock);
524 }
525 
526 
527 
528 /**
529  * sunxi_mux_clk_setup() - Setup function for muxes
530  */
531 
532 #define SUNXI_MUX_GATE_WIDTH    2
533 
534 struct mux_data {
535         u8 shift;
536 };
537 
538 static const struct mux_data sun4i_cpu_mux_data __initconst = {
539         .shift = 16,
540 };
541 
542 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
543         .shift = 12,
544 };
545 
546 static void __init sunxi_mux_clk_setup(struct device_node *node,
547                                        struct mux_data *data)
548 {
549         struct clk *clk;
550         const char *clk_name = node->name;
551         const char *parents[SUNXI_MAX_PARENTS];
552         void __iomem *reg;
553         int i = 0;
554 
555         reg = of_iomap(node, 0);
556 
557         while (i < SUNXI_MAX_PARENTS &&
558                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
559                 i++;
560 
561         of_property_read_string(node, "clock-output-names", &clk_name);
562 
563         clk = clk_register_mux(NULL, clk_name, parents, i,
564                                CLK_SET_RATE_NO_REPARENT, reg,
565                                data->shift, SUNXI_MUX_GATE_WIDTH,
566                                0, &clk_lock);
567 
568         if (clk) {
569                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
570                 clk_register_clkdev(clk, clk_name, NULL);
571         }
572 }
573 
574 
575 
576 /**
577  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
578  */
579 
580 struct div_data {
581         u8      shift;
582         u8      pow;
583         u8      width;
584         const struct clk_div_table *table;
585 };
586 
587 static const struct div_data sun4i_axi_data __initconst = {
588         .shift  = 0,
589         .pow    = 0,
590         .width  = 2,
591 };
592 
593 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
594         { .val = 0, .div = 1 },
595         { .val = 1, .div = 2 },
596         { .val = 2, .div = 3 },
597         { .val = 3, .div = 4 },
598         { .val = 4, .div = 4 },
599         { .val = 5, .div = 4 },
600         { .val = 6, .div = 4 },
601         { .val = 7, .div = 4 },
602         { } /* sentinel */
603 };
604 
605 static const struct div_data sun8i_a23_axi_data __initconst = {
606         .width  = 3,
607         .table  = sun8i_a23_axi_table,
608 };
609 
610 static const struct div_data sun4i_ahb_data __initconst = {
611         .shift  = 4,
612         .pow    = 1,
613         .width  = 2,
614 };
615 
616 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
617         { .val = 0, .div = 2 },
618         { .val = 1, .div = 2 },
619         { .val = 2, .div = 4 },
620         { .val = 3, .div = 8 },
621         { } /* sentinel */
622 };
623 
624 static const struct div_data sun4i_apb0_data __initconst = {
625         .shift  = 8,
626         .pow    = 1,
627         .width  = 2,
628         .table  = sun4i_apb0_table,
629 };
630 
631 static void __init sunxi_divider_clk_setup(struct device_node *node,
632                                            struct div_data *data)
633 {
634         struct clk *clk;
635         const char *clk_name = node->name;
636         const char *clk_parent;
637         void __iomem *reg;
638 
639         reg = of_iomap(node, 0);
640 
641         clk_parent = of_clk_get_parent_name(node, 0);
642 
643         of_property_read_string(node, "clock-output-names", &clk_name);
644 
645         clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
646                                          reg, data->shift, data->width,
647                                          data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
648                                          data->table, &clk_lock);
649         if (clk) {
650                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
651                 clk_register_clkdev(clk, clk_name, NULL);
652         }
653 }
654 
655 
656 
657 /**
658  * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
659  */
660 
661 struct gates_reset_data {
662         void __iomem                    *reg;
663         spinlock_t                      *lock;
664         struct reset_controller_dev     rcdev;
665 };
666 
667 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
668                               unsigned long id)
669 {
670         struct gates_reset_data *data = container_of(rcdev,
671                                                      struct gates_reset_data,
672                                                      rcdev);
673         unsigned long flags;
674         u32 reg;
675 
676         spin_lock_irqsave(data->lock, flags);
677 
678         reg = readl(data->reg);
679         writel(reg & ~BIT(id), data->reg);
680 
681         spin_unlock_irqrestore(data->lock, flags);
682 
683         return 0;
684 }
685 
686 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
687                                 unsigned long id)
688 {
689         struct gates_reset_data *data = container_of(rcdev,
690                                                      struct gates_reset_data,
691                                                      rcdev);
692         unsigned long flags;
693         u32 reg;
694 
695         spin_lock_irqsave(data->lock, flags);
696 
697         reg = readl(data->reg);
698         writel(reg | BIT(id), data->reg);
699 
700         spin_unlock_irqrestore(data->lock, flags);
701 
702         return 0;
703 }
704 
705 static struct reset_control_ops sunxi_gates_reset_ops = {
706         .assert         = sunxi_gates_reset_assert,
707         .deassert       = sunxi_gates_reset_deassert,
708 };
709 
710 /**
711  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
712  */
713 
714 #define SUNXI_GATES_MAX_SIZE    64
715 
716 struct gates_data {
717         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
718         u32 reset_mask;
719 };
720 
721 static const struct gates_data sun4i_axi_gates_data __initconst = {
722         .mask = {1},
723 };
724 
725 static const struct gates_data sun4i_ahb_gates_data __initconst = {
726         .mask = {0x7F77FFF, 0x14FB3F},
727 };
728 
729 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
730         .mask = {0x147667e7, 0x185915},
731 };
732 
733 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
734         .mask = {0x107067e7, 0x185111},
735 };
736 
737 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
738         .mask = {0xEDFE7F62, 0x794F931},
739 };
740 
741 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
742         .mask = { 0x12f77fff, 0x16ff3f },
743 };
744 
745 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
746         .mask = {0x25386742, 0x2505111},
747 };
748 
749 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
750         .mask = {0xF5F12B},
751 };
752 
753 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
754         .mask = {0x1E20003},
755 };
756 
757 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
758         .mask = {0x9B7},
759 };
760 
761 static const struct gates_data sun4i_apb0_gates_data __initconst = {
762         .mask = {0x4EF},
763 };
764 
765 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
766         .mask = {0x469},
767 };
768 
769 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
770         .mask = {0x61},
771 };
772 
773 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
774         .mask = { 0x4ff },
775 };
776 
777 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
778         .mask = {0xEB822},
779 };
780 
781 static const struct gates_data sun4i_apb1_gates_data __initconst = {
782         .mask = {0xFF00F7},
783 };
784 
785 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
786         .mask = {0xf0007},
787 };
788 
789 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
790         .mask = {0xa0007},
791 };
792 
793 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
794         .mask = {0x3031},
795 };
796 
797 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
798         .mask = {0x3021},
799 };
800 
801 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
802         .mask = {0x3F000F},
803 };
804 
805 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
806         .mask = { 0xff80ff },
807 };
808 
809 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
810         .mask = {0x3F001F},
811 };
812 
813 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
814         .mask = {0x1F0007},
815 };
816 
817 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
818         .mask = {0x1C0},
819         .reset_mask = 0x07,
820 };
821 
822 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
823         .mask = {0x140},
824         .reset_mask = 0x03,
825 };
826 
827 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
828         .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
829         .reset_mask = BIT(2) | BIT(1) | BIT(0),
830 };
831 
832 static void __init sunxi_gates_clk_setup(struct device_node *node,
833                                          struct gates_data *data)
834 {
835         struct clk_onecell_data *clk_data;
836         struct gates_reset_data *reset_data;
837         const char *clk_parent;
838         const char *clk_name;
839         void __iomem *reg;
840         int qty;
841         int i = 0;
842         int j = 0;
843 
844         reg = of_iomap(node, 0);
845 
846         clk_parent = of_clk_get_parent_name(node, 0);
847 
848         /* Worst-case size approximation and memory allocation */
849         qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
850         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
851         if (!clk_data)
852                 return;
853         clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
854         if (!clk_data->clks) {
855                 kfree(clk_data);
856                 return;
857         }
858 
859         for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
860                 of_property_read_string_index(node, "clock-output-names",
861                                               j, &clk_name);
862 
863                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
864                                                       clk_parent, 0,
865                                                       reg + 4 * (i/32), i % 32,
866                                                       0, &clk_lock);
867                 WARN_ON(IS_ERR(clk_data->clks[i]));
868                 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
869 
870                 j++;
871         }
872 
873         /* Adjust to the real max */
874         clk_data->clk_num = i;
875 
876         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
877 
878         /* Register a reset controler for gates with reset bits */
879         if (data->reset_mask == 0)
880                 return;
881 
882         reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
883         if (!reset_data)
884                 return;
885 
886         reset_data->reg = reg;
887         reset_data->lock = &clk_lock;
888         reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
889         reset_data->rcdev.ops = &sunxi_gates_reset_ops;
890         reset_data->rcdev.of_node = node;
891         reset_controller_register(&reset_data->rcdev);
892 }
893 
894 
895 
896 /**
897  * sunxi_divs_clk_setup() helper data
898  */
899 
900 #define SUNXI_DIVS_MAX_QTY      2
901 #define SUNXI_DIVISOR_WIDTH     2
902 
903 struct divs_data {
904         const struct factors_data *factors; /* data for the factor clock */
905         int ndivs; /* number of children */
906         struct {
907                 u8 fixed; /* is it a fixed divisor? if not... */
908                 struct clk_div_table *table; /* is it a table based divisor? */
909                 u8 shift; /* otherwise it's a normal divisor with this shift */
910                 u8 pow;   /* is it power-of-two based? */
911                 u8 gate;  /* is it independently gateable? */
912         } div[SUNXI_DIVS_MAX_QTY];
913 };
914 
915 static struct clk_div_table pll6_sata_tbl[] = {
916         { .val = 0, .div = 6, },
917         { .val = 1, .div = 12, },
918         { .val = 2, .div = 18, },
919         { .val = 3, .div = 24, },
920         { } /* sentinel */
921 };
922 
923 static const struct divs_data pll5_divs_data __initconst = {
924         .factors = &sun4i_pll5_data,
925         .ndivs = 2,
926         .div = {
927                 { .shift = 0, .pow = 0, }, /* M, DDR */
928                 { .shift = 16, .pow = 1, }, /* P, other */
929         }
930 };
931 
932 static const struct divs_data pll6_divs_data __initconst = {
933         .factors = &sun4i_pll6_data,
934         .ndivs = 2,
935         .div = {
936                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
937                 { .fixed = 2 }, /* P, other */
938         }
939 };
940 
941 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
942         .factors = &sun6i_a31_pll6_data,
943         .ndivs = 1,
944         .div = {
945                 { .fixed = 2 }, /* normal output */
946         }
947 };
948 
949 /**
950  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
951  *
952  * These clocks look something like this
953  *            ________________________
954  *           |         ___divisor 1---|----> to consumer
955  * parent >--|  pll___/___divisor 2---|----> to consumer
956  *           |        \_______________|____> to consumer
957  *           |________________________|
958  */
959 
960 static void __init sunxi_divs_clk_setup(struct device_node *node,
961                                         struct divs_data *data)
962 {
963         struct clk_onecell_data *clk_data;
964         const char *parent;
965         const char *clk_name;
966         struct clk **clks, *pclk;
967         struct clk_hw *gate_hw, *rate_hw;
968         const struct clk_ops *rate_ops;
969         struct clk_gate *gate = NULL;
970         struct clk_fixed_factor *fix_factor;
971         struct clk_divider *divider;
972         void __iomem *reg;
973         int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
974         int flags, clkflags;
975 
976         /* Set up factor clock that we will be dividing */
977         pclk = sunxi_factors_clk_setup(node, data->factors);
978         parent = __clk_get_name(pclk);
979 
980         reg = of_iomap(node, 0);
981 
982         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
983         if (!clk_data)
984                 return;
985 
986         clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
987         if (!clks)
988                 goto free_clkdata;
989 
990         clk_data->clks = clks;
991 
992         /* It's not a good idea to have automatic reparenting changing
993          * our RAM clock! */
994         clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
995 
996         /* if number of children known, use it */
997         if (data->ndivs)
998                 ndivs = data->ndivs;
999 
1000         for (i = 0; i < ndivs; i++) {
1001                 if (of_property_read_string_index(node, "clock-output-names",
1002                                                   i, &clk_name) != 0)
1003                         break;
1004 
1005                 gate_hw = NULL;
1006                 rate_hw = NULL;
1007                 rate_ops = NULL;
1008 
1009                 /* If this leaf clock can be gated, create a gate */
1010                 if (data->div[i].gate) {
1011                         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1012                         if (!gate)
1013                                 goto free_clks;
1014 
1015                         gate->reg = reg;
1016                         gate->bit_idx = data->div[i].gate;
1017                         gate->lock = &clk_lock;
1018 
1019                         gate_hw = &gate->hw;
1020                 }
1021 
1022                 /* Leaves can be fixed or configurable divisors */
1023                 if (data->div[i].fixed) {
1024                         fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1025                         if (!fix_factor)
1026                                 goto free_gate;
1027 
1028                         fix_factor->mult = 1;
1029                         fix_factor->div = data->div[i].fixed;
1030 
1031                         rate_hw = &fix_factor->hw;
1032                         rate_ops = &clk_fixed_factor_ops;
1033                 } else {
1034                         divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1035                         if (!divider)
1036                                 goto free_gate;
1037 
1038                         flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1039 
1040                         divider->reg = reg;
1041                         divider->shift = data->div[i].shift;
1042                         divider->width = SUNXI_DIVISOR_WIDTH;
1043                         divider->flags = flags;
1044                         divider->lock = &clk_lock;
1045                         divider->table = data->div[i].table;
1046 
1047                         rate_hw = &divider->hw;
1048                         rate_ops = &clk_divider_ops;
1049                 }
1050 
1051                 /* Wrap the (potential) gate and the divisor on a composite
1052                  * clock to unify them */
1053                 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1054                                                  NULL, NULL,
1055                                                  rate_hw, rate_ops,
1056                                                  gate_hw, &clk_gate_ops,
1057                                                  clkflags);
1058 
1059                 WARN_ON(IS_ERR(clk_data->clks[i]));
1060                 clk_register_clkdev(clks[i], clk_name, NULL);
1061         }
1062 
1063         /* The last clock available on the getter is the parent */
1064         clks[i++] = pclk;
1065 
1066         /* Adjust to the real max */
1067         clk_data->clk_num = i;
1068 
1069         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1070 
1071         return;
1072 
1073 free_gate:
1074         kfree(gate);
1075 free_clks:
1076         kfree(clks);
1077 free_clkdata:
1078         kfree(clk_data);
1079 }
1080 
1081 
1082 
1083 /* Matches for factors clocks */
1084 static const struct of_device_id clk_factors_match[] __initconst = {
1085         {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1086         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1087         {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1088         {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1089         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1090         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1091         {}
1092 };
1093 
1094 /* Matches for divider clocks */
1095 static const struct of_device_id clk_div_match[] __initconst = {
1096         {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1097         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1098         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1099         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1100         {}
1101 };
1102 
1103 /* Matches for divided outputs */
1104 static const struct of_device_id clk_divs_match[] __initconst = {
1105         {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1106         {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1107         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1108         {}
1109 };
1110 
1111 /* Matches for mux clocks */
1112 static const struct of_device_id clk_mux_match[] __initconst = {
1113         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1114         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1115         {}
1116 };
1117 
1118 /* Matches for gate clocks */
1119 static const struct of_device_id clk_gates_match[] __initconst = {
1120         {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1121         {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1122         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1123         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1124         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1125         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1126         {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1127         {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1128         {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1129         {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1130         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1131         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1132         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1133         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1134         {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1135         {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1136         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1137         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1138         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1139         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1140         {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1141         {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1142         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1143         {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1144         {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1145         {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1146         {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1147         {}
1148 };
1149 
1150 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1151                                               void *function)
1152 {
1153         struct device_node *np;
1154         const struct div_data *data;
1155         const struct of_device_id *match;
1156         void (*setup_function)(struct device_node *, const void *) = function;
1157 
1158         for_each_matching_node_and_match(np, clk_match, &match) {
1159                 data = match->data;
1160                 setup_function(np, data);
1161         }
1162 }
1163 
1164 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1165 {
1166         unsigned int i;
1167 
1168         /* Register factor clocks */
1169         of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1170 
1171         /* Register divider clocks */
1172         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1173 
1174         /* Register divided output clocks */
1175         of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1176 
1177         /* Register mux clocks */
1178         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1179 
1180         /* Register gate clocks */
1181         of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1182 
1183         /* Protect the clocks that needs to stay on */
1184         for (i = 0; i < nclocks; i++) {
1185                 struct clk *clk = clk_get(NULL, clocks[i]);
1186 
1187                 if (!IS_ERR(clk))
1188                         clk_prepare_enable(clk);
1189         }
1190 }
1191 
1192 static const char *sun4i_a10_critical_clocks[] __initdata = {
1193         "pll5_ddr",
1194         "ahb_sdram",
1195 };
1196 
1197 static void __init sun4i_a10_init_clocks(struct device_node *node)
1198 {
1199         sunxi_init_clocks(sun4i_a10_critical_clocks,
1200                           ARRAY_SIZE(sun4i_a10_critical_clocks));
1201 }
1202 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1203 
1204 static const char *sun5i_critical_clocks[] __initdata = {
1205         "pll5_ddr",
1206         "ahb_sdram",
1207 };
1208 
1209 static void __init sun5i_init_clocks(struct device_node *node)
1210 {
1211         sunxi_init_clocks(sun5i_critical_clocks,
1212                           ARRAY_SIZE(sun5i_critical_clocks));
1213 }
1214 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1215 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1216 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1217 
1218 static const char *sun6i_critical_clocks[] __initdata = {
1219         "cpu",
1220         "ahb1_sdram",
1221 };
1222 
1223 static void __init sun6i_init_clocks(struct device_node *node)
1224 {
1225         sunxi_init_clocks(sun6i_critical_clocks,
1226                           ARRAY_SIZE(sun6i_critical_clocks));
1227 }
1228 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1229 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1230 
1231 static void __init sun9i_init_clocks(struct device_node *node)
1232 {
1233         sunxi_init_clocks(NULL, 0);
1234 }
1235 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
1236 

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