Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/clk/sunxi/clk-sunxi.c

  1 /*
  2  * Copyright 2013 Emilio López
  3  *
  4  * Emilio López <emilio@elopez.com.ar>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/clk-provider.h>
 18 #include <linux/clkdev.h>
 19 #include <linux/of.h>
 20 #include <linux/of_address.h>
 21 #include <linux/reset-controller.h>
 22 #include <linux/spinlock.h>
 23 
 24 #include "clk-factors.h"
 25 
 26 static DEFINE_SPINLOCK(clk_lock);
 27 
 28 /* Maximum number of parents our clocks have */
 29 #define SUNXI_MAX_PARENTS       5
 30 
 31 /**
 32  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
 33  * PLL1 rate is calculated as follows
 34  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
 35  * parent_rate is always 24Mhz
 36  */
 37 
 38 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
 39                                    u8 *n, u8 *k, u8 *m, u8 *p)
 40 {
 41         u8 div;
 42 
 43         /* Normalize value to a 6M multiple */
 44         div = *freq / 6000000;
 45         *freq = 6000000 * div;
 46 
 47         /* we were called to round the frequency, we can now return */
 48         if (n == NULL)
 49                 return;
 50 
 51         /* m is always zero for pll1 */
 52         *m = 0;
 53 
 54         /* k is 1 only on these cases */
 55         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
 56                 *k = 1;
 57         else
 58                 *k = 0;
 59 
 60         /* p will be 3 for divs under 10 */
 61         if (div < 10)
 62                 *p = 3;
 63 
 64         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
 65         else if (div < 20 || (div < 32 && (div & 1)))
 66                 *p = 2;
 67 
 68         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
 69          * of divs between 40-62 */
 70         else if (div < 40 || (div < 64 && (div & 2)))
 71                 *p = 1;
 72 
 73         /* any other entries have p = 0 */
 74         else
 75                 *p = 0;
 76 
 77         /* calculate a suitable n based on k and p */
 78         div <<= *p;
 79         div /= (*k + 1);
 80         *n = div / 4;
 81 }
 82 
 83 /**
 84  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
 85  * PLL1 rate is calculated as follows
 86  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
 87  * parent_rate should always be 24MHz
 88  */
 89 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
 90                                        u8 *n, u8 *k, u8 *m, u8 *p)
 91 {
 92         /*
 93          * We can operate only on MHz, this will make our life easier
 94          * later.
 95          */
 96         u32 freq_mhz = *freq / 1000000;
 97         u32 parent_freq_mhz = parent_rate / 1000000;
 98 
 99         /*
100          * Round down the frequency to the closest multiple of either
101          * 6 or 16
102          */
103         u32 round_freq_6 = round_down(freq_mhz, 6);
104         u32 round_freq_16 = round_down(freq_mhz, 16);
105 
106         if (round_freq_6 > round_freq_16)
107                 freq_mhz = round_freq_6;
108         else
109                 freq_mhz = round_freq_16;
110 
111         *freq = freq_mhz * 1000000;
112 
113         /*
114          * If the factors pointer are null, we were just called to
115          * round down the frequency.
116          * Exit.
117          */
118         if (n == NULL)
119                 return;
120 
121         /* If the frequency is a multiple of 32 MHz, k is always 3 */
122         if (!(freq_mhz % 32))
123                 *k = 3;
124         /* If the frequency is a multiple of 9 MHz, k is always 2 */
125         else if (!(freq_mhz % 9))
126                 *k = 2;
127         /* If the frequency is a multiple of 8 MHz, k is always 1 */
128         else if (!(freq_mhz % 8))
129                 *k = 1;
130         /* Otherwise, we don't use the k factor */
131         else
132                 *k = 0;
133 
134         /*
135          * If the frequency is a multiple of 2 but not a multiple of
136          * 3, m is 3. This is the first time we use 6 here, yet we
137          * will use it on several other places.
138          * We use this number because it's the lowest frequency we can
139          * generate (with n = 0, k = 0, m = 3), so every other frequency
140          * somehow relates to this frequency.
141          */
142         if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
143                 *m = 2;
144         /*
145          * If the frequency is a multiple of 6MHz, but the factor is
146          * odd, m will be 3
147          */
148         else if ((freq_mhz / 6) & 1)
149                 *m = 3;
150         /* Otherwise, we end up with m = 1 */
151         else
152                 *m = 1;
153 
154         /* Calculate n thanks to the above factors we already got */
155         *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
156 
157         /*
158          * If n end up being outbound, and that we can still decrease
159          * m, do it.
160          */
161         if ((*n + 1) > 31 && (*m + 1) > 1) {
162                 *n = (*n + 1) / 2 - 1;
163                 *m = (*m + 1) / 2 - 1;
164         }
165 }
166 
167 /**
168  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
169  * PLL1 rate is calculated as follows
170  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
171  * parent_rate is always 24Mhz
172  */
173 
174 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
175                                    u8 *n, u8 *k, u8 *m, u8 *p)
176 {
177         u8 div;
178 
179         /* Normalize value to a 6M multiple */
180         div = *freq / 6000000;
181         *freq = 6000000 * div;
182 
183         /* we were called to round the frequency, we can now return */
184         if (n == NULL)
185                 return;
186 
187         /* m is always zero for pll1 */
188         *m = 0;
189 
190         /* k is 1 only on these cases */
191         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
192                 *k = 1;
193         else
194                 *k = 0;
195 
196         /* p will be 2 for divs under 20 and odd divs under 32 */
197         if (div < 20 || (div < 32 && (div & 1)))
198                 *p = 2;
199 
200         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
201          * of divs between 40-62 */
202         else if (div < 40 || (div < 64 && (div & 2)))
203                 *p = 1;
204 
205         /* any other entries have p = 0 */
206         else
207                 *p = 0;
208 
209         /* calculate a suitable n based on k and p */
210         div <<= *p;
211         div /= (*k + 1);
212         *n = div / 4 - 1;
213 }
214 
215 /**
216  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
217  * PLL5 rate is calculated as follows
218  * rate = parent_rate * n * (k + 1)
219  * parent_rate is always 24Mhz
220  */
221 
222 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
223                                    u8 *n, u8 *k, u8 *m, u8 *p)
224 {
225         u8 div;
226 
227         /* Normalize value to a parent_rate multiple (24M) */
228         div = *freq / parent_rate;
229         *freq = parent_rate * div;
230 
231         /* we were called to round the frequency, we can now return */
232         if (n == NULL)
233                 return;
234 
235         if (div < 31)
236                 *k = 0;
237         else if (div / 2 < 31)
238                 *k = 1;
239         else if (div / 3 < 31)
240                 *k = 2;
241         else
242                 *k = 3;
243 
244         *n = DIV_ROUND_UP(div, (*k+1));
245 }
246 
247 /**
248  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
249  * PLL6 rate is calculated as follows
250  * rate = parent_rate * n * (k + 1) / 2
251  * parent_rate is always 24Mhz
252  */
253 
254 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
255                                        u8 *n, u8 *k, u8 *m, u8 *p)
256 {
257         u8 div;
258 
259         /*
260          * We always have 24MHz / 2, so we can just say that our
261          * parent clock is 12MHz.
262          */
263         parent_rate = parent_rate / 2;
264 
265         /* Normalize value to a parent_rate multiple (24M / 2) */
266         div = *freq / parent_rate;
267         *freq = parent_rate * div;
268 
269         /* we were called to round the frequency, we can now return */
270         if (n == NULL)
271                 return;
272 
273         *k = div / 32;
274         if (*k > 3)
275                 *k = 3;
276 
277         *n = DIV_ROUND_UP(div, (*k+1));
278 }
279 
280 /**
281  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
282  * APB1 rate is calculated as follows
283  * rate = (parent_rate >> p) / (m + 1);
284  */
285 
286 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
287                                    u8 *n, u8 *k, u8 *m, u8 *p)
288 {
289         u8 calcm, calcp;
290 
291         if (parent_rate < *freq)
292                 *freq = parent_rate;
293 
294         parent_rate = DIV_ROUND_UP(parent_rate, *freq);
295 
296         /* Invalid rate! */
297         if (parent_rate > 32)
298                 return;
299 
300         if (parent_rate <= 4)
301                 calcp = 0;
302         else if (parent_rate <= 8)
303                 calcp = 1;
304         else if (parent_rate <= 16)
305                 calcp = 2;
306         else
307                 calcp = 3;
308 
309         calcm = (parent_rate >> calcp) - 1;
310 
311         *freq = (parent_rate >> calcp) / (calcm + 1);
312 
313         /* we were called to round the frequency, we can now return */
314         if (n == NULL)
315                 return;
316 
317         *m = calcm;
318         *p = calcp;
319 }
320 
321 
322 
323 
324 /**
325  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
326  * CLK_OUT rate is calculated as follows
327  * rate = (parent_rate >> p) / (m + 1);
328  */
329 
330 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
331                                       u8 *n, u8 *k, u8 *m, u8 *p)
332 {
333         u8 div, calcm, calcp;
334 
335         /* These clocks can only divide, so we will never be able to achieve
336          * frequencies higher than the parent frequency */
337         if (*freq > parent_rate)
338                 *freq = parent_rate;
339 
340         div = DIV_ROUND_UP(parent_rate, *freq);
341 
342         if (div < 32)
343                 calcp = 0;
344         else if (div / 2 < 32)
345                 calcp = 1;
346         else if (div / 4 < 32)
347                 calcp = 2;
348         else
349                 calcp = 3;
350 
351         calcm = DIV_ROUND_UP(div, 1 << calcp);
352 
353         *freq = (parent_rate >> calcp) / calcm;
354 
355         /* we were called to round the frequency, we can now return */
356         if (n == NULL)
357                 return;
358 
359         *m = calcm - 1;
360         *p = calcp;
361 }
362 
363 /**
364  * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
365  */
366 
367 void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
368 {
369         #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
370         #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
371 
372         struct clk_hw *hw = __clk_get_hw(clk);
373         struct clk_composite *composite = to_clk_composite(hw);
374         struct clk_hw *rate_hw = composite->rate_hw;
375         struct clk_factors *factors = to_clk_factors(rate_hw);
376         unsigned long flags = 0;
377         u32 reg;
378 
379         if (factors->lock)
380                 spin_lock_irqsave(factors->lock, flags);
381 
382         reg = readl(factors->reg);
383 
384         /* set sample clock phase control */
385         reg &= ~(0x7 << 20);
386         reg |= ((sample & 0x7) << 20);
387 
388         /* set output clock phase control */
389         reg &= ~(0x7 << 8);
390         reg |= ((output & 0x7) << 8);
391 
392         writel(reg, factors->reg);
393 
394         if (factors->lock)
395                 spin_unlock_irqrestore(factors->lock, flags);
396 }
397 EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
398 
399 
400 /**
401  * sunxi_factors_clk_setup() - Setup function for factor clocks
402  */
403 
404 static struct clk_factors_config sun4i_pll1_config = {
405         .nshift = 8,
406         .nwidth = 5,
407         .kshift = 4,
408         .kwidth = 2,
409         .mshift = 0,
410         .mwidth = 2,
411         .pshift = 16,
412         .pwidth = 2,
413 };
414 
415 static struct clk_factors_config sun6i_a31_pll1_config = {
416         .nshift = 8,
417         .nwidth = 5,
418         .kshift = 4,
419         .kwidth = 2,
420         .mshift = 0,
421         .mwidth = 2,
422 };
423 
424 static struct clk_factors_config sun8i_a23_pll1_config = {
425         .nshift = 8,
426         .nwidth = 5,
427         .kshift = 4,
428         .kwidth = 2,
429         .mshift = 0,
430         .mwidth = 2,
431         .pshift = 16,
432         .pwidth = 2,
433         .n_start = 1,
434 };
435 
436 static struct clk_factors_config sun4i_pll5_config = {
437         .nshift = 8,
438         .nwidth = 5,
439         .kshift = 4,
440         .kwidth = 2,
441 };
442 
443 static struct clk_factors_config sun6i_a31_pll6_config = {
444         .nshift = 8,
445         .nwidth = 5,
446         .kshift = 4,
447         .kwidth = 2,
448 };
449 
450 static struct clk_factors_config sun4i_apb1_config = {
451         .mshift = 0,
452         .mwidth = 5,
453         .pshift = 16,
454         .pwidth = 2,
455 };
456 
457 /* user manual says "n" but it's really "p" */
458 static struct clk_factors_config sun7i_a20_out_config = {
459         .mshift = 8,
460         .mwidth = 5,
461         .pshift = 20,
462         .pwidth = 2,
463 };
464 
465 static const struct factors_data sun4i_pll1_data __initconst = {
466         .enable = 31,
467         .table = &sun4i_pll1_config,
468         .getter = sun4i_get_pll1_factors,
469 };
470 
471 static const struct factors_data sun6i_a31_pll1_data __initconst = {
472         .enable = 31,
473         .table = &sun6i_a31_pll1_config,
474         .getter = sun6i_a31_get_pll1_factors,
475 };
476 
477 static const struct factors_data sun8i_a23_pll1_data __initconst = {
478         .enable = 31,
479         .table = &sun8i_a23_pll1_config,
480         .getter = sun8i_a23_get_pll1_factors,
481 };
482 
483 static const struct factors_data sun7i_a20_pll4_data __initconst = {
484         .enable = 31,
485         .table = &sun4i_pll5_config,
486         .getter = sun4i_get_pll5_factors,
487 };
488 
489 static const struct factors_data sun4i_pll5_data __initconst = {
490         .enable = 31,
491         .table = &sun4i_pll5_config,
492         .getter = sun4i_get_pll5_factors,
493         .name = "pll5",
494 };
495 
496 static const struct factors_data sun4i_pll6_data __initconst = {
497         .enable = 31,
498         .table = &sun4i_pll5_config,
499         .getter = sun4i_get_pll5_factors,
500         .name = "pll6",
501 };
502 
503 static const struct factors_data sun6i_a31_pll6_data __initconst = {
504         .enable = 31,
505         .table = &sun6i_a31_pll6_config,
506         .getter = sun6i_a31_get_pll6_factors,
507 };
508 
509 static const struct factors_data sun4i_apb1_data __initconst = {
510         .table = &sun4i_apb1_config,
511         .getter = sun4i_get_apb1_factors,
512 };
513 
514 static const struct factors_data sun7i_a20_out_data __initconst = {
515         .enable = 31,
516         .mux = 24,
517         .table = &sun7i_a20_out_config,
518         .getter = sun7i_a20_get_out_factors,
519 };
520 
521 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
522                                                    const struct factors_data *data)
523 {
524         return sunxi_factors_register(node, data, &clk_lock);
525 }
526 
527 
528 
529 /**
530  * sunxi_mux_clk_setup() - Setup function for muxes
531  */
532 
533 #define SUNXI_MUX_GATE_WIDTH    2
534 
535 struct mux_data {
536         u8 shift;
537 };
538 
539 static const struct mux_data sun4i_cpu_mux_data __initconst = {
540         .shift = 16,
541 };
542 
543 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
544         .shift = 12,
545 };
546 
547 static const struct mux_data sun4i_apb1_mux_data __initconst = {
548         .shift = 24,
549 };
550 
551 static void __init sunxi_mux_clk_setup(struct device_node *node,
552                                        struct mux_data *data)
553 {
554         struct clk *clk;
555         const char *clk_name = node->name;
556         const char *parents[SUNXI_MAX_PARENTS];
557         void __iomem *reg;
558         int i = 0;
559 
560         reg = of_iomap(node, 0);
561 
562         while (i < SUNXI_MAX_PARENTS &&
563                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
564                 i++;
565 
566         of_property_read_string(node, "clock-output-names", &clk_name);
567 
568         clk = clk_register_mux(NULL, clk_name, parents, i,
569                                CLK_SET_RATE_NO_REPARENT, reg,
570                                data->shift, SUNXI_MUX_GATE_WIDTH,
571                                0, &clk_lock);
572 
573         if (clk) {
574                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
575                 clk_register_clkdev(clk, clk_name, NULL);
576         }
577 }
578 
579 
580 
581 /**
582  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
583  */
584 
585 struct div_data {
586         u8      shift;
587         u8      pow;
588         u8      width;
589         const struct clk_div_table *table;
590 };
591 
592 static const struct div_data sun4i_axi_data __initconst = {
593         .shift  = 0,
594         .pow    = 0,
595         .width  = 2,
596 };
597 
598 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
599         { .val = 0, .div = 1 },
600         { .val = 1, .div = 2 },
601         { .val = 2, .div = 3 },
602         { .val = 3, .div = 4 },
603         { .val = 4, .div = 4 },
604         { .val = 5, .div = 4 },
605         { .val = 6, .div = 4 },
606         { .val = 7, .div = 4 },
607         { } /* sentinel */
608 };
609 
610 static const struct div_data sun8i_a23_axi_data __initconst = {
611         .width  = 3,
612         .table  = sun8i_a23_axi_table,
613 };
614 
615 static const struct div_data sun4i_ahb_data __initconst = {
616         .shift  = 4,
617         .pow    = 1,
618         .width  = 2,
619 };
620 
621 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
622         { .val = 0, .div = 2 },
623         { .val = 1, .div = 2 },
624         { .val = 2, .div = 4 },
625         { .val = 3, .div = 8 },
626         { } /* sentinel */
627 };
628 
629 static const struct div_data sun4i_apb0_data __initconst = {
630         .shift  = 8,
631         .pow    = 1,
632         .width  = 2,
633         .table  = sun4i_apb0_table,
634 };
635 
636 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
637         .shift  = 0,
638         .pow    = 0,
639         .width  = 4,
640 };
641 
642 static void __init sunxi_divider_clk_setup(struct device_node *node,
643                                            struct div_data *data)
644 {
645         struct clk *clk;
646         const char *clk_name = node->name;
647         const char *clk_parent;
648         void __iomem *reg;
649 
650         reg = of_iomap(node, 0);
651 
652         clk_parent = of_clk_get_parent_name(node, 0);
653 
654         of_property_read_string(node, "clock-output-names", &clk_name);
655 
656         clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
657                                          reg, data->shift, data->width,
658                                          data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
659                                          data->table, &clk_lock);
660         if (clk) {
661                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
662                 clk_register_clkdev(clk, clk_name, NULL);
663         }
664 }
665 
666 
667 
668 /**
669  * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
670  */
671 
672 struct gates_reset_data {
673         void __iomem                    *reg;
674         spinlock_t                      *lock;
675         struct reset_controller_dev     rcdev;
676 };
677 
678 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
679                               unsigned long id)
680 {
681         struct gates_reset_data *data = container_of(rcdev,
682                                                      struct gates_reset_data,
683                                                      rcdev);
684         unsigned long flags;
685         u32 reg;
686 
687         spin_lock_irqsave(data->lock, flags);
688 
689         reg = readl(data->reg);
690         writel(reg & ~BIT(id), data->reg);
691 
692         spin_unlock_irqrestore(data->lock, flags);
693 
694         return 0;
695 }
696 
697 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
698                                 unsigned long id)
699 {
700         struct gates_reset_data *data = container_of(rcdev,
701                                                      struct gates_reset_data,
702                                                      rcdev);
703         unsigned long flags;
704         u32 reg;
705 
706         spin_lock_irqsave(data->lock, flags);
707 
708         reg = readl(data->reg);
709         writel(reg | BIT(id), data->reg);
710 
711         spin_unlock_irqrestore(data->lock, flags);
712 
713         return 0;
714 }
715 
716 static struct reset_control_ops sunxi_gates_reset_ops = {
717         .assert         = sunxi_gates_reset_assert,
718         .deassert       = sunxi_gates_reset_deassert,
719 };
720 
721 /**
722  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
723  */
724 
725 #define SUNXI_GATES_MAX_SIZE    64
726 
727 struct gates_data {
728         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
729         u32 reset_mask;
730 };
731 
732 static const struct gates_data sun4i_axi_gates_data __initconst = {
733         .mask = {1},
734 };
735 
736 static const struct gates_data sun4i_ahb_gates_data __initconst = {
737         .mask = {0x7F77FFF, 0x14FB3F},
738 };
739 
740 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
741         .mask = {0x147667e7, 0x185915},
742 };
743 
744 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
745         .mask = {0x107067e7, 0x185111},
746 };
747 
748 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
749         .mask = {0xEDFE7F62, 0x794F931},
750 };
751 
752 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
753         .mask = { 0x12f77fff, 0x16ff3f },
754 };
755 
756 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
757         .mask = {0x25386742, 0x2505111},
758 };
759 
760 static const struct gates_data sun4i_apb0_gates_data __initconst = {
761         .mask = {0x4EF},
762 };
763 
764 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
765         .mask = {0x469},
766 };
767 
768 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
769         .mask = {0x61},
770 };
771 
772 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
773         .mask = { 0x4ff },
774 };
775 
776 static const struct gates_data sun4i_apb1_gates_data __initconst = {
777         .mask = {0xFF00F7},
778 };
779 
780 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
781         .mask = {0xf0007},
782 };
783 
784 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
785         .mask = {0xa0007},
786 };
787 
788 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
789         .mask = {0x3031},
790 };
791 
792 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
793         .mask = {0x3021},
794 };
795 
796 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
797         .mask = {0x3F000F},
798 };
799 
800 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
801         .mask = { 0xff80ff },
802 };
803 
804 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
805         .mask = {0x1F0007},
806 };
807 
808 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
809         .mask = {0x1C0},
810         .reset_mask = 0x07,
811 };
812 
813 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
814         .mask = {0x140},
815         .reset_mask = 0x03,
816 };
817 
818 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
819         .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
820         .reset_mask = BIT(2) | BIT(1) | BIT(0),
821 };
822 
823 static void __init sunxi_gates_clk_setup(struct device_node *node,
824                                          struct gates_data *data)
825 {
826         struct clk_onecell_data *clk_data;
827         struct gates_reset_data *reset_data;
828         const char *clk_parent;
829         const char *clk_name;
830         void __iomem *reg;
831         int qty;
832         int i = 0;
833         int j = 0;
834 
835         reg = of_iomap(node, 0);
836 
837         clk_parent = of_clk_get_parent_name(node, 0);
838 
839         /* Worst-case size approximation and memory allocation */
840         qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
841         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
842         if (!clk_data)
843                 return;
844         clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
845         if (!clk_data->clks) {
846                 kfree(clk_data);
847                 return;
848         }
849 
850         for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
851                 of_property_read_string_index(node, "clock-output-names",
852                                               j, &clk_name);
853 
854                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
855                                                       clk_parent, 0,
856                                                       reg + 4 * (i/32), i % 32,
857                                                       0, &clk_lock);
858                 WARN_ON(IS_ERR(clk_data->clks[i]));
859                 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
860 
861                 j++;
862         }
863 
864         /* Adjust to the real max */
865         clk_data->clk_num = i;
866 
867         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
868 
869         /* Register a reset controler for gates with reset bits */
870         if (data->reset_mask == 0)
871                 return;
872 
873         reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
874         if (!reset_data)
875                 return;
876 
877         reset_data->reg = reg;
878         reset_data->lock = &clk_lock;
879         reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
880         reset_data->rcdev.ops = &sunxi_gates_reset_ops;
881         reset_data->rcdev.of_node = node;
882         reset_controller_register(&reset_data->rcdev);
883 }
884 
885 
886 
887 /**
888  * sunxi_divs_clk_setup() helper data
889  */
890 
891 #define SUNXI_DIVS_MAX_QTY      2
892 #define SUNXI_DIVISOR_WIDTH     2
893 
894 struct divs_data {
895         const struct factors_data *factors; /* data for the factor clock */
896         struct {
897                 u8 fixed; /* is it a fixed divisor? if not... */
898                 struct clk_div_table *table; /* is it a table based divisor? */
899                 u8 shift; /* otherwise it's a normal divisor with this shift */
900                 u8 pow;   /* is it power-of-two based? */
901                 u8 gate;  /* is it independently gateable? */
902         } div[SUNXI_DIVS_MAX_QTY];
903 };
904 
905 static struct clk_div_table pll6_sata_tbl[] = {
906         { .val = 0, .div = 6, },
907         { .val = 1, .div = 12, },
908         { .val = 2, .div = 18, },
909         { .val = 3, .div = 24, },
910         { } /* sentinel */
911 };
912 
913 static const struct divs_data pll5_divs_data __initconst = {
914         .factors = &sun4i_pll5_data,
915         .div = {
916                 { .shift = 0, .pow = 0, }, /* M, DDR */
917                 { .shift = 16, .pow = 1, }, /* P, other */
918         }
919 };
920 
921 static const struct divs_data pll6_divs_data __initconst = {
922         .factors = &sun4i_pll6_data,
923         .div = {
924                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
925                 { .fixed = 2 }, /* P, other */
926         }
927 };
928 
929 /**
930  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
931  *
932  * These clocks look something like this
933  *            ________________________
934  *           |         ___divisor 1---|----> to consumer
935  * parent >--|  pll___/___divisor 2---|----> to consumer
936  *           |        \_______________|____> to consumer
937  *           |________________________|
938  */
939 
940 static void __init sunxi_divs_clk_setup(struct device_node *node,
941                                         struct divs_data *data)
942 {
943         struct clk_onecell_data *clk_data;
944         const char *parent;
945         const char *clk_name;
946         struct clk **clks, *pclk;
947         struct clk_hw *gate_hw, *rate_hw;
948         const struct clk_ops *rate_ops;
949         struct clk_gate *gate = NULL;
950         struct clk_fixed_factor *fix_factor;
951         struct clk_divider *divider;
952         void __iomem *reg;
953         int i = 0;
954         int flags, clkflags;
955 
956         /* Set up factor clock that we will be dividing */
957         pclk = sunxi_factors_clk_setup(node, data->factors);
958         parent = __clk_get_name(pclk);
959 
960         reg = of_iomap(node, 0);
961 
962         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
963         if (!clk_data)
964                 return;
965 
966         clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
967         if (!clks)
968                 goto free_clkdata;
969 
970         clk_data->clks = clks;
971 
972         /* It's not a good idea to have automatic reparenting changing
973          * our RAM clock! */
974         clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
975 
976         for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
977                 if (of_property_read_string_index(node, "clock-output-names",
978                                                   i, &clk_name) != 0)
979                         break;
980 
981                 gate_hw = NULL;
982                 rate_hw = NULL;
983                 rate_ops = NULL;
984 
985                 /* If this leaf clock can be gated, create a gate */
986                 if (data->div[i].gate) {
987                         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
988                         if (!gate)
989                                 goto free_clks;
990 
991                         gate->reg = reg;
992                         gate->bit_idx = data->div[i].gate;
993                         gate->lock = &clk_lock;
994 
995                         gate_hw = &gate->hw;
996                 }
997 
998                 /* Leaves can be fixed or configurable divisors */
999                 if (data->div[i].fixed) {
1000                         fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1001                         if (!fix_factor)
1002                                 goto free_gate;
1003 
1004                         fix_factor->mult = 1;
1005                         fix_factor->div = data->div[i].fixed;
1006 
1007                         rate_hw = &fix_factor->hw;
1008                         rate_ops = &clk_fixed_factor_ops;
1009                 } else {
1010                         divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1011                         if (!divider)
1012                                 goto free_gate;
1013 
1014                         flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1015 
1016                         divider->reg = reg;
1017                         divider->shift = data->div[i].shift;
1018                         divider->width = SUNXI_DIVISOR_WIDTH;
1019                         divider->flags = flags;
1020                         divider->lock = &clk_lock;
1021                         divider->table = data->div[i].table;
1022 
1023                         rate_hw = &divider->hw;
1024                         rate_ops = &clk_divider_ops;
1025                 }
1026 
1027                 /* Wrap the (potential) gate and the divisor on a composite
1028                  * clock to unify them */
1029                 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1030                                                  NULL, NULL,
1031                                                  rate_hw, rate_ops,
1032                                                  gate_hw, &clk_gate_ops,
1033                                                  clkflags);
1034 
1035                 WARN_ON(IS_ERR(clk_data->clks[i]));
1036                 clk_register_clkdev(clks[i], clk_name, NULL);
1037         }
1038 
1039         /* The last clock available on the getter is the parent */
1040         clks[i++] = pclk;
1041 
1042         /* Adjust to the real max */
1043         clk_data->clk_num = i;
1044 
1045         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1046 
1047         return;
1048 
1049 free_gate:
1050         kfree(gate);
1051 free_clks:
1052         kfree(clks);
1053 free_clkdata:
1054         kfree(clk_data);
1055 }
1056 
1057 
1058 
1059 /* Matches for factors clocks */
1060 static const struct of_device_id clk_factors_match[] __initconst = {
1061         {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1062         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1063         {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1064         {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1065         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1066         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1067         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1068         {}
1069 };
1070 
1071 /* Matches for divider clocks */
1072 static const struct of_device_id clk_div_match[] __initconst = {
1073         {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1074         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1075         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1076         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1077         {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
1078         {}
1079 };
1080 
1081 /* Matches for divided outputs */
1082 static const struct of_device_id clk_divs_match[] __initconst = {
1083         {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1084         {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1085         {}
1086 };
1087 
1088 /* Matches for mux clocks */
1089 static const struct of_device_id clk_mux_match[] __initconst = {
1090         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1091         {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1092         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1093         {}
1094 };
1095 
1096 /* Matches for gate clocks */
1097 static const struct of_device_id clk_gates_match[] __initconst = {
1098         {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1099         {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1100         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1101         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1102         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1103         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1104         {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1105         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1106         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1107         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1108         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1109         {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1110         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1111         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1112         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1113         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1114         {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1115         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1116         {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1117         {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1118         {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1119         {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1120         {}
1121 };
1122 
1123 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1124                                               void *function)
1125 {
1126         struct device_node *np;
1127         const struct div_data *data;
1128         const struct of_device_id *match;
1129         void (*setup_function)(struct device_node *, const void *) = function;
1130 
1131         for_each_matching_node_and_match(np, clk_match, &match) {
1132                 data = match->data;
1133                 setup_function(np, data);
1134         }
1135 }
1136 
1137 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1138 {
1139         unsigned int i;
1140 
1141         /* Register factor clocks */
1142         of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1143 
1144         /* Register divider clocks */
1145         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1146 
1147         /* Register divided output clocks */
1148         of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1149 
1150         /* Register mux clocks */
1151         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1152 
1153         /* Register gate clocks */
1154         of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1155 
1156         /* Protect the clocks that needs to stay on */
1157         for (i = 0; i < nclocks; i++) {
1158                 struct clk *clk = clk_get(NULL, clocks[i]);
1159 
1160                 if (!IS_ERR(clk))
1161                         clk_prepare_enable(clk);
1162         }
1163 }
1164 
1165 static const char *sun4i_a10_critical_clocks[] __initdata = {
1166         "pll5_ddr",
1167         "ahb_sdram",
1168 };
1169 
1170 static void __init sun4i_a10_init_clocks(struct device_node *node)
1171 {
1172         sunxi_init_clocks(sun4i_a10_critical_clocks,
1173                           ARRAY_SIZE(sun4i_a10_critical_clocks));
1174 }
1175 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1176 
1177 static const char *sun5i_critical_clocks[] __initdata = {
1178         "pll5_ddr",
1179         "ahb_sdram",
1180 };
1181 
1182 static void __init sun5i_init_clocks(struct device_node *node)
1183 {
1184         sunxi_init_clocks(sun5i_critical_clocks,
1185                           ARRAY_SIZE(sun5i_critical_clocks));
1186 }
1187 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1188 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1189 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1190 
1191 static const char *sun6i_critical_clocks[] __initdata = {
1192         "cpu",
1193         "ahb1_sdram",
1194 };
1195 
1196 static void __init sun6i_init_clocks(struct device_node *node)
1197 {
1198         sunxi_init_clocks(sun6i_critical_clocks,
1199                           ARRAY_SIZE(sun6i_critical_clocks));
1200 }
1201 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1202 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1203 

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