Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/clk/sunxi/clk-sunxi.c

  1 /*
  2  * Copyright 2013 Emilio López
  3  *
  4  * Emilio López <emilio@elopez.com.ar>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  *
 11  * This program is distributed in the hope that it will be useful,
 12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14  * GNU General Public License for more details.
 15  */
 16 
 17 #include <linux/clk-provider.h>
 18 #include <linux/clkdev.h>
 19 #include <linux/of.h>
 20 #include <linux/of_address.h>
 21 #include <linux/reset-controller.h>
 22 #include <linux/spinlock.h>
 23 #include <linux/log2.h>
 24 
 25 #include "clk-factors.h"
 26 
 27 static DEFINE_SPINLOCK(clk_lock);
 28 
 29 /**
 30  * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
 31  */
 32 
 33 #define SUN6I_AHB1_MAX_PARENTS          4
 34 #define SUN6I_AHB1_MUX_PARENT_PLL6      3
 35 #define SUN6I_AHB1_MUX_SHIFT            12
 36 /* un-shifted mask is what mux_clk expects */
 37 #define SUN6I_AHB1_MUX_MASK             0x3
 38 #define SUN6I_AHB1_MUX_GET_PARENT(reg)  ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
 39                                          SUN6I_AHB1_MUX_MASK)
 40 
 41 #define SUN6I_AHB1_DIV_SHIFT            4
 42 #define SUN6I_AHB1_DIV_MASK             (0x3 << SUN6I_AHB1_DIV_SHIFT)
 43 #define SUN6I_AHB1_DIV_GET(reg)         ((reg & SUN6I_AHB1_DIV_MASK) >> \
 44                                                 SUN6I_AHB1_DIV_SHIFT)
 45 #define SUN6I_AHB1_DIV_SET(reg, div)    ((reg & ~SUN6I_AHB1_DIV_MASK) | \
 46                                                 (div << SUN6I_AHB1_DIV_SHIFT))
 47 #define SUN6I_AHB1_PLL6_DIV_SHIFT       6
 48 #define SUN6I_AHB1_PLL6_DIV_MASK        (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
 49 #define SUN6I_AHB1_PLL6_DIV_GET(reg)    ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
 50                                                 SUN6I_AHB1_PLL6_DIV_SHIFT)
 51 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
 52                                                 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
 53 
 54 struct sun6i_ahb1_clk {
 55         struct clk_hw hw;
 56         void __iomem *reg;
 57 };
 58 
 59 #define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
 60 
 61 static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
 62                                                 unsigned long parent_rate)
 63 {
 64         struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
 65         unsigned long rate;
 66         u32 reg;
 67 
 68         /* Fetch the register value */
 69         reg = readl(ahb1->reg);
 70 
 71         /* apply pre-divider first if parent is pll6 */
 72         if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
 73                 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
 74 
 75         /* clk divider */
 76         rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
 77 
 78         return rate;
 79 }
 80 
 81 static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
 82                                  u8 parent, unsigned long parent_rate)
 83 {
 84         u8 div, calcp, calcm = 1;
 85 
 86         /*
 87          * clock can only divide, so we will never be able to achieve
 88          * frequencies higher than the parent frequency
 89          */
 90         if (parent_rate && rate > parent_rate)
 91                 rate = parent_rate;
 92 
 93         div = DIV_ROUND_UP(parent_rate, rate);
 94 
 95         /* calculate pre-divider if parent is pll6 */
 96         if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
 97                 if (div < 4)
 98                         calcp = 0;
 99                 else if (div / 2 < 4)
100                         calcp = 1;
101                 else if (div / 4 < 4)
102                         calcp = 2;
103                 else
104                         calcp = 3;
105 
106                 calcm = DIV_ROUND_UP(div, 1 << calcp);
107         } else {
108                 calcp = __roundup_pow_of_two(div);
109                 calcp = calcp > 3 ? 3 : calcp;
110         }
111 
112         /* we were asked to pass back divider values */
113         if (divp) {
114                 *divp = calcp;
115                 *pre_divp = calcm - 1;
116         }
117 
118         return (parent_rate / calcm) >> calcp;
119 }
120 
121 static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
122                                           unsigned long min_rate,
123                                           unsigned long max_rate,
124                                           unsigned long *best_parent_rate,
125                                           struct clk_hw **best_parent_clk)
126 {
127         struct clk *clk = hw->clk, *parent, *best_parent = NULL;
128         int i, num_parents;
129         unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
130 
131         /* find the parent that can help provide the fastest rate <= rate */
132         num_parents = __clk_get_num_parents(clk);
133         for (i = 0; i < num_parents; i++) {
134                 parent = clk_get_parent_by_index(clk, i);
135                 if (!parent)
136                         continue;
137                 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
138                         parent_rate = __clk_round_rate(parent, rate);
139                 else
140                         parent_rate = __clk_get_rate(parent);
141 
142                 child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
143                                                   parent_rate);
144 
145                 if (child_rate <= rate && child_rate > best_child_rate) {
146                         best_parent = parent;
147                         best = parent_rate;
148                         best_child_rate = child_rate;
149                 }
150         }
151 
152         if (best_parent)
153                 *best_parent_clk = __clk_get_hw(best_parent);
154         *best_parent_rate = best;
155 
156         return best_child_rate;
157 }
158 
159 static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
160                                    unsigned long parent_rate)
161 {
162         struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
163         unsigned long flags;
164         u8 div, pre_div, parent;
165         u32 reg;
166 
167         spin_lock_irqsave(&clk_lock, flags);
168 
169         reg = readl(ahb1->reg);
170 
171         /* need to know which parent is used to apply pre-divider */
172         parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
173         sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
174 
175         reg = SUN6I_AHB1_DIV_SET(reg, div);
176         reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
177         writel(reg, ahb1->reg);
178 
179         spin_unlock_irqrestore(&clk_lock, flags);
180 
181         return 0;
182 }
183 
184 static const struct clk_ops sun6i_ahb1_clk_ops = {
185         .determine_rate = sun6i_ahb1_clk_determine_rate,
186         .recalc_rate    = sun6i_ahb1_clk_recalc_rate,
187         .set_rate       = sun6i_ahb1_clk_set_rate,
188 };
189 
190 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
191 {
192         struct clk *clk;
193         struct sun6i_ahb1_clk *ahb1;
194         struct clk_mux *mux;
195         const char *clk_name = node->name;
196         const char *parents[SUN6I_AHB1_MAX_PARENTS];
197         void __iomem *reg;
198         int i = 0;
199 
200         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
201 
202         /* we have a mux, we will have >1 parents */
203         while (i < SUN6I_AHB1_MAX_PARENTS &&
204                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
205                 i++;
206 
207         of_property_read_string(node, "clock-output-names", &clk_name);
208 
209         ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
210         if (!ahb1)
211                 return;
212 
213         mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
214         if (!mux) {
215                 kfree(ahb1);
216                 return;
217         }
218 
219         /* set up clock properties */
220         mux->reg = reg;
221         mux->shift = SUN6I_AHB1_MUX_SHIFT;
222         mux->mask = SUN6I_AHB1_MUX_MASK;
223         mux->lock = &clk_lock;
224         ahb1->reg = reg;
225 
226         clk = clk_register_composite(NULL, clk_name, parents, i,
227                                      &mux->hw, &clk_mux_ops,
228                                      &ahb1->hw, &sun6i_ahb1_clk_ops,
229                                      NULL, NULL, 0);
230 
231         if (!IS_ERR(clk)) {
232                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
233                 clk_register_clkdev(clk, clk_name, NULL);
234         }
235 }
236 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
237 
238 /* Maximum number of parents our clocks have */
239 #define SUNXI_MAX_PARENTS       5
240 
241 /**
242  * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
243  * PLL1 rate is calculated as follows
244  * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
245  * parent_rate is always 24Mhz
246  */
247 
248 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
249                                    u8 *n, u8 *k, u8 *m, u8 *p)
250 {
251         u8 div;
252 
253         /* Normalize value to a 6M multiple */
254         div = *freq / 6000000;
255         *freq = 6000000 * div;
256 
257         /* we were called to round the frequency, we can now return */
258         if (n == NULL)
259                 return;
260 
261         /* m is always zero for pll1 */
262         *m = 0;
263 
264         /* k is 1 only on these cases */
265         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
266                 *k = 1;
267         else
268                 *k = 0;
269 
270         /* p will be 3 for divs under 10 */
271         if (div < 10)
272                 *p = 3;
273 
274         /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
275         else if (div < 20 || (div < 32 && (div & 1)))
276                 *p = 2;
277 
278         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
279          * of divs between 40-62 */
280         else if (div < 40 || (div < 64 && (div & 2)))
281                 *p = 1;
282 
283         /* any other entries have p = 0 */
284         else
285                 *p = 0;
286 
287         /* calculate a suitable n based on k and p */
288         div <<= *p;
289         div /= (*k + 1);
290         *n = div / 4;
291 }
292 
293 /**
294  * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
295  * PLL1 rate is calculated as follows
296  * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
297  * parent_rate should always be 24MHz
298  */
299 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
300                                        u8 *n, u8 *k, u8 *m, u8 *p)
301 {
302         /*
303          * We can operate only on MHz, this will make our life easier
304          * later.
305          */
306         u32 freq_mhz = *freq / 1000000;
307         u32 parent_freq_mhz = parent_rate / 1000000;
308 
309         /*
310          * Round down the frequency to the closest multiple of either
311          * 6 or 16
312          */
313         u32 round_freq_6 = round_down(freq_mhz, 6);
314         u32 round_freq_16 = round_down(freq_mhz, 16);
315 
316         if (round_freq_6 > round_freq_16)
317                 freq_mhz = round_freq_6;
318         else
319                 freq_mhz = round_freq_16;
320 
321         *freq = freq_mhz * 1000000;
322 
323         /*
324          * If the factors pointer are null, we were just called to
325          * round down the frequency.
326          * Exit.
327          */
328         if (n == NULL)
329                 return;
330 
331         /* If the frequency is a multiple of 32 MHz, k is always 3 */
332         if (!(freq_mhz % 32))
333                 *k = 3;
334         /* If the frequency is a multiple of 9 MHz, k is always 2 */
335         else if (!(freq_mhz % 9))
336                 *k = 2;
337         /* If the frequency is a multiple of 8 MHz, k is always 1 */
338         else if (!(freq_mhz % 8))
339                 *k = 1;
340         /* Otherwise, we don't use the k factor */
341         else
342                 *k = 0;
343 
344         /*
345          * If the frequency is a multiple of 2 but not a multiple of
346          * 3, m is 3. This is the first time we use 6 here, yet we
347          * will use it on several other places.
348          * We use this number because it's the lowest frequency we can
349          * generate (with n = 0, k = 0, m = 3), so every other frequency
350          * somehow relates to this frequency.
351          */
352         if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
353                 *m = 2;
354         /*
355          * If the frequency is a multiple of 6MHz, but the factor is
356          * odd, m will be 3
357          */
358         else if ((freq_mhz / 6) & 1)
359                 *m = 3;
360         /* Otherwise, we end up with m = 1 */
361         else
362                 *m = 1;
363 
364         /* Calculate n thanks to the above factors we already got */
365         *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
366 
367         /*
368          * If n end up being outbound, and that we can still decrease
369          * m, do it.
370          */
371         if ((*n + 1) > 31 && (*m + 1) > 1) {
372                 *n = (*n + 1) / 2 - 1;
373                 *m = (*m + 1) / 2 - 1;
374         }
375 }
376 
377 /**
378  * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
379  * PLL1 rate is calculated as follows
380  * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
381  * parent_rate is always 24Mhz
382  */
383 
384 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
385                                    u8 *n, u8 *k, u8 *m, u8 *p)
386 {
387         u8 div;
388 
389         /* Normalize value to a 6M multiple */
390         div = *freq / 6000000;
391         *freq = 6000000 * div;
392 
393         /* we were called to round the frequency, we can now return */
394         if (n == NULL)
395                 return;
396 
397         /* m is always zero for pll1 */
398         *m = 0;
399 
400         /* k is 1 only on these cases */
401         if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
402                 *k = 1;
403         else
404                 *k = 0;
405 
406         /* p will be 2 for divs under 20 and odd divs under 32 */
407         if (div < 20 || (div < 32 && (div & 1)))
408                 *p = 2;
409 
410         /* p will be 1 for even divs under 32, divs under 40 and odd pairs
411          * of divs between 40-62 */
412         else if (div < 40 || (div < 64 && (div & 2)))
413                 *p = 1;
414 
415         /* any other entries have p = 0 */
416         else
417                 *p = 0;
418 
419         /* calculate a suitable n based on k and p */
420         div <<= *p;
421         div /= (*k + 1);
422         *n = div / 4 - 1;
423 }
424 
425 /**
426  * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
427  * PLL5 rate is calculated as follows
428  * rate = parent_rate * n * (k + 1)
429  * parent_rate is always 24Mhz
430  */
431 
432 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
433                                    u8 *n, u8 *k, u8 *m, u8 *p)
434 {
435         u8 div;
436 
437         /* Normalize value to a parent_rate multiple (24M) */
438         div = *freq / parent_rate;
439         *freq = parent_rate * div;
440 
441         /* we were called to round the frequency, we can now return */
442         if (n == NULL)
443                 return;
444 
445         if (div < 31)
446                 *k = 0;
447         else if (div / 2 < 31)
448                 *k = 1;
449         else if (div / 3 < 31)
450                 *k = 2;
451         else
452                 *k = 3;
453 
454         *n = DIV_ROUND_UP(div, (*k+1));
455 }
456 
457 /**
458  * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
459  * PLL6x2 rate is calculated as follows
460  * rate = parent_rate * (n + 1) * (k + 1)
461  * parent_rate is always 24Mhz
462  */
463 
464 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
465                                        u8 *n, u8 *k, u8 *m, u8 *p)
466 {
467         u8 div;
468 
469         /* Normalize value to a parent_rate multiple (24M) */
470         div = *freq / parent_rate;
471         *freq = parent_rate * div;
472 
473         /* we were called to round the frequency, we can now return */
474         if (n == NULL)
475                 return;
476 
477         *k = div / 32;
478         if (*k > 3)
479                 *k = 3;
480 
481         *n = DIV_ROUND_UP(div, (*k+1)) - 1;
482 }
483 
484 /**
485  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
486  * APB1 rate is calculated as follows
487  * rate = (parent_rate >> p) / (m + 1);
488  */
489 
490 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
491                                    u8 *n, u8 *k, u8 *m, u8 *p)
492 {
493         u8 calcm, calcp;
494 
495         if (parent_rate < *freq)
496                 *freq = parent_rate;
497 
498         parent_rate = DIV_ROUND_UP(parent_rate, *freq);
499 
500         /* Invalid rate! */
501         if (parent_rate > 32)
502                 return;
503 
504         if (parent_rate <= 4)
505                 calcp = 0;
506         else if (parent_rate <= 8)
507                 calcp = 1;
508         else if (parent_rate <= 16)
509                 calcp = 2;
510         else
511                 calcp = 3;
512 
513         calcm = (parent_rate >> calcp) - 1;
514 
515         *freq = (parent_rate >> calcp) / (calcm + 1);
516 
517         /* we were called to round the frequency, we can now return */
518         if (n == NULL)
519                 return;
520 
521         *m = calcm;
522         *p = calcp;
523 }
524 
525 
526 
527 
528 /**
529  * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
530  * CLK_OUT rate is calculated as follows
531  * rate = (parent_rate >> p) / (m + 1);
532  */
533 
534 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
535                                       u8 *n, u8 *k, u8 *m, u8 *p)
536 {
537         u8 div, calcm, calcp;
538 
539         /* These clocks can only divide, so we will never be able to achieve
540          * frequencies higher than the parent frequency */
541         if (*freq > parent_rate)
542                 *freq = parent_rate;
543 
544         div = DIV_ROUND_UP(parent_rate, *freq);
545 
546         if (div < 32)
547                 calcp = 0;
548         else if (div / 2 < 32)
549                 calcp = 1;
550         else if (div / 4 < 32)
551                 calcp = 2;
552         else
553                 calcp = 3;
554 
555         calcm = DIV_ROUND_UP(div, 1 << calcp);
556 
557         *freq = (parent_rate >> calcp) / calcm;
558 
559         /* we were called to round the frequency, we can now return */
560         if (n == NULL)
561                 return;
562 
563         *m = calcm - 1;
564         *p = calcp;
565 }
566 
567 /**
568  * sunxi_factors_clk_setup() - Setup function for factor clocks
569  */
570 
571 static struct clk_factors_config sun4i_pll1_config = {
572         .nshift = 8,
573         .nwidth = 5,
574         .kshift = 4,
575         .kwidth = 2,
576         .mshift = 0,
577         .mwidth = 2,
578         .pshift = 16,
579         .pwidth = 2,
580 };
581 
582 static struct clk_factors_config sun6i_a31_pll1_config = {
583         .nshift = 8,
584         .nwidth = 5,
585         .kshift = 4,
586         .kwidth = 2,
587         .mshift = 0,
588         .mwidth = 2,
589         .n_start = 1,
590 };
591 
592 static struct clk_factors_config sun8i_a23_pll1_config = {
593         .nshift = 8,
594         .nwidth = 5,
595         .kshift = 4,
596         .kwidth = 2,
597         .mshift = 0,
598         .mwidth = 2,
599         .pshift = 16,
600         .pwidth = 2,
601         .n_start = 1,
602 };
603 
604 static struct clk_factors_config sun4i_pll5_config = {
605         .nshift = 8,
606         .nwidth = 5,
607         .kshift = 4,
608         .kwidth = 2,
609 };
610 
611 static struct clk_factors_config sun6i_a31_pll6_config = {
612         .nshift = 8,
613         .nwidth = 5,
614         .kshift = 4,
615         .kwidth = 2,
616         .n_start = 1,
617 };
618 
619 static struct clk_factors_config sun4i_apb1_config = {
620         .mshift = 0,
621         .mwidth = 5,
622         .pshift = 16,
623         .pwidth = 2,
624 };
625 
626 /* user manual says "n" but it's really "p" */
627 static struct clk_factors_config sun7i_a20_out_config = {
628         .mshift = 8,
629         .mwidth = 5,
630         .pshift = 20,
631         .pwidth = 2,
632 };
633 
634 static const struct factors_data sun4i_pll1_data __initconst = {
635         .enable = 31,
636         .table = &sun4i_pll1_config,
637         .getter = sun4i_get_pll1_factors,
638 };
639 
640 static const struct factors_data sun6i_a31_pll1_data __initconst = {
641         .enable = 31,
642         .table = &sun6i_a31_pll1_config,
643         .getter = sun6i_a31_get_pll1_factors,
644 };
645 
646 static const struct factors_data sun8i_a23_pll1_data __initconst = {
647         .enable = 31,
648         .table = &sun8i_a23_pll1_config,
649         .getter = sun8i_a23_get_pll1_factors,
650 };
651 
652 static const struct factors_data sun7i_a20_pll4_data __initconst = {
653         .enable = 31,
654         .table = &sun4i_pll5_config,
655         .getter = sun4i_get_pll5_factors,
656 };
657 
658 static const struct factors_data sun4i_pll5_data __initconst = {
659         .enable = 31,
660         .table = &sun4i_pll5_config,
661         .getter = sun4i_get_pll5_factors,
662         .name = "pll5",
663 };
664 
665 static const struct factors_data sun4i_pll6_data __initconst = {
666         .enable = 31,
667         .table = &sun4i_pll5_config,
668         .getter = sun4i_get_pll5_factors,
669         .name = "pll6",
670 };
671 
672 static const struct factors_data sun6i_a31_pll6_data __initconst = {
673         .enable = 31,
674         .table = &sun6i_a31_pll6_config,
675         .getter = sun6i_a31_get_pll6_factors,
676         .name = "pll6x2",
677 };
678 
679 static const struct factors_data sun4i_apb1_data __initconst = {
680         .mux = 24,
681         .muxmask = BIT(1) | BIT(0),
682         .table = &sun4i_apb1_config,
683         .getter = sun4i_get_apb1_factors,
684 };
685 
686 static const struct factors_data sun7i_a20_out_data __initconst = {
687         .enable = 31,
688         .mux = 24,
689         .muxmask = BIT(1) | BIT(0),
690         .table = &sun7i_a20_out_config,
691         .getter = sun7i_a20_get_out_factors,
692 };
693 
694 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
695                                                    const struct factors_data *data)
696 {
697         void __iomem *reg;
698 
699         reg = of_iomap(node, 0);
700         if (!reg) {
701                 pr_err("Could not get registers for factors-clk: %s\n",
702                        node->name);
703                 return NULL;
704         }
705 
706         return sunxi_factors_register(node, data, &clk_lock, reg);
707 }
708 
709 
710 
711 /**
712  * sunxi_mux_clk_setup() - Setup function for muxes
713  */
714 
715 #define SUNXI_MUX_GATE_WIDTH    2
716 
717 struct mux_data {
718         u8 shift;
719 };
720 
721 static const struct mux_data sun4i_cpu_mux_data __initconst = {
722         .shift = 16,
723 };
724 
725 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
726         .shift = 12,
727 };
728 
729 static void __init sunxi_mux_clk_setup(struct device_node *node,
730                                        struct mux_data *data)
731 {
732         struct clk *clk;
733         const char *clk_name = node->name;
734         const char *parents[SUNXI_MAX_PARENTS];
735         void __iomem *reg;
736         int i = 0;
737 
738         reg = of_iomap(node, 0);
739 
740         while (i < SUNXI_MAX_PARENTS &&
741                (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
742                 i++;
743 
744         of_property_read_string(node, "clock-output-names", &clk_name);
745 
746         clk = clk_register_mux(NULL, clk_name, parents, i,
747                                CLK_SET_RATE_PARENT, reg,
748                                data->shift, SUNXI_MUX_GATE_WIDTH,
749                                0, &clk_lock);
750 
751         if (clk) {
752                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
753                 clk_register_clkdev(clk, clk_name, NULL);
754         }
755 }
756 
757 
758 
759 /**
760  * sunxi_divider_clk_setup() - Setup function for simple divider clocks
761  */
762 
763 struct div_data {
764         u8      shift;
765         u8      pow;
766         u8      width;
767         const struct clk_div_table *table;
768 };
769 
770 static const struct div_data sun4i_axi_data __initconst = {
771         .shift  = 0,
772         .pow    = 0,
773         .width  = 2,
774 };
775 
776 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
777         { .val = 0, .div = 1 },
778         { .val = 1, .div = 2 },
779         { .val = 2, .div = 3 },
780         { .val = 3, .div = 4 },
781         { .val = 4, .div = 4 },
782         { .val = 5, .div = 4 },
783         { .val = 6, .div = 4 },
784         { .val = 7, .div = 4 },
785         { } /* sentinel */
786 };
787 
788 static const struct div_data sun8i_a23_axi_data __initconst = {
789         .width  = 3,
790         .table  = sun8i_a23_axi_table,
791 };
792 
793 static const struct div_data sun4i_ahb_data __initconst = {
794         .shift  = 4,
795         .pow    = 1,
796         .width  = 2,
797 };
798 
799 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
800         { .val = 0, .div = 2 },
801         { .val = 1, .div = 2 },
802         { .val = 2, .div = 4 },
803         { .val = 3, .div = 8 },
804         { } /* sentinel */
805 };
806 
807 static const struct div_data sun4i_apb0_data __initconst = {
808         .shift  = 8,
809         .pow    = 1,
810         .width  = 2,
811         .table  = sun4i_apb0_table,
812 };
813 
814 static void __init sunxi_divider_clk_setup(struct device_node *node,
815                                            struct div_data *data)
816 {
817         struct clk *clk;
818         const char *clk_name = node->name;
819         const char *clk_parent;
820         void __iomem *reg;
821 
822         reg = of_iomap(node, 0);
823 
824         clk_parent = of_clk_get_parent_name(node, 0);
825 
826         of_property_read_string(node, "clock-output-names", &clk_name);
827 
828         clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
829                                          reg, data->shift, data->width,
830                                          data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
831                                          data->table, &clk_lock);
832         if (clk) {
833                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
834                 clk_register_clkdev(clk, clk_name, NULL);
835         }
836 }
837 
838 
839 
840 /**
841  * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
842  */
843 
844 struct gates_reset_data {
845         void __iomem                    *reg;
846         spinlock_t                      *lock;
847         struct reset_controller_dev     rcdev;
848 };
849 
850 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
851                               unsigned long id)
852 {
853         struct gates_reset_data *data = container_of(rcdev,
854                                                      struct gates_reset_data,
855                                                      rcdev);
856         unsigned long flags;
857         u32 reg;
858 
859         spin_lock_irqsave(data->lock, flags);
860 
861         reg = readl(data->reg);
862         writel(reg & ~BIT(id), data->reg);
863 
864         spin_unlock_irqrestore(data->lock, flags);
865 
866         return 0;
867 }
868 
869 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
870                                 unsigned long id)
871 {
872         struct gates_reset_data *data = container_of(rcdev,
873                                                      struct gates_reset_data,
874                                                      rcdev);
875         unsigned long flags;
876         u32 reg;
877 
878         spin_lock_irqsave(data->lock, flags);
879 
880         reg = readl(data->reg);
881         writel(reg | BIT(id), data->reg);
882 
883         spin_unlock_irqrestore(data->lock, flags);
884 
885         return 0;
886 }
887 
888 static struct reset_control_ops sunxi_gates_reset_ops = {
889         .assert         = sunxi_gates_reset_assert,
890         .deassert       = sunxi_gates_reset_deassert,
891 };
892 
893 /**
894  * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
895  */
896 
897 #define SUNXI_GATES_MAX_SIZE    64
898 
899 struct gates_data {
900         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
901         u32 reset_mask;
902 };
903 
904 static const struct gates_data sun4i_axi_gates_data __initconst = {
905         .mask = {1},
906 };
907 
908 static const struct gates_data sun4i_ahb_gates_data __initconst = {
909         .mask = {0x7F77FFF, 0x14FB3F},
910 };
911 
912 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
913         .mask = {0x147667e7, 0x185915},
914 };
915 
916 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
917         .mask = {0x107067e7, 0x185111},
918 };
919 
920 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
921         .mask = {0xEDFE7F62, 0x794F931},
922 };
923 
924 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
925         .mask = { 0x12f77fff, 0x16ff3f },
926 };
927 
928 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
929         .mask = {0x25386742, 0x2505111},
930 };
931 
932 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
933         .mask = {0xF5F12B},
934 };
935 
936 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
937         .mask = {0x1E20003},
938 };
939 
940 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
941         .mask = {0x9B7},
942 };
943 
944 static const struct gates_data sun4i_apb0_gates_data __initconst = {
945         .mask = {0x4EF},
946 };
947 
948 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
949         .mask = {0x469},
950 };
951 
952 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
953         .mask = {0x61},
954 };
955 
956 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
957         .mask = { 0x4ff },
958 };
959 
960 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
961         .mask = {0xEB822},
962 };
963 
964 static const struct gates_data sun4i_apb1_gates_data __initconst = {
965         .mask = {0xFF00F7},
966 };
967 
968 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
969         .mask = {0xf0007},
970 };
971 
972 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
973         .mask = {0xa0007},
974 };
975 
976 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
977         .mask = {0x3031},
978 };
979 
980 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
981         .mask = {0x3021},
982 };
983 
984 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
985         .mask = {0x3F000F},
986 };
987 
988 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
989         .mask = { 0xff80ff },
990 };
991 
992 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
993         .mask = {0x3F001F},
994 };
995 
996 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
997         .mask = {0x1F0007},
998 };
999 
1000 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
1001         .mask = {0x1C0},
1002         .reset_mask = 0x07,
1003 };
1004 
1005 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
1006         .mask = {0x140},
1007         .reset_mask = 0x03,
1008 };
1009 
1010 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
1011         .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
1012         .reset_mask = BIT(2) | BIT(1) | BIT(0),
1013 };
1014 
1015 static void __init sunxi_gates_clk_setup(struct device_node *node,
1016                                          struct gates_data *data)
1017 {
1018         struct clk_onecell_data *clk_data;
1019         struct gates_reset_data *reset_data;
1020         const char *clk_parent;
1021         const char *clk_name;
1022         void __iomem *reg;
1023         int qty;
1024         int i = 0;
1025         int j = 0;
1026 
1027         reg = of_iomap(node, 0);
1028 
1029         clk_parent = of_clk_get_parent_name(node, 0);
1030 
1031         /* Worst-case size approximation and memory allocation */
1032         qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1033         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1034         if (!clk_data)
1035                 return;
1036         clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1037         if (!clk_data->clks) {
1038                 kfree(clk_data);
1039                 return;
1040         }
1041 
1042         for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1043                 of_property_read_string_index(node, "clock-output-names",
1044                                               j, &clk_name);
1045 
1046                 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1047                                                       clk_parent, 0,
1048                                                       reg + 4 * (i/32), i % 32,
1049                                                       0, &clk_lock);
1050                 WARN_ON(IS_ERR(clk_data->clks[i]));
1051                 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
1052 
1053                 j++;
1054         }
1055 
1056         /* Adjust to the real max */
1057         clk_data->clk_num = i;
1058 
1059         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1060 
1061         /* Register a reset controler for gates with reset bits */
1062         if (data->reset_mask == 0)
1063                 return;
1064 
1065         reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
1066         if (!reset_data)
1067                 return;
1068 
1069         reset_data->reg = reg;
1070         reset_data->lock = &clk_lock;
1071         reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
1072         reset_data->rcdev.ops = &sunxi_gates_reset_ops;
1073         reset_data->rcdev.of_node = node;
1074         reset_controller_register(&reset_data->rcdev);
1075 }
1076 
1077 
1078 
1079 /**
1080  * sunxi_divs_clk_setup() helper data
1081  */
1082 
1083 #define SUNXI_DIVS_MAX_QTY      2
1084 #define SUNXI_DIVISOR_WIDTH     2
1085 
1086 struct divs_data {
1087         const struct factors_data *factors; /* data for the factor clock */
1088         int ndivs; /* number of children */
1089         struct {
1090                 u8 fixed; /* is it a fixed divisor? if not... */
1091                 struct clk_div_table *table; /* is it a table based divisor? */
1092                 u8 shift; /* otherwise it's a normal divisor with this shift */
1093                 u8 pow;   /* is it power-of-two based? */
1094                 u8 gate;  /* is it independently gateable? */
1095         } div[SUNXI_DIVS_MAX_QTY];
1096 };
1097 
1098 static struct clk_div_table pll6_sata_tbl[] = {
1099         { .val = 0, .div = 6, },
1100         { .val = 1, .div = 12, },
1101         { .val = 2, .div = 18, },
1102         { .val = 3, .div = 24, },
1103         { } /* sentinel */
1104 };
1105 
1106 static const struct divs_data pll5_divs_data __initconst = {
1107         .factors = &sun4i_pll5_data,
1108         .ndivs = 2,
1109         .div = {
1110                 { .shift = 0, .pow = 0, }, /* M, DDR */
1111                 { .shift = 16, .pow = 1, }, /* P, other */
1112         }
1113 };
1114 
1115 static const struct divs_data pll6_divs_data __initconst = {
1116         .factors = &sun4i_pll6_data,
1117         .ndivs = 2,
1118         .div = {
1119                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1120                 { .fixed = 2 }, /* P, other */
1121         }
1122 };
1123 
1124 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1125         .factors = &sun6i_a31_pll6_data,
1126         .ndivs = 1,
1127         .div = {
1128                 { .fixed = 2 }, /* normal output */
1129         }
1130 };
1131 
1132 /**
1133  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1134  *
1135  * These clocks look something like this
1136  *            ________________________
1137  *           |         ___divisor 1---|----> to consumer
1138  * parent >--|  pll___/___divisor 2---|----> to consumer
1139  *           |        \_______________|____> to consumer
1140  *           |________________________|
1141  */
1142 
1143 static void __init sunxi_divs_clk_setup(struct device_node *node,
1144                                         struct divs_data *data)
1145 {
1146         struct clk_onecell_data *clk_data;
1147         const char *parent;
1148         const char *clk_name;
1149         struct clk **clks, *pclk;
1150         struct clk_hw *gate_hw, *rate_hw;
1151         const struct clk_ops *rate_ops;
1152         struct clk_gate *gate = NULL;
1153         struct clk_fixed_factor *fix_factor;
1154         struct clk_divider *divider;
1155         void __iomem *reg;
1156         int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1157         int flags, clkflags;
1158 
1159         /* Set up factor clock that we will be dividing */
1160         pclk = sunxi_factors_clk_setup(node, data->factors);
1161         parent = __clk_get_name(pclk);
1162 
1163         reg = of_iomap(node, 0);
1164 
1165         clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1166         if (!clk_data)
1167                 return;
1168 
1169         clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
1170         if (!clks)
1171                 goto free_clkdata;
1172 
1173         clk_data->clks = clks;
1174 
1175         /* It's not a good idea to have automatic reparenting changing
1176          * our RAM clock! */
1177         clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1178 
1179         /* if number of children known, use it */
1180         if (data->ndivs)
1181                 ndivs = data->ndivs;
1182 
1183         for (i = 0; i < ndivs; i++) {
1184                 if (of_property_read_string_index(node, "clock-output-names",
1185                                                   i, &clk_name) != 0)
1186                         break;
1187 
1188                 gate_hw = NULL;
1189                 rate_hw = NULL;
1190                 rate_ops = NULL;
1191 
1192                 /* If this leaf clock can be gated, create a gate */
1193                 if (data->div[i].gate) {
1194                         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1195                         if (!gate)
1196                                 goto free_clks;
1197 
1198                         gate->reg = reg;
1199                         gate->bit_idx = data->div[i].gate;
1200                         gate->lock = &clk_lock;
1201 
1202                         gate_hw = &gate->hw;
1203                 }
1204 
1205                 /* Leaves can be fixed or configurable divisors */
1206                 if (data->div[i].fixed) {
1207                         fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1208                         if (!fix_factor)
1209                                 goto free_gate;
1210 
1211                         fix_factor->mult = 1;
1212                         fix_factor->div = data->div[i].fixed;
1213 
1214                         rate_hw = &fix_factor->hw;
1215                         rate_ops = &clk_fixed_factor_ops;
1216                 } else {
1217                         divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1218                         if (!divider)
1219                                 goto free_gate;
1220 
1221                         flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1222 
1223                         divider->reg = reg;
1224                         divider->shift = data->div[i].shift;
1225                         divider->width = SUNXI_DIVISOR_WIDTH;
1226                         divider->flags = flags;
1227                         divider->lock = &clk_lock;
1228                         divider->table = data->div[i].table;
1229 
1230                         rate_hw = &divider->hw;
1231                         rate_ops = &clk_divider_ops;
1232                 }
1233 
1234                 /* Wrap the (potential) gate and the divisor on a composite
1235                  * clock to unify them */
1236                 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1237                                                  NULL, NULL,
1238                                                  rate_hw, rate_ops,
1239                                                  gate_hw, &clk_gate_ops,
1240                                                  clkflags);
1241 
1242                 WARN_ON(IS_ERR(clk_data->clks[i]));
1243                 clk_register_clkdev(clks[i], clk_name, NULL);
1244         }
1245 
1246         /* The last clock available on the getter is the parent */
1247         clks[i++] = pclk;
1248 
1249         /* Adjust to the real max */
1250         clk_data->clk_num = i;
1251 
1252         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1253 
1254         return;
1255 
1256 free_gate:
1257         kfree(gate);
1258 free_clks:
1259         kfree(clks);
1260 free_clkdata:
1261         kfree(clk_data);
1262 }
1263 
1264 
1265 
1266 /* Matches for factors clocks */
1267 static const struct of_device_id clk_factors_match[] __initconst = {
1268         {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1269         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1270         {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1271         {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1272         {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1273         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1274         {}
1275 };
1276 
1277 /* Matches for divider clocks */
1278 static const struct of_device_id clk_div_match[] __initconst = {
1279         {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1280         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1281         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1282         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1283         {}
1284 };
1285 
1286 /* Matches for divided outputs */
1287 static const struct of_device_id clk_divs_match[] __initconst = {
1288         {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1289         {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1290         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1291         {}
1292 };
1293 
1294 /* Matches for mux clocks */
1295 static const struct of_device_id clk_mux_match[] __initconst = {
1296         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1297         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1298         {}
1299 };
1300 
1301 /* Matches for gate clocks */
1302 static const struct of_device_id clk_gates_match[] __initconst = {
1303         {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1304         {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1305         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1306         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1307         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1308         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1309         {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1310         {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1311         {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1312         {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1313         {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1314         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1315         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1316         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1317         {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1318         {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1319         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1320         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1321         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1322         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1323         {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1324         {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1325         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1326         {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1327         {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1328         {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1329         {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1330         {}
1331 };
1332 
1333 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1334                                               void *function)
1335 {
1336         struct device_node *np;
1337         const struct div_data *data;
1338         const struct of_device_id *match;
1339         void (*setup_function)(struct device_node *, const void *) = function;
1340 
1341         for_each_matching_node_and_match(np, clk_match, &match) {
1342                 data = match->data;
1343                 setup_function(np, data);
1344         }
1345 }
1346 
1347 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1348 {
1349         unsigned int i;
1350 
1351         /* Register factor clocks */
1352         of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1353 
1354         /* Register divider clocks */
1355         of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1356 
1357         /* Register divided output clocks */
1358         of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1359 
1360         /* Register mux clocks */
1361         of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1362 
1363         /* Register gate clocks */
1364         of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1365 
1366         /* Protect the clocks that needs to stay on */
1367         for (i = 0; i < nclocks; i++) {
1368                 struct clk *clk = clk_get(NULL, clocks[i]);
1369 
1370                 if (!IS_ERR(clk))
1371                         clk_prepare_enable(clk);
1372         }
1373 }
1374 
1375 static const char *sun4i_a10_critical_clocks[] __initdata = {
1376         "pll5_ddr",
1377         "ahb_sdram",
1378 };
1379 
1380 static void __init sun4i_a10_init_clocks(struct device_node *node)
1381 {
1382         sunxi_init_clocks(sun4i_a10_critical_clocks,
1383                           ARRAY_SIZE(sun4i_a10_critical_clocks));
1384 }
1385 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1386 
1387 static const char *sun5i_critical_clocks[] __initdata = {
1388         "pll5_ddr",
1389         "ahb_sdram",
1390 };
1391 
1392 static void __init sun5i_init_clocks(struct device_node *node)
1393 {
1394         sunxi_init_clocks(sun5i_critical_clocks,
1395                           ARRAY_SIZE(sun5i_critical_clocks));
1396 }
1397 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1398 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1399 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1400 
1401 static const char *sun6i_critical_clocks[] __initdata = {
1402         "cpu",
1403 };
1404 
1405 static void __init sun6i_init_clocks(struct device_node *node)
1406 {
1407         sunxi_init_clocks(sun6i_critical_clocks,
1408                           ARRAY_SIZE(sun6i_critical_clocks));
1409 }
1410 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1411 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1412 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1413 
1414 static void __init sun9i_init_clocks(struct device_node *node)
1415 {
1416         sunxi_init_clocks(NULL, 0);
1417 }
1418 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
1419 

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