Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/clk/samsung/clk-exynos5420.c

  1 /*
  2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3  * Authors: Thomas Abraham <thomas.ab@samsung.com>
  4  *          Chander Kashyap <k.chander@samsung.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * Common Clock Framework support for Exynos5420 SoC.
 11 */
 12 
 13 #include <dt-bindings/clock/exynos5420.h>
 14 #include <linux/clk.h>
 15 #include <linux/clkdev.h>
 16 #include <linux/clk-provider.h>
 17 #include <linux/of.h>
 18 #include <linux/of_address.h>
 19 #include <linux/syscore_ops.h>
 20 
 21 #include "clk.h"
 22 
 23 #define APLL_LOCK               0x0
 24 #define APLL_CON0               0x100
 25 #define SRC_CPU                 0x200
 26 #define DIV_CPU0                0x500
 27 #define DIV_CPU1                0x504
 28 #define GATE_BUS_CPU            0x700
 29 #define GATE_SCLK_CPU           0x800
 30 #define CLKOUT_CMU_CPU          0xa00
 31 #define GATE_IP_G2D             0x8800
 32 #define CPLL_LOCK               0x10020
 33 #define DPLL_LOCK               0x10030
 34 #define EPLL_LOCK               0x10040
 35 #define RPLL_LOCK               0x10050
 36 #define IPLL_LOCK               0x10060
 37 #define SPLL_LOCK               0x10070
 38 #define VPLL_LOCK               0x10080
 39 #define MPLL_LOCK               0x10090
 40 #define CPLL_CON0               0x10120
 41 #define DPLL_CON0               0x10128
 42 #define EPLL_CON0               0x10130
 43 #define EPLL_CON1               0x10134
 44 #define EPLL_CON2               0x10138
 45 #define RPLL_CON0               0x10140
 46 #define RPLL_CON1               0x10144
 47 #define RPLL_CON2               0x10148
 48 #define IPLL_CON0               0x10150
 49 #define SPLL_CON0               0x10160
 50 #define VPLL_CON0               0x10170
 51 #define MPLL_CON0               0x10180
 52 #define SRC_TOP0                0x10200
 53 #define SRC_TOP1                0x10204
 54 #define SRC_TOP2                0x10208
 55 #define SRC_TOP3                0x1020c
 56 #define SRC_TOP4                0x10210
 57 #define SRC_TOP5                0x10214
 58 #define SRC_TOP6                0x10218
 59 #define SRC_TOP7                0x1021c
 60 #define SRC_TOP8                0x10220 /* 5800 specific */
 61 #define SRC_TOP9                0x10224 /* 5800 specific */
 62 #define SRC_DISP10              0x1022c
 63 #define SRC_MAU                 0x10240
 64 #define SRC_FSYS                0x10244
 65 #define SRC_PERIC0              0x10250
 66 #define SRC_PERIC1              0x10254
 67 #define SRC_ISP                 0x10270
 68 #define SRC_CAM                 0x10274 /* 5800 specific */
 69 #define SRC_TOP10               0x10280
 70 #define SRC_TOP11               0x10284
 71 #define SRC_TOP12               0x10288
 72 #define SRC_TOP13               0x1028c /* 5800 specific */
 73 #define SRC_MASK_TOP2           0x10308
 74 #define SRC_MASK_TOP7           0x1031c
 75 #define SRC_MASK_DISP10         0x1032c
 76 #define SRC_MASK_MAU            0x10334
 77 #define SRC_MASK_FSYS           0x10340
 78 #define SRC_MASK_PERIC0         0x10350
 79 #define SRC_MASK_PERIC1         0x10354
 80 #define DIV_TOP0                0x10500
 81 #define DIV_TOP1                0x10504
 82 #define DIV_TOP2                0x10508
 83 #define DIV_TOP8                0x10520 /* 5800 specific */
 84 #define DIV_TOP9                0x10524 /* 5800 specific */
 85 #define DIV_DISP10              0x1052c
 86 #define DIV_MAU                 0x10544
 87 #define DIV_FSYS0               0x10548
 88 #define DIV_FSYS1               0x1054c
 89 #define DIV_FSYS2               0x10550
 90 #define DIV_PERIC0              0x10558
 91 #define DIV_PERIC1              0x1055c
 92 #define DIV_PERIC2              0x10560
 93 #define DIV_PERIC3              0x10564
 94 #define DIV_PERIC4              0x10568
 95 #define DIV_CAM                 0x10574 /* 5800 specific */
 96 #define SCLK_DIV_ISP0           0x10580
 97 #define SCLK_DIV_ISP1           0x10584
 98 #define DIV2_RATIO0             0x10590
 99 #define DIV4_RATIO              0x105a0
100 #define GATE_BUS_TOP            0x10700
101 #define GATE_BUS_GEN            0x1073c
102 #define GATE_BUS_FSYS0          0x10740
103 #define GATE_BUS_FSYS2          0x10748
104 #define GATE_BUS_PERIC          0x10750
105 #define GATE_BUS_PERIC1         0x10754
106 #define GATE_BUS_PERIS0         0x10760
107 #define GATE_BUS_PERIS1         0x10764
108 #define GATE_BUS_NOC            0x10770
109 #define GATE_TOP_SCLK_ISP       0x10870
110 #define GATE_IP_GSCL0           0x10910
111 #define GATE_IP_GSCL1           0x10920
112 #define GATE_IP_CAM             0x10924 /* 5800 specific */
113 #define GATE_IP_MFC             0x1092c
114 #define GATE_IP_DISP1           0x10928
115 #define GATE_IP_G3D             0x10930
116 #define GATE_IP_GEN             0x10934
117 #define GATE_IP_FSYS            0x10944
118 #define GATE_IP_PERIC           0x10950
119 #define GATE_IP_PERIS           0x10960
120 #define GATE_IP_MSCL            0x10970
121 #define GATE_TOP_SCLK_GSCL      0x10820
122 #define GATE_TOP_SCLK_DISP1     0x10828
123 #define GATE_TOP_SCLK_MAU       0x1083c
124 #define GATE_TOP_SCLK_FSYS      0x10840
125 #define GATE_TOP_SCLK_PERIC     0x10850
126 #define TOP_SPARE2              0x10b08
127 #define BPLL_LOCK               0x20010
128 #define BPLL_CON0               0x20110
129 #define KPLL_LOCK               0x28000
130 #define KPLL_CON0               0x28100
131 #define SRC_KFC                 0x28200
132 #define DIV_KFC0                0x28500
133 
134 /* Exynos5x SoC type */
135 enum exynos5x_soc {
136         EXYNOS5420,
137         EXYNOS5800,
138 };
139 
140 /* list of PLLs */
141 enum exynos5x_plls {
142         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
143         bpll, kpll,
144         nr_plls                 /* number of PLLs */
145 };
146 
147 static void __iomem *reg_base;
148 static enum exynos5x_soc exynos5x_soc;
149 
150 #ifdef CONFIG_PM_SLEEP
151 static struct samsung_clk_reg_dump *exynos5x_save;
152 static struct samsung_clk_reg_dump *exynos5800_save;
153 
154 /*
155  * list of controller registers to be saved and restored during a
156  * suspend/resume cycle.
157  */
158 static unsigned long exynos5x_clk_regs[] __initdata = {
159         SRC_CPU,
160         DIV_CPU0,
161         DIV_CPU1,
162         GATE_BUS_CPU,
163         GATE_SCLK_CPU,
164         CLKOUT_CMU_CPU,
165         EPLL_CON0,
166         EPLL_CON1,
167         EPLL_CON2,
168         RPLL_CON0,
169         RPLL_CON1,
170         RPLL_CON2,
171         SRC_TOP0,
172         SRC_TOP1,
173         SRC_TOP2,
174         SRC_TOP3,
175         SRC_TOP4,
176         SRC_TOP5,
177         SRC_TOP6,
178         SRC_TOP7,
179         SRC_DISP10,
180         SRC_MAU,
181         SRC_FSYS,
182         SRC_PERIC0,
183         SRC_PERIC1,
184         SRC_TOP10,
185         SRC_TOP11,
186         SRC_TOP12,
187         SRC_MASK_TOP2,
188         SRC_MASK_TOP7,
189         SRC_MASK_DISP10,
190         SRC_MASK_FSYS,
191         SRC_MASK_PERIC0,
192         SRC_MASK_PERIC1,
193         SRC_ISP,
194         DIV_TOP0,
195         DIV_TOP1,
196         DIV_TOP2,
197         DIV_DISP10,
198         DIV_MAU,
199         DIV_FSYS0,
200         DIV_FSYS1,
201         DIV_FSYS2,
202         DIV_PERIC0,
203         DIV_PERIC1,
204         DIV_PERIC2,
205         DIV_PERIC3,
206         DIV_PERIC4,
207         SCLK_DIV_ISP0,
208         SCLK_DIV_ISP1,
209         DIV2_RATIO0,
210         DIV4_RATIO,
211         GATE_BUS_TOP,
212         GATE_BUS_GEN,
213         GATE_BUS_FSYS0,
214         GATE_BUS_FSYS2,
215         GATE_BUS_PERIC,
216         GATE_BUS_PERIC1,
217         GATE_BUS_PERIS0,
218         GATE_BUS_PERIS1,
219         GATE_BUS_NOC,
220         GATE_TOP_SCLK_ISP,
221         GATE_IP_GSCL0,
222         GATE_IP_GSCL1,
223         GATE_IP_MFC,
224         GATE_IP_DISP1,
225         GATE_IP_G3D,
226         GATE_IP_GEN,
227         GATE_IP_FSYS,
228         GATE_IP_PERIC,
229         GATE_IP_PERIS,
230         GATE_IP_MSCL,
231         GATE_TOP_SCLK_GSCL,
232         GATE_TOP_SCLK_DISP1,
233         GATE_TOP_SCLK_MAU,
234         GATE_TOP_SCLK_FSYS,
235         GATE_TOP_SCLK_PERIC,
236         TOP_SPARE2,
237         SRC_KFC,
238         DIV_KFC0,
239 };
240 
241 static unsigned long exynos5800_clk_regs[] __initdata = {
242         SRC_TOP8,
243         SRC_TOP9,
244         SRC_CAM,
245         SRC_TOP1,
246         DIV_TOP8,
247         DIV_TOP9,
248         DIV_CAM,
249         GATE_IP_CAM,
250 };
251 
252 static int exynos5420_clk_suspend(void)
253 {
254         samsung_clk_save(reg_base, exynos5x_save,
255                                 ARRAY_SIZE(exynos5x_clk_regs));
256 
257         if (exynos5x_soc == EXYNOS5800)
258                 samsung_clk_save(reg_base, exynos5800_save,
259                                 ARRAY_SIZE(exynos5800_clk_regs));
260 
261         return 0;
262 }
263 
264 static void exynos5420_clk_resume(void)
265 {
266         samsung_clk_restore(reg_base, exynos5x_save,
267                                 ARRAY_SIZE(exynos5x_clk_regs));
268 
269         if (exynos5x_soc == EXYNOS5800)
270                 samsung_clk_restore(reg_base, exynos5800_save,
271                                 ARRAY_SIZE(exynos5800_clk_regs));
272 }
273 
274 static struct syscore_ops exynos5420_clk_syscore_ops = {
275         .suspend = exynos5420_clk_suspend,
276         .resume = exynos5420_clk_resume,
277 };
278 
279 static void exynos5420_clk_sleep_init(void)
280 {
281         exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
282                                         ARRAY_SIZE(exynos5x_clk_regs));
283         if (!exynos5x_save) {
284                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
285                         __func__);
286                 return;
287         }
288 
289         if (exynos5x_soc == EXYNOS5800) {
290                 exynos5800_save =
291                         samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
292                                         ARRAY_SIZE(exynos5800_clk_regs));
293                 if (!exynos5800_save)
294                         goto err_soc;
295         }
296 
297         register_syscore_ops(&exynos5420_clk_syscore_ops);
298         return;
299 err_soc:
300         kfree(exynos5x_save);
301         pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
302                 __func__);
303         return;
304 }
305 #else
306 static void exynos5420_clk_sleep_init(void) {}
307 #endif
308 
309 /* list of all parent clocks */
310 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
311                                 "mout_sclk_mpll", "mout_sclk_spll"};
312 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
313 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
314 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
315 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
316 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
317 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
318 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
319 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
320 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
321 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
322 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
323 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
324 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
325 
326 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
327                                         "mout_sclk_mpll"};
328 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
329                         "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
330                         "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
331 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
332 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
333 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
334 
335 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
336 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
337 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
338 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
339 
340 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
341 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
342 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
343 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
344 
345 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
346 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
347 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
348 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
349 
350 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
351 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
352 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
353 
354 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
355 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
356 
357 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
358                                         "mout_sclk_spll"};
359 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
360 
361 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
362 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
363 
364 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
365 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
366 
367 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
368 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
369 
370 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
371 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
372 
373 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
374 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
375 
376 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
377 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
378 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
379 
380 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
381 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
382 
383 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
384 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
385 
386 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
387 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
388 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
389 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
390 
391 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
392 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
393 
394 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
395 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
396 
397 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
398 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
399 
400 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
401 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
402 
403 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
404                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
405                         "mout_sclk_epll", "mout_sclk_rpll"};
406 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
407                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
408                         "mout_sclk_epll", "mout_sclk_rpll"};
409 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
410                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
411                         "mout_sclk_epll", "mout_sclk_rpll"};
412 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
413                         "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
414                         "mout_sclk_epll", "mout_sclk_rpll"};
415 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
416 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
417                          "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
418                          "mout_sclk_epll", "mout_sclk_rpll"};
419 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
420                                 "mout_sclk_mpll", "mout_sclk_spll"};
421 /* List of parents specific to exynos5800 */
422 PNAME(mout_epll2_5800_p)        = { "mout_sclk_epll", "ff_dout_epll2" };
423 PNAME(mout_group1_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
424                                 "mout_sclk_mpll", "ff_dout_spll2" };
425 PNAME(mout_group2_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
426                                         "mout_sclk_mpll", "ff_dout_spll2",
427                                         "mout_epll2", "mout_sclk_ipll" };
428 PNAME(mout_group3_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
429                                         "mout_sclk_mpll", "ff_dout_spll2",
430                                         "mout_epll2" };
431 PNAME(mout_group5_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
432                                         "mout_sclk_mpll", "mout_sclk_spll" };
433 PNAME(mout_group6_5800_p)       = { "mout_sclk_ipll", "mout_sclk_dpll",
434                                 "mout_sclk_mpll", "ff_dout_spll2" };
435 PNAME(mout_group7_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
436                                         "mout_sclk_mpll", "mout_sclk_spll",
437                                         "mout_epll2", "mout_sclk_ipll" };
438 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
439                                         "mout_sclk_mpll",
440                                         "ff_dout_spll2" };
441 PNAME(mout_group8_5800_p)       = { "dout_aclk432_scaler", "dout_sclk_sw" };
442 PNAME(mout_group9_5800_p)       = { "dout_osc_div", "mout_sw_aclk432_scaler" };
443 PNAME(mout_group10_5800_p)      = { "dout_aclk432_cam", "dout_sclk_sw" };
444 PNAME(mout_group11_5800_p)      = { "dout_osc_div", "mout_sw_aclk432_cam" };
445 PNAME(mout_group12_5800_p)      = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
446 PNAME(mout_group13_5800_p)      = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
447 PNAME(mout_group14_5800_p)      = { "dout_aclk550_cam", "dout_sclk_sw" };
448 PNAME(mout_group15_5800_p)      = { "dout_osc_div", "mout_sw_aclk550_cam" };
449 
450 /* fixed rate clocks generated outside the soc */
451 static struct samsung_fixed_rate_clock
452                 exynos5x_fixed_rate_ext_clks[] __initdata = {
453         FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
454 };
455 
456 /* fixed rate clocks generated inside the soc */
457 static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
458         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
459         FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
460         FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
461         FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
462         FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
463 };
464 
465 static struct samsung_fixed_factor_clock
466                 exynos5x_fixed_factor_clks[] __initdata = {
467         FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
468         FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
469 };
470 
471 static struct samsung_fixed_factor_clock
472                 exynos5800_fixed_factor_clks[] __initdata = {
473         FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
474         FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
475 };
476 
477 struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
478         MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
479         MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
480         MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
481         MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
482 
483         MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
484         MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
485         MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
486         MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
487         MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
488 
489         MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
490         MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
491         MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
492         MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
493         MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
494         MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
495 
496         MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
497                         20, 2),
498         MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
499         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
500 
501         MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
502         MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
503         MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
504         MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
505 
506         MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
507                                                         SRC_TOP9, 16, 1),
508         MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
509                                                         SRC_TOP9, 20, 1),
510         MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
511                                                         SRC_TOP9, 24, 1),
512         MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
513                                                         SRC_TOP9, 28, 1),
514 
515         MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
516         MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
517                                                         SRC_TOP13, 20, 1),
518         MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
519                                                         SRC_TOP13, 24, 1),
520         MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
521                                                         SRC_TOP13, 28, 1),
522 
523         MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
524 };
525 
526 struct samsung_div_clock exynos5800_div_clks[] __initdata = {
527         DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
528 
529         DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
530                                 DIV_TOP8, 16, 3),
531         DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
532                                 DIV_TOP8, 20, 3),
533         DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
534                                 DIV_TOP8, 24, 3),
535         DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
536                                 DIV_TOP8, 28, 3),
537 
538         DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
539         DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
540 };
541 
542 struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
543         GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
544                                 GATE_BUS_TOP, 24, 0, 0),
545         GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
546                                 GATE_BUS_TOP, 27, 0, 0),
547 };
548 
549 struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
550         MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
551         MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
552                                 TOP_SPARE2, 4, 1),
553 
554         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
555         MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
556                                 SRC_TOP0, 4, 2, "aclk400_mscl"),
557         MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
558         MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
559 
560         MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
561         MUX(0, "mout_aclk333_432_isp", mout_group4_p,
562                                 SRC_TOP1, 4, 2),
563         MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
564         MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
565         MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
566 
567         MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
568         MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
569         MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
570         MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
571         MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
572         MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
573 
574         MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
575 
576         MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
577 };
578 
579 struct samsung_div_clock exynos5420_div_clks[] __initdata = {
580         DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
581                         DIV_TOP0, 16, 3),
582 };
583 
584 static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
585         MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
586                         SRC_TOP7, 4, 1),
587         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
588         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
589 
590         MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
591         MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
592         MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
593         MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
594 
595         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
596         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
597         MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
598         MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
599 
600         MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
601         MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
602 
603         MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
604 
605         MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
606                         SRC_TOP3, 0, 1),
607         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
608                         SRC_TOP3, 4, 1),
609         MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
610                         SRC_TOP3, 8, 1),
611         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
612                         SRC_TOP3, 12, 1),
613         MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
614                         SRC_TOP3, 16, 1),
615         MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
616                         SRC_TOP3, 20, 1),
617         MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
618                         SRC_TOP3, 24, 1),
619         MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
620                         SRC_TOP3, 28, 1),
621 
622         MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
623                         SRC_TOP4, 0, 1),
624         MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
625                         SRC_TOP4, 4, 1),
626         MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
627                         SRC_TOP4, 8, 1),
628         MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
629                         SRC_TOP4, 12, 1),
630         MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
631                         SRC_TOP4, 16, 1),
632         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
633         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
634         MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
635                         SRC_TOP4, 28, 1),
636 
637         MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
638                         SRC_TOP5, 0, 1),
639         MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
640                         SRC_TOP5, 4, 1),
641         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
642                         SRC_TOP5, 8, 1),
643         MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
644                         SRC_TOP5, 12, 1),
645         MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
646                         SRC_TOP5, 16, 1),
647         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
648                         SRC_TOP5, 20, 1),
649         MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
650                         SRC_TOP5, 24, 1),
651         MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
652                         SRC_TOP5, 28, 1),
653 
654         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
655         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
656         MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
657         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
658         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
659         MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
660         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
661         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
662 
663         MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
664                         SRC_TOP10, 0, 1),
665         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
666                         SRC_TOP10, 4, 1),
667         MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
668         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
669                         SRC_TOP10, 12, 1),
670         MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
671                         SRC_TOP10, 16, 1),
672         MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
673                         SRC_TOP10, 20, 1),
674         MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
675                         SRC_TOP10, 24, 1),
676         MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
677                         SRC_TOP10, 28, 1),
678 
679         MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
680                         SRC_TOP11, 0, 1),
681         MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
682                         SRC_TOP11, 4, 1),
683         MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
684         MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
685                         SRC_TOP11, 12, 1),
686         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
687         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
688         MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
689                         SRC_TOP11, 28, 1),
690 
691         MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
692                         SRC_TOP12, 4, 1),
693         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
694                         SRC_TOP12, 8, 1),
695         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
696                         SRC_TOP12, 12, 1),
697         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
698         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
699                         SRC_TOP12, 20, 1),
700         MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
701                         SRC_TOP12, 24, 1),
702         MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
703                         SRC_TOP12, 28, 1),
704 
705         /* DISP1 Block */
706         MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
707         MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
708         MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
709         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
710         MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
711 
712         MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
713 
714         /* MAU Block */
715         MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
716 
717         /* FSYS Block */
718         MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
719         MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
720         MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
721         MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
722         MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
723         MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
724         MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
725 
726         /* PERIC Block */
727         MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
728         MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
729         MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
730         MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
731         MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
732         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
733         MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
734         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
735         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
736         MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
737         MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
738         MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
739 
740         /* ISP Block */
741         MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
742         MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
743         MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
744         MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
745         MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
746 };
747 
748 static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
749         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
750         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
751         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
752         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
753         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
754 
755         DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
756         DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
757         DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
758         DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
759         DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
760         DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
761         DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
762 
763         DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
764                         DIV_TOP1, 0, 3),
765         DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
766                         DIV_TOP1, 4, 3),
767         DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
768         DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
769                         DIV_TOP1, 16, 3),
770         DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
771         DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
772         DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
773 
774         DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
775         DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
776         DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
777         DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
778         DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
779         DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
780 
781         /* DISP1 Block */
782         DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
783         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
784         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
785         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
786         DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
787         DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
788 
789         /* Audio Block */
790         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
791         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
792 
793         /* USB3.0 */
794         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
795         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
796         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
797         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
798 
799         /* MMC */
800         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
801         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
802         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
803 
804         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
805         DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
806 
807         /* UART and PWM */
808         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
809         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
810         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
811         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
812         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
813 
814         /* SPI */
815         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
816         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
817         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
818 
819         /* Mfc Block */
820         DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
821 
822         /* PCM */
823         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
824         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
825 
826         /* Audio - I2S */
827         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
828         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
829         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
830         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
831         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
832 
833         /* SPI Pre-Ratio */
834         DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
835         DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
836         DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
837 
838         /* GSCL Block */
839         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
840                         DIV2_RATIO0, 4, 2),
841         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
842 
843         /* MSCL Block */
844         DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
845 
846         /* PSGEN */
847         DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
848         DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
849 
850         /* ISP Block */
851         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
852         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
853         DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
854         DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
855         DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
856         DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
857         DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
858         DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
859                         CLK_SET_RATE_PARENT, 0),
860         DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
861                         CLK_SET_RATE_PARENT, 0),
862 };
863 
864 static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
865         /* G2D */
866         GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
867         GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
868         GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
869         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
870         GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
871 
872         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
873                         GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
874         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
875                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
876 
877         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
878                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
879         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
880                         GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
881         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
882                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
883         GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
884                         GATE_BUS_TOP, 5, 0, 0),
885         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
886                         GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
887         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
888                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
889         GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
890                         GATE_BUS_TOP, 8, 0, 0),
891         GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
892                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
893         GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
894                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
895         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
896                         GATE_BUS_TOP, 13, 0, 0),
897         GATE(0, "aclk166", "mout_user_aclk166",
898                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
899         GATE(0, "aclk333", "mout_aclk333",
900                         GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
901         GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
902                         GATE_BUS_TOP, 16, 0, 0),
903         GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
904                         GATE_BUS_TOP, 17, 0, 0),
905         GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
906                         GATE_BUS_TOP, 18, 0, 0),
907         GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
908                         GATE_BUS_TOP, 28, 0, 0),
909         GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
910                         GATE_BUS_TOP, 29, 0, 0),
911 
912         GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
913                         SRC_MASK_TOP2, 24, 0, 0),
914 
915         GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
916                         SRC_MASK_TOP7, 20, 0, 0),
917 
918         /* sclk */
919         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
920                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
921         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
922                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
923         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
924                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
925         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
926                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
927         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
928                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
929         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
930                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
931         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
932                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
933         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
934                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
935         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
936                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
937         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
938                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
939         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
940                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
941         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
942                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
943         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
944                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
945 
946         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
947                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
948         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
949                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
950         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
951                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
952         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
953                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
954         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
955                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
956         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
957                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
958         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
959                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
960 
961         /* Display */
962         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
963                         GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
964         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
965                         GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
966         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
967                         GATE_TOP_SCLK_DISP1, 9, 0, 0),
968         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
969                         GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
970         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
971                         GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
972 
973         /* Maudio Block */
974         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
975                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
976         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
977                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
978 
979         /* FSYS Block */
980         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
981         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
982         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
983         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
984         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
985         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
986         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
987         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
988         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
989                         GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
990         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
991         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
992         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
993         GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
994                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
995 
996         /* PERIC Block */
997         GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
998                         GATE_IP_PERIC, 0, 0, 0),
999         GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1000                         GATE_IP_PERIC, 1, 0, 0),
1001         GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1002                         GATE_IP_PERIC, 2, 0, 0),
1003         GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1004                         GATE_IP_PERIC, 3, 0, 0),
1005         GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1006                         GATE_IP_PERIC, 6, 0, 0),
1007         GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1008                         GATE_IP_PERIC, 7, 0, 0),
1009         GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1010                         GATE_IP_PERIC, 8, 0, 0),
1011         GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1012                         GATE_IP_PERIC, 9, 0, 0),
1013         GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1014                         GATE_IP_PERIC, 10, 0, 0),
1015         GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1016                         GATE_IP_PERIC, 11, 0, 0),
1017         GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1018                         GATE_IP_PERIC, 12, 0, 0),
1019         GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1020                         GATE_IP_PERIC, 13, 0, 0),
1021         GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1022                         GATE_IP_PERIC, 14, 0, 0),
1023         GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1024                         GATE_IP_PERIC, 15, 0, 0),
1025         GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1026                         GATE_IP_PERIC, 16, 0, 0),
1027         GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1028                         GATE_IP_PERIC, 17, 0, 0),
1029         GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1030                         GATE_IP_PERIC, 18, 0, 0),
1031         GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1032                         GATE_IP_PERIC, 20, 0, 0),
1033         GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1034                         GATE_IP_PERIC, 21, 0, 0),
1035         GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1036                         GATE_IP_PERIC, 22, 0, 0),
1037         GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1038                         GATE_IP_PERIC, 23, 0, 0),
1039         GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1040                         GATE_IP_PERIC, 24, 0, 0),
1041         GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1042                         GATE_IP_PERIC, 26, 0, 0),
1043         GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1044                         GATE_IP_PERIC, 28, 0, 0),
1045         GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1046                         GATE_IP_PERIC, 30, 0, 0),
1047         GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1048                         GATE_IP_PERIC, 31, 0, 0),
1049 
1050         GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1051                         GATE_BUS_PERIC, 22, 0, 0),
1052 
1053         /* PERIS Block */
1054         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1055                         GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1056         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1057                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1058         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1059         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1060         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1061         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1062         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1063         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1064         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1065         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1066         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1067         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1068         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1069         GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1070         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1071         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1072         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1073         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1074 
1075         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
1076 
1077         /* GEN Block */
1078         GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1079         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1080         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1081         GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1082         GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1083         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1084                         GATE_IP_GEN, 6, 0, 0),
1085         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1086         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1087                         GATE_IP_GEN, 9, 0, 0),
1088 
1089         /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1090         GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1091                         GATE_BUS_GEN, 28, 0, 0),
1092         GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1093 
1094         /* GSCL Block */
1095         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1096                         GATE_TOP_SCLK_GSCL, 6, 0, 0),
1097         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1098                         GATE_TOP_SCLK_GSCL, 7, 0, 0),
1099 
1100         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1101         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1102         GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1103                         GATE_IP_GSCL0, 4, 0, 0),
1104         GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1105                         GATE_IP_GSCL0, 5, 0, 0),
1106         GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1107                         GATE_IP_GSCL0, 6, 0, 0),
1108 
1109         GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1110                         GATE_IP_GSCL1, 2, 0, 0),
1111         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1112                         GATE_IP_GSCL1, 3, 0, 0),
1113         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1114                         GATE_IP_GSCL1, 4, 0, 0),
1115         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1116                         GATE_IP_GSCL1, 6, 0, 0),
1117         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1118                         GATE_IP_GSCL1, 7, 0, 0),
1119         GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1120         GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1121         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1122                         GATE_IP_GSCL1, 16, 0, 0),
1123         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1124                         GATE_IP_GSCL1, 17, 0, 0),
1125 
1126         /* MSCL Block */
1127         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1128         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1129         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1130         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1131                         GATE_IP_MSCL, 8, 0, 0),
1132         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1133                         GATE_IP_MSCL, 9, 0, 0),
1134         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1135                         GATE_IP_MSCL, 10, 0, 0),
1136 
1137         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1138         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1139         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1140         GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1141         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1142         GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1143                         GATE_IP_DISP1, 7, 0, 0),
1144         GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1145                         GATE_IP_DISP1, 8, 0, 0),
1146         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1147                         GATE_IP_DISP1, 9, 0, 0),
1148 
1149         /* ISP */
1150         GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1151                         GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1152         GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1153                         GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1154         GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1155                         GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1156         GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1157                         GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1158         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1159                         GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1160         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1161                         GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1162         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1163                         GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1164 
1165         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1166         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1167         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1168 
1169         GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1170 };
1171 
1172 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1173         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1174                 APLL_CON0, NULL),
1175         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1176                 CPLL_CON0, NULL),
1177         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1178                 DPLL_CON0, NULL),
1179         [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1180                 EPLL_CON0, NULL),
1181         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1182                 RPLL_CON0, NULL),
1183         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1184                 IPLL_CON0, NULL),
1185         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1186                 SPLL_CON0, NULL),
1187         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1188                 VPLL_CON0, NULL),
1189         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1190                 MPLL_CON0, NULL),
1191         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1192                 BPLL_CON0, NULL),
1193         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1194                 KPLL_CON0, NULL),
1195 };
1196 
1197 static struct of_device_id ext_clk_match[] __initdata = {
1198         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1199         { },
1200 };
1201 
1202 /* register exynos5420 clocks */
1203 static void __init exynos5x_clk_init(struct device_node *np,
1204                 enum exynos5x_soc soc)
1205 {
1206         struct samsung_clk_provider *ctx;
1207 
1208         if (np) {
1209                 reg_base = of_iomap(np, 0);
1210                 if (!reg_base)
1211                         panic("%s: failed to map registers\n", __func__);
1212         } else {
1213                 panic("%s: unable to determine soc\n", __func__);
1214         }
1215 
1216         exynos5x_soc = soc;
1217 
1218         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1219         if (!ctx)
1220                 panic("%s: unable to allocate context.\n", __func__);
1221 
1222         samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1223                         ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1224                         ext_clk_match);
1225         samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1226                                         reg_base);
1227         samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1228                         ARRAY_SIZE(exynos5x_fixed_rate_clks));
1229         samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1230                         ARRAY_SIZE(exynos5x_fixed_factor_clks));
1231         samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1232                         ARRAY_SIZE(exynos5x_mux_clks));
1233         samsung_clk_register_div(ctx, exynos5x_div_clks,
1234                         ARRAY_SIZE(exynos5x_div_clks));
1235         samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1236                         ARRAY_SIZE(exynos5x_gate_clks));
1237 
1238         if (soc == EXYNOS5420) {
1239                 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1240                                 ARRAY_SIZE(exynos5420_mux_clks));
1241                 samsung_clk_register_div(ctx, exynos5420_div_clks,
1242                                 ARRAY_SIZE(exynos5420_div_clks));
1243         } else {
1244                 samsung_clk_register_fixed_factor(
1245                                 ctx, exynos5800_fixed_factor_clks,
1246                                 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1247                 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1248                                 ARRAY_SIZE(exynos5800_mux_clks));
1249                 samsung_clk_register_div(ctx, exynos5800_div_clks,
1250                                 ARRAY_SIZE(exynos5800_div_clks));
1251                 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1252                                 ARRAY_SIZE(exynos5800_gate_clks));
1253         }
1254 
1255         exynos5420_clk_sleep_init();
1256 }
1257 
1258 static void __init exynos5420_clk_init(struct device_node *np)
1259 {
1260         exynos5x_clk_init(np, EXYNOS5420);
1261 }
1262 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1263 
1264 static void __init exynos5800_clk_init(struct device_node *np)
1265 {
1266         exynos5x_clk_init(np, EXYNOS5800);
1267 }
1268 CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
1269 

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