Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/clk/samsung/clk-exynos5420.c

  1 /*
  2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3  * Authors: Thomas Abraham <thomas.ab@samsung.com>
  4  *          Chander Kashyap <k.chander@samsung.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * Common Clock Framework support for Exynos5420 SoC.
 11 */
 12 
 13 #include <dt-bindings/clock/exynos5420.h>
 14 #include <linux/clk.h>
 15 #include <linux/clkdev.h>
 16 #include <linux/clk-provider.h>
 17 #include <linux/of.h>
 18 #include <linux/of_address.h>
 19 #include <linux/syscore_ops.h>
 20 
 21 #include "clk.h"
 22 
 23 #define APLL_LOCK               0x0
 24 #define APLL_CON0               0x100
 25 #define SRC_CPU                 0x200
 26 #define DIV_CPU0                0x500
 27 #define DIV_CPU1                0x504
 28 #define GATE_BUS_CPU            0x700
 29 #define GATE_SCLK_CPU           0x800
 30 #define CPLL_LOCK               0x10020
 31 #define DPLL_LOCK               0x10030
 32 #define EPLL_LOCK               0x10040
 33 #define RPLL_LOCK               0x10050
 34 #define IPLL_LOCK               0x10060
 35 #define SPLL_LOCK               0x10070
 36 #define VPLL_LOCK               0x10070
 37 #define MPLL_LOCK               0x10090
 38 #define CPLL_CON0               0x10120
 39 #define DPLL_CON0               0x10128
 40 #define EPLL_CON0               0x10130
 41 #define RPLL_CON0               0x10140
 42 #define IPLL_CON0               0x10150
 43 #define SPLL_CON0               0x10160
 44 #define VPLL_CON0               0x10170
 45 #define MPLL_CON0               0x10180
 46 #define SRC_TOP0                0x10200
 47 #define SRC_TOP1                0x10204
 48 #define SRC_TOP2                0x10208
 49 #define SRC_TOP3                0x1020c
 50 #define SRC_TOP4                0x10210
 51 #define SRC_TOP5                0x10214
 52 #define SRC_TOP6                0x10218
 53 #define SRC_TOP7                0x1021c
 54 #define SRC_DISP10              0x1022c
 55 #define SRC_MAU                 0x10240
 56 #define SRC_FSYS                0x10244
 57 #define SRC_PERIC0              0x10250
 58 #define SRC_PERIC1              0x10254
 59 #define SRC_TOP10               0x10280
 60 #define SRC_TOP11               0x10284
 61 #define SRC_TOP12               0x10288
 62 #define SRC_MASK_DISP10         0x1032c
 63 #define SRC_MASK_FSYS           0x10340
 64 #define SRC_MASK_PERIC0         0x10350
 65 #define SRC_MASK_PERIC1         0x10354
 66 #define DIV_TOP0                0x10500
 67 #define DIV_TOP1                0x10504
 68 #define DIV_TOP2                0x10508
 69 #define DIV_DISP10              0x1052c
 70 #define DIV_MAU                 0x10544
 71 #define DIV_FSYS0               0x10548
 72 #define DIV_FSYS1               0x1054c
 73 #define DIV_FSYS2               0x10550
 74 #define DIV_PERIC0              0x10558
 75 #define DIV_PERIC1              0x1055c
 76 #define DIV_PERIC2              0x10560
 77 #define DIV_PERIC3              0x10564
 78 #define DIV_PERIC4              0x10568
 79 #define GATE_BUS_TOP            0x10700
 80 #define GATE_BUS_FSYS0          0x10740
 81 #define GATE_BUS_PERIC          0x10750
 82 #define GATE_BUS_PERIC1         0x10754
 83 #define GATE_BUS_PERIS0         0x10760
 84 #define GATE_BUS_PERIS1         0x10764
 85 #define GATE_IP_GSCL0           0x10910
 86 #define GATE_IP_GSCL1           0x10920
 87 #define GATE_IP_MFC             0x1092c
 88 #define GATE_IP_DISP1           0x10928
 89 #define GATE_IP_G3D             0x10930
 90 #define GATE_IP_GEN             0x10934
 91 #define GATE_IP_MSCL            0x10970
 92 #define GATE_TOP_SCLK_GSCL      0x10820
 93 #define GATE_TOP_SCLK_DISP1     0x10828
 94 #define GATE_TOP_SCLK_MAU       0x1083c
 95 #define GATE_TOP_SCLK_FSYS      0x10840
 96 #define GATE_TOP_SCLK_PERIC     0x10850
 97 #define BPLL_LOCK               0x20010
 98 #define BPLL_CON0               0x20110
 99 #define SRC_CDREX               0x20200
100 #define KPLL_LOCK               0x28000
101 #define KPLL_CON0               0x28100
102 #define SRC_KFC                 0x28200
103 #define DIV_KFC0                0x28500
104 
105 /* list of PLLs */
106 enum exynos5420_plls {
107         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
108         bpll, kpll,
109         nr_plls                 /* number of PLLs */
110 };
111 
112 static void __iomem *reg_base;
113 
114 #ifdef CONFIG_PM_SLEEP
115 static struct samsung_clk_reg_dump *exynos5420_save;
116 
117 /*
118  * list of controller registers to be saved and restored during a
119  * suspend/resume cycle.
120  */
121 static unsigned long exynos5420_clk_regs[] __initdata = {
122         SRC_CPU,
123         DIV_CPU0,
124         DIV_CPU1,
125         GATE_BUS_CPU,
126         GATE_SCLK_CPU,
127         SRC_TOP0,
128         SRC_TOP1,
129         SRC_TOP2,
130         SRC_TOP3,
131         SRC_TOP4,
132         SRC_TOP5,
133         SRC_TOP6,
134         SRC_TOP7,
135         SRC_DISP10,
136         SRC_MAU,
137         SRC_FSYS,
138         SRC_PERIC0,
139         SRC_PERIC1,
140         SRC_TOP10,
141         SRC_TOP11,
142         SRC_TOP12,
143         SRC_MASK_DISP10,
144         SRC_MASK_FSYS,
145         SRC_MASK_PERIC0,
146         SRC_MASK_PERIC1,
147         DIV_TOP0,
148         DIV_TOP1,
149         DIV_TOP2,
150         DIV_DISP10,
151         DIV_MAU,
152         DIV_FSYS0,
153         DIV_FSYS1,
154         DIV_FSYS2,
155         DIV_PERIC0,
156         DIV_PERIC1,
157         DIV_PERIC2,
158         DIV_PERIC3,
159         DIV_PERIC4,
160         GATE_BUS_TOP,
161         GATE_BUS_FSYS0,
162         GATE_BUS_PERIC,
163         GATE_BUS_PERIC1,
164         GATE_BUS_PERIS0,
165         GATE_BUS_PERIS1,
166         GATE_IP_GSCL0,
167         GATE_IP_GSCL1,
168         GATE_IP_MFC,
169         GATE_IP_DISP1,
170         GATE_IP_G3D,
171         GATE_IP_GEN,
172         GATE_IP_MSCL,
173         GATE_TOP_SCLK_GSCL,
174         GATE_TOP_SCLK_DISP1,
175         GATE_TOP_SCLK_MAU,
176         GATE_TOP_SCLK_FSYS,
177         GATE_TOP_SCLK_PERIC,
178         SRC_CDREX,
179         SRC_KFC,
180         DIV_KFC0,
181 };
182 
183 static int exynos5420_clk_suspend(void)
184 {
185         samsung_clk_save(reg_base, exynos5420_save,
186                                 ARRAY_SIZE(exynos5420_clk_regs));
187 
188         return 0;
189 }
190 
191 static void exynos5420_clk_resume(void)
192 {
193         samsung_clk_restore(reg_base, exynos5420_save,
194                                 ARRAY_SIZE(exynos5420_clk_regs));
195 }
196 
197 static struct syscore_ops exynos5420_clk_syscore_ops = {
198         .suspend = exynos5420_clk_suspend,
199         .resume = exynos5420_clk_resume,
200 };
201 
202 static void exynos5420_clk_sleep_init(void)
203 {
204         exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs,
205                                         ARRAY_SIZE(exynos5420_clk_regs));
206         if (!exynos5420_save) {
207                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
208                         __func__);
209                 return;
210         }
211 
212         register_syscore_ops(&exynos5420_clk_syscore_ops);
213 }
214 #else
215 static void exynos5420_clk_sleep_init(void) {}
216 #endif
217 
218 /* list of all parent clocks */
219 PNAME(mspll_cpu_p)      = { "sclk_cpll", "sclk_dpll",
220                                 "sclk_mpll", "sclk_spll" };
221 PNAME(cpu_p)            = { "mout_apll" , "mout_mspll_cpu" };
222 PNAME(kfc_p)            = { "mout_kpll" , "mout_mspll_kfc" };
223 PNAME(apll_p)           = { "fin_pll", "fout_apll", };
224 PNAME(bpll_p)           = { "fin_pll", "fout_bpll", };
225 PNAME(cpll_p)           = { "fin_pll", "fout_cpll", };
226 PNAME(dpll_p)           = { "fin_pll", "fout_dpll", };
227 PNAME(epll_p)           = { "fin_pll", "fout_epll", };
228 PNAME(ipll_p)           = { "fin_pll", "fout_ipll", };
229 PNAME(kpll_p)           = { "fin_pll", "fout_kpll", };
230 PNAME(mpll_p)           = { "fin_pll", "fout_mpll", };
231 PNAME(rpll_p)           = { "fin_pll", "fout_rpll", };
232 PNAME(spll_p)           = { "fin_pll", "fout_spll", };
233 PNAME(vpll_p)           = { "fin_pll", "fout_vpll", };
234 
235 PNAME(group1_p)         = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
236 PNAME(group2_p)         = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
237                           "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
238 PNAME(group3_p)         = { "sclk_rpll", "sclk_spll" };
239 PNAME(group4_p)         = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
240 PNAME(group5_p)         = { "sclk_vpll", "sclk_dpll" };
241 
242 PNAME(sw_aclk66_p)      = { "dout_aclk66", "sclk_spll" };
243 PNAME(aclk66_peric_p)   = { "fin_pll", "mout_sw_aclk66" };
244 
245 PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
246 PNAME(user_aclk200_fsys_p)      = { "fin_pll", "mout_sw_aclk200_fsys" };
247 
248 PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
249 PNAME(user_aclk200_fsys2_p)     = { "fin_pll", "mout_sw_aclk200_fsys2" };
250 
251 PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
252 PNAME(aclk200_disp1_p)  = { "fin_pll", "mout_sw_aclk200" };
253 
254 PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
255 PNAME(user_aclk400_mscl_p)      = { "fin_pll", "mout_sw_aclk400_mscl" };
256 
257 PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
258 PNAME(user_aclk333_p)   = { "fin_pll", "mout_sw_aclk333" };
259 
260 PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
261 PNAME(user_aclk166_p)   = { "fin_pll", "mout_sw_aclk166" };
262 
263 PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
264 PNAME(user_aclk266_p)   = { "fin_pll", "mout_sw_aclk266" };
265 
266 PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
267 PNAME(user_aclk333_432_gscl_p)  = { "fin_pll", "mout_sw_aclk333_432_gscl" };
268 
269 PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
270 PNAME(user_aclk300_gscl_p)      = { "fin_pll", "mout_sw_aclk300_gscl" };
271 
272 PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
273 PNAME(user_aclk300_disp1_p)     = { "fin_pll", "mout_sw_aclk300_disp1" };
274 
275 PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
276 PNAME(user_aclk300_jpeg_p)      = { "fin_pll", "mout_sw_aclk300_jpeg" };
277 
278 PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
279 PNAME(user_aclk_g3d_p)  = { "fin_pll", "mout_sw_aclk_g3d" };
280 
281 PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
282 PNAME(user_aclk266_g2d_p)       = { "fin_pll", "mout_sw_aclk266_g2d" };
283 
284 PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
285 PNAME(user_aclk333_g2d_p)       = { "fin_pll", "mout_sw_aclk333_g2d" };
286 
287 PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
288                   "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
289 PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
290                   "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
291 PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
292                   "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
293 PNAME(spdif_p)  = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
294                   "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
295 PNAME(hdmi_p)   = { "dout_hdmi_pixel", "sclk_hdmiphy" };
296 PNAME(maudio0_p)        = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
297                           "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
298 
299 /* fixed rate clocks generated outside the soc */
300 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
301         FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
302 };
303 
304 /* fixed rate clocks generated inside the soc */
305 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
306         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
307         FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
308         FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
309         FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
310         FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
311 };
312 
313 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
314         FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
315 };
316 
317 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
318         MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
319         MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
320         MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
321         MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
322         MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
323         MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
324 
325         MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
326 
327         MUX_A(0, "mout_aclk400_mscl", group1_p,
328                         SRC_TOP0, 4, 2, "aclk400_mscl"),
329         MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
330         MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
331         MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
332 
333         MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
334         MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
335         MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
336         MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
337         MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
338 
339         MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
340         MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
341         MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
342         MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
343         MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
344         MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
345 
346         MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
347                         SRC_TOP3, 4, 1),
348         MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
349                         SRC_TOP3, 8, 1, "aclk200_disp1"),
350         MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
351                         SRC_TOP3, 12, 1),
352         MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
353                         SRC_TOP3, 28, 1),
354 
355         MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
356                         SRC_TOP4, 0, 1),
357         MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
358         MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
359         MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
360         MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
361 
362         MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
363         MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
364         MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
365         MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
366                         SRC_TOP5, 16, 1, "aclkg3d"),
367         MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
368                         SRC_TOP5, 20, 1),
369         MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
370                         SRC_TOP5, 24, 1),
371         MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
372                         SRC_TOP5, 28, 1),
373 
374         MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
375         MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
376         MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
377         MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
378         MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
379         MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
380         MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
381         MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
382 
383         MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
384         MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
385         MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
386                         SRC_TOP10, 12, 1),
387         MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
388 
389         MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
390                         SRC_TOP11, 0, 1),
391         MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
392         MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
393         MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
394         MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
395 
396         MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
397         MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
398         MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
399         MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
400         MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
401                         SRC_TOP12, 24, 1),
402         MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
403 
404         /* DISP1 Block */
405         MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
406         MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
407         MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
408         MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
409         MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
410 
411         /* MAU Block */
412         MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
413 
414         /* FSYS Block */
415         MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
416         MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
417         MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
418         MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
419         MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
420         MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
421 
422         /* PERIC Block */
423         MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
424         MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
425         MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
426         MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
427         MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
428         MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
429         MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
430         MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
431         MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
432         MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
433         MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
434         MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
435 };
436 
437 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
438         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441         DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
442         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 
444         DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445         DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446         DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
447         DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448         DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 
450         DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451                         DIV_TOP1, 0, 3),
452         DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
453         DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454         DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455         DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
456 
457         DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
458         DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459         DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460         DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461         DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
462                         DIV_TOP2, 24, 3, "aclk300_disp1"),
463         DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 
465         /* DISP1 Block */
466         DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
467         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
470 
471         /* Audio Block */
472         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
473         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
474 
475         /* USB3.0 */
476         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
477         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
478         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
479         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
480 
481         /* MMC */
482         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
483         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
484         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 
486         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
487 
488         /* UART and PWM */
489         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
490         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
491         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
492         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
493         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
494 
495         /* SPI */
496         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
497         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 
500         /* PCM */
501         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
503 
504         /* Audio - I2S */
505         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
506         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
507         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
508         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
509         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 
511         /* SPI Pre-Ratio */
512         DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
513         DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
514         DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
515 };
516 
517 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
518         /* TODO: Re-verify the CG bits for all the gate clocks */
519         GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
520                 "mct"),
521 
522         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
523                         GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
524         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
525                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
526 
527         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
528                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
529         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
530                         GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
531         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
532                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
533         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
534                         GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
535         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
536                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
537         GATE(0, "pclk66_gpio", "mout_sw_aclk66",
538                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
539         GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
540                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
541         GATE(0, "aclk66_peric", "mout_aclk66_peric",
542                         GATE_BUS_TOP, 11, 0, 0),
543         GATE(0, "aclk166", "mout_user_aclk166",
544                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
545         GATE(0, "aclk333", "mout_aclk333",
546                         GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
547 
548         /* sclk */
549         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
550                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
551         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
552                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
553         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
554                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
555         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
556                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
557         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
558                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
559         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
560                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
561         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
562                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
563         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
564                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
565         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
566                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
567         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
568                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
569         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
570                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
571         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
572                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
573         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
574                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
575 
576         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
577                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
578         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
579                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
580         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
581                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
582         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
583                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
584         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
585                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
586         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
587                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
588         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
589                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
590 
591         GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
592                 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
593 
594         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
595                 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
596         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
597                 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
598 
599         /* Display */
600         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
601                 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
602         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
603                 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
604         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
605                 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
606         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
607                 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
608         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
609                 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
610 
611         /* Maudio Block */
612         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
613                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
614         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
615                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
616         /* FSYS */
617         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
618         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
619         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
620         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
621         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
622         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
623         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
624         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
625         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
626                         GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
627         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
628         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
629         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
630 
631         /* UART */
632         GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
633         GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
634         GATE_A(CLK_UART2, "uart2", "aclk66_peric",
635                 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
636         GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
637         /* I2C */
638         GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
639         GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
640         GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
641         GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
642         GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
643         GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
644         GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
645         GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
646         GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
647                 0),
648         GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
649         /* SPI */
650         GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
651         GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
652         GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
653         GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
654         /* I2S */
655         GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
656         GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
657         /* PCM */
658         GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
659         GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
660         /* PWM */
661         GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
662         /* SPDIF */
663         GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
664 
665         GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
666         GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
667         GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
668 
669         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
670                         GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
671         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
672                         GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
673         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
674         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
675         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
676         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
677         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
678         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
679         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
680         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
681         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
682         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
683 
684         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
685                 0),
686         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
687         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
688         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
689         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
690         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
691 
692         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
693         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
694         GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
695 
696         GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
697                 0),
698         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
699                         GATE_IP_GSCL1, 3, 0, 0),
700         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
701                         GATE_IP_GSCL1, 4, 0, 0),
702         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
703                 0),
704         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
705                 0),
706         GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
707         GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
708         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
709                         GATE_IP_GSCL1, 16, 0, 0),
710         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
711                         GATE_IP_GSCL1, 17, 0, 0),
712 
713         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
714         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
715         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
716         GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
717         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
718         GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
719                 0),
720 
721         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
722         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
723         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
724 
725         GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
726 
727         GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
728         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
729         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
730         GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
731         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
732         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
733         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
734 
735         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
736         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
737         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
738         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
739                 0),
740         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
741                 0),
742         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
743                 0),
744         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
745                 0),
746 };
747 
748 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
749         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
750                 APLL_CON0, NULL),
751         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
752                 CPLL_CON0, NULL),
753         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
754                 DPLL_CON0, NULL),
755         [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
756                 EPLL_CON0, NULL),
757         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
758                 RPLL_CON0, NULL),
759         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
760                 IPLL_CON0, NULL),
761         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
762                 SPLL_CON0, NULL),
763         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
764                 VPLL_CON0, NULL),
765         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
766                 MPLL_CON0, NULL),
767         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
768                 BPLL_CON0, NULL),
769         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
770                 KPLL_CON0, NULL),
771 };
772 
773 static struct of_device_id ext_clk_match[] __initdata = {
774         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
775         { },
776 };
777 
778 /* register exynos5420 clocks */
779 static void __init exynos5420_clk_init(struct device_node *np)
780 {
781         if (np) {
782                 reg_base = of_iomap(np, 0);
783                 if (!reg_base)
784                         panic("%s: failed to map registers\n", __func__);
785         } else {
786                 panic("%s: unable to determine soc\n", __func__);
787         }
788 
789         samsung_clk_init(np, reg_base, CLK_NR_CLKS);
790         samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
791                         ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
792                         ext_clk_match);
793         samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
794                                         reg_base);
795         samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
796                         ARRAY_SIZE(exynos5420_fixed_rate_clks));
797         samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
798                         ARRAY_SIZE(exynos5420_fixed_factor_clks));
799         samsung_clk_register_mux(exynos5420_mux_clks,
800                         ARRAY_SIZE(exynos5420_mux_clks));
801         samsung_clk_register_div(exynos5420_div_clks,
802                         ARRAY_SIZE(exynos5420_div_clks));
803         samsung_clk_register_gate(exynos5420_gate_clks,
804                         ARRAY_SIZE(exynos5420_gate_clks));
805 
806         exynos5420_clk_sleep_init();
807 }
808 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
809 

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