Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/drivers/clk/samsung/clk-exynos5420.c

  1 /*
  2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3  * Authors: Thomas Abraham <thomas.ab@samsung.com>
  4  *          Chander Kashyap <k.chander@samsung.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * Common Clock Framework support for Exynos5420 SoC.
 11 */
 12 
 13 #include <dt-bindings/clock/exynos5420.h>
 14 #include <linux/slab.h>
 15 #include <linux/clk-provider.h>
 16 #include <linux/of.h>
 17 #include <linux/of_address.h>
 18 #include <linux/syscore_ops.h>
 19 
 20 #include "clk.h"
 21 #include "clk-cpu.h"
 22 
 23 #define APLL_LOCK               0x0
 24 #define APLL_CON0               0x100
 25 #define SRC_CPU                 0x200
 26 #define DIV_CPU0                0x500
 27 #define DIV_CPU1                0x504
 28 #define GATE_BUS_CPU            0x700
 29 #define GATE_SCLK_CPU           0x800
 30 #define CLKOUT_CMU_CPU          0xa00
 31 #define SRC_MASK_CPERI          0x4300
 32 #define GATE_IP_G2D             0x8800
 33 #define CPLL_LOCK               0x10020
 34 #define DPLL_LOCK               0x10030
 35 #define EPLL_LOCK               0x10040
 36 #define RPLL_LOCK               0x10050
 37 #define IPLL_LOCK               0x10060
 38 #define SPLL_LOCK               0x10070
 39 #define VPLL_LOCK               0x10080
 40 #define MPLL_LOCK               0x10090
 41 #define CPLL_CON0               0x10120
 42 #define DPLL_CON0               0x10128
 43 #define EPLL_CON0               0x10130
 44 #define EPLL_CON1               0x10134
 45 #define EPLL_CON2               0x10138
 46 #define RPLL_CON0               0x10140
 47 #define RPLL_CON1               0x10144
 48 #define RPLL_CON2               0x10148
 49 #define IPLL_CON0               0x10150
 50 #define SPLL_CON0               0x10160
 51 #define VPLL_CON0               0x10170
 52 #define MPLL_CON0               0x10180
 53 #define SRC_TOP0                0x10200
 54 #define SRC_TOP1                0x10204
 55 #define SRC_TOP2                0x10208
 56 #define SRC_TOP3                0x1020c
 57 #define SRC_TOP4                0x10210
 58 #define SRC_TOP5                0x10214
 59 #define SRC_TOP6                0x10218
 60 #define SRC_TOP7                0x1021c
 61 #define SRC_TOP8                0x10220 /* 5800 specific */
 62 #define SRC_TOP9                0x10224 /* 5800 specific */
 63 #define SRC_DISP10              0x1022c
 64 #define SRC_MAU                 0x10240
 65 #define SRC_FSYS                0x10244
 66 #define SRC_PERIC0              0x10250
 67 #define SRC_PERIC1              0x10254
 68 #define SRC_ISP                 0x10270
 69 #define SRC_CAM                 0x10274 /* 5800 specific */
 70 #define SRC_TOP10               0x10280
 71 #define SRC_TOP11               0x10284
 72 #define SRC_TOP12               0x10288
 73 #define SRC_TOP13               0x1028c /* 5800 specific */
 74 #define SRC_MASK_TOP0           0x10300
 75 #define SRC_MASK_TOP1           0x10304
 76 #define SRC_MASK_TOP2           0x10308
 77 #define SRC_MASK_TOP7           0x1031c
 78 #define SRC_MASK_DISP10         0x1032c
 79 #define SRC_MASK_MAU            0x10334
 80 #define SRC_MASK_FSYS           0x10340
 81 #define SRC_MASK_PERIC0         0x10350
 82 #define SRC_MASK_PERIC1         0x10354
 83 #define SRC_MASK_ISP            0x10370
 84 #define DIV_TOP0                0x10500
 85 #define DIV_TOP1                0x10504
 86 #define DIV_TOP2                0x10508
 87 #define DIV_TOP8                0x10520 /* 5800 specific */
 88 #define DIV_TOP9                0x10524 /* 5800 specific */
 89 #define DIV_DISP10              0x1052c
 90 #define DIV_MAU                 0x10544
 91 #define DIV_FSYS0               0x10548
 92 #define DIV_FSYS1               0x1054c
 93 #define DIV_FSYS2               0x10550
 94 #define DIV_PERIC0              0x10558
 95 #define DIV_PERIC1              0x1055c
 96 #define DIV_PERIC2              0x10560
 97 #define DIV_PERIC3              0x10564
 98 #define DIV_PERIC4              0x10568
 99 #define DIV_CAM                 0x10574 /* 5800 specific */
100 #define SCLK_DIV_ISP0           0x10580
101 #define SCLK_DIV_ISP1           0x10584
102 #define DIV2_RATIO0             0x10590
103 #define DIV4_RATIO              0x105a0
104 #define GATE_BUS_TOP            0x10700
105 #define GATE_BUS_DISP1          0x10728
106 #define GATE_BUS_GEN            0x1073c
107 #define GATE_BUS_FSYS0          0x10740
108 #define GATE_BUS_FSYS2          0x10748
109 #define GATE_BUS_PERIC          0x10750
110 #define GATE_BUS_PERIC1         0x10754
111 #define GATE_BUS_PERIS0         0x10760
112 #define GATE_BUS_PERIS1         0x10764
113 #define GATE_BUS_NOC            0x10770
114 #define GATE_TOP_SCLK_ISP       0x10870
115 #define GATE_IP_GSCL0           0x10910
116 #define GATE_IP_GSCL1           0x10920
117 #define GATE_IP_CAM             0x10924 /* 5800 specific */
118 #define GATE_IP_MFC             0x1092c
119 #define GATE_IP_DISP1           0x10928
120 #define GATE_IP_G3D             0x10930
121 #define GATE_IP_GEN             0x10934
122 #define GATE_IP_FSYS            0x10944
123 #define GATE_IP_PERIC           0x10950
124 #define GATE_IP_PERIS           0x10960
125 #define GATE_IP_MSCL            0x10970
126 #define GATE_TOP_SCLK_GSCL      0x10820
127 #define GATE_TOP_SCLK_DISP1     0x10828
128 #define GATE_TOP_SCLK_MAU       0x1083c
129 #define GATE_TOP_SCLK_FSYS      0x10840
130 #define GATE_TOP_SCLK_PERIC     0x10850
131 #define TOP_SPARE2              0x10b08
132 #define BPLL_LOCK               0x20010
133 #define BPLL_CON0               0x20110
134 #define SRC_CDREX               0x20200
135 #define DIV_CDREX0              0x20500
136 #define DIV_CDREX1              0x20504
137 #define KPLL_LOCK               0x28000
138 #define KPLL_CON0               0x28100
139 #define SRC_KFC                 0x28200
140 #define DIV_KFC0                0x28500
141 
142 /* Exynos5x SoC type */
143 enum exynos5x_soc {
144         EXYNOS5420,
145         EXYNOS5800,
146 };
147 
148 /* list of PLLs */
149 enum exynos5x_plls {
150         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
151         bpll, kpll,
152         nr_plls                 /* number of PLLs */
153 };
154 
155 static void __iomem *reg_base;
156 static enum exynos5x_soc exynos5x_soc;
157 
158 #ifdef CONFIG_PM_SLEEP
159 static struct samsung_clk_reg_dump *exynos5x_save;
160 static struct samsung_clk_reg_dump *exynos5800_save;
161 
162 /*
163  * list of controller registers to be saved and restored during a
164  * suspend/resume cycle.
165  */
166 static const unsigned long exynos5x_clk_regs[] __initconst = {
167         SRC_CPU,
168         DIV_CPU0,
169         DIV_CPU1,
170         GATE_BUS_CPU,
171         GATE_SCLK_CPU,
172         CLKOUT_CMU_CPU,
173         EPLL_CON0,
174         EPLL_CON1,
175         EPLL_CON2,
176         RPLL_CON0,
177         RPLL_CON1,
178         RPLL_CON2,
179         SRC_TOP0,
180         SRC_TOP1,
181         SRC_TOP2,
182         SRC_TOP3,
183         SRC_TOP4,
184         SRC_TOP5,
185         SRC_TOP6,
186         SRC_TOP7,
187         SRC_DISP10,
188         SRC_MAU,
189         SRC_FSYS,
190         SRC_PERIC0,
191         SRC_PERIC1,
192         SRC_TOP10,
193         SRC_TOP11,
194         SRC_TOP12,
195         SRC_MASK_TOP2,
196         SRC_MASK_TOP7,
197         SRC_MASK_DISP10,
198         SRC_MASK_FSYS,
199         SRC_MASK_PERIC0,
200         SRC_MASK_PERIC1,
201         SRC_MASK_TOP0,
202         SRC_MASK_TOP1,
203         SRC_MASK_MAU,
204         SRC_MASK_ISP,
205         SRC_ISP,
206         DIV_TOP0,
207         DIV_TOP1,
208         DIV_TOP2,
209         DIV_DISP10,
210         DIV_MAU,
211         DIV_FSYS0,
212         DIV_FSYS1,
213         DIV_FSYS2,
214         DIV_PERIC0,
215         DIV_PERIC1,
216         DIV_PERIC2,
217         DIV_PERIC3,
218         DIV_PERIC4,
219         SCLK_DIV_ISP0,
220         SCLK_DIV_ISP1,
221         DIV2_RATIO0,
222         DIV4_RATIO,
223         GATE_BUS_DISP1,
224         GATE_BUS_TOP,
225         GATE_BUS_GEN,
226         GATE_BUS_FSYS0,
227         GATE_BUS_FSYS2,
228         GATE_BUS_PERIC,
229         GATE_BUS_PERIC1,
230         GATE_BUS_PERIS0,
231         GATE_BUS_PERIS1,
232         GATE_BUS_NOC,
233         GATE_TOP_SCLK_ISP,
234         GATE_IP_GSCL0,
235         GATE_IP_GSCL1,
236         GATE_IP_MFC,
237         GATE_IP_DISP1,
238         GATE_IP_G3D,
239         GATE_IP_GEN,
240         GATE_IP_FSYS,
241         GATE_IP_PERIC,
242         GATE_IP_PERIS,
243         GATE_IP_MSCL,
244         GATE_TOP_SCLK_GSCL,
245         GATE_TOP_SCLK_DISP1,
246         GATE_TOP_SCLK_MAU,
247         GATE_TOP_SCLK_FSYS,
248         GATE_TOP_SCLK_PERIC,
249         TOP_SPARE2,
250         SRC_CDREX,
251         DIV_CDREX0,
252         DIV_CDREX1,
253         SRC_KFC,
254         DIV_KFC0,
255 };
256 
257 static const unsigned long exynos5800_clk_regs[] __initconst = {
258         SRC_TOP8,
259         SRC_TOP9,
260         SRC_CAM,
261         SRC_TOP1,
262         DIV_TOP8,
263         DIV_TOP9,
264         DIV_CAM,
265         GATE_IP_CAM,
266 };
267 
268 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
269         { .offset = SRC_MASK_CPERI,             .value = 0xffffffff, },
270         { .offset = SRC_MASK_TOP0,              .value = 0x11111111, },
271         { .offset = SRC_MASK_TOP1,              .value = 0x11101111, },
272         { .offset = SRC_MASK_TOP2,              .value = 0x11111110, },
273         { .offset = SRC_MASK_TOP7,              .value = 0x00111100, },
274         { .offset = SRC_MASK_DISP10,            .value = 0x11111110, },
275         { .offset = SRC_MASK_MAU,               .value = 0x10000000, },
276         { .offset = SRC_MASK_FSYS,              .value = 0x11111110, },
277         { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
278         { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
279         { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
280         { .offset = GATE_BUS_TOP,               .value = 0xffffffff, },
281         { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
282         { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
283 };
284 
285 static int exynos5420_clk_suspend(void)
286 {
287         samsung_clk_save(reg_base, exynos5x_save,
288                                 ARRAY_SIZE(exynos5x_clk_regs));
289 
290         if (exynos5x_soc == EXYNOS5800)
291                 samsung_clk_save(reg_base, exynos5800_save,
292                                 ARRAY_SIZE(exynos5800_clk_regs));
293 
294         samsung_clk_restore(reg_base, exynos5420_set_clksrc,
295                                 ARRAY_SIZE(exynos5420_set_clksrc));
296 
297         return 0;
298 }
299 
300 static void exynos5420_clk_resume(void)
301 {
302         samsung_clk_restore(reg_base, exynos5x_save,
303                                 ARRAY_SIZE(exynos5x_clk_regs));
304 
305         if (exynos5x_soc == EXYNOS5800)
306                 samsung_clk_restore(reg_base, exynos5800_save,
307                                 ARRAY_SIZE(exynos5800_clk_regs));
308 }
309 
310 static struct syscore_ops exynos5420_clk_syscore_ops = {
311         .suspend = exynos5420_clk_suspend,
312         .resume = exynos5420_clk_resume,
313 };
314 
315 static void __init exynos5420_clk_sleep_init(void)
316 {
317         exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
318                                         ARRAY_SIZE(exynos5x_clk_regs));
319         if (!exynos5x_save) {
320                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
321                         __func__);
322                 return;
323         }
324 
325         if (exynos5x_soc == EXYNOS5800) {
326                 exynos5800_save =
327                         samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
328                                         ARRAY_SIZE(exynos5800_clk_regs));
329                 if (!exynos5800_save)
330                         goto err_soc;
331         }
332 
333         register_syscore_ops(&exynos5420_clk_syscore_ops);
334         return;
335 err_soc:
336         kfree(exynos5x_save);
337         pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
338                 __func__);
339         return;
340 }
341 #else
342 static void __init exynos5420_clk_sleep_init(void) {}
343 #endif
344 
345 /* list of all parent clocks */
346 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
347                                 "mout_sclk_mpll", "mout_sclk_spll"};
348 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
349 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
350 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
351 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
352 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
353 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
354 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
355 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
356 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
357 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
358 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
359 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
360 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
361 
362 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
363                                         "mout_sclk_mpll"};
364 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
365                         "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
366                         "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
367 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
368 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
369 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
370 
371 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
372 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
373 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
374 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
375 
376 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
377 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
378 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
379 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
380 
381 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
382 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
383 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
384 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
385 
386 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
387 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
388 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
389 
390 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
391 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
392 
393 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
394                                         "mout_sclk_spll"};
395 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
396 
397 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
398 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
399 
400 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
401 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
402 
403 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
404 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
405 
406 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
407 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
408 
409 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
410 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
411 
412 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
413 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
414 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
415 
416 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
417 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
418 
419 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
420 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
421 
422 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
423 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
424 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
425 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
426 
427 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
428 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
429 
430 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
431 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
432 
433 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
434 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
435 
436 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
437 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
438 
439 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
440                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
441                         "mout_sclk_epll", "mout_sclk_rpll"};
442 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
443                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
444                         "mout_sclk_epll", "mout_sclk_rpll"};
445 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
446                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
447                         "mout_sclk_epll", "mout_sclk_rpll"};
448 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
449                         "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
450                         "mout_sclk_epll", "mout_sclk_rpll"};
451 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
452 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
453                          "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
454                          "mout_sclk_epll", "mout_sclk_rpll"};
455 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
456                                 "mout_sclk_mpll", "mout_sclk_spll"};
457 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
458 
459 /* List of parents specific to exynos5800 */
460 PNAME(mout_epll2_5800_p)        = { "mout_sclk_epll", "ff_dout_epll2" };
461 PNAME(mout_group1_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
462                                 "mout_sclk_mpll", "ff_dout_spll2" };
463 PNAME(mout_group2_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
464                                         "mout_sclk_mpll", "ff_dout_spll2",
465                                         "mout_epll2", "mout_sclk_ipll" };
466 PNAME(mout_group3_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
467                                         "mout_sclk_mpll", "ff_dout_spll2",
468                                         "mout_epll2" };
469 PNAME(mout_group5_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
470                                         "mout_sclk_mpll", "mout_sclk_spll" };
471 PNAME(mout_group6_5800_p)       = { "mout_sclk_ipll", "mout_sclk_dpll",
472                                 "mout_sclk_mpll", "ff_dout_spll2" };
473 PNAME(mout_group7_5800_p)       = { "mout_sclk_cpll", "mout_sclk_dpll",
474                                         "mout_sclk_mpll", "mout_sclk_spll",
475                                         "mout_epll2", "mout_sclk_ipll" };
476 PNAME(mout_mx_mspll_ccore_p)    = {"sclk_bpll", "mout_sclk_dpll",
477                                         "mout_sclk_mpll", "ff_dout_spll2",
478                                         "mout_sclk_spll", "mout_sclk_epll"};
479 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
480                                         "mout_sclk_mpll",
481                                         "ff_dout_spll2" };
482 PNAME(mout_group8_5800_p)       = { "dout_aclk432_scaler", "dout_sclk_sw" };
483 PNAME(mout_group9_5800_p)       = { "dout_osc_div", "mout_sw_aclk432_scaler" };
484 PNAME(mout_group10_5800_p)      = { "dout_aclk432_cam", "dout_sclk_sw" };
485 PNAME(mout_group11_5800_p)      = { "dout_osc_div", "mout_sw_aclk432_cam" };
486 PNAME(mout_group12_5800_p)      = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
487 PNAME(mout_group13_5800_p)      = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
488 PNAME(mout_group14_5800_p)      = { "dout_aclk550_cam", "dout_sclk_sw" };
489 PNAME(mout_group15_5800_p)      = { "dout_osc_div", "mout_sw_aclk550_cam" };
490 
491 /* fixed rate clocks generated outside the soc */
492 static struct samsung_fixed_rate_clock
493                 exynos5x_fixed_rate_ext_clks[] __initdata = {
494         FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
495 };
496 
497 /* fixed rate clocks generated inside the soc */
498 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
499         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
500         FRATE(0, "sclk_pwi", NULL, 0, 24000000),
501         FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
502         FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
503         FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
504 };
505 
506 static const struct samsung_fixed_factor_clock
507                 exynos5x_fixed_factor_clks[] __initconst = {
508         FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
509         FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
510 };
511 
512 static const struct samsung_fixed_factor_clock
513                 exynos5800_fixed_factor_clks[] __initconst = {
514         FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
515         FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
516 };
517 
518 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
519         MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
520         MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
521         MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
522         MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
523 
524         MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
525         MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
526         MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
527         MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
528         MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
529 
530         MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
531         MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
532         MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
533         MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
534         MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
535         MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
536 
537         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
538                         mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
539         MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
540                         20, 2),
541         MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
542         MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
543 
544         MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
545         MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
546         MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
547         MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
548 
549         MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
550                                                         SRC_TOP9, 16, 1),
551         MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
552                                                         SRC_TOP9, 20, 1),
553         MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
554                                                         SRC_TOP9, 24, 1),
555         MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
556                                                         SRC_TOP9, 28, 1),
557 
558         MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
559         MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
560                                                         SRC_TOP13, 20, 1),
561         MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
562                                                         SRC_TOP13, 24, 1),
563         MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
564                                                         SRC_TOP13, 28, 1),
565 
566         MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
567 };
568 
569 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
570         DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
571                         "mout_aclk400_wcore", DIV_TOP0, 16, 3),
572         DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
573                                 DIV_TOP8, 16, 3),
574         DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
575                                 DIV_TOP8, 20, 3),
576         DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
577                                 DIV_TOP8, 24, 3),
578         DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
579                                 DIV_TOP8, 28, 3),
580 
581         DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
582         DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
583 };
584 
585 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
586         GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
587                                 GATE_BUS_TOP, 24, 0, 0),
588         GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
589                                 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
590 };
591 
592 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
593         MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
594         MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
595                                 TOP_SPARE2, 4, 1),
596 
597         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
598         MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
599                                 SRC_TOP0, 4, 2, "aclk400_mscl"),
600         MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
601         MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
602 
603         MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
604         MUX(0, "mout_aclk333_432_isp", mout_group4_p,
605                                 SRC_TOP1, 4, 2),
606         MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
607         MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
608         MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
609 
610         MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
611         MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
612         MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
613         MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
614         MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
615         MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
616 
617         MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
618                         mout_group5_5800_p, SRC_TOP7, 16, 2),
619         MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
620 
621         MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
622 };
623 
624 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
625         DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
626                         "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
627 };
628 
629 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
630         MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
631                         SRC_TOP7, 4, 1),
632         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
633         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
634 
635         MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
636               CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
637         MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
638         MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
639               CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
640         MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
641 
642         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
643         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
644         MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
645         MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
646 
647         MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
648         MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
649 
650         MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
651 
652         MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
653                         SRC_TOP3, 0, 1),
654         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
655                         SRC_TOP3, 4, 1),
656         MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
657                         mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
658         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
659                         SRC_TOP3, 12, 1),
660         MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
661                         SRC_TOP3, 16, 1),
662         MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
663                         SRC_TOP3, 20, 1),
664         MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
665                         SRC_TOP3, 24, 1),
666         MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
667                         SRC_TOP3, 28, 1),
668 
669         MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
670                         SRC_TOP4, 0, 1),
671         MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
672                         SRC_TOP4, 4, 1),
673         MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
674                         SRC_TOP4, 8, 1),
675         MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
676                         SRC_TOP4, 12, 1),
677         MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
678                         SRC_TOP4, 16, 1),
679         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
680         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
681         MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
682                         SRC_TOP4, 28, 1),
683 
684         MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
685                         mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
686         MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
687                         SRC_TOP5, 4, 1),
688         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
689                         SRC_TOP5, 8, 1),
690         MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
691                         SRC_TOP5, 12, 1),
692         MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
693                         SRC_TOP5, 16, 1),
694         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
695                         SRC_TOP5, 20, 1),
696         MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
697                         mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
698         MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
699                         mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
700 
701         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
702         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
703         MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
704         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
705         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
706         MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
707         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
708         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
709 
710         MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
711                         SRC_TOP10, 0, 1),
712         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
713                         SRC_TOP10, 4, 1),
714         MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
715                         SRC_TOP10, 8, 1),
716         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
717                         SRC_TOP10, 12, 1),
718         MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
719                         SRC_TOP10, 16, 1),
720         MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
721                         SRC_TOP10, 20, 1),
722         MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
723                         SRC_TOP10, 24, 1),
724         MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
725                         SRC_TOP10, 28, 1),
726 
727         MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
728                         SRC_TOP11, 0, 1),
729         MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
730                         SRC_TOP11, 4, 1),
731         MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
732         MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
733                         SRC_TOP11, 12, 1),
734         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
735         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
736         MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
737                         SRC_TOP11, 28, 1),
738 
739         MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
740                         mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
741         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
742                         SRC_TOP12, 8, 1),
743         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
744                         SRC_TOP12, 12, 1),
745         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
746         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
747                         SRC_TOP12, 20, 1),
748         MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
749                         mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
750         MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
751                         mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
752 
753         /* DISP1 Block */
754         MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
755         MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
756         MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
757         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
758         MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
759 
760         MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
761 
762         /* CDREX block */
763         MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
764                         SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
765         MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
766                         CLK_SET_RATE_PARENT, 0),
767 
768         /* MAU Block */
769         MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
770 
771         /* FSYS Block */
772         MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
773         MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
774         MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
775         MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
776         MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
777         MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
778         MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
779 
780         /* PERIC Block */
781         MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
782         MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
783         MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
784         MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
785         MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
786         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
787         MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
788         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
789         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
790         MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
791         MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
792         MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
793 
794         /* ISP Block */
795         MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
796         MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
797         MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
798         MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
799         MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
800 };
801 
802 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
803         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
804         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
805         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
806         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
807         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
808 
809         DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
810                         DIV_TOP0, 0, 3),
811         DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
812                         DIV_TOP0, 4, 3),
813         DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
814                         DIV_TOP0, 8, 3),
815         DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
816                         DIV_TOP0, 12, 3),
817         DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
818                         DIV_TOP0, 20, 3),
819         DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
820                         DIV_TOP0, 24, 3),
821         DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
822                         DIV_TOP0, 28, 3),
823         DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
824                         "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
825         DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
826                         "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
827         DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
828                         DIV_TOP1, 8, 6),
829         DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
830                         "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
831         DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
832                         DIV_TOP1, 20, 3),
833         DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
834                         DIV_TOP1, 24, 3),
835         DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
836                         DIV_TOP1, 28, 3),
837 
838         DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
839                         DIV_TOP2, 8, 3),
840         DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
841                         DIV_TOP2, 12, 3),
842         DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
843                         16, 3),
844         DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
845                         DIV_TOP2, 20, 3),
846         DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
847                         "mout_aclk300_disp1", DIV_TOP2, 24, 3),
848         DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
849                         DIV_TOP2, 28, 3),
850 
851         /* DISP1 Block */
852         DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
853         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
854         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
855         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
856         DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
857         DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
858                         "mout_aclk400_disp1", DIV_TOP2, 4, 3),
859 
860         /* CDREX Block */
861         DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
862                         DIV_CDREX0, 28, 3),
863         DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
864                         DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
865         DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
866                         DIV_CDREX0, 16, 3),
867         DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
868                         DIV_CDREX0, 8, 3),
869         DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
870                         DIV_CDREX0, 3, 5),
871 
872         DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
873                         DIV_CDREX1, 8, 3),
874 
875         /* Audio Block */
876         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
877         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
878 
879         /* USB3.0 */
880         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
881         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
882         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
883         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
884 
885         /* MMC */
886         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
887         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
888         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
889 
890         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
891         DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
892 
893         /* UART and PWM */
894         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
895         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
896         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
897         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
898         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
899 
900         /* SPI */
901         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
902         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
903         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
904 
905         /* Mfc Block */
906         DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
907 
908         /* PCM */
909         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
910         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
911 
912         /* Audio - I2S */
913         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
914         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
915         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
916         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
917         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
918 
919         /* SPI Pre-Ratio */
920         DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
921         DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
922         DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
923 
924         /* GSCL Block */
925         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
926                         DIV2_RATIO0, 4, 2),
927         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
928 
929         /* MSCL Block */
930         DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
931 
932         /* PSGEN */
933         DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
934         DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
935 
936         /* ISP Block */
937         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
938         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
939         DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
940         DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
941         DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
942         DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
943         DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
944         DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
945                         CLK_SET_RATE_PARENT, 0),
946         DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
947                         CLK_SET_RATE_PARENT, 0),
948 };
949 
950 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
951         /* G2D */
952         GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
953         GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
954         GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
955         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
956         GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
957 
958         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
959                         GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
960         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
961                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
962 
963         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
964                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
965         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
966                         GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
967         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
968                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
969         GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
970                         GATE_BUS_TOP, 5, 0, 0),
971         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
972                         GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
973         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
974                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
975         GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
976                         GATE_BUS_TOP, 8, 0, 0),
977         GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
978                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
979         GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
980                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
981         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
982                         GATE_BUS_TOP, 13, 0, 0),
983         GATE(0, "aclk166", "mout_user_aclk166",
984                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
985         GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
986                         GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
987         GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
988                         GATE_BUS_TOP, 16, 0, 0),
989         GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
990                         GATE_BUS_TOP, 17, 0, 0),
991         GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
992                         GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
993         GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
994                         GATE_BUS_TOP, 28, 0, 0),
995         GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
996                         GATE_BUS_TOP, 29, 0, 0),
997 
998         GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
999                         SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
1000 
1001         GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
1002                         SRC_MASK_TOP7, 20, 0, 0),
1003 
1004         /* sclk */
1005         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
1006                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1007         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
1008                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1009         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
1010                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1011         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
1012                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
1013         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
1014                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1015         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
1016                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1017         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
1018                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1019         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
1020                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
1021         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
1022                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1023         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
1024                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
1025         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
1026                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
1027         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1028                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
1029         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1030                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
1031 
1032         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1033                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
1034         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
1035                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
1036         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
1037                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1038         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
1039                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1040         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
1041                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1042         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
1043                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1044         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
1045                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1046 
1047         /* Display */
1048         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
1049                         GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1050         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
1051                         GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1052         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
1053                         GATE_TOP_SCLK_DISP1, 9, 0, 0),
1054         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
1055                         GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1056         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1057                         GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1058 
1059         /* Maudio Block */
1060         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1061                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1062         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1063                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1064 
1065         /* FSYS Block */
1066         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1067         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1068         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1069         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1070         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1071         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1072         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1073         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1074         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1075                         GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1076         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1077         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1078         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1079         GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1080                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1081 
1082         /* PERIC Block */
1083         GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1084                         GATE_IP_PERIC, 0, 0, 0),
1085         GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1086                         GATE_IP_PERIC, 1, 0, 0),
1087         GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1088                         GATE_IP_PERIC, 2, 0, 0),
1089         GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1090                         GATE_IP_PERIC, 3, 0, 0),
1091         GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1092                         GATE_IP_PERIC, 6, 0, 0),
1093         GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1094                         GATE_IP_PERIC, 7, 0, 0),
1095         GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1096                         GATE_IP_PERIC, 8, 0, 0),
1097         GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1098                         GATE_IP_PERIC, 9, 0, 0),
1099         GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1100                         GATE_IP_PERIC, 10, 0, 0),
1101         GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1102                         GATE_IP_PERIC, 11, 0, 0),
1103         GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1104                         GATE_IP_PERIC, 12, 0, 0),
1105         GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1106                         GATE_IP_PERIC, 13, 0, 0),
1107         GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1108                         GATE_IP_PERIC, 14, 0, 0),
1109         GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1110                         GATE_IP_PERIC, 15, 0, 0),
1111         GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1112                         GATE_IP_PERIC, 16, 0, 0),
1113         GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1114                         GATE_IP_PERIC, 17, 0, 0),
1115         GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1116                         GATE_IP_PERIC, 18, 0, 0),
1117         GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1118                         GATE_IP_PERIC, 20, 0, 0),
1119         GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1120                         GATE_IP_PERIC, 21, 0, 0),
1121         GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1122                         GATE_IP_PERIC, 22, 0, 0),
1123         GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1124                         GATE_IP_PERIC, 23, 0, 0),
1125         GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1126                         GATE_IP_PERIC, 24, 0, 0),
1127         GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1128                         GATE_IP_PERIC, 26, 0, 0),
1129         GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1130                         GATE_IP_PERIC, 28, 0, 0),
1131         GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1132                         GATE_IP_PERIC, 30, 0, 0),
1133         GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1134                         GATE_IP_PERIC, 31, 0, 0),
1135 
1136         GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1137                         GATE_BUS_PERIC, 22, 0, 0),
1138 
1139         /* PERIS Block */
1140         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1141                         GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1142         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1143                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1144         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1145         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1146         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1147         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1148         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1149         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1150         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1151         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1152         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1153         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1154         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1155         GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1156         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1157         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1158         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1159         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1160 
1161         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
1162 
1163         /* GEN Block */
1164         GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1165         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1166         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1167         GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1168         GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1169         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1170                         GATE_IP_GEN, 6, 0, 0),
1171         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1172         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1173                         GATE_IP_GEN, 9, 0, 0),
1174 
1175         /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1176         GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1177                         GATE_BUS_GEN, 28, 0, 0),
1178         GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1179 
1180         /* GSCL Block */
1181         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1182                         GATE_TOP_SCLK_GSCL, 6, 0, 0),
1183         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1184                         GATE_TOP_SCLK_GSCL, 7, 0, 0),
1185 
1186         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1187         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1188         GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1189                         GATE_IP_GSCL0, 4, 0, 0),
1190         GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1191                         GATE_IP_GSCL0, 5, 0, 0),
1192         GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1193                         GATE_IP_GSCL0, 6, 0, 0),
1194 
1195         GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1196                         GATE_IP_GSCL1, 2, 0, 0),
1197         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1198                         GATE_IP_GSCL1, 3, 0, 0),
1199         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1200                         GATE_IP_GSCL1, 4, 0, 0),
1201         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1202                         GATE_IP_GSCL1, 6, 0, 0),
1203         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1204                         GATE_IP_GSCL1, 7, 0, 0),
1205         GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1206         GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1207         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1208                         GATE_IP_GSCL1, 16, 0, 0),
1209         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1210                         GATE_IP_GSCL1, 17, 0, 0),
1211 
1212         /* MSCL Block */
1213         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1214         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1215         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1216         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1217                         GATE_IP_MSCL, 8, 0, 0),
1218         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1219                         GATE_IP_MSCL, 9, 0, 0),
1220         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1221                         GATE_IP_MSCL, 10, 0, 0),
1222 
1223         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1224         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1225         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1226         GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1227         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1228         GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1229                         GATE_IP_DISP1, 7, 0, 0),
1230         GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1231                         GATE_IP_DISP1, 8, 0, 0),
1232         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1233                         GATE_IP_DISP1, 9, 0, 0),
1234 
1235         /* ISP */
1236         GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1237                         GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1238         GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1239                         GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1240         GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1241                         GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1242         GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1243                         GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1244         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1245                         GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1246         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1247                         GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1248         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1249                         GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1250 
1251         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1252         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1253         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1254 
1255         GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1256 };
1257 
1258 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1259         PLL_35XX_RATE(2000000000, 250, 3, 0),
1260         PLL_35XX_RATE(1900000000, 475, 6, 0),
1261         PLL_35XX_RATE(1800000000, 225, 3, 0),
1262         PLL_35XX_RATE(1700000000, 425, 6, 0),
1263         PLL_35XX_RATE(1600000000, 200, 3, 0),
1264         PLL_35XX_RATE(1500000000, 250, 4, 0),
1265         PLL_35XX_RATE(1400000000, 175, 3, 0),
1266         PLL_35XX_RATE(1300000000, 325, 6, 0),
1267         PLL_35XX_RATE(1200000000, 200, 2, 1),
1268         PLL_35XX_RATE(1100000000, 275, 3, 1),
1269         PLL_35XX_RATE(1000000000, 250, 3, 1),
1270         PLL_35XX_RATE(900000000,  150, 2, 1),
1271         PLL_35XX_RATE(800000000,  200, 3, 1),
1272         PLL_35XX_RATE(700000000,  175, 3, 1),
1273         PLL_35XX_RATE(600000000,  200, 2, 2),
1274         PLL_35XX_RATE(500000000,  250, 3, 2),
1275         PLL_35XX_RATE(400000000,  200, 3, 2),
1276         PLL_35XX_RATE(300000000,  200, 2, 3),
1277         PLL_35XX_RATE(200000000,  200, 3, 3),
1278 };
1279 
1280 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1281         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1282                 APLL_CON0, NULL),
1283         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1284                 CPLL_CON0, NULL),
1285         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1286                 DPLL_CON0, NULL),
1287         [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1288                 EPLL_CON0, NULL),
1289         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1290                 RPLL_CON0, NULL),
1291         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1292                 IPLL_CON0, NULL),
1293         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1294                 SPLL_CON0, NULL),
1295         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1296                 VPLL_CON0, NULL),
1297         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1298                 MPLL_CON0, NULL),
1299         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1300                 BPLL_CON0, NULL),
1301         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1302                 KPLL_CON0, NULL),
1303 };
1304 
1305 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)                       \
1306                 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1307                  ((cpud) << 4)))
1308 
1309 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1310         { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1311         { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1312         { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1313         { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1314         { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1315         { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1316         { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1317         { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1318         { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1319         {  900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1320         {  800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1321         {  700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1322         {  600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1323         {  500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1324         {  400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1325         {  300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1326         {  200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1327         {  0 },
1328 };
1329 
1330 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1331         { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1332         { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1333         { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1334         { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1335         { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1336         { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1337         { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1338         { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1339         { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1340         { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1341         { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1342         {  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1343         {  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1344         {  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1345         {  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1346         {  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1347         {  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1348         {  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1349         {  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1350         {  0 },
1351 };
1352 
1353 #define E5420_KFC_DIV(kpll, pclk, aclk)                                 \
1354                 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1355 
1356 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
1357         { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
1358         { 1300000, E5420_KFC_DIV(3, 5, 2), },
1359         { 1200000, E5420_KFC_DIV(3, 5, 2), },
1360         { 1100000, E5420_KFC_DIV(3, 5, 2), },
1361         { 1000000, E5420_KFC_DIV(3, 5, 2), },
1362         {  900000, E5420_KFC_DIV(3, 5, 2), },
1363         {  800000, E5420_KFC_DIV(3, 5, 2), },
1364         {  700000, E5420_KFC_DIV(3, 4, 2), },
1365         {  600000, E5420_KFC_DIV(3, 4, 2), },
1366         {  500000, E5420_KFC_DIV(3, 4, 2), },
1367         {  400000, E5420_KFC_DIV(3, 3, 2), },
1368         {  300000, E5420_KFC_DIV(3, 3, 2), },
1369         {  200000, E5420_KFC_DIV(3, 3, 2), },
1370         {  0 },
1371 };
1372 
1373 static const struct of_device_id ext_clk_match[] __initconst = {
1374         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1375         { },
1376 };
1377 
1378 /* register exynos5420 clocks */
1379 static void __init exynos5x_clk_init(struct device_node *np,
1380                 enum exynos5x_soc soc)
1381 {
1382         struct samsung_clk_provider *ctx;
1383 
1384         if (np) {
1385                 reg_base = of_iomap(np, 0);
1386                 if (!reg_base)
1387                         panic("%s: failed to map registers\n", __func__);
1388         } else {
1389                 panic("%s: unable to determine soc\n", __func__);
1390         }
1391 
1392         exynos5x_soc = soc;
1393 
1394         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1395 
1396         samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1397                         ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1398                         ext_clk_match);
1399 
1400         if (_get_rate("fin_pll") == 24 * MHZ) {
1401                 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1402                 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1403                 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1404         }
1405 
1406         samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1407                                         reg_base);
1408         samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1409                         ARRAY_SIZE(exynos5x_fixed_rate_clks));
1410         samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1411                         ARRAY_SIZE(exynos5x_fixed_factor_clks));
1412         samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1413                         ARRAY_SIZE(exynos5x_mux_clks));
1414         samsung_clk_register_div(ctx, exynos5x_div_clks,
1415                         ARRAY_SIZE(exynos5x_div_clks));
1416         samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1417                         ARRAY_SIZE(exynos5x_gate_clks));
1418 
1419         if (soc == EXYNOS5420) {
1420                 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1421                                 ARRAY_SIZE(exynos5420_mux_clks));
1422                 samsung_clk_register_div(ctx, exynos5420_div_clks,
1423                                 ARRAY_SIZE(exynos5420_div_clks));
1424         } else {
1425                 samsung_clk_register_fixed_factor(
1426                                 ctx, exynos5800_fixed_factor_clks,
1427                                 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1428                 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1429                                 ARRAY_SIZE(exynos5800_mux_clks));
1430                 samsung_clk_register_div(ctx, exynos5800_div_clks,
1431                                 ARRAY_SIZE(exynos5800_div_clks));
1432                 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1433                                 ARRAY_SIZE(exynos5800_gate_clks));
1434         }
1435 
1436         if (soc == EXYNOS5420) {
1437                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1438                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
1439                         exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1440         } else {
1441                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1442                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
1443                         exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1444         }
1445         exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1446                 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1447                 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1448 
1449         exynos5420_clk_sleep_init();
1450 
1451         samsung_clk_of_add_provider(np, ctx);
1452 }
1453 
1454 static void __init exynos5420_clk_init(struct device_node *np)
1455 {
1456         exynos5x_clk_init(np, EXYNOS5420);
1457 }
1458 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1459 
1460 static void __init exynos5800_clk_init(struct device_node *np)
1461 {
1462         exynos5x_clk_init(np, EXYNOS5800);
1463 }
1464 CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
1465 

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