Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5

Linux/drivers/clk/samsung/clk-exynos5250.c

  1 /*
  2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3  * Copyright (c) 2013 Linaro Ltd.
  4  * Author: Thomas Abraham <thomas.ab@samsung.com>
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License version 2 as
  8  * published by the Free Software Foundation.
  9  *
 10  * Common Clock Framework support for Exynos5250 SoC.
 11 */
 12 
 13 #include <dt-bindings/clock/exynos5250.h>
 14 #include <linux/clk-provider.h>
 15 #include <linux/of.h>
 16 #include <linux/of_address.h>
 17 #include <linux/syscore_ops.h>
 18 
 19 #include "clk.h"
 20 #include "clk-cpu.h"
 21 
 22 #define APLL_LOCK               0x0
 23 #define APLL_CON0               0x100
 24 #define SRC_CPU                 0x200
 25 #define DIV_CPU0                0x500
 26 #define PWR_CTRL1               0x1020
 27 #define PWR_CTRL2               0x1024
 28 #define MPLL_LOCK               0x4000
 29 #define MPLL_CON0               0x4100
 30 #define SRC_CORE1               0x4204
 31 #define GATE_IP_ACP             0x8800
 32 #define GATE_IP_ISP0            0xc800
 33 #define GATE_IP_ISP1            0xc804
 34 #define CPLL_LOCK               0x10020
 35 #define EPLL_LOCK               0x10030
 36 #define VPLL_LOCK               0x10040
 37 #define GPLL_LOCK               0x10050
 38 #define CPLL_CON0               0x10120
 39 #define EPLL_CON0               0x10130
 40 #define VPLL_CON0               0x10140
 41 #define GPLL_CON0               0x10150
 42 #define SRC_TOP0                0x10210
 43 #define SRC_TOP1                0x10214
 44 #define SRC_TOP2                0x10218
 45 #define SRC_TOP3                0x1021c
 46 #define SRC_GSCL                0x10220
 47 #define SRC_DISP1_0             0x1022c
 48 #define SRC_MAU                 0x10240
 49 #define SRC_FSYS                0x10244
 50 #define SRC_GEN                 0x10248
 51 #define SRC_PERIC0              0x10250
 52 #define SRC_PERIC1              0x10254
 53 #define SRC_MASK_GSCL           0x10320
 54 #define SRC_MASK_DISP1_0        0x1032c
 55 #define SRC_MASK_MAU            0x10334
 56 #define SRC_MASK_FSYS           0x10340
 57 #define SRC_MASK_GEN            0x10344
 58 #define SRC_MASK_PERIC0         0x10350
 59 #define SRC_MASK_PERIC1         0x10354
 60 #define DIV_TOP0                0x10510
 61 #define DIV_TOP1                0x10514
 62 #define DIV_GSCL                0x10520
 63 #define DIV_DISP1_0             0x1052c
 64 #define DIV_GEN                 0x1053c
 65 #define DIV_MAU                 0x10544
 66 #define DIV_FSYS0               0x10548
 67 #define DIV_FSYS1               0x1054c
 68 #define DIV_FSYS2               0x10550
 69 #define DIV_PERIC0              0x10558
 70 #define DIV_PERIC1              0x1055c
 71 #define DIV_PERIC2              0x10560
 72 #define DIV_PERIC3              0x10564
 73 #define DIV_PERIC4              0x10568
 74 #define DIV_PERIC5              0x1056c
 75 #define GATE_IP_GSCL            0x10920
 76 #define GATE_IP_DISP1           0x10928
 77 #define GATE_IP_MFC             0x1092c
 78 #define GATE_IP_G3D             0x10930
 79 #define GATE_IP_GEN             0x10934
 80 #define GATE_IP_FSYS            0x10944
 81 #define GATE_IP_PERIC           0x10950
 82 #define GATE_IP_PERIS           0x10960
 83 #define BPLL_LOCK               0x20010
 84 #define BPLL_CON0               0x20110
 85 #define SRC_CDREX               0x20200
 86 #define PLL_DIV2_SEL            0x20a24
 87 
 88 /*Below definitions are used for PWR_CTRL settings*/
 89 #define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
 90 #define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
 91 #define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
 92 #define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
 93 #define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
 94 #define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
 95 #define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
 96 #define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
 97 
 98 #define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
 99 #define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
100 #define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
101 #define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
102 #define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
103 #define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
104 
105 /* list of PLLs to be registered */
106 enum exynos5250_plls {
107         apll, mpll, cpll, epll, vpll, gpll, bpll,
108         nr_plls                 /* number of PLLs */
109 };
110 
111 static void __iomem *reg_base;
112 
113 #ifdef CONFIG_PM_SLEEP
114 static struct samsung_clk_reg_dump *exynos5250_save;
115 
116 /*
117  * list of controller registers to be saved and restored during a
118  * suspend/resume cycle.
119  */
120 static unsigned long exynos5250_clk_regs[] __initdata = {
121         SRC_CPU,
122         DIV_CPU0,
123         PWR_CTRL1,
124         PWR_CTRL2,
125         SRC_CORE1,
126         SRC_TOP0,
127         SRC_TOP1,
128         SRC_TOP2,
129         SRC_TOP3,
130         SRC_GSCL,
131         SRC_DISP1_0,
132         SRC_MAU,
133         SRC_FSYS,
134         SRC_GEN,
135         SRC_PERIC0,
136         SRC_PERIC1,
137         SRC_MASK_GSCL,
138         SRC_MASK_DISP1_0,
139         SRC_MASK_MAU,
140         SRC_MASK_FSYS,
141         SRC_MASK_GEN,
142         SRC_MASK_PERIC0,
143         SRC_MASK_PERIC1,
144         DIV_TOP0,
145         DIV_TOP1,
146         DIV_GSCL,
147         DIV_DISP1_0,
148         DIV_GEN,
149         DIV_MAU,
150         DIV_FSYS0,
151         DIV_FSYS1,
152         DIV_FSYS2,
153         DIV_PERIC0,
154         DIV_PERIC1,
155         DIV_PERIC2,
156         DIV_PERIC3,
157         DIV_PERIC4,
158         DIV_PERIC5,
159         GATE_IP_GSCL,
160         GATE_IP_MFC,
161         GATE_IP_G3D,
162         GATE_IP_GEN,
163         GATE_IP_FSYS,
164         GATE_IP_PERIC,
165         GATE_IP_PERIS,
166         SRC_CDREX,
167         PLL_DIV2_SEL,
168         GATE_IP_DISP1,
169         GATE_IP_ACP,
170         GATE_IP_ISP0,
171         GATE_IP_ISP1,
172 };
173 
174 static int exynos5250_clk_suspend(void)
175 {
176         samsung_clk_save(reg_base, exynos5250_save,
177                                 ARRAY_SIZE(exynos5250_clk_regs));
178 
179         return 0;
180 }
181 
182 static void exynos5250_clk_resume(void)
183 {
184         samsung_clk_restore(reg_base, exynos5250_save,
185                                 ARRAY_SIZE(exynos5250_clk_regs));
186 }
187 
188 static struct syscore_ops exynos5250_clk_syscore_ops = {
189         .suspend = exynos5250_clk_suspend,
190         .resume = exynos5250_clk_resume,
191 };
192 
193 static void exynos5250_clk_sleep_init(void)
194 {
195         exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
196                                         ARRAY_SIZE(exynos5250_clk_regs));
197         if (!exynos5250_save) {
198                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
199                         __func__);
200                 return;
201         }
202 
203         register_syscore_ops(&exynos5250_clk_syscore_ops);
204 }
205 #else
206 static void exynos5250_clk_sleep_init(void) {}
207 #endif
208 
209 /* list of all parent clock list */
210 PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
211 PNAME(mout_cpu_p)       = { "mout_apll", "mout_mpll", };
212 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
213 PNAME(mout_mpll_p)      = { "fin_pll", "mout_mpll_fout" };
214 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
215 PNAME(mout_bpll_p)      = { "fin_pll", "mout_bpll_fout" };
216 PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi27m" };
217 PNAME(mout_vpll_p)      = { "mout_vpllsrc", "fout_vpll" };
218 PNAME(mout_cpll_p)      = { "fin_pll", "fout_cpll" };
219 PNAME(mout_epll_p)      = { "fin_pll", "fout_epll" };
220 PNAME(mout_gpll_p)      = { "fin_pll", "fout_gpll" };
221 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
222 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
223 PNAME(mout_aclk166_p)   = { "mout_cpll", "mout_mpll_user" };
224 PNAME(mout_aclk200_p)   = { "mout_mpll_user", "mout_bpll_user" };
225 PNAME(mout_aclk300_p)   = { "mout_aclk300_disp1_mid",
226                             "mout_aclk300_disp1_mid1" };
227 PNAME(mout_aclk400_p)   = { "mout_aclk400_g3d_mid", "mout_gpll" };
228 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
229 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
230 PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
231 PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
232 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
233 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
234 PNAME(mout_hdmi_p)      = { "div_hdmi_pixel", "sclk_hdmiphy" };
235 PNAME(mout_usb3_p)      = { "mout_mpll_user", "mout_cpll" };
236 PNAME(mout_group1_p)    = { "fin_pll", "fin_pll", "sclk_hdmi27m",
237                                 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
238                                 "mout_mpll_user", "mout_epll", "mout_vpll",
239                                 "mout_cpll", "none", "none",
240                                 "none", "none", "none",
241                                 "none" };
242 PNAME(mout_audio0_p)    = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
243                                 "sclk_uhostphy", "fin_pll",
244                                 "mout_mpll_user", "mout_epll", "mout_vpll",
245                                 "mout_cpll", "none", "none",
246                                 "none", "none", "none",
247                                 "none" };
248 PNAME(mout_audio1_p)    = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
249                                 "sclk_uhostphy", "fin_pll",
250                                 "mout_mpll_user", "mout_epll", "mout_vpll",
251                                 "mout_cpll", "none", "none",
252                                 "none", "none", "none",
253                                 "none" };
254 PNAME(mout_audio2_p)    = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
255                                 "sclk_uhostphy", "fin_pll",
256                                 "mout_mpll_user", "mout_epll", "mout_vpll",
257                                 "mout_cpll", "none", "none",
258                                 "none", "none", "none",
259                                 "none" };
260 PNAME(mout_spdif_p)     = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
261                                 "spdif_extclk" };
262 
263 /* fixed rate clocks generated outside the soc */
264 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
265         FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
266 };
267 
268 /* fixed rate clocks generated inside the soc */
269 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
270         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
271         FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
272         FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
273         FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
274 };
275 
276 static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
277         FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
278         FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
279 };
280 
281 static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
282         MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
283 };
284 
285 static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
286         /*
287          * NOTE: Following table is sorted by (clock domain, register address,
288          * bitfield shift) triplet in ascending order. When adding new entries,
289          * please make sure that the order is kept, to avoid merge conflicts
290          * and make further work with defined data easier.
291          */
292 
293         /*
294          * CMU_CPU
295          */
296         MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
297                                         CLK_SET_RATE_PARENT, 0, "mout_apll"),
298         MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
299 
300         /*
301          * CMU_CORE
302          */
303         MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
304 
305         /*
306          * CMU_TOP
307          */
308         MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
309         MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
310         MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
311         MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
312         MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
313         MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
314 
315         MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
316                 8, 1),
317         MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
318         MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
319 
320         MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
321         MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
322         MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
323         MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
324         MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
325         MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
326 
327         MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
328                 mout_aclk200_sub_p, SRC_TOP3, 4, 1),
329         MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
330                 mout_aclk300_sub_p, SRC_TOP3, 6, 1),
331         MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
332         MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
333         MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
334                         SRC_TOP3, 20, 1),
335         MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
336 
337         MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
338         MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
339         MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
340         MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
341         MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
342 
343         MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
344         MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
345         MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
346         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
347 
348         MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
349 
350         MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
351         MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
352         MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
353         MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
354         MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
355         MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
356 
357         MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
358 
359         MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
360         MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
361         MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
362         MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
363         MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
364 
365         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
366         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
367         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
368         MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
369         MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
370         MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
371 
372         /*
373          * CMU_CDREX
374          */
375         MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
376 
377         MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
378         MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
379 };
380 
381 static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
382         /*
383          * NOTE: Following table is sorted by (clock domain, register address,
384          * bitfield shift) triplet in ascending order. When adding new entries,
385          * please make sure that the order is kept, to avoid merge conflicts
386          * and make further work with defined data easier.
387          */
388 
389         /*
390          * CMU_CPU
391          */
392         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
393         DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
394         DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
395 
396         /*
397          * CMU_TOP
398          */
399         DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
400         DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
401         DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
402         DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
403         DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
404         DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
405                                                         24, 3),
406         DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
407 
408         DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
409         DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
410 
411         DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
412         DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
413         DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
414         DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
415         DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
416 
417         DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
418         DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
419         DIV_F(0, "div_mipi1_pre", "div_mipi1",
420                         DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
421         DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
422         DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
423 
424         DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
425 
426         DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
427         DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
428 
429         DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
430         DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
431 
432         DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
433         DIV_F(0, "div_mmc_pre0", "div_mmc0",
434                         DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
435         DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
436         DIV_F(0, "div_mmc_pre1", "div_mmc1",
437                         DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
438 
439         DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
440         DIV_F(0, "div_mmc_pre2", "div_mmc2",
441                         DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
442         DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
443         DIV_F(0, "div_mmc_pre3", "div_mmc3",
444                         DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
445 
446         DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
447         DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
448         DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
449         DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
450 
451         DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
452         DIV_F(0, "div_spi_pre0", "div_spi0",
453                         DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
454         DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
455         DIV_F(0, "div_spi_pre1", "div_spi1",
456                         DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
457 
458         DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
459         DIV_F(0, "div_spi_pre2", "div_spi2",
460                         DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
461 
462         DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
463 
464         DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
465         DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
466         DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
467         DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
468 
469         DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
470         DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
471 };
472 
473 static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
474         /*
475          * NOTE: Following table is sorted by (clock domain, register address,
476          * bitfield shift) triplet in ascending order. When adding new entries,
477          * please make sure that the order is kept, to avoid merge conflicts
478          * and make further work with defined data easier.
479          */
480 
481         /*
482          * CMU_ACP
483          */
484         GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
485         GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
486         GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
487         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
488 
489         /*
490          * CMU_TOP
491          */
492         GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
493                         SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
494         GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
495                         SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
496         GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
497                         SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
498         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
499                         SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
500         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
501                         SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
502 
503         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
504                         SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
505         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
506                         SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
507         GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
508                         SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
509         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
510                         SRC_MASK_DISP1_0, 20, 0, 0),
511 
512         GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
513                         SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
514 
515         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
516                         SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
517         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
518                         SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
519         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
520                         SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
521         GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
522                         SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
523         GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
524                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
525         GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
526                         SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
527 
528         GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
529                         SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
530 
531         GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
532                         SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
533         GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
534                         SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
535         GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
536                         SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
537         GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
538                         SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
539         GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
540                         SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
541 
542         GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
543                         SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
544         GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
545                         SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
546         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
547                         SRC_MASK_PERIC1, 4, 0, 0),
548         GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
549                         SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
550         GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
551                         SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
552         GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
553                         SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
554 
555         GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
556                 0),
557         GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
558                 0),
559         GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
560                 0),
561         GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
562                 0),
563         GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
564         GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
565         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
566                         GATE_IP_GSCL, 7, 0, 0),
567         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
568                         GATE_IP_GSCL, 8, 0, 0),
569         GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
570                         GATE_IP_GSCL, 9, 0, 0),
571         GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
572                         GATE_IP_GSCL, 10, 0, 0),
573 
574         GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
575                 0),
576         GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
577                 0),
578         GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
579                 0),
580         GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
581         GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
582                 0),
583         GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
584                 0),
585 
586         GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
587         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
588                 0),
589         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
590                 0),
591         GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
592                                         CLK_SET_RATE_PARENT, 0),
593         GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
594         GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
595         GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
596         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
597                 0),
598         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
599         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
600 
601         GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
602         GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
603         GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
604         GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
605         GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
606         GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
607         GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
608         GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
609         GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
610         GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
611         GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
612         GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
613         GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
614                         GATE_IP_FSYS, 24, 0, 0),
615         GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
616                 0),
617 
618         GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
619         GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
620         GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
621         GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
622         GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
623         GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
624         GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
625         GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
626         GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
627         GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
628         GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
629         GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
630         GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
631         GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
632         GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
633         GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
634         GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
635         GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
636         GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
637         GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
638         GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
639         GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
640         GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
641         GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
642         GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
643         GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
644         GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
645         GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
646         GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
647 
648         GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
649         GATE(CLK_SYSREG, "sysreg", "div_aclk66",
650                         GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
651         GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
652                 0),
653         GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
654                         GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
655         GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
656                         GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
657         GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
658                         GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
659         GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
660         GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
661         GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
662         GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
663         GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
664         GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
665         GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
666         GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
667         GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
668         GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
669         GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
670         GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
671         GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
672         GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
673         GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
674         GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
675                         GATE_IP_DISP1, 9, 0, 0),
676         GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
677                         GATE_IP_DISP1, 8, 0, 0),
678         GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
679         GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
680                         GATE_IP_ISP0, 8, 0, 0),
681         GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
682                         GATE_IP_ISP0, 9, 0, 0),
683         GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
684                         GATE_IP_ISP0, 10, 0, 0),
685         GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
686                         GATE_IP_ISP0, 11, 0, 0),
687         GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
688                         GATE_IP_ISP0, 12, 0, 0),
689         GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
690                         GATE_IP_ISP0, 13, 0, 0),
691         GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
692                         GATE_IP_ISP1, 4, 0, 0),
693         GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
694                         GATE_IP_ISP1, 5, 0, 0),
695         GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
696                         GATE_IP_ISP1, 6, 0, 0),
697         GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
698                         GATE_IP_ISP1, 7, 0, 0),
699 };
700 
701 static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
702         /* sorted in descending order */
703         /* PLL_36XX_RATE(rate, m, p, s, k) */
704         PLL_36XX_RATE(266000000, 266, 3, 3, 0),
705         /* Not in UM, but need for eDP on snow */
706         PLL_36XX_RATE(70500000, 94, 2, 4, 0),
707         { },
708 };
709 
710 static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
711         /* sorted in descending order */
712         /* PLL_36XX_RATE(rate, m, p, s, k) */
713         PLL_36XX_RATE(192000000, 64, 2, 2, 0),
714         PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
715         PLL_36XX_RATE(180000000, 90, 3, 2, 0),
716         PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
717         PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
718         PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
719         PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
720         PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
721         { },
722 };
723 
724 static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
725         /* sorted in descending order */
726         /* PLL_35XX_RATE(rate, m, p, s) */
727         PLL_35XX_RATE(1700000000, 425, 6, 0),
728         PLL_35XX_RATE(1600000000, 200, 3, 0),
729         PLL_35XX_RATE(1500000000, 250, 4, 0),
730         PLL_35XX_RATE(1400000000, 175, 3, 0),
731         PLL_35XX_RATE(1300000000, 325, 6, 0),
732         PLL_35XX_RATE(1200000000, 200, 4, 0),
733         PLL_35XX_RATE(1100000000, 275, 6, 0),
734         PLL_35XX_RATE(1000000000, 125, 3, 0),
735         PLL_35XX_RATE(900000000, 150, 4, 0),
736         PLL_35XX_RATE(800000000, 100, 3, 0),
737         PLL_35XX_RATE(700000000, 175, 3, 1),
738         PLL_35XX_RATE(600000000, 200, 4, 1),
739         PLL_35XX_RATE(500000000, 125, 3, 1),
740         PLL_35XX_RATE(400000000, 100, 3, 1),
741         PLL_35XX_RATE(300000000, 200, 4, 2),
742         PLL_35XX_RATE(200000000, 100, 3, 2),
743 };
744 
745 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
746         [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
747                 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
748         [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
749                 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
750         [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
751                 BPLL_CON0, NULL),
752         [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
753                 GPLL_CON0, NULL),
754         [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
755                 CPLL_CON0, NULL),
756         [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
757                 EPLL_CON0, NULL),
758         [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
759                 VPLL_LOCK, VPLL_CON0, NULL),
760 };
761 
762 #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud)          \
763                 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
764                  ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
765 #define E5250_CPU_DIV1(hpm, copy)                                       \
766                 (((hpm) << 4) | (copy))
767 
768 static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
769         { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
770         { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
771         { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
772         { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
773         { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
774         { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
775         { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
776         { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
777         {  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
778         {  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
779         {  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
780         {  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
781         {  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
782         {  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
783         {  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
784         {  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
785         {  0 },
786 };
787 
788 static const struct of_device_id ext_clk_match[] __initconst = {
789         { .compatible = "samsung,clock-xxti", .data = (void *)0, },
790         { },
791 };
792 
793 /* register exynox5250 clocks */
794 static void __init exynos5250_clk_init(struct device_node *np)
795 {
796         struct samsung_clk_provider *ctx;
797         unsigned int tmp;
798 
799         if (np) {
800                 reg_base = of_iomap(np, 0);
801                 if (!reg_base)
802                         panic("%s: failed to map registers\n", __func__);
803         } else {
804                 panic("%s: unable to determine soc\n", __func__);
805         }
806 
807         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
808         if (!ctx)
809                 panic("%s: unable to allocate context.\n", __func__);
810         samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
811                         ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
812                         ext_clk_match);
813         samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
814                                 ARRAY_SIZE(exynos5250_pll_pmux_clks));
815 
816         if (_get_rate("fin_pll") == 24 * MHZ) {
817                 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
818                 exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
819         }
820 
821         if (_get_rate("mout_vpllsrc") == 24 * MHZ)
822                 exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
823 
824         samsung_clk_register_pll(ctx, exynos5250_plls,
825                         ARRAY_SIZE(exynos5250_plls),
826                         reg_base);
827         samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
828                         ARRAY_SIZE(exynos5250_fixed_rate_clks));
829         samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
830                         ARRAY_SIZE(exynos5250_fixed_factor_clks));
831         samsung_clk_register_mux(ctx, exynos5250_mux_clks,
832                         ARRAY_SIZE(exynos5250_mux_clks));
833         samsung_clk_register_div(ctx, exynos5250_div_clks,
834                         ARRAY_SIZE(exynos5250_div_clks));
835         samsung_clk_register_gate(ctx, exynos5250_gate_clks,
836                         ARRAY_SIZE(exynos5250_gate_clks));
837         exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
838                         mout_cpu_p[0], mout_cpu_p[1], 0x200,
839                         exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
840                         CLK_CPU_HAS_DIV1);
841 
842         /*
843          * Enable arm clock down (in idle) and set arm divider
844          * ratios in WFI/WFE state.
845          */
846         tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
847                 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
848                 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
849                 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
850         __raw_writel(tmp, reg_base + PWR_CTRL1);
851 
852         /*
853          * Enable arm clock up (on exiting idle). Set arm divider
854          * ratios when not in idle along with the standby duration
855          * ratios.
856          */
857         tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
858                 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
859                 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
860         __raw_writel(tmp, reg_base + PWR_CTRL2);
861 
862         exynos5250_clk_sleep_init();
863 
864         samsung_clk_of_add_provider(np, ctx);
865 
866         pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
867                         _get_rate("div_arm2"));
868 }
869 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
870 

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