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Linux/drivers/clk/samsung/clk-exynos-audss.c

  1 /*
  2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3  * Author: Padmavathi Venna <padma.v@samsung.com>
  4  *
  5  * This program is free software; you can redistribute it and/or modify
  6  * it under the terms of the GNU General Public License version 2 as
  7  * published by the Free Software Foundation.
  8  *
  9  * Common Clock Framework support for Audio Subsystem Clock Controller.
 10 */
 11 
 12 #include <linux/clkdev.h>
 13 #include <linux/io.h>
 14 #include <linux/clk-provider.h>
 15 #include <linux/of_address.h>
 16 #include <linux/syscore_ops.h>
 17 #include <linux/module.h>
 18 #include <linux/platform_device.h>
 19 
 20 #include <dt-bindings/clock/exynos-audss-clk.h>
 21 
 22 enum exynos_audss_clk_type {
 23         TYPE_EXYNOS4210,
 24         TYPE_EXYNOS5250,
 25         TYPE_EXYNOS5420,
 26 };
 27 
 28 static DEFINE_SPINLOCK(lock);
 29 static struct clk **clk_table;
 30 static void __iomem *reg_base;
 31 static struct clk_onecell_data clk_data;
 32 /*
 33  * On Exynos5420 this will be a clock which has to be enabled before any
 34  * access to audss registers. Typically a child of EPLL.
 35  *
 36  * On other platforms this will be -ENODEV.
 37  */
 38 static struct clk *epll;
 39 
 40 #define ASS_CLK_SRC 0x0
 41 #define ASS_CLK_DIV 0x4
 42 #define ASS_CLK_GATE 0x8
 43 
 44 #ifdef CONFIG_PM_SLEEP
 45 static unsigned long reg_save[][2] = {
 46         {ASS_CLK_SRC,  0},
 47         {ASS_CLK_DIV,  0},
 48         {ASS_CLK_GATE, 0},
 49 };
 50 
 51 static int exynos_audss_clk_suspend(void)
 52 {
 53         int i;
 54 
 55         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
 56                 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
 57 
 58         return 0;
 59 }
 60 
 61 static void exynos_audss_clk_resume(void)
 62 {
 63         int i;
 64 
 65         for (i = 0; i < ARRAY_SIZE(reg_save); i++)
 66                 writel(reg_save[i][1], reg_base + reg_save[i][0]);
 67 }
 68 
 69 static struct syscore_ops exynos_audss_clk_syscore_ops = {
 70         .suspend        = exynos_audss_clk_suspend,
 71         .resume         = exynos_audss_clk_resume,
 72 };
 73 #endif /* CONFIG_PM_SLEEP */
 74 
 75 static const struct of_device_id exynos_audss_clk_of_match[] = {
 76         { .compatible = "samsung,exynos4210-audss-clock",
 77           .data = (void *)TYPE_EXYNOS4210, },
 78         { .compatible = "samsung,exynos5250-audss-clock",
 79           .data = (void *)TYPE_EXYNOS5250, },
 80         { .compatible = "samsung,exynos5420-audss-clock",
 81           .data = (void *)TYPE_EXYNOS5420, },
 82         {},
 83 };
 84 
 85 static void exynos_audss_clk_teardown(void)
 86 {
 87         int i;
 88 
 89         for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
 90                 if (!IS_ERR(clk_table[i]))
 91                         clk_unregister_mux(clk_table[i]);
 92         }
 93 
 94         for (; i < EXYNOS_SRP_CLK; i++) {
 95                 if (!IS_ERR(clk_table[i]))
 96                         clk_unregister_divider(clk_table[i]);
 97         }
 98 
 99         for (; i < clk_data.clk_num; i++) {
100                 if (!IS_ERR(clk_table[i]))
101                         clk_unregister_gate(clk_table[i]);
102         }
103 }
104 
105 /* register exynos_audss clocks */
106 static int exynos_audss_clk_probe(struct platform_device *pdev)
107 {
108         int i, ret = 0;
109         struct resource *res;
110         const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
111         const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
112         const char *sclk_pcm_p = "sclk_pcm0";
113         struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
114         const struct of_device_id *match;
115         enum exynos_audss_clk_type variant;
116 
117         match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
118         if (!match)
119                 return -EINVAL;
120         variant = (enum exynos_audss_clk_type)match->data;
121 
122         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
123         reg_base = devm_ioremap_resource(&pdev->dev, res);
124         if (IS_ERR(reg_base)) {
125                 dev_err(&pdev->dev, "failed to map audss registers\n");
126                 return PTR_ERR(reg_base);
127         }
128         /* EPLL don't have to be enabled for boards other than Exynos5420 */
129         epll = ERR_PTR(-ENODEV);
130 
131         clk_table = devm_kzalloc(&pdev->dev,
132                                 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
133                                 GFP_KERNEL);
134         if (!clk_table)
135                 return -ENOMEM;
136 
137         clk_data.clks = clk_table;
138         if (variant == TYPE_EXYNOS5420)
139                 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
140         else
141                 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
142 
143         pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
144         pll_in = devm_clk_get(&pdev->dev, "pll_in");
145         if (!IS_ERR(pll_ref))
146                 mout_audss_p[0] = __clk_get_name(pll_ref);
147         if (!IS_ERR(pll_in)) {
148                 mout_audss_p[1] = __clk_get_name(pll_in);
149 
150                 if (variant == TYPE_EXYNOS5420) {
151                         epll = pll_in;
152 
153                         ret = clk_prepare_enable(epll);
154                         if (ret) {
155                                 dev_err(&pdev->dev,
156                                                 "failed to prepare the epll clock\n");
157                                 return ret;
158                         }
159                 }
160         }
161         clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
162                                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
163                                 CLK_SET_RATE_NO_REPARENT,
164                                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
165 
166         cdclk = devm_clk_get(&pdev->dev, "cdclk");
167         sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
168         if (!IS_ERR(cdclk))
169                 mout_i2s_p[1] = __clk_get_name(cdclk);
170         if (!IS_ERR(sclk_audio))
171                 mout_i2s_p[2] = __clk_get_name(sclk_audio);
172         clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
173                                 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
174                                 CLK_SET_RATE_NO_REPARENT,
175                                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
176 
177         clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
178                                 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
179                                 0, &lock);
180 
181         clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
182                                 "dout_aud_bus", "dout_srp", 0,
183                                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
184 
185         clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
186                                 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
187                                 &lock);
188 
189         clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
190                                 "dout_srp", CLK_SET_RATE_PARENT,
191                                 reg_base + ASS_CLK_GATE, 0, 0, &lock);
192 
193         clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
194                                 "dout_aud_bus", CLK_SET_RATE_PARENT,
195                                 reg_base + ASS_CLK_GATE, 2, 0, &lock);
196 
197         clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
198                                 "dout_i2s", CLK_SET_RATE_PARENT,
199                                 reg_base + ASS_CLK_GATE, 3, 0, &lock);
200 
201         clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
202                                  "sclk_pcm", CLK_SET_RATE_PARENT,
203                                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
204 
205         sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
206         if (!IS_ERR(sclk_pcm_in))
207                 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
208         clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
209                                 sclk_pcm_p, CLK_SET_RATE_PARENT,
210                                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
211 
212         if (variant == TYPE_EXYNOS5420) {
213                 clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
214                                 "dout_srp", CLK_SET_RATE_PARENT,
215                                 reg_base + ASS_CLK_GATE, 9, 0, &lock);
216         }
217 
218         for (i = 0; i < clk_data.clk_num; i++) {
219                 if (IS_ERR(clk_table[i])) {
220                         dev_err(&pdev->dev, "failed to register clock %d\n", i);
221                         ret = PTR_ERR(clk_table[i]);
222                         goto unregister;
223                 }
224         }
225 
226         ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
227                                         &clk_data);
228         if (ret) {
229                 dev_err(&pdev->dev, "failed to add clock provider\n");
230                 goto unregister;
231         }
232 
233 #ifdef CONFIG_PM_SLEEP
234         register_syscore_ops(&exynos_audss_clk_syscore_ops);
235 #endif
236 
237         dev_info(&pdev->dev, "setup completed\n");
238 
239         return 0;
240 
241 unregister:
242         exynos_audss_clk_teardown();
243 
244         if (!IS_ERR(epll))
245                 clk_disable_unprepare(epll);
246 
247         return ret;
248 }
249 
250 static int exynos_audss_clk_remove(struct platform_device *pdev)
251 {
252 #ifdef CONFIG_PM_SLEEP
253         unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
254 #endif
255 
256         of_clk_del_provider(pdev->dev.of_node);
257 
258         exynos_audss_clk_teardown();
259 
260         if (!IS_ERR(epll))
261                 clk_disable_unprepare(epll);
262 
263         return 0;
264 }
265 
266 static struct platform_driver exynos_audss_clk_driver = {
267         .driver = {
268                 .name = "exynos-audss-clk",
269                 .of_match_table = exynos_audss_clk_of_match,
270         },
271         .probe = exynos_audss_clk_probe,
272         .remove = exynos_audss_clk_remove,
273 };
274 
275 static int __init exynos_audss_clk_init(void)
276 {
277         return platform_driver_register(&exynos_audss_clk_driver);
278 }
279 core_initcall(exynos_audss_clk_init);
280 
281 static void __exit exynos_audss_clk_exit(void)
282 {
283         platform_driver_unregister(&exynos_audss_clk_driver);
284 }
285 module_exit(exynos_audss_clk_exit);
286 
287 MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
288 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
289 MODULE_LICENSE("GPL v2");
290 MODULE_ALIAS("platform:exynos-audss-clk");
291 

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