Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/char/agp/amd64-agp.c

  1 /*
  2  * Copyright 2001-2003 SuSE Labs.
  3  * Distributed under the GNU public license, v2.
  4  *
  5  * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
  6  * It also includes support for the AMD 8151 AGP bridge,
  7  * although it doesn't actually do much, as all the real
  8  * work is done in the northbridge(s).
  9  */
 10 
 11 #include <linux/module.h>
 12 #include <linux/pci.h>
 13 #include <linux/init.h>
 14 #include <linux/agp_backend.h>
 15 #include <linux/mmzone.h>
 16 #include <asm/page.h>           /* PAGE_SIZE */
 17 #include <asm/e820.h>
 18 #include <asm/amd_nb.h>
 19 #include <asm/gart.h>
 20 #include "agp.h"
 21 
 22 /* NVIDIA K8 registers */
 23 #define NVIDIA_X86_64_0_APBASE          0x10
 24 #define NVIDIA_X86_64_1_APBASE1         0x50
 25 #define NVIDIA_X86_64_1_APLIMIT1        0x54
 26 #define NVIDIA_X86_64_1_APSIZE          0xa8
 27 #define NVIDIA_X86_64_1_APBASE2         0xd8
 28 #define NVIDIA_X86_64_1_APLIMIT2        0xdc
 29 
 30 /* ULi K8 registers */
 31 #define ULI_X86_64_BASE_ADDR            0x10
 32 #define ULI_X86_64_HTT_FEA_REG          0x50
 33 #define ULI_X86_64_ENU_SCR_REG          0x54
 34 
 35 static struct resource *aperture_resource;
 36 static bool __initdata agp_try_unsupported = 1;
 37 static int agp_bridges_found;
 38 
 39 static void amd64_tlbflush(struct agp_memory *temp)
 40 {
 41         amd_flush_garts();
 42 }
 43 
 44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 45 {
 46         int i, j, num_entries;
 47         long long tmp;
 48         int mask_type;
 49         struct agp_bridge_data *bridge = mem->bridge;
 50         u32 pte;
 51 
 52         num_entries = agp_num_entries();
 53 
 54         if (type != mem->type)
 55                 return -EINVAL;
 56         mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
 57         if (mask_type != 0)
 58                 return -EINVAL;
 59 
 60 
 61         /* Make sure we can fit the range in the gatt table. */
 62         /* FIXME: could wrap */
 63         if (((unsigned long)pg_start + mem->page_count) > num_entries)
 64                 return -EINVAL;
 65 
 66         j = pg_start;
 67 
 68         /* gatt table should be empty. */
 69         while (j < (pg_start + mem->page_count)) {
 70                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
 71                         return -EBUSY;
 72                 j++;
 73         }
 74 
 75         if (!mem->is_flushed) {
 76                 global_cache_flush();
 77                 mem->is_flushed = true;
 78         }
 79 
 80         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 81                 tmp = agp_bridge->driver->mask_memory(agp_bridge,
 82                                                       page_to_phys(mem->pages[i]),
 83                                                       mask_type);
 84 
 85                 BUG_ON(tmp & 0xffffff0000000ffcULL);
 86                 pte = (tmp & 0x000000ff00000000ULL) >> 28;
 87                 pte |=(tmp & 0x00000000fffff000ULL);
 88                 pte |= GPTE_VALID | GPTE_COHERENT;
 89 
 90                 writel(pte, agp_bridge->gatt_table+j);
 91                 readl(agp_bridge->gatt_table+j);        /* PCI Posting. */
 92         }
 93         amd64_tlbflush(mem);
 94         return 0;
 95 }
 96 
 97 /*
 98  * This hack alters the order element according
 99  * to the size of a long. It sucks. I totally disown this, even
100  * though it does appear to work for the most part.
101  */
102 static struct aper_size_info_32 amd64_aperture_sizes[7] =
103 {
104         {32,   8192,   3+(sizeof(long)/8), 0 },
105         {64,   16384,  4+(sizeof(long)/8), 1<<1 },
106         {128,  32768,  5+(sizeof(long)/8), 1<<2 },
107         {256,  65536,  6+(sizeof(long)/8), 1<<1 | 1<<2 },
108         {512,  131072, 7+(sizeof(long)/8), 1<<3 },
109         {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
110         {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
111 };
112 
113 
114 /*
115  * Get the current Aperture size from the x86-64.
116  * Note, that there may be multiple x86-64's, but we just return
117  * the value from the first one we find. The set_size functions
118  * keep the rest coherent anyway. Or at least should do.
119  */
120 static int amd64_fetch_size(void)
121 {
122         struct pci_dev *dev;
123         int i;
124         u32 temp;
125         struct aper_size_info_32 *values;
126 
127         dev = node_to_amd_nb(0)->misc;
128         if (dev==NULL)
129                 return 0;
130 
131         pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
132         temp = (temp & 0xe);
133         values = A_SIZE_32(amd64_aperture_sizes);
134 
135         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
136                 if (temp == values[i].size_value) {
137                         agp_bridge->previous_size =
138                             agp_bridge->current_size = (void *) (values + i);
139 
140                         agp_bridge->aperture_size_idx = i;
141                         return values[i].size;
142                 }
143         }
144         return 0;
145 }
146 
147 /*
148  * In a multiprocessor x86-64 system, this function gets
149  * called once for each CPU.
150  */
151 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
152 {
153         u64 aperturebase;
154         u32 tmp;
155         u64 aper_base;
156 
157         /* Address to map to */
158         pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
159         aperturebase = tmp << 25;
160         aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
161 
162         enable_gart_translation(hammer, gatt_table);
163 
164         return aper_base;
165 }
166 
167 
168 static const struct aper_size_info_32 amd_8151_sizes[7] =
169 {
170         {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
171         {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
172         {512,  131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
173         {256,  65536,  6, 0x00000700 }, /* 1 1 1 0 0 0 */
174         {128,  32768,  5, 0x00000720 }, /* 1 1 1 1 0 0 */
175         {64,   16384,  4, 0x00000730 }, /* 1 1 1 1 1 0 */
176         {32,   8192,   3, 0x00000738 }  /* 1 1 1 1 1 1 */
177 };
178 
179 static int amd_8151_configure(void)
180 {
181         unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
182         int i;
183 
184         if (!amd_nb_has_feature(AMD_NB_GART))
185                 return 0;
186 
187         /* Configure AGP regs in each x86-64 host bridge. */
188         for (i = 0; i < amd_nb_num(); i++) {
189                 agp_bridge->gart_bus_addr =
190                         amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
191         }
192         amd_flush_garts();
193         return 0;
194 }
195 
196 
197 static void amd64_cleanup(void)
198 {
199         u32 tmp;
200         int i;
201 
202         if (!amd_nb_has_feature(AMD_NB_GART))
203                 return;
204 
205         for (i = 0; i < amd_nb_num(); i++) {
206                 struct pci_dev *dev = node_to_amd_nb(i)->misc;
207                 /* disable gart translation */
208                 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
209                 tmp &= ~GARTEN;
210                 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
211         }
212 }
213 
214 
215 static const struct agp_bridge_driver amd_8151_driver = {
216         .owner                  = THIS_MODULE,
217         .aperture_sizes         = amd_8151_sizes,
218         .size_type              = U32_APER_SIZE,
219         .num_aperture_sizes     = 7,
220         .needs_scratch_page     = true,
221         .configure              = amd_8151_configure,
222         .fetch_size             = amd64_fetch_size,
223         .cleanup                = amd64_cleanup,
224         .tlb_flush              = amd64_tlbflush,
225         .mask_memory            = agp_generic_mask_memory,
226         .masks                  = NULL,
227         .agp_enable             = agp_generic_enable,
228         .cache_flush            = global_cache_flush,
229         .create_gatt_table      = agp_generic_create_gatt_table,
230         .free_gatt_table        = agp_generic_free_gatt_table,
231         .insert_memory          = amd64_insert_memory,
232         .remove_memory          = agp_generic_remove_memory,
233         .alloc_by_type          = agp_generic_alloc_by_type,
234         .free_by_type           = agp_generic_free_by_type,
235         .agp_alloc_page         = agp_generic_alloc_page,
236         .agp_alloc_pages        = agp_generic_alloc_pages,
237         .agp_destroy_page       = agp_generic_destroy_page,
238         .agp_destroy_pages      = agp_generic_destroy_pages,
239         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
240 };
241 
242 /* Some basic sanity checks for the aperture. */
243 static int agp_aperture_valid(u64 aper, u32 size)
244 {
245         if (!aperture_valid(aper, size, 32*1024*1024))
246                 return 0;
247 
248         /* Request the Aperture. This catches cases when someone else
249            already put a mapping in there - happens with some very broken BIOS
250 
251            Maybe better to use pci_assign_resource/pci_enable_device instead
252            trusting the bridges? */
253         if (!aperture_resource &&
254             !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
255                 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
256                 return 0;
257         }
258         return 1;
259 }
260 
261 /*
262  * W*s centric BIOS sometimes only set up the aperture in the AGP
263  * bridge, not the northbridge. On AMD64 this is handled early
264  * in aperture.c, but when IOMMU is not enabled or we run
265  * on a 32bit kernel this needs to be redone.
266  * Unfortunately it is impossible to fix the aperture here because it's too late
267  * to allocate that much memory. But at least error out cleanly instead of
268  * crashing.
269  */
270 static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
271 {
272         u64 aper, nb_aper;
273         int order = 0;
274         u32 nb_order, nb_base;
275         u16 apsize;
276 
277         pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
278         nb_order = (nb_order >> 1) & 7;
279         pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
280         nb_aper = nb_base << 25;
281 
282         /* Northbridge seems to contain crap. Try the AGP bridge. */
283 
284         pci_read_config_word(agp, cap+0x14, &apsize);
285         if (apsize == 0xffff) {
286                 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
287                         return 0;
288                 return -1;
289         }
290 
291         apsize &= 0xfff;
292         /* Some BIOS use weird encodings not in the AGPv3 table. */
293         if (apsize & 0xff)
294                 apsize |= 0xf00;
295         order = 7 - hweight16(apsize);
296 
297         aper = pci_bus_address(agp, AGP_APERTURE_BAR);
298 
299         /*
300          * On some sick chips APSIZE is 0. This means it wants 4G
301          * so let double check that order, and lets trust the AMD NB settings
302          */
303         if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
304                 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
305                          32 << order);
306                 order = nb_order;
307         }
308 
309         if (nb_order >= order) {
310                 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
311                         return 0;
312         }
313 
314         dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
315                  aper, 32 << order);
316         if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
317                 return -1;
318 
319         gart_set_size_and_enable(nb, order);
320         pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
321 
322         return 0;
323 }
324 
325 static int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
326 {
327         int i;
328 
329         if (amd_cache_northbridges() < 0)
330                 return -ENODEV;
331 
332         if (!amd_nb_has_feature(AMD_NB_GART))
333                 return -ENODEV;
334 
335         i = 0;
336         for (i = 0; i < amd_nb_num(); i++) {
337                 struct pci_dev *dev = node_to_amd_nb(i)->misc;
338                 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
339                         dev_err(&dev->dev, "no usable aperture found\n");
340 #ifdef __x86_64__
341                         /* should port this to i386 */
342                         dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
343 #endif
344                         return -1;
345                 }
346         }
347         return 0;
348 }
349 
350 /* Handle AMD 8151 quirks */
351 static void amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
352 {
353         char *revstring;
354 
355         switch (pdev->revision) {
356         case 0x01: revstring="A0"; break;
357         case 0x02: revstring="A1"; break;
358         case 0x11: revstring="B0"; break;
359         case 0x12: revstring="B1"; break;
360         case 0x13: revstring="B2"; break;
361         case 0x14: revstring="B3"; break;
362         default:   revstring="??"; break;
363         }
364 
365         dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
366 
367         /*
368          * Work around errata.
369          * Chips before B2 stepping incorrectly reporting v3.5
370          */
371         if (pdev->revision < 0x13) {
372                 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
373                 bridge->major_version = 3;
374                 bridge->minor_version = 0;
375         }
376 }
377 
378 
379 static const struct aper_size_info_32 uli_sizes[7] =
380 {
381         {256, 65536, 6, 10},
382         {128, 32768, 5, 9},
383         {64, 16384, 4, 8},
384         {32, 8192, 3, 7},
385         {16, 4096, 2, 6},
386         {8, 2048, 1, 4},
387         {4, 1024, 0, 3}
388 };
389 static int uli_agp_init(struct pci_dev *pdev)
390 {
391         u32 httfea,baseaddr,enuscr;
392         struct pci_dev *dev1;
393         int i, ret;
394         unsigned size = amd64_fetch_size();
395 
396         dev_info(&pdev->dev, "setting up ULi AGP\n");
397         dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
398         if (dev1 == NULL) {
399                 dev_info(&pdev->dev, "can't find ULi secondary device\n");
400                 return -ENODEV;
401         }
402 
403         for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
404                 if (uli_sizes[i].size == size)
405                         break;
406 
407         if (i == ARRAY_SIZE(uli_sizes)) {
408                 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
409                 ret = -ENODEV;
410                 goto put;
411         }
412 
413         /* shadow x86-64 registers into ULi registers */
414         pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
415                                &httfea);
416 
417         /* if x86-64 aperture base is beyond 4G, exit here */
418         if ((httfea & 0x7fff) >> (32 - 25)) {
419                 ret = -ENODEV;
420                 goto put;
421         }
422 
423         httfea = (httfea& 0x7fff) << 25;
424 
425         pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
426         baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
427         baseaddr|= httfea;
428         pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
429 
430         enuscr= httfea+ (size * 1024 * 1024) - 1;
431         pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
432         pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
433         ret = 0;
434 put:
435         pci_dev_put(dev1);
436         return ret;
437 }
438 
439 
440 static const struct aper_size_info_32 nforce3_sizes[5] =
441 {
442         {512,  131072, 7, 0x00000000 },
443         {256,  65536,  6, 0x00000008 },
444         {128,  32768,  5, 0x0000000C },
445         {64,   16384,  4, 0x0000000E },
446         {32,   8192,   3, 0x0000000F }
447 };
448 
449 /* Handle shadow device of the Nvidia NForce3 */
450 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
451 static int nforce3_agp_init(struct pci_dev *pdev)
452 {
453         u32 tmp, apbase, apbar, aplimit;
454         struct pci_dev *dev1;
455         int i, ret;
456         unsigned size = amd64_fetch_size();
457 
458         dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
459 
460         dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
461         if (dev1 == NULL) {
462                 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
463                 return -ENODEV;
464         }
465 
466         for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
467                 if (nforce3_sizes[i].size == size)
468                         break;
469 
470         if (i == ARRAY_SIZE(nforce3_sizes)) {
471                 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
472                 ret = -ENODEV;
473                 goto put;
474         }
475 
476         pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
477         tmp &= ~(0xf);
478         tmp |= nforce3_sizes[i].size_value;
479         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
480 
481         /* shadow x86-64 registers into NVIDIA registers */
482         pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
483                                &apbase);
484 
485         /* if x86-64 aperture base is beyond 4G, exit here */
486         if ( (apbase & 0x7fff) >> (32 - 25) ) {
487                 dev_info(&pdev->dev, "aperture base > 4G\n");
488                 ret = -ENODEV;
489                 goto put;
490         }
491 
492         apbase = (apbase & 0x7fff) << 25;
493 
494         pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
495         apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
496         apbar |= apbase;
497         pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
498 
499         aplimit = apbase + (size * 1024 * 1024) - 1;
500         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
501         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
502         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
503         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
504 
505         ret = 0;
506 put:
507         pci_dev_put(dev1);
508 
509         return ret;
510 }
511 
512 static int agp_amd64_probe(struct pci_dev *pdev,
513                            const struct pci_device_id *ent)
514 {
515         struct agp_bridge_data *bridge;
516         u8 cap_ptr;
517         int err;
518 
519         /* The Highlander principle */
520         if (agp_bridges_found)
521                 return -ENODEV;
522 
523         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
524         if (!cap_ptr)
525                 return -ENODEV;
526 
527         /* Could check for AGPv3 here */
528 
529         bridge = agp_alloc_bridge();
530         if (!bridge)
531                 return -ENOMEM;
532 
533         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
534             pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
535                 amd8151_init(pdev, bridge);
536         } else {
537                 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
538                          pdev->vendor, pdev->device);
539         }
540 
541         bridge->driver = &amd_8151_driver;
542         bridge->dev = pdev;
543         bridge->capndx = cap_ptr;
544 
545         /* Fill in the mode register */
546         pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
547 
548         if (cache_nbs(pdev, cap_ptr) == -1) {
549                 agp_put_bridge(bridge);
550                 return -ENODEV;
551         }
552 
553         if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
554                 int ret = nforce3_agp_init(pdev);
555                 if (ret) {
556                         agp_put_bridge(bridge);
557                         return ret;
558                 }
559         }
560 
561         if (pdev->vendor == PCI_VENDOR_ID_AL) {
562                 int ret = uli_agp_init(pdev);
563                 if (ret) {
564                         agp_put_bridge(bridge);
565                         return ret;
566                 }
567         }
568 
569         pci_set_drvdata(pdev, bridge);
570         err = agp_add_bridge(bridge);
571         if (err < 0)
572                 return err;
573 
574         agp_bridges_found++;
575         return 0;
576 }
577 
578 static void agp_amd64_remove(struct pci_dev *pdev)
579 {
580         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
581 
582         release_mem_region(virt_to_phys(bridge->gatt_table_real),
583                            amd64_aperture_sizes[bridge->aperture_size_idx].size);
584         agp_remove_bridge(bridge);
585         agp_put_bridge(bridge);
586 
587         agp_bridges_found--;
588 }
589 
590 #ifdef CONFIG_PM
591 
592 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
593 {
594         pci_save_state(pdev);
595         pci_set_power_state(pdev, pci_choose_state(pdev, state));
596 
597         return 0;
598 }
599 
600 static int agp_amd64_resume(struct pci_dev *pdev)
601 {
602         pci_set_power_state(pdev, PCI_D0);
603         pci_restore_state(pdev);
604 
605         if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
606                 nforce3_agp_init(pdev);
607 
608         return amd_8151_configure();
609 }
610 
611 #endif /* CONFIG_PM */
612 
613 static struct pci_device_id agp_amd64_pci_table[] = {
614         {
615         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
616         .class_mask     = ~0,
617         .vendor         = PCI_VENDOR_ID_AMD,
618         .device         = PCI_DEVICE_ID_AMD_8151_0,
619         .subvendor      = PCI_ANY_ID,
620         .subdevice      = PCI_ANY_ID,
621         },
622         /* ULi M1689 */
623         {
624         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
625         .class_mask     = ~0,
626         .vendor         = PCI_VENDOR_ID_AL,
627         .device         = PCI_DEVICE_ID_AL_M1689,
628         .subvendor      = PCI_ANY_ID,
629         .subdevice      = PCI_ANY_ID,
630         },
631         /* VIA K8T800Pro */
632         {
633         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
634         .class_mask     = ~0,
635         .vendor         = PCI_VENDOR_ID_VIA,
636         .device         = PCI_DEVICE_ID_VIA_K8T800PRO_0,
637         .subvendor      = PCI_ANY_ID,
638         .subdevice      = PCI_ANY_ID,
639         },
640         /* VIA K8T800 */
641         {
642         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
643         .class_mask     = ~0,
644         .vendor         = PCI_VENDOR_ID_VIA,
645         .device         = PCI_DEVICE_ID_VIA_8385_0,
646         .subvendor      = PCI_ANY_ID,
647         .subdevice      = PCI_ANY_ID,
648         },
649         /* VIA K8M800 / K8N800 */
650         {
651         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
652         .class_mask     = ~0,
653         .vendor         = PCI_VENDOR_ID_VIA,
654         .device         = PCI_DEVICE_ID_VIA_8380_0,
655         .subvendor      = PCI_ANY_ID,
656         .subdevice      = PCI_ANY_ID,
657         },
658         /* VIA K8M890 / K8N890 */
659         {
660         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
661         .class_mask     = ~0,
662         .vendor         = PCI_VENDOR_ID_VIA,
663         .device         = PCI_DEVICE_ID_VIA_VT3336,
664         .subvendor      = PCI_ANY_ID,
665         .subdevice      = PCI_ANY_ID,
666         },
667         /* VIA K8T890 */
668         {
669         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
670         .class_mask     = ~0,
671         .vendor         = PCI_VENDOR_ID_VIA,
672         .device         = PCI_DEVICE_ID_VIA_3238_0,
673         .subvendor      = PCI_ANY_ID,
674         .subdevice      = PCI_ANY_ID,
675         },
676         /* VIA K8T800/K8M800/K8N800 */
677         {
678         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
679         .class_mask     = ~0,
680         .vendor         = PCI_VENDOR_ID_VIA,
681         .device         = PCI_DEVICE_ID_VIA_838X_1,
682         .subvendor      = PCI_ANY_ID,
683         .subdevice      = PCI_ANY_ID,
684         },
685         /* NForce3 */
686         {
687         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
688         .class_mask     = ~0,
689         .vendor         = PCI_VENDOR_ID_NVIDIA,
690         .device         = PCI_DEVICE_ID_NVIDIA_NFORCE3,
691         .subvendor      = PCI_ANY_ID,
692         .subdevice      = PCI_ANY_ID,
693         },
694         {
695         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
696         .class_mask     = ~0,
697         .vendor         = PCI_VENDOR_ID_NVIDIA,
698         .device         = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
699         .subvendor      = PCI_ANY_ID,
700         .subdevice      = PCI_ANY_ID,
701         },
702         /* SIS 755 */
703         {
704         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
705         .class_mask     = ~0,
706         .vendor         = PCI_VENDOR_ID_SI,
707         .device         = PCI_DEVICE_ID_SI_755,
708         .subvendor      = PCI_ANY_ID,
709         .subdevice      = PCI_ANY_ID,
710         },
711         /* SIS 760 */
712         {
713         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
714         .class_mask     = ~0,
715         .vendor         = PCI_VENDOR_ID_SI,
716         .device         = PCI_DEVICE_ID_SI_760,
717         .subvendor      = PCI_ANY_ID,
718         .subdevice      = PCI_ANY_ID,
719         },
720         /* ALI/ULI M1695 */
721         {
722         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
723         .class_mask     = ~0,
724         .vendor         = PCI_VENDOR_ID_AL,
725         .device         = 0x1695,
726         .subvendor      = PCI_ANY_ID,
727         .subdevice      = PCI_ANY_ID,
728         },
729 
730         { }
731 };
732 
733 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
734 
735 static const struct pci_device_id agp_amd64_pci_promisc_table[] = {
736         { PCI_DEVICE_CLASS(0, 0) },
737         { }
738 };
739 
740 static struct pci_driver agp_amd64_pci_driver = {
741         .name           = "agpgart-amd64",
742         .id_table       = agp_amd64_pci_table,
743         .probe          = agp_amd64_probe,
744         .remove         = agp_amd64_remove,
745 #ifdef CONFIG_PM
746         .suspend        = agp_amd64_suspend,
747         .resume         = agp_amd64_resume,
748 #endif
749 };
750 
751 
752 /* Not static due to IOMMU code calling it early. */
753 int __init agp_amd64_init(void)
754 {
755         int err = 0;
756 
757         if (agp_off)
758                 return -EINVAL;
759 
760         err = pci_register_driver(&agp_amd64_pci_driver);
761         if (err < 0)
762                 return err;
763 
764         if (agp_bridges_found == 0) {
765                 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
766                         printk(KERN_INFO PFX "No supported AGP bridge found.\n");
767 #ifdef MODULE
768                         printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
769 #else
770                         printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
771 #endif
772                         pci_unregister_driver(&agp_amd64_pci_driver);
773                         return -ENODEV;
774                 }
775 
776                 /* First check that we have at least one AMD64 NB */
777                 if (!pci_dev_present(amd_nb_misc_ids)) {
778                         pci_unregister_driver(&agp_amd64_pci_driver);
779                         return -ENODEV;
780                 }
781 
782                 /* Look for any AGP bridge */
783                 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
784                 err = driver_attach(&agp_amd64_pci_driver.driver);
785                 if (err == 0 && agp_bridges_found == 0) {
786                         pci_unregister_driver(&agp_amd64_pci_driver);
787                         err = -ENODEV;
788                 }
789         }
790         return err;
791 }
792 
793 static int __init agp_amd64_mod_init(void)
794 {
795 #ifndef MODULE
796         if (gart_iommu_aperture)
797                 return agp_bridges_found ? 0 : -ENODEV;
798 #endif
799         return agp_amd64_init();
800 }
801 
802 static void __exit agp_amd64_cleanup(void)
803 {
804 #ifndef MODULE
805         if (gart_iommu_aperture)
806                 return;
807 #endif
808         if (aperture_resource)
809                 release_resource(aperture_resource);
810         pci_unregister_driver(&agp_amd64_pci_driver);
811 }
812 
813 module_init(agp_amd64_mod_init);
814 module_exit(agp_amd64_cleanup);
815 
816 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
817 module_param(agp_try_unsupported, bool, 0);
818 MODULE_LICENSE("GPL");
819 

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